uhci.c revision 1.240.6.8
1 /* $NetBSD: uhci.c,v 1.240.6.8 2012/02/20 03:23:26 mrg Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2011 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 11 * and Matthew R. Green. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Universal Host Controller driver. 37 * Handles e.g. PIIX3 and PIIX4. 38 * 39 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 40 * USB spec: http://www.usb.org/developers/docs/ 41 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 42 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.240.6.8 2012/02/20 03:23:26 mrg Exp $"); 47 48 #include "opt_usb.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/device.h> 55 #include <sys/select.h> 56 #include <sys/extent.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/bus.h> 60 61 #include <machine/endian.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usb_mem.h> 67 #include <dev/usb/usb_quirks.h> 68 69 #include <dev/usb/uhcireg.h> 70 #include <dev/usb/uhcivar.h> 71 #include <dev/usb/usbroothub_subr.h> 72 73 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 74 /*#define UHCI_CTL_LOOP */ 75 76 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 #define DPRINTF(x) if (uhcidebug) printf x 81 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 82 int uhcidebug = 0; 83 int uhcinoloop = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n,x) 87 #endif 88 89 /* 90 * The UHCI controller is little endian, so on big endian machines 91 * the data stored in memory needs to be swapped. 92 */ 93 94 struct uhci_pipe { 95 struct usbd_pipe pipe; 96 int nexttoggle; 97 98 u_char aborting; 99 usbd_xfer_handle abortstart, abortend; 100 101 /* Info needed for different pipe kinds. */ 102 union { 103 /* Control pipe */ 104 struct { 105 uhci_soft_qh_t *sqh; 106 usb_dma_t reqdma; 107 uhci_soft_td_t *setup, *stat; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 int npoll; 113 int isread; 114 uhci_soft_qh_t **qhs; 115 } intr; 116 /* Bulk pipe */ 117 struct { 118 uhci_soft_qh_t *sqh; 119 u_int length; 120 int isread; 121 } bulk; 122 /* Iso pipe */ 123 struct iso { 124 uhci_soft_td_t **stds; 125 int next, inuse; 126 } iso; 127 } u; 128 }; 129 130 Static void uhci_globalreset(uhci_softc_t *); 131 Static usbd_status uhci_portreset(uhci_softc_t*, int); 132 Static void uhci_reset(uhci_softc_t *); 133 Static usbd_status uhci_run(uhci_softc_t *, int run); 134 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 135 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 136 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 137 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 138 #if 0 139 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 140 uhci_intr_info_t *); 141 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 142 #endif 143 144 Static void uhci_free_std_chain(uhci_softc_t *, 145 uhci_soft_td_t *, uhci_soft_td_t *); 146 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 147 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 148 uhci_soft_td_t **, uhci_soft_td_t **); 149 Static void uhci_poll_hub(void *); 150 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 151 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 152 Static void uhci_idone(uhci_intr_info_t *); 153 154 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 155 156 Static void uhci_timeout(void *); 157 Static void uhci_timeout_task(void *); 158 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 160 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 161 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 163 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 164 Static void uhci_add_loop(uhci_softc_t *sc); 165 Static void uhci_rem_loop(uhci_softc_t *sc); 166 167 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 168 Static void uhci_device_isoc_enter(usbd_xfer_handle); 169 170 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 171 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 172 173 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 174 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void uhci_get_locks(struct usbd_bus *, kmutex_t **, 176 kmutex_t **); 177 178 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 179 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 180 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 181 Static void uhci_device_ctrl_close(usbd_pipe_handle); 182 Static void uhci_device_ctrl_done(usbd_xfer_handle); 183 184 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 185 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 186 Static void uhci_device_intr_abort(usbd_xfer_handle); 187 Static void uhci_device_intr_close(usbd_pipe_handle); 188 Static void uhci_device_intr_done(usbd_xfer_handle); 189 190 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 191 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 192 Static void uhci_device_bulk_abort(usbd_xfer_handle); 193 Static void uhci_device_bulk_close(usbd_pipe_handle); 194 Static void uhci_device_bulk_done(usbd_xfer_handle); 195 196 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 197 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 198 Static void uhci_device_isoc_abort(usbd_xfer_handle); 199 Static void uhci_device_isoc_close(usbd_pipe_handle); 200 Static void uhci_device_isoc_done(usbd_xfer_handle); 201 202 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 203 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 204 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 205 Static void uhci_root_ctrl_close(usbd_pipe_handle); 206 Static void uhci_root_ctrl_done(usbd_xfer_handle); 207 208 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 209 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 210 Static void uhci_root_intr_abort(usbd_xfer_handle); 211 Static void uhci_root_intr_close(usbd_pipe_handle); 212 Static void uhci_root_intr_done(usbd_xfer_handle); 213 214 Static usbd_status uhci_open(usbd_pipe_handle); 215 Static void uhci_poll(struct usbd_bus *); 216 Static void uhci_softintr(void *); 217 218 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 219 220 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 221 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 222 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 223 struct uhci_pipe *pipe, int ival); 224 225 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 226 Static void uhci_noop(usbd_pipe_handle pipe); 227 228 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 229 uhci_soft_qh_t *); 230 231 #ifdef UHCI_DEBUG 232 Static void uhci_dump_all(uhci_softc_t *); 233 Static void uhci_dumpregs(uhci_softc_t *); 234 Static void uhci_dump_qhs(uhci_soft_qh_t *); 235 Static void uhci_dump_qh(uhci_soft_qh_t *); 236 Static void uhci_dump_tds(uhci_soft_td_t *); 237 Static void uhci_dump_td(uhci_soft_td_t *); 238 Static void uhci_dump_ii(uhci_intr_info_t *ii); 239 void uhci_dump(void); 240 #endif 241 242 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 243 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 244 #define UWRITE1(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE2(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 #define UWRITE4(sc, r, x) \ 251 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 252 } while (/*CONSTCOND*/0) 253 static __inline uint8_t 254 UREAD1(uhci_softc_t *sc, bus_size_t r) 255 { 256 257 UBARR(sc); 258 return bus_space_read_1(sc->iot, sc->ioh, r); 259 } 260 261 static __inline uint16_t 262 UREAD2(uhci_softc_t *sc, bus_size_t r) 263 { 264 265 UBARR(sc); 266 return bus_space_read_2(sc->iot, sc->ioh, r); 267 } 268 269 static __inline uint32_t 270 UREAD4(uhci_softc_t *sc, bus_size_t r) 271 { 272 273 UBARR(sc); 274 return bus_space_read_4(sc->iot, sc->ioh, r); 275 } 276 277 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 278 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 279 280 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 281 282 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 283 284 #define UHCI_INTR_ENDPT 1 285 286 const struct usbd_bus_methods uhci_bus_methods = { 287 .open_pipe = uhci_open, 288 .soft_intr = uhci_softintr, 289 .do_poll = uhci_poll, 290 .allocm = uhci_allocm, 291 .freem = uhci_freem, 292 .allocx = uhci_allocx, 293 .freex = uhci_freex, 294 .get_locks = uhci_get_locks, 295 }; 296 297 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 298 .transfer = uhci_root_ctrl_transfer, 299 .start = uhci_root_ctrl_start, 300 .abort = uhci_root_ctrl_abort, 301 .close = uhci_root_ctrl_close, 302 .cleartoggle = uhci_noop, 303 .done = uhci_root_ctrl_done, 304 }; 305 306 const struct usbd_pipe_methods uhci_root_intr_methods = { 307 .transfer = uhci_root_intr_transfer, 308 .start = uhci_root_intr_start, 309 .abort = uhci_root_intr_abort, 310 .close = uhci_root_intr_close, 311 .cleartoggle = uhci_noop, 312 .done = uhci_root_intr_done, 313 }; 314 315 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 316 .transfer = uhci_device_ctrl_transfer, 317 .start = uhci_device_ctrl_start, 318 .abort = uhci_device_ctrl_abort, 319 .close = uhci_device_ctrl_close, 320 .cleartoggle = uhci_noop, 321 .done = uhci_device_ctrl_done, 322 }; 323 324 const struct usbd_pipe_methods uhci_device_intr_methods = { 325 .transfer = uhci_device_intr_transfer, 326 .start = uhci_device_intr_start, 327 .abort = uhci_device_intr_abort, 328 .close = uhci_device_intr_close, 329 .cleartoggle = uhci_device_clear_toggle, 330 .done = uhci_device_intr_done, 331 }; 332 333 const struct usbd_pipe_methods uhci_device_bulk_methods = { 334 .transfer = uhci_device_bulk_transfer, 335 .start = uhci_device_bulk_start, 336 .abort = uhci_device_bulk_abort, 337 .close = uhci_device_bulk_close, 338 .cleartoggle = uhci_device_clear_toggle, 339 .done = uhci_device_bulk_done, 340 }; 341 342 const struct usbd_pipe_methods uhci_device_isoc_methods = { 343 .transfer = uhci_device_isoc_transfer, 344 .start = uhci_device_isoc_start, 345 .abort = uhci_device_isoc_abort, 346 .close = uhci_device_isoc_close, 347 .cleartoggle = uhci_noop, 348 .done = uhci_device_isoc_done, 349 }; 350 351 #define uhci_add_intr_info(sc, ii) \ 352 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 353 #define uhci_del_intr_info(ii) \ 354 do { \ 355 LIST_REMOVE((ii), list); \ 356 (ii)->list.le_prev = NULL; \ 357 } while (0) 358 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 359 360 static inline uhci_soft_qh_t * 361 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 362 { 363 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 364 365 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 366 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 367 usb_syncmem(&pqh->dma, 368 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 369 sizeof(pqh->qh.qh_hlink), 370 BUS_DMASYNC_POSTWRITE); 371 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 372 printf("uhci_find_prev_qh: QH not found\n"); 373 return (NULL); 374 } 375 #endif 376 } 377 return (pqh); 378 } 379 380 void 381 uhci_globalreset(uhci_softc_t *sc) 382 { 383 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 384 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 385 UHCICMD(sc, 0); /* do nothing */ 386 } 387 388 usbd_status 389 uhci_init(uhci_softc_t *sc) 390 { 391 usbd_status err; 392 int i, j; 393 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 394 uhci_soft_td_t *std; 395 396 DPRINTFN(1,("uhci_init: start\n")); 397 398 #ifdef UHCI_DEBUG 399 thesc = sc; 400 401 if (uhcidebug > 2) 402 uhci_dumpregs(sc); 403 #endif 404 405 sc->sc_suspend = PWR_RESUME; 406 407 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 408 uhci_globalreset(sc); /* reset the controller */ 409 uhci_reset(sc); 410 411 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 412 USB_MEM_RESERVE); 413 414 /* Allocate and initialize real frame array. */ 415 err = usb_allocmem(&sc->sc_bus, 416 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 417 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 418 if (err) 419 return (err); 420 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 421 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 422 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 423 424 /* 425 * Allocate a TD, inactive, that hangs from the last QH. 426 * This is to avoid a bug in the PIIX that makes it run berserk 427 * otherwise. 428 */ 429 std = uhci_alloc_std(sc); 430 if (std == NULL) 431 return (USBD_NOMEM); 432 std->link.std = NULL; 433 std->td.td_link = htole32(UHCI_PTR_T); 434 std->td.td_status = htole32(0); /* inactive */ 435 std->td.td_token = htole32(0); 436 std->td.td_buffer = htole32(0); 437 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 438 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 439 440 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 441 lsqh = uhci_alloc_sqh(sc); 442 if (lsqh == NULL) 443 return (USBD_NOMEM); 444 lsqh->hlink = NULL; 445 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 446 lsqh->elink = std; 447 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 448 sc->sc_last_qh = lsqh; 449 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 451 452 /* Allocate the dummy QH where bulk traffic will be queued. */ 453 bsqh = uhci_alloc_sqh(sc); 454 if (bsqh == NULL) 455 return (USBD_NOMEM); 456 bsqh->hlink = lsqh; 457 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 458 bsqh->elink = NULL; 459 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 460 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 461 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 463 464 /* Allocate dummy QH where high speed control traffic will be queued. */ 465 chsqh = uhci_alloc_sqh(sc); 466 if (chsqh == NULL) 467 return (USBD_NOMEM); 468 chsqh->hlink = bsqh; 469 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 470 chsqh->elink = NULL; 471 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 472 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 473 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 475 476 /* Allocate dummy QH where control traffic will be queued. */ 477 clsqh = uhci_alloc_sqh(sc); 478 if (clsqh == NULL) 479 return (USBD_NOMEM); 480 clsqh->hlink = chsqh; 481 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 482 clsqh->elink = NULL; 483 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 484 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 485 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 487 488 /* 489 * Make all (virtual) frame list pointers point to the interrupt 490 * queue heads and the interrupt queue heads at the control 491 * queue head and point the physical frame list to the virtual. 492 */ 493 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 494 std = uhci_alloc_std(sc); 495 sqh = uhci_alloc_sqh(sc); 496 if (std == NULL || sqh == NULL) 497 return (USBD_NOMEM); 498 std->link.sqh = sqh; 499 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 500 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 501 std->td.td_token = htole32(0); 502 std->td.td_buffer = htole32(0); 503 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 504 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 505 sqh->hlink = clsqh; 506 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 507 sqh->elink = NULL; 508 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 509 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 511 sc->sc_vframes[i].htd = std; 512 sc->sc_vframes[i].etd = std; 513 sc->sc_vframes[i].hqh = sqh; 514 sc->sc_vframes[i].eqh = sqh; 515 for (j = i; 516 j < UHCI_FRAMELIST_COUNT; 517 j += UHCI_VFRAMELIST_COUNT) 518 sc->sc_pframes[j] = htole32(std->physaddr); 519 } 520 usb_syncmem(&sc->sc_dma, 0, 521 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 522 BUS_DMASYNC_PREWRITE); 523 524 525 LIST_INIT(&sc->sc_intrhead); 526 527 SIMPLEQ_INIT(&sc->sc_free_xfers); 528 529 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 530 531 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 532 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 533 cv_init(&sc->sc_softwake_cv, "uhciab"); 534 535 /* Set up the bus struct. */ 536 sc->sc_bus.methods = &uhci_bus_methods; 537 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 538 539 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 540 541 DPRINTFN(1,("uhci_init: enabling\n")); 542 543 err = uhci_run(sc, 1); /* and here we go... */ 544 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 545 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 546 return err; 547 } 548 549 int 550 uhci_activate(device_t self, enum devact act) 551 { 552 struct uhci_softc *sc = device_private(self); 553 554 switch (act) { 555 case DVACT_DEACTIVATE: 556 sc->sc_dying = 1; 557 return 0; 558 default: 559 return EOPNOTSUPP; 560 } 561 } 562 563 void 564 uhci_childdet(device_t self, device_t child) 565 { 566 struct uhci_softc *sc = device_private(self); 567 568 KASSERT(sc->sc_child == child); 569 sc->sc_child = NULL; 570 } 571 572 int 573 uhci_detach(struct uhci_softc *sc, int flags) 574 { 575 usbd_xfer_handle xfer; 576 int rv = 0; 577 578 if (sc->sc_child != NULL) 579 rv = config_detach(sc->sc_child, flags); 580 581 if (rv != 0) 582 return (rv); 583 584 /* Free all xfers associated with this HC. */ 585 for (;;) { 586 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 587 if (xfer == NULL) 588 break; 589 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 590 kmem_free(xfer, sizeof(struct uhci_xfer)); 591 } 592 593 callout_halt(&sc->sc_poll_handle, NULL); 594 callout_destroy(&sc->sc_poll_handle); 595 596 cv_destroy(&sc->sc_softwake_cv); 597 598 mutex_destroy(&sc->sc_lock); 599 mutex_destroy(&sc->sc_intr_lock); 600 601 /* XXX free other data structures XXX */ 602 603 return (rv); 604 } 605 606 usbd_status 607 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 608 { 609 struct uhci_softc *sc = bus->hci_private; 610 usbd_status status; 611 u_int32_t n; 612 613 /* 614 * XXX 615 * Since we are allocating a buffer we can assume that we will 616 * need TDs for it. Since we don't want to allocate those from 617 * an interrupt context, we allocate them here and free them again. 618 * This is no guarantee that we'll get the TDs next time... 619 */ 620 n = size / 8; 621 if (n > 16) { 622 u_int32_t i; 623 uhci_soft_td_t **stds; 624 625 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 626 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 627 if (!stds) 628 return USBD_NOMEM; 629 for(i = 0; i < n; i++) 630 stds[i] = uhci_alloc_std(sc); 631 for(i = 0; i < n; i++) 632 if (stds[i] != NULL) 633 uhci_free_std(sc, stds[i]); 634 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 635 } 636 637 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 638 if (status == USBD_NOMEM) 639 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 640 return status; 641 } 642 643 void 644 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 645 { 646 if (dma->block->flags & USB_DMA_RESERVE) { 647 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 648 dma); 649 return; 650 } 651 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 652 } 653 654 usbd_xfer_handle 655 uhci_allocx(struct usbd_bus *bus) 656 { 657 struct uhci_softc *sc = bus->hci_private; 658 usbd_xfer_handle xfer; 659 660 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 661 if (xfer != NULL) { 662 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 663 #ifdef DIAGNOSTIC 664 if (xfer->busy_free != XFER_FREE) { 665 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 666 xfer->busy_free); 667 } 668 #endif 669 } else { 670 xfer = kmem_alloc(sizeof(struct uhci_xfer), KM_SLEEP); 671 } 672 if (xfer != NULL) { 673 memset(xfer, 0, sizeof (struct uhci_xfer)); 674 UXFER(xfer)->iinfo.sc = sc; 675 #ifdef DIAGNOSTIC 676 UXFER(xfer)->iinfo.isdone = 1; 677 xfer->busy_free = XFER_BUSY; 678 #endif 679 } 680 return (xfer); 681 } 682 683 void 684 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 685 { 686 struct uhci_softc *sc = bus->hci_private; 687 688 #ifdef DIAGNOSTIC 689 if (xfer->busy_free != XFER_BUSY) { 690 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 691 xfer->busy_free); 692 } 693 xfer->busy_free = XFER_FREE; 694 if (!UXFER(xfer)->iinfo.isdone) { 695 printf("uhci_freex: !isdone\n"); 696 } 697 #endif 698 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 699 } 700 701 Static void 702 uhci_get_locks(struct usbd_bus *bus, kmutex_t **intr, kmutex_t **thread) 703 { 704 struct uhci_softc *sc = bus->hci_private; 705 706 *intr = &sc->sc_intr_lock; 707 *thread = &sc->sc_lock; 708 } 709 710 711 /* 712 * Handle suspend/resume. 713 * 714 * We need to switch to polling mode here, because this routine is 715 * called from an interrupt context. This is all right since we 716 * are almost suspended anyway. 717 */ 718 bool 719 uhci_resume(device_t dv, const pmf_qual_t *qual) 720 { 721 uhci_softc_t *sc = device_private(dv); 722 int cmd; 723 724 mutex_spin_enter(&sc->sc_intr_lock); 725 726 cmd = UREAD2(sc, UHCI_CMD); 727 sc->sc_bus.use_polling++; 728 UWRITE2(sc, UHCI_INTR, 0); 729 uhci_globalreset(sc); 730 uhci_reset(sc); 731 if (cmd & UHCI_CMD_RS) 732 uhci_run(sc, 0); 733 734 /* restore saved state */ 735 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 736 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 737 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 738 739 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 740 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 741 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 742 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 743 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 744 UHCICMD(sc, UHCI_CMD_MAXP); 745 uhci_run(sc, 1); /* and start traffic again */ 746 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 747 sc->sc_bus.use_polling--; 748 if (sc->sc_intr_xfer != NULL) 749 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 750 sc->sc_intr_xfer); 751 #ifdef UHCI_DEBUG 752 if (uhcidebug > 2) 753 uhci_dumpregs(sc); 754 #endif 755 756 sc->sc_suspend = PWR_RESUME; 757 mutex_spin_exit(&sc->sc_intr_lock); 758 759 return true; 760 } 761 762 bool 763 uhci_suspend(device_t dv, const pmf_qual_t *qual) 764 { 765 uhci_softc_t *sc = device_private(dv); 766 int cmd; 767 768 mutex_spin_enter(&sc->sc_intr_lock); 769 770 cmd = UREAD2(sc, UHCI_CMD); 771 772 #ifdef UHCI_DEBUG 773 if (uhcidebug > 2) 774 uhci_dumpregs(sc); 775 #endif 776 if (sc->sc_intr_xfer != NULL) 777 callout_stop(&sc->sc_poll_handle); 778 sc->sc_suspend = PWR_SUSPEND; 779 sc->sc_bus.use_polling++; 780 781 uhci_run(sc, 0); /* stop the controller */ 782 cmd &= ~UHCI_CMD_RS; 783 784 /* save some state if BIOS doesn't */ 785 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 786 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 787 788 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 789 790 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 791 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 792 sc->sc_bus.use_polling--; 793 794 mutex_spin_exit(&sc->sc_intr_lock); 795 796 return true; 797 } 798 799 #ifdef UHCI_DEBUG 800 Static void 801 uhci_dumpregs(uhci_softc_t *sc) 802 { 803 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 804 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 805 device_xname(sc->sc_dev), 806 UREAD2(sc, UHCI_CMD), 807 UREAD2(sc, UHCI_STS), 808 UREAD2(sc, UHCI_INTR), 809 UREAD2(sc, UHCI_FRNUM), 810 UREAD4(sc, UHCI_FLBASEADDR), 811 UREAD1(sc, UHCI_SOF), 812 UREAD2(sc, UHCI_PORTSC1), 813 UREAD2(sc, UHCI_PORTSC2))); 814 } 815 816 void 817 uhci_dump_td(uhci_soft_td_t *p) 818 { 819 char sbuf[128], sbuf2[128]; 820 821 822 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 823 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 824 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 825 "token=0x%08lx buffer=0x%08lx\n", 826 p, (long)p->physaddr, 827 (long)le32toh(p->td.td_link), 828 (long)le32toh(p->td.td_status), 829 (long)le32toh(p->td.td_token), 830 (long)le32toh(p->td.td_buffer))); 831 832 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 833 (u_int32_t)le32toh(p->td.td_link)); 834 snprintb(sbuf2, sizeof(sbuf2), 835 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 836 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 837 (u_int32_t)le32toh(p->td.td_status)); 838 839 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 840 "D=%d,maxlen=%d\n", sbuf, sbuf2, 841 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 842 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 843 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 844 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 845 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 846 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 847 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 848 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 849 BUS_DMASYNC_PREREAD); 850 } 851 852 void 853 uhci_dump_qh(uhci_soft_qh_t *sqh) 854 { 855 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 856 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 857 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 858 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 859 le32toh(sqh->qh.qh_elink))); 860 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 861 } 862 863 864 #if 1 865 void 866 uhci_dump(void) 867 { 868 uhci_dump_all(thesc); 869 } 870 #endif 871 872 void 873 uhci_dump_all(uhci_softc_t *sc) 874 { 875 uhci_dumpregs(sc); 876 printf("intrs=%d\n", sc->sc_bus.no_intrs); 877 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 878 uhci_dump_qh(sc->sc_lctl_start); 879 } 880 881 882 void 883 uhci_dump_qhs(uhci_soft_qh_t *sqh) 884 { 885 uhci_dump_qh(sqh); 886 887 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 888 * Traverses sideways first, then down. 889 * 890 * QH1 891 * QH2 892 * No QH 893 * TD2.1 894 * TD2.2 895 * TD1.1 896 * etc. 897 * 898 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 899 */ 900 901 902 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 903 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 904 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 905 uhci_dump_qhs(sqh->hlink); 906 else 907 DPRINTF(("No QH\n")); 908 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 909 910 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 911 uhci_dump_tds(sqh->elink); 912 else 913 DPRINTF(("No TD\n")); 914 } 915 916 void 917 uhci_dump_tds(uhci_soft_td_t *std) 918 { 919 uhci_soft_td_t *td; 920 int stop; 921 922 for(td = std; td != NULL; td = td->link.std) { 923 uhci_dump_td(td); 924 925 /* Check whether the link pointer in this TD marks 926 * the link pointer as end of queue. This avoids 927 * printing the free list in case the queue/TD has 928 * already been moved there (seatbelt). 929 */ 930 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 931 sizeof(td->td.td_link), 932 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 933 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 934 le32toh(td->td.td_link) == 0); 935 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 936 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 937 if (stop) 938 break; 939 } 940 } 941 942 Static void 943 uhci_dump_ii(uhci_intr_info_t *ii) 944 { 945 usbd_pipe_handle pipe; 946 usb_endpoint_descriptor_t *ed; 947 usbd_device_handle dev; 948 949 #ifdef DIAGNOSTIC 950 #define DONE ii->isdone 951 #else 952 #define DONE 0 953 #endif 954 if (ii == NULL) { 955 printf("ii NULL\n"); 956 return; 957 } 958 if (ii->xfer == NULL) { 959 printf("ii %p: done=%d xfer=NULL\n", 960 ii, DONE); 961 return; 962 } 963 pipe = ii->xfer->pipe; 964 if (pipe == NULL) { 965 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 966 ii, DONE, ii->xfer); 967 return; 968 } 969 if (pipe->endpoint == NULL) { 970 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 971 ii, DONE, ii->xfer, pipe); 972 return; 973 } 974 if (pipe->device == NULL) { 975 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 976 ii, DONE, ii->xfer, pipe); 977 return; 978 } 979 ed = pipe->endpoint->edesc; 980 dev = pipe->device; 981 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 982 ii, DONE, ii->xfer, dev, 983 UGETW(dev->ddesc.idVendor), 984 UGETW(dev->ddesc.idProduct), 985 dev->address, pipe, 986 ed->bEndpointAddress, ed->bmAttributes); 987 #undef DONE 988 } 989 990 void uhci_dump_iis(struct uhci_softc *sc); 991 void 992 uhci_dump_iis(struct uhci_softc *sc) 993 { 994 uhci_intr_info_t *ii; 995 996 printf("intr_info list:\n"); 997 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 998 uhci_dump_ii(ii); 999 } 1000 1001 void iidump(void); 1002 void iidump(void) { uhci_dump_iis(thesc); } 1003 1004 #endif 1005 1006 /* 1007 * This routine is executed periodically and simulates interrupts 1008 * from the root controller interrupt pipe for port status change. 1009 */ 1010 void 1011 uhci_poll_hub(void *addr) 1012 { 1013 usbd_xfer_handle xfer = addr; 1014 usbd_pipe_handle pipe = xfer->pipe; 1015 uhci_softc_t *sc; 1016 u_char *p; 1017 1018 DPRINTFN(20, ("uhci_poll_hub\n")); 1019 1020 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1021 return; /* device has detached */ 1022 sc = pipe->device->bus->hci_private; 1023 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1024 1025 p = KERNADDR(&xfer->dmabuf, 0); 1026 p[0] = 0; 1027 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1028 p[0] |= 1<<1; 1029 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1030 p[0] |= 1<<2; 1031 if (p[0] == 0) 1032 /* No change, try again in a while */ 1033 return; 1034 1035 xfer->actlen = 1; 1036 xfer->status = USBD_NORMAL_COMPLETION; 1037 mutex_enter(&sc->sc_lock); 1038 xfer->device->bus->intr_context++; 1039 usb_transfer_complete(xfer); 1040 xfer->device->bus->intr_context--; 1041 mutex_exit(&sc->sc_lock); 1042 } 1043 1044 void 1045 uhci_root_intr_done(usbd_xfer_handle xfer) 1046 { 1047 } 1048 1049 void 1050 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1051 { 1052 } 1053 1054 /* 1055 * Let the last QH loop back to the high speed control transfer QH. 1056 * This is what intel calls "bandwidth reclamation" and improves 1057 * USB performance a lot for some devices. 1058 * If we are already looping, just count it. 1059 */ 1060 void 1061 uhci_add_loop(uhci_softc_t *sc) { 1062 #ifdef UHCI_DEBUG 1063 if (uhcinoloop) 1064 return; 1065 #endif 1066 if (++sc->sc_loops == 1) { 1067 DPRINTFN(5,("uhci_start_loop: add\n")); 1068 /* Note, we don't loop back the soft pointer. */ 1069 sc->sc_last_qh->qh.qh_hlink = 1070 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1071 usb_syncmem(&sc->sc_last_qh->dma, 1072 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1073 sizeof(sc->sc_last_qh->qh.qh_hlink), 1074 BUS_DMASYNC_PREWRITE); 1075 } 1076 } 1077 1078 void 1079 uhci_rem_loop(uhci_softc_t *sc) { 1080 #ifdef UHCI_DEBUG 1081 if (uhcinoloop) 1082 return; 1083 #endif 1084 if (--sc->sc_loops == 0) { 1085 DPRINTFN(5,("uhci_end_loop: remove\n")); 1086 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1087 usb_syncmem(&sc->sc_last_qh->dma, 1088 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1089 sizeof(sc->sc_last_qh->qh.qh_hlink), 1090 BUS_DMASYNC_PREWRITE); 1091 } 1092 } 1093 1094 /* Add high speed control QH, called with thread lock held. */ 1095 void 1096 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1097 { 1098 uhci_soft_qh_t *eqh; 1099 1100 KASSERT(mutex_owned(&sc->sc_lock)); 1101 1102 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1103 eqh = sc->sc_hctl_end; 1104 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1105 sizeof(eqh->qh.qh_hlink), 1106 BUS_DMASYNC_POSTWRITE); 1107 sqh->hlink = eqh->hlink; 1108 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1109 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1110 BUS_DMASYNC_PREWRITE); 1111 eqh->hlink = sqh; 1112 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1113 sc->sc_hctl_end = sqh; 1114 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1115 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1116 #ifdef UHCI_CTL_LOOP 1117 uhci_add_loop(sc); 1118 #endif 1119 } 1120 1121 /* Remove high speed control QH, called with thread lock held. */ 1122 void 1123 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1124 { 1125 uhci_soft_qh_t *pqh; 1126 1127 KASSERT(mutex_owned(&sc->sc_lock)); 1128 1129 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1130 #ifdef UHCI_CTL_LOOP 1131 uhci_rem_loop(sc); 1132 #endif 1133 /* 1134 * The T bit should be set in the elink of the QH so that the HC 1135 * doesn't follow the pointer. This condition may fail if the 1136 * the transferred packet was short so that the QH still points 1137 * at the last used TD. 1138 * In this case we set the T bit and wait a little for the HC 1139 * to stop looking at the TD. 1140 * Note that if the TD chain is large enough, the controller 1141 * may still be looking at the chain at the end of this function. 1142 * uhci_free_std_chain() will make sure the controller stops 1143 * looking at it quickly, but until then we should not change 1144 * sqh->hlink. 1145 */ 1146 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1147 sizeof(sqh->qh.qh_elink), 1148 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1149 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1150 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1151 usb_syncmem(&sqh->dma, 1152 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1153 sizeof(sqh->qh.qh_elink), 1154 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1155 delay(UHCI_QH_REMOVE_DELAY); 1156 } 1157 1158 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1159 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1160 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1161 pqh->hlink = sqh->hlink; 1162 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1163 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1164 sizeof(pqh->qh.qh_hlink), 1165 BUS_DMASYNC_PREWRITE); 1166 delay(UHCI_QH_REMOVE_DELAY); 1167 if (sc->sc_hctl_end == sqh) 1168 sc->sc_hctl_end = pqh; 1169 } 1170 1171 /* Add low speed control QH, called with thread lock held. */ 1172 void 1173 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1174 { 1175 uhci_soft_qh_t *eqh; 1176 1177 KASSERT(mutex_owned(&sc->sc_lock)); 1178 1179 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1180 eqh = sc->sc_lctl_end; 1181 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1182 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1183 sqh->hlink = eqh->hlink; 1184 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1185 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1186 BUS_DMASYNC_PREWRITE); 1187 eqh->hlink = sqh; 1188 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1189 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1190 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1191 sc->sc_lctl_end = sqh; 1192 } 1193 1194 /* Remove low speed control QH, called with thread lock held. */ 1195 void 1196 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1197 { 1198 uhci_soft_qh_t *pqh; 1199 1200 KASSERT(mutex_owned(&sc->sc_lock)); 1201 1202 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1203 /* See comment in uhci_remove_hs_ctrl() */ 1204 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1205 sizeof(sqh->qh.qh_elink), 1206 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1207 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1208 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1209 usb_syncmem(&sqh->dma, 1210 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1211 sizeof(sqh->qh.qh_elink), 1212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1213 delay(UHCI_QH_REMOVE_DELAY); 1214 } 1215 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1216 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1217 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1218 pqh->hlink = sqh->hlink; 1219 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1220 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1221 sizeof(pqh->qh.qh_hlink), 1222 BUS_DMASYNC_PREWRITE); 1223 delay(UHCI_QH_REMOVE_DELAY); 1224 if (sc->sc_lctl_end == sqh) 1225 sc->sc_lctl_end = pqh; 1226 } 1227 1228 /* Add bulk QH, called with thread lock held. */ 1229 void 1230 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1231 { 1232 uhci_soft_qh_t *eqh; 1233 1234 KASSERT(mutex_owned(&sc->sc_lock)); 1235 1236 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1237 eqh = sc->sc_bulk_end; 1238 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1239 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1240 sqh->hlink = eqh->hlink; 1241 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1242 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1243 BUS_DMASYNC_PREWRITE); 1244 eqh->hlink = sqh; 1245 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1246 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1247 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1248 sc->sc_bulk_end = sqh; 1249 uhci_add_loop(sc); 1250 } 1251 1252 /* Remove bulk QH, called with thread lock held. */ 1253 void 1254 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1255 { 1256 uhci_soft_qh_t *pqh; 1257 1258 KASSERT(mutex_owned(&sc->sc_lock)); 1259 1260 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1261 uhci_rem_loop(sc); 1262 /* See comment in uhci_remove_hs_ctrl() */ 1263 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1264 sizeof(sqh->qh.qh_elink), 1265 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1266 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1267 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1268 usb_syncmem(&sqh->dma, 1269 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1270 sizeof(sqh->qh.qh_elink), 1271 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1272 delay(UHCI_QH_REMOVE_DELAY); 1273 } 1274 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1275 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1276 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1277 pqh->hlink = sqh->hlink; 1278 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1279 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1280 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1281 delay(UHCI_QH_REMOVE_DELAY); 1282 if (sc->sc_bulk_end == sqh) 1283 sc->sc_bulk_end = pqh; 1284 } 1285 1286 Static int uhci_intr1(uhci_softc_t *); 1287 1288 int 1289 uhci_intr(void *arg) 1290 { 1291 uhci_softc_t *sc = arg; 1292 int ret = 0; 1293 1294 mutex_spin_enter(&sc->sc_intr_lock); 1295 1296 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1297 goto done; 1298 1299 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1300 #ifdef DIAGNOSTIC 1301 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1302 #endif 1303 goto done; 1304 } 1305 1306 ret = uhci_intr1(sc); 1307 1308 done: 1309 mutex_spin_exit(&sc->sc_intr_lock); 1310 return ret; 1311 } 1312 1313 int 1314 uhci_intr1(uhci_softc_t *sc) 1315 { 1316 int status; 1317 int ack; 1318 1319 #ifdef UHCI_DEBUG 1320 if (uhcidebug > 15) { 1321 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1322 uhci_dumpregs(sc); 1323 } 1324 #endif 1325 1326 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1327 1328 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1329 if (status == 0) /* The interrupt was not for us. */ 1330 return (0); 1331 1332 if (sc->sc_suspend != PWR_RESUME) { 1333 #ifdef DIAGNOSTIC 1334 printf("%s: interrupt while not operating ignored\n", 1335 device_xname(sc->sc_dev)); 1336 #endif 1337 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1338 return (0); 1339 } 1340 1341 ack = 0; 1342 if (status & UHCI_STS_USBINT) 1343 ack |= UHCI_STS_USBINT; 1344 if (status & UHCI_STS_USBEI) 1345 ack |= UHCI_STS_USBEI; 1346 if (status & UHCI_STS_RD) { 1347 ack |= UHCI_STS_RD; 1348 #ifdef UHCI_DEBUG 1349 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1350 #endif 1351 } 1352 if (status & UHCI_STS_HSE) { 1353 ack |= UHCI_STS_HSE; 1354 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1355 } 1356 if (status & UHCI_STS_HCPE) { 1357 ack |= UHCI_STS_HCPE; 1358 printf("%s: host controller process error\n", 1359 device_xname(sc->sc_dev)); 1360 } 1361 1362 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1363 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1364 /* no acknowledge needed */ 1365 if (!sc->sc_dying) { 1366 printf("%s: host controller halted\n", 1367 device_xname(sc->sc_dev)); 1368 #ifdef UHCI_DEBUG 1369 uhci_dump_all(sc); 1370 #endif 1371 } 1372 sc->sc_dying = 1; 1373 } 1374 1375 if (!ack) 1376 return (0); /* nothing to acknowledge */ 1377 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1378 1379 sc->sc_bus.no_intrs++; 1380 usb_schedsoftintr(&sc->sc_bus); 1381 1382 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1383 1384 return (1); 1385 } 1386 1387 void 1388 uhci_softintr(void *v) 1389 { 1390 struct usbd_bus *bus = v; 1391 uhci_softc_t *sc = bus->hci_private; 1392 uhci_intr_info_t *ii, *nextii; 1393 1394 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1395 1396 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1397 sc->sc_bus.intr_context)); 1398 1399 sc->sc_bus.intr_context++; 1400 1401 /* 1402 * Interrupts on UHCI really suck. When the host controller 1403 * interrupts because a transfer is completed there is no 1404 * way of knowing which transfer it was. You can scan down 1405 * the TDs and QHs of the previous frame to limit the search, 1406 * but that assumes that the interrupt was not delayed by more 1407 * than 1 ms, which may not always be true (e.g. after debug 1408 * output on a slow console). 1409 * We scan all interrupt descriptors to see if any have 1410 * completed. 1411 */ 1412 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1413 nextii = LIST_NEXT(ii, list); 1414 uhci_check_intr(sc, ii); 1415 } 1416 1417 if (sc->sc_softwake) { 1418 sc->sc_softwake = 0; 1419 cv_broadcast(&sc->sc_softwake_cv); 1420 } 1421 1422 sc->sc_bus.intr_context--; 1423 } 1424 1425 /* Check for an interrupt. */ 1426 void 1427 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1428 { 1429 uhci_soft_td_t *std, *lstd; 1430 u_int32_t status; 1431 1432 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1433 #ifdef DIAGNOSTIC 1434 if (ii == NULL) { 1435 printf("uhci_check_intr: no ii? %p\n", ii); 1436 return; 1437 } 1438 #endif 1439 if (ii->xfer->status == USBD_CANCELLED || 1440 ii->xfer->status == USBD_TIMEOUT) { 1441 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1442 return; 1443 } 1444 1445 if (ii->stdstart == NULL) 1446 return; 1447 lstd = ii->stdend; 1448 #ifdef DIAGNOSTIC 1449 if (lstd == NULL) { 1450 printf("uhci_check_intr: std==0\n"); 1451 return; 1452 } 1453 #endif 1454 /* 1455 * If the last TD is still active we need to check whether there 1456 * is an error somewhere in the middle, or whether there was a 1457 * short packet (SPD and not ACTIVE). 1458 */ 1459 usb_syncmem(&lstd->dma, 1460 lstd->offs + offsetof(uhci_td_t, td_status), 1461 sizeof(lstd->td.td_status), 1462 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1463 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1464 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1465 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1466 usb_syncmem(&std->dma, 1467 std->offs + offsetof(uhci_td_t, td_status), 1468 sizeof(std->td.td_status), 1469 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1470 status = le32toh(std->td.td_status); 1471 usb_syncmem(&std->dma, 1472 std->offs + offsetof(uhci_td_t, td_status), 1473 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1474 /* If there's an active TD the xfer isn't done. */ 1475 if (status & UHCI_TD_ACTIVE) 1476 break; 1477 /* Any kind of error makes the xfer done. */ 1478 if (status & UHCI_TD_STALLED) 1479 goto done; 1480 /* We want short packets, and it is short: it's done */ 1481 usb_syncmem(&std->dma, 1482 std->offs + offsetof(uhci_td_t, td_token), 1483 sizeof(std->td.td_token), 1484 BUS_DMASYNC_POSTWRITE); 1485 if ((status & UHCI_TD_SPD) && 1486 UHCI_TD_GET_ACTLEN(status) < 1487 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1488 goto done; 1489 } 1490 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1491 ii, ii->stdstart)); 1492 usb_syncmem(&lstd->dma, 1493 lstd->offs + offsetof(uhci_td_t, td_status), 1494 sizeof(lstd->td.td_status), 1495 BUS_DMASYNC_PREREAD); 1496 return; 1497 } 1498 done: 1499 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1500 callout_stop(&ii->xfer->timeout_handle); 1501 uhci_idone(ii); 1502 } 1503 1504 /* Called with USB thread lock held. */ 1505 void 1506 uhci_idone(uhci_intr_info_t *ii) 1507 { 1508 usbd_xfer_handle xfer = ii->xfer; 1509 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1510 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1511 uhci_soft_td_t *std; 1512 u_int32_t status = 0, nstatus; 1513 int actlen; 1514 1515 KASSERT(mutex_owned(&sc->sc_lock)); 1516 1517 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1518 #ifdef DIAGNOSTIC 1519 { 1520 /* XXX SMP? */ 1521 int s = splhigh(); 1522 if (ii->isdone) { 1523 splx(s); 1524 #ifdef UHCI_DEBUG 1525 printf("uhci_idone: ii is done!\n "); 1526 uhci_dump_ii(ii); 1527 #else 1528 printf("uhci_idone: ii=%p is done!\n", ii); 1529 #endif 1530 return; 1531 } 1532 ii->isdone = 1; 1533 splx(s); 1534 } 1535 #endif 1536 1537 if (xfer->nframes != 0) { 1538 /* Isoc transfer, do things differently. */ 1539 uhci_soft_td_t **stds = upipe->u.iso.stds; 1540 int i, n, nframes, len; 1541 1542 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1543 1544 nframes = xfer->nframes; 1545 actlen = 0; 1546 n = UXFER(xfer)->curframe; 1547 for (i = 0; i < nframes; i++) { 1548 std = stds[n]; 1549 #ifdef UHCI_DEBUG 1550 if (uhcidebug > 5) { 1551 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1552 uhci_dump_td(std); 1553 } 1554 #endif 1555 if (++n >= UHCI_VFRAMELIST_COUNT) 1556 n = 0; 1557 usb_syncmem(&std->dma, 1558 std->offs + offsetof(uhci_td_t, td_status), 1559 sizeof(std->td.td_status), 1560 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1561 status = le32toh(std->td.td_status); 1562 len = UHCI_TD_GET_ACTLEN(status); 1563 xfer->frlengths[i] = len; 1564 actlen += len; 1565 } 1566 upipe->u.iso.inuse -= nframes; 1567 xfer->actlen = actlen; 1568 xfer->status = USBD_NORMAL_COMPLETION; 1569 goto end; 1570 } 1571 1572 #ifdef UHCI_DEBUG 1573 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1574 ii, xfer, upipe)); 1575 if (uhcidebug > 10) 1576 uhci_dump_tds(ii->stdstart); 1577 #endif 1578 1579 /* The transfer is done, compute actual length and status. */ 1580 actlen = 0; 1581 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1582 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1583 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1584 nstatus = le32toh(std->td.td_status); 1585 if (nstatus & UHCI_TD_ACTIVE) 1586 break; 1587 1588 status = nstatus; 1589 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1590 UHCI_TD_PID_SETUP) 1591 actlen += UHCI_TD_GET_ACTLEN(status); 1592 else { 1593 /* 1594 * UHCI will report CRCTO in addition to a STALL or NAK 1595 * for a SETUP transaction. See section 3.2.2, "TD 1596 * CONTROL AND STATUS". 1597 */ 1598 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1599 status &= ~UHCI_TD_CRCTO; 1600 } 1601 } 1602 /* If there are left over TDs we need to update the toggle. */ 1603 if (std != NULL) 1604 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1605 1606 status &= UHCI_TD_ERROR; 1607 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1608 actlen, status)); 1609 xfer->actlen = actlen; 1610 if (status != 0) { 1611 #ifdef UHCI_DEBUG 1612 char sbuf[128]; 1613 1614 snprintb(sbuf, sizeof(sbuf), 1615 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1616 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1617 1618 DPRINTFN((status == UHCI_TD_STALLED)*10, 1619 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1620 "status 0x%s\n", 1621 xfer->pipe->device->address, 1622 xfer->pipe->endpoint->edesc->bEndpointAddress, 1623 sbuf)); 1624 #endif 1625 1626 if (status == UHCI_TD_STALLED) 1627 xfer->status = USBD_STALLED; 1628 else 1629 xfer->status = USBD_IOERROR; /* more info XXX */ 1630 } else { 1631 xfer->status = USBD_NORMAL_COMPLETION; 1632 } 1633 1634 end: 1635 usb_transfer_complete(xfer); 1636 KASSERT(mutex_owned(&sc->sc_lock)); 1637 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1638 } 1639 1640 /* 1641 * Called when a request does not complete. 1642 */ 1643 void 1644 uhci_timeout(void *addr) 1645 { 1646 uhci_intr_info_t *ii = addr; 1647 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1648 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1649 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1650 1651 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1652 1653 if (sc->sc_dying) { 1654 mutex_enter(&sc->sc_lock); 1655 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1656 mutex_exit(&sc->sc_lock); 1657 return; 1658 } 1659 1660 /* Execute the abort in a process context. */ 1661 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1662 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1663 USB_TASKQ_HC); 1664 } 1665 1666 void 1667 uhci_timeout_task(void *addr) 1668 { 1669 usbd_xfer_handle xfer = addr; 1670 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1671 1672 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1673 1674 mutex_enter(&sc->sc_lock); 1675 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1676 mutex_exit(&sc->sc_lock); 1677 } 1678 1679 /* 1680 * Wait here until controller claims to have an interrupt. 1681 * Then call uhci_intr and return. Use timeout to avoid waiting 1682 * too long. 1683 * Only used during boot when interrupts are not enabled yet. 1684 */ 1685 void 1686 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1687 { 1688 int timo = xfer->timeout; 1689 uhci_intr_info_t *ii; 1690 1691 mutex_enter(&sc->sc_lock); 1692 1693 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1694 1695 xfer->status = USBD_IN_PROGRESS; 1696 for (; timo >= 0; timo--) { 1697 usb_delay_ms(&sc->sc_bus, 1); 1698 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1699 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1700 mutex_spin_enter(&sc->sc_intr_lock); 1701 uhci_intr1(sc); 1702 mutex_spin_exit(&sc->sc_intr_lock); 1703 if (xfer->status != USBD_IN_PROGRESS) 1704 goto done; 1705 } 1706 } 1707 1708 /* Timeout */ 1709 DPRINTF(("uhci_waitintr: timeout\n")); 1710 for (ii = LIST_FIRST(&sc->sc_intrhead); 1711 ii != NULL && ii->xfer != xfer; 1712 ii = LIST_NEXT(ii, list)) 1713 ; 1714 #ifdef DIAGNOSTIC 1715 if (ii == NULL) 1716 panic("uhci_waitintr: lost intr_info"); 1717 #endif 1718 uhci_idone(ii); 1719 1720 done: 1721 mutex_exit(&sc->sc_lock); 1722 } 1723 1724 void 1725 uhci_poll(struct usbd_bus *bus) 1726 { 1727 uhci_softc_t *sc = bus->hci_private; 1728 1729 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1730 mutex_spin_enter(&sc->sc_intr_lock); 1731 uhci_intr1(sc); 1732 mutex_spin_exit(&sc->sc_intr_lock); 1733 } 1734 } 1735 1736 void 1737 uhci_reset(uhci_softc_t *sc) 1738 { 1739 int n; 1740 1741 UHCICMD(sc, UHCI_CMD_HCRESET); 1742 /* The reset bit goes low when the controller is done. */ 1743 for (n = 0; n < UHCI_RESET_TIMEOUT && 1744 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1745 usb_delay_ms(&sc->sc_bus, 1); 1746 if (n >= UHCI_RESET_TIMEOUT) 1747 printf("%s: controller did not reset\n", 1748 device_xname(sc->sc_dev)); 1749 } 1750 1751 usbd_status 1752 uhci_run(uhci_softc_t *sc, int run) 1753 { 1754 int n, running; 1755 u_int16_t cmd; 1756 1757 run = run != 0; 1758 mutex_spin_enter(&sc->sc_intr_lock); 1759 DPRINTF(("uhci_run: setting run=%d\n", run)); 1760 cmd = UREAD2(sc, UHCI_CMD); 1761 if (run) 1762 cmd |= UHCI_CMD_RS; 1763 else 1764 cmd &= ~UHCI_CMD_RS; 1765 UHCICMD(sc, cmd); 1766 for(n = 0; n < 10; n++) { 1767 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1768 /* return when we've entered the state we want */ 1769 if (run == running) { 1770 mutex_spin_exit(&sc->sc_intr_lock); 1771 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1772 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1773 return (USBD_NORMAL_COMPLETION); 1774 } 1775 usb_delay_ms(&sc->sc_bus, 1); 1776 } 1777 mutex_spin_exit(&sc->sc_intr_lock); 1778 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1779 run ? "start" : "stop"); 1780 return (USBD_IOERROR); 1781 } 1782 1783 /* 1784 * Memory management routines. 1785 * uhci_alloc_std allocates TDs 1786 * uhci_alloc_sqh allocates QHs 1787 * These two routines do their own free list management, 1788 * partly for speed, partly because allocating DMAable memory 1789 * has page size granularaity so much memory would be wasted if 1790 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1791 */ 1792 1793 uhci_soft_td_t * 1794 uhci_alloc_std(uhci_softc_t *sc) 1795 { 1796 uhci_soft_td_t *std; 1797 usbd_status err; 1798 int i, offs; 1799 usb_dma_t dma; 1800 1801 if (sc->sc_freetds == NULL) { 1802 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1803 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1804 UHCI_TD_ALIGN, &dma); 1805 if (err) 1806 return (0); 1807 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1808 offs = i * UHCI_STD_SIZE; 1809 std = KERNADDR(&dma, offs); 1810 std->physaddr = DMAADDR(&dma, offs); 1811 std->dma = dma; 1812 std->offs = offs; 1813 std->link.std = sc->sc_freetds; 1814 sc->sc_freetds = std; 1815 } 1816 } 1817 std = sc->sc_freetds; 1818 sc->sc_freetds = std->link.std; 1819 memset(&std->td, 0, sizeof(uhci_td_t)); 1820 return std; 1821 } 1822 1823 void 1824 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1825 { 1826 #ifdef DIAGNOSTIC 1827 #define TD_IS_FREE 0x12345678 1828 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1829 printf("uhci_free_std: freeing free TD %p\n", std); 1830 return; 1831 } 1832 std->td.td_token = htole32(TD_IS_FREE); 1833 #endif 1834 std->link.std = sc->sc_freetds; 1835 sc->sc_freetds = std; 1836 } 1837 1838 uhci_soft_qh_t * 1839 uhci_alloc_sqh(uhci_softc_t *sc) 1840 { 1841 uhci_soft_qh_t *sqh; 1842 usbd_status err; 1843 int i, offs; 1844 usb_dma_t dma; 1845 1846 if (sc->sc_freeqhs == NULL) { 1847 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1848 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1849 UHCI_QH_ALIGN, &dma); 1850 if (err) 1851 return (0); 1852 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1853 offs = i * UHCI_SQH_SIZE; 1854 sqh = KERNADDR(&dma, offs); 1855 sqh->physaddr = DMAADDR(&dma, offs); 1856 sqh->dma = dma; 1857 sqh->offs = offs; 1858 sqh->hlink = sc->sc_freeqhs; 1859 sc->sc_freeqhs = sqh; 1860 } 1861 } 1862 sqh = sc->sc_freeqhs; 1863 sc->sc_freeqhs = sqh->hlink; 1864 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1865 return (sqh); 1866 } 1867 1868 void 1869 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1870 { 1871 sqh->hlink = sc->sc_freeqhs; 1872 sc->sc_freeqhs = sqh; 1873 } 1874 1875 void 1876 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1877 uhci_soft_td_t *stdend) 1878 { 1879 uhci_soft_td_t *p; 1880 1881 /* 1882 * to avoid race condition with the controller which may be looking 1883 * at this chain, we need to first invalidate all links, and 1884 * then wait for the controller to move to another queue 1885 */ 1886 for (p = std; p != stdend; p = p->link.std) { 1887 usb_syncmem(&p->dma, 1888 p->offs + offsetof(uhci_td_t, td_link), 1889 sizeof(p->td.td_link), 1890 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1891 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1892 p->td.td_link = UHCI_PTR_T; 1893 usb_syncmem(&p->dma, 1894 p->offs + offsetof(uhci_td_t, td_link), 1895 sizeof(p->td.td_link), 1896 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1897 } 1898 } 1899 delay(UHCI_QH_REMOVE_DELAY); 1900 1901 for (; std != stdend; std = p) { 1902 p = std->link.std; 1903 uhci_free_std(sc, std); 1904 } 1905 } 1906 1907 usbd_status 1908 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1909 int rd, u_int16_t flags, usb_dma_t *dma, 1910 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1911 { 1912 uhci_soft_td_t *p, *lastp; 1913 uhci_physaddr_t lastlink; 1914 int i, ntd, l, tog, maxp; 1915 u_int32_t status; 1916 int addr = upipe->pipe.device->address; 1917 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1918 1919 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1920 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1921 upipe->pipe.device->speed, flags)); 1922 1923 KASSERT(mutex_owned(&sc->sc_lock)); 1924 1925 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1926 if (maxp == 0) { 1927 printf("uhci_alloc_std_chain: maxp=0\n"); 1928 return (USBD_INVAL); 1929 } 1930 ntd = (len + maxp - 1) / maxp; 1931 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1932 ntd++; 1933 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1934 if (ntd == 0) { 1935 *sp = *ep = 0; 1936 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1937 return (USBD_NORMAL_COMPLETION); 1938 } 1939 tog = upipe->nexttoggle; 1940 if (ntd % 2 == 0) 1941 tog ^= 1; 1942 upipe->nexttoggle = tog ^ 1; 1943 lastp = NULL; 1944 lastlink = UHCI_PTR_T; 1945 ntd--; 1946 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1947 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1948 status |= UHCI_TD_LS; 1949 if (flags & USBD_SHORT_XFER_OK) 1950 status |= UHCI_TD_SPD; 1951 usb_syncmem(dma, 0, len, 1952 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1953 for (i = ntd; i >= 0; i--) { 1954 p = uhci_alloc_std(sc); 1955 if (p == NULL) { 1956 KASSERT(lastp != NULL); 1957 uhci_free_std_chain(sc, lastp, NULL); 1958 return (USBD_NOMEM); 1959 } 1960 p->link.std = lastp; 1961 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1962 lastp = p; 1963 lastlink = p->physaddr; 1964 p->td.td_status = htole32(status); 1965 if (i == ntd) { 1966 /* last TD */ 1967 l = len % maxp; 1968 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1969 l = maxp; 1970 *ep = p; 1971 } else 1972 l = maxp; 1973 p->td.td_token = 1974 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1975 UHCI_TD_OUT(l, endpt, addr, tog)); 1976 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1977 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1978 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1979 tog ^= 1; 1980 } 1981 *sp = lastp; 1982 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1983 upipe->nexttoggle)); 1984 return (USBD_NORMAL_COMPLETION); 1985 } 1986 1987 void 1988 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1989 { 1990 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1991 upipe->nexttoggle = 0; 1992 } 1993 1994 void 1995 uhci_noop(usbd_pipe_handle pipe) 1996 { 1997 } 1998 1999 usbd_status 2000 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 2001 { 2002 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2003 usbd_status err; 2004 2005 /* Insert last in queue. */ 2006 mutex_enter(&sc->sc_lock); 2007 err = usb_insert_transfer(xfer); 2008 mutex_exit(&sc->sc_lock); 2009 if (err) 2010 return (err); 2011 2012 /* 2013 * Pipe isn't running (otherwise err would be USBD_INPROG), 2014 * so start it first. 2015 */ 2016 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2017 } 2018 2019 usbd_status 2020 uhci_device_bulk_start(usbd_xfer_handle xfer) 2021 { 2022 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2023 usbd_device_handle dev = upipe->pipe.device; 2024 uhci_softc_t *sc = dev->bus->hci_private; 2025 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2026 uhci_soft_td_t *data, *dataend; 2027 uhci_soft_qh_t *sqh; 2028 usbd_status err; 2029 int len, isread, endpt; 2030 2031 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2032 xfer, xfer->length, xfer->flags, ii)); 2033 2034 if (sc->sc_dying) 2035 return (USBD_IOERROR); 2036 2037 #ifdef DIAGNOSTIC 2038 if (xfer->rqflags & URQ_REQUEST) 2039 panic("uhci_device_bulk_transfer: a request"); 2040 #endif 2041 2042 mutex_enter(&sc->sc_lock); 2043 2044 len = xfer->length; 2045 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2046 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2047 sqh = upipe->u.bulk.sqh; 2048 2049 upipe->u.bulk.isread = isread; 2050 upipe->u.bulk.length = len; 2051 2052 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2053 &xfer->dmabuf, &data, &dataend); 2054 if (err) { 2055 mutex_exit(&sc->sc_lock); 2056 return (err); 2057 } 2058 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2059 usb_syncmem(&dataend->dma, 2060 dataend->offs + offsetof(uhci_td_t, td_status), 2061 sizeof(dataend->td.td_status), 2062 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2063 2064 2065 #ifdef UHCI_DEBUG 2066 if (uhcidebug > 8) { 2067 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2068 uhci_dump_tds(data); 2069 } 2070 #endif 2071 2072 /* Set up interrupt info. */ 2073 ii->xfer = xfer; 2074 ii->stdstart = data; 2075 ii->stdend = dataend; 2076 #ifdef DIAGNOSTIC 2077 if (!ii->isdone) { 2078 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2079 } 2080 ii->isdone = 0; 2081 #endif 2082 2083 sqh->elink = data; 2084 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2085 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2086 2087 uhci_add_bulk(sc, sqh); 2088 uhci_add_intr_info(sc, ii); 2089 2090 if (xfer->timeout && !sc->sc_bus.use_polling) { 2091 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2092 uhci_timeout, ii); 2093 } 2094 xfer->status = USBD_IN_PROGRESS; 2095 2096 #ifdef UHCI_DEBUG 2097 if (uhcidebug > 10) { 2098 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2099 uhci_dump_tds(data); 2100 } 2101 #endif 2102 2103 if (sc->sc_bus.use_polling) 2104 uhci_waitintr(sc, xfer); 2105 2106 mutex_exit(&sc->sc_lock); 2107 return (USBD_IN_PROGRESS); 2108 } 2109 2110 /* Abort a device bulk request. */ 2111 void 2112 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2113 { 2114 #ifdef DIAGNOSTIC 2115 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2116 #endif 2117 2118 KASSERT(mutex_owned(&sc->sc_lock)); 2119 2120 DPRINTF(("uhci_device_bulk_abort:\n")); 2121 uhci_abort_xfer(xfer, USBD_CANCELLED); 2122 } 2123 2124 /* 2125 * Abort a device request. 2126 * If this routine is called at splusb() it guarantees that the request 2127 * will be removed from the hardware scheduling and that the callback 2128 * for it will be called with USBD_CANCELLED status. 2129 * It's impossible to guarantee that the requested transfer will not 2130 * have happened since the hardware runs concurrently. 2131 * If the transaction has already happened we rely on the ordinary 2132 * interrupt processing to process it. 2133 * XXX This is most probably wrong. 2134 * XXXMRG this doesn't make sense anymore. 2135 */ 2136 void 2137 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2138 { 2139 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2140 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2141 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2142 uhci_soft_td_t *std; 2143 int wake; 2144 2145 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2146 2147 KASSERT(mutex_owned(&sc->sc_lock)); 2148 2149 if (sc->sc_dying) { 2150 /* If we're dying, just do the software part. */ 2151 xfer->status = status; /* make software ignore it */ 2152 callout_stop(&xfer->timeout_handle); 2153 usb_transfer_complete(xfer); 2154 return; 2155 } 2156 2157 if (xfer->device->bus->intr_context || !curproc) 2158 panic("uhci_abort_xfer: not in process context"); 2159 2160 /* 2161 * If an abort is already in progress then just wait for it to 2162 * complete and return. 2163 */ 2164 if (xfer->hcflags & UXFER_ABORTING) { 2165 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2166 #ifdef DIAGNOSTIC 2167 if (status == USBD_TIMEOUT) 2168 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2169 #endif 2170 /* Override the status which might be USBD_TIMEOUT. */ 2171 xfer->status = status; 2172 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2173 xfer->hcflags |= UXFER_ABORTWAIT; 2174 while (xfer->hcflags & UXFER_ABORTING) 2175 cv_wait(&xfer->hccv, &sc->sc_lock); 2176 goto done; 2177 } 2178 xfer->hcflags |= UXFER_ABORTING; 2179 2180 /* 2181 * Step 1: Make interrupt routine and hardware ignore xfer. 2182 */ 2183 xfer->status = status; /* make software ignore it */ 2184 callout_stop(&xfer->timeout_handle); 2185 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2186 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2187 usb_syncmem(&std->dma, 2188 std->offs + offsetof(uhci_td_t, td_status), 2189 sizeof(std->td.td_status), 2190 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2191 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2192 usb_syncmem(&std->dma, 2193 std->offs + offsetof(uhci_td_t, td_status), 2194 sizeof(std->td.td_status), 2195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2196 } 2197 2198 /* 2199 * Step 2: Wait until we know hardware has finished any possible 2200 * use of the xfer. Also make sure the soft interrupt routine 2201 * has run. 2202 */ 2203 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2204 sc->sc_softwake = 1; 2205 usb_schedsoftintr(&sc->sc_bus); 2206 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2207 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2208 2209 /* 2210 * Step 3: Execute callback. 2211 */ 2212 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2213 #ifdef DIAGNOSTIC 2214 ii->isdone = 1; 2215 #endif 2216 wake = xfer->hcflags & UXFER_ABORTWAIT; 2217 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2218 usb_transfer_complete(xfer); 2219 if (wake) 2220 cv_broadcast(&xfer->hccv); 2221 done: 2222 KASSERT(mutex_owned(&sc->sc_lock)); 2223 } 2224 2225 /* Close a device bulk pipe. */ 2226 void 2227 uhci_device_bulk_close(usbd_pipe_handle pipe) 2228 { 2229 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2230 usbd_device_handle dev = upipe->pipe.device; 2231 uhci_softc_t *sc = dev->bus->hci_private; 2232 2233 KASSERT(mutex_owned(&sc->sc_lock)); 2234 2235 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2236 2237 pipe->endpoint->datatoggle = upipe->nexttoggle; 2238 } 2239 2240 usbd_status 2241 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2242 { 2243 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2244 usbd_status err; 2245 2246 /* Insert last in queue. */ 2247 mutex_enter(&sc->sc_lock); 2248 err = usb_insert_transfer(xfer); 2249 mutex_exit(&sc->sc_lock); 2250 if (err) 2251 return (err); 2252 2253 /* 2254 * Pipe isn't running (otherwise err would be USBD_INPROG), 2255 * so start it first. 2256 */ 2257 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2258 } 2259 2260 usbd_status 2261 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2262 { 2263 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2264 usbd_status err; 2265 2266 if (sc->sc_dying) 2267 return (USBD_IOERROR); 2268 2269 #ifdef DIAGNOSTIC 2270 if (!(xfer->rqflags & URQ_REQUEST)) 2271 panic("uhci_device_ctrl_transfer: not a request"); 2272 #endif 2273 2274 mutex_enter(&sc->sc_lock); 2275 err = uhci_device_request(xfer); 2276 mutex_exit(&sc->sc_lock); 2277 if (err) 2278 return (err); 2279 2280 if (sc->sc_bus.use_polling) 2281 uhci_waitintr(sc, xfer); 2282 return (USBD_IN_PROGRESS); 2283 } 2284 2285 usbd_status 2286 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2287 { 2288 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2289 usbd_status err; 2290 2291 /* Insert last in queue. */ 2292 mutex_enter(&sc->sc_lock); 2293 err = usb_insert_transfer(xfer); 2294 mutex_exit(&sc->sc_lock); 2295 if (err) 2296 return (err); 2297 2298 /* 2299 * Pipe isn't running (otherwise err would be USBD_INPROG), 2300 * so start it first. 2301 */ 2302 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2303 } 2304 2305 usbd_status 2306 uhci_device_intr_start(usbd_xfer_handle xfer) 2307 { 2308 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2309 usbd_device_handle dev = upipe->pipe.device; 2310 uhci_softc_t *sc = dev->bus->hci_private; 2311 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2312 uhci_soft_td_t *data, *dataend; 2313 uhci_soft_qh_t *sqh; 2314 usbd_status err; 2315 int isread, endpt; 2316 int i; 2317 2318 if (sc->sc_dying) 2319 return (USBD_IOERROR); 2320 2321 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2322 xfer, xfer->length, xfer->flags)); 2323 2324 #ifdef DIAGNOSTIC 2325 if (xfer->rqflags & URQ_REQUEST) 2326 panic("uhci_device_intr_transfer: a request"); 2327 #endif 2328 2329 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2330 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2331 2332 upipe->u.intr.isread = isread; 2333 2334 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2335 xfer->flags, &xfer->dmabuf, &data, 2336 &dataend); 2337 if (err) 2338 return (err); 2339 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2340 usb_syncmem(&dataend->dma, 2341 dataend->offs + offsetof(uhci_td_t, td_status), 2342 sizeof(dataend->td.td_status), 2343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2344 2345 #ifdef UHCI_DEBUG 2346 if (uhcidebug > 10) { 2347 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2348 uhci_dump_tds(data); 2349 uhci_dump_qh(upipe->u.intr.qhs[0]); 2350 } 2351 #endif 2352 2353 mutex_enter(&sc->sc_lock); 2354 /* Set up interrupt info. */ 2355 ii->xfer = xfer; 2356 ii->stdstart = data; 2357 ii->stdend = dataend; 2358 #ifdef DIAGNOSTIC 2359 if (!ii->isdone) { 2360 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2361 } 2362 ii->isdone = 0; 2363 #endif 2364 2365 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2366 upipe->u.intr.qhs[0])); 2367 for (i = 0; i < upipe->u.intr.npoll; i++) { 2368 sqh = upipe->u.intr.qhs[i]; 2369 sqh->elink = data; 2370 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2371 usb_syncmem(&sqh->dma, 2372 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2373 sizeof(sqh->qh.qh_elink), 2374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2375 } 2376 uhci_add_intr_info(sc, ii); 2377 xfer->status = USBD_IN_PROGRESS; 2378 mutex_exit(&sc->sc_lock); 2379 2380 #ifdef UHCI_DEBUG 2381 if (uhcidebug > 10) { 2382 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2383 uhci_dump_tds(data); 2384 uhci_dump_qh(upipe->u.intr.qhs[0]); 2385 } 2386 #endif 2387 2388 return (USBD_IN_PROGRESS); 2389 } 2390 2391 /* Abort a device control request. */ 2392 void 2393 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2394 { 2395 #ifdef DIAGNOSTIC 2396 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2397 #endif 2398 2399 KASSERT(mutex_owned(&sc->sc_lock)); 2400 2401 DPRINTF(("uhci_device_ctrl_abort:\n")); 2402 uhci_abort_xfer(xfer, USBD_CANCELLED); 2403 } 2404 2405 /* Close a device control pipe. */ 2406 void 2407 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2408 { 2409 } 2410 2411 /* Abort a device interrupt request. */ 2412 void 2413 uhci_device_intr_abort(usbd_xfer_handle xfer) 2414 { 2415 #ifdef DIAGNOSTIC 2416 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2417 #endif 2418 2419 KASSERT(mutex_owned(&sc->sc_lock)); 2420 2421 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2422 if (xfer->pipe->intrxfer == xfer) { 2423 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2424 xfer->pipe->intrxfer = NULL; 2425 } 2426 uhci_abort_xfer(xfer, USBD_CANCELLED); 2427 } 2428 2429 /* Close a device interrupt pipe. */ 2430 void 2431 uhci_device_intr_close(usbd_pipe_handle pipe) 2432 { 2433 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2434 uhci_softc_t *sc = pipe->device->bus->hci_private; 2435 int i, npoll; 2436 2437 KASSERT(mutex_owned(&sc->sc_lock)); 2438 2439 /* Unlink descriptors from controller data structures. */ 2440 npoll = upipe->u.intr.npoll; 2441 for (i = 0; i < npoll; i++) 2442 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2443 2444 /* 2445 * We now have to wait for any activity on the physical 2446 * descriptors to stop. 2447 */ 2448 usb_delay_ms(&sc->sc_bus, 2); 2449 2450 for(i = 0; i < npoll; i++) 2451 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2452 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2453 2454 /* XXX free other resources */ 2455 } 2456 2457 usbd_status 2458 uhci_device_request(usbd_xfer_handle xfer) 2459 { 2460 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2461 usb_device_request_t *req = &xfer->request; 2462 usbd_device_handle dev = upipe->pipe.device; 2463 uhci_softc_t *sc = dev->bus->hci_private; 2464 int addr = dev->address; 2465 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2466 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2467 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2468 uhci_soft_qh_t *sqh; 2469 int len; 2470 u_int32_t ls; 2471 usbd_status err; 2472 int isread; 2473 2474 KASSERT(mutex_owned(&sc->sc_lock)); 2475 2476 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2477 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2478 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2479 UGETW(req->wIndex), UGETW(req->wLength), 2480 addr, endpt)); 2481 2482 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2483 isread = req->bmRequestType & UT_READ; 2484 len = UGETW(req->wLength); 2485 2486 setup = upipe->u.ctl.setup; 2487 stat = upipe->u.ctl.stat; 2488 sqh = upipe->u.ctl.sqh; 2489 2490 /* Set up data transaction */ 2491 if (len != 0) { 2492 upipe->nexttoggle = 1; 2493 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2494 &xfer->dmabuf, &data, &dataend); 2495 if (err) 2496 return (err); 2497 next = data; 2498 dataend->link.std = stat; 2499 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2500 usb_syncmem(&dataend->dma, 2501 dataend->offs + offsetof(uhci_td_t, td_link), 2502 sizeof(dataend->td.td_link), 2503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2504 } else { 2505 next = stat; 2506 } 2507 upipe->u.ctl.length = len; 2508 2509 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2510 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2511 2512 setup->link.std = next; 2513 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2514 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2515 UHCI_TD_ACTIVE); 2516 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2517 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2518 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2520 2521 stat->link.std = NULL; 2522 stat->td.td_link = htole32(UHCI_PTR_T); 2523 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2524 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2525 stat->td.td_token = 2526 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2527 UHCI_TD_IN (0, endpt, addr, 1)); 2528 stat->td.td_buffer = htole32(0); 2529 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2531 2532 #ifdef UHCI_DEBUG 2533 if (uhcidebug > 10) { 2534 DPRINTF(("uhci_device_request: before transfer\n")); 2535 uhci_dump_tds(setup); 2536 } 2537 #endif 2538 2539 /* Set up interrupt info. */ 2540 ii->xfer = xfer; 2541 ii->stdstart = setup; 2542 ii->stdend = stat; 2543 #ifdef DIAGNOSTIC 2544 if (!ii->isdone) { 2545 printf("uhci_device_request: not done, ii=%p\n", ii); 2546 } 2547 ii->isdone = 0; 2548 #endif 2549 2550 sqh->elink = setup; 2551 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2552 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2553 2554 if (dev->speed == USB_SPEED_LOW) 2555 uhci_add_ls_ctrl(sc, sqh); 2556 else 2557 uhci_add_hs_ctrl(sc, sqh); 2558 uhci_add_intr_info(sc, ii); 2559 #ifdef UHCI_DEBUG 2560 if (uhcidebug > 12) { 2561 uhci_soft_td_t *std; 2562 uhci_soft_qh_t *xqh; 2563 uhci_soft_qh_t *sxqh; 2564 int maxqh = 0; 2565 uhci_physaddr_t link; 2566 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2567 for (std = sc->sc_vframes[0].htd, link = 0; 2568 (link & UHCI_PTR_QH) == 0; 2569 std = std->link.std) { 2570 link = le32toh(std->td.td_link); 2571 uhci_dump_td(std); 2572 } 2573 sxqh = (uhci_soft_qh_t *)std; 2574 uhci_dump_qh(sxqh); 2575 for (xqh = sxqh; 2576 xqh != NULL; 2577 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2578 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2579 uhci_dump_qh(xqh); 2580 } 2581 DPRINTF(("Enqueued QH:\n")); 2582 uhci_dump_qh(sqh); 2583 uhci_dump_tds(sqh->elink); 2584 } 2585 #endif 2586 if (xfer->timeout && !sc->sc_bus.use_polling) { 2587 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2588 uhci_timeout, ii); 2589 } 2590 xfer->status = USBD_IN_PROGRESS; 2591 2592 return (USBD_NORMAL_COMPLETION); 2593 } 2594 2595 usbd_status 2596 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2597 { 2598 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2599 usbd_status err; 2600 2601 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2602 2603 /* Put it on our queue, */ 2604 mutex_enter(&sc->sc_lock); 2605 err = usb_insert_transfer(xfer); 2606 mutex_exit(&sc->sc_lock); 2607 2608 /* bail out on error, */ 2609 if (err && err != USBD_IN_PROGRESS) 2610 return (err); 2611 2612 /* XXX should check inuse here */ 2613 2614 /* insert into schedule, */ 2615 uhci_device_isoc_enter(xfer); 2616 2617 /* and start if the pipe wasn't running */ 2618 if (!err) 2619 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2620 2621 return (err); 2622 } 2623 2624 void 2625 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2626 { 2627 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2628 usbd_device_handle dev = upipe->pipe.device; 2629 uhci_softc_t *sc = dev->bus->hci_private; 2630 struct iso *iso = &upipe->u.iso; 2631 uhci_soft_td_t *std; 2632 u_int32_t buf, len, status, offs; 2633 int i, next, nframes; 2634 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2635 2636 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2637 "nframes=%d\n", 2638 iso->inuse, iso->next, xfer, xfer->nframes)); 2639 2640 if (sc->sc_dying) 2641 return; 2642 2643 if (xfer->status == USBD_IN_PROGRESS) { 2644 /* This request has already been entered into the frame list */ 2645 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2646 /* XXX */ 2647 } 2648 2649 #ifdef DIAGNOSTIC 2650 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2651 printf("uhci_device_isoc_enter: overflow!\n"); 2652 #endif 2653 2654 next = iso->next; 2655 if (next == -1) { 2656 /* Not in use yet, schedule it a few frames ahead. */ 2657 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2658 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2659 } 2660 2661 xfer->status = USBD_IN_PROGRESS; 2662 UXFER(xfer)->curframe = next; 2663 2664 buf = DMAADDR(&xfer->dmabuf, 0); 2665 offs = 0; 2666 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2667 UHCI_TD_ACTIVE | 2668 UHCI_TD_IOS); 2669 nframes = xfer->nframes; 2670 mutex_enter(&sc->sc_lock); 2671 for (i = 0; i < nframes; i++) { 2672 std = iso->stds[next]; 2673 if (++next >= UHCI_VFRAMELIST_COUNT) 2674 next = 0; 2675 len = xfer->frlengths[i]; 2676 std->td.td_buffer = htole32(buf); 2677 usb_syncmem(&xfer->dmabuf, offs, len, 2678 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2679 if (i == nframes - 1) 2680 status |= UHCI_TD_IOC; 2681 std->td.td_status = htole32(status); 2682 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2683 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2684 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2685 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2686 #ifdef UHCI_DEBUG 2687 if (uhcidebug > 5) { 2688 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2689 uhci_dump_td(std); 2690 } 2691 #endif 2692 buf += len; 2693 offs += len; 2694 } 2695 iso->next = next; 2696 iso->inuse += xfer->nframes; 2697 2698 mutex_exit(&sc->sc_lock); 2699 } 2700 2701 usbd_status 2702 uhci_device_isoc_start(usbd_xfer_handle xfer) 2703 { 2704 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2705 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2706 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2707 uhci_soft_td_t *end; 2708 int i; 2709 2710 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2711 2712 mutex_enter(&sc->sc_lock); 2713 2714 if (sc->sc_dying) { 2715 mutex_exit(&sc->sc_lock); 2716 return (USBD_IOERROR); 2717 } 2718 2719 #ifdef DIAGNOSTIC 2720 if (xfer->status != USBD_IN_PROGRESS) 2721 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2722 #endif 2723 2724 /* Find the last TD */ 2725 i = UXFER(xfer)->curframe + xfer->nframes; 2726 if (i >= UHCI_VFRAMELIST_COUNT) 2727 i -= UHCI_VFRAMELIST_COUNT; 2728 end = upipe->u.iso.stds[i]; 2729 2730 #ifdef DIAGNOSTIC 2731 if (end == NULL) { 2732 printf("uhci_device_isoc_start: end == NULL\n"); 2733 return (USBD_INVAL); 2734 } 2735 #endif 2736 2737 /* Set up interrupt info. */ 2738 ii->xfer = xfer; 2739 ii->stdstart = end; 2740 ii->stdend = end; 2741 #ifdef DIAGNOSTIC 2742 if (!ii->isdone) 2743 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2744 ii->isdone = 0; 2745 #endif 2746 uhci_add_intr_info(sc, ii); 2747 2748 mutex_exit(&sc->sc_lock); 2749 2750 return (USBD_IN_PROGRESS); 2751 } 2752 2753 void 2754 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2755 { 2756 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2757 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2758 uhci_soft_td_t **stds = upipe->u.iso.stds; 2759 uhci_soft_td_t *std; 2760 int i, n, nframes, maxlen, len; 2761 2762 KASSERT(mutex_owned(&sc->sc_lock)); 2763 2764 /* Transfer is already done. */ 2765 if (xfer->status != USBD_NOT_STARTED && 2766 xfer->status != USBD_IN_PROGRESS) { 2767 return; 2768 } 2769 2770 /* Give xfer the requested abort code. */ 2771 xfer->status = USBD_CANCELLED; 2772 2773 /* make hardware ignore it, */ 2774 nframes = xfer->nframes; 2775 n = UXFER(xfer)->curframe; 2776 maxlen = 0; 2777 for (i = 0; i < nframes; i++) { 2778 std = stds[n]; 2779 usb_syncmem(&std->dma, 2780 std->offs + offsetof(uhci_td_t, td_status), 2781 sizeof(std->td.td_status), 2782 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2783 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2784 usb_syncmem(&std->dma, 2785 std->offs + offsetof(uhci_td_t, td_status), 2786 sizeof(std->td.td_status), 2787 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2788 usb_syncmem(&std->dma, 2789 std->offs + offsetof(uhci_td_t, td_token), 2790 sizeof(std->td.td_token), 2791 BUS_DMASYNC_POSTWRITE); 2792 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2793 if (len > maxlen) 2794 maxlen = len; 2795 if (++n >= UHCI_VFRAMELIST_COUNT) 2796 n = 0; 2797 } 2798 2799 /* and wait until we are sure the hardware has finished. */ 2800 delay(maxlen); 2801 2802 #ifdef DIAGNOSTIC 2803 UXFER(xfer)->iinfo.isdone = 1; 2804 #endif 2805 /* Run callback and remove from interrupt list. */ 2806 usb_transfer_complete(xfer); 2807 2808 KASSERT(mutex_owned(&sc->sc_lock)); 2809 } 2810 2811 void 2812 uhci_device_isoc_close(usbd_pipe_handle pipe) 2813 { 2814 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2815 usbd_device_handle dev = upipe->pipe.device; 2816 uhci_softc_t *sc = dev->bus->hci_private; 2817 uhci_soft_td_t *std, *vstd; 2818 struct iso *iso; 2819 int i; 2820 2821 KASSERT(mutex_owned(&sc->sc_lock)); 2822 2823 /* 2824 * Make sure all TDs are marked as inactive. 2825 * Wait for completion. 2826 * Unschedule. 2827 * Deallocate. 2828 */ 2829 iso = &upipe->u.iso; 2830 2831 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2832 std = iso->stds[i]; 2833 usb_syncmem(&std->dma, 2834 std->offs + offsetof(uhci_td_t, td_status), 2835 sizeof(std->td.td_status), 2836 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2837 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2838 usb_syncmem(&std->dma, 2839 std->offs + offsetof(uhci_td_t, td_status), 2840 sizeof(std->td.td_status), 2841 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2842 } 2843 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2844 2845 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2846 std = iso->stds[i]; 2847 for (vstd = sc->sc_vframes[i].htd; 2848 vstd != NULL && vstd->link.std != std; 2849 vstd = vstd->link.std) 2850 ; 2851 if (vstd == NULL) { 2852 /*panic*/ 2853 printf("uhci_device_isoc_close: %p not found\n", std); 2854 mutex_exit(&sc->sc_lock); 2855 return; 2856 } 2857 vstd->link = std->link; 2858 usb_syncmem(&std->dma, 2859 std->offs + offsetof(uhci_td_t, td_link), 2860 sizeof(std->td.td_link), 2861 BUS_DMASYNC_POSTWRITE); 2862 vstd->td.td_link = std->td.td_link; 2863 usb_syncmem(&vstd->dma, 2864 vstd->offs + offsetof(uhci_td_t, td_link), 2865 sizeof(vstd->td.td_link), 2866 BUS_DMASYNC_PREWRITE); 2867 uhci_free_std(sc, std); 2868 } 2869 2870 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2871 } 2872 2873 usbd_status 2874 uhci_setup_isoc(usbd_pipe_handle pipe) 2875 { 2876 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2877 usbd_device_handle dev = upipe->pipe.device; 2878 uhci_softc_t *sc = dev->bus->hci_private; 2879 int addr = upipe->pipe.device->address; 2880 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2881 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2882 uhci_soft_td_t *std, *vstd; 2883 u_int32_t token; 2884 struct iso *iso; 2885 int i; 2886 2887 iso = &upipe->u.iso; 2888 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2889 sizeof (uhci_soft_td_t *), 2890 KM_SLEEP); 2891 if (iso->stds == NULL) 2892 return USBD_NOMEM; 2893 2894 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2895 UHCI_TD_OUT(0, endpt, addr, 0); 2896 2897 mutex_enter(&sc->sc_lock); 2898 2899 /* Allocate the TDs and mark as inactive; */ 2900 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2901 std = uhci_alloc_std(sc); 2902 if (std == 0) 2903 goto bad; 2904 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2905 std->td.td_token = htole32(token); 2906 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2907 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2908 iso->stds[i] = std; 2909 } 2910 2911 /* Insert TDs into schedule. */ 2912 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2913 std = iso->stds[i]; 2914 vstd = sc->sc_vframes[i].htd; 2915 usb_syncmem(&vstd->dma, 2916 vstd->offs + offsetof(uhci_td_t, td_link), 2917 sizeof(vstd->td.td_link), 2918 BUS_DMASYNC_POSTWRITE); 2919 std->link = vstd->link; 2920 std->td.td_link = vstd->td.td_link; 2921 usb_syncmem(&std->dma, 2922 std->offs + offsetof(uhci_td_t, td_link), 2923 sizeof(std->td.td_link), 2924 BUS_DMASYNC_PREWRITE); 2925 vstd->link.std = std; 2926 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2927 usb_syncmem(&vstd->dma, 2928 vstd->offs + offsetof(uhci_td_t, td_link), 2929 sizeof(vstd->td.td_link), 2930 BUS_DMASYNC_PREWRITE); 2931 } 2932 mutex_exit(&sc->sc_lock); 2933 2934 iso->next = -1; 2935 iso->inuse = 0; 2936 2937 return (USBD_NORMAL_COMPLETION); 2938 2939 bad: 2940 while (--i >= 0) 2941 uhci_free_std(sc, iso->stds[i]); 2942 mutex_exit(&sc->sc_lock); 2943 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2944 return (USBD_NOMEM); 2945 } 2946 2947 void 2948 uhci_device_isoc_done(usbd_xfer_handle xfer) 2949 { 2950 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2951 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2952 int i, offs; 2953 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2954 2955 2956 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2957 xfer->actlen, xfer->busy_free)); 2958 2959 if (ii->xfer != xfer) 2960 /* Not on interrupt list, ignore it. */ 2961 return; 2962 2963 if (!uhci_active_intr_info(ii)) 2964 return; 2965 2966 #ifdef DIAGNOSTIC 2967 if (ii->stdend == NULL) { 2968 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2969 #ifdef UHCI_DEBUG 2970 uhci_dump_ii(ii); 2971 #endif 2972 return; 2973 } 2974 #endif 2975 2976 /* Turn off the interrupt since it is active even if the TD is not. */ 2977 usb_syncmem(&ii->stdend->dma, 2978 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2979 sizeof(ii->stdend->td.td_status), 2980 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2981 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2982 usb_syncmem(&ii->stdend->dma, 2983 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2984 sizeof(ii->stdend->td.td_status), 2985 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2986 2987 uhci_del_intr_info(ii); /* remove from active list */ 2988 2989 offs = 0; 2990 for (i = 0; i < xfer->nframes; i++) { 2991 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2992 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2993 offs += xfer->frlengths[i]; 2994 } 2995 } 2996 2997 void 2998 uhci_device_intr_done(usbd_xfer_handle xfer) 2999 { 3000 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3001 uhci_softc_t *sc = ii->sc; 3002 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3003 uhci_soft_qh_t *sqh; 3004 int i, npoll, isread; 3005 3006 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3007 3008 KASSERT(mutex_owned(&sc->sc_lock)); 3009 3010 npoll = upipe->u.intr.npoll; 3011 for(i = 0; i < npoll; i++) { 3012 sqh = upipe->u.intr.qhs[i]; 3013 sqh->elink = NULL; 3014 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3015 usb_syncmem(&sqh->dma, 3016 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3017 sizeof(sqh->qh.qh_elink), 3018 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3019 } 3020 uhci_free_std_chain(sc, ii->stdstart, NULL); 3021 3022 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3023 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3024 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3025 3026 /* XXX Wasteful. */ 3027 if (xfer->pipe->repeat) { 3028 uhci_soft_td_t *data, *dataend; 3029 3030 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3031 3032 /* This alloc cannot fail since we freed the chain above. */ 3033 uhci_alloc_std_chain(upipe, sc, xfer->length, 3034 upipe->u.intr.isread, xfer->flags, 3035 &xfer->dmabuf, &data, &dataend); 3036 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3037 usb_syncmem(&dataend->dma, 3038 dataend->offs + offsetof(uhci_td_t, td_status), 3039 sizeof(dataend->td.td_status), 3040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3041 3042 #ifdef UHCI_DEBUG 3043 if (uhcidebug > 10) { 3044 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3045 uhci_dump_tds(data); 3046 uhci_dump_qh(upipe->u.intr.qhs[0]); 3047 } 3048 #endif 3049 3050 ii->stdstart = data; 3051 ii->stdend = dataend; 3052 #ifdef DIAGNOSTIC 3053 if (!ii->isdone) { 3054 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3055 } 3056 ii->isdone = 0; 3057 #endif 3058 for (i = 0; i < npoll; i++) { 3059 sqh = upipe->u.intr.qhs[i]; 3060 sqh->elink = data; 3061 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3062 usb_syncmem(&sqh->dma, 3063 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3064 sizeof(sqh->qh.qh_elink), 3065 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3066 } 3067 xfer->status = USBD_IN_PROGRESS; 3068 /* The ii is already on the examined list, just leave it. */ 3069 } else { 3070 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3071 if (uhci_active_intr_info(ii)) 3072 uhci_del_intr_info(ii); 3073 } 3074 } 3075 3076 /* Deallocate request data structures */ 3077 void 3078 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3079 { 3080 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3081 uhci_softc_t *sc = ii->sc; 3082 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3083 int len = UGETW(xfer->request.wLength); 3084 int isread = (xfer->request.bmRequestType & UT_READ); 3085 3086 KASSERT(mutex_owned(&sc->sc_lock)); 3087 3088 #ifdef DIAGNOSTIC 3089 if (!(xfer->rqflags & URQ_REQUEST)) 3090 panic("uhci_device_ctrl_done: not a request"); 3091 #endif 3092 3093 if (!uhci_active_intr_info(ii)) 3094 return; 3095 3096 uhci_del_intr_info(ii); /* remove from active list */ 3097 3098 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3099 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3100 else 3101 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3102 3103 if (upipe->u.ctl.length != 0) 3104 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3105 3106 if (len) { 3107 usb_syncmem(&xfer->dmabuf, 0, len, 3108 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3109 } 3110 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3111 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3112 3113 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3114 } 3115 3116 /* Deallocate request data structures */ 3117 void 3118 uhci_device_bulk_done(usbd_xfer_handle xfer) 3119 { 3120 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3121 uhci_softc_t *sc = ii->sc; 3122 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3123 3124 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3125 xfer, ii, sc, upipe)); 3126 3127 KASSERT(mutex_owned(&sc->sc_lock)); 3128 3129 if (!uhci_active_intr_info(ii)) 3130 return; 3131 3132 uhci_del_intr_info(ii); /* remove from active list */ 3133 3134 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3135 3136 uhci_free_std_chain(sc, ii->stdstart, NULL); 3137 3138 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3139 } 3140 3141 /* Add interrupt QH, called with vflock. */ 3142 void 3143 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3144 { 3145 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3146 uhci_soft_qh_t *eqh; 3147 3148 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3149 3150 eqh = vf->eqh; 3151 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3152 sizeof(eqh->qh.qh_hlink), 3153 BUS_DMASYNC_POSTWRITE); 3154 sqh->hlink = eqh->hlink; 3155 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3156 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3157 sizeof(sqh->qh.qh_hlink), 3158 BUS_DMASYNC_PREWRITE); 3159 eqh->hlink = sqh; 3160 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3161 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3162 sizeof(eqh->qh.qh_hlink), 3163 BUS_DMASYNC_PREWRITE); 3164 vf->eqh = sqh; 3165 vf->bandwidth++; 3166 } 3167 3168 /* Remove interrupt QH. */ 3169 void 3170 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3171 { 3172 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3173 uhci_soft_qh_t *pqh; 3174 3175 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3176 3177 /* See comment in uhci_remove_ctrl() */ 3178 3179 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3180 sizeof(sqh->qh.qh_elink), 3181 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3182 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3183 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3184 usb_syncmem(&sqh->dma, 3185 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3186 sizeof(sqh->qh.qh_elink), 3187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3188 delay(UHCI_QH_REMOVE_DELAY); 3189 } 3190 3191 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3192 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3193 sizeof(sqh->qh.qh_hlink), 3194 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3195 pqh->hlink = sqh->hlink; 3196 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3197 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3198 sizeof(pqh->qh.qh_hlink), 3199 BUS_DMASYNC_PREWRITE); 3200 delay(UHCI_QH_REMOVE_DELAY); 3201 if (vf->eqh == sqh) 3202 vf->eqh = pqh; 3203 vf->bandwidth--; 3204 } 3205 3206 usbd_status 3207 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3208 { 3209 uhci_soft_qh_t *sqh; 3210 int i, npoll; 3211 u_int bestbw, bw, bestoffs, offs; 3212 3213 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3214 if (ival == 0) { 3215 printf("uhci_device_setintr: 0 interval\n"); 3216 return (USBD_INVAL); 3217 } 3218 3219 if (ival > UHCI_VFRAMELIST_COUNT) 3220 ival = UHCI_VFRAMELIST_COUNT; 3221 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3222 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3223 3224 upipe->u.intr.npoll = npoll; 3225 upipe->u.intr.qhs = 3226 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3227 if (upipe->u.intr.qhs == NULL) 3228 return USBD_NOMEM; 3229 3230 /* 3231 * Figure out which offset in the schedule that has most 3232 * bandwidth left over. 3233 */ 3234 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3235 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3236 for (bw = i = 0; i < npoll; i++) 3237 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3238 if (bw < bestbw) { 3239 bestbw = bw; 3240 bestoffs = offs; 3241 } 3242 } 3243 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3244 3245 mutex_enter(&sc->sc_lock); 3246 for(i = 0; i < npoll; i++) { 3247 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3248 sqh->elink = NULL; 3249 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3250 usb_syncmem(&sqh->dma, 3251 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3252 sizeof(sqh->qh.qh_elink), 3253 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3254 sqh->pos = MOD(i * ival + bestoffs); 3255 } 3256 #undef MOD 3257 3258 /* Enter QHs into the controller data structures. */ 3259 for(i = 0; i < npoll; i++) 3260 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3261 mutex_exit(&sc->sc_lock); 3262 3263 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3264 return (USBD_NORMAL_COMPLETION); 3265 } 3266 3267 /* Open a new pipe. */ 3268 usbd_status 3269 uhci_open(usbd_pipe_handle pipe) 3270 { 3271 uhci_softc_t *sc = pipe->device->bus->hci_private; 3272 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3273 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3274 usbd_status err = USBD_NOMEM; 3275 int ival; 3276 3277 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3278 pipe, pipe->device->address, 3279 ed->bEndpointAddress, sc->sc_addr)); 3280 3281 if (sc->sc_dying) 3282 return USBD_IOERROR; 3283 3284 upipe->aborting = 0; 3285 /* toggle state needed for bulk endpoints */ 3286 upipe->nexttoggle = pipe->endpoint->datatoggle; 3287 3288 if (pipe->device->address == sc->sc_addr) { 3289 switch (ed->bEndpointAddress) { 3290 case USB_CONTROL_ENDPOINT: 3291 pipe->methods = &uhci_root_ctrl_methods; 3292 break; 3293 case UE_DIR_IN | UHCI_INTR_ENDPT: 3294 pipe->methods = &uhci_root_intr_methods; 3295 break; 3296 default: 3297 return (USBD_INVAL); 3298 } 3299 } else { 3300 switch (ed->bmAttributes & UE_XFERTYPE) { 3301 case UE_CONTROL: 3302 pipe->methods = &uhci_device_ctrl_methods; 3303 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3304 if (upipe->u.ctl.sqh == NULL) 3305 goto bad; 3306 upipe->u.ctl.setup = uhci_alloc_std(sc); 3307 if (upipe->u.ctl.setup == NULL) { 3308 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3309 goto bad; 3310 } 3311 upipe->u.ctl.stat = uhci_alloc_std(sc); 3312 if (upipe->u.ctl.stat == NULL) { 3313 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3314 uhci_free_std(sc, upipe->u.ctl.setup); 3315 goto bad; 3316 } 3317 err = usb_allocmem(&sc->sc_bus, 3318 sizeof(usb_device_request_t), 3319 0, &upipe->u.ctl.reqdma); 3320 if (err) { 3321 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3322 uhci_free_std(sc, upipe->u.ctl.setup); 3323 uhci_free_std(sc, upipe->u.ctl.stat); 3324 goto bad; 3325 } 3326 break; 3327 case UE_INTERRUPT: 3328 pipe->methods = &uhci_device_intr_methods; 3329 ival = pipe->interval; 3330 if (ival == USBD_DEFAULT_INTERVAL) 3331 ival = ed->bInterval; 3332 return (uhci_device_setintr(sc, upipe, ival)); 3333 case UE_ISOCHRONOUS: 3334 pipe->methods = &uhci_device_isoc_methods; 3335 return (uhci_setup_isoc(pipe)); 3336 case UE_BULK: 3337 pipe->methods = &uhci_device_bulk_methods; 3338 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3339 if (upipe->u.bulk.sqh == NULL) 3340 goto bad; 3341 break; 3342 } 3343 } 3344 return (USBD_NORMAL_COMPLETION); 3345 3346 bad: 3347 return USBD_NOMEM; 3348 } 3349 3350 /* 3351 * Data structures and routines to emulate the root hub. 3352 */ 3353 usb_device_descriptor_t uhci_devd = { 3354 USB_DEVICE_DESCRIPTOR_SIZE, 3355 UDESC_DEVICE, /* type */ 3356 {0x00, 0x01}, /* USB version */ 3357 UDCLASS_HUB, /* class */ 3358 UDSUBCLASS_HUB, /* subclass */ 3359 UDPROTO_FSHUB, /* protocol */ 3360 64, /* max packet */ 3361 {0},{0},{0x00,0x01}, /* device id */ 3362 1,2,0, /* string indicies */ 3363 1 /* # of configurations */ 3364 }; 3365 3366 const usb_config_descriptor_t uhci_confd = { 3367 USB_CONFIG_DESCRIPTOR_SIZE, 3368 UDESC_CONFIG, 3369 {USB_CONFIG_DESCRIPTOR_SIZE + 3370 USB_INTERFACE_DESCRIPTOR_SIZE + 3371 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3372 1, 3373 1, 3374 0, 3375 UC_ATTR_MBO | UC_SELF_POWERED, 3376 0 /* max power */ 3377 }; 3378 3379 const usb_interface_descriptor_t uhci_ifcd = { 3380 USB_INTERFACE_DESCRIPTOR_SIZE, 3381 UDESC_INTERFACE, 3382 0, 3383 0, 3384 1, 3385 UICLASS_HUB, 3386 UISUBCLASS_HUB, 3387 UIPROTO_FSHUB, 3388 0 3389 }; 3390 3391 const usb_endpoint_descriptor_t uhci_endpd = { 3392 USB_ENDPOINT_DESCRIPTOR_SIZE, 3393 UDESC_ENDPOINT, 3394 UE_DIR_IN | UHCI_INTR_ENDPT, 3395 UE_INTERRUPT, 3396 {8}, 3397 255 3398 }; 3399 3400 const usb_hub_descriptor_t uhci_hubd_piix = { 3401 USB_HUB_DESCRIPTOR_SIZE, 3402 UDESC_HUB, 3403 2, 3404 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3405 50, /* power on to power good */ 3406 0, 3407 { 0x00 }, /* both ports are removable */ 3408 { 0 }, 3409 }; 3410 3411 /* 3412 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3413 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3414 * should not be used by the USB subsystem. As we cannot issue a 3415 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3416 * will be enabled as part of the reset. 3417 * 3418 * On the VT83C572, the port cannot be successfully enabled until the 3419 * outstanding "port enable change" and "connection status change" 3420 * events have been reset. 3421 */ 3422 Static usbd_status 3423 uhci_portreset(uhci_softc_t *sc, int index) 3424 { 3425 int lim, port, x; 3426 3427 if (index == 1) 3428 port = UHCI_PORTSC1; 3429 else if (index == 2) 3430 port = UHCI_PORTSC2; 3431 else 3432 return (USBD_IOERROR); 3433 3434 x = URWMASK(UREAD2(sc, port)); 3435 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3436 3437 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3438 3439 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3440 index, UREAD2(sc, port))); 3441 3442 x = URWMASK(UREAD2(sc, port)); 3443 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3444 3445 delay(100); 3446 3447 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3448 index, UREAD2(sc, port))); 3449 3450 x = URWMASK(UREAD2(sc, port)); 3451 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3452 3453 for (lim = 10; --lim > 0;) { 3454 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3455 3456 x = UREAD2(sc, port); 3457 3458 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3459 index, lim, x)); 3460 3461 if (!(x & UHCI_PORTSC_CCS)) { 3462 /* 3463 * No device is connected (or was disconnected 3464 * during reset). Consider the port reset. 3465 * The delay must be long enough to ensure on 3466 * the initial iteration that the device 3467 * connection will have been registered. 50ms 3468 * appears to be sufficient, but 20ms is not. 3469 */ 3470 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3471 index, lim)); 3472 break; 3473 } 3474 3475 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3476 /* 3477 * Port enabled changed and/or connection 3478 * status changed were set. Reset either or 3479 * both raised flags (by writing a 1 to that 3480 * bit), and wait again for state to settle. 3481 */ 3482 UWRITE2(sc, port, URWMASK(x) | 3483 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3484 continue; 3485 } 3486 3487 if (x & UHCI_PORTSC_PE) 3488 /* Port is enabled */ 3489 break; 3490 3491 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3492 } 3493 3494 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3495 index, UREAD2(sc, port))); 3496 3497 if (lim <= 0) { 3498 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3499 return (USBD_TIMEOUT); 3500 } 3501 3502 sc->sc_isreset = 1; 3503 return (USBD_NORMAL_COMPLETION); 3504 } 3505 3506 /* 3507 * Simulate a hardware hub by handling all the necessary requests. 3508 */ 3509 usbd_status 3510 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3511 { 3512 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3513 usbd_status err; 3514 3515 /* Insert last in queue. */ 3516 mutex_enter(&sc->sc_lock); 3517 err = usb_insert_transfer(xfer); 3518 mutex_exit(&sc->sc_lock); 3519 if (err) 3520 return (err); 3521 3522 /* 3523 * Pipe isn't running (otherwise err would be USBD_INPROG), 3524 * so start it first. 3525 */ 3526 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3527 } 3528 3529 usbd_status 3530 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3531 { 3532 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3533 usb_device_request_t *req; 3534 void *buf = NULL; 3535 int port, x; 3536 int len, value, index, status, change, l, totlen = 0; 3537 usb_port_status_t ps; 3538 usbd_status err; 3539 3540 if (sc->sc_dying) 3541 return (USBD_IOERROR); 3542 3543 #ifdef DIAGNOSTIC 3544 if (!(xfer->rqflags & URQ_REQUEST)) 3545 panic("uhci_root_ctrl_transfer: not a request"); 3546 #endif 3547 req = &xfer->request; 3548 3549 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3550 req->bmRequestType, req->bRequest)); 3551 3552 len = UGETW(req->wLength); 3553 value = UGETW(req->wValue); 3554 index = UGETW(req->wIndex); 3555 3556 if (len != 0) 3557 buf = KERNADDR(&xfer->dmabuf, 0); 3558 3559 #define C(x,y) ((x) | ((y) << 8)) 3560 switch(C(req->bRequest, req->bmRequestType)) { 3561 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3562 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3563 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3564 /* 3565 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3566 * for the integrated root hub. 3567 */ 3568 break; 3569 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3570 if (len > 0) { 3571 *(u_int8_t *)buf = sc->sc_conf; 3572 totlen = 1; 3573 } 3574 break; 3575 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3576 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3577 if (len == 0) 3578 break; 3579 switch(value >> 8) { 3580 case UDESC_DEVICE: 3581 if ((value & 0xff) != 0) { 3582 err = USBD_IOERROR; 3583 goto ret; 3584 } 3585 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3586 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3587 memcpy(buf, &uhci_devd, l); 3588 break; 3589 case UDESC_CONFIG: 3590 if ((value & 0xff) != 0) { 3591 err = USBD_IOERROR; 3592 goto ret; 3593 } 3594 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3595 memcpy(buf, &uhci_confd, l); 3596 buf = (char *)buf + l; 3597 len -= l; 3598 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3599 totlen += l; 3600 memcpy(buf, &uhci_ifcd, l); 3601 buf = (char *)buf + l; 3602 len -= l; 3603 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3604 totlen += l; 3605 memcpy(buf, &uhci_endpd, l); 3606 break; 3607 case UDESC_STRING: 3608 #define sd ((usb_string_descriptor_t *)buf) 3609 switch (value & 0xff) { 3610 case 0: /* Language table */ 3611 totlen = usb_makelangtbl(sd, len); 3612 break; 3613 case 1: /* Vendor */ 3614 totlen = usb_makestrdesc(sd, len, 3615 sc->sc_vendor); 3616 break; 3617 case 2: /* Product */ 3618 totlen = usb_makestrdesc(sd, len, 3619 "UHCI root hub"); 3620 break; 3621 } 3622 #undef sd 3623 break; 3624 default: 3625 err = USBD_IOERROR; 3626 goto ret; 3627 } 3628 break; 3629 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3630 if (len > 0) { 3631 *(u_int8_t *)buf = 0; 3632 totlen = 1; 3633 } 3634 break; 3635 case C(UR_GET_STATUS, UT_READ_DEVICE): 3636 if (len > 1) { 3637 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3638 totlen = 2; 3639 } 3640 break; 3641 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3642 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3643 if (len > 1) { 3644 USETW(((usb_status_t *)buf)->wStatus, 0); 3645 totlen = 2; 3646 } 3647 break; 3648 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3649 if (value >= USB_MAX_DEVICES) { 3650 err = USBD_IOERROR; 3651 goto ret; 3652 } 3653 sc->sc_addr = value; 3654 break; 3655 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3656 if (value != 0 && value != 1) { 3657 err = USBD_IOERROR; 3658 goto ret; 3659 } 3660 sc->sc_conf = value; 3661 break; 3662 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3663 break; 3664 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3665 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3666 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3667 err = USBD_IOERROR; 3668 goto ret; 3669 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3670 break; 3671 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3672 break; 3673 /* Hub requests */ 3674 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3675 break; 3676 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3677 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3678 "port=%d feature=%d\n", 3679 index, value)); 3680 if (index == 1) 3681 port = UHCI_PORTSC1; 3682 else if (index == 2) 3683 port = UHCI_PORTSC2; 3684 else { 3685 err = USBD_IOERROR; 3686 goto ret; 3687 } 3688 switch(value) { 3689 case UHF_PORT_ENABLE: 3690 x = URWMASK(UREAD2(sc, port)); 3691 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3692 break; 3693 case UHF_PORT_SUSPEND: 3694 x = URWMASK(UREAD2(sc, port)); 3695 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3696 break; 3697 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3698 /* see USB2 spec ch. 7.1.7.7 */ 3699 usb_delay_ms(&sc->sc_bus, 20); 3700 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3701 /* 10ms resume delay must be provided by caller */ 3702 break; 3703 case UHF_PORT_RESET: 3704 x = URWMASK(UREAD2(sc, port)); 3705 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3706 break; 3707 case UHF_C_PORT_CONNECTION: 3708 x = URWMASK(UREAD2(sc, port)); 3709 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3710 break; 3711 case UHF_C_PORT_ENABLE: 3712 x = URWMASK(UREAD2(sc, port)); 3713 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3714 break; 3715 case UHF_C_PORT_OVER_CURRENT: 3716 x = URWMASK(UREAD2(sc, port)); 3717 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3718 break; 3719 case UHF_C_PORT_RESET: 3720 sc->sc_isreset = 0; 3721 err = USBD_NORMAL_COMPLETION; 3722 goto ret; 3723 case UHF_PORT_CONNECTION: 3724 case UHF_PORT_OVER_CURRENT: 3725 case UHF_PORT_POWER: 3726 case UHF_PORT_LOW_SPEED: 3727 case UHF_C_PORT_SUSPEND: 3728 default: 3729 err = USBD_IOERROR; 3730 goto ret; 3731 } 3732 break; 3733 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3734 if (index == 1) 3735 port = UHCI_PORTSC1; 3736 else if (index == 2) 3737 port = UHCI_PORTSC2; 3738 else { 3739 err = USBD_IOERROR; 3740 goto ret; 3741 } 3742 if (len > 0) { 3743 *(u_int8_t *)buf = 3744 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3745 UHCI_PORTSC_LS_SHIFT; 3746 totlen = 1; 3747 } 3748 break; 3749 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3750 if (len == 0) 3751 break; 3752 if ((value & 0xff) != 0) { 3753 err = USBD_IOERROR; 3754 goto ret; 3755 } 3756 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3757 totlen = l; 3758 memcpy(buf, &uhci_hubd_piix, l); 3759 break; 3760 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3761 if (len != 4) { 3762 err = USBD_IOERROR; 3763 goto ret; 3764 } 3765 memset(buf, 0, len); 3766 totlen = len; 3767 break; 3768 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3769 if (index == 1) 3770 port = UHCI_PORTSC1; 3771 else if (index == 2) 3772 port = UHCI_PORTSC2; 3773 else { 3774 err = USBD_IOERROR; 3775 goto ret; 3776 } 3777 if (len != 4) { 3778 err = USBD_IOERROR; 3779 goto ret; 3780 } 3781 x = UREAD2(sc, port); 3782 status = change = 0; 3783 if (x & UHCI_PORTSC_CCS) 3784 status |= UPS_CURRENT_CONNECT_STATUS; 3785 if (x & UHCI_PORTSC_CSC) 3786 change |= UPS_C_CONNECT_STATUS; 3787 if (x & UHCI_PORTSC_PE) 3788 status |= UPS_PORT_ENABLED; 3789 if (x & UHCI_PORTSC_POEDC) 3790 change |= UPS_C_PORT_ENABLED; 3791 if (x & UHCI_PORTSC_OCI) 3792 status |= UPS_OVERCURRENT_INDICATOR; 3793 if (x & UHCI_PORTSC_OCIC) 3794 change |= UPS_C_OVERCURRENT_INDICATOR; 3795 if (x & UHCI_PORTSC_SUSP) 3796 status |= UPS_SUSPEND; 3797 if (x & UHCI_PORTSC_LSDA) 3798 status |= UPS_LOW_SPEED; 3799 status |= UPS_PORT_POWER; 3800 if (sc->sc_isreset) 3801 change |= UPS_C_PORT_RESET; 3802 USETW(ps.wPortStatus, status); 3803 USETW(ps.wPortChange, change); 3804 l = min(len, sizeof ps); 3805 memcpy(buf, &ps, l); 3806 totlen = l; 3807 break; 3808 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3809 err = USBD_IOERROR; 3810 goto ret; 3811 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3812 break; 3813 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3814 if (index == 1) 3815 port = UHCI_PORTSC1; 3816 else if (index == 2) 3817 port = UHCI_PORTSC2; 3818 else { 3819 err = USBD_IOERROR; 3820 goto ret; 3821 } 3822 switch(value) { 3823 case UHF_PORT_ENABLE: 3824 x = URWMASK(UREAD2(sc, port)); 3825 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3826 break; 3827 case UHF_PORT_SUSPEND: 3828 x = URWMASK(UREAD2(sc, port)); 3829 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3830 break; 3831 case UHF_PORT_RESET: 3832 err = uhci_portreset(sc, index); 3833 goto ret; 3834 case UHF_PORT_POWER: 3835 /* Pretend we turned on power */ 3836 err = USBD_NORMAL_COMPLETION; 3837 goto ret; 3838 case UHF_C_PORT_CONNECTION: 3839 case UHF_C_PORT_ENABLE: 3840 case UHF_C_PORT_OVER_CURRENT: 3841 case UHF_PORT_CONNECTION: 3842 case UHF_PORT_OVER_CURRENT: 3843 case UHF_PORT_LOW_SPEED: 3844 case UHF_C_PORT_SUSPEND: 3845 case UHF_C_PORT_RESET: 3846 default: 3847 err = USBD_IOERROR; 3848 goto ret; 3849 } 3850 break; 3851 default: 3852 err = USBD_IOERROR; 3853 goto ret; 3854 } 3855 xfer->actlen = totlen; 3856 err = USBD_NORMAL_COMPLETION; 3857 ret: 3858 xfer->status = err; 3859 mutex_enter(&sc->sc_lock); 3860 usb_transfer_complete(xfer); 3861 mutex_exit(&sc->sc_lock); 3862 return (USBD_IN_PROGRESS); 3863 } 3864 3865 /* Abort a root control request. */ 3866 void 3867 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3868 { 3869 /* Nothing to do, all transfers are synchronous. */ 3870 } 3871 3872 /* Close the root pipe. */ 3873 void 3874 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3875 { 3876 DPRINTF(("uhci_root_ctrl_close\n")); 3877 } 3878 3879 /* Abort a root interrupt request. */ 3880 void 3881 uhci_root_intr_abort(usbd_xfer_handle xfer) 3882 { 3883 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3884 3885 KASSERT(mutex_owned(&sc->sc_lock)); 3886 3887 callout_stop(&sc->sc_poll_handle); 3888 sc->sc_intr_xfer = NULL; 3889 3890 if (xfer->pipe->intrxfer == xfer) { 3891 DPRINTF(("uhci_root_intr_abort: remove\n")); 3892 xfer->pipe->intrxfer = 0; 3893 } 3894 xfer->status = USBD_CANCELLED; 3895 #ifdef DIAGNOSTIC 3896 UXFER(xfer)->iinfo.isdone = 1; 3897 #endif 3898 usb_transfer_complete(xfer); 3899 } 3900 3901 usbd_status 3902 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3903 { 3904 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3905 usbd_status err; 3906 3907 /* Insert last in queue. */ 3908 mutex_enter(&sc->sc_lock); 3909 err = usb_insert_transfer(xfer); 3910 mutex_exit(&sc->sc_lock); 3911 if (err) 3912 return (err); 3913 3914 /* 3915 * Pipe isn't running (otherwise err would be USBD_INPROG), 3916 * start first 3917 */ 3918 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3919 } 3920 3921 /* Start a transfer on the root interrupt pipe */ 3922 usbd_status 3923 uhci_root_intr_start(usbd_xfer_handle xfer) 3924 { 3925 usbd_pipe_handle pipe = xfer->pipe; 3926 uhci_softc_t *sc = pipe->device->bus->hci_private; 3927 unsigned int ival; 3928 3929 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3930 xfer, xfer->length, xfer->flags)); 3931 3932 if (sc->sc_dying) 3933 return (USBD_IOERROR); 3934 3935 /* XXX temporary variable needed to avoid gcc3 warning */ 3936 ival = xfer->pipe->endpoint->edesc->bInterval; 3937 sc->sc_ival = mstohz(ival); 3938 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3939 sc->sc_intr_xfer = xfer; 3940 return (USBD_IN_PROGRESS); 3941 } 3942 3943 /* Close the root interrupt pipe. */ 3944 void 3945 uhci_root_intr_close(usbd_pipe_handle pipe) 3946 { 3947 uhci_softc_t *sc = pipe->device->bus->hci_private; 3948 3949 KASSERT(mutex_owned(&sc->sc_lock)); 3950 3951 callout_stop(&sc->sc_poll_handle); 3952 sc->sc_intr_xfer = NULL; 3953 DPRINTF(("uhci_root_intr_close\n")); 3954 } 3955
Indexes created Tue Sep 30 17:09:57 GMT 2025