uhci.c revision 1.242
1 /* $NetBSD: uhci.c,v 1.242 2011/12/23 00:51:46 jakllsch Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.242 2011/12/23 00:51:46 jakllsch Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/select.h> 55 #include <sys/extent.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/bus.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/uhcireg.h> 69 #include <dev/usb/uhcivar.h> 70 #include <dev/usb/usbroothub_subr.h> 71 72 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 73 /*#define UHCI_CTL_LOOP */ 74 75 76 77 #ifdef UHCI_DEBUG 78 uhci_softc_t *thesc; 79 #define DPRINTF(x) if (uhcidebug) printf x 80 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 81 int uhcidebug = 0; 82 int uhcinoloop = 0; 83 #else 84 #define DPRINTF(x) 85 #define DPRINTFN(n,x) 86 #endif 87 88 /* 89 * The UHCI controller is little endian, so on big endian machines 90 * the data stored in memory needs to be swapped. 91 */ 92 93 struct uhci_pipe { 94 struct usbd_pipe pipe; 95 int nexttoggle; 96 97 u_char aborting; 98 usbd_xfer_handle abortstart, abortend; 99 100 /* Info needed for different pipe kinds. */ 101 union { 102 /* Control pipe */ 103 struct { 104 uhci_soft_qh_t *sqh; 105 usb_dma_t reqdma; 106 uhci_soft_td_t *setup, *stat; 107 u_int length; 108 } ctl; 109 /* Interrupt pipe */ 110 struct { 111 int npoll; 112 int isread; 113 uhci_soft_qh_t **qhs; 114 } intr; 115 /* Bulk pipe */ 116 struct { 117 uhci_soft_qh_t *sqh; 118 u_int length; 119 int isread; 120 } bulk; 121 /* Iso pipe */ 122 struct iso { 123 uhci_soft_td_t **stds; 124 int next, inuse; 125 } iso; 126 } u; 127 }; 128 129 Static void uhci_globalreset(uhci_softc_t *); 130 Static usbd_status uhci_portreset(uhci_softc_t*, int); 131 Static void uhci_reset(uhci_softc_t *); 132 Static usbd_status uhci_run(uhci_softc_t *, int run); 133 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 134 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 135 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 136 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 137 #if 0 138 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 139 uhci_intr_info_t *); 140 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 141 #endif 142 143 Static void uhci_free_std_chain(uhci_softc_t *, 144 uhci_soft_td_t *, uhci_soft_td_t *); 145 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 146 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 147 uhci_soft_td_t **, uhci_soft_td_t **); 148 Static void uhci_poll_hub(void *); 149 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 150 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 151 Static void uhci_idone(uhci_intr_info_t *); 152 153 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 154 155 Static void uhci_timeout(void *); 156 Static void uhci_timeout_task(void *); 157 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 160 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 163 Static void uhci_add_loop(uhci_softc_t *sc); 164 Static void uhci_rem_loop(uhci_softc_t *sc); 165 166 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 167 Static void uhci_device_isoc_enter(usbd_xfer_handle); 168 169 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 170 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 171 172 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 173 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 static __inline uint32_t 267 UREAD4(uhci_softc_t *sc, bus_size_t r) 268 { 269 270 UBARR(sc); 271 return bus_space_read_4(sc->iot, sc->ioh, r); 272 } 273 274 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 275 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 276 277 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 278 279 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 280 281 #define UHCI_INTR_ENDPT 1 282 283 const struct usbd_bus_methods uhci_bus_methods = { 284 uhci_open, 285 uhci_softintr, 286 uhci_poll, 287 uhci_allocm, 288 uhci_freem, 289 uhci_allocx, 290 uhci_freex, 291 }; 292 293 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 294 uhci_root_ctrl_transfer, 295 uhci_root_ctrl_start, 296 uhci_root_ctrl_abort, 297 uhci_root_ctrl_close, 298 uhci_noop, 299 uhci_root_ctrl_done, 300 }; 301 302 const struct usbd_pipe_methods uhci_root_intr_methods = { 303 uhci_root_intr_transfer, 304 uhci_root_intr_start, 305 uhci_root_intr_abort, 306 uhci_root_intr_close, 307 uhci_noop, 308 uhci_root_intr_done, 309 }; 310 311 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 312 uhci_device_ctrl_transfer, 313 uhci_device_ctrl_start, 314 uhci_device_ctrl_abort, 315 uhci_device_ctrl_close, 316 uhci_noop, 317 uhci_device_ctrl_done, 318 }; 319 320 const struct usbd_pipe_methods uhci_device_intr_methods = { 321 uhci_device_intr_transfer, 322 uhci_device_intr_start, 323 uhci_device_intr_abort, 324 uhci_device_intr_close, 325 uhci_device_clear_toggle, 326 uhci_device_intr_done, 327 }; 328 329 const struct usbd_pipe_methods uhci_device_bulk_methods = { 330 uhci_device_bulk_transfer, 331 uhci_device_bulk_start, 332 uhci_device_bulk_abort, 333 uhci_device_bulk_close, 334 uhci_device_clear_toggle, 335 uhci_device_bulk_done, 336 }; 337 338 const struct usbd_pipe_methods uhci_device_isoc_methods = { 339 uhci_device_isoc_transfer, 340 uhci_device_isoc_start, 341 uhci_device_isoc_abort, 342 uhci_device_isoc_close, 343 uhci_noop, 344 uhci_device_isoc_done, 345 }; 346 347 #define uhci_add_intr_info(sc, ii) \ 348 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 349 #define uhci_del_intr_info(ii) \ 350 do { \ 351 LIST_REMOVE((ii), list); \ 352 (ii)->list.le_prev = NULL; \ 353 } while (0) 354 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 355 356 static inline uhci_soft_qh_t * 357 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 358 { 359 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 360 361 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 362 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 363 usb_syncmem(&pqh->dma, 364 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 365 sizeof(pqh->qh.qh_hlink), 366 BUS_DMASYNC_POSTWRITE); 367 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 368 printf("uhci_find_prev_qh: QH not found\n"); 369 return (NULL); 370 } 371 #endif 372 } 373 return (pqh); 374 } 375 376 void 377 uhci_globalreset(uhci_softc_t *sc) 378 { 379 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 380 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 381 UHCICMD(sc, 0); /* do nothing */ 382 } 383 384 usbd_status 385 uhci_init(uhci_softc_t *sc) 386 { 387 usbd_status err; 388 int i, j; 389 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 390 uhci_soft_td_t *std; 391 392 DPRINTFN(1,("uhci_init: start\n")); 393 394 #ifdef UHCI_DEBUG 395 thesc = sc; 396 397 if (uhcidebug > 2) 398 uhci_dumpregs(sc); 399 #endif 400 401 sc->sc_suspend = PWR_RESUME; 402 403 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 404 uhci_globalreset(sc); /* reset the controller */ 405 uhci_reset(sc); 406 407 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 408 USB_MEM_RESERVE); 409 410 /* Allocate and initialize real frame array. */ 411 err = usb_allocmem(&sc->sc_bus, 412 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 413 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 414 if (err) 415 return (err); 416 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 417 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 418 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 419 420 /* 421 * Allocate a TD, inactive, that hangs from the last QH. 422 * This is to avoid a bug in the PIIX that makes it run berserk 423 * otherwise. 424 */ 425 std = uhci_alloc_std(sc); 426 if (std == NULL) 427 return (USBD_NOMEM); 428 std->link.std = NULL; 429 std->td.td_link = htole32(UHCI_PTR_T); 430 std->td.td_status = htole32(0); /* inactive */ 431 std->td.td_token = htole32(0); 432 std->td.td_buffer = htole32(0); 433 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 434 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 435 436 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 437 lsqh = uhci_alloc_sqh(sc); 438 if (lsqh == NULL) 439 return (USBD_NOMEM); 440 lsqh->hlink = NULL; 441 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 442 lsqh->elink = std; 443 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 444 sc->sc_last_qh = lsqh; 445 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 446 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 447 448 /* Allocate the dummy QH where bulk traffic will be queued. */ 449 bsqh = uhci_alloc_sqh(sc); 450 if (bsqh == NULL) 451 return (USBD_NOMEM); 452 bsqh->hlink = lsqh; 453 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 454 bsqh->elink = NULL; 455 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 456 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 457 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 459 460 /* Allocate dummy QH where high speed control traffic will be queued. */ 461 chsqh = uhci_alloc_sqh(sc); 462 if (chsqh == NULL) 463 return (USBD_NOMEM); 464 chsqh->hlink = bsqh; 465 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 466 chsqh->elink = NULL; 467 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 468 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 469 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 470 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 471 472 /* Allocate dummy QH where control traffic will be queued. */ 473 clsqh = uhci_alloc_sqh(sc); 474 if (clsqh == NULL) 475 return (USBD_NOMEM); 476 clsqh->hlink = chsqh; 477 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 478 clsqh->elink = NULL; 479 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 480 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 481 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 483 484 /* 485 * Make all (virtual) frame list pointers point to the interrupt 486 * queue heads and the interrupt queue heads at the control 487 * queue head and point the physical frame list to the virtual. 488 */ 489 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 490 std = uhci_alloc_std(sc); 491 sqh = uhci_alloc_sqh(sc); 492 if (std == NULL || sqh == NULL) 493 return (USBD_NOMEM); 494 std->link.sqh = sqh; 495 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 496 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 497 std->td.td_token = htole32(0); 498 std->td.td_buffer = htole32(0); 499 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 500 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 501 sqh->hlink = clsqh; 502 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 503 sqh->elink = NULL; 504 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 sc->sc_vframes[i].htd = std; 508 sc->sc_vframes[i].etd = std; 509 sc->sc_vframes[i].hqh = sqh; 510 sc->sc_vframes[i].eqh = sqh; 511 for (j = i; 512 j < UHCI_FRAMELIST_COUNT; 513 j += UHCI_VFRAMELIST_COUNT) 514 sc->sc_pframes[j] = htole32(std->physaddr); 515 } 516 usb_syncmem(&sc->sc_dma, 0, 517 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 518 BUS_DMASYNC_PREWRITE); 519 520 521 LIST_INIT(&sc->sc_intrhead); 522 523 SIMPLEQ_INIT(&sc->sc_free_xfers); 524 525 callout_init(&sc->sc_poll_handle, 0); 526 527 /* Set up the bus struct. */ 528 sc->sc_bus.methods = &uhci_bus_methods; 529 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 530 531 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 532 533 DPRINTFN(1,("uhci_init: enabling\n")); 534 535 err = uhci_run(sc, 1); /* and here we go... */ 536 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 537 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 538 return err; 539 } 540 541 int 542 uhci_activate(device_t self, enum devact act) 543 { 544 struct uhci_softc *sc = device_private(self); 545 546 switch (act) { 547 case DVACT_DEACTIVATE: 548 sc->sc_dying = 1; 549 return 0; 550 default: 551 return EOPNOTSUPP; 552 } 553 } 554 555 void 556 uhci_childdet(device_t self, device_t child) 557 { 558 struct uhci_softc *sc = device_private(self); 559 560 KASSERT(sc->sc_child == child); 561 sc->sc_child = NULL; 562 } 563 564 int 565 uhci_detach(struct uhci_softc *sc, int flags) 566 { 567 usbd_xfer_handle xfer; 568 int rv = 0; 569 570 if (sc->sc_child != NULL) 571 rv = config_detach(sc->sc_child, flags); 572 573 if (rv != 0) 574 return (rv); 575 576 /* Free all xfers associated with this HC. */ 577 for (;;) { 578 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 579 if (xfer == NULL) 580 break; 581 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 582 free(xfer, M_USB); 583 } 584 585 callout_halt(&sc->sc_poll_handle, NULL); 586 callout_destroy(&sc->sc_poll_handle); 587 588 /* XXX free other data structures XXX */ 589 590 return (rv); 591 } 592 593 usbd_status 594 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 595 { 596 struct uhci_softc *sc = bus->hci_private; 597 usbd_status status; 598 u_int32_t n; 599 600 /* 601 * XXX 602 * Since we are allocating a buffer we can assume that we will 603 * need TDs for it. Since we don't want to allocate those from 604 * an interrupt context, we allocate them here and free them again. 605 * This is no guarantee that we'll get the TDs next time... 606 */ 607 n = size / 8; 608 if (n > 16) { 609 u_int32_t i; 610 uhci_soft_td_t **stds; 611 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 612 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP, 613 M_WAITOK|M_ZERO); 614 for(i=0; i < n; i++) 615 stds[i] = uhci_alloc_std(sc); 616 for(i=0; i < n; i++) 617 if (stds[i] != NULL) 618 uhci_free_std(sc, stds[i]); 619 free(stds, M_TEMP); 620 } 621 622 623 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 624 if (status == USBD_NOMEM) 625 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 626 return status; 627 } 628 629 void 630 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 631 { 632 if (dma->block->flags & USB_DMA_RESERVE) { 633 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 634 dma); 635 return; 636 } 637 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 638 } 639 640 usbd_xfer_handle 641 uhci_allocx(struct usbd_bus *bus) 642 { 643 struct uhci_softc *sc = bus->hci_private; 644 usbd_xfer_handle xfer; 645 646 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 647 if (xfer != NULL) { 648 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 649 #ifdef DIAGNOSTIC 650 if (xfer->busy_free != XFER_FREE) { 651 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 652 xfer->busy_free); 653 } 654 #endif 655 } else { 656 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT); 657 } 658 if (xfer != NULL) { 659 memset(xfer, 0, sizeof (struct uhci_xfer)); 660 UXFER(xfer)->iinfo.sc = sc; 661 #ifdef DIAGNOSTIC 662 UXFER(xfer)->iinfo.isdone = 1; 663 xfer->busy_free = XFER_BUSY; 664 #endif 665 } 666 return (xfer); 667 } 668 669 void 670 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 671 { 672 struct uhci_softc *sc = bus->hci_private; 673 674 #ifdef DIAGNOSTIC 675 if (xfer->busy_free != XFER_BUSY) { 676 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 677 xfer->busy_free); 678 } 679 xfer->busy_free = XFER_FREE; 680 if (!UXFER(xfer)->iinfo.isdone) { 681 printf("uhci_freex: !isdone\n"); 682 } 683 #endif 684 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 685 } 686 687 /* 688 * Handle suspend/resume. 689 * 690 * We need to switch to polling mode here, because this routine is 691 * called from an interrupt context. This is all right since we 692 * are almost suspended anyway. 693 */ 694 bool 695 uhci_resume(device_t dv, const pmf_qual_t *qual) 696 { 697 uhci_softc_t *sc = device_private(dv); 698 int cmd; 699 int s; 700 701 s = splhardusb(); 702 703 cmd = UREAD2(sc, UHCI_CMD); 704 sc->sc_bus.use_polling++; 705 UWRITE2(sc, UHCI_INTR, 0); 706 uhci_globalreset(sc); 707 uhci_reset(sc); 708 if (cmd & UHCI_CMD_RS) 709 uhci_run(sc, 0); 710 711 /* restore saved state */ 712 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 713 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 714 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 715 716 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 717 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 718 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 719 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 720 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 721 UHCICMD(sc, UHCI_CMD_MAXP); 722 uhci_run(sc, 1); /* and start traffic again */ 723 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 724 sc->sc_bus.use_polling--; 725 if (sc->sc_intr_xfer != NULL) 726 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 727 sc->sc_intr_xfer); 728 #ifdef UHCI_DEBUG 729 if (uhcidebug > 2) 730 uhci_dumpregs(sc); 731 #endif 732 733 sc->sc_suspend = PWR_RESUME; 734 splx(s); 735 736 return true; 737 } 738 739 bool 740 uhci_suspend(device_t dv, const pmf_qual_t *qual) 741 { 742 uhci_softc_t *sc = device_private(dv); 743 int cmd; 744 int s; 745 746 s = splhardusb(); 747 748 cmd = UREAD2(sc, UHCI_CMD); 749 750 #ifdef UHCI_DEBUG 751 if (uhcidebug > 2) 752 uhci_dumpregs(sc); 753 #endif 754 if (sc->sc_intr_xfer != NULL) 755 callout_stop(&sc->sc_poll_handle); 756 sc->sc_suspend = PWR_SUSPEND; 757 sc->sc_bus.use_polling++; 758 759 uhci_run(sc, 0); /* stop the controller */ 760 cmd &= ~UHCI_CMD_RS; 761 762 /* save some state if BIOS doesn't */ 763 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 764 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 765 766 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 767 768 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 769 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 770 sc->sc_bus.use_polling--; 771 772 splx(s); 773 774 return true; 775 } 776 777 #ifdef UHCI_DEBUG 778 Static void 779 uhci_dumpregs(uhci_softc_t *sc) 780 { 781 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 782 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 783 device_xname(sc->sc_dev), 784 UREAD2(sc, UHCI_CMD), 785 UREAD2(sc, UHCI_STS), 786 UREAD2(sc, UHCI_INTR), 787 UREAD2(sc, UHCI_FRNUM), 788 UREAD4(sc, UHCI_FLBASEADDR), 789 UREAD1(sc, UHCI_SOF), 790 UREAD2(sc, UHCI_PORTSC1), 791 UREAD2(sc, UHCI_PORTSC2))); 792 } 793 794 void 795 uhci_dump_td(uhci_soft_td_t *p) 796 { 797 char sbuf[128], sbuf2[128]; 798 799 800 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 801 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 802 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 803 "token=0x%08lx buffer=0x%08lx\n", 804 p, (long)p->physaddr, 805 (long)le32toh(p->td.td_link), 806 (long)le32toh(p->td.td_status), 807 (long)le32toh(p->td.td_token), 808 (long)le32toh(p->td.td_buffer))); 809 810 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 811 (u_int32_t)le32toh(p->td.td_link)); 812 snprintb(sbuf2, sizeof(sbuf2), 813 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 814 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 815 (u_int32_t)le32toh(p->td.td_status)); 816 817 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 818 "D=%d,maxlen=%d\n", sbuf, sbuf2, 819 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 820 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 821 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 822 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 823 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 824 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 825 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 826 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 827 BUS_DMASYNC_PREREAD); 828 } 829 830 void 831 uhci_dump_qh(uhci_soft_qh_t *sqh) 832 { 833 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 834 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 835 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 836 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 837 le32toh(sqh->qh.qh_elink))); 838 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 839 } 840 841 842 #if 1 843 void 844 uhci_dump(void) 845 { 846 uhci_dump_all(thesc); 847 } 848 #endif 849 850 void 851 uhci_dump_all(uhci_softc_t *sc) 852 { 853 uhci_dumpregs(sc); 854 printf("intrs=%d\n", sc->sc_bus.no_intrs); 855 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 856 uhci_dump_qh(sc->sc_lctl_start); 857 } 858 859 860 void 861 uhci_dump_qhs(uhci_soft_qh_t *sqh) 862 { 863 uhci_dump_qh(sqh); 864 865 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 866 * Traverses sideways first, then down. 867 * 868 * QH1 869 * QH2 870 * No QH 871 * TD2.1 872 * TD2.2 873 * TD1.1 874 * etc. 875 * 876 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 877 */ 878 879 880 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 881 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 882 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 883 uhci_dump_qhs(sqh->hlink); 884 else 885 DPRINTF(("No QH\n")); 886 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 887 888 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 889 uhci_dump_tds(sqh->elink); 890 else 891 DPRINTF(("No TD\n")); 892 } 893 894 void 895 uhci_dump_tds(uhci_soft_td_t *std) 896 { 897 uhci_soft_td_t *td; 898 int stop; 899 900 for(td = std; td != NULL; td = td->link.std) { 901 uhci_dump_td(td); 902 903 /* Check whether the link pointer in this TD marks 904 * the link pointer as end of queue. This avoids 905 * printing the free list in case the queue/TD has 906 * already been moved there (seatbelt). 907 */ 908 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 909 sizeof(td->td.td_link), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 912 le32toh(td->td.td_link) == 0); 913 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 914 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 915 if (stop) 916 break; 917 } 918 } 919 920 Static void 921 uhci_dump_ii(uhci_intr_info_t *ii) 922 { 923 usbd_pipe_handle pipe; 924 usb_endpoint_descriptor_t *ed; 925 usbd_device_handle dev; 926 927 #ifdef DIAGNOSTIC 928 #define DONE ii->isdone 929 #else 930 #define DONE 0 931 #endif 932 if (ii == NULL) { 933 printf("ii NULL\n"); 934 return; 935 } 936 if (ii->xfer == NULL) { 937 printf("ii %p: done=%d xfer=NULL\n", 938 ii, DONE); 939 return; 940 } 941 pipe = ii->xfer->pipe; 942 if (pipe == NULL) { 943 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 944 ii, DONE, ii->xfer); 945 return; 946 } 947 if (pipe->endpoint == NULL) { 948 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 949 ii, DONE, ii->xfer, pipe); 950 return; 951 } 952 if (pipe->device == NULL) { 953 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 954 ii, DONE, ii->xfer, pipe); 955 return; 956 } 957 ed = pipe->endpoint->edesc; 958 dev = pipe->device; 959 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 960 ii, DONE, ii->xfer, dev, 961 UGETW(dev->ddesc.idVendor), 962 UGETW(dev->ddesc.idProduct), 963 dev->address, pipe, 964 ed->bEndpointAddress, ed->bmAttributes); 965 #undef DONE 966 } 967 968 void uhci_dump_iis(struct uhci_softc *sc); 969 void 970 uhci_dump_iis(struct uhci_softc *sc) 971 { 972 uhci_intr_info_t *ii; 973 974 printf("intr_info list:\n"); 975 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 976 uhci_dump_ii(ii); 977 } 978 979 void iidump(void); 980 void iidump(void) { uhci_dump_iis(thesc); } 981 982 #endif 983 984 /* 985 * This routine is executed periodically and simulates interrupts 986 * from the root controller interrupt pipe for port status change. 987 */ 988 void 989 uhci_poll_hub(void *addr) 990 { 991 usbd_xfer_handle xfer = addr; 992 usbd_pipe_handle pipe = xfer->pipe; 993 uhci_softc_t *sc; 994 int s; 995 u_char *p; 996 997 DPRINTFN(20, ("uhci_poll_hub\n")); 998 999 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1000 return; /* device has detached */ 1001 sc = pipe->device->bus->hci_private; 1002 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1003 1004 p = KERNADDR(&xfer->dmabuf, 0); 1005 p[0] = 0; 1006 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<1; 1008 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<2; 1010 if (p[0] == 0) 1011 /* No change, try again in a while */ 1012 return; 1013 1014 xfer->actlen = 1; 1015 xfer->status = USBD_NORMAL_COMPLETION; 1016 s = splusb(); 1017 xfer->device->bus->intr_context++; 1018 usb_transfer_complete(xfer); 1019 xfer->device->bus->intr_context--; 1020 splx(s); 1021 } 1022 1023 void 1024 uhci_root_intr_done(usbd_xfer_handle xfer) 1025 { 1026 } 1027 1028 void 1029 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1030 { 1031 } 1032 1033 /* 1034 * Let the last QH loop back to the high speed control transfer QH. 1035 * This is what intel calls "bandwidth reclamation" and improves 1036 * USB performance a lot for some devices. 1037 * If we are already looping, just count it. 1038 */ 1039 void 1040 uhci_add_loop(uhci_softc_t *sc) { 1041 #ifdef UHCI_DEBUG 1042 if (uhcinoloop) 1043 return; 1044 #endif 1045 if (++sc->sc_loops == 1) { 1046 DPRINTFN(5,("uhci_start_loop: add\n")); 1047 /* Note, we don't loop back the soft pointer. */ 1048 sc->sc_last_qh->qh.qh_hlink = 1049 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1050 usb_syncmem(&sc->sc_last_qh->dma, 1051 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1052 sizeof(sc->sc_last_qh->qh.qh_hlink), 1053 BUS_DMASYNC_PREWRITE); 1054 } 1055 } 1056 1057 void 1058 uhci_rem_loop(uhci_softc_t *sc) { 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (--sc->sc_loops == 0) { 1064 DPRINTFN(5,("uhci_end_loop: remove\n")); 1065 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1066 usb_syncmem(&sc->sc_last_qh->dma, 1067 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1068 sizeof(sc->sc_last_qh->qh.qh_hlink), 1069 BUS_DMASYNC_PREWRITE); 1070 } 1071 } 1072 1073 /* Add high speed control QH, called at splusb(). */ 1074 void 1075 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1076 { 1077 uhci_soft_qh_t *eqh; 1078 1079 SPLUSBCHECK; 1080 1081 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1082 eqh = sc->sc_hctl_end; 1083 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1084 sizeof(eqh->qh.qh_hlink), 1085 BUS_DMASYNC_POSTWRITE); 1086 sqh->hlink = eqh->hlink; 1087 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1088 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1089 BUS_DMASYNC_PREWRITE); 1090 eqh->hlink = sqh; 1091 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1092 sc->sc_hctl_end = sqh; 1093 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1094 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1095 #ifdef UHCI_CTL_LOOP 1096 uhci_add_loop(sc); 1097 #endif 1098 } 1099 1100 /* Remove high speed control QH, called at splusb(). */ 1101 void 1102 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1103 { 1104 uhci_soft_qh_t *pqh; 1105 1106 SPLUSBCHECK; 1107 1108 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1109 #ifdef UHCI_CTL_LOOP 1110 uhci_rem_loop(sc); 1111 #endif 1112 /* 1113 * The T bit should be set in the elink of the QH so that the HC 1114 * doesn't follow the pointer. This condition may fail if the 1115 * the transferred packet was short so that the QH still points 1116 * at the last used TD. 1117 * In this case we set the T bit and wait a little for the HC 1118 * to stop looking at the TD. 1119 * Note that if the TD chain is large enough, the controller 1120 * may still be looking at the chain at the end of this function. 1121 * uhci_free_std_chain() will make sure the controller stops 1122 * looking at it quickly, but until then we should not change 1123 * sqh->hlink. 1124 */ 1125 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1126 sizeof(sqh->qh.qh_elink), 1127 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1128 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1129 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1130 usb_syncmem(&sqh->dma, 1131 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1132 sizeof(sqh->qh.qh_elink), 1133 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1134 delay(UHCI_QH_REMOVE_DELAY); 1135 } 1136 1137 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1138 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1139 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1140 pqh->hlink = sqh->hlink; 1141 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1142 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1143 sizeof(pqh->qh.qh_hlink), 1144 BUS_DMASYNC_PREWRITE); 1145 delay(UHCI_QH_REMOVE_DELAY); 1146 if (sc->sc_hctl_end == sqh) 1147 sc->sc_hctl_end = pqh; 1148 } 1149 1150 /* Add low speed control QH, called at splusb(). */ 1151 void 1152 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1153 { 1154 uhci_soft_qh_t *eqh; 1155 1156 SPLUSBCHECK; 1157 1158 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1159 eqh = sc->sc_lctl_end; 1160 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1161 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1162 sqh->hlink = eqh->hlink; 1163 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1164 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1165 BUS_DMASYNC_PREWRITE); 1166 eqh->hlink = sqh; 1167 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1168 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1169 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1170 sc->sc_lctl_end = sqh; 1171 } 1172 1173 /* Remove low speed control QH, called at splusb(). */ 1174 void 1175 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1176 { 1177 uhci_soft_qh_t *pqh; 1178 1179 SPLUSBCHECK; 1180 1181 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1182 /* See comment in uhci_remove_hs_ctrl() */ 1183 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1184 sizeof(sqh->qh.qh_elink), 1185 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1186 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1187 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1188 usb_syncmem(&sqh->dma, 1189 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1190 sizeof(sqh->qh.qh_elink), 1191 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1192 delay(UHCI_QH_REMOVE_DELAY); 1193 } 1194 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1195 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1196 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1197 pqh->hlink = sqh->hlink; 1198 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1199 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1200 sizeof(pqh->qh.qh_hlink), 1201 BUS_DMASYNC_PREWRITE); 1202 delay(UHCI_QH_REMOVE_DELAY); 1203 if (sc->sc_lctl_end == sqh) 1204 sc->sc_lctl_end = pqh; 1205 } 1206 1207 /* Add bulk QH, called at splusb(). */ 1208 void 1209 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1210 { 1211 uhci_soft_qh_t *eqh; 1212 1213 SPLUSBCHECK; 1214 1215 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1216 eqh = sc->sc_bulk_end; 1217 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1218 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1219 sqh->hlink = eqh->hlink; 1220 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1221 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1222 BUS_DMASYNC_PREWRITE); 1223 eqh->hlink = sqh; 1224 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1225 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1226 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1227 sc->sc_bulk_end = sqh; 1228 uhci_add_loop(sc); 1229 } 1230 1231 /* Remove bulk QH, called at splusb(). */ 1232 void 1233 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1234 { 1235 uhci_soft_qh_t *pqh; 1236 1237 SPLUSBCHECK; 1238 1239 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1240 uhci_rem_loop(sc); 1241 /* See comment in uhci_remove_hs_ctrl() */ 1242 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1243 sizeof(sqh->qh.qh_elink), 1244 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1245 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1246 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1247 usb_syncmem(&sqh->dma, 1248 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1249 sizeof(sqh->qh.qh_elink), 1250 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1251 delay(UHCI_QH_REMOVE_DELAY); 1252 } 1253 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1254 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1255 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1256 pqh->hlink = sqh->hlink; 1257 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1258 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1259 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1260 delay(UHCI_QH_REMOVE_DELAY); 1261 if (sc->sc_bulk_end == sqh) 1262 sc->sc_bulk_end = pqh; 1263 } 1264 1265 Static int uhci_intr1(uhci_softc_t *); 1266 1267 int 1268 uhci_intr(void *arg) 1269 { 1270 uhci_softc_t *sc = arg; 1271 1272 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1273 return (0); 1274 1275 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1276 #ifdef DIAGNOSTIC 1277 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1278 #endif 1279 return (0); 1280 } 1281 1282 return (uhci_intr1(sc)); 1283 } 1284 1285 int 1286 uhci_intr1(uhci_softc_t *sc) 1287 { 1288 int status; 1289 int ack; 1290 1291 #ifdef UHCI_DEBUG 1292 if (uhcidebug > 15) { 1293 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1294 uhci_dumpregs(sc); 1295 } 1296 #endif 1297 1298 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1299 if (status == 0) /* The interrupt was not for us. */ 1300 return (0); 1301 1302 if (sc->sc_suspend != PWR_RESUME) { 1303 #ifdef DIAGNOSTIC 1304 printf("%s: interrupt while not operating ignored\n", 1305 device_xname(sc->sc_dev)); 1306 #endif 1307 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1308 return (0); 1309 } 1310 1311 ack = 0; 1312 if (status & UHCI_STS_USBINT) 1313 ack |= UHCI_STS_USBINT; 1314 if (status & UHCI_STS_USBEI) 1315 ack |= UHCI_STS_USBEI; 1316 if (status & UHCI_STS_RD) { 1317 ack |= UHCI_STS_RD; 1318 #ifdef UHCI_DEBUG 1319 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1320 #endif 1321 } 1322 if (status & UHCI_STS_HSE) { 1323 ack |= UHCI_STS_HSE; 1324 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1325 } 1326 if (status & UHCI_STS_HCPE) { 1327 ack |= UHCI_STS_HCPE; 1328 printf("%s: host controller process error\n", 1329 device_xname(sc->sc_dev)); 1330 } 1331 1332 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1333 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1334 /* no acknowledge needed */ 1335 if (!sc->sc_dying) { 1336 printf("%s: host controller halted\n", 1337 device_xname(sc->sc_dev)); 1338 #ifdef UHCI_DEBUG 1339 uhci_dump_all(sc); 1340 #endif 1341 } 1342 sc->sc_dying = 1; 1343 } 1344 1345 if (!ack) 1346 return (0); /* nothing to acknowledge */ 1347 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1348 1349 sc->sc_bus.no_intrs++; 1350 usb_schedsoftintr(&sc->sc_bus); 1351 1352 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1353 1354 return (1); 1355 } 1356 1357 void 1358 uhci_softintr(void *v) 1359 { 1360 struct usbd_bus *bus = v; 1361 uhci_softc_t *sc = bus->hci_private; 1362 uhci_intr_info_t *ii, *nextii; 1363 1364 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1365 sc->sc_bus.intr_context)); 1366 1367 sc->sc_bus.intr_context++; 1368 1369 /* 1370 * Interrupts on UHCI really suck. When the host controller 1371 * interrupts because a transfer is completed there is no 1372 * way of knowing which transfer it was. You can scan down 1373 * the TDs and QHs of the previous frame to limit the search, 1374 * but that assumes that the interrupt was not delayed by more 1375 * than 1 ms, which may not always be true (e.g. after debug 1376 * output on a slow console). 1377 * We scan all interrupt descriptors to see if any have 1378 * completed. 1379 */ 1380 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1381 nextii = LIST_NEXT(ii, list); 1382 uhci_check_intr(sc, ii); 1383 } 1384 1385 #ifdef USB_USE_SOFTINTR 1386 if (sc->sc_softwake) { 1387 sc->sc_softwake = 0; 1388 wakeup(&sc->sc_softwake); 1389 } 1390 #endif /* USB_USE_SOFTINTR */ 1391 1392 sc->sc_bus.intr_context--; 1393 } 1394 1395 /* Check for an interrupt. */ 1396 void 1397 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1398 { 1399 uhci_soft_td_t *std, *lstd; 1400 u_int32_t status; 1401 1402 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1403 #ifdef DIAGNOSTIC 1404 if (ii == NULL) { 1405 printf("uhci_check_intr: no ii? %p\n", ii); 1406 return; 1407 } 1408 #endif 1409 if (ii->xfer->status == USBD_CANCELLED || 1410 ii->xfer->status == USBD_TIMEOUT) { 1411 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1412 return; 1413 } 1414 1415 if (ii->stdstart == NULL) 1416 return; 1417 lstd = ii->stdend; 1418 #ifdef DIAGNOSTIC 1419 if (lstd == NULL) { 1420 printf("uhci_check_intr: std==0\n"); 1421 return; 1422 } 1423 #endif 1424 /* 1425 * If the last TD is still active we need to check whether there 1426 * is an error somewhere in the middle, or whether there was a 1427 * short packet (SPD and not ACTIVE). 1428 */ 1429 usb_syncmem(&lstd->dma, 1430 lstd->offs + offsetof(uhci_td_t, td_status), 1431 sizeof(lstd->td.td_status), 1432 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1433 if (le32toh(lstd->td.td_status) & UHCI_TD_ACTIVE) { 1434 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1435 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1436 usb_syncmem(&std->dma, 1437 std->offs + offsetof(uhci_td_t, td_status), 1438 sizeof(std->td.td_status), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 status = le32toh(std->td.td_status); 1441 usb_syncmem(&std->dma, 1442 std->offs + offsetof(uhci_td_t, td_status), 1443 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1444 /* If there's an active TD the xfer isn't done. */ 1445 if (status & UHCI_TD_ACTIVE) 1446 break; 1447 /* Any kind of error makes the xfer done. */ 1448 if (status & UHCI_TD_STALLED) 1449 goto done; 1450 /* We want short packets, and it is short: it's done */ 1451 usb_syncmem(&std->dma, 1452 std->offs + offsetof(uhci_td_t, td_token), 1453 sizeof(std->td.td_token), 1454 BUS_DMASYNC_POSTWRITE); 1455 if ((status & UHCI_TD_SPD) && 1456 UHCI_TD_GET_ACTLEN(status) < 1457 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1458 goto done; 1459 } 1460 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1461 ii, ii->stdstart)); 1462 usb_syncmem(&lstd->dma, 1463 lstd->offs + offsetof(uhci_td_t, td_status), 1464 sizeof(lstd->td.td_status), 1465 BUS_DMASYNC_PREREAD); 1466 return; 1467 } 1468 done: 1469 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1470 callout_stop(&ii->xfer->timeout_handle); 1471 uhci_idone(ii); 1472 } 1473 1474 /* Called at splusb() */ 1475 void 1476 uhci_idone(uhci_intr_info_t *ii) 1477 { 1478 usbd_xfer_handle xfer = ii->xfer; 1479 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1480 uhci_soft_td_t *std; 1481 u_int32_t status = 0, nstatus; 1482 int actlen; 1483 1484 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1485 #ifdef DIAGNOSTIC 1486 { 1487 int s = splhigh(); 1488 if (ii->isdone) { 1489 splx(s); 1490 #ifdef UHCI_DEBUG 1491 printf("uhci_idone: ii is done!\n "); 1492 uhci_dump_ii(ii); 1493 #else 1494 printf("uhci_idone: ii=%p is done!\n", ii); 1495 #endif 1496 return; 1497 } 1498 ii->isdone = 1; 1499 splx(s); 1500 } 1501 #endif 1502 1503 if (xfer->nframes != 0) { 1504 /* Isoc transfer, do things differently. */ 1505 uhci_soft_td_t **stds = upipe->u.iso.stds; 1506 int i, n, nframes, len; 1507 1508 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1509 1510 nframes = xfer->nframes; 1511 actlen = 0; 1512 n = UXFER(xfer)->curframe; 1513 for (i = 0; i < nframes; i++) { 1514 std = stds[n]; 1515 #ifdef UHCI_DEBUG 1516 if (uhcidebug > 5) { 1517 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1518 uhci_dump_td(std); 1519 } 1520 #endif 1521 if (++n >= UHCI_VFRAMELIST_COUNT) 1522 n = 0; 1523 usb_syncmem(&std->dma, 1524 std->offs + offsetof(uhci_td_t, td_status), 1525 sizeof(std->td.td_status), 1526 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1527 status = le32toh(std->td.td_status); 1528 len = UHCI_TD_GET_ACTLEN(status); 1529 xfer->frlengths[i] = len; 1530 actlen += len; 1531 } 1532 upipe->u.iso.inuse -= nframes; 1533 xfer->actlen = actlen; 1534 xfer->status = USBD_NORMAL_COMPLETION; 1535 goto end; 1536 } 1537 1538 #ifdef UHCI_DEBUG 1539 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1540 ii, xfer, upipe)); 1541 if (uhcidebug > 10) 1542 uhci_dump_tds(ii->stdstart); 1543 #endif 1544 1545 /* The transfer is done, compute actual length and status. */ 1546 actlen = 0; 1547 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1548 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1549 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1550 nstatus = le32toh(std->td.td_status); 1551 if (nstatus & UHCI_TD_ACTIVE) 1552 break; 1553 1554 status = nstatus; 1555 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1556 UHCI_TD_PID_SETUP) 1557 actlen += UHCI_TD_GET_ACTLEN(status); 1558 else { 1559 /* 1560 * UHCI will report CRCTO in addition to a STALL or NAK 1561 * for a SETUP transaction. See section 3.2.2, "TD 1562 * CONTROL AND STATUS". 1563 */ 1564 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1565 status &= ~UHCI_TD_CRCTO; 1566 } 1567 } 1568 /* If there are left over TDs we need to update the toggle. */ 1569 if (std != NULL) 1570 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1571 1572 status &= UHCI_TD_ERROR; 1573 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1574 actlen, status)); 1575 xfer->actlen = actlen; 1576 if (status != 0) { 1577 #ifdef UHCI_DEBUG 1578 char sbuf[128]; 1579 1580 snprintb(sbuf, sizeof(sbuf), 1581 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1582 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1583 1584 DPRINTFN((status == UHCI_TD_STALLED)*10, 1585 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1586 "status 0x%s\n", 1587 xfer->pipe->device->address, 1588 xfer->pipe->endpoint->edesc->bEndpointAddress, 1589 sbuf)); 1590 #endif 1591 1592 if (status == UHCI_TD_STALLED) 1593 xfer->status = USBD_STALLED; 1594 else 1595 xfer->status = USBD_IOERROR; /* more info XXX */ 1596 } else { 1597 xfer->status = USBD_NORMAL_COMPLETION; 1598 } 1599 1600 end: 1601 usb_transfer_complete(xfer); 1602 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1603 } 1604 1605 /* 1606 * Called when a request does not complete. 1607 */ 1608 void 1609 uhci_timeout(void *addr) 1610 { 1611 uhci_intr_info_t *ii = addr; 1612 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1613 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1614 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1615 1616 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1617 1618 if (sc->sc_dying) { 1619 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1620 return; 1621 } 1622 1623 /* Execute the abort in a process context. */ 1624 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1625 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1626 USB_TASKQ_HC); 1627 } 1628 1629 void 1630 uhci_timeout_task(void *addr) 1631 { 1632 usbd_xfer_handle xfer = addr; 1633 int s; 1634 1635 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1636 1637 s = splusb(); 1638 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1639 splx(s); 1640 } 1641 1642 /* 1643 * Wait here until controller claims to have an interrupt. 1644 * Then call uhci_intr and return. Use timeout to avoid waiting 1645 * too long. 1646 * Only used during boot when interrupts are not enabled yet. 1647 */ 1648 void 1649 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1650 { 1651 int timo = xfer->timeout; 1652 uhci_intr_info_t *ii; 1653 1654 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1655 1656 xfer->status = USBD_IN_PROGRESS; 1657 for (; timo >= 0; timo--) { 1658 usb_delay_ms(&sc->sc_bus, 1); 1659 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1660 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1661 uhci_intr1(sc); 1662 if (xfer->status != USBD_IN_PROGRESS) 1663 return; 1664 } 1665 } 1666 1667 /* Timeout */ 1668 DPRINTF(("uhci_waitintr: timeout\n")); 1669 for (ii = LIST_FIRST(&sc->sc_intrhead); 1670 ii != NULL && ii->xfer != xfer; 1671 ii = LIST_NEXT(ii, list)) 1672 ; 1673 #ifdef DIAGNOSTIC 1674 if (ii == NULL) 1675 panic("uhci_waitintr: lost intr_info"); 1676 #endif 1677 uhci_idone(ii); 1678 } 1679 1680 void 1681 uhci_poll(struct usbd_bus *bus) 1682 { 1683 uhci_softc_t *sc = bus->hci_private; 1684 1685 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) 1686 uhci_intr1(sc); 1687 } 1688 1689 void 1690 uhci_reset(uhci_softc_t *sc) 1691 { 1692 int n; 1693 1694 UHCICMD(sc, UHCI_CMD_HCRESET); 1695 /* The reset bit goes low when the controller is done. */ 1696 for (n = 0; n < UHCI_RESET_TIMEOUT && 1697 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1698 usb_delay_ms(&sc->sc_bus, 1); 1699 if (n >= UHCI_RESET_TIMEOUT) 1700 printf("%s: controller did not reset\n", 1701 device_xname(sc->sc_dev)); 1702 } 1703 1704 usbd_status 1705 uhci_run(uhci_softc_t *sc, int run) 1706 { 1707 int s, n, running; 1708 u_int16_t cmd; 1709 1710 run = run != 0; 1711 s = splhardusb(); 1712 DPRINTF(("uhci_run: setting run=%d\n", run)); 1713 cmd = UREAD2(sc, UHCI_CMD); 1714 if (run) 1715 cmd |= UHCI_CMD_RS; 1716 else 1717 cmd &= ~UHCI_CMD_RS; 1718 UHCICMD(sc, cmd); 1719 for(n = 0; n < 10; n++) { 1720 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1721 /* return when we've entered the state we want */ 1722 if (run == running) { 1723 splx(s); 1724 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1725 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1726 return (USBD_NORMAL_COMPLETION); 1727 } 1728 usb_delay_ms(&sc->sc_bus, 1); 1729 } 1730 splx(s); 1731 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1732 run ? "start" : "stop"); 1733 return (USBD_IOERROR); 1734 } 1735 1736 /* 1737 * Memory management routines. 1738 * uhci_alloc_std allocates TDs 1739 * uhci_alloc_sqh allocates QHs 1740 * These two routines do their own free list management, 1741 * partly for speed, partly because allocating DMAable memory 1742 * has page size granularaity so much memory would be wasted if 1743 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1744 */ 1745 1746 uhci_soft_td_t * 1747 uhci_alloc_std(uhci_softc_t *sc) 1748 { 1749 uhci_soft_td_t *std; 1750 usbd_status err; 1751 int i, offs; 1752 usb_dma_t dma; 1753 1754 if (sc->sc_freetds == NULL) { 1755 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1756 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1757 UHCI_TD_ALIGN, &dma); 1758 if (err) 1759 return (0); 1760 for(i = 0; i < UHCI_STD_CHUNK; i++) { 1761 offs = i * UHCI_STD_SIZE; 1762 std = KERNADDR(&dma, offs); 1763 std->physaddr = DMAADDR(&dma, offs); 1764 std->dma = dma; 1765 std->offs = offs; 1766 std->link.std = sc->sc_freetds; 1767 sc->sc_freetds = std; 1768 } 1769 } 1770 std = sc->sc_freetds; 1771 sc->sc_freetds = std->link.std; 1772 memset(&std->td, 0, sizeof(uhci_td_t)); 1773 return std; 1774 } 1775 1776 void 1777 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1778 { 1779 #ifdef DIAGNOSTIC 1780 #define TD_IS_FREE 0x12345678 1781 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1782 printf("uhci_free_std: freeing free TD %p\n", std); 1783 return; 1784 } 1785 std->td.td_token = htole32(TD_IS_FREE); 1786 #endif 1787 std->link.std = sc->sc_freetds; 1788 sc->sc_freetds = std; 1789 } 1790 1791 uhci_soft_qh_t * 1792 uhci_alloc_sqh(uhci_softc_t *sc) 1793 { 1794 uhci_soft_qh_t *sqh; 1795 usbd_status err; 1796 int i, offs; 1797 usb_dma_t dma; 1798 1799 if (sc->sc_freeqhs == NULL) { 1800 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1801 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1802 UHCI_QH_ALIGN, &dma); 1803 if (err) 1804 return (0); 1805 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1806 offs = i * UHCI_SQH_SIZE; 1807 sqh = KERNADDR(&dma, offs); 1808 sqh->physaddr = DMAADDR(&dma, offs); 1809 sqh->dma = dma; 1810 sqh->offs = offs; 1811 sqh->hlink = sc->sc_freeqhs; 1812 sc->sc_freeqhs = sqh; 1813 } 1814 } 1815 sqh = sc->sc_freeqhs; 1816 sc->sc_freeqhs = sqh->hlink; 1817 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1818 return (sqh); 1819 } 1820 1821 void 1822 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1823 { 1824 sqh->hlink = sc->sc_freeqhs; 1825 sc->sc_freeqhs = sqh; 1826 } 1827 1828 void 1829 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1830 uhci_soft_td_t *stdend) 1831 { 1832 uhci_soft_td_t *p; 1833 1834 /* 1835 * to avoid race condition with the controller which may be looking 1836 * at this chain, we need to first invalidate all links, and 1837 * then wait for the controller to move to another queue 1838 */ 1839 for (p = std; p != stdend; p = p->link.std) { 1840 usb_syncmem(&p->dma, 1841 p->offs + offsetof(uhci_td_t, td_link), 1842 sizeof(p->td.td_link), 1843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1844 if ((p->td.td_link & UHCI_PTR_T) == 0) { 1845 p->td.td_link = UHCI_PTR_T; 1846 usb_syncmem(&p->dma, 1847 p->offs + offsetof(uhci_td_t, td_link), 1848 sizeof(p->td.td_link), 1849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1850 } 1851 } 1852 delay(UHCI_QH_REMOVE_DELAY); 1853 1854 for (; std != stdend; std = p) { 1855 p = std->link.std; 1856 uhci_free_std(sc, std); 1857 } 1858 } 1859 1860 usbd_status 1861 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1862 int rd, u_int16_t flags, usb_dma_t *dma, 1863 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1864 { 1865 uhci_soft_td_t *p, *lastp; 1866 uhci_physaddr_t lastlink; 1867 int i, ntd, l, tog, maxp; 1868 u_int32_t status; 1869 int addr = upipe->pipe.device->address; 1870 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1871 1872 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1873 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1874 upipe->pipe.device->speed, flags)); 1875 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1876 if (maxp == 0) { 1877 printf("uhci_alloc_std_chain: maxp=0\n"); 1878 return (USBD_INVAL); 1879 } 1880 ntd = (len + maxp - 1) / maxp; 1881 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1882 ntd++; 1883 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1884 if (ntd == 0) { 1885 *sp = *ep = 0; 1886 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1887 return (USBD_NORMAL_COMPLETION); 1888 } 1889 tog = upipe->nexttoggle; 1890 if (ntd % 2 == 0) 1891 tog ^= 1; 1892 upipe->nexttoggle = tog ^ 1; 1893 lastp = NULL; 1894 lastlink = UHCI_PTR_T; 1895 ntd--; 1896 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1897 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1898 status |= UHCI_TD_LS; 1899 if (flags & USBD_SHORT_XFER_OK) 1900 status |= UHCI_TD_SPD; 1901 usb_syncmem(dma, 0, len, 1902 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1903 for (i = ntd; i >= 0; i--) { 1904 p = uhci_alloc_std(sc); 1905 if (p == NULL) { 1906 KASSERT(lastp != NULL); 1907 uhci_free_std_chain(sc, lastp, NULL); 1908 return (USBD_NOMEM); 1909 } 1910 p->link.std = lastp; 1911 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1912 lastp = p; 1913 lastlink = p->physaddr; 1914 p->td.td_status = htole32(status); 1915 if (i == ntd) { 1916 /* last TD */ 1917 l = len % maxp; 1918 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1919 l = maxp; 1920 *ep = p; 1921 } else 1922 l = maxp; 1923 p->td.td_token = 1924 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1925 UHCI_TD_OUT(l, endpt, addr, tog)); 1926 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1927 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1928 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1929 tog ^= 1; 1930 } 1931 *sp = lastp; 1932 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1933 upipe->nexttoggle)); 1934 return (USBD_NORMAL_COMPLETION); 1935 } 1936 1937 void 1938 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1939 { 1940 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1941 upipe->nexttoggle = 0; 1942 } 1943 1944 void 1945 uhci_noop(usbd_pipe_handle pipe) 1946 { 1947 } 1948 1949 usbd_status 1950 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1951 { 1952 usbd_status err; 1953 1954 /* Insert last in queue. */ 1955 err = usb_insert_transfer(xfer); 1956 if (err) 1957 return (err); 1958 1959 /* 1960 * Pipe isn't running (otherwise err would be USBD_INPROG), 1961 * so start it first. 1962 */ 1963 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1964 } 1965 1966 usbd_status 1967 uhci_device_bulk_start(usbd_xfer_handle xfer) 1968 { 1969 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1970 usbd_device_handle dev = upipe->pipe.device; 1971 uhci_softc_t *sc = dev->bus->hci_private; 1972 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1973 uhci_soft_td_t *data, *dataend; 1974 uhci_soft_qh_t *sqh; 1975 usbd_status err; 1976 int len, isread, endpt; 1977 int s; 1978 1979 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1980 xfer, xfer->length, xfer->flags, ii)); 1981 1982 if (sc->sc_dying) 1983 return (USBD_IOERROR); 1984 1985 #ifdef DIAGNOSTIC 1986 if (xfer->rqflags & URQ_REQUEST) 1987 panic("uhci_device_bulk_transfer: a request"); 1988 #endif 1989 1990 len = xfer->length; 1991 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1992 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 1993 sqh = upipe->u.bulk.sqh; 1994 1995 upipe->u.bulk.isread = isread; 1996 upipe->u.bulk.length = len; 1997 1998 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 1999 &xfer->dmabuf, &data, &dataend); 2000 if (err) 2001 return (err); 2002 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2003 usb_syncmem(&dataend->dma, 2004 dataend->offs + offsetof(uhci_td_t, td_status), 2005 sizeof(dataend->td.td_status), 2006 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2007 2008 2009 #ifdef UHCI_DEBUG 2010 if (uhcidebug > 8) { 2011 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2012 uhci_dump_tds(data); 2013 } 2014 #endif 2015 2016 /* Set up interrupt info. */ 2017 ii->xfer = xfer; 2018 ii->stdstart = data; 2019 ii->stdend = dataend; 2020 #ifdef DIAGNOSTIC 2021 if (!ii->isdone) { 2022 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2023 } 2024 ii->isdone = 0; 2025 #endif 2026 2027 sqh->elink = data; 2028 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2029 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2030 2031 s = splusb(); 2032 uhci_add_bulk(sc, sqh); 2033 uhci_add_intr_info(sc, ii); 2034 2035 if (xfer->timeout && !sc->sc_bus.use_polling) { 2036 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2037 uhci_timeout, ii); 2038 } 2039 xfer->status = USBD_IN_PROGRESS; 2040 splx(s); 2041 2042 #ifdef UHCI_DEBUG 2043 if (uhcidebug > 10) { 2044 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2045 uhci_dump_tds(data); 2046 } 2047 #endif 2048 2049 if (sc->sc_bus.use_polling) 2050 uhci_waitintr(sc, xfer); 2051 2052 return (USBD_IN_PROGRESS); 2053 } 2054 2055 /* Abort a device bulk request. */ 2056 void 2057 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2058 { 2059 DPRINTF(("uhci_device_bulk_abort:\n")); 2060 uhci_abort_xfer(xfer, USBD_CANCELLED); 2061 } 2062 2063 /* 2064 * Abort a device request. 2065 * If this routine is called at splusb() it guarantees that the request 2066 * will be removed from the hardware scheduling and that the callback 2067 * for it will be called with USBD_CANCELLED status. 2068 * It's impossible to guarantee that the requested transfer will not 2069 * have happened since the hardware runs concurrently. 2070 * If the transaction has already happened we rely on the ordinary 2071 * interrupt processing to process it. 2072 */ 2073 void 2074 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2075 { 2076 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2077 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2078 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2079 uhci_soft_td_t *std; 2080 int s; 2081 int wake; 2082 2083 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2084 2085 if (sc->sc_dying) { 2086 /* If we're dying, just do the software part. */ 2087 s = splusb(); 2088 xfer->status = status; /* make software ignore it */ 2089 callout_stop(&xfer->timeout_handle); 2090 usb_transfer_complete(xfer); 2091 splx(s); 2092 return; 2093 } 2094 2095 if (xfer->device->bus->intr_context || !curproc) 2096 panic("uhci_abort_xfer: not in process context"); 2097 2098 /* 2099 * If an abort is already in progress then just wait for it to 2100 * complete and return. 2101 */ 2102 if (xfer->hcflags & UXFER_ABORTING) { 2103 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2104 #ifdef DIAGNOSTIC 2105 if (status == USBD_TIMEOUT) 2106 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2107 #endif 2108 /* Override the status which might be USBD_TIMEOUT. */ 2109 xfer->status = status; 2110 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2111 xfer->hcflags |= UXFER_ABORTWAIT; 2112 while (xfer->hcflags & UXFER_ABORTING) 2113 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0); 2114 return; 2115 } 2116 xfer->hcflags |= UXFER_ABORTING; 2117 2118 /* 2119 * Step 1: Make interrupt routine and hardware ignore xfer. 2120 */ 2121 s = splusb(); 2122 xfer->status = status; /* make software ignore it */ 2123 callout_stop(&xfer->timeout_handle); 2124 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2125 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2126 usb_syncmem(&std->dma, 2127 std->offs + offsetof(uhci_td_t, td_status), 2128 sizeof(std->td.td_status), 2129 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2130 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2131 usb_syncmem(&std->dma, 2132 std->offs + offsetof(uhci_td_t, td_status), 2133 sizeof(std->td.td_status), 2134 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2135 } 2136 splx(s); 2137 2138 /* 2139 * Step 2: Wait until we know hardware has finished any possible 2140 * use of the xfer. Also make sure the soft interrupt routine 2141 * has run. 2142 */ 2143 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2144 s = splusb(); 2145 #ifdef USB_USE_SOFTINTR 2146 sc->sc_softwake = 1; 2147 #endif /* USB_USE_SOFTINTR */ 2148 usb_schedsoftintr(&sc->sc_bus); 2149 #ifdef USB_USE_SOFTINTR 2150 DPRINTFN(1,("uhci_abort_xfer: tsleep\n")); 2151 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0); 2152 #endif /* USB_USE_SOFTINTR */ 2153 splx(s); 2154 2155 /* 2156 * Step 3: Execute callback. 2157 */ 2158 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2159 s = splusb(); 2160 #ifdef DIAGNOSTIC 2161 ii->isdone = 1; 2162 #endif 2163 wake = xfer->hcflags & UXFER_ABORTWAIT; 2164 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2165 usb_transfer_complete(xfer); 2166 if (wake) 2167 wakeup(&xfer->hcflags); 2168 splx(s); 2169 } 2170 2171 /* Close a device bulk pipe. */ 2172 void 2173 uhci_device_bulk_close(usbd_pipe_handle pipe) 2174 { 2175 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2176 usbd_device_handle dev = upipe->pipe.device; 2177 uhci_softc_t *sc = dev->bus->hci_private; 2178 2179 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2180 2181 pipe->endpoint->datatoggle = upipe->nexttoggle; 2182 } 2183 2184 usbd_status 2185 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2186 { 2187 usbd_status err; 2188 2189 /* Insert last in queue. */ 2190 err = usb_insert_transfer(xfer); 2191 if (err) 2192 return (err); 2193 2194 /* 2195 * Pipe isn't running (otherwise err would be USBD_INPROG), 2196 * so start it first. 2197 */ 2198 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2199 } 2200 2201 usbd_status 2202 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2203 { 2204 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2205 usbd_status err; 2206 2207 if (sc->sc_dying) 2208 return (USBD_IOERROR); 2209 2210 #ifdef DIAGNOSTIC 2211 if (!(xfer->rqflags & URQ_REQUEST)) 2212 panic("uhci_device_ctrl_transfer: not a request"); 2213 #endif 2214 2215 err = uhci_device_request(xfer); 2216 if (err) 2217 return (err); 2218 2219 if (sc->sc_bus.use_polling) 2220 uhci_waitintr(sc, xfer); 2221 return (USBD_IN_PROGRESS); 2222 } 2223 2224 usbd_status 2225 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2226 { 2227 usbd_status err; 2228 2229 /* Insert last in queue. */ 2230 err = usb_insert_transfer(xfer); 2231 if (err) 2232 return (err); 2233 2234 /* 2235 * Pipe isn't running (otherwise err would be USBD_INPROG), 2236 * so start it first. 2237 */ 2238 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2239 } 2240 2241 usbd_status 2242 uhci_device_intr_start(usbd_xfer_handle xfer) 2243 { 2244 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2245 usbd_device_handle dev = upipe->pipe.device; 2246 uhci_softc_t *sc = dev->bus->hci_private; 2247 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2248 uhci_soft_td_t *data, *dataend; 2249 uhci_soft_qh_t *sqh; 2250 usbd_status err; 2251 int isread, endpt; 2252 int i, s; 2253 2254 if (sc->sc_dying) 2255 return (USBD_IOERROR); 2256 2257 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2258 xfer, xfer->length, xfer->flags)); 2259 2260 #ifdef DIAGNOSTIC 2261 if (xfer->rqflags & URQ_REQUEST) 2262 panic("uhci_device_intr_transfer: a request"); 2263 #endif 2264 2265 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2266 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2267 2268 upipe->u.intr.isread = isread; 2269 2270 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2271 xfer->flags, &xfer->dmabuf, &data, 2272 &dataend); 2273 if (err) 2274 return (err); 2275 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2276 usb_syncmem(&dataend->dma, 2277 dataend->offs + offsetof(uhci_td_t, td_status), 2278 sizeof(dataend->td.td_status), 2279 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2280 2281 #ifdef UHCI_DEBUG 2282 if (uhcidebug > 10) { 2283 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2284 uhci_dump_tds(data); 2285 uhci_dump_qh(upipe->u.intr.qhs[0]); 2286 } 2287 #endif 2288 2289 s = splusb(); 2290 /* Set up interrupt info. */ 2291 ii->xfer = xfer; 2292 ii->stdstart = data; 2293 ii->stdend = dataend; 2294 #ifdef DIAGNOSTIC 2295 if (!ii->isdone) { 2296 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2297 } 2298 ii->isdone = 0; 2299 #endif 2300 2301 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2302 upipe->u.intr.qhs[0])); 2303 for (i = 0; i < upipe->u.intr.npoll; i++) { 2304 sqh = upipe->u.intr.qhs[i]; 2305 sqh->elink = data; 2306 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2307 usb_syncmem(&sqh->dma, 2308 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2309 sizeof(sqh->qh.qh_elink), 2310 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2311 } 2312 uhci_add_intr_info(sc, ii); 2313 xfer->status = USBD_IN_PROGRESS; 2314 splx(s); 2315 2316 #ifdef UHCI_DEBUG 2317 if (uhcidebug > 10) { 2318 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2319 uhci_dump_tds(data); 2320 uhci_dump_qh(upipe->u.intr.qhs[0]); 2321 } 2322 #endif 2323 2324 return (USBD_IN_PROGRESS); 2325 } 2326 2327 /* Abort a device control request. */ 2328 void 2329 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2330 { 2331 DPRINTF(("uhci_device_ctrl_abort:\n")); 2332 uhci_abort_xfer(xfer, USBD_CANCELLED); 2333 } 2334 2335 /* Close a device control pipe. */ 2336 void 2337 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2338 { 2339 } 2340 2341 /* Abort a device interrupt request. */ 2342 void 2343 uhci_device_intr_abort(usbd_xfer_handle xfer) 2344 { 2345 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2346 if (xfer->pipe->intrxfer == xfer) { 2347 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2348 xfer->pipe->intrxfer = NULL; 2349 } 2350 uhci_abort_xfer(xfer, USBD_CANCELLED); 2351 } 2352 2353 /* Close a device interrupt pipe. */ 2354 void 2355 uhci_device_intr_close(usbd_pipe_handle pipe) 2356 { 2357 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2358 uhci_softc_t *sc = pipe->device->bus->hci_private; 2359 int i, npoll; 2360 int s; 2361 2362 /* Unlink descriptors from controller data structures. */ 2363 npoll = upipe->u.intr.npoll; 2364 s = splusb(); 2365 for (i = 0; i < npoll; i++) 2366 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2367 splx(s); 2368 2369 /* 2370 * We now have to wait for any activity on the physical 2371 * descriptors to stop. 2372 */ 2373 usb_delay_ms(&sc->sc_bus, 2); 2374 2375 for(i = 0; i < npoll; i++) 2376 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2377 free(upipe->u.intr.qhs, M_USBHC); 2378 2379 /* XXX free other resources */ 2380 } 2381 2382 usbd_status 2383 uhci_device_request(usbd_xfer_handle xfer) 2384 { 2385 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2386 usb_device_request_t *req = &xfer->request; 2387 usbd_device_handle dev = upipe->pipe.device; 2388 uhci_softc_t *sc = dev->bus->hci_private; 2389 int addr = dev->address; 2390 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2391 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2392 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2393 uhci_soft_qh_t *sqh; 2394 int len; 2395 u_int32_t ls; 2396 usbd_status err; 2397 int isread; 2398 int s; 2399 2400 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2401 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2402 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2403 UGETW(req->wIndex), UGETW(req->wLength), 2404 addr, endpt)); 2405 2406 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2407 isread = req->bmRequestType & UT_READ; 2408 len = UGETW(req->wLength); 2409 2410 setup = upipe->u.ctl.setup; 2411 stat = upipe->u.ctl.stat; 2412 sqh = upipe->u.ctl.sqh; 2413 2414 /* Set up data transaction */ 2415 if (len != 0) { 2416 upipe->nexttoggle = 1; 2417 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2418 &xfer->dmabuf, &data, &dataend); 2419 if (err) 2420 return (err); 2421 next = data; 2422 dataend->link.std = stat; 2423 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2424 usb_syncmem(&dataend->dma, 2425 dataend->offs + offsetof(uhci_td_t, td_link), 2426 sizeof(dataend->td.td_link), 2427 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2428 } else { 2429 next = stat; 2430 } 2431 upipe->u.ctl.length = len; 2432 2433 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2434 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2435 2436 setup->link.std = next; 2437 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2438 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2439 UHCI_TD_ACTIVE); 2440 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2441 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2442 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2443 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2444 2445 stat->link.std = NULL; 2446 stat->td.td_link = htole32(UHCI_PTR_T); 2447 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2448 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2449 stat->td.td_token = 2450 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2451 UHCI_TD_IN (0, endpt, addr, 1)); 2452 stat->td.td_buffer = htole32(0); 2453 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2455 2456 #ifdef UHCI_DEBUG 2457 if (uhcidebug > 10) { 2458 DPRINTF(("uhci_device_request: before transfer\n")); 2459 uhci_dump_tds(setup); 2460 } 2461 #endif 2462 2463 /* Set up interrupt info. */ 2464 ii->xfer = xfer; 2465 ii->stdstart = setup; 2466 ii->stdend = stat; 2467 #ifdef DIAGNOSTIC 2468 if (!ii->isdone) { 2469 printf("uhci_device_request: not done, ii=%p\n", ii); 2470 } 2471 ii->isdone = 0; 2472 #endif 2473 2474 sqh->elink = setup; 2475 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2476 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2477 2478 s = splusb(); 2479 if (dev->speed == USB_SPEED_LOW) 2480 uhci_add_ls_ctrl(sc, sqh); 2481 else 2482 uhci_add_hs_ctrl(sc, sqh); 2483 uhci_add_intr_info(sc, ii); 2484 #ifdef UHCI_DEBUG 2485 if (uhcidebug > 12) { 2486 uhci_soft_td_t *std; 2487 uhci_soft_qh_t *xqh; 2488 uhci_soft_qh_t *sxqh; 2489 int maxqh = 0; 2490 uhci_physaddr_t link; 2491 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2492 for (std = sc->sc_vframes[0].htd, link = 0; 2493 (link & UHCI_PTR_QH) == 0; 2494 std = std->link.std) { 2495 link = le32toh(std->td.td_link); 2496 uhci_dump_td(std); 2497 } 2498 sxqh = (uhci_soft_qh_t *)std; 2499 uhci_dump_qh(sxqh); 2500 for (xqh = sxqh; 2501 xqh != NULL; 2502 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2503 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2504 uhci_dump_qh(xqh); 2505 } 2506 DPRINTF(("Enqueued QH:\n")); 2507 uhci_dump_qh(sqh); 2508 uhci_dump_tds(sqh->elink); 2509 } 2510 #endif 2511 if (xfer->timeout && !sc->sc_bus.use_polling) { 2512 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2513 uhci_timeout, ii); 2514 } 2515 xfer->status = USBD_IN_PROGRESS; 2516 splx(s); 2517 2518 return (USBD_NORMAL_COMPLETION); 2519 } 2520 2521 usbd_status 2522 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2523 { 2524 usbd_status err; 2525 2526 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2527 2528 /* Put it on our queue, */ 2529 err = usb_insert_transfer(xfer); 2530 2531 /* bail out on error, */ 2532 if (err && err != USBD_IN_PROGRESS) 2533 return (err); 2534 2535 /* XXX should check inuse here */ 2536 2537 /* insert into schedule, */ 2538 uhci_device_isoc_enter(xfer); 2539 2540 /* and start if the pipe wasn't running */ 2541 if (!err) 2542 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2543 2544 return (err); 2545 } 2546 2547 void 2548 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2549 { 2550 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2551 usbd_device_handle dev = upipe->pipe.device; 2552 uhci_softc_t *sc = dev->bus->hci_private; 2553 struct iso *iso = &upipe->u.iso; 2554 uhci_soft_td_t *std; 2555 u_int32_t buf, len, status, offs; 2556 int s, i, next, nframes; 2557 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2558 2559 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2560 "nframes=%d\n", 2561 iso->inuse, iso->next, xfer, xfer->nframes)); 2562 2563 if (sc->sc_dying) 2564 return; 2565 2566 if (xfer->status == USBD_IN_PROGRESS) { 2567 /* This request has already been entered into the frame list */ 2568 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2569 /* XXX */ 2570 } 2571 2572 #ifdef DIAGNOSTIC 2573 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2574 printf("uhci_device_isoc_enter: overflow!\n"); 2575 #endif 2576 2577 next = iso->next; 2578 if (next == -1) { 2579 /* Not in use yet, schedule it a few frames ahead. */ 2580 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2581 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2582 } 2583 2584 xfer->status = USBD_IN_PROGRESS; 2585 UXFER(xfer)->curframe = next; 2586 2587 buf = DMAADDR(&xfer->dmabuf, 0); 2588 offs = 0; 2589 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2590 UHCI_TD_ACTIVE | 2591 UHCI_TD_IOS); 2592 nframes = xfer->nframes; 2593 s = splusb(); 2594 for (i = 0; i < nframes; i++) { 2595 std = iso->stds[next]; 2596 if (++next >= UHCI_VFRAMELIST_COUNT) 2597 next = 0; 2598 len = xfer->frlengths[i]; 2599 std->td.td_buffer = htole32(buf); 2600 usb_syncmem(&xfer->dmabuf, offs, len, 2601 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2602 if (i == nframes - 1) 2603 status |= UHCI_TD_IOC; 2604 std->td.td_status = htole32(status); 2605 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2606 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2607 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2608 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2609 #ifdef UHCI_DEBUG 2610 if (uhcidebug > 5) { 2611 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2612 uhci_dump_td(std); 2613 } 2614 #endif 2615 buf += len; 2616 offs += len; 2617 } 2618 iso->next = next; 2619 iso->inuse += xfer->nframes; 2620 2621 splx(s); 2622 } 2623 2624 usbd_status 2625 uhci_device_isoc_start(usbd_xfer_handle xfer) 2626 { 2627 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2628 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2629 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2630 uhci_soft_td_t *end; 2631 int s, i; 2632 2633 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2634 2635 if (sc->sc_dying) 2636 return (USBD_IOERROR); 2637 2638 #ifdef DIAGNOSTIC 2639 if (xfer->status != USBD_IN_PROGRESS) 2640 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2641 #endif 2642 2643 /* Find the last TD */ 2644 i = UXFER(xfer)->curframe + xfer->nframes; 2645 if (i >= UHCI_VFRAMELIST_COUNT) 2646 i -= UHCI_VFRAMELIST_COUNT; 2647 end = upipe->u.iso.stds[i]; 2648 2649 #ifdef DIAGNOSTIC 2650 if (end == NULL) { 2651 printf("uhci_device_isoc_start: end == NULL\n"); 2652 return (USBD_INVAL); 2653 } 2654 #endif 2655 2656 s = splusb(); 2657 2658 /* Set up interrupt info. */ 2659 ii->xfer = xfer; 2660 ii->stdstart = end; 2661 ii->stdend = end; 2662 #ifdef DIAGNOSTIC 2663 if (!ii->isdone) 2664 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2665 ii->isdone = 0; 2666 #endif 2667 uhci_add_intr_info(sc, ii); 2668 2669 splx(s); 2670 2671 return (USBD_IN_PROGRESS); 2672 } 2673 2674 void 2675 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2676 { 2677 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2678 uhci_soft_td_t **stds = upipe->u.iso.stds; 2679 uhci_soft_td_t *std; 2680 int i, n, s, nframes, maxlen, len; 2681 2682 s = splusb(); 2683 2684 /* Transfer is already done. */ 2685 if (xfer->status != USBD_NOT_STARTED && 2686 xfer->status != USBD_IN_PROGRESS) { 2687 splx(s); 2688 return; 2689 } 2690 2691 /* Give xfer the requested abort code. */ 2692 xfer->status = USBD_CANCELLED; 2693 2694 /* make hardware ignore it, */ 2695 nframes = xfer->nframes; 2696 n = UXFER(xfer)->curframe; 2697 maxlen = 0; 2698 for (i = 0; i < nframes; i++) { 2699 std = stds[n]; 2700 usb_syncmem(&std->dma, 2701 std->offs + offsetof(uhci_td_t, td_status), 2702 sizeof(std->td.td_status), 2703 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2704 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2705 usb_syncmem(&std->dma, 2706 std->offs + offsetof(uhci_td_t, td_status), 2707 sizeof(std->td.td_status), 2708 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2709 usb_syncmem(&std->dma, 2710 std->offs + offsetof(uhci_td_t, td_token), 2711 sizeof(std->td.td_token), 2712 BUS_DMASYNC_POSTWRITE); 2713 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2714 if (len > maxlen) 2715 maxlen = len; 2716 if (++n >= UHCI_VFRAMELIST_COUNT) 2717 n = 0; 2718 } 2719 2720 /* and wait until we are sure the hardware has finished. */ 2721 delay(maxlen); 2722 2723 #ifdef DIAGNOSTIC 2724 UXFER(xfer)->iinfo.isdone = 1; 2725 #endif 2726 /* Run callback and remove from interrupt list. */ 2727 usb_transfer_complete(xfer); 2728 2729 splx(s); 2730 } 2731 2732 void 2733 uhci_device_isoc_close(usbd_pipe_handle pipe) 2734 { 2735 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2736 usbd_device_handle dev = upipe->pipe.device; 2737 uhci_softc_t *sc = dev->bus->hci_private; 2738 uhci_soft_td_t *std, *vstd; 2739 struct iso *iso; 2740 int i, s; 2741 2742 /* 2743 * Make sure all TDs are marked as inactive. 2744 * Wait for completion. 2745 * Unschedule. 2746 * Deallocate. 2747 */ 2748 iso = &upipe->u.iso; 2749 2750 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2751 std = iso->stds[i]; 2752 usb_syncmem(&std->dma, 2753 std->offs + offsetof(uhci_td_t, td_status), 2754 sizeof(std->td.td_status), 2755 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2756 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2757 usb_syncmem(&std->dma, 2758 std->offs + offsetof(uhci_td_t, td_status), 2759 sizeof(std->td.td_status), 2760 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2761 } 2762 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2763 2764 s = splusb(); 2765 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2766 std = iso->stds[i]; 2767 for (vstd = sc->sc_vframes[i].htd; 2768 vstd != NULL && vstd->link.std != std; 2769 vstd = vstd->link.std) 2770 ; 2771 if (vstd == NULL) { 2772 /*panic*/ 2773 printf("uhci_device_isoc_close: %p not found\n", std); 2774 splx(s); 2775 return; 2776 } 2777 vstd->link = std->link; 2778 usb_syncmem(&std->dma, 2779 std->offs + offsetof(uhci_td_t, td_link), 2780 sizeof(std->td.td_link), 2781 BUS_DMASYNC_POSTWRITE); 2782 vstd->td.td_link = std->td.td_link; 2783 usb_syncmem(&vstd->dma, 2784 vstd->offs + offsetof(uhci_td_t, td_link), 2785 sizeof(vstd->td.td_link), 2786 BUS_DMASYNC_PREWRITE); 2787 uhci_free_std(sc, std); 2788 } 2789 splx(s); 2790 2791 free(iso->stds, M_USBHC); 2792 } 2793 2794 usbd_status 2795 uhci_setup_isoc(usbd_pipe_handle pipe) 2796 { 2797 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2798 usbd_device_handle dev = upipe->pipe.device; 2799 uhci_softc_t *sc = dev->bus->hci_private; 2800 int addr = upipe->pipe.device->address; 2801 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2802 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2803 uhci_soft_td_t *std, *vstd; 2804 u_int32_t token; 2805 struct iso *iso; 2806 int i, s; 2807 2808 iso = &upipe->u.iso; 2809 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *), 2810 M_USBHC, M_WAITOK); 2811 2812 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2813 UHCI_TD_OUT(0, endpt, addr, 0); 2814 2815 /* Allocate the TDs and mark as inactive; */ 2816 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2817 std = uhci_alloc_std(sc); 2818 if (std == 0) 2819 goto bad; 2820 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2821 std->td.td_token = htole32(token); 2822 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2824 iso->stds[i] = std; 2825 } 2826 2827 /* Insert TDs into schedule. */ 2828 s = splusb(); 2829 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2830 std = iso->stds[i]; 2831 vstd = sc->sc_vframes[i].htd; 2832 usb_syncmem(&vstd->dma, 2833 vstd->offs + offsetof(uhci_td_t, td_link), 2834 sizeof(vstd->td.td_link), 2835 BUS_DMASYNC_POSTWRITE); 2836 std->link = vstd->link; 2837 std->td.td_link = vstd->td.td_link; 2838 usb_syncmem(&std->dma, 2839 std->offs + offsetof(uhci_td_t, td_link), 2840 sizeof(std->td.td_link), 2841 BUS_DMASYNC_PREWRITE); 2842 vstd->link.std = std; 2843 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2844 usb_syncmem(&vstd->dma, 2845 vstd->offs + offsetof(uhci_td_t, td_link), 2846 sizeof(vstd->td.td_link), 2847 BUS_DMASYNC_PREWRITE); 2848 } 2849 splx(s); 2850 2851 iso->next = -1; 2852 iso->inuse = 0; 2853 2854 return (USBD_NORMAL_COMPLETION); 2855 2856 bad: 2857 while (--i >= 0) 2858 uhci_free_std(sc, iso->stds[i]); 2859 free(iso->stds, M_USBHC); 2860 return (USBD_NOMEM); 2861 } 2862 2863 void 2864 uhci_device_isoc_done(usbd_xfer_handle xfer) 2865 { 2866 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2867 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2868 int i, offs; 2869 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2870 2871 2872 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2873 xfer->actlen, xfer->busy_free)); 2874 2875 if (ii->xfer != xfer) 2876 /* Not on interrupt list, ignore it. */ 2877 return; 2878 2879 if (!uhci_active_intr_info(ii)) 2880 return; 2881 2882 #ifdef DIAGNOSTIC 2883 if (ii->stdend == NULL) { 2884 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2885 #ifdef UHCI_DEBUG 2886 uhci_dump_ii(ii); 2887 #endif 2888 return; 2889 } 2890 #endif 2891 2892 /* Turn off the interrupt since it is active even if the TD is not. */ 2893 usb_syncmem(&ii->stdend->dma, 2894 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2895 sizeof(ii->stdend->td.td_status), 2896 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2897 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2898 usb_syncmem(&ii->stdend->dma, 2899 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2900 sizeof(ii->stdend->td.td_status), 2901 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2902 2903 uhci_del_intr_info(ii); /* remove from active list */ 2904 2905 offs = 0; 2906 for (i = 0; i < xfer->nframes; i++) { 2907 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2908 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2909 offs += xfer->frlengths[i]; 2910 } 2911 } 2912 2913 void 2914 uhci_device_intr_done(usbd_xfer_handle xfer) 2915 { 2916 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2917 uhci_softc_t *sc = ii->sc; 2918 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2919 uhci_soft_qh_t *sqh; 2920 int i, npoll, isread; 2921 2922 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 2923 2924 npoll = upipe->u.intr.npoll; 2925 for(i = 0; i < npoll; i++) { 2926 sqh = upipe->u.intr.qhs[i]; 2927 sqh->elink = NULL; 2928 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2929 usb_syncmem(&sqh->dma, 2930 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2931 sizeof(sqh->qh.qh_elink), 2932 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2933 } 2934 uhci_free_std_chain(sc, ii->stdstart, NULL); 2935 2936 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2937 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2938 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2939 2940 /* XXX Wasteful. */ 2941 if (xfer->pipe->repeat) { 2942 uhci_soft_td_t *data, *dataend; 2943 2944 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2945 2946 /* This alloc cannot fail since we freed the chain above. */ 2947 uhci_alloc_std_chain(upipe, sc, xfer->length, 2948 upipe->u.intr.isread, xfer->flags, 2949 &xfer->dmabuf, &data, &dataend); 2950 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2951 usb_syncmem(&dataend->dma, 2952 dataend->offs + offsetof(uhci_td_t, td_status), 2953 sizeof(dataend->td.td_status), 2954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2955 2956 #ifdef UHCI_DEBUG 2957 if (uhcidebug > 10) { 2958 DPRINTF(("uhci_device_intr_done: data(1)\n")); 2959 uhci_dump_tds(data); 2960 uhci_dump_qh(upipe->u.intr.qhs[0]); 2961 } 2962 #endif 2963 2964 ii->stdstart = data; 2965 ii->stdend = dataend; 2966 #ifdef DIAGNOSTIC 2967 if (!ii->isdone) { 2968 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 2969 } 2970 ii->isdone = 0; 2971 #endif 2972 for (i = 0; i < npoll; i++) { 2973 sqh = upipe->u.intr.qhs[i]; 2974 sqh->elink = data; 2975 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2976 usb_syncmem(&sqh->dma, 2977 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2978 sizeof(sqh->qh.qh_elink), 2979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2980 } 2981 xfer->status = USBD_IN_PROGRESS; 2982 /* The ii is already on the examined list, just leave it. */ 2983 } else { 2984 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 2985 if (uhci_active_intr_info(ii)) 2986 uhci_del_intr_info(ii); 2987 } 2988 } 2989 2990 /* Deallocate request data structures */ 2991 void 2992 uhci_device_ctrl_done(usbd_xfer_handle xfer) 2993 { 2994 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2995 uhci_softc_t *sc = ii->sc; 2996 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2997 int len = UGETW(xfer->request.wLength); 2998 int isread = (xfer->request.bmRequestType & UT_READ); 2999 3000 #ifdef DIAGNOSTIC 3001 if (!(xfer->rqflags & URQ_REQUEST)) 3002 panic("uhci_device_ctrl_done: not a request"); 3003 #endif 3004 3005 if (!uhci_active_intr_info(ii)) 3006 return; 3007 3008 uhci_del_intr_info(ii); /* remove from active list */ 3009 3010 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3011 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3012 else 3013 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3014 3015 if (upipe->u.ctl.length != 0) 3016 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3017 3018 if (len) { 3019 usb_syncmem(&xfer->dmabuf, 0, len, 3020 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3021 } 3022 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3023 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3024 3025 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3026 } 3027 3028 /* Deallocate request data structures */ 3029 void 3030 uhci_device_bulk_done(usbd_xfer_handle xfer) 3031 { 3032 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3033 uhci_softc_t *sc = ii->sc; 3034 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3035 3036 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3037 xfer, ii, sc, upipe)); 3038 3039 if (!uhci_active_intr_info(ii)) 3040 return; 3041 3042 uhci_del_intr_info(ii); /* remove from active list */ 3043 3044 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3045 3046 uhci_free_std_chain(sc, ii->stdstart, NULL); 3047 3048 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3049 } 3050 3051 /* Add interrupt QH, called with vflock. */ 3052 void 3053 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3054 { 3055 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3056 uhci_soft_qh_t *eqh; 3057 3058 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3059 3060 eqh = vf->eqh; 3061 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3062 sizeof(eqh->qh.qh_hlink), 3063 BUS_DMASYNC_POSTWRITE); 3064 sqh->hlink = eqh->hlink; 3065 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3066 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3067 sizeof(sqh->qh.qh_hlink), 3068 BUS_DMASYNC_PREWRITE); 3069 eqh->hlink = sqh; 3070 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3071 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3072 sizeof(eqh->qh.qh_hlink), 3073 BUS_DMASYNC_PREWRITE); 3074 vf->eqh = sqh; 3075 vf->bandwidth++; 3076 } 3077 3078 /* Remove interrupt QH. */ 3079 void 3080 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3081 { 3082 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3083 uhci_soft_qh_t *pqh; 3084 3085 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3086 3087 /* See comment in uhci_remove_ctrl() */ 3088 3089 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3090 sizeof(sqh->qh.qh_elink), 3091 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3092 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3093 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3094 usb_syncmem(&sqh->dma, 3095 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3096 sizeof(sqh->qh.qh_elink), 3097 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3098 delay(UHCI_QH_REMOVE_DELAY); 3099 } 3100 3101 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3102 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3103 sizeof(sqh->qh.qh_hlink), 3104 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3105 pqh->hlink = sqh->hlink; 3106 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3107 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3108 sizeof(pqh->qh.qh_hlink), 3109 BUS_DMASYNC_PREWRITE); 3110 delay(UHCI_QH_REMOVE_DELAY); 3111 if (vf->eqh == sqh) 3112 vf->eqh = pqh; 3113 vf->bandwidth--; 3114 } 3115 3116 usbd_status 3117 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3118 { 3119 uhci_soft_qh_t *sqh; 3120 int i, npoll, s; 3121 u_int bestbw, bw, bestoffs, offs; 3122 3123 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3124 if (ival == 0) { 3125 printf("uhci_device_setintr: 0 interval\n"); 3126 return (USBD_INVAL); 3127 } 3128 3129 if (ival > UHCI_VFRAMELIST_COUNT) 3130 ival = UHCI_VFRAMELIST_COUNT; 3131 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3132 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3133 3134 upipe->u.intr.npoll = npoll; 3135 upipe->u.intr.qhs = 3136 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK); 3137 3138 /* 3139 * Figure out which offset in the schedule that has most 3140 * bandwidth left over. 3141 */ 3142 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3143 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3144 for (bw = i = 0; i < npoll; i++) 3145 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3146 if (bw < bestbw) { 3147 bestbw = bw; 3148 bestoffs = offs; 3149 } 3150 } 3151 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3152 3153 for(i = 0; i < npoll; i++) { 3154 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3155 sqh->elink = NULL; 3156 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3157 usb_syncmem(&sqh->dma, 3158 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3159 sizeof(sqh->qh.qh_elink), 3160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3161 sqh->pos = MOD(i * ival + bestoffs); 3162 } 3163 #undef MOD 3164 3165 s = splusb(); 3166 /* Enter QHs into the controller data structures. */ 3167 for(i = 0; i < npoll; i++) 3168 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3169 splx(s); 3170 3171 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3172 return (USBD_NORMAL_COMPLETION); 3173 } 3174 3175 /* Open a new pipe. */ 3176 usbd_status 3177 uhci_open(usbd_pipe_handle pipe) 3178 { 3179 uhci_softc_t *sc = pipe->device->bus->hci_private; 3180 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3181 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3182 usbd_status err; 3183 int ival; 3184 3185 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3186 pipe, pipe->device->address, 3187 ed->bEndpointAddress, sc->sc_addr)); 3188 3189 upipe->aborting = 0; 3190 /* toggle state needed for bulk endpoints */ 3191 upipe->nexttoggle = pipe->endpoint->datatoggle; 3192 3193 if (pipe->device->address == sc->sc_addr) { 3194 switch (ed->bEndpointAddress) { 3195 case USB_CONTROL_ENDPOINT: 3196 pipe->methods = &uhci_root_ctrl_methods; 3197 break; 3198 case UE_DIR_IN | UHCI_INTR_ENDPT: 3199 pipe->methods = &uhci_root_intr_methods; 3200 break; 3201 default: 3202 return (USBD_INVAL); 3203 } 3204 } else { 3205 switch (ed->bmAttributes & UE_XFERTYPE) { 3206 case UE_CONTROL: 3207 pipe->methods = &uhci_device_ctrl_methods; 3208 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3209 if (upipe->u.ctl.sqh == NULL) 3210 goto bad; 3211 upipe->u.ctl.setup = uhci_alloc_std(sc); 3212 if (upipe->u.ctl.setup == NULL) { 3213 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3214 goto bad; 3215 } 3216 upipe->u.ctl.stat = uhci_alloc_std(sc); 3217 if (upipe->u.ctl.stat == NULL) { 3218 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3219 uhci_free_std(sc, upipe->u.ctl.setup); 3220 goto bad; 3221 } 3222 err = usb_allocmem(&sc->sc_bus, 3223 sizeof(usb_device_request_t), 3224 0, &upipe->u.ctl.reqdma); 3225 if (err) { 3226 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3227 uhci_free_std(sc, upipe->u.ctl.setup); 3228 uhci_free_std(sc, upipe->u.ctl.stat); 3229 goto bad; 3230 } 3231 break; 3232 case UE_INTERRUPT: 3233 pipe->methods = &uhci_device_intr_methods; 3234 ival = pipe->interval; 3235 if (ival == USBD_DEFAULT_INTERVAL) 3236 ival = ed->bInterval; 3237 return (uhci_device_setintr(sc, upipe, ival)); 3238 case UE_ISOCHRONOUS: 3239 pipe->methods = &uhci_device_isoc_methods; 3240 return (uhci_setup_isoc(pipe)); 3241 case UE_BULK: 3242 pipe->methods = &uhci_device_bulk_methods; 3243 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3244 if (upipe->u.bulk.sqh == NULL) 3245 goto bad; 3246 break; 3247 } 3248 } 3249 return (USBD_NORMAL_COMPLETION); 3250 3251 bad: 3252 return (USBD_NOMEM); 3253 } 3254 3255 /* 3256 * Data structures and routines to emulate the root hub. 3257 */ 3258 usb_device_descriptor_t uhci_devd = { 3259 USB_DEVICE_DESCRIPTOR_SIZE, 3260 UDESC_DEVICE, /* type */ 3261 {0x00, 0x01}, /* USB version */ 3262 UDCLASS_HUB, /* class */ 3263 UDSUBCLASS_HUB, /* subclass */ 3264 UDPROTO_FSHUB, /* protocol */ 3265 64, /* max packet */ 3266 {0},{0},{0x00,0x01}, /* device id */ 3267 1,2,0, /* string indicies */ 3268 1 /* # of configurations */ 3269 }; 3270 3271 const usb_config_descriptor_t uhci_confd = { 3272 USB_CONFIG_DESCRIPTOR_SIZE, 3273 UDESC_CONFIG, 3274 {USB_CONFIG_DESCRIPTOR_SIZE + 3275 USB_INTERFACE_DESCRIPTOR_SIZE + 3276 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3277 1, 3278 1, 3279 0, 3280 UC_ATTR_MBO | UC_SELF_POWERED, 3281 0 /* max power */ 3282 }; 3283 3284 const usb_interface_descriptor_t uhci_ifcd = { 3285 USB_INTERFACE_DESCRIPTOR_SIZE, 3286 UDESC_INTERFACE, 3287 0, 3288 0, 3289 1, 3290 UICLASS_HUB, 3291 UISUBCLASS_HUB, 3292 UIPROTO_FSHUB, 3293 0 3294 }; 3295 3296 const usb_endpoint_descriptor_t uhci_endpd = { 3297 USB_ENDPOINT_DESCRIPTOR_SIZE, 3298 UDESC_ENDPOINT, 3299 UE_DIR_IN | UHCI_INTR_ENDPT, 3300 UE_INTERRUPT, 3301 {8}, 3302 255 3303 }; 3304 3305 const usb_hub_descriptor_t uhci_hubd_piix = { 3306 USB_HUB_DESCRIPTOR_SIZE, 3307 UDESC_HUB, 3308 2, 3309 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3310 50, /* power on to power good */ 3311 0, 3312 { 0x00 }, /* both ports are removable */ 3313 { 0 }, 3314 }; 3315 3316 /* 3317 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3318 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3319 * should not be used by the USB subsystem. As we cannot issue a 3320 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3321 * will be enabled as part of the reset. 3322 * 3323 * On the VT83C572, the port cannot be successfully enabled until the 3324 * outstanding "port enable change" and "connection status change" 3325 * events have been reset. 3326 */ 3327 Static usbd_status 3328 uhci_portreset(uhci_softc_t *sc, int index) 3329 { 3330 int lim, port, x; 3331 3332 if (index == 1) 3333 port = UHCI_PORTSC1; 3334 else if (index == 2) 3335 port = UHCI_PORTSC2; 3336 else 3337 return (USBD_IOERROR); 3338 3339 x = URWMASK(UREAD2(sc, port)); 3340 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3341 3342 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3343 3344 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3345 index, UREAD2(sc, port))); 3346 3347 x = URWMASK(UREAD2(sc, port)); 3348 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3349 3350 delay(100); 3351 3352 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3353 index, UREAD2(sc, port))); 3354 3355 x = URWMASK(UREAD2(sc, port)); 3356 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3357 3358 for (lim = 10; --lim > 0;) { 3359 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3360 3361 x = UREAD2(sc, port); 3362 3363 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3364 index, lim, x)); 3365 3366 if (!(x & UHCI_PORTSC_CCS)) { 3367 /* 3368 * No device is connected (or was disconnected 3369 * during reset). Consider the port reset. 3370 * The delay must be long enough to ensure on 3371 * the initial iteration that the device 3372 * connection will have been registered. 50ms 3373 * appears to be sufficient, but 20ms is not. 3374 */ 3375 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3376 index, lim)); 3377 break; 3378 } 3379 3380 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3381 /* 3382 * Port enabled changed and/or connection 3383 * status changed were set. Reset either or 3384 * both raised flags (by writing a 1 to that 3385 * bit), and wait again for state to settle. 3386 */ 3387 UWRITE2(sc, port, URWMASK(x) | 3388 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3389 continue; 3390 } 3391 3392 if (x & UHCI_PORTSC_PE) 3393 /* Port is enabled */ 3394 break; 3395 3396 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3397 } 3398 3399 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3400 index, UREAD2(sc, port))); 3401 3402 if (lim <= 0) { 3403 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3404 return (USBD_TIMEOUT); 3405 } 3406 3407 sc->sc_isreset = 1; 3408 return (USBD_NORMAL_COMPLETION); 3409 } 3410 3411 /* 3412 * Simulate a hardware hub by handling all the necessary requests. 3413 */ 3414 usbd_status 3415 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3416 { 3417 usbd_status err; 3418 3419 /* Insert last in queue. */ 3420 err = usb_insert_transfer(xfer); 3421 if (err) 3422 return (err); 3423 3424 /* 3425 * Pipe isn't running (otherwise err would be USBD_INPROG), 3426 * so start it first. 3427 */ 3428 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3429 } 3430 3431 usbd_status 3432 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3433 { 3434 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3435 usb_device_request_t *req; 3436 void *buf = NULL; 3437 int port, x; 3438 int s, len, value, index, status, change, l, totlen = 0; 3439 usb_port_status_t ps; 3440 usbd_status err; 3441 3442 if (sc->sc_dying) 3443 return (USBD_IOERROR); 3444 3445 #ifdef DIAGNOSTIC 3446 if (!(xfer->rqflags & URQ_REQUEST)) 3447 panic("uhci_root_ctrl_transfer: not a request"); 3448 #endif 3449 req = &xfer->request; 3450 3451 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3452 req->bmRequestType, req->bRequest)); 3453 3454 len = UGETW(req->wLength); 3455 value = UGETW(req->wValue); 3456 index = UGETW(req->wIndex); 3457 3458 if (len != 0) 3459 buf = KERNADDR(&xfer->dmabuf, 0); 3460 3461 #define C(x,y) ((x) | ((y) << 8)) 3462 switch(C(req->bRequest, req->bmRequestType)) { 3463 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3464 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3465 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3466 /* 3467 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3468 * for the integrated root hub. 3469 */ 3470 break; 3471 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3472 if (len > 0) { 3473 *(u_int8_t *)buf = sc->sc_conf; 3474 totlen = 1; 3475 } 3476 break; 3477 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3478 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3479 if (len == 0) 3480 break; 3481 switch(value >> 8) { 3482 case UDESC_DEVICE: 3483 if ((value & 0xff) != 0) { 3484 err = USBD_IOERROR; 3485 goto ret; 3486 } 3487 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3488 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3489 memcpy(buf, &uhci_devd, l); 3490 break; 3491 case UDESC_CONFIG: 3492 if ((value & 0xff) != 0) { 3493 err = USBD_IOERROR; 3494 goto ret; 3495 } 3496 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3497 memcpy(buf, &uhci_confd, l); 3498 buf = (char *)buf + l; 3499 len -= l; 3500 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3501 totlen += l; 3502 memcpy(buf, &uhci_ifcd, l); 3503 buf = (char *)buf + l; 3504 len -= l; 3505 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3506 totlen += l; 3507 memcpy(buf, &uhci_endpd, l); 3508 break; 3509 case UDESC_STRING: 3510 #define sd ((usb_string_descriptor_t *)buf) 3511 switch (value & 0xff) { 3512 case 0: /* Language table */ 3513 totlen = usb_makelangtbl(sd, len); 3514 break; 3515 case 1: /* Vendor */ 3516 totlen = usb_makestrdesc(sd, len, 3517 sc->sc_vendor); 3518 break; 3519 case 2: /* Product */ 3520 totlen = usb_makestrdesc(sd, len, 3521 "UHCI root hub"); 3522 break; 3523 } 3524 #undef sd 3525 break; 3526 default: 3527 err = USBD_IOERROR; 3528 goto ret; 3529 } 3530 break; 3531 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3532 if (len > 0) { 3533 *(u_int8_t *)buf = 0; 3534 totlen = 1; 3535 } 3536 break; 3537 case C(UR_GET_STATUS, UT_READ_DEVICE): 3538 if (len > 1) { 3539 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3540 totlen = 2; 3541 } 3542 break; 3543 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3544 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3545 if (len > 1) { 3546 USETW(((usb_status_t *)buf)->wStatus, 0); 3547 totlen = 2; 3548 } 3549 break; 3550 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3551 if (value >= USB_MAX_DEVICES) { 3552 err = USBD_IOERROR; 3553 goto ret; 3554 } 3555 sc->sc_addr = value; 3556 break; 3557 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3558 if (value != 0 && value != 1) { 3559 err = USBD_IOERROR; 3560 goto ret; 3561 } 3562 sc->sc_conf = value; 3563 break; 3564 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3565 break; 3566 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3567 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3568 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3569 err = USBD_IOERROR; 3570 goto ret; 3571 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3572 break; 3573 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3574 break; 3575 /* Hub requests */ 3576 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3577 break; 3578 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3579 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3580 "port=%d feature=%d\n", 3581 index, value)); 3582 if (index == 1) 3583 port = UHCI_PORTSC1; 3584 else if (index == 2) 3585 port = UHCI_PORTSC2; 3586 else { 3587 err = USBD_IOERROR; 3588 goto ret; 3589 } 3590 switch(value) { 3591 case UHF_PORT_ENABLE: 3592 x = URWMASK(UREAD2(sc, port)); 3593 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3594 break; 3595 case UHF_PORT_SUSPEND: 3596 x = URWMASK(UREAD2(sc, port)); 3597 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3598 break; 3599 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3600 /* see USB2 spec ch. 7.1.7.7 */ 3601 usb_delay_ms(&sc->sc_bus, 20); 3602 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3603 /* 10ms resume delay must be provided by caller */ 3604 break; 3605 case UHF_PORT_RESET: 3606 x = URWMASK(UREAD2(sc, port)); 3607 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3608 break; 3609 case UHF_C_PORT_CONNECTION: 3610 x = URWMASK(UREAD2(sc, port)); 3611 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3612 break; 3613 case UHF_C_PORT_ENABLE: 3614 x = URWMASK(UREAD2(sc, port)); 3615 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3616 break; 3617 case UHF_C_PORT_OVER_CURRENT: 3618 x = URWMASK(UREAD2(sc, port)); 3619 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3620 break; 3621 case UHF_C_PORT_RESET: 3622 sc->sc_isreset = 0; 3623 err = USBD_NORMAL_COMPLETION; 3624 goto ret; 3625 case UHF_PORT_CONNECTION: 3626 case UHF_PORT_OVER_CURRENT: 3627 case UHF_PORT_POWER: 3628 case UHF_PORT_LOW_SPEED: 3629 case UHF_C_PORT_SUSPEND: 3630 default: 3631 err = USBD_IOERROR; 3632 goto ret; 3633 } 3634 break; 3635 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3636 if (index == 1) 3637 port = UHCI_PORTSC1; 3638 else if (index == 2) 3639 port = UHCI_PORTSC2; 3640 else { 3641 err = USBD_IOERROR; 3642 goto ret; 3643 } 3644 if (len > 0) { 3645 *(u_int8_t *)buf = 3646 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3647 UHCI_PORTSC_LS_SHIFT; 3648 totlen = 1; 3649 } 3650 break; 3651 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3652 if (len == 0) 3653 break; 3654 if ((value & 0xff) != 0) { 3655 err = USBD_IOERROR; 3656 goto ret; 3657 } 3658 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3659 totlen = l; 3660 memcpy(buf, &uhci_hubd_piix, l); 3661 break; 3662 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3663 if (len != 4) { 3664 err = USBD_IOERROR; 3665 goto ret; 3666 } 3667 memset(buf, 0, len); 3668 totlen = len; 3669 break; 3670 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3671 if (index == 1) 3672 port = UHCI_PORTSC1; 3673 else if (index == 2) 3674 port = UHCI_PORTSC2; 3675 else { 3676 err = USBD_IOERROR; 3677 goto ret; 3678 } 3679 if (len != 4) { 3680 err = USBD_IOERROR; 3681 goto ret; 3682 } 3683 x = UREAD2(sc, port); 3684 status = change = 0; 3685 if (x & UHCI_PORTSC_CCS) 3686 status |= UPS_CURRENT_CONNECT_STATUS; 3687 if (x & UHCI_PORTSC_CSC) 3688 change |= UPS_C_CONNECT_STATUS; 3689 if (x & UHCI_PORTSC_PE) 3690 status |= UPS_PORT_ENABLED; 3691 if (x & UHCI_PORTSC_POEDC) 3692 change |= UPS_C_PORT_ENABLED; 3693 if (x & UHCI_PORTSC_OCI) 3694 status |= UPS_OVERCURRENT_INDICATOR; 3695 if (x & UHCI_PORTSC_OCIC) 3696 change |= UPS_C_OVERCURRENT_INDICATOR; 3697 if (x & UHCI_PORTSC_SUSP) 3698 status |= UPS_SUSPEND; 3699 if (x & UHCI_PORTSC_LSDA) 3700 status |= UPS_LOW_SPEED; 3701 status |= UPS_PORT_POWER; 3702 if (sc->sc_isreset) 3703 change |= UPS_C_PORT_RESET; 3704 USETW(ps.wPortStatus, status); 3705 USETW(ps.wPortChange, change); 3706 l = min(len, sizeof ps); 3707 memcpy(buf, &ps, l); 3708 totlen = l; 3709 break; 3710 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3711 err = USBD_IOERROR; 3712 goto ret; 3713 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3714 break; 3715 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3716 if (index == 1) 3717 port = UHCI_PORTSC1; 3718 else if (index == 2) 3719 port = UHCI_PORTSC2; 3720 else { 3721 err = USBD_IOERROR; 3722 goto ret; 3723 } 3724 switch(value) { 3725 case UHF_PORT_ENABLE: 3726 x = URWMASK(UREAD2(sc, port)); 3727 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3728 break; 3729 case UHF_PORT_SUSPEND: 3730 x = URWMASK(UREAD2(sc, port)); 3731 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3732 break; 3733 case UHF_PORT_RESET: 3734 err = uhci_portreset(sc, index); 3735 goto ret; 3736 case UHF_PORT_POWER: 3737 /* Pretend we turned on power */ 3738 err = USBD_NORMAL_COMPLETION; 3739 goto ret; 3740 case UHF_C_PORT_CONNECTION: 3741 case UHF_C_PORT_ENABLE: 3742 case UHF_C_PORT_OVER_CURRENT: 3743 case UHF_PORT_CONNECTION: 3744 case UHF_PORT_OVER_CURRENT: 3745 case UHF_PORT_LOW_SPEED: 3746 case UHF_C_PORT_SUSPEND: 3747 case UHF_C_PORT_RESET: 3748 default: 3749 err = USBD_IOERROR; 3750 goto ret; 3751 } 3752 break; 3753 default: 3754 err = USBD_IOERROR; 3755 goto ret; 3756 } 3757 xfer->actlen = totlen; 3758 err = USBD_NORMAL_COMPLETION; 3759 ret: 3760 xfer->status = err; 3761 s = splusb(); 3762 usb_transfer_complete(xfer); 3763 splx(s); 3764 return (USBD_IN_PROGRESS); 3765 } 3766 3767 /* Abort a root control request. */ 3768 void 3769 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3770 { 3771 /* Nothing to do, all transfers are synchronous. */ 3772 } 3773 3774 /* Close the root pipe. */ 3775 void 3776 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3777 { 3778 DPRINTF(("uhci_root_ctrl_close\n")); 3779 } 3780 3781 /* Abort a root interrupt request. */ 3782 void 3783 uhci_root_intr_abort(usbd_xfer_handle xfer) 3784 { 3785 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3786 3787 callout_stop(&sc->sc_poll_handle); 3788 sc->sc_intr_xfer = NULL; 3789 3790 if (xfer->pipe->intrxfer == xfer) { 3791 DPRINTF(("uhci_root_intr_abort: remove\n")); 3792 xfer->pipe->intrxfer = 0; 3793 } 3794 xfer->status = USBD_CANCELLED; 3795 #ifdef DIAGNOSTIC 3796 UXFER(xfer)->iinfo.isdone = 1; 3797 #endif 3798 usb_transfer_complete(xfer); 3799 } 3800 3801 usbd_status 3802 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3803 { 3804 usbd_status err; 3805 3806 /* Insert last in queue. */ 3807 err = usb_insert_transfer(xfer); 3808 if (err) 3809 return (err); 3810 3811 /* 3812 * Pipe isn't running (otherwise err would be USBD_INPROG), 3813 * start first 3814 */ 3815 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3816 } 3817 3818 /* Start a transfer on the root interrupt pipe */ 3819 usbd_status 3820 uhci_root_intr_start(usbd_xfer_handle xfer) 3821 { 3822 usbd_pipe_handle pipe = xfer->pipe; 3823 uhci_softc_t *sc = pipe->device->bus->hci_private; 3824 unsigned int ival; 3825 3826 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3827 xfer, xfer->length, xfer->flags)); 3828 3829 if (sc->sc_dying) 3830 return (USBD_IOERROR); 3831 3832 /* XXX temporary variable needed to avoid gcc3 warning */ 3833 ival = xfer->pipe->endpoint->edesc->bInterval; 3834 sc->sc_ival = mstohz(ival); 3835 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3836 sc->sc_intr_xfer = xfer; 3837 return (USBD_IN_PROGRESS); 3838 } 3839 3840 /* Close the root interrupt pipe. */ 3841 void 3842 uhci_root_intr_close(usbd_pipe_handle pipe) 3843 { 3844 uhci_softc_t *sc = pipe->device->bus->hci_private; 3845 3846 callout_stop(&sc->sc_poll_handle); 3847 sc->sc_intr_xfer = NULL; 3848 DPRINTF(("uhci_root_intr_close\n")); 3849 } 3850
Indexes created Tue Sep 23 07:09:52 GMT 2025