uhci.c revision 1.242.8.1
1 /* $NetBSD: uhci.c,v 1.242.8.1 2013/09/26 01:57:22 riz Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/uhci.c,v 1.33 1999/11/17 22:33:41 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.242.8.1 2013/09/26 01:57:22 riz Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/select.h> 55 #include <sys/extent.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/bus.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/uhcireg.h> 69 #include <dev/usb/uhcivar.h> 70 #include <dev/usb/usbroothub_subr.h> 71 72 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 73 /*#define UHCI_CTL_LOOP */ 74 75 76 77 #ifdef UHCI_DEBUG 78 uhci_softc_t *thesc; 79 #define DPRINTF(x) if (uhcidebug) printf x 80 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 81 int uhcidebug = 0; 82 int uhcinoloop = 0; 83 #else 84 #define DPRINTF(x) 85 #define DPRINTFN(n,x) 86 #endif 87 88 /* 89 * The UHCI controller is little endian, so on big endian machines 90 * the data stored in memory needs to be swapped. 91 */ 92 93 struct uhci_pipe { 94 struct usbd_pipe pipe; 95 int nexttoggle; 96 97 u_char aborting; 98 usbd_xfer_handle abortstart, abortend; 99 100 /* Info needed for different pipe kinds. */ 101 union { 102 /* Control pipe */ 103 struct { 104 uhci_soft_qh_t *sqh; 105 usb_dma_t reqdma; 106 uhci_soft_td_t *setup, *stat; 107 u_int length; 108 } ctl; 109 /* Interrupt pipe */ 110 struct { 111 int npoll; 112 int isread; 113 uhci_soft_qh_t **qhs; 114 } intr; 115 /* Bulk pipe */ 116 struct { 117 uhci_soft_qh_t *sqh; 118 u_int length; 119 int isread; 120 } bulk; 121 /* Iso pipe */ 122 struct iso { 123 uhci_soft_td_t **stds; 124 int next, inuse; 125 } iso; 126 } u; 127 }; 128 129 Static void uhci_globalreset(uhci_softc_t *); 130 Static usbd_status uhci_portreset(uhci_softc_t*, int); 131 Static void uhci_reset(uhci_softc_t *); 132 Static usbd_status uhci_run(uhci_softc_t *, int run); 133 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 134 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 135 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 136 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 137 #if 0 138 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 139 uhci_intr_info_t *); 140 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 141 #endif 142 143 Static void uhci_free_std_chain(uhci_softc_t *, 144 uhci_soft_td_t *, uhci_soft_td_t *); 145 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 146 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 147 uhci_soft_td_t **, uhci_soft_td_t **); 148 Static void uhci_poll_hub(void *); 149 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 150 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 151 Static void uhci_idone(uhci_intr_info_t *); 152 153 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 154 155 Static void uhci_timeout(void *); 156 Static void uhci_timeout_task(void *); 157 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 160 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 163 Static void uhci_add_loop(uhci_softc_t *sc); 164 Static void uhci_rem_loop(uhci_softc_t *sc); 165 166 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 167 Static void uhci_device_isoc_enter(usbd_xfer_handle); 168 169 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 170 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 171 172 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 173 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 static __inline uint32_t 267 UREAD4(uhci_softc_t *sc, bus_size_t r) 268 { 269 270 UBARR(sc); 271 return bus_space_read_4(sc->iot, sc->ioh, r); 272 } 273 274 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 275 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 276 277 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 278 279 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 280 281 #define UHCI_INTR_ENDPT 1 282 283 const struct usbd_bus_methods uhci_bus_methods = { 284 uhci_open, 285 uhci_softintr, 286 uhci_poll, 287 uhci_allocm, 288 uhci_freem, 289 uhci_allocx, 290 uhci_freex, 291 }; 292 293 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 294 uhci_root_ctrl_transfer, 295 uhci_root_ctrl_start, 296 uhci_root_ctrl_abort, 297 uhci_root_ctrl_close, 298 uhci_noop, 299 uhci_root_ctrl_done, 300 }; 301 302 const struct usbd_pipe_methods uhci_root_intr_methods = { 303 uhci_root_intr_transfer, 304 uhci_root_intr_start, 305 uhci_root_intr_abort, 306 uhci_root_intr_close, 307 uhci_noop, 308 uhci_root_intr_done, 309 }; 310 311 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 312 uhci_device_ctrl_transfer, 313 uhci_device_ctrl_start, 314 uhci_device_ctrl_abort, 315 uhci_device_ctrl_close, 316 uhci_noop, 317 uhci_device_ctrl_done, 318 }; 319 320 const struct usbd_pipe_methods uhci_device_intr_methods = { 321 uhci_device_intr_transfer, 322 uhci_device_intr_start, 323 uhci_device_intr_abort, 324 uhci_device_intr_close, 325 uhci_device_clear_toggle, 326 uhci_device_intr_done, 327 }; 328 329 const struct usbd_pipe_methods uhci_device_bulk_methods = { 330 uhci_device_bulk_transfer, 331 uhci_device_bulk_start, 332 uhci_device_bulk_abort, 333 uhci_device_bulk_close, 334 uhci_device_clear_toggle, 335 uhci_device_bulk_done, 336 }; 337 338 const struct usbd_pipe_methods uhci_device_isoc_methods = { 339 uhci_device_isoc_transfer, 340 uhci_device_isoc_start, 341 uhci_device_isoc_abort, 342 uhci_device_isoc_close, 343 uhci_noop, 344 uhci_device_isoc_done, 345 }; 346 347 #define uhci_add_intr_info(sc, ii) \ 348 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 349 #define uhci_del_intr_info(ii) \ 350 do { \ 351 LIST_REMOVE((ii), list); \ 352 (ii)->list.le_prev = NULL; \ 353 } while (0) 354 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 355 356 static inline uhci_soft_qh_t * 357 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 358 { 359 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 360 361 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 362 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 363 usb_syncmem(&pqh->dma, 364 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 365 sizeof(pqh->qh.qh_hlink), 366 BUS_DMASYNC_POSTWRITE); 367 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 368 printf("uhci_find_prev_qh: QH not found\n"); 369 return (NULL); 370 } 371 #endif 372 } 373 return (pqh); 374 } 375 376 void 377 uhci_globalreset(uhci_softc_t *sc) 378 { 379 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 380 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 381 UHCICMD(sc, 0); /* do nothing */ 382 } 383 384 usbd_status 385 uhci_init(uhci_softc_t *sc) 386 { 387 usbd_status err; 388 int i, j; 389 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 390 uhci_soft_td_t *std; 391 392 DPRINTFN(1,("uhci_init: start\n")); 393 394 #ifdef UHCI_DEBUG 395 thesc = sc; 396 397 if (uhcidebug > 2) 398 uhci_dumpregs(sc); 399 #endif 400 401 sc->sc_suspend = PWR_RESUME; 402 403 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 404 uhci_globalreset(sc); /* reset the controller */ 405 uhci_reset(sc); 406 407 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 408 USB_MEM_RESERVE); 409 410 /* Allocate and initialize real frame array. */ 411 err = usb_allocmem(&sc->sc_bus, 412 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 413 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 414 if (err) 415 return (err); 416 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 417 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 418 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 419 420 /* 421 * Allocate a TD, inactive, that hangs from the last QH. 422 * This is to avoid a bug in the PIIX that makes it run berserk 423 * otherwise. 424 */ 425 std = uhci_alloc_std(sc); 426 if (std == NULL) 427 return (USBD_NOMEM); 428 std->link.std = NULL; 429 std->td.td_link = htole32(UHCI_PTR_T); 430 std->td.td_status = htole32(0); /* inactive */ 431 std->td.td_token = htole32(0); 432 std->td.td_buffer = htole32(0); 433 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 434 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 435 436 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 437 lsqh = uhci_alloc_sqh(sc); 438 if (lsqh == NULL) 439 return (USBD_NOMEM); 440 lsqh->hlink = NULL; 441 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 442 lsqh->elink = std; 443 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 444 sc->sc_last_qh = lsqh; 445 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 446 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 447 448 /* Allocate the dummy QH where bulk traffic will be queued. */ 449 bsqh = uhci_alloc_sqh(sc); 450 if (bsqh == NULL) 451 return (USBD_NOMEM); 452 bsqh->hlink = lsqh; 453 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 454 bsqh->elink = NULL; 455 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 456 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 457 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 459 460 /* Allocate dummy QH where high speed control traffic will be queued. */ 461 chsqh = uhci_alloc_sqh(sc); 462 if (chsqh == NULL) 463 return (USBD_NOMEM); 464 chsqh->hlink = bsqh; 465 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 466 chsqh->elink = NULL; 467 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 468 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 469 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 470 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 471 472 /* Allocate dummy QH where control traffic will be queued. */ 473 clsqh = uhci_alloc_sqh(sc); 474 if (clsqh == NULL) 475 return (USBD_NOMEM); 476 clsqh->hlink = chsqh; 477 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 478 clsqh->elink = NULL; 479 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 480 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 481 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 483 484 /* 485 * Make all (virtual) frame list pointers point to the interrupt 486 * queue heads and the interrupt queue heads at the control 487 * queue head and point the physical frame list to the virtual. 488 */ 489 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 490 std = uhci_alloc_std(sc); 491 sqh = uhci_alloc_sqh(sc); 492 if (std == NULL || sqh == NULL) 493 return (USBD_NOMEM); 494 std->link.sqh = sqh; 495 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 496 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 497 std->td.td_token = htole32(0); 498 std->td.td_buffer = htole32(0); 499 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 500 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 501 sqh->hlink = clsqh; 502 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 503 sqh->elink = NULL; 504 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 sc->sc_vframes[i].htd = std; 508 sc->sc_vframes[i].etd = std; 509 sc->sc_vframes[i].hqh = sqh; 510 sc->sc_vframes[i].eqh = sqh; 511 for (j = i; 512 j < UHCI_FRAMELIST_COUNT; 513 j += UHCI_VFRAMELIST_COUNT) 514 sc->sc_pframes[j] = htole32(std->physaddr); 515 } 516 usb_syncmem(&sc->sc_dma, 0, 517 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 518 BUS_DMASYNC_PREWRITE); 519 520 521 LIST_INIT(&sc->sc_intrhead); 522 523 SIMPLEQ_INIT(&sc->sc_free_xfers); 524 525 callout_init(&sc->sc_poll_handle, 0); 526 527 /* Set up the bus struct. */ 528 sc->sc_bus.methods = &uhci_bus_methods; 529 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 530 531 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 532 533 DPRINTFN(1,("uhci_init: enabling\n")); 534 535 err = uhci_run(sc, 1); /* and here we go... */ 536 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 537 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 538 return err; 539 } 540 541 int 542 uhci_activate(device_t self, enum devact act) 543 { 544 struct uhci_softc *sc = device_private(self); 545 546 switch (act) { 547 case DVACT_DEACTIVATE: 548 sc->sc_dying = 1; 549 return 0; 550 default: 551 return EOPNOTSUPP; 552 } 553 } 554 555 void 556 uhci_childdet(device_t self, device_t child) 557 { 558 struct uhci_softc *sc = device_private(self); 559 560 KASSERT(sc->sc_child == child); 561 sc->sc_child = NULL; 562 } 563 564 int 565 uhci_detach(struct uhci_softc *sc, int flags) 566 { 567 usbd_xfer_handle xfer; 568 int rv = 0; 569 570 if (sc->sc_child != NULL) 571 rv = config_detach(sc->sc_child, flags); 572 573 if (rv != 0) 574 return (rv); 575 576 /* Free all xfers associated with this HC. */ 577 for (;;) { 578 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 579 if (xfer == NULL) 580 break; 581 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 582 free(xfer, M_USB); 583 } 584 585 callout_halt(&sc->sc_poll_handle, NULL); 586 callout_destroy(&sc->sc_poll_handle); 587 588 /* XXX free other data structures XXX */ 589 590 return (rv); 591 } 592 593 usbd_status 594 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 595 { 596 struct uhci_softc *sc = bus->hci_private; 597 usbd_status status; 598 u_int32_t n; 599 600 /* 601 * XXX 602 * Since we are allocating a buffer we can assume that we will 603 * need TDs for it. Since we don't want to allocate those from 604 * an interrupt context, we allocate them here and free them again. 605 * This is no guarantee that we'll get the TDs next time... 606 */ 607 n = size / 8; 608 if (n > 16) { 609 u_int32_t i; 610 uhci_soft_td_t **stds; 611 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 612 stds = malloc(sizeof(uhci_soft_td_t *) * n, M_TEMP, 613 M_WAITOK|M_ZERO); 614 for(i=0; i < n; i++) 615 stds[i] = uhci_alloc_std(sc); 616 for(i=0; i < n; i++) 617 if (stds[i] != NULL) 618 uhci_free_std(sc, stds[i]); 619 free(stds, M_TEMP); 620 } 621 622 623 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 624 if (status == USBD_NOMEM) 625 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 626 return status; 627 } 628 629 void 630 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 631 { 632 if (dma->block->flags & USB_DMA_RESERVE) { 633 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 634 dma); 635 return; 636 } 637 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 638 } 639 640 usbd_xfer_handle 641 uhci_allocx(struct usbd_bus *bus) 642 { 643 struct uhci_softc *sc = bus->hci_private; 644 usbd_xfer_handle xfer; 645 646 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 647 if (xfer != NULL) { 648 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 649 #ifdef DIAGNOSTIC 650 if (xfer->busy_free != XFER_FREE) { 651 printf("uhci_allocx: xfer=%p not free, 0x%08x\n", xfer, 652 xfer->busy_free); 653 } 654 #endif 655 } else { 656 xfer = malloc(sizeof(struct uhci_xfer), M_USB, M_NOWAIT); 657 } 658 if (xfer != NULL) { 659 memset(xfer, 0, sizeof (struct uhci_xfer)); 660 UXFER(xfer)->iinfo.sc = sc; 661 #ifdef DIAGNOSTIC 662 UXFER(xfer)->iinfo.isdone = 1; 663 xfer->busy_free = XFER_BUSY; 664 #endif 665 } 666 return (xfer); 667 } 668 669 void 670 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 671 { 672 struct uhci_softc *sc = bus->hci_private; 673 674 #ifdef DIAGNOSTIC 675 if (xfer->busy_free != XFER_BUSY) { 676 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 677 xfer->busy_free); 678 } 679 xfer->busy_free = XFER_FREE; 680 if (!UXFER(xfer)->iinfo.isdone) { 681 printf("uhci_freex: !isdone\n"); 682 } 683 #endif 684 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 685 } 686 687 /* 688 * Handle suspend/resume. 689 * 690 * We need to switch to polling mode here, because this routine is 691 * called from an interrupt context. This is all right since we 692 * are almost suspended anyway. 693 */ 694 bool 695 uhci_resume(device_t dv, const pmf_qual_t *qual) 696 { 697 uhci_softc_t *sc = device_private(dv); 698 int cmd; 699 int s; 700 701 s = splhardusb(); 702 703 cmd = UREAD2(sc, UHCI_CMD); 704 sc->sc_bus.use_polling++; 705 UWRITE2(sc, UHCI_INTR, 0); 706 uhci_globalreset(sc); 707 uhci_reset(sc); 708 if (cmd & UHCI_CMD_RS) 709 uhci_run(sc, 0); 710 711 /* restore saved state */ 712 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 713 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 714 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 715 716 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 717 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 718 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 719 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 720 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 721 UHCICMD(sc, UHCI_CMD_MAXP); 722 uhci_run(sc, 1); /* and start traffic again */ 723 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 724 sc->sc_bus.use_polling--; 725 if (sc->sc_intr_xfer != NULL) 726 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 727 sc->sc_intr_xfer); 728 #ifdef UHCI_DEBUG 729 if (uhcidebug > 2) 730 uhci_dumpregs(sc); 731 #endif 732 733 sc->sc_suspend = PWR_RESUME; 734 splx(s); 735 736 return true; 737 } 738 739 bool 740 uhci_suspend(device_t dv, const pmf_qual_t *qual) 741 { 742 uhci_softc_t *sc = device_private(dv); 743 int cmd; 744 int s; 745 746 s = splhardusb(); 747 748 cmd = UREAD2(sc, UHCI_CMD); 749 750 #ifdef UHCI_DEBUG 751 if (uhcidebug > 2) 752 uhci_dumpregs(sc); 753 #endif 754 if (sc->sc_intr_xfer != NULL) 755 callout_stop(&sc->sc_poll_handle); 756 sc->sc_suspend = PWR_SUSPEND; 757 sc->sc_bus.use_polling++; 758 759 uhci_run(sc, 0); /* stop the controller */ 760 cmd &= ~UHCI_CMD_RS; 761 762 /* save some state if BIOS doesn't */ 763 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 764 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 765 766 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 767 768 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 769 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 770 sc->sc_bus.use_polling--; 771 772 splx(s); 773 774 return true; 775 } 776 777 #ifdef UHCI_DEBUG 778 Static void 779 uhci_dumpregs(uhci_softc_t *sc) 780 { 781 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 782 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 783 device_xname(sc->sc_dev), 784 UREAD2(sc, UHCI_CMD), 785 UREAD2(sc, UHCI_STS), 786 UREAD2(sc, UHCI_INTR), 787 UREAD2(sc, UHCI_FRNUM), 788 UREAD4(sc, UHCI_FLBASEADDR), 789 UREAD1(sc, UHCI_SOF), 790 UREAD2(sc, UHCI_PORTSC1), 791 UREAD2(sc, UHCI_PORTSC2))); 792 } 793 794 void 795 uhci_dump_td(uhci_soft_td_t *p) 796 { 797 char sbuf[128], sbuf2[128]; 798 799 800 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 801 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 802 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 803 "token=0x%08lx buffer=0x%08lx\n", 804 p, (long)p->physaddr, 805 (long)le32toh(p->td.td_link), 806 (long)le32toh(p->td.td_status), 807 (long)le32toh(p->td.td_token), 808 (long)le32toh(p->td.td_buffer))); 809 810 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 811 (u_int32_t)le32toh(p->td.td_link)); 812 snprintb(sbuf2, sizeof(sbuf2), 813 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 814 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 815 (u_int32_t)le32toh(p->td.td_status)); 816 817 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 818 "D=%d,maxlen=%d\n", sbuf, sbuf2, 819 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 820 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 821 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 822 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 823 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 824 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 825 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 826 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 827 BUS_DMASYNC_PREREAD); 828 } 829 830 void 831 uhci_dump_qh(uhci_soft_qh_t *sqh) 832 { 833 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 834 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 835 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 836 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 837 le32toh(sqh->qh.qh_elink))); 838 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 839 } 840 841 842 #if 1 843 void 844 uhci_dump(void) 845 { 846 uhci_dump_all(thesc); 847 } 848 #endif 849 850 void 851 uhci_dump_all(uhci_softc_t *sc) 852 { 853 uhci_dumpregs(sc); 854 printf("intrs=%d\n", sc->sc_bus.no_intrs); 855 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 856 uhci_dump_qh(sc->sc_lctl_start); 857 } 858 859 860 void 861 uhci_dump_qhs(uhci_soft_qh_t *sqh) 862 { 863 uhci_dump_qh(sqh); 864 865 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 866 * Traverses sideways first, then down. 867 * 868 * QH1 869 * QH2 870 * No QH 871 * TD2.1 872 * TD2.2 873 * TD1.1 874 * etc. 875 * 876 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 877 */ 878 879 880 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 881 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 882 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 883 uhci_dump_qhs(sqh->hlink); 884 else 885 DPRINTF(("No QH\n")); 886 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 887 888 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 889 uhci_dump_tds(sqh->elink); 890 else 891 DPRINTF(("No TD\n")); 892 } 893 894 void 895 uhci_dump_tds(uhci_soft_td_t *std) 896 { 897 uhci_soft_td_t *td; 898 int stop; 899 900 for(td = std; td != NULL; td = td->link.std) { 901 uhci_dump_td(td); 902 903 /* Check whether the link pointer in this TD marks 904 * the link pointer as end of queue. This avoids 905 * printing the free list in case the queue/TD has 906 * already been moved there (seatbelt). 907 */ 908 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 909 sizeof(td->td.td_link), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 912 le32toh(td->td.td_link) == 0); 913 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 914 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 915 if (stop) 916 break; 917 } 918 } 919 920 Static void 921 uhci_dump_ii(uhci_intr_info_t *ii) 922 { 923 usbd_pipe_handle pipe; 924 usb_endpoint_descriptor_t *ed; 925 usbd_device_handle dev; 926 927 #ifdef DIAGNOSTIC 928 #define DONE ii->isdone 929 #else 930 #define DONE 0 931 #endif 932 if (ii == NULL) { 933 printf("ii NULL\n"); 934 return; 935 } 936 if (ii->xfer == NULL) { 937 printf("ii %p: done=%d xfer=NULL\n", 938 ii, DONE); 939 return; 940 } 941 pipe = ii->xfer->pipe; 942 if (pipe == NULL) { 943 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 944 ii, DONE, ii->xfer); 945 return; 946 } 947 if (pipe->endpoint == NULL) { 948 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 949 ii, DONE, ii->xfer, pipe); 950 return; 951 } 952 if (pipe->device == NULL) { 953 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 954 ii, DONE, ii->xfer, pipe); 955 return; 956 } 957 ed = pipe->endpoint->edesc; 958 dev = pipe->device; 959 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 960 ii, DONE, ii->xfer, dev, 961 UGETW(dev->ddesc.idVendor), 962 UGETW(dev->ddesc.idProduct), 963 dev->address, pipe, 964 ed->bEndpointAddress, ed->bmAttributes); 965 #undef DONE 966 } 967 968 void uhci_dump_iis(struct uhci_softc *sc); 969 void 970 uhci_dump_iis(struct uhci_softc *sc) 971 { 972 uhci_intr_info_t *ii; 973 974 printf("intr_info list:\n"); 975 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 976 uhci_dump_ii(ii); 977 } 978 979 void iidump(void); 980 void iidump(void) { uhci_dump_iis(thesc); } 981 982 #endif 983 984 /* 985 * This routine is executed periodically and simulates interrupts 986 * from the root controller interrupt pipe for port status change. 987 */ 988 void 989 uhci_poll_hub(void *addr) 990 { 991 usbd_xfer_handle xfer = addr; 992 usbd_pipe_handle pipe = xfer->pipe; 993 uhci_softc_t *sc; 994 int s; 995 u_char *p; 996 997 DPRINTFN(20, ("uhci_poll_hub\n")); 998 999 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1000 return; /* device has detached */ 1001 sc = pipe->device->bus->hci_private; 1002 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1003 1004 p = KERNADDR(&xfer->dmabuf, 0); 1005 p[0] = 0; 1006 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<1; 1008 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<2; 1010 if (p[0] == 0) 1011 /* No change, try again in a while */ 1012 return; 1013 1014 xfer->actlen = 1; 1015 xfer->status = USBD_NORMAL_COMPLETION; 1016 s = splusb(); 1017 xfer->device->bus->intr_context++; 1018 usb_transfer_complete(xfer); 1019 xfer->device->bus->intr_context--; 1020 splx(s); 1021 } 1022 1023 void 1024 uhci_root_intr_done(usbd_xfer_handle xfer) 1025 { 1026 } 1027 1028 void 1029 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1030 { 1031 } 1032 1033 /* 1034 * Let the last QH loop back to the high speed control transfer QH. 1035 * This is what intel calls "bandwidth reclamation" and improves 1036 * USB performance a lot for some devices. 1037 * If we are already looping, just count it. 1038 */ 1039 void 1040 uhci_add_loop(uhci_softc_t *sc) { 1041 #ifdef UHCI_DEBUG 1042 if (uhcinoloop) 1043 return; 1044 #endif 1045 if (++sc->sc_loops == 1) { 1046 DPRINTFN(5,("uhci_start_loop: add\n")); 1047 /* Note, we don't loop back the soft pointer. */ 1048 sc->sc_last_qh->qh.qh_hlink = 1049 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1050 usb_syncmem(&sc->sc_last_qh->dma, 1051 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1052 sizeof(sc->sc_last_qh->qh.qh_hlink), 1053 BUS_DMASYNC_PREWRITE); 1054 } 1055 } 1056 1057 void 1058 uhci_rem_loop(uhci_softc_t *sc) { 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (--sc->sc_loops == 0) { 1064 DPRINTFN(5,("uhci_end_loop: remove\n")); 1065 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1066 usb_syncmem(&sc->sc_last_qh->dma, 1067 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1068 sizeof(sc->sc_last_qh->qh.qh_hlink), 1069 BUS_DMASYNC_PREWRITE); 1070 } 1071 } 1072 1073 /* Add high speed control QH, called at splusb(). */ 1074 void 1075 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1076 { 1077 uhci_soft_qh_t *eqh; 1078 1079 SPLUSBCHECK; 1080 1081 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1082 eqh = sc->sc_hctl_end; 1083 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1084 sizeof(eqh->qh.qh_hlink), 1085 BUS_DMASYNC_POSTWRITE); 1086 sqh->hlink = eqh->hlink; 1087 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1088 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1089 BUS_DMASYNC_PREWRITE); 1090 eqh->hlink = sqh; 1091 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1092 sc->sc_hctl_end = sqh; 1093 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1094 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1095 #ifdef UHCI_CTL_LOOP 1096 uhci_add_loop(sc); 1097 #endif 1098 } 1099 1100 /* Remove high speed control QH, called at splusb(). */ 1101 void 1102 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1103 { 1104 uhci_soft_qh_t *pqh; 1105 uint32_t elink; 1106 1107 SPLUSBCHECK; 1108 1109 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1110 #ifdef UHCI_CTL_LOOP 1111 uhci_rem_loop(sc); 1112 #endif 1113 /* 1114 * The T bit should be set in the elink of the QH so that the HC 1115 * doesn't follow the pointer. This condition may fail if the 1116 * the transferred packet was short so that the QH still points 1117 * at the last used TD. 1118 * In this case we set the T bit and wait a little for the HC 1119 * to stop looking at the TD. 1120 * Note that if the TD chain is large enough, the controller 1121 * may still be looking at the chain at the end of this function. 1122 * uhci_free_std_chain() will make sure the controller stops 1123 * looking at it quickly, but until then we should not change 1124 * sqh->hlink. 1125 */ 1126 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1127 sizeof(sqh->qh.qh_elink), 1128 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1129 elink = le32toh(sqh->qh.qh_elink); 1130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1131 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1132 if (!(elink & UHCI_PTR_T)) { 1133 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1134 usb_syncmem(&sqh->dma, 1135 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1136 sizeof(sqh->qh.qh_elink), 1137 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1138 delay(UHCI_QH_REMOVE_DELAY); 1139 } 1140 1141 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1142 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1143 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1144 pqh->hlink = sqh->hlink; 1145 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1146 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1147 sizeof(pqh->qh.qh_hlink), 1148 BUS_DMASYNC_PREWRITE); 1149 delay(UHCI_QH_REMOVE_DELAY); 1150 if (sc->sc_hctl_end == sqh) 1151 sc->sc_hctl_end = pqh; 1152 } 1153 1154 /* Add low speed control QH, called at splusb(). */ 1155 void 1156 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1157 { 1158 uhci_soft_qh_t *eqh; 1159 1160 SPLUSBCHECK; 1161 1162 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1163 eqh = sc->sc_lctl_end; 1164 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1165 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1166 sqh->hlink = eqh->hlink; 1167 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1168 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1169 BUS_DMASYNC_PREWRITE); 1170 eqh->hlink = sqh; 1171 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1172 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1173 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1174 sc->sc_lctl_end = sqh; 1175 } 1176 1177 /* Remove low speed control QH, called at splusb(). */ 1178 void 1179 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1180 { 1181 uhci_soft_qh_t *pqh; 1182 uint32_t elink; 1183 1184 SPLUSBCHECK; 1185 1186 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1187 /* See comment in uhci_remove_hs_ctrl() */ 1188 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1189 sizeof(sqh->qh.qh_elink), 1190 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1191 elink = le32toh(sqh->qh.qh_elink); 1192 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1193 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1194 if (!(elink & UHCI_PTR_T)) { 1195 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1196 usb_syncmem(&sqh->dma, 1197 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1198 sizeof(sqh->qh.qh_elink), 1199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1200 delay(UHCI_QH_REMOVE_DELAY); 1201 } 1202 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1203 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1204 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1205 pqh->hlink = sqh->hlink; 1206 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1207 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1208 sizeof(pqh->qh.qh_hlink), 1209 BUS_DMASYNC_PREWRITE); 1210 delay(UHCI_QH_REMOVE_DELAY); 1211 if (sc->sc_lctl_end == sqh) 1212 sc->sc_lctl_end = pqh; 1213 } 1214 1215 /* Add bulk QH, called at splusb(). */ 1216 void 1217 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1218 { 1219 uhci_soft_qh_t *eqh; 1220 1221 SPLUSBCHECK; 1222 1223 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1224 eqh = sc->sc_bulk_end; 1225 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1226 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1227 sqh->hlink = eqh->hlink; 1228 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1229 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1230 BUS_DMASYNC_PREWRITE); 1231 eqh->hlink = sqh; 1232 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1233 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1234 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1235 sc->sc_bulk_end = sqh; 1236 uhci_add_loop(sc); 1237 } 1238 1239 /* Remove bulk QH, called at splusb(). */ 1240 void 1241 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1242 { 1243 uhci_soft_qh_t *pqh; 1244 1245 SPLUSBCHECK; 1246 1247 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1248 uhci_rem_loop(sc); 1249 /* See comment in uhci_remove_hs_ctrl() */ 1250 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1251 sizeof(sqh->qh.qh_elink), 1252 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1253 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1254 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1255 usb_syncmem(&sqh->dma, 1256 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1257 sizeof(sqh->qh.qh_elink), 1258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1259 delay(UHCI_QH_REMOVE_DELAY); 1260 } 1261 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1262 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1263 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1264 pqh->hlink = sqh->hlink; 1265 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1266 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1267 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1268 delay(UHCI_QH_REMOVE_DELAY); 1269 if (sc->sc_bulk_end == sqh) 1270 sc->sc_bulk_end = pqh; 1271 } 1272 1273 Static int uhci_intr1(uhci_softc_t *); 1274 1275 int 1276 uhci_intr(void *arg) 1277 { 1278 uhci_softc_t *sc = arg; 1279 1280 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1281 return (0); 1282 1283 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1284 #ifdef DIAGNOSTIC 1285 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1286 #endif 1287 return (0); 1288 } 1289 1290 return (uhci_intr1(sc)); 1291 } 1292 1293 int 1294 uhci_intr1(uhci_softc_t *sc) 1295 { 1296 int status; 1297 int ack; 1298 1299 #ifdef UHCI_DEBUG 1300 if (uhcidebug > 15) { 1301 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1302 uhci_dumpregs(sc); 1303 } 1304 #endif 1305 1306 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1307 if (status == 0) /* The interrupt was not for us. */ 1308 return (0); 1309 1310 if (sc->sc_suspend != PWR_RESUME) { 1311 #ifdef DIAGNOSTIC 1312 printf("%s: interrupt while not operating ignored\n", 1313 device_xname(sc->sc_dev)); 1314 #endif 1315 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1316 return (0); 1317 } 1318 1319 ack = 0; 1320 if (status & UHCI_STS_USBINT) 1321 ack |= UHCI_STS_USBINT; 1322 if (status & UHCI_STS_USBEI) 1323 ack |= UHCI_STS_USBEI; 1324 if (status & UHCI_STS_RD) { 1325 ack |= UHCI_STS_RD; 1326 #ifdef UHCI_DEBUG 1327 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1328 #endif 1329 } 1330 if (status & UHCI_STS_HSE) { 1331 ack |= UHCI_STS_HSE; 1332 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1333 } 1334 if (status & UHCI_STS_HCPE) { 1335 ack |= UHCI_STS_HCPE; 1336 printf("%s: host controller process error\n", 1337 device_xname(sc->sc_dev)); 1338 } 1339 1340 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1341 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1342 /* no acknowledge needed */ 1343 if (!sc->sc_dying) { 1344 printf("%s: host controller halted\n", 1345 device_xname(sc->sc_dev)); 1346 #ifdef UHCI_DEBUG 1347 uhci_dump_all(sc); 1348 #endif 1349 } 1350 sc->sc_dying = 1; 1351 } 1352 1353 if (!ack) 1354 return (0); /* nothing to acknowledge */ 1355 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1356 1357 sc->sc_bus.no_intrs++; 1358 usb_schedsoftintr(&sc->sc_bus); 1359 1360 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1361 1362 return (1); 1363 } 1364 1365 void 1366 uhci_softintr(void *v) 1367 { 1368 struct usbd_bus *bus = v; 1369 uhci_softc_t *sc = bus->hci_private; 1370 uhci_intr_info_t *ii, *nextii; 1371 1372 DPRINTFN(10,("%s: uhci_softintr (%d)\n", device_xname(sc->sc_dev), 1373 sc->sc_bus.intr_context)); 1374 1375 sc->sc_bus.intr_context++; 1376 1377 /* 1378 * Interrupts on UHCI really suck. When the host controller 1379 * interrupts because a transfer is completed there is no 1380 * way of knowing which transfer it was. You can scan down 1381 * the TDs and QHs of the previous frame to limit the search, 1382 * but that assumes that the interrupt was not delayed by more 1383 * than 1 ms, which may not always be true (e.g. after debug 1384 * output on a slow console). 1385 * We scan all interrupt descriptors to see if any have 1386 * completed. 1387 */ 1388 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1389 nextii = LIST_NEXT(ii, list); 1390 uhci_check_intr(sc, ii); 1391 } 1392 1393 #ifdef USB_USE_SOFTINTR 1394 if (sc->sc_softwake) { 1395 sc->sc_softwake = 0; 1396 wakeup(&sc->sc_softwake); 1397 } 1398 #endif /* USB_USE_SOFTINTR */ 1399 1400 sc->sc_bus.intr_context--; 1401 } 1402 1403 /* Check for an interrupt. */ 1404 void 1405 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1406 { 1407 uhci_soft_td_t *std, *lstd; 1408 u_int32_t status; 1409 1410 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1411 #ifdef DIAGNOSTIC 1412 if (ii == NULL) { 1413 printf("uhci_check_intr: no ii? %p\n", ii); 1414 return; 1415 } 1416 #endif 1417 if (ii->xfer->status == USBD_CANCELLED || 1418 ii->xfer->status == USBD_TIMEOUT) { 1419 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1420 return; 1421 } 1422 1423 if (ii->stdstart == NULL) 1424 return; 1425 lstd = ii->stdend; 1426 #ifdef DIAGNOSTIC 1427 if (lstd == NULL) { 1428 printf("uhci_check_intr: std==0\n"); 1429 return; 1430 } 1431 #endif 1432 usb_syncmem(&lstd->dma, 1433 lstd->offs + offsetof(uhci_td_t, td_status), 1434 sizeof(lstd->td.td_status), 1435 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1436 status = le32toh(lstd->td.td_status); 1437 usb_syncmem(&lstd->dma, 1438 lstd->offs + offsetof(uhci_td_t, td_status), 1439 sizeof(lstd->td.td_status), 1440 BUS_DMASYNC_PREREAD); 1441 1442 /* If the last TD is not marked active we can complete */ 1443 if (!(status & UHCI_TD_ACTIVE)) { 1444 done: 1445 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1446 callout_stop(&ii->xfer->timeout_handle); 1447 uhci_idone(ii); 1448 return; 1449 } 1450 1451 /* 1452 * If the last TD is still active we need to check whether there 1453 * is an error somewhere in the middle, or whether there was a 1454 * short packet (SPD and not ACTIVE). 1455 */ 1456 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1457 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1458 usb_syncmem(&std->dma, 1459 std->offs + offsetof(uhci_td_t, td_status), 1460 sizeof(std->td.td_status), 1461 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1462 status = le32toh(std->td.td_status); 1463 usb_syncmem(&std->dma, 1464 std->offs + offsetof(uhci_td_t, td_status), 1465 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1466 1467 /* If there's an active TD the xfer isn't done. */ 1468 if (status & UHCI_TD_ACTIVE) { 1469 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1470 __func__, ii, std)); 1471 return; 1472 } 1473 1474 /* Any kind of error makes the xfer done. */ 1475 if (status & UHCI_TD_STALLED) 1476 goto done; 1477 1478 /* 1479 * If the data phase of a control transfer is short, we need 1480 * to complete the status stage 1481 */ 1482 usbd_xfer_handle xfer = ii->xfer; 1483 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1484 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1485 1486 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1487 struct uhci_pipe *upipe = 1488 (struct uhci_pipe *)xfer->pipe; 1489 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1490 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1491 1492 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1493 "phase needs completion\n", __func__, ii, 1494 ii->stdstart)); 1495 1496 sqh->qh.qh_elink = 1497 htole32(stat->physaddr | UHCI_PTR_TD); 1498 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1499 BUS_DMASYNC_PREWRITE); 1500 break; 1501 } 1502 1503 /* We want short packets, and it is short: it's done */ 1504 usb_syncmem(&std->dma, 1505 std->offs + offsetof(uhci_td_t, td_token), 1506 sizeof(std->td.td_token), 1507 BUS_DMASYNC_POSTWRITE); 1508 1509 if ((status & UHCI_TD_SPD) && 1510 UHCI_TD_GET_ACTLEN(status) < 1511 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1512 goto done; 1513 } 1514 } 1515 } 1516 1517 /* Called at splusb() */ 1518 void 1519 uhci_idone(uhci_intr_info_t *ii) 1520 { 1521 usbd_xfer_handle xfer = ii->xfer; 1522 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1523 uhci_soft_td_t *std; 1524 u_int32_t status = 0, nstatus; 1525 int actlen; 1526 1527 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1528 #ifdef DIAGNOSTIC 1529 { 1530 int s = splhigh(); 1531 if (ii->isdone) { 1532 splx(s); 1533 #ifdef UHCI_DEBUG 1534 printf("uhci_idone: ii is done!\n "); 1535 uhci_dump_ii(ii); 1536 #else 1537 printf("uhci_idone: ii=%p is done!\n", ii); 1538 #endif 1539 return; 1540 } 1541 ii->isdone = 1; 1542 splx(s); 1543 } 1544 #endif 1545 1546 if (xfer->nframes != 0) { 1547 /* Isoc transfer, do things differently. */ 1548 uhci_soft_td_t **stds = upipe->u.iso.stds; 1549 int i, n, nframes, len; 1550 1551 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1552 1553 nframes = xfer->nframes; 1554 actlen = 0; 1555 n = UXFER(xfer)->curframe; 1556 for (i = 0; i < nframes; i++) { 1557 std = stds[n]; 1558 #ifdef UHCI_DEBUG 1559 if (uhcidebug > 5) { 1560 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1561 uhci_dump_td(std); 1562 } 1563 #endif 1564 if (++n >= UHCI_VFRAMELIST_COUNT) 1565 n = 0; 1566 usb_syncmem(&std->dma, 1567 std->offs + offsetof(uhci_td_t, td_status), 1568 sizeof(std->td.td_status), 1569 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1570 status = le32toh(std->td.td_status); 1571 len = UHCI_TD_GET_ACTLEN(status); 1572 xfer->frlengths[i] = len; 1573 actlen += len; 1574 } 1575 upipe->u.iso.inuse -= nframes; 1576 xfer->actlen = actlen; 1577 xfer->status = USBD_NORMAL_COMPLETION; 1578 goto end; 1579 } 1580 1581 #ifdef UHCI_DEBUG 1582 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1583 ii, xfer, upipe)); 1584 if (uhcidebug > 10) 1585 uhci_dump_tds(ii->stdstart); 1586 #endif 1587 1588 /* The transfer is done, compute actual length and status. */ 1589 actlen = 0; 1590 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1591 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1592 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1593 nstatus = le32toh(std->td.td_status); 1594 if (nstatus & UHCI_TD_ACTIVE) 1595 break; 1596 1597 status = nstatus; 1598 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1599 UHCI_TD_PID_SETUP) 1600 actlen += UHCI_TD_GET_ACTLEN(status); 1601 else { 1602 /* 1603 * UHCI will report CRCTO in addition to a STALL or NAK 1604 * for a SETUP transaction. See section 3.2.2, "TD 1605 * CONTROL AND STATUS". 1606 */ 1607 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1608 status &= ~UHCI_TD_CRCTO; 1609 } 1610 } 1611 /* If there are left over TDs we need to update the toggle. */ 1612 if (std != NULL) 1613 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1614 1615 status &= UHCI_TD_ERROR; 1616 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1617 actlen, status)); 1618 xfer->actlen = actlen; 1619 if (status != 0) { 1620 #ifdef UHCI_DEBUG 1621 char sbuf[128]; 1622 1623 snprintb(sbuf, sizeof(sbuf), 1624 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1625 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1626 1627 DPRINTFN((status == UHCI_TD_STALLED)*10, 1628 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1629 "status 0x%s\n", 1630 xfer->pipe->device->address, 1631 xfer->pipe->endpoint->edesc->bEndpointAddress, 1632 sbuf)); 1633 #endif 1634 1635 if (status == UHCI_TD_STALLED) 1636 xfer->status = USBD_STALLED; 1637 else 1638 xfer->status = USBD_IOERROR; /* more info XXX */ 1639 } else { 1640 xfer->status = USBD_NORMAL_COMPLETION; 1641 } 1642 1643 end: 1644 usb_transfer_complete(xfer); 1645 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1646 } 1647 1648 /* 1649 * Called when a request does not complete. 1650 */ 1651 void 1652 uhci_timeout(void *addr) 1653 { 1654 uhci_intr_info_t *ii = addr; 1655 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1656 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1657 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1658 1659 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1660 1661 if (sc->sc_dying) { 1662 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1663 return; 1664 } 1665 1666 /* Execute the abort in a process context. */ 1667 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer); 1668 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1669 USB_TASKQ_HC); 1670 } 1671 1672 void 1673 uhci_timeout_task(void *addr) 1674 { 1675 usbd_xfer_handle xfer = addr; 1676 int s; 1677 1678 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1679 1680 s = splusb(); 1681 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1682 splx(s); 1683 } 1684 1685 /* 1686 * Wait here until controller claims to have an interrupt. 1687 * Then call uhci_intr and return. Use timeout to avoid waiting 1688 * too long. 1689 * Only used during boot when interrupts are not enabled yet. 1690 */ 1691 void 1692 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1693 { 1694 int timo = xfer->timeout; 1695 uhci_intr_info_t *ii; 1696 1697 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1698 1699 xfer->status = USBD_IN_PROGRESS; 1700 for (; timo >= 0; timo--) { 1701 usb_delay_ms(&sc->sc_bus, 1); 1702 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1703 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1704 uhci_intr1(sc); 1705 if (xfer->status != USBD_IN_PROGRESS) 1706 return; 1707 } 1708 } 1709 1710 /* Timeout */ 1711 DPRINTF(("uhci_waitintr: timeout\n")); 1712 for (ii = LIST_FIRST(&sc->sc_intrhead); 1713 ii != NULL && ii->xfer != xfer; 1714 ii = LIST_NEXT(ii, list)) 1715 ; 1716 #ifdef DIAGNOSTIC 1717 if (ii == NULL) 1718 panic("uhci_waitintr: lost intr_info"); 1719 #endif 1720 uhci_idone(ii); 1721 } 1722 1723 void 1724 uhci_poll(struct usbd_bus *bus) 1725 { 1726 uhci_softc_t *sc = bus->hci_private; 1727 1728 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) 1729 uhci_intr1(sc); 1730 } 1731 1732 void 1733 uhci_reset(uhci_softc_t *sc) 1734 { 1735 int n; 1736 1737 UHCICMD(sc, UHCI_CMD_HCRESET); 1738 /* The reset bit goes low when the controller is done. */ 1739 for (n = 0; n < UHCI_RESET_TIMEOUT && 1740 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1741 usb_delay_ms(&sc->sc_bus, 1); 1742 if (n >= UHCI_RESET_TIMEOUT) 1743 printf("%s: controller did not reset\n", 1744 device_xname(sc->sc_dev)); 1745 } 1746 1747 usbd_status 1748 uhci_run(uhci_softc_t *sc, int run) 1749 { 1750 int s, n, running; 1751 u_int16_t cmd; 1752 1753 run = run != 0; 1754 s = splhardusb(); 1755 DPRINTF(("uhci_run: setting run=%d\n", run)); 1756 cmd = UREAD2(sc, UHCI_CMD); 1757 if (run) 1758 cmd |= UHCI_CMD_RS; 1759 else 1760 cmd &= ~UHCI_CMD_RS; 1761 UHCICMD(sc, cmd); 1762 for(n = 0; n < 10; n++) { 1763 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1764 /* return when we've entered the state we want */ 1765 if (run == running) { 1766 splx(s); 1767 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1768 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1769 return (USBD_NORMAL_COMPLETION); 1770 } 1771 usb_delay_ms(&sc->sc_bus, 1); 1772 } 1773 splx(s); 1774 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1775 run ? "start" : "stop"); 1776 return (USBD_IOERROR); 1777 } 1778 1779 /* 1780 * Memory management routines. 1781 * uhci_alloc_std allocates TDs 1782 * uhci_alloc_sqh allocates QHs 1783 * These two routines do their own free list management, 1784 * partly for speed, partly because allocating DMAable memory 1785 * has page size granularaity so much memory would be wasted if 1786 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1787 */ 1788 1789 uhci_soft_td_t * 1790 uhci_alloc_std(uhci_softc_t *sc) 1791 { 1792 uhci_soft_td_t *std; 1793 usbd_status err; 1794 int i, offs; 1795 usb_dma_t dma; 1796 1797 if (sc->sc_freetds == NULL) { 1798 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1799 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1800 UHCI_TD_ALIGN, &dma); 1801 if (err) 1802 return (0); 1803 for(i = 0; i < UHCI_STD_CHUNK; i++) { 1804 offs = i * UHCI_STD_SIZE; 1805 std = KERNADDR(&dma, offs); 1806 std->physaddr = DMAADDR(&dma, offs); 1807 std->dma = dma; 1808 std->offs = offs; 1809 std->link.std = sc->sc_freetds; 1810 sc->sc_freetds = std; 1811 } 1812 } 1813 std = sc->sc_freetds; 1814 sc->sc_freetds = std->link.std; 1815 memset(&std->td, 0, sizeof(uhci_td_t)); 1816 return std; 1817 } 1818 1819 void 1820 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1821 { 1822 #ifdef DIAGNOSTIC 1823 #define TD_IS_FREE 0x12345678 1824 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1825 printf("uhci_free_std: freeing free TD %p\n", std); 1826 return; 1827 } 1828 std->td.td_token = htole32(TD_IS_FREE); 1829 #endif 1830 std->link.std = sc->sc_freetds; 1831 sc->sc_freetds = std; 1832 } 1833 1834 uhci_soft_qh_t * 1835 uhci_alloc_sqh(uhci_softc_t *sc) 1836 { 1837 uhci_soft_qh_t *sqh; 1838 usbd_status err; 1839 int i, offs; 1840 usb_dma_t dma; 1841 1842 if (sc->sc_freeqhs == NULL) { 1843 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1844 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1845 UHCI_QH_ALIGN, &dma); 1846 if (err) 1847 return (0); 1848 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1849 offs = i * UHCI_SQH_SIZE; 1850 sqh = KERNADDR(&dma, offs); 1851 sqh->physaddr = DMAADDR(&dma, offs); 1852 sqh->dma = dma; 1853 sqh->offs = offs; 1854 sqh->hlink = sc->sc_freeqhs; 1855 sc->sc_freeqhs = sqh; 1856 } 1857 } 1858 sqh = sc->sc_freeqhs; 1859 sc->sc_freeqhs = sqh->hlink; 1860 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1861 return (sqh); 1862 } 1863 1864 void 1865 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1866 { 1867 sqh->hlink = sc->sc_freeqhs; 1868 sc->sc_freeqhs = sqh; 1869 } 1870 1871 void 1872 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1873 uhci_soft_td_t *stdend) 1874 { 1875 uhci_soft_td_t *p; 1876 uint32_t td_link; 1877 1878 /* 1879 * to avoid race condition with the controller which may be looking 1880 * at this chain, we need to first invalidate all links, and 1881 * then wait for the controller to move to another queue 1882 */ 1883 for (p = std; p != stdend; p = p->link.std) { 1884 usb_syncmem(&p->dma, 1885 p->offs + offsetof(uhci_td_t, td_link), 1886 sizeof(p->td.td_link), 1887 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1888 td_link = le32toh(p->td.td_link); 1889 usb_syncmem(&p->dma, 1890 p->offs + offsetof(uhci_td_t, td_link), 1891 sizeof(p->td.td_link), 1892 BUS_DMASYNC_PREREAD); 1893 if ((td_link & UHCI_PTR_T) == 0) { 1894 p->td.td_link = htole32(UHCI_PTR_T); 1895 usb_syncmem(&p->dma, 1896 p->offs + offsetof(uhci_td_t, td_link), 1897 sizeof(p->td.td_link), 1898 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1899 } 1900 } 1901 delay(UHCI_QH_REMOVE_DELAY); 1902 1903 for (; std != stdend; std = p) { 1904 p = std->link.std; 1905 uhci_free_std(sc, std); 1906 } 1907 } 1908 1909 usbd_status 1910 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1911 int rd, u_int16_t flags, usb_dma_t *dma, 1912 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1913 { 1914 uhci_soft_td_t *p, *lastp; 1915 uhci_physaddr_t lastlink; 1916 int i, ntd, l, tog, maxp; 1917 u_int32_t status; 1918 int addr = upipe->pipe.device->address; 1919 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1920 1921 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1922 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1923 upipe->pipe.device->speed, flags)); 1924 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1925 if (maxp == 0) { 1926 printf("uhci_alloc_std_chain: maxp=0\n"); 1927 return (USBD_INVAL); 1928 } 1929 ntd = (len + maxp - 1) / maxp; 1930 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1931 ntd++; 1932 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1933 if (ntd == 0) { 1934 *sp = *ep = 0; 1935 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1936 return (USBD_NORMAL_COMPLETION); 1937 } 1938 tog = upipe->nexttoggle; 1939 if (ntd % 2 == 0) 1940 tog ^= 1; 1941 upipe->nexttoggle = tog ^ 1; 1942 lastp = NULL; 1943 lastlink = UHCI_PTR_T; 1944 ntd--; 1945 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1946 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1947 status |= UHCI_TD_LS; 1948 if (flags & USBD_SHORT_XFER_OK) 1949 status |= UHCI_TD_SPD; 1950 usb_syncmem(dma, 0, len, 1951 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1952 for (i = ntd; i >= 0; i--) { 1953 p = uhci_alloc_std(sc); 1954 if (p == NULL) { 1955 KASSERT(lastp != NULL); 1956 uhci_free_std_chain(sc, lastp, NULL); 1957 return (USBD_NOMEM); 1958 } 1959 p->link.std = lastp; 1960 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1961 lastp = p; 1962 lastlink = p->physaddr; 1963 p->td.td_status = htole32(status); 1964 if (i == ntd) { 1965 /* last TD */ 1966 l = len % maxp; 1967 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1968 l = maxp; 1969 *ep = p; 1970 } else 1971 l = maxp; 1972 p->td.td_token = 1973 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1974 UHCI_TD_OUT(l, endpt, addr, tog)); 1975 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1976 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1978 tog ^= 1; 1979 } 1980 *sp = lastp; 1981 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1982 upipe->nexttoggle)); 1983 return (USBD_NORMAL_COMPLETION); 1984 } 1985 1986 void 1987 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1988 { 1989 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1990 upipe->nexttoggle = 0; 1991 } 1992 1993 void 1994 uhci_noop(usbd_pipe_handle pipe) 1995 { 1996 } 1997 1998 usbd_status 1999 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 2000 { 2001 usbd_status err; 2002 2003 /* Insert last in queue. */ 2004 err = usb_insert_transfer(xfer); 2005 if (err) 2006 return (err); 2007 2008 /* 2009 * Pipe isn't running (otherwise err would be USBD_INPROG), 2010 * so start it first. 2011 */ 2012 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2013 } 2014 2015 usbd_status 2016 uhci_device_bulk_start(usbd_xfer_handle xfer) 2017 { 2018 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2019 usbd_device_handle dev = upipe->pipe.device; 2020 uhci_softc_t *sc = dev->bus->hci_private; 2021 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2022 uhci_soft_td_t *data, *dataend; 2023 uhci_soft_qh_t *sqh; 2024 usbd_status err; 2025 int len, isread, endpt; 2026 int s; 2027 2028 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2029 xfer, xfer->length, xfer->flags, ii)); 2030 2031 if (sc->sc_dying) 2032 return (USBD_IOERROR); 2033 2034 #ifdef DIAGNOSTIC 2035 if (xfer->rqflags & URQ_REQUEST) 2036 panic("uhci_device_bulk_transfer: a request"); 2037 #endif 2038 2039 len = xfer->length; 2040 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2041 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2042 sqh = upipe->u.bulk.sqh; 2043 2044 upipe->u.bulk.isread = isread; 2045 upipe->u.bulk.length = len; 2046 2047 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2048 &xfer->dmabuf, &data, &dataend); 2049 if (err) 2050 return (err); 2051 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2052 usb_syncmem(&dataend->dma, 2053 dataend->offs + offsetof(uhci_td_t, td_status), 2054 sizeof(dataend->td.td_status), 2055 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2056 2057 2058 #ifdef UHCI_DEBUG 2059 if (uhcidebug > 8) { 2060 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2061 uhci_dump_tds(data); 2062 } 2063 #endif 2064 2065 /* Set up interrupt info. */ 2066 ii->xfer = xfer; 2067 ii->stdstart = data; 2068 ii->stdend = dataend; 2069 #ifdef DIAGNOSTIC 2070 if (!ii->isdone) { 2071 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2072 } 2073 ii->isdone = 0; 2074 #endif 2075 2076 sqh->elink = data; 2077 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2078 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2079 2080 s = splusb(); 2081 uhci_add_bulk(sc, sqh); 2082 uhci_add_intr_info(sc, ii); 2083 2084 if (xfer->timeout && !sc->sc_bus.use_polling) { 2085 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2086 uhci_timeout, ii); 2087 } 2088 xfer->status = USBD_IN_PROGRESS; 2089 splx(s); 2090 2091 #ifdef UHCI_DEBUG 2092 if (uhcidebug > 10) { 2093 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2094 uhci_dump_tds(data); 2095 } 2096 #endif 2097 2098 if (sc->sc_bus.use_polling) 2099 uhci_waitintr(sc, xfer); 2100 2101 return (USBD_IN_PROGRESS); 2102 } 2103 2104 /* Abort a device bulk request. */ 2105 void 2106 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2107 { 2108 DPRINTF(("uhci_device_bulk_abort:\n")); 2109 uhci_abort_xfer(xfer, USBD_CANCELLED); 2110 } 2111 2112 /* 2113 * Abort a device request. 2114 * If this routine is called at splusb() it guarantees that the request 2115 * will be removed from the hardware scheduling and that the callback 2116 * for it will be called with USBD_CANCELLED status. 2117 * It's impossible to guarantee that the requested transfer will not 2118 * have happened since the hardware runs concurrently. 2119 * If the transaction has already happened we rely on the ordinary 2120 * interrupt processing to process it. 2121 */ 2122 void 2123 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2124 { 2125 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2126 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2127 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2128 uhci_soft_td_t *std; 2129 int s; 2130 int wake; 2131 2132 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2133 2134 if (sc->sc_dying) { 2135 /* If we're dying, just do the software part. */ 2136 s = splusb(); 2137 xfer->status = status; /* make software ignore it */ 2138 callout_stop(&xfer->timeout_handle); 2139 usb_transfer_complete(xfer); 2140 splx(s); 2141 return; 2142 } 2143 2144 if (xfer->device->bus->intr_context || !curproc) 2145 panic("uhci_abort_xfer: not in process context"); 2146 2147 /* 2148 * If an abort is already in progress then just wait for it to 2149 * complete and return. 2150 */ 2151 if (xfer->hcflags & UXFER_ABORTING) { 2152 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2153 #ifdef DIAGNOSTIC 2154 if (status == USBD_TIMEOUT) 2155 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2156 #endif 2157 /* Override the status which might be USBD_TIMEOUT. */ 2158 xfer->status = status; 2159 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2160 xfer->hcflags |= UXFER_ABORTWAIT; 2161 while (xfer->hcflags & UXFER_ABORTING) 2162 tsleep(&xfer->hcflags, PZERO, "uhciaw", 0); 2163 return; 2164 } 2165 xfer->hcflags |= UXFER_ABORTING; 2166 2167 /* 2168 * Step 1: Make interrupt routine and hardware ignore xfer. 2169 */ 2170 s = splusb(); 2171 xfer->status = status; /* make software ignore it */ 2172 callout_stop(&xfer->timeout_handle); 2173 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2174 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2175 usb_syncmem(&std->dma, 2176 std->offs + offsetof(uhci_td_t, td_status), 2177 sizeof(std->td.td_status), 2178 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2179 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2180 usb_syncmem(&std->dma, 2181 std->offs + offsetof(uhci_td_t, td_status), 2182 sizeof(std->td.td_status), 2183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2184 } 2185 splx(s); 2186 2187 /* 2188 * Step 2: Wait until we know hardware has finished any possible 2189 * use of the xfer. Also make sure the soft interrupt routine 2190 * has run. 2191 */ 2192 usb_delay_ms(upipe->pipe.device->bus, 2); /* Hardware finishes in 1ms */ 2193 s = splusb(); 2194 #ifdef USB_USE_SOFTINTR 2195 sc->sc_softwake = 1; 2196 #endif /* USB_USE_SOFTINTR */ 2197 usb_schedsoftintr(&sc->sc_bus); 2198 #ifdef USB_USE_SOFTINTR 2199 DPRINTFN(1,("uhci_abort_xfer: tsleep\n")); 2200 tsleep(&sc->sc_softwake, PZERO, "uhciab", 0); 2201 #endif /* USB_USE_SOFTINTR */ 2202 splx(s); 2203 2204 /* 2205 * Step 3: Execute callback. 2206 */ 2207 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2208 s = splusb(); 2209 #ifdef DIAGNOSTIC 2210 ii->isdone = 1; 2211 #endif 2212 wake = xfer->hcflags & UXFER_ABORTWAIT; 2213 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2214 usb_transfer_complete(xfer); 2215 if (wake) 2216 wakeup(&xfer->hcflags); 2217 splx(s); 2218 } 2219 2220 /* Close a device bulk pipe. */ 2221 void 2222 uhci_device_bulk_close(usbd_pipe_handle pipe) 2223 { 2224 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2225 usbd_device_handle dev = upipe->pipe.device; 2226 uhci_softc_t *sc = dev->bus->hci_private; 2227 2228 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2229 2230 pipe->endpoint->datatoggle = upipe->nexttoggle; 2231 } 2232 2233 usbd_status 2234 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2235 { 2236 usbd_status err; 2237 2238 /* Insert last in queue. */ 2239 err = usb_insert_transfer(xfer); 2240 if (err) 2241 return (err); 2242 2243 /* 2244 * Pipe isn't running (otherwise err would be USBD_INPROG), 2245 * so start it first. 2246 */ 2247 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2248 } 2249 2250 usbd_status 2251 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2252 { 2253 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2254 usbd_status err; 2255 2256 if (sc->sc_dying) 2257 return (USBD_IOERROR); 2258 2259 #ifdef DIAGNOSTIC 2260 if (!(xfer->rqflags & URQ_REQUEST)) 2261 panic("uhci_device_ctrl_transfer: not a request"); 2262 #endif 2263 2264 err = uhci_device_request(xfer); 2265 if (err) 2266 return (err); 2267 2268 if (sc->sc_bus.use_polling) 2269 uhci_waitintr(sc, xfer); 2270 return (USBD_IN_PROGRESS); 2271 } 2272 2273 usbd_status 2274 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2275 { 2276 usbd_status err; 2277 2278 /* Insert last in queue. */ 2279 err = usb_insert_transfer(xfer); 2280 if (err) 2281 return (err); 2282 2283 /* 2284 * Pipe isn't running (otherwise err would be USBD_INPROG), 2285 * so start it first. 2286 */ 2287 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2288 } 2289 2290 usbd_status 2291 uhci_device_intr_start(usbd_xfer_handle xfer) 2292 { 2293 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2294 usbd_device_handle dev = upipe->pipe.device; 2295 uhci_softc_t *sc = dev->bus->hci_private; 2296 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2297 uhci_soft_td_t *data, *dataend; 2298 uhci_soft_qh_t *sqh; 2299 usbd_status err; 2300 int isread, endpt; 2301 int i, s; 2302 2303 if (sc->sc_dying) 2304 return (USBD_IOERROR); 2305 2306 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2307 xfer, xfer->length, xfer->flags)); 2308 2309 #ifdef DIAGNOSTIC 2310 if (xfer->rqflags & URQ_REQUEST) 2311 panic("uhci_device_intr_transfer: a request"); 2312 #endif 2313 2314 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2315 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2316 2317 upipe->u.intr.isread = isread; 2318 2319 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2320 xfer->flags, &xfer->dmabuf, &data, 2321 &dataend); 2322 if (err) 2323 return (err); 2324 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2325 usb_syncmem(&dataend->dma, 2326 dataend->offs + offsetof(uhci_td_t, td_status), 2327 sizeof(dataend->td.td_status), 2328 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2329 2330 #ifdef UHCI_DEBUG 2331 if (uhcidebug > 10) { 2332 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2333 uhci_dump_tds(data); 2334 uhci_dump_qh(upipe->u.intr.qhs[0]); 2335 } 2336 #endif 2337 2338 s = splusb(); 2339 /* Set up interrupt info. */ 2340 ii->xfer = xfer; 2341 ii->stdstart = data; 2342 ii->stdend = dataend; 2343 #ifdef DIAGNOSTIC 2344 if (!ii->isdone) { 2345 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2346 } 2347 ii->isdone = 0; 2348 #endif 2349 2350 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2351 upipe->u.intr.qhs[0])); 2352 for (i = 0; i < upipe->u.intr.npoll; i++) { 2353 sqh = upipe->u.intr.qhs[i]; 2354 sqh->elink = data; 2355 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2356 usb_syncmem(&sqh->dma, 2357 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2358 sizeof(sqh->qh.qh_elink), 2359 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2360 } 2361 uhci_add_intr_info(sc, ii); 2362 xfer->status = USBD_IN_PROGRESS; 2363 splx(s); 2364 2365 #ifdef UHCI_DEBUG 2366 if (uhcidebug > 10) { 2367 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2368 uhci_dump_tds(data); 2369 uhci_dump_qh(upipe->u.intr.qhs[0]); 2370 } 2371 #endif 2372 2373 return (USBD_IN_PROGRESS); 2374 } 2375 2376 /* Abort a device control request. */ 2377 void 2378 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2379 { 2380 DPRINTF(("uhci_device_ctrl_abort:\n")); 2381 uhci_abort_xfer(xfer, USBD_CANCELLED); 2382 } 2383 2384 /* Close a device control pipe. */ 2385 void 2386 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2387 { 2388 } 2389 2390 /* Abort a device interrupt request. */ 2391 void 2392 uhci_device_intr_abort(usbd_xfer_handle xfer) 2393 { 2394 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2395 if (xfer->pipe->intrxfer == xfer) { 2396 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2397 xfer->pipe->intrxfer = NULL; 2398 } 2399 uhci_abort_xfer(xfer, USBD_CANCELLED); 2400 } 2401 2402 /* Close a device interrupt pipe. */ 2403 void 2404 uhci_device_intr_close(usbd_pipe_handle pipe) 2405 { 2406 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2407 uhci_softc_t *sc = pipe->device->bus->hci_private; 2408 int i, npoll; 2409 int s; 2410 2411 /* Unlink descriptors from controller data structures. */ 2412 npoll = upipe->u.intr.npoll; 2413 s = splusb(); 2414 for (i = 0; i < npoll; i++) 2415 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2416 splx(s); 2417 2418 /* 2419 * We now have to wait for any activity on the physical 2420 * descriptors to stop. 2421 */ 2422 usb_delay_ms(&sc->sc_bus, 2); 2423 2424 for(i = 0; i < npoll; i++) 2425 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2426 free(upipe->u.intr.qhs, M_USBHC); 2427 2428 /* XXX free other resources */ 2429 } 2430 2431 usbd_status 2432 uhci_device_request(usbd_xfer_handle xfer) 2433 { 2434 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2435 usb_device_request_t *req = &xfer->request; 2436 usbd_device_handle dev = upipe->pipe.device; 2437 uhci_softc_t *sc = dev->bus->hci_private; 2438 int addr = dev->address; 2439 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2440 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2441 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2442 uhci_soft_qh_t *sqh; 2443 int len; 2444 u_int32_t ls; 2445 usbd_status err; 2446 int isread; 2447 int s; 2448 2449 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2450 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2451 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2452 UGETW(req->wIndex), UGETW(req->wLength), 2453 addr, endpt)); 2454 2455 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2456 isread = req->bmRequestType & UT_READ; 2457 len = UGETW(req->wLength); 2458 2459 setup = upipe->u.ctl.setup; 2460 stat = upipe->u.ctl.stat; 2461 sqh = upipe->u.ctl.sqh; 2462 2463 /* Set up data transaction */ 2464 if (len != 0) { 2465 upipe->nexttoggle = 1; 2466 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2467 &xfer->dmabuf, &data, &dataend); 2468 if (err) 2469 return (err); 2470 next = data; 2471 dataend->link.std = stat; 2472 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2473 usb_syncmem(&dataend->dma, 2474 dataend->offs + offsetof(uhci_td_t, td_link), 2475 sizeof(dataend->td.td_link), 2476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2477 } else { 2478 next = stat; 2479 } 2480 upipe->u.ctl.length = len; 2481 2482 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2483 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2484 2485 setup->link.std = next; 2486 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2487 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2488 UHCI_TD_ACTIVE); 2489 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2490 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2491 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2492 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2493 2494 stat->link.std = NULL; 2495 stat->td.td_link = htole32(UHCI_PTR_T); 2496 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2497 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2498 stat->td.td_token = 2499 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2500 UHCI_TD_IN (0, endpt, addr, 1)); 2501 stat->td.td_buffer = htole32(0); 2502 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2504 2505 #ifdef UHCI_DEBUG 2506 if (uhcidebug > 10) { 2507 DPRINTF(("uhci_device_request: before transfer\n")); 2508 uhci_dump_tds(setup); 2509 } 2510 #endif 2511 2512 /* Set up interrupt info. */ 2513 ii->xfer = xfer; 2514 ii->stdstart = setup; 2515 ii->stdend = stat; 2516 #ifdef DIAGNOSTIC 2517 if (!ii->isdone) { 2518 printf("uhci_device_request: not done, ii=%p\n", ii); 2519 } 2520 ii->isdone = 0; 2521 #endif 2522 2523 sqh->elink = setup; 2524 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2525 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2526 2527 s = splusb(); 2528 if (dev->speed == USB_SPEED_LOW) 2529 uhci_add_ls_ctrl(sc, sqh); 2530 else 2531 uhci_add_hs_ctrl(sc, sqh); 2532 uhci_add_intr_info(sc, ii); 2533 #ifdef UHCI_DEBUG 2534 if (uhcidebug > 12) { 2535 uhci_soft_td_t *std; 2536 uhci_soft_qh_t *xqh; 2537 uhci_soft_qh_t *sxqh; 2538 int maxqh = 0; 2539 uhci_physaddr_t link; 2540 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2541 for (std = sc->sc_vframes[0].htd, link = 0; 2542 (link & UHCI_PTR_QH) == 0; 2543 std = std->link.std) { 2544 link = le32toh(std->td.td_link); 2545 uhci_dump_td(std); 2546 } 2547 sxqh = (uhci_soft_qh_t *)std; 2548 uhci_dump_qh(sxqh); 2549 for (xqh = sxqh; 2550 xqh != NULL; 2551 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2552 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2553 uhci_dump_qh(xqh); 2554 } 2555 DPRINTF(("Enqueued QH:\n")); 2556 uhci_dump_qh(sqh); 2557 uhci_dump_tds(sqh->elink); 2558 } 2559 #endif 2560 if (xfer->timeout && !sc->sc_bus.use_polling) { 2561 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2562 uhci_timeout, ii); 2563 } 2564 xfer->status = USBD_IN_PROGRESS; 2565 splx(s); 2566 2567 return (USBD_NORMAL_COMPLETION); 2568 } 2569 2570 usbd_status 2571 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2572 { 2573 usbd_status err; 2574 2575 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2576 2577 /* Put it on our queue, */ 2578 err = usb_insert_transfer(xfer); 2579 2580 /* bail out on error, */ 2581 if (err && err != USBD_IN_PROGRESS) 2582 return (err); 2583 2584 /* XXX should check inuse here */ 2585 2586 /* insert into schedule, */ 2587 uhci_device_isoc_enter(xfer); 2588 2589 /* and start if the pipe wasn't running */ 2590 if (!err) 2591 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2592 2593 return (err); 2594 } 2595 2596 void 2597 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2598 { 2599 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2600 usbd_device_handle dev = upipe->pipe.device; 2601 uhci_softc_t *sc = dev->bus->hci_private; 2602 struct iso *iso = &upipe->u.iso; 2603 uhci_soft_td_t *std; 2604 u_int32_t buf, len, status, offs; 2605 int s, i, next, nframes; 2606 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2607 2608 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2609 "nframes=%d\n", 2610 iso->inuse, iso->next, xfer, xfer->nframes)); 2611 2612 if (sc->sc_dying) 2613 return; 2614 2615 if (xfer->status == USBD_IN_PROGRESS) { 2616 /* This request has already been entered into the frame list */ 2617 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2618 /* XXX */ 2619 } 2620 2621 #ifdef DIAGNOSTIC 2622 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2623 printf("uhci_device_isoc_enter: overflow!\n"); 2624 #endif 2625 2626 next = iso->next; 2627 if (next == -1) { 2628 /* Not in use yet, schedule it a few frames ahead. */ 2629 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2630 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2631 } 2632 2633 xfer->status = USBD_IN_PROGRESS; 2634 UXFER(xfer)->curframe = next; 2635 2636 buf = DMAADDR(&xfer->dmabuf, 0); 2637 offs = 0; 2638 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2639 UHCI_TD_ACTIVE | 2640 UHCI_TD_IOS); 2641 nframes = xfer->nframes; 2642 s = splusb(); 2643 for (i = 0; i < nframes; i++) { 2644 std = iso->stds[next]; 2645 if (++next >= UHCI_VFRAMELIST_COUNT) 2646 next = 0; 2647 len = xfer->frlengths[i]; 2648 std->td.td_buffer = htole32(buf); 2649 usb_syncmem(&xfer->dmabuf, offs, len, 2650 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2651 if (i == nframes - 1) 2652 status |= UHCI_TD_IOC; 2653 std->td.td_status = htole32(status); 2654 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2655 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2656 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2657 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2658 #ifdef UHCI_DEBUG 2659 if (uhcidebug > 5) { 2660 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2661 uhci_dump_td(std); 2662 } 2663 #endif 2664 buf += len; 2665 offs += len; 2666 } 2667 iso->next = next; 2668 iso->inuse += xfer->nframes; 2669 2670 splx(s); 2671 } 2672 2673 usbd_status 2674 uhci_device_isoc_start(usbd_xfer_handle xfer) 2675 { 2676 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2677 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2678 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2679 uhci_soft_td_t *end; 2680 int s, i; 2681 2682 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2683 2684 if (sc->sc_dying) 2685 return (USBD_IOERROR); 2686 2687 #ifdef DIAGNOSTIC 2688 if (xfer->status != USBD_IN_PROGRESS) 2689 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2690 #endif 2691 2692 /* Find the last TD */ 2693 i = UXFER(xfer)->curframe + xfer->nframes; 2694 if (i >= UHCI_VFRAMELIST_COUNT) 2695 i -= UHCI_VFRAMELIST_COUNT; 2696 end = upipe->u.iso.stds[i]; 2697 2698 #ifdef DIAGNOSTIC 2699 if (end == NULL) { 2700 printf("uhci_device_isoc_start: end == NULL\n"); 2701 return (USBD_INVAL); 2702 } 2703 #endif 2704 2705 s = splusb(); 2706 2707 /* Set up interrupt info. */ 2708 ii->xfer = xfer; 2709 ii->stdstart = end; 2710 ii->stdend = end; 2711 #ifdef DIAGNOSTIC 2712 if (!ii->isdone) 2713 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2714 ii->isdone = 0; 2715 #endif 2716 uhci_add_intr_info(sc, ii); 2717 2718 splx(s); 2719 2720 return (USBD_IN_PROGRESS); 2721 } 2722 2723 void 2724 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2725 { 2726 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2727 uhci_soft_td_t **stds = upipe->u.iso.stds; 2728 uhci_soft_td_t *std; 2729 int i, n, s, nframes, maxlen, len; 2730 2731 s = splusb(); 2732 2733 /* Transfer is already done. */ 2734 if (xfer->status != USBD_NOT_STARTED && 2735 xfer->status != USBD_IN_PROGRESS) { 2736 splx(s); 2737 return; 2738 } 2739 2740 /* Give xfer the requested abort code. */ 2741 xfer->status = USBD_CANCELLED; 2742 2743 /* make hardware ignore it, */ 2744 nframes = xfer->nframes; 2745 n = UXFER(xfer)->curframe; 2746 maxlen = 0; 2747 for (i = 0; i < nframes; i++) { 2748 std = stds[n]; 2749 usb_syncmem(&std->dma, 2750 std->offs + offsetof(uhci_td_t, td_status), 2751 sizeof(std->td.td_status), 2752 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2753 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2754 usb_syncmem(&std->dma, 2755 std->offs + offsetof(uhci_td_t, td_status), 2756 sizeof(std->td.td_status), 2757 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2758 usb_syncmem(&std->dma, 2759 std->offs + offsetof(uhci_td_t, td_token), 2760 sizeof(std->td.td_token), 2761 BUS_DMASYNC_POSTWRITE); 2762 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2763 if (len > maxlen) 2764 maxlen = len; 2765 if (++n >= UHCI_VFRAMELIST_COUNT) 2766 n = 0; 2767 } 2768 2769 /* and wait until we are sure the hardware has finished. */ 2770 delay(maxlen); 2771 2772 #ifdef DIAGNOSTIC 2773 UXFER(xfer)->iinfo.isdone = 1; 2774 #endif 2775 /* Run callback and remove from interrupt list. */ 2776 usb_transfer_complete(xfer); 2777 2778 splx(s); 2779 } 2780 2781 void 2782 uhci_device_isoc_close(usbd_pipe_handle pipe) 2783 { 2784 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2785 usbd_device_handle dev = upipe->pipe.device; 2786 uhci_softc_t *sc = dev->bus->hci_private; 2787 uhci_soft_td_t *std, *vstd; 2788 struct iso *iso; 2789 int i, s; 2790 2791 /* 2792 * Make sure all TDs are marked as inactive. 2793 * Wait for completion. 2794 * Unschedule. 2795 * Deallocate. 2796 */ 2797 iso = &upipe->u.iso; 2798 2799 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2800 std = iso->stds[i]; 2801 usb_syncmem(&std->dma, 2802 std->offs + offsetof(uhci_td_t, td_status), 2803 sizeof(std->td.td_status), 2804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2805 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2806 usb_syncmem(&std->dma, 2807 std->offs + offsetof(uhci_td_t, td_status), 2808 sizeof(std->td.td_status), 2809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2810 } 2811 usb_delay_ms(&sc->sc_bus, 2); /* wait for completion */ 2812 2813 s = splusb(); 2814 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2815 std = iso->stds[i]; 2816 for (vstd = sc->sc_vframes[i].htd; 2817 vstd != NULL && vstd->link.std != std; 2818 vstd = vstd->link.std) 2819 ; 2820 if (vstd == NULL) { 2821 /*panic*/ 2822 printf("uhci_device_isoc_close: %p not found\n", std); 2823 splx(s); 2824 return; 2825 } 2826 vstd->link = std->link; 2827 usb_syncmem(&std->dma, 2828 std->offs + offsetof(uhci_td_t, td_link), 2829 sizeof(std->td.td_link), 2830 BUS_DMASYNC_POSTWRITE); 2831 vstd->td.td_link = std->td.td_link; 2832 usb_syncmem(&vstd->dma, 2833 vstd->offs + offsetof(uhci_td_t, td_link), 2834 sizeof(vstd->td.td_link), 2835 BUS_DMASYNC_PREWRITE); 2836 uhci_free_std(sc, std); 2837 } 2838 splx(s); 2839 2840 free(iso->stds, M_USBHC); 2841 } 2842 2843 usbd_status 2844 uhci_setup_isoc(usbd_pipe_handle pipe) 2845 { 2846 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2847 usbd_device_handle dev = upipe->pipe.device; 2848 uhci_softc_t *sc = dev->bus->hci_private; 2849 int addr = upipe->pipe.device->address; 2850 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2851 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2852 uhci_soft_td_t *std, *vstd; 2853 u_int32_t token; 2854 struct iso *iso; 2855 int i, s; 2856 2857 iso = &upipe->u.iso; 2858 iso->stds = malloc(UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *), 2859 M_USBHC, M_WAITOK); 2860 2861 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2862 UHCI_TD_OUT(0, endpt, addr, 0); 2863 2864 /* Allocate the TDs and mark as inactive; */ 2865 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2866 std = uhci_alloc_std(sc); 2867 if (std == 0) 2868 goto bad; 2869 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2870 std->td.td_token = htole32(token); 2871 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2872 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2873 iso->stds[i] = std; 2874 } 2875 2876 /* Insert TDs into schedule. */ 2877 s = splusb(); 2878 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2879 std = iso->stds[i]; 2880 vstd = sc->sc_vframes[i].htd; 2881 usb_syncmem(&vstd->dma, 2882 vstd->offs + offsetof(uhci_td_t, td_link), 2883 sizeof(vstd->td.td_link), 2884 BUS_DMASYNC_POSTWRITE); 2885 std->link = vstd->link; 2886 std->td.td_link = vstd->td.td_link; 2887 usb_syncmem(&std->dma, 2888 std->offs + offsetof(uhci_td_t, td_link), 2889 sizeof(std->td.td_link), 2890 BUS_DMASYNC_PREWRITE); 2891 vstd->link.std = std; 2892 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2893 usb_syncmem(&vstd->dma, 2894 vstd->offs + offsetof(uhci_td_t, td_link), 2895 sizeof(vstd->td.td_link), 2896 BUS_DMASYNC_PREWRITE); 2897 } 2898 splx(s); 2899 2900 iso->next = -1; 2901 iso->inuse = 0; 2902 2903 return (USBD_NORMAL_COMPLETION); 2904 2905 bad: 2906 while (--i >= 0) 2907 uhci_free_std(sc, iso->stds[i]); 2908 free(iso->stds, M_USBHC); 2909 return (USBD_NOMEM); 2910 } 2911 2912 void 2913 uhci_device_isoc_done(usbd_xfer_handle xfer) 2914 { 2915 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2916 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2917 int i, offs; 2918 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2919 2920 2921 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2922 xfer->actlen, xfer->busy_free)); 2923 2924 if (ii->xfer != xfer) 2925 /* Not on interrupt list, ignore it. */ 2926 return; 2927 2928 if (!uhci_active_intr_info(ii)) 2929 return; 2930 2931 #ifdef DIAGNOSTIC 2932 if (ii->stdend == NULL) { 2933 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2934 #ifdef UHCI_DEBUG 2935 uhci_dump_ii(ii); 2936 #endif 2937 return; 2938 } 2939 #endif 2940 2941 /* Turn off the interrupt since it is active even if the TD is not. */ 2942 usb_syncmem(&ii->stdend->dma, 2943 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2944 sizeof(ii->stdend->td.td_status), 2945 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2946 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2947 usb_syncmem(&ii->stdend->dma, 2948 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2949 sizeof(ii->stdend->td.td_status), 2950 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2951 2952 uhci_del_intr_info(ii); /* remove from active list */ 2953 2954 offs = 0; 2955 for (i = 0; i < xfer->nframes; i++) { 2956 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2957 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2958 offs += xfer->frlengths[i]; 2959 } 2960 } 2961 2962 void 2963 uhci_device_intr_done(usbd_xfer_handle xfer) 2964 { 2965 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2966 uhci_softc_t *sc = ii->sc; 2967 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2968 uhci_soft_qh_t *sqh; 2969 int i, npoll, isread; 2970 2971 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 2972 2973 npoll = upipe->u.intr.npoll; 2974 for(i = 0; i < npoll; i++) { 2975 sqh = upipe->u.intr.qhs[i]; 2976 sqh->elink = NULL; 2977 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2978 usb_syncmem(&sqh->dma, 2979 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2980 sizeof(sqh->qh.qh_elink), 2981 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2982 } 2983 uhci_free_std_chain(sc, ii->stdstart, NULL); 2984 2985 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2986 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2987 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2988 2989 /* XXX Wasteful. */ 2990 if (xfer->pipe->repeat) { 2991 uhci_soft_td_t *data, *dataend; 2992 2993 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2994 2995 /* This alloc cannot fail since we freed the chain above. */ 2996 uhci_alloc_std_chain(upipe, sc, xfer->length, 2997 upipe->u.intr.isread, xfer->flags, 2998 &xfer->dmabuf, &data, &dataend); 2999 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3000 usb_syncmem(&dataend->dma, 3001 dataend->offs + offsetof(uhci_td_t, td_status), 3002 sizeof(dataend->td.td_status), 3003 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3004 3005 #ifdef UHCI_DEBUG 3006 if (uhcidebug > 10) { 3007 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3008 uhci_dump_tds(data); 3009 uhci_dump_qh(upipe->u.intr.qhs[0]); 3010 } 3011 #endif 3012 3013 ii->stdstart = data; 3014 ii->stdend = dataend; 3015 #ifdef DIAGNOSTIC 3016 if (!ii->isdone) { 3017 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3018 } 3019 ii->isdone = 0; 3020 #endif 3021 for (i = 0; i < npoll; i++) { 3022 sqh = upipe->u.intr.qhs[i]; 3023 sqh->elink = data; 3024 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3025 usb_syncmem(&sqh->dma, 3026 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3027 sizeof(sqh->qh.qh_elink), 3028 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3029 } 3030 xfer->status = USBD_IN_PROGRESS; 3031 /* The ii is already on the examined list, just leave it. */ 3032 } else { 3033 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3034 if (uhci_active_intr_info(ii)) 3035 uhci_del_intr_info(ii); 3036 } 3037 } 3038 3039 /* Deallocate request data structures */ 3040 void 3041 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3042 { 3043 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3044 uhci_softc_t *sc = ii->sc; 3045 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3046 int len = UGETW(xfer->request.wLength); 3047 int isread = (xfer->request.bmRequestType & UT_READ); 3048 3049 #ifdef DIAGNOSTIC 3050 if (!(xfer->rqflags & URQ_REQUEST)) 3051 panic("uhci_device_ctrl_done: not a request"); 3052 #endif 3053 3054 if (!uhci_active_intr_info(ii)) 3055 return; 3056 3057 uhci_del_intr_info(ii); /* remove from active list */ 3058 3059 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3060 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3061 else 3062 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3063 3064 if (upipe->u.ctl.length != 0) 3065 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3066 3067 if (len) { 3068 usb_syncmem(&xfer->dmabuf, 0, len, 3069 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3070 } 3071 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3072 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3073 3074 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3075 } 3076 3077 /* Deallocate request data structures */ 3078 void 3079 uhci_device_bulk_done(usbd_xfer_handle xfer) 3080 { 3081 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3082 uhci_softc_t *sc = ii->sc; 3083 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3084 3085 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3086 xfer, ii, sc, upipe)); 3087 3088 if (!uhci_active_intr_info(ii)) 3089 return; 3090 3091 uhci_del_intr_info(ii); /* remove from active list */ 3092 3093 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3094 3095 uhci_free_std_chain(sc, ii->stdstart, NULL); 3096 3097 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3098 } 3099 3100 /* Add interrupt QH, called with vflock. */ 3101 void 3102 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3103 { 3104 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3105 uhci_soft_qh_t *eqh; 3106 3107 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3108 3109 eqh = vf->eqh; 3110 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3111 sizeof(eqh->qh.qh_hlink), 3112 BUS_DMASYNC_POSTWRITE); 3113 sqh->hlink = eqh->hlink; 3114 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3115 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3116 sizeof(sqh->qh.qh_hlink), 3117 BUS_DMASYNC_PREWRITE); 3118 eqh->hlink = sqh; 3119 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3120 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3121 sizeof(eqh->qh.qh_hlink), 3122 BUS_DMASYNC_PREWRITE); 3123 vf->eqh = sqh; 3124 vf->bandwidth++; 3125 } 3126 3127 /* Remove interrupt QH. */ 3128 void 3129 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3130 { 3131 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3132 uhci_soft_qh_t *pqh; 3133 3134 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3135 3136 /* See comment in uhci_remove_ctrl() */ 3137 3138 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3139 sizeof(sqh->qh.qh_elink), 3140 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3141 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3142 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3143 usb_syncmem(&sqh->dma, 3144 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3145 sizeof(sqh->qh.qh_elink), 3146 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3147 delay(UHCI_QH_REMOVE_DELAY); 3148 } 3149 3150 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3151 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3152 sizeof(sqh->qh.qh_hlink), 3153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3154 pqh->hlink = sqh->hlink; 3155 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3156 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3157 sizeof(pqh->qh.qh_hlink), 3158 BUS_DMASYNC_PREWRITE); 3159 delay(UHCI_QH_REMOVE_DELAY); 3160 if (vf->eqh == sqh) 3161 vf->eqh = pqh; 3162 vf->bandwidth--; 3163 } 3164 3165 usbd_status 3166 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3167 { 3168 uhci_soft_qh_t *sqh; 3169 int i, npoll, s; 3170 u_int bestbw, bw, bestoffs, offs; 3171 3172 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3173 if (ival == 0) { 3174 printf("uhci_device_setintr: 0 interval\n"); 3175 return (USBD_INVAL); 3176 } 3177 3178 if (ival > UHCI_VFRAMELIST_COUNT) 3179 ival = UHCI_VFRAMELIST_COUNT; 3180 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3181 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3182 3183 upipe->u.intr.npoll = npoll; 3184 upipe->u.intr.qhs = 3185 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USBHC, M_WAITOK); 3186 3187 /* 3188 * Figure out which offset in the schedule that has most 3189 * bandwidth left over. 3190 */ 3191 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3192 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3193 for (bw = i = 0; i < npoll; i++) 3194 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3195 if (bw < bestbw) { 3196 bestbw = bw; 3197 bestoffs = offs; 3198 } 3199 } 3200 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3201 3202 for(i = 0; i < npoll; i++) { 3203 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3204 sqh->elink = NULL; 3205 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3206 usb_syncmem(&sqh->dma, 3207 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3208 sizeof(sqh->qh.qh_elink), 3209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3210 sqh->pos = MOD(i * ival + bestoffs); 3211 } 3212 #undef MOD 3213 3214 s = splusb(); 3215 /* Enter QHs into the controller data structures. */ 3216 for(i = 0; i < npoll; i++) 3217 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3218 splx(s); 3219 3220 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3221 return (USBD_NORMAL_COMPLETION); 3222 } 3223 3224 /* Open a new pipe. */ 3225 usbd_status 3226 uhci_open(usbd_pipe_handle pipe) 3227 { 3228 uhci_softc_t *sc = pipe->device->bus->hci_private; 3229 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3230 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3231 usbd_status err; 3232 int ival; 3233 3234 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3235 pipe, pipe->device->address, 3236 ed->bEndpointAddress, sc->sc_addr)); 3237 3238 upipe->aborting = 0; 3239 /* toggle state needed for bulk endpoints */ 3240 upipe->nexttoggle = pipe->endpoint->datatoggle; 3241 3242 if (pipe->device->address == sc->sc_addr) { 3243 switch (ed->bEndpointAddress) { 3244 case USB_CONTROL_ENDPOINT: 3245 pipe->methods = &uhci_root_ctrl_methods; 3246 break; 3247 case UE_DIR_IN | UHCI_INTR_ENDPT: 3248 pipe->methods = &uhci_root_intr_methods; 3249 break; 3250 default: 3251 return (USBD_INVAL); 3252 } 3253 } else { 3254 switch (ed->bmAttributes & UE_XFERTYPE) { 3255 case UE_CONTROL: 3256 pipe->methods = &uhci_device_ctrl_methods; 3257 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3258 if (upipe->u.ctl.sqh == NULL) 3259 goto bad; 3260 upipe->u.ctl.setup = uhci_alloc_std(sc); 3261 if (upipe->u.ctl.setup == NULL) { 3262 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3263 goto bad; 3264 } 3265 upipe->u.ctl.stat = uhci_alloc_std(sc); 3266 if (upipe->u.ctl.stat == NULL) { 3267 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3268 uhci_free_std(sc, upipe->u.ctl.setup); 3269 goto bad; 3270 } 3271 err = usb_allocmem(&sc->sc_bus, 3272 sizeof(usb_device_request_t), 3273 0, &upipe->u.ctl.reqdma); 3274 if (err) { 3275 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3276 uhci_free_std(sc, upipe->u.ctl.setup); 3277 uhci_free_std(sc, upipe->u.ctl.stat); 3278 goto bad; 3279 } 3280 break; 3281 case UE_INTERRUPT: 3282 pipe->methods = &uhci_device_intr_methods; 3283 ival = pipe->interval; 3284 if (ival == USBD_DEFAULT_INTERVAL) 3285 ival = ed->bInterval; 3286 return (uhci_device_setintr(sc, upipe, ival)); 3287 case UE_ISOCHRONOUS: 3288 pipe->methods = &uhci_device_isoc_methods; 3289 return (uhci_setup_isoc(pipe)); 3290 case UE_BULK: 3291 pipe->methods = &uhci_device_bulk_methods; 3292 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3293 if (upipe->u.bulk.sqh == NULL) 3294 goto bad; 3295 break; 3296 } 3297 } 3298 return (USBD_NORMAL_COMPLETION); 3299 3300 bad: 3301 return (USBD_NOMEM); 3302 } 3303 3304 /* 3305 * Data structures and routines to emulate the root hub. 3306 */ 3307 usb_device_descriptor_t uhci_devd = { 3308 USB_DEVICE_DESCRIPTOR_SIZE, 3309 UDESC_DEVICE, /* type */ 3310 {0x00, 0x01}, /* USB version */ 3311 UDCLASS_HUB, /* class */ 3312 UDSUBCLASS_HUB, /* subclass */ 3313 UDPROTO_FSHUB, /* protocol */ 3314 64, /* max packet */ 3315 {0},{0},{0x00,0x01}, /* device id */ 3316 1,2,0, /* string indicies */ 3317 1 /* # of configurations */ 3318 }; 3319 3320 const usb_config_descriptor_t uhci_confd = { 3321 USB_CONFIG_DESCRIPTOR_SIZE, 3322 UDESC_CONFIG, 3323 {USB_CONFIG_DESCRIPTOR_SIZE + 3324 USB_INTERFACE_DESCRIPTOR_SIZE + 3325 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3326 1, 3327 1, 3328 0, 3329 UC_ATTR_MBO | UC_SELF_POWERED, 3330 0 /* max power */ 3331 }; 3332 3333 const usb_interface_descriptor_t uhci_ifcd = { 3334 USB_INTERFACE_DESCRIPTOR_SIZE, 3335 UDESC_INTERFACE, 3336 0, 3337 0, 3338 1, 3339 UICLASS_HUB, 3340 UISUBCLASS_HUB, 3341 UIPROTO_FSHUB, 3342 0 3343 }; 3344 3345 const usb_endpoint_descriptor_t uhci_endpd = { 3346 USB_ENDPOINT_DESCRIPTOR_SIZE, 3347 UDESC_ENDPOINT, 3348 UE_DIR_IN | UHCI_INTR_ENDPT, 3349 UE_INTERRUPT, 3350 {8}, 3351 255 3352 }; 3353 3354 const usb_hub_descriptor_t uhci_hubd_piix = { 3355 USB_HUB_DESCRIPTOR_SIZE, 3356 UDESC_HUB, 3357 2, 3358 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3359 50, /* power on to power good */ 3360 0, 3361 { 0x00 }, /* both ports are removable */ 3362 { 0 }, 3363 }; 3364 3365 /* 3366 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3367 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3368 * should not be used by the USB subsystem. As we cannot issue a 3369 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3370 * will be enabled as part of the reset. 3371 * 3372 * On the VT83C572, the port cannot be successfully enabled until the 3373 * outstanding "port enable change" and "connection status change" 3374 * events have been reset. 3375 */ 3376 Static usbd_status 3377 uhci_portreset(uhci_softc_t *sc, int index) 3378 { 3379 int lim, port, x; 3380 3381 if (index == 1) 3382 port = UHCI_PORTSC1; 3383 else if (index == 2) 3384 port = UHCI_PORTSC2; 3385 else 3386 return (USBD_IOERROR); 3387 3388 x = URWMASK(UREAD2(sc, port)); 3389 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3390 3391 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3392 3393 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3394 index, UREAD2(sc, port))); 3395 3396 x = URWMASK(UREAD2(sc, port)); 3397 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3398 3399 delay(100); 3400 3401 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3402 index, UREAD2(sc, port))); 3403 3404 x = URWMASK(UREAD2(sc, port)); 3405 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3406 3407 for (lim = 10; --lim > 0;) { 3408 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3409 3410 x = UREAD2(sc, port); 3411 3412 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3413 index, lim, x)); 3414 3415 if (!(x & UHCI_PORTSC_CCS)) { 3416 /* 3417 * No device is connected (or was disconnected 3418 * during reset). Consider the port reset. 3419 * The delay must be long enough to ensure on 3420 * the initial iteration that the device 3421 * connection will have been registered. 50ms 3422 * appears to be sufficient, but 20ms is not. 3423 */ 3424 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3425 index, lim)); 3426 break; 3427 } 3428 3429 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3430 /* 3431 * Port enabled changed and/or connection 3432 * status changed were set. Reset either or 3433 * both raised flags (by writing a 1 to that 3434 * bit), and wait again for state to settle. 3435 */ 3436 UWRITE2(sc, port, URWMASK(x) | 3437 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3438 continue; 3439 } 3440 3441 if (x & UHCI_PORTSC_PE) 3442 /* Port is enabled */ 3443 break; 3444 3445 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3446 } 3447 3448 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3449 index, UREAD2(sc, port))); 3450 3451 if (lim <= 0) { 3452 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3453 return (USBD_TIMEOUT); 3454 } 3455 3456 sc->sc_isreset = 1; 3457 return (USBD_NORMAL_COMPLETION); 3458 } 3459 3460 /* 3461 * Simulate a hardware hub by handling all the necessary requests. 3462 */ 3463 usbd_status 3464 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3465 { 3466 usbd_status err; 3467 3468 /* Insert last in queue. */ 3469 err = usb_insert_transfer(xfer); 3470 if (err) 3471 return (err); 3472 3473 /* 3474 * Pipe isn't running (otherwise err would be USBD_INPROG), 3475 * so start it first. 3476 */ 3477 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3478 } 3479 3480 usbd_status 3481 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3482 { 3483 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3484 usb_device_request_t *req; 3485 void *buf = NULL; 3486 int port, x; 3487 int s, len, value, index, status, change, l, totlen = 0; 3488 usb_port_status_t ps; 3489 usbd_status err; 3490 3491 if (sc->sc_dying) 3492 return (USBD_IOERROR); 3493 3494 #ifdef DIAGNOSTIC 3495 if (!(xfer->rqflags & URQ_REQUEST)) 3496 panic("uhci_root_ctrl_transfer: not a request"); 3497 #endif 3498 req = &xfer->request; 3499 3500 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3501 req->bmRequestType, req->bRequest)); 3502 3503 len = UGETW(req->wLength); 3504 value = UGETW(req->wValue); 3505 index = UGETW(req->wIndex); 3506 3507 if (len != 0) 3508 buf = KERNADDR(&xfer->dmabuf, 0); 3509 3510 #define C(x,y) ((x) | ((y) << 8)) 3511 switch(C(req->bRequest, req->bmRequestType)) { 3512 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3513 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3514 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3515 /* 3516 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3517 * for the integrated root hub. 3518 */ 3519 break; 3520 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3521 if (len > 0) { 3522 *(u_int8_t *)buf = sc->sc_conf; 3523 totlen = 1; 3524 } 3525 break; 3526 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3527 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3528 if (len == 0) 3529 break; 3530 switch(value >> 8) { 3531 case UDESC_DEVICE: 3532 if ((value & 0xff) != 0) { 3533 err = USBD_IOERROR; 3534 goto ret; 3535 } 3536 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3537 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3538 memcpy(buf, &uhci_devd, l); 3539 break; 3540 case UDESC_CONFIG: 3541 if ((value & 0xff) != 0) { 3542 err = USBD_IOERROR; 3543 goto ret; 3544 } 3545 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3546 memcpy(buf, &uhci_confd, l); 3547 buf = (char *)buf + l; 3548 len -= l; 3549 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3550 totlen += l; 3551 memcpy(buf, &uhci_ifcd, l); 3552 buf = (char *)buf + l; 3553 len -= l; 3554 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3555 totlen += l; 3556 memcpy(buf, &uhci_endpd, l); 3557 break; 3558 case UDESC_STRING: 3559 #define sd ((usb_string_descriptor_t *)buf) 3560 switch (value & 0xff) { 3561 case 0: /* Language table */ 3562 totlen = usb_makelangtbl(sd, len); 3563 break; 3564 case 1: /* Vendor */ 3565 totlen = usb_makestrdesc(sd, len, 3566 sc->sc_vendor); 3567 break; 3568 case 2: /* Product */ 3569 totlen = usb_makestrdesc(sd, len, 3570 "UHCI root hub"); 3571 break; 3572 } 3573 #undef sd 3574 break; 3575 default: 3576 err = USBD_IOERROR; 3577 goto ret; 3578 } 3579 break; 3580 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3581 if (len > 0) { 3582 *(u_int8_t *)buf = 0; 3583 totlen = 1; 3584 } 3585 break; 3586 case C(UR_GET_STATUS, UT_READ_DEVICE): 3587 if (len > 1) { 3588 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3589 totlen = 2; 3590 } 3591 break; 3592 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3593 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3594 if (len > 1) { 3595 USETW(((usb_status_t *)buf)->wStatus, 0); 3596 totlen = 2; 3597 } 3598 break; 3599 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3600 if (value >= USB_MAX_DEVICES) { 3601 err = USBD_IOERROR; 3602 goto ret; 3603 } 3604 sc->sc_addr = value; 3605 break; 3606 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3607 if (value != 0 && value != 1) { 3608 err = USBD_IOERROR; 3609 goto ret; 3610 } 3611 sc->sc_conf = value; 3612 break; 3613 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3614 break; 3615 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3616 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3617 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3618 err = USBD_IOERROR; 3619 goto ret; 3620 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3621 break; 3622 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3623 break; 3624 /* Hub requests */ 3625 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3626 break; 3627 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3628 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3629 "port=%d feature=%d\n", 3630 index, value)); 3631 if (index == 1) 3632 port = UHCI_PORTSC1; 3633 else if (index == 2) 3634 port = UHCI_PORTSC2; 3635 else { 3636 err = USBD_IOERROR; 3637 goto ret; 3638 } 3639 switch(value) { 3640 case UHF_PORT_ENABLE: 3641 x = URWMASK(UREAD2(sc, port)); 3642 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3643 break; 3644 case UHF_PORT_SUSPEND: 3645 x = URWMASK(UREAD2(sc, port)); 3646 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3647 break; 3648 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3649 /* see USB2 spec ch. 7.1.7.7 */ 3650 usb_delay_ms(&sc->sc_bus, 20); 3651 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3652 /* 10ms resume delay must be provided by caller */ 3653 break; 3654 case UHF_PORT_RESET: 3655 x = URWMASK(UREAD2(sc, port)); 3656 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3657 break; 3658 case UHF_C_PORT_CONNECTION: 3659 x = URWMASK(UREAD2(sc, port)); 3660 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3661 break; 3662 case UHF_C_PORT_ENABLE: 3663 x = URWMASK(UREAD2(sc, port)); 3664 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3665 break; 3666 case UHF_C_PORT_OVER_CURRENT: 3667 x = URWMASK(UREAD2(sc, port)); 3668 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3669 break; 3670 case UHF_C_PORT_RESET: 3671 sc->sc_isreset = 0; 3672 err = USBD_NORMAL_COMPLETION; 3673 goto ret; 3674 case UHF_PORT_CONNECTION: 3675 case UHF_PORT_OVER_CURRENT: 3676 case UHF_PORT_POWER: 3677 case UHF_PORT_LOW_SPEED: 3678 case UHF_C_PORT_SUSPEND: 3679 default: 3680 err = USBD_IOERROR; 3681 goto ret; 3682 } 3683 break; 3684 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3685 if (index == 1) 3686 port = UHCI_PORTSC1; 3687 else if (index == 2) 3688 port = UHCI_PORTSC2; 3689 else { 3690 err = USBD_IOERROR; 3691 goto ret; 3692 } 3693 if (len > 0) { 3694 *(u_int8_t *)buf = 3695 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3696 UHCI_PORTSC_LS_SHIFT; 3697 totlen = 1; 3698 } 3699 break; 3700 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3701 if (len == 0) 3702 break; 3703 if ((value & 0xff) != 0) { 3704 err = USBD_IOERROR; 3705 goto ret; 3706 } 3707 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3708 totlen = l; 3709 memcpy(buf, &uhci_hubd_piix, l); 3710 break; 3711 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3712 if (len != 4) { 3713 err = USBD_IOERROR; 3714 goto ret; 3715 } 3716 memset(buf, 0, len); 3717 totlen = len; 3718 break; 3719 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3720 if (index == 1) 3721 port = UHCI_PORTSC1; 3722 else if (index == 2) 3723 port = UHCI_PORTSC2; 3724 else { 3725 err = USBD_IOERROR; 3726 goto ret; 3727 } 3728 if (len != 4) { 3729 err = USBD_IOERROR; 3730 goto ret; 3731 } 3732 x = UREAD2(sc, port); 3733 status = change = 0; 3734 if (x & UHCI_PORTSC_CCS) 3735 status |= UPS_CURRENT_CONNECT_STATUS; 3736 if (x & UHCI_PORTSC_CSC) 3737 change |= UPS_C_CONNECT_STATUS; 3738 if (x & UHCI_PORTSC_PE) 3739 status |= UPS_PORT_ENABLED; 3740 if (x & UHCI_PORTSC_POEDC) 3741 change |= UPS_C_PORT_ENABLED; 3742 if (x & UHCI_PORTSC_OCI) 3743 status |= UPS_OVERCURRENT_INDICATOR; 3744 if (x & UHCI_PORTSC_OCIC) 3745 change |= UPS_C_OVERCURRENT_INDICATOR; 3746 if (x & UHCI_PORTSC_SUSP) 3747 status |= UPS_SUSPEND; 3748 if (x & UHCI_PORTSC_LSDA) 3749 status |= UPS_LOW_SPEED; 3750 status |= UPS_PORT_POWER; 3751 if (sc->sc_isreset) 3752 change |= UPS_C_PORT_RESET; 3753 USETW(ps.wPortStatus, status); 3754 USETW(ps.wPortChange, change); 3755 l = min(len, sizeof ps); 3756 memcpy(buf, &ps, l); 3757 totlen = l; 3758 break; 3759 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3760 err = USBD_IOERROR; 3761 goto ret; 3762 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3763 break; 3764 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3765 if (index == 1) 3766 port = UHCI_PORTSC1; 3767 else if (index == 2) 3768 port = UHCI_PORTSC2; 3769 else { 3770 err = USBD_IOERROR; 3771 goto ret; 3772 } 3773 switch(value) { 3774 case UHF_PORT_ENABLE: 3775 x = URWMASK(UREAD2(sc, port)); 3776 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3777 break; 3778 case UHF_PORT_SUSPEND: 3779 x = URWMASK(UREAD2(sc, port)); 3780 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3781 break; 3782 case UHF_PORT_RESET: 3783 err = uhci_portreset(sc, index); 3784 goto ret; 3785 case UHF_PORT_POWER: 3786 /* Pretend we turned on power */ 3787 err = USBD_NORMAL_COMPLETION; 3788 goto ret; 3789 case UHF_C_PORT_CONNECTION: 3790 case UHF_C_PORT_ENABLE: 3791 case UHF_C_PORT_OVER_CURRENT: 3792 case UHF_PORT_CONNECTION: 3793 case UHF_PORT_OVER_CURRENT: 3794 case UHF_PORT_LOW_SPEED: 3795 case UHF_C_PORT_SUSPEND: 3796 case UHF_C_PORT_RESET: 3797 default: 3798 err = USBD_IOERROR; 3799 goto ret; 3800 } 3801 break; 3802 default: 3803 err = USBD_IOERROR; 3804 goto ret; 3805 } 3806 xfer->actlen = totlen; 3807 err = USBD_NORMAL_COMPLETION; 3808 ret: 3809 xfer->status = err; 3810 s = splusb(); 3811 usb_transfer_complete(xfer); 3812 splx(s); 3813 return (USBD_IN_PROGRESS); 3814 } 3815 3816 /* Abort a root control request. */ 3817 void 3818 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3819 { 3820 /* Nothing to do, all transfers are synchronous. */ 3821 } 3822 3823 /* Close the root pipe. */ 3824 void 3825 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3826 { 3827 DPRINTF(("uhci_root_ctrl_close\n")); 3828 } 3829 3830 /* Abort a root interrupt request. */ 3831 void 3832 uhci_root_intr_abort(usbd_xfer_handle xfer) 3833 { 3834 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3835 3836 callout_stop(&sc->sc_poll_handle); 3837 sc->sc_intr_xfer = NULL; 3838 3839 if (xfer->pipe->intrxfer == xfer) { 3840 DPRINTF(("uhci_root_intr_abort: remove\n")); 3841 xfer->pipe->intrxfer = 0; 3842 } 3843 xfer->status = USBD_CANCELLED; 3844 #ifdef DIAGNOSTIC 3845 UXFER(xfer)->iinfo.isdone = 1; 3846 #endif 3847 usb_transfer_complete(xfer); 3848 } 3849 3850 usbd_status 3851 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3852 { 3853 usbd_status err; 3854 3855 /* Insert last in queue. */ 3856 err = usb_insert_transfer(xfer); 3857 if (err) 3858 return (err); 3859 3860 /* 3861 * Pipe isn't running (otherwise err would be USBD_INPROG), 3862 * start first 3863 */ 3864 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3865 } 3866 3867 /* Start a transfer on the root interrupt pipe */ 3868 usbd_status 3869 uhci_root_intr_start(usbd_xfer_handle xfer) 3870 { 3871 usbd_pipe_handle pipe = xfer->pipe; 3872 uhci_softc_t *sc = pipe->device->bus->hci_private; 3873 unsigned int ival; 3874 3875 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3876 xfer, xfer->length, xfer->flags)); 3877 3878 if (sc->sc_dying) 3879 return (USBD_IOERROR); 3880 3881 /* XXX temporary variable needed to avoid gcc3 warning */ 3882 ival = xfer->pipe->endpoint->edesc->bInterval; 3883 sc->sc_ival = mstohz(ival); 3884 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3885 sc->sc_intr_xfer = xfer; 3886 return (USBD_IN_PROGRESS); 3887 } 3888 3889 /* Close the root interrupt pipe. */ 3890 void 3891 uhci_root_intr_close(usbd_pipe_handle pipe) 3892 { 3893 uhci_softc_t *sc = pipe->device->bus->hci_private; 3894 3895 callout_stop(&sc->sc_poll_handle); 3896 sc->sc_intr_xfer = NULL; 3897 DPRINTF(("uhci_root_intr_close\n")); 3898 } 3899
Indexes created Tue Sep 30 20:09:53 GMT 2025