uhci.c revision 1.249.2.1
1 /* $NetBSD: uhci.c,v 1.249.2.1 2013/02/25 00:29:39 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.249.2.1 2013/02/25 00:29:39 tls Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run, int locked); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 169 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 170 171 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 172 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 173 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 static __inline uint32_t 267 UREAD4(uhci_softc_t *sc, bus_size_t r) 268 { 269 270 UBARR(sc); 271 return bus_space_read_4(sc->iot, sc->ioh, r); 272 } 273 274 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 275 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 276 277 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 278 279 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 280 281 #define UHCI_INTR_ENDPT 1 282 283 const struct usbd_bus_methods uhci_bus_methods = { 284 .open_pipe = uhci_open, 285 .soft_intr = uhci_softintr, 286 .do_poll = uhci_poll, 287 .allocm = uhci_allocm, 288 .freem = uhci_freem, 289 .allocx = uhci_allocx, 290 .freex = uhci_freex, 291 .get_lock = uhci_get_lock, 292 }; 293 294 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 295 .transfer = uhci_root_ctrl_transfer, 296 .start = uhci_root_ctrl_start, 297 .abort = uhci_root_ctrl_abort, 298 .close = uhci_root_ctrl_close, 299 .cleartoggle = uhci_noop, 300 .done = uhci_root_ctrl_done, 301 }; 302 303 const struct usbd_pipe_methods uhci_root_intr_methods = { 304 .transfer = uhci_root_intr_transfer, 305 .start = uhci_root_intr_start, 306 .abort = uhci_root_intr_abort, 307 .close = uhci_root_intr_close, 308 .cleartoggle = uhci_noop, 309 .done = uhci_root_intr_done, 310 }; 311 312 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 313 .transfer = uhci_device_ctrl_transfer, 314 .start = uhci_device_ctrl_start, 315 .abort = uhci_device_ctrl_abort, 316 .close = uhci_device_ctrl_close, 317 .cleartoggle = uhci_noop, 318 .done = uhci_device_ctrl_done, 319 }; 320 321 const struct usbd_pipe_methods uhci_device_intr_methods = { 322 .transfer = uhci_device_intr_transfer, 323 .start = uhci_device_intr_start, 324 .abort = uhci_device_intr_abort, 325 .close = uhci_device_intr_close, 326 .cleartoggle = uhci_device_clear_toggle, 327 .done = uhci_device_intr_done, 328 }; 329 330 const struct usbd_pipe_methods uhci_device_bulk_methods = { 331 .transfer = uhci_device_bulk_transfer, 332 .start = uhci_device_bulk_start, 333 .abort = uhci_device_bulk_abort, 334 .close = uhci_device_bulk_close, 335 .cleartoggle = uhci_device_clear_toggle, 336 .done = uhci_device_bulk_done, 337 }; 338 339 const struct usbd_pipe_methods uhci_device_isoc_methods = { 340 .transfer = uhci_device_isoc_transfer, 341 .start = uhci_device_isoc_start, 342 .abort = uhci_device_isoc_abort, 343 .close = uhci_device_isoc_close, 344 .cleartoggle = uhci_noop, 345 .done = uhci_device_isoc_done, 346 }; 347 348 #define uhci_add_intr_info(sc, ii) \ 349 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 350 #define uhci_del_intr_info(ii) \ 351 do { \ 352 LIST_REMOVE((ii), list); \ 353 (ii)->list.le_prev = NULL; \ 354 } while (0) 355 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 356 357 static inline uhci_soft_qh_t * 358 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 359 { 360 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 361 362 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 363 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 364 usb_syncmem(&pqh->dma, 365 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 366 sizeof(pqh->qh.qh_hlink), 367 BUS_DMASYNC_POSTWRITE); 368 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 369 printf("uhci_find_prev_qh: QH not found\n"); 370 return (NULL); 371 } 372 #endif 373 } 374 return (pqh); 375 } 376 377 void 378 uhci_globalreset(uhci_softc_t *sc) 379 { 380 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 381 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 382 UHCICMD(sc, 0); /* do nothing */ 383 } 384 385 usbd_status 386 uhci_init(uhci_softc_t *sc) 387 { 388 usbd_status err; 389 int i, j; 390 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 391 uhci_soft_td_t *std; 392 393 DPRINTFN(1,("uhci_init: start\n")); 394 395 #ifdef UHCI_DEBUG 396 thesc = sc; 397 398 if (uhcidebug > 2) 399 uhci_dumpregs(sc); 400 #endif 401 402 sc->sc_suspend = PWR_RESUME; 403 404 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 405 uhci_globalreset(sc); /* reset the controller */ 406 uhci_reset(sc); 407 408 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 409 USB_MEM_RESERVE); 410 411 /* Allocate and initialize real frame array. */ 412 err = usb_allocmem(&sc->sc_bus, 413 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 414 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 415 if (err) 416 return (err); 417 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 418 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 419 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 420 421 /* 422 * Allocate a TD, inactive, that hangs from the last QH. 423 * This is to avoid a bug in the PIIX that makes it run berserk 424 * otherwise. 425 */ 426 std = uhci_alloc_std(sc); 427 if (std == NULL) 428 return (USBD_NOMEM); 429 std->link.std = NULL; 430 std->td.td_link = htole32(UHCI_PTR_T); 431 std->td.td_status = htole32(0); /* inactive */ 432 std->td.td_token = htole32(0); 433 std->td.td_buffer = htole32(0); 434 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 436 437 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 438 lsqh = uhci_alloc_sqh(sc); 439 if (lsqh == NULL) 440 return (USBD_NOMEM); 441 lsqh->hlink = NULL; 442 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 443 lsqh->elink = std; 444 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 445 sc->sc_last_qh = lsqh; 446 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 448 449 /* Allocate the dummy QH where bulk traffic will be queued. */ 450 bsqh = uhci_alloc_sqh(sc); 451 if (bsqh == NULL) 452 return (USBD_NOMEM); 453 bsqh->hlink = lsqh; 454 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 455 bsqh->elink = NULL; 456 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 457 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 458 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 460 461 /* Allocate dummy QH where high speed control traffic will be queued. */ 462 chsqh = uhci_alloc_sqh(sc); 463 if (chsqh == NULL) 464 return (USBD_NOMEM); 465 chsqh->hlink = bsqh; 466 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 467 chsqh->elink = NULL; 468 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 469 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 470 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 472 473 /* Allocate dummy QH where control traffic will be queued. */ 474 clsqh = uhci_alloc_sqh(sc); 475 if (clsqh == NULL) 476 return (USBD_NOMEM); 477 clsqh->hlink = chsqh; 478 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 479 clsqh->elink = NULL; 480 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 481 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 482 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* 486 * Make all (virtual) frame list pointers point to the interrupt 487 * queue heads and the interrupt queue heads at the control 488 * queue head and point the physical frame list to the virtual. 489 */ 490 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 491 std = uhci_alloc_std(sc); 492 sqh = uhci_alloc_sqh(sc); 493 if (std == NULL || sqh == NULL) 494 return (USBD_NOMEM); 495 std->link.sqh = sqh; 496 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 497 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 498 std->td.td_token = htole32(0); 499 std->td.td_buffer = htole32(0); 500 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 502 sqh->hlink = clsqh; 503 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 504 sqh->elink = NULL; 505 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 506 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 sc->sc_vframes[i].htd = std; 509 sc->sc_vframes[i].etd = std; 510 sc->sc_vframes[i].hqh = sqh; 511 sc->sc_vframes[i].eqh = sqh; 512 for (j = i; 513 j < UHCI_FRAMELIST_COUNT; 514 j += UHCI_VFRAMELIST_COUNT) 515 sc->sc_pframes[j] = htole32(std->physaddr); 516 } 517 usb_syncmem(&sc->sc_dma, 0, 518 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 519 BUS_DMASYNC_PREWRITE); 520 521 522 LIST_INIT(&sc->sc_intrhead); 523 524 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 525 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 526 527 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 528 529 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 530 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 531 cv_init(&sc->sc_softwake_cv, "uhciab"); 532 533 /* Set up the bus struct. */ 534 sc->sc_bus.methods = &uhci_bus_methods; 535 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 536 537 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 538 539 DPRINTFN(1,("uhci_init: enabling\n")); 540 541 err = uhci_run(sc, 1, 0); /* and here we go... */ 542 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 543 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 544 return err; 545 } 546 547 int 548 uhci_activate(device_t self, enum devact act) 549 { 550 struct uhci_softc *sc = device_private(self); 551 552 switch (act) { 553 case DVACT_DEACTIVATE: 554 sc->sc_dying = 1; 555 return 0; 556 default: 557 return EOPNOTSUPP; 558 } 559 } 560 561 void 562 uhci_childdet(device_t self, device_t child) 563 { 564 struct uhci_softc *sc = device_private(self); 565 566 KASSERT(sc->sc_child == child); 567 sc->sc_child = NULL; 568 } 569 570 int 571 uhci_detach(struct uhci_softc *sc, int flags) 572 { 573 int rv = 0; 574 575 if (sc->sc_child != NULL) 576 rv = config_detach(sc->sc_child, flags); 577 578 if (rv != 0) 579 return (rv); 580 581 callout_halt(&sc->sc_poll_handle, NULL); 582 callout_destroy(&sc->sc_poll_handle); 583 584 cv_destroy(&sc->sc_softwake_cv); 585 586 mutex_destroy(&sc->sc_lock); 587 mutex_destroy(&sc->sc_intr_lock); 588 589 pool_cache_destroy(sc->sc_xferpool); 590 591 /* XXX free other data structures XXX */ 592 593 return (rv); 594 } 595 596 usbd_status 597 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 598 { 599 struct uhci_softc *sc = bus->hci_private; 600 usbd_status status; 601 u_int32_t n; 602 603 /* 604 * XXX 605 * Since we are allocating a buffer we can assume that we will 606 * need TDs for it. Since we don't want to allocate those from 607 * an interrupt context, we allocate them here and free them again. 608 * This is no guarantee that we'll get the TDs next time... 609 */ 610 n = size / 8; 611 if (n > 16) { 612 u_int32_t i; 613 uhci_soft_td_t **stds; 614 615 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 616 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 617 if (!stds) 618 return USBD_NOMEM; 619 for(i = 0; i < n; i++) 620 stds[i] = uhci_alloc_std(sc); 621 for(i = 0; i < n; i++) 622 if (stds[i] != NULL) 623 uhci_free_std(sc, stds[i]); 624 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 625 } 626 627 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 628 if (status == USBD_NOMEM) 629 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 630 return status; 631 } 632 633 void 634 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 635 { 636 if (dma->block->flags & USB_DMA_RESERVE) { 637 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 638 dma); 639 return; 640 } 641 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 642 } 643 644 usbd_xfer_handle 645 uhci_allocx(struct usbd_bus *bus) 646 { 647 struct uhci_softc *sc = bus->hci_private; 648 usbd_xfer_handle xfer; 649 650 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 651 if (xfer != NULL) { 652 memset(xfer, 0, sizeof(struct uhci_xfer)); 653 UXFER(xfer)->iinfo.sc = sc; 654 #ifdef DIAGNOSTIC 655 UXFER(xfer)->iinfo.isdone = 1; 656 xfer->busy_free = XFER_BUSY; 657 #endif 658 } 659 return (xfer); 660 } 661 662 void 663 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 664 { 665 struct uhci_softc *sc = bus->hci_private; 666 667 #ifdef DIAGNOSTIC 668 if (xfer->busy_free != XFER_BUSY) { 669 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 670 xfer->busy_free); 671 } 672 xfer->busy_free = XFER_FREE; 673 if (!UXFER(xfer)->iinfo.isdone) { 674 printf("uhci_freex: !isdone\n"); 675 } 676 #endif 677 pool_cache_put(sc->sc_xferpool, xfer); 678 } 679 680 Static void 681 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 682 { 683 struct uhci_softc *sc = bus->hci_private; 684 685 *lock = &sc->sc_lock; 686 } 687 688 689 /* 690 * Handle suspend/resume. 691 * 692 * We need to switch to polling mode here, because this routine is 693 * called from an interrupt context. This is all right since we 694 * are almost suspended anyway. 695 */ 696 bool 697 uhci_resume(device_t dv, const pmf_qual_t *qual) 698 { 699 uhci_softc_t *sc = device_private(dv); 700 int cmd; 701 702 mutex_spin_enter(&sc->sc_intr_lock); 703 704 cmd = UREAD2(sc, UHCI_CMD); 705 sc->sc_bus.use_polling++; 706 UWRITE2(sc, UHCI_INTR, 0); 707 uhci_globalreset(sc); 708 uhci_reset(sc); 709 if (cmd & UHCI_CMD_RS) 710 uhci_run(sc, 0, 1); 711 712 /* restore saved state */ 713 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 714 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 715 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 716 717 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 718 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 719 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 720 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 721 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 722 UHCICMD(sc, UHCI_CMD_MAXP); 723 uhci_run(sc, 1, 1); /* and start traffic again */ 724 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 725 sc->sc_bus.use_polling--; 726 if (sc->sc_intr_xfer != NULL) 727 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 728 sc->sc_intr_xfer); 729 #ifdef UHCI_DEBUG 730 if (uhcidebug > 2) 731 uhci_dumpregs(sc); 732 #endif 733 734 sc->sc_suspend = PWR_RESUME; 735 mutex_spin_exit(&sc->sc_intr_lock); 736 737 return true; 738 } 739 740 bool 741 uhci_suspend(device_t dv, const pmf_qual_t *qual) 742 { 743 uhci_softc_t *sc = device_private(dv); 744 int cmd; 745 746 mutex_spin_enter(&sc->sc_intr_lock); 747 748 cmd = UREAD2(sc, UHCI_CMD); 749 750 #ifdef UHCI_DEBUG 751 if (uhcidebug > 2) 752 uhci_dumpregs(sc); 753 #endif 754 if (sc->sc_intr_xfer != NULL) 755 callout_stop(&sc->sc_poll_handle); 756 sc->sc_suspend = PWR_SUSPEND; 757 sc->sc_bus.use_polling++; 758 759 uhci_run(sc, 0, 1); /* stop the controller */ 760 cmd &= ~UHCI_CMD_RS; 761 762 /* save some state if BIOS doesn't */ 763 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 764 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 765 766 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 767 768 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 769 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 770 sc->sc_bus.use_polling--; 771 772 mutex_spin_exit(&sc->sc_intr_lock); 773 774 return true; 775 } 776 777 #ifdef UHCI_DEBUG 778 Static void 779 uhci_dumpregs(uhci_softc_t *sc) 780 { 781 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 782 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 783 device_xname(sc->sc_dev), 784 UREAD2(sc, UHCI_CMD), 785 UREAD2(sc, UHCI_STS), 786 UREAD2(sc, UHCI_INTR), 787 UREAD2(sc, UHCI_FRNUM), 788 UREAD4(sc, UHCI_FLBASEADDR), 789 UREAD1(sc, UHCI_SOF), 790 UREAD2(sc, UHCI_PORTSC1), 791 UREAD2(sc, UHCI_PORTSC2))); 792 } 793 794 void 795 uhci_dump_td(uhci_soft_td_t *p) 796 { 797 char sbuf[128], sbuf2[128]; 798 799 800 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 801 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 802 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 803 "token=0x%08lx buffer=0x%08lx\n", 804 p, (long)p->physaddr, 805 (long)le32toh(p->td.td_link), 806 (long)le32toh(p->td.td_status), 807 (long)le32toh(p->td.td_token), 808 (long)le32toh(p->td.td_buffer))); 809 810 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 811 (u_int32_t)le32toh(p->td.td_link)); 812 snprintb(sbuf2, sizeof(sbuf2), 813 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 814 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 815 (u_int32_t)le32toh(p->td.td_status)); 816 817 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 818 "D=%d,maxlen=%d\n", sbuf, sbuf2, 819 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 820 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 821 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 822 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 823 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 824 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 825 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 826 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 827 BUS_DMASYNC_PREREAD); 828 } 829 830 void 831 uhci_dump_qh(uhci_soft_qh_t *sqh) 832 { 833 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 834 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 835 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 836 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 837 le32toh(sqh->qh.qh_elink))); 838 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 839 } 840 841 842 #if 1 843 void 844 uhci_dump(void) 845 { 846 uhci_dump_all(thesc); 847 } 848 #endif 849 850 void 851 uhci_dump_all(uhci_softc_t *sc) 852 { 853 uhci_dumpregs(sc); 854 printf("intrs=%d\n", sc->sc_bus.no_intrs); 855 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 856 uhci_dump_qh(sc->sc_lctl_start); 857 } 858 859 860 void 861 uhci_dump_qhs(uhci_soft_qh_t *sqh) 862 { 863 uhci_dump_qh(sqh); 864 865 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 866 * Traverses sideways first, then down. 867 * 868 * QH1 869 * QH2 870 * No QH 871 * TD2.1 872 * TD2.2 873 * TD1.1 874 * etc. 875 * 876 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 877 */ 878 879 880 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 881 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 882 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 883 uhci_dump_qhs(sqh->hlink); 884 else 885 DPRINTF(("No QH\n")); 886 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 887 888 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 889 uhci_dump_tds(sqh->elink); 890 else 891 DPRINTF(("No TD\n")); 892 } 893 894 void 895 uhci_dump_tds(uhci_soft_td_t *std) 896 { 897 uhci_soft_td_t *td; 898 int stop; 899 900 for(td = std; td != NULL; td = td->link.std) { 901 uhci_dump_td(td); 902 903 /* Check whether the link pointer in this TD marks 904 * the link pointer as end of queue. This avoids 905 * printing the free list in case the queue/TD has 906 * already been moved there (seatbelt). 907 */ 908 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 909 sizeof(td->td.td_link), 910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 911 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 912 le32toh(td->td.td_link) == 0); 913 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 914 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 915 if (stop) 916 break; 917 } 918 } 919 920 Static void 921 uhci_dump_ii(uhci_intr_info_t *ii) 922 { 923 usbd_pipe_handle pipe; 924 usb_endpoint_descriptor_t *ed; 925 usbd_device_handle dev; 926 927 #ifdef DIAGNOSTIC 928 #define DONE ii->isdone 929 #else 930 #define DONE 0 931 #endif 932 if (ii == NULL) { 933 printf("ii NULL\n"); 934 return; 935 } 936 if (ii->xfer == NULL) { 937 printf("ii %p: done=%d xfer=NULL\n", 938 ii, DONE); 939 return; 940 } 941 pipe = ii->xfer->pipe; 942 if (pipe == NULL) { 943 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 944 ii, DONE, ii->xfer); 945 return; 946 } 947 if (pipe->endpoint == NULL) { 948 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 949 ii, DONE, ii->xfer, pipe); 950 return; 951 } 952 if (pipe->device == NULL) { 953 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 954 ii, DONE, ii->xfer, pipe); 955 return; 956 } 957 ed = pipe->endpoint->edesc; 958 dev = pipe->device; 959 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 960 ii, DONE, ii->xfer, dev, 961 UGETW(dev->ddesc.idVendor), 962 UGETW(dev->ddesc.idProduct), 963 dev->address, pipe, 964 ed->bEndpointAddress, ed->bmAttributes); 965 #undef DONE 966 } 967 968 void uhci_dump_iis(struct uhci_softc *sc); 969 void 970 uhci_dump_iis(struct uhci_softc *sc) 971 { 972 uhci_intr_info_t *ii; 973 974 printf("intr_info list:\n"); 975 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 976 uhci_dump_ii(ii); 977 } 978 979 void iidump(void); 980 void iidump(void) { uhci_dump_iis(thesc); } 981 982 #endif 983 984 /* 985 * This routine is executed periodically and simulates interrupts 986 * from the root controller interrupt pipe for port status change. 987 */ 988 void 989 uhci_poll_hub(void *addr) 990 { 991 usbd_xfer_handle xfer = addr; 992 usbd_pipe_handle pipe = xfer->pipe; 993 uhci_softc_t *sc; 994 u_char *p; 995 996 DPRINTFN(20, ("uhci_poll_hub\n")); 997 998 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 999 return; /* device has detached */ 1000 sc = pipe->device->bus->hci_private; 1001 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1002 1003 p = KERNADDR(&xfer->dmabuf, 0); 1004 p[0] = 0; 1005 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1006 p[0] |= 1<<1; 1007 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1008 p[0] |= 1<<2; 1009 if (p[0] == 0) 1010 /* No change, try again in a while */ 1011 return; 1012 1013 xfer->actlen = 1; 1014 xfer->status = USBD_NORMAL_COMPLETION; 1015 mutex_enter(&sc->sc_lock); 1016 usb_transfer_complete(xfer); 1017 mutex_exit(&sc->sc_lock); 1018 } 1019 1020 void 1021 uhci_root_intr_done(usbd_xfer_handle xfer) 1022 { 1023 } 1024 1025 void 1026 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1027 { 1028 } 1029 1030 /* 1031 * Let the last QH loop back to the high speed control transfer QH. 1032 * This is what intel calls "bandwidth reclamation" and improves 1033 * USB performance a lot for some devices. 1034 * If we are already looping, just count it. 1035 */ 1036 void 1037 uhci_add_loop(uhci_softc_t *sc) { 1038 #ifdef UHCI_DEBUG 1039 if (uhcinoloop) 1040 return; 1041 #endif 1042 if (++sc->sc_loops == 1) { 1043 DPRINTFN(5,("uhci_start_loop: add\n")); 1044 /* Note, we don't loop back the soft pointer. */ 1045 sc->sc_last_qh->qh.qh_hlink = 1046 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1047 usb_syncmem(&sc->sc_last_qh->dma, 1048 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1049 sizeof(sc->sc_last_qh->qh.qh_hlink), 1050 BUS_DMASYNC_PREWRITE); 1051 } 1052 } 1053 1054 void 1055 uhci_rem_loop(uhci_softc_t *sc) { 1056 #ifdef UHCI_DEBUG 1057 if (uhcinoloop) 1058 return; 1059 #endif 1060 if (--sc->sc_loops == 0) { 1061 DPRINTFN(5,("uhci_end_loop: remove\n")); 1062 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1063 usb_syncmem(&sc->sc_last_qh->dma, 1064 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1065 sizeof(sc->sc_last_qh->qh.qh_hlink), 1066 BUS_DMASYNC_PREWRITE); 1067 } 1068 } 1069 1070 /* Add high speed control QH, called with lock held. */ 1071 void 1072 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1073 { 1074 uhci_soft_qh_t *eqh; 1075 1076 KASSERT(mutex_owned(&sc->sc_lock)); 1077 1078 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1079 eqh = sc->sc_hctl_end; 1080 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1081 sizeof(eqh->qh.qh_hlink), 1082 BUS_DMASYNC_POSTWRITE); 1083 sqh->hlink = eqh->hlink; 1084 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1085 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1086 BUS_DMASYNC_PREWRITE); 1087 eqh->hlink = sqh; 1088 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1089 sc->sc_hctl_end = sqh; 1090 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1091 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1092 #ifdef UHCI_CTL_LOOP 1093 uhci_add_loop(sc); 1094 #endif 1095 } 1096 1097 /* Remove high speed control QH, called with lock held. */ 1098 void 1099 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1100 { 1101 uhci_soft_qh_t *pqh; 1102 uint32_t elink; 1103 1104 KASSERT(mutex_owned(&sc->sc_lock)); 1105 1106 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1107 #ifdef UHCI_CTL_LOOP 1108 uhci_rem_loop(sc); 1109 #endif 1110 /* 1111 * The T bit should be set in the elink of the QH so that the HC 1112 * doesn't follow the pointer. This condition may fail if the 1113 * the transferred packet was short so that the QH still points 1114 * at the last used TD. 1115 * In this case we set the T bit and wait a little for the HC 1116 * to stop looking at the TD. 1117 * Note that if the TD chain is large enough, the controller 1118 * may still be looking at the chain at the end of this function. 1119 * uhci_free_std_chain() will make sure the controller stops 1120 * looking at it quickly, but until then we should not change 1121 * sqh->hlink. 1122 */ 1123 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1124 sizeof(sqh->qh.qh_elink), 1125 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1126 elink = le32toh(sqh->qh.qh_elink); 1127 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1128 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1129 if (!(elink & UHCI_PTR_T)) { 1130 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1131 usb_syncmem(&sqh->dma, 1132 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1133 sizeof(sqh->qh.qh_elink), 1134 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1135 delay(UHCI_QH_REMOVE_DELAY); 1136 } 1137 1138 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1139 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1140 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1141 pqh->hlink = sqh->hlink; 1142 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1143 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1144 sizeof(pqh->qh.qh_hlink), 1145 BUS_DMASYNC_PREWRITE); 1146 delay(UHCI_QH_REMOVE_DELAY); 1147 if (sc->sc_hctl_end == sqh) 1148 sc->sc_hctl_end = pqh; 1149 } 1150 1151 /* Add low speed control QH, called with lock held. */ 1152 void 1153 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1154 { 1155 uhci_soft_qh_t *eqh; 1156 1157 KASSERT(mutex_owned(&sc->sc_lock)); 1158 1159 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1160 eqh = sc->sc_lctl_end; 1161 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1162 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1163 sqh->hlink = eqh->hlink; 1164 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1165 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1166 BUS_DMASYNC_PREWRITE); 1167 eqh->hlink = sqh; 1168 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1169 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1170 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1171 sc->sc_lctl_end = sqh; 1172 } 1173 1174 /* Remove low speed control QH, called with lock held. */ 1175 void 1176 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1177 { 1178 uhci_soft_qh_t *pqh; 1179 uint32_t elink; 1180 1181 KASSERT(mutex_owned(&sc->sc_lock)); 1182 1183 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1184 /* See comment in uhci_remove_hs_ctrl() */ 1185 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1186 sizeof(sqh->qh.qh_elink), 1187 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1188 elink = le32toh(sqh->qh.qh_elink); 1189 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1190 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1191 if (!(elink & UHCI_PTR_T)) { 1192 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1193 usb_syncmem(&sqh->dma, 1194 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1195 sizeof(sqh->qh.qh_elink), 1196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1197 delay(UHCI_QH_REMOVE_DELAY); 1198 } 1199 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1200 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1201 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1202 pqh->hlink = sqh->hlink; 1203 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1204 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1205 sizeof(pqh->qh.qh_hlink), 1206 BUS_DMASYNC_PREWRITE); 1207 delay(UHCI_QH_REMOVE_DELAY); 1208 if (sc->sc_lctl_end == sqh) 1209 sc->sc_lctl_end = pqh; 1210 } 1211 1212 /* Add bulk QH, called with lock held. */ 1213 void 1214 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1215 { 1216 uhci_soft_qh_t *eqh; 1217 1218 KASSERT(mutex_owned(&sc->sc_lock)); 1219 1220 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1221 eqh = sc->sc_bulk_end; 1222 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1223 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1224 sqh->hlink = eqh->hlink; 1225 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1226 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1227 BUS_DMASYNC_PREWRITE); 1228 eqh->hlink = sqh; 1229 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1230 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1231 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1232 sc->sc_bulk_end = sqh; 1233 uhci_add_loop(sc); 1234 } 1235 1236 /* Remove bulk QH, called with lock held. */ 1237 void 1238 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1239 { 1240 uhci_soft_qh_t *pqh; 1241 1242 KASSERT(mutex_owned(&sc->sc_lock)); 1243 1244 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1245 uhci_rem_loop(sc); 1246 /* See comment in uhci_remove_hs_ctrl() */ 1247 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1248 sizeof(sqh->qh.qh_elink), 1249 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1250 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1251 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1252 usb_syncmem(&sqh->dma, 1253 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1254 sizeof(sqh->qh.qh_elink), 1255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1256 delay(UHCI_QH_REMOVE_DELAY); 1257 } 1258 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1259 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1260 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1261 pqh->hlink = sqh->hlink; 1262 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1263 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1264 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1265 delay(UHCI_QH_REMOVE_DELAY); 1266 if (sc->sc_bulk_end == sqh) 1267 sc->sc_bulk_end = pqh; 1268 } 1269 1270 Static int uhci_intr1(uhci_softc_t *); 1271 1272 int 1273 uhci_intr(void *arg) 1274 { 1275 uhci_softc_t *sc = arg; 1276 int ret = 0; 1277 1278 mutex_spin_enter(&sc->sc_intr_lock); 1279 1280 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1281 goto done; 1282 1283 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1284 #ifdef DIAGNOSTIC 1285 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1286 #endif 1287 goto done; 1288 } 1289 1290 ret = uhci_intr1(sc); 1291 1292 done: 1293 mutex_spin_exit(&sc->sc_intr_lock); 1294 return ret; 1295 } 1296 1297 int 1298 uhci_intr1(uhci_softc_t *sc) 1299 { 1300 int status; 1301 int ack; 1302 1303 #ifdef UHCI_DEBUG 1304 if (uhcidebug > 15) { 1305 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1306 uhci_dumpregs(sc); 1307 } 1308 #endif 1309 1310 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1311 1312 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1313 if (status == 0) /* The interrupt was not for us. */ 1314 return (0); 1315 1316 if (sc->sc_suspend != PWR_RESUME) { 1317 #ifdef DIAGNOSTIC 1318 printf("%s: interrupt while not operating ignored\n", 1319 device_xname(sc->sc_dev)); 1320 #endif 1321 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1322 return (0); 1323 } 1324 1325 ack = 0; 1326 if (status & UHCI_STS_USBINT) 1327 ack |= UHCI_STS_USBINT; 1328 if (status & UHCI_STS_USBEI) 1329 ack |= UHCI_STS_USBEI; 1330 if (status & UHCI_STS_RD) { 1331 ack |= UHCI_STS_RD; 1332 #ifdef UHCI_DEBUG 1333 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1334 #endif 1335 } 1336 if (status & UHCI_STS_HSE) { 1337 ack |= UHCI_STS_HSE; 1338 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1339 } 1340 if (status & UHCI_STS_HCPE) { 1341 ack |= UHCI_STS_HCPE; 1342 printf("%s: host controller process error\n", 1343 device_xname(sc->sc_dev)); 1344 } 1345 1346 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1347 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1348 /* no acknowledge needed */ 1349 if (!sc->sc_dying) { 1350 printf("%s: host controller halted\n", 1351 device_xname(sc->sc_dev)); 1352 #ifdef UHCI_DEBUG 1353 uhci_dump_all(sc); 1354 #endif 1355 } 1356 sc->sc_dying = 1; 1357 } 1358 1359 if (!ack) 1360 return (0); /* nothing to acknowledge */ 1361 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1362 1363 sc->sc_bus.no_intrs++; 1364 usb_schedsoftintr(&sc->sc_bus); 1365 1366 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1367 1368 return (1); 1369 } 1370 1371 void 1372 uhci_softintr(void *v) 1373 { 1374 struct usbd_bus *bus = v; 1375 uhci_softc_t *sc = bus->hci_private; 1376 uhci_intr_info_t *ii, *nextii; 1377 1378 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1379 1380 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1381 1382 /* 1383 * Interrupts on UHCI really suck. When the host controller 1384 * interrupts because a transfer is completed there is no 1385 * way of knowing which transfer it was. You can scan down 1386 * the TDs and QHs of the previous frame to limit the search, 1387 * but that assumes that the interrupt was not delayed by more 1388 * than 1 ms, which may not always be true (e.g. after debug 1389 * output on a slow console). 1390 * We scan all interrupt descriptors to see if any have 1391 * completed. 1392 */ 1393 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1394 nextii = LIST_NEXT(ii, list); 1395 uhci_check_intr(sc, ii); 1396 } 1397 1398 if (sc->sc_softwake) { 1399 sc->sc_softwake = 0; 1400 cv_broadcast(&sc->sc_softwake_cv); 1401 } 1402 } 1403 1404 /* Check for an interrupt. */ 1405 void 1406 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1407 { 1408 uhci_soft_td_t *std, *lstd; 1409 u_int32_t status; 1410 1411 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1412 #ifdef DIAGNOSTIC 1413 if (ii == NULL) { 1414 printf("uhci_check_intr: no ii? %p\n", ii); 1415 return; 1416 } 1417 #endif 1418 if (ii->xfer->status == USBD_CANCELLED || 1419 ii->xfer->status == USBD_TIMEOUT) { 1420 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1421 return; 1422 } 1423 1424 if (ii->stdstart == NULL) 1425 return; 1426 lstd = ii->stdend; 1427 #ifdef DIAGNOSTIC 1428 if (lstd == NULL) { 1429 printf("uhci_check_intr: std==0\n"); 1430 return; 1431 } 1432 #endif 1433 /* 1434 * If the last TD is still active we need to check whether there 1435 * is an error somewhere in the middle, or whether there was a 1436 * short packet (SPD and not ACTIVE). 1437 */ 1438 usb_syncmem(&lstd->dma, 1439 lstd->offs + offsetof(uhci_td_t, td_status), 1440 sizeof(lstd->td.td_status), 1441 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1442 status = le32toh(lstd->td.td_status); 1443 usb_syncmem(&lstd->dma, 1444 lstd->offs + offsetof(uhci_td_t, td_status), 1445 sizeof(lstd->td.td_status), 1446 BUS_DMASYNC_PREREAD); 1447 if (status & UHCI_TD_ACTIVE) { 1448 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1449 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1450 usb_syncmem(&std->dma, 1451 std->offs + offsetof(uhci_td_t, td_status), 1452 sizeof(std->td.td_status), 1453 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1454 status = le32toh(std->td.td_status); 1455 usb_syncmem(&std->dma, 1456 std->offs + offsetof(uhci_td_t, td_status), 1457 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1458 /* If there's an active TD the xfer isn't done. */ 1459 if (status & UHCI_TD_ACTIVE) 1460 break; 1461 /* Any kind of error makes the xfer done. */ 1462 if (status & UHCI_TD_STALLED) 1463 goto done; 1464 /* We want short packets, and it is short: it's done */ 1465 usb_syncmem(&std->dma, 1466 std->offs + offsetof(uhci_td_t, td_token), 1467 sizeof(std->td.td_token), 1468 BUS_DMASYNC_POSTWRITE); 1469 if ((status & UHCI_TD_SPD) && 1470 UHCI_TD_GET_ACTLEN(status) < 1471 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) 1472 goto done; 1473 } 1474 DPRINTFN(12, ("uhci_check_intr: ii=%p std=%p still active\n", 1475 ii, ii->stdstart)); 1476 return; 1477 } 1478 done: 1479 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1480 callout_stop(&ii->xfer->timeout_handle); 1481 uhci_idone(ii); 1482 } 1483 1484 /* Called with USB lock held. */ 1485 void 1486 uhci_idone(uhci_intr_info_t *ii) 1487 { 1488 usbd_xfer_handle xfer = ii->xfer; 1489 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1490 #ifdef DIAGNOSTIC 1491 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1492 #endif 1493 uhci_soft_td_t *std; 1494 u_int32_t status = 0, nstatus; 1495 int actlen; 1496 1497 KASSERT(mutex_owned(&sc->sc_lock)); 1498 1499 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1500 #ifdef DIAGNOSTIC 1501 { 1502 /* XXX SMP? */ 1503 int s = splhigh(); 1504 if (ii->isdone) { 1505 splx(s); 1506 #ifdef UHCI_DEBUG 1507 printf("uhci_idone: ii is done!\n "); 1508 uhci_dump_ii(ii); 1509 #else 1510 printf("uhci_idone: ii=%p is done!\n", ii); 1511 #endif 1512 return; 1513 } 1514 ii->isdone = 1; 1515 splx(s); 1516 } 1517 #endif 1518 1519 if (xfer->nframes != 0) { 1520 /* Isoc transfer, do things differently. */ 1521 uhci_soft_td_t **stds = upipe->u.iso.stds; 1522 int i, n, nframes, len; 1523 1524 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1525 1526 nframes = xfer->nframes; 1527 actlen = 0; 1528 n = UXFER(xfer)->curframe; 1529 for (i = 0; i < nframes; i++) { 1530 std = stds[n]; 1531 #ifdef UHCI_DEBUG 1532 if (uhcidebug > 5) { 1533 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1534 uhci_dump_td(std); 1535 } 1536 #endif 1537 if (++n >= UHCI_VFRAMELIST_COUNT) 1538 n = 0; 1539 usb_syncmem(&std->dma, 1540 std->offs + offsetof(uhci_td_t, td_status), 1541 sizeof(std->td.td_status), 1542 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1543 status = le32toh(std->td.td_status); 1544 len = UHCI_TD_GET_ACTLEN(status); 1545 xfer->frlengths[i] = len; 1546 actlen += len; 1547 } 1548 upipe->u.iso.inuse -= nframes; 1549 xfer->actlen = actlen; 1550 xfer->status = USBD_NORMAL_COMPLETION; 1551 goto end; 1552 } 1553 1554 #ifdef UHCI_DEBUG 1555 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1556 ii, xfer, upipe)); 1557 if (uhcidebug > 10) 1558 uhci_dump_tds(ii->stdstart); 1559 #endif 1560 1561 /* The transfer is done, compute actual length and status. */ 1562 actlen = 0; 1563 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1564 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1565 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1566 nstatus = le32toh(std->td.td_status); 1567 if (nstatus & UHCI_TD_ACTIVE) 1568 break; 1569 1570 status = nstatus; 1571 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1572 UHCI_TD_PID_SETUP) 1573 actlen += UHCI_TD_GET_ACTLEN(status); 1574 else { 1575 /* 1576 * UHCI will report CRCTO in addition to a STALL or NAK 1577 * for a SETUP transaction. See section 3.2.2, "TD 1578 * CONTROL AND STATUS". 1579 */ 1580 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1581 status &= ~UHCI_TD_CRCTO; 1582 } 1583 } 1584 /* If there are left over TDs we need to update the toggle. */ 1585 if (std != NULL) 1586 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1587 1588 status &= UHCI_TD_ERROR; 1589 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1590 actlen, status)); 1591 xfer->actlen = actlen; 1592 if (status != 0) { 1593 #ifdef UHCI_DEBUG 1594 char sbuf[128]; 1595 1596 snprintb(sbuf, sizeof(sbuf), 1597 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1598 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1599 1600 DPRINTFN((status == UHCI_TD_STALLED)*10, 1601 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1602 "status 0x%s\n", 1603 xfer->pipe->device->address, 1604 xfer->pipe->endpoint->edesc->bEndpointAddress, 1605 sbuf)); 1606 #endif 1607 1608 if (status == UHCI_TD_STALLED) 1609 xfer->status = USBD_STALLED; 1610 else 1611 xfer->status = USBD_IOERROR; /* more info XXX */ 1612 } else { 1613 xfer->status = USBD_NORMAL_COMPLETION; 1614 } 1615 1616 end: 1617 usb_transfer_complete(xfer); 1618 KASSERT(mutex_owned(&sc->sc_lock)); 1619 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1620 } 1621 1622 /* 1623 * Called when a request does not complete. 1624 */ 1625 void 1626 uhci_timeout(void *addr) 1627 { 1628 uhci_intr_info_t *ii = addr; 1629 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1630 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1631 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1632 1633 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1634 1635 if (sc->sc_dying) { 1636 mutex_enter(&sc->sc_lock); 1637 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1638 mutex_exit(&sc->sc_lock); 1639 return; 1640 } 1641 1642 /* Execute the abort in a process context. */ 1643 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1644 USB_TASKQ_MPSAFE); 1645 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1646 USB_TASKQ_HC); 1647 } 1648 1649 void 1650 uhci_timeout_task(void *addr) 1651 { 1652 usbd_xfer_handle xfer = addr; 1653 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1654 1655 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1656 1657 mutex_enter(&sc->sc_lock); 1658 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1659 mutex_exit(&sc->sc_lock); 1660 } 1661 1662 /* 1663 * Wait here until controller claims to have an interrupt. 1664 * Then call uhci_intr and return. Use timeout to avoid waiting 1665 * too long. 1666 * Only used during boot when interrupts are not enabled yet. 1667 */ 1668 void 1669 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1670 { 1671 int timo = xfer->timeout; 1672 uhci_intr_info_t *ii; 1673 1674 mutex_enter(&sc->sc_lock); 1675 1676 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1677 1678 xfer->status = USBD_IN_PROGRESS; 1679 for (; timo >= 0; timo--) { 1680 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1681 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1682 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1683 mutex_spin_enter(&sc->sc_intr_lock); 1684 uhci_intr1(sc); 1685 mutex_spin_exit(&sc->sc_intr_lock); 1686 if (xfer->status != USBD_IN_PROGRESS) 1687 goto done; 1688 } 1689 } 1690 1691 /* Timeout */ 1692 DPRINTF(("uhci_waitintr: timeout\n")); 1693 for (ii = LIST_FIRST(&sc->sc_intrhead); 1694 ii != NULL && ii->xfer != xfer; 1695 ii = LIST_NEXT(ii, list)) 1696 ; 1697 #ifdef DIAGNOSTIC 1698 if (ii == NULL) 1699 panic("uhci_waitintr: lost intr_info"); 1700 #endif 1701 uhci_idone(ii); 1702 1703 done: 1704 mutex_exit(&sc->sc_lock); 1705 } 1706 1707 void 1708 uhci_poll(struct usbd_bus *bus) 1709 { 1710 uhci_softc_t *sc = bus->hci_private; 1711 1712 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1713 mutex_spin_enter(&sc->sc_intr_lock); 1714 uhci_intr1(sc); 1715 mutex_spin_exit(&sc->sc_intr_lock); 1716 } 1717 } 1718 1719 void 1720 uhci_reset(uhci_softc_t *sc) 1721 { 1722 int n; 1723 1724 UHCICMD(sc, UHCI_CMD_HCRESET); 1725 /* The reset bit goes low when the controller is done. */ 1726 for (n = 0; n < UHCI_RESET_TIMEOUT && 1727 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1728 usb_delay_ms(&sc->sc_bus, 1); 1729 if (n >= UHCI_RESET_TIMEOUT) 1730 printf("%s: controller did not reset\n", 1731 device_xname(sc->sc_dev)); 1732 } 1733 1734 usbd_status 1735 uhci_run(uhci_softc_t *sc, int run, int locked) 1736 { 1737 int n, running; 1738 u_int16_t cmd; 1739 1740 run = run != 0; 1741 if (!locked) 1742 mutex_spin_enter(&sc->sc_intr_lock); 1743 DPRINTF(("uhci_run: setting run=%d\n", run)); 1744 cmd = UREAD2(sc, UHCI_CMD); 1745 if (run) 1746 cmd |= UHCI_CMD_RS; 1747 else 1748 cmd &= ~UHCI_CMD_RS; 1749 UHCICMD(sc, cmd); 1750 for(n = 0; n < 10; n++) { 1751 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1752 /* return when we've entered the state we want */ 1753 if (run == running) { 1754 if (!locked) 1755 mutex_spin_exit(&sc->sc_intr_lock); 1756 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1757 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1758 return (USBD_NORMAL_COMPLETION); 1759 } 1760 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1761 } 1762 if (!locked) 1763 mutex_spin_exit(&sc->sc_intr_lock); 1764 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1765 run ? "start" : "stop"); 1766 return (USBD_IOERROR); 1767 } 1768 1769 /* 1770 * Memory management routines. 1771 * uhci_alloc_std allocates TDs 1772 * uhci_alloc_sqh allocates QHs 1773 * These two routines do their own free list management, 1774 * partly for speed, partly because allocating DMAable memory 1775 * has page size granularaity so much memory would be wasted if 1776 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1777 */ 1778 1779 uhci_soft_td_t * 1780 uhci_alloc_std(uhci_softc_t *sc) 1781 { 1782 uhci_soft_td_t *std; 1783 usbd_status err; 1784 int i, offs; 1785 usb_dma_t dma; 1786 1787 if (sc->sc_freetds == NULL) { 1788 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1789 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1790 UHCI_TD_ALIGN, &dma); 1791 if (err) 1792 return (0); 1793 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1794 offs = i * UHCI_STD_SIZE; 1795 std = KERNADDR(&dma, offs); 1796 std->physaddr = DMAADDR(&dma, offs); 1797 std->dma = dma; 1798 std->offs = offs; 1799 std->link.std = sc->sc_freetds; 1800 sc->sc_freetds = std; 1801 } 1802 } 1803 std = sc->sc_freetds; 1804 sc->sc_freetds = std->link.std; 1805 memset(&std->td, 0, sizeof(uhci_td_t)); 1806 return std; 1807 } 1808 1809 void 1810 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1811 { 1812 #ifdef DIAGNOSTIC 1813 #define TD_IS_FREE 0x12345678 1814 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1815 printf("uhci_free_std: freeing free TD %p\n", std); 1816 return; 1817 } 1818 std->td.td_token = htole32(TD_IS_FREE); 1819 #endif 1820 std->link.std = sc->sc_freetds; 1821 sc->sc_freetds = std; 1822 } 1823 1824 uhci_soft_qh_t * 1825 uhci_alloc_sqh(uhci_softc_t *sc) 1826 { 1827 uhci_soft_qh_t *sqh; 1828 usbd_status err; 1829 int i, offs; 1830 usb_dma_t dma; 1831 1832 if (sc->sc_freeqhs == NULL) { 1833 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1834 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1835 UHCI_QH_ALIGN, &dma); 1836 if (err) 1837 return (0); 1838 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1839 offs = i * UHCI_SQH_SIZE; 1840 sqh = KERNADDR(&dma, offs); 1841 sqh->physaddr = DMAADDR(&dma, offs); 1842 sqh->dma = dma; 1843 sqh->offs = offs; 1844 sqh->hlink = sc->sc_freeqhs; 1845 sc->sc_freeqhs = sqh; 1846 } 1847 } 1848 sqh = sc->sc_freeqhs; 1849 sc->sc_freeqhs = sqh->hlink; 1850 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1851 return (sqh); 1852 } 1853 1854 void 1855 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1856 { 1857 sqh->hlink = sc->sc_freeqhs; 1858 sc->sc_freeqhs = sqh; 1859 } 1860 1861 void 1862 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1863 uhci_soft_td_t *stdend) 1864 { 1865 uhci_soft_td_t *p; 1866 uint32_t td_link; 1867 1868 /* 1869 * to avoid race condition with the controller which may be looking 1870 * at this chain, we need to first invalidate all links, and 1871 * then wait for the controller to move to another queue 1872 */ 1873 for (p = std; p != stdend; p = p->link.std) { 1874 usb_syncmem(&p->dma, 1875 p->offs + offsetof(uhci_td_t, td_link), 1876 sizeof(p->td.td_link), 1877 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1878 td_link = le32toh(p->td.td_link); 1879 usb_syncmem(&p->dma, 1880 p->offs + offsetof(uhci_td_t, td_link), 1881 sizeof(p->td.td_link), 1882 BUS_DMASYNC_PREREAD); 1883 if ((td_link & UHCI_PTR_T) == 0) { 1884 p->td.td_link = htole32(UHCI_PTR_T); 1885 usb_syncmem(&p->dma, 1886 p->offs + offsetof(uhci_td_t, td_link), 1887 sizeof(p->td.td_link), 1888 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1889 } 1890 } 1891 delay(UHCI_QH_REMOVE_DELAY); 1892 1893 for (; std != stdend; std = p) { 1894 p = std->link.std; 1895 uhci_free_std(sc, std); 1896 } 1897 } 1898 1899 usbd_status 1900 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1901 int rd, u_int16_t flags, usb_dma_t *dma, 1902 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1903 { 1904 uhci_soft_td_t *p, *lastp; 1905 uhci_physaddr_t lastlink; 1906 int i, ntd, l, tog, maxp; 1907 u_int32_t status; 1908 int addr = upipe->pipe.device->address; 1909 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1910 1911 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1912 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1913 upipe->pipe.device->speed, flags)); 1914 1915 KASSERT(mutex_owned(&sc->sc_lock)); 1916 1917 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1918 if (maxp == 0) { 1919 printf("uhci_alloc_std_chain: maxp=0\n"); 1920 return (USBD_INVAL); 1921 } 1922 ntd = (len + maxp - 1) / maxp; 1923 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1924 ntd++; 1925 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1926 if (ntd == 0) { 1927 *sp = *ep = 0; 1928 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1929 return (USBD_NORMAL_COMPLETION); 1930 } 1931 tog = upipe->nexttoggle; 1932 if (ntd % 2 == 0) 1933 tog ^= 1; 1934 upipe->nexttoggle = tog ^ 1; 1935 lastp = NULL; 1936 lastlink = UHCI_PTR_T; 1937 ntd--; 1938 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1939 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1940 status |= UHCI_TD_LS; 1941 if (flags & USBD_SHORT_XFER_OK) 1942 status |= UHCI_TD_SPD; 1943 usb_syncmem(dma, 0, len, 1944 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1945 for (i = ntd; i >= 0; i--) { 1946 p = uhci_alloc_std(sc); 1947 if (p == NULL) { 1948 KASSERT(lastp != NULL); 1949 uhci_free_std_chain(sc, lastp, NULL); 1950 return (USBD_NOMEM); 1951 } 1952 p->link.std = lastp; 1953 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1954 lastp = p; 1955 lastlink = p->physaddr; 1956 p->td.td_status = htole32(status); 1957 if (i == ntd) { 1958 /* last TD */ 1959 l = len % maxp; 1960 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1961 l = maxp; 1962 *ep = p; 1963 } else 1964 l = maxp; 1965 p->td.td_token = 1966 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1967 UHCI_TD_OUT(l, endpt, addr, tog)); 1968 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1969 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1970 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1971 tog ^= 1; 1972 } 1973 *sp = lastp; 1974 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1975 upipe->nexttoggle)); 1976 return (USBD_NORMAL_COMPLETION); 1977 } 1978 1979 void 1980 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1981 { 1982 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1983 upipe->nexttoggle = 0; 1984 } 1985 1986 void 1987 uhci_noop(usbd_pipe_handle pipe) 1988 { 1989 } 1990 1991 usbd_status 1992 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1993 { 1994 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1995 usbd_status err; 1996 1997 /* Insert last in queue. */ 1998 mutex_enter(&sc->sc_lock); 1999 err = usb_insert_transfer(xfer); 2000 mutex_exit(&sc->sc_lock); 2001 if (err) 2002 return (err); 2003 2004 /* 2005 * Pipe isn't running (otherwise err would be USBD_INPROG), 2006 * so start it first. 2007 */ 2008 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2009 } 2010 2011 usbd_status 2012 uhci_device_bulk_start(usbd_xfer_handle xfer) 2013 { 2014 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2015 usbd_device_handle dev = upipe->pipe.device; 2016 uhci_softc_t *sc = dev->bus->hci_private; 2017 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2018 uhci_soft_td_t *data, *dataend; 2019 uhci_soft_qh_t *sqh; 2020 usbd_status err; 2021 int len, isread, endpt; 2022 2023 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2024 xfer, xfer->length, xfer->flags, ii)); 2025 2026 if (sc->sc_dying) 2027 return (USBD_IOERROR); 2028 2029 #ifdef DIAGNOSTIC 2030 if (xfer->rqflags & URQ_REQUEST) 2031 panic("uhci_device_bulk_transfer: a request"); 2032 #endif 2033 2034 mutex_enter(&sc->sc_lock); 2035 2036 len = xfer->length; 2037 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2038 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2039 sqh = upipe->u.bulk.sqh; 2040 2041 upipe->u.bulk.isread = isread; 2042 upipe->u.bulk.length = len; 2043 2044 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2045 &xfer->dmabuf, &data, &dataend); 2046 if (err) { 2047 mutex_exit(&sc->sc_lock); 2048 return (err); 2049 } 2050 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2051 usb_syncmem(&dataend->dma, 2052 dataend->offs + offsetof(uhci_td_t, td_status), 2053 sizeof(dataend->td.td_status), 2054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2055 2056 2057 #ifdef UHCI_DEBUG 2058 if (uhcidebug > 8) { 2059 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2060 uhci_dump_tds(data); 2061 } 2062 #endif 2063 2064 /* Set up interrupt info. */ 2065 ii->xfer = xfer; 2066 ii->stdstart = data; 2067 ii->stdend = dataend; 2068 #ifdef DIAGNOSTIC 2069 if (!ii->isdone) { 2070 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2071 } 2072 ii->isdone = 0; 2073 #endif 2074 2075 sqh->elink = data; 2076 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2077 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2078 2079 uhci_add_bulk(sc, sqh); 2080 uhci_add_intr_info(sc, ii); 2081 2082 if (xfer->timeout && !sc->sc_bus.use_polling) { 2083 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2084 uhci_timeout, ii); 2085 } 2086 xfer->status = USBD_IN_PROGRESS; 2087 2088 #ifdef UHCI_DEBUG 2089 if (uhcidebug > 10) { 2090 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2091 uhci_dump_tds(data); 2092 } 2093 #endif 2094 2095 if (sc->sc_bus.use_polling) 2096 uhci_waitintr(sc, xfer); 2097 2098 mutex_exit(&sc->sc_lock); 2099 return (USBD_IN_PROGRESS); 2100 } 2101 2102 /* Abort a device bulk request. */ 2103 void 2104 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2105 { 2106 #ifdef DIAGNOSTIC 2107 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2108 #endif 2109 2110 KASSERT(mutex_owned(&sc->sc_lock)); 2111 2112 DPRINTF(("uhci_device_bulk_abort:\n")); 2113 uhci_abort_xfer(xfer, USBD_CANCELLED); 2114 } 2115 2116 /* 2117 * Abort a device request. 2118 * If this routine is called at splusb() it guarantees that the request 2119 * will be removed from the hardware scheduling and that the callback 2120 * for it will be called with USBD_CANCELLED status. 2121 * It's impossible to guarantee that the requested transfer will not 2122 * have happened since the hardware runs concurrently. 2123 * If the transaction has already happened we rely on the ordinary 2124 * interrupt processing to process it. 2125 * XXX This is most probably wrong. 2126 * XXXMRG this doesn't make sense anymore. 2127 */ 2128 void 2129 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2130 { 2131 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2132 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2133 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2134 uhci_soft_td_t *std; 2135 int wake; 2136 2137 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2138 2139 KASSERT(mutex_owned(&sc->sc_lock)); 2140 2141 if (sc->sc_dying) { 2142 /* If we're dying, just do the software part. */ 2143 xfer->status = status; /* make software ignore it */ 2144 callout_stop(&xfer->timeout_handle); 2145 usb_transfer_complete(xfer); 2146 return; 2147 } 2148 2149 if (cpu_intr_p() || cpu_softintr_p()) 2150 panic("uhci_abort_xfer: not in process context"); 2151 2152 /* 2153 * If an abort is already in progress then just wait for it to 2154 * complete and return. 2155 */ 2156 if (xfer->hcflags & UXFER_ABORTING) { 2157 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2158 #ifdef DIAGNOSTIC 2159 if (status == USBD_TIMEOUT) 2160 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2161 #endif 2162 /* Override the status which might be USBD_TIMEOUT. */ 2163 xfer->status = status; 2164 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2165 xfer->hcflags |= UXFER_ABORTWAIT; 2166 while (xfer->hcflags & UXFER_ABORTING) 2167 cv_wait(&xfer->hccv, &sc->sc_lock); 2168 goto done; 2169 } 2170 xfer->hcflags |= UXFER_ABORTING; 2171 2172 /* 2173 * Step 1: Make interrupt routine and hardware ignore xfer. 2174 */ 2175 xfer->status = status; /* make software ignore it */ 2176 callout_stop(&xfer->timeout_handle); 2177 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2178 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2179 usb_syncmem(&std->dma, 2180 std->offs + offsetof(uhci_td_t, td_status), 2181 sizeof(std->td.td_status), 2182 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2183 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2184 usb_syncmem(&std->dma, 2185 std->offs + offsetof(uhci_td_t, td_status), 2186 sizeof(std->td.td_status), 2187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2188 } 2189 2190 /* 2191 * Step 2: Wait until we know hardware has finished any possible 2192 * use of the xfer. Also make sure the soft interrupt routine 2193 * has run. 2194 */ 2195 /* Hardware finishes in 1ms */ 2196 usb_delay_ms_locked(upipe->pipe.device->bus, 2, &sc->sc_lock); 2197 sc->sc_softwake = 1; 2198 usb_schedsoftintr(&sc->sc_bus); 2199 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2200 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2201 2202 /* 2203 * Step 3: Execute callback. 2204 */ 2205 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2206 #ifdef DIAGNOSTIC 2207 ii->isdone = 1; 2208 #endif 2209 wake = xfer->hcflags & UXFER_ABORTWAIT; 2210 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2211 usb_transfer_complete(xfer); 2212 if (wake) 2213 cv_broadcast(&xfer->hccv); 2214 done: 2215 KASSERT(mutex_owned(&sc->sc_lock)); 2216 } 2217 2218 /* Close a device bulk pipe. */ 2219 void 2220 uhci_device_bulk_close(usbd_pipe_handle pipe) 2221 { 2222 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2223 usbd_device_handle dev = upipe->pipe.device; 2224 uhci_softc_t *sc = dev->bus->hci_private; 2225 2226 KASSERT(mutex_owned(&sc->sc_lock)); 2227 2228 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2229 2230 pipe->endpoint->datatoggle = upipe->nexttoggle; 2231 } 2232 2233 usbd_status 2234 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2235 { 2236 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2237 usbd_status err; 2238 2239 /* Insert last in queue. */ 2240 mutex_enter(&sc->sc_lock); 2241 err = usb_insert_transfer(xfer); 2242 mutex_exit(&sc->sc_lock); 2243 if (err) 2244 return (err); 2245 2246 /* 2247 * Pipe isn't running (otherwise err would be USBD_INPROG), 2248 * so start it first. 2249 */ 2250 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2251 } 2252 2253 usbd_status 2254 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2255 { 2256 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2257 usbd_status err; 2258 2259 if (sc->sc_dying) 2260 return (USBD_IOERROR); 2261 2262 #ifdef DIAGNOSTIC 2263 if (!(xfer->rqflags & URQ_REQUEST)) 2264 panic("uhci_device_ctrl_transfer: not a request"); 2265 #endif 2266 2267 mutex_enter(&sc->sc_lock); 2268 err = uhci_device_request(xfer); 2269 mutex_exit(&sc->sc_lock); 2270 if (err) 2271 return (err); 2272 2273 if (sc->sc_bus.use_polling) 2274 uhci_waitintr(sc, xfer); 2275 return (USBD_IN_PROGRESS); 2276 } 2277 2278 usbd_status 2279 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2280 { 2281 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2282 usbd_status err; 2283 2284 /* Insert last in queue. */ 2285 mutex_enter(&sc->sc_lock); 2286 err = usb_insert_transfer(xfer); 2287 mutex_exit(&sc->sc_lock); 2288 if (err) 2289 return (err); 2290 2291 /* 2292 * Pipe isn't running (otherwise err would be USBD_INPROG), 2293 * so start it first. 2294 */ 2295 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2296 } 2297 2298 usbd_status 2299 uhci_device_intr_start(usbd_xfer_handle xfer) 2300 { 2301 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2302 usbd_device_handle dev = upipe->pipe.device; 2303 uhci_softc_t *sc = dev->bus->hci_private; 2304 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2305 uhci_soft_td_t *data, *dataend; 2306 uhci_soft_qh_t *sqh; 2307 usbd_status err; 2308 int isread, endpt; 2309 int i; 2310 2311 if (sc->sc_dying) 2312 return (USBD_IOERROR); 2313 2314 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2315 xfer, xfer->length, xfer->flags)); 2316 2317 #ifdef DIAGNOSTIC 2318 if (xfer->rqflags & URQ_REQUEST) 2319 panic("uhci_device_intr_transfer: a request"); 2320 #endif 2321 2322 mutex_enter(&sc->sc_lock); 2323 2324 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2325 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2326 2327 upipe->u.intr.isread = isread; 2328 2329 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2330 xfer->flags, &xfer->dmabuf, &data, 2331 &dataend); 2332 if (err) { 2333 mutex_exit(&sc->sc_lock); 2334 return (err); 2335 } 2336 2337 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2338 usb_syncmem(&dataend->dma, 2339 dataend->offs + offsetof(uhci_td_t, td_status), 2340 sizeof(dataend->td.td_status), 2341 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2342 2343 #ifdef UHCI_DEBUG 2344 if (uhcidebug > 10) { 2345 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2346 uhci_dump_tds(data); 2347 uhci_dump_qh(upipe->u.intr.qhs[0]); 2348 } 2349 #endif 2350 2351 /* Set up interrupt info. */ 2352 ii->xfer = xfer; 2353 ii->stdstart = data; 2354 ii->stdend = dataend; 2355 #ifdef DIAGNOSTIC 2356 if (!ii->isdone) { 2357 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2358 } 2359 ii->isdone = 0; 2360 #endif 2361 2362 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2363 upipe->u.intr.qhs[0])); 2364 for (i = 0; i < upipe->u.intr.npoll; i++) { 2365 sqh = upipe->u.intr.qhs[i]; 2366 sqh->elink = data; 2367 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2368 usb_syncmem(&sqh->dma, 2369 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2370 sizeof(sqh->qh.qh_elink), 2371 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2372 } 2373 uhci_add_intr_info(sc, ii); 2374 xfer->status = USBD_IN_PROGRESS; 2375 mutex_exit(&sc->sc_lock); 2376 2377 #ifdef UHCI_DEBUG 2378 if (uhcidebug > 10) { 2379 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2380 uhci_dump_tds(data); 2381 uhci_dump_qh(upipe->u.intr.qhs[0]); 2382 } 2383 #endif 2384 2385 return (USBD_IN_PROGRESS); 2386 } 2387 2388 /* Abort a device control request. */ 2389 void 2390 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2391 { 2392 #ifdef DIAGNOSTIC 2393 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2394 #endif 2395 2396 KASSERT(mutex_owned(&sc->sc_lock)); 2397 2398 DPRINTF(("uhci_device_ctrl_abort:\n")); 2399 uhci_abort_xfer(xfer, USBD_CANCELLED); 2400 } 2401 2402 /* Close a device control pipe. */ 2403 void 2404 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2405 { 2406 } 2407 2408 /* Abort a device interrupt request. */ 2409 void 2410 uhci_device_intr_abort(usbd_xfer_handle xfer) 2411 { 2412 #ifdef DIAGNOSTIC 2413 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2414 #endif 2415 2416 KASSERT(mutex_owned(&sc->sc_lock)); 2417 2418 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2419 if (xfer->pipe->intrxfer == xfer) { 2420 DPRINTFN(1,("uhci_device_intr_abort: remove\n")); 2421 xfer->pipe->intrxfer = NULL; 2422 } 2423 uhci_abort_xfer(xfer, USBD_CANCELLED); 2424 } 2425 2426 /* Close a device interrupt pipe. */ 2427 void 2428 uhci_device_intr_close(usbd_pipe_handle pipe) 2429 { 2430 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2431 uhci_softc_t *sc = pipe->device->bus->hci_private; 2432 int i, npoll; 2433 2434 KASSERT(mutex_owned(&sc->sc_lock)); 2435 2436 /* Unlink descriptors from controller data structures. */ 2437 npoll = upipe->u.intr.npoll; 2438 for (i = 0; i < npoll; i++) 2439 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2440 2441 /* 2442 * We now have to wait for any activity on the physical 2443 * descriptors to stop. 2444 */ 2445 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2446 2447 for(i = 0; i < npoll; i++) 2448 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2449 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2450 2451 /* XXX free other resources */ 2452 } 2453 2454 usbd_status 2455 uhci_device_request(usbd_xfer_handle xfer) 2456 { 2457 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2458 usb_device_request_t *req = &xfer->request; 2459 usbd_device_handle dev = upipe->pipe.device; 2460 uhci_softc_t *sc = dev->bus->hci_private; 2461 int addr = dev->address; 2462 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2463 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2464 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2465 uhci_soft_qh_t *sqh; 2466 int len; 2467 u_int32_t ls; 2468 usbd_status err; 2469 int isread; 2470 2471 KASSERT(mutex_owned(&sc->sc_lock)); 2472 2473 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2474 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2475 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2476 UGETW(req->wIndex), UGETW(req->wLength), 2477 addr, endpt)); 2478 2479 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2480 isread = req->bmRequestType & UT_READ; 2481 len = UGETW(req->wLength); 2482 2483 setup = upipe->u.ctl.setup; 2484 stat = upipe->u.ctl.stat; 2485 sqh = upipe->u.ctl.sqh; 2486 2487 /* Set up data transaction */ 2488 if (len != 0) { 2489 upipe->nexttoggle = 1; 2490 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2491 &xfer->dmabuf, &data, &dataend); 2492 if (err) 2493 return (err); 2494 next = data; 2495 dataend->link.std = stat; 2496 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2497 usb_syncmem(&dataend->dma, 2498 dataend->offs + offsetof(uhci_td_t, td_link), 2499 sizeof(dataend->td.td_link), 2500 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2501 } else { 2502 next = stat; 2503 } 2504 upipe->u.ctl.length = len; 2505 2506 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2507 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2508 2509 setup->link.std = next; 2510 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_VF | UHCI_PTR_TD); 2511 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2512 UHCI_TD_ACTIVE); 2513 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2514 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2515 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2516 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2517 2518 stat->link.std = NULL; 2519 stat->td.td_link = htole32(UHCI_PTR_T); 2520 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2521 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2522 stat->td.td_token = 2523 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2524 UHCI_TD_IN (0, endpt, addr, 1)); 2525 stat->td.td_buffer = htole32(0); 2526 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2528 2529 #ifdef UHCI_DEBUG 2530 if (uhcidebug > 10) { 2531 DPRINTF(("uhci_device_request: before transfer\n")); 2532 uhci_dump_tds(setup); 2533 } 2534 #endif 2535 2536 /* Set up interrupt info. */ 2537 ii->xfer = xfer; 2538 ii->stdstart = setup; 2539 ii->stdend = stat; 2540 #ifdef DIAGNOSTIC 2541 if (!ii->isdone) { 2542 printf("uhci_device_request: not done, ii=%p\n", ii); 2543 } 2544 ii->isdone = 0; 2545 #endif 2546 2547 sqh->elink = setup; 2548 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2549 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2550 2551 if (dev->speed == USB_SPEED_LOW) 2552 uhci_add_ls_ctrl(sc, sqh); 2553 else 2554 uhci_add_hs_ctrl(sc, sqh); 2555 uhci_add_intr_info(sc, ii); 2556 #ifdef UHCI_DEBUG 2557 if (uhcidebug > 12) { 2558 uhci_soft_td_t *std; 2559 uhci_soft_qh_t *xqh; 2560 uhci_soft_qh_t *sxqh; 2561 int maxqh = 0; 2562 uhci_physaddr_t link; 2563 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2564 for (std = sc->sc_vframes[0].htd, link = 0; 2565 (link & UHCI_PTR_QH) == 0; 2566 std = std->link.std) { 2567 link = le32toh(std->td.td_link); 2568 uhci_dump_td(std); 2569 } 2570 sxqh = (uhci_soft_qh_t *)std; 2571 uhci_dump_qh(sxqh); 2572 for (xqh = sxqh; 2573 xqh != NULL; 2574 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2575 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2576 uhci_dump_qh(xqh); 2577 } 2578 DPRINTF(("Enqueued QH:\n")); 2579 uhci_dump_qh(sqh); 2580 uhci_dump_tds(sqh->elink); 2581 } 2582 #endif 2583 if (xfer->timeout && !sc->sc_bus.use_polling) { 2584 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2585 uhci_timeout, ii); 2586 } 2587 xfer->status = USBD_IN_PROGRESS; 2588 2589 return (USBD_NORMAL_COMPLETION); 2590 } 2591 2592 usbd_status 2593 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2594 { 2595 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2596 usbd_status err; 2597 2598 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2599 2600 /* Put it on our queue, */ 2601 mutex_enter(&sc->sc_lock); 2602 err = usb_insert_transfer(xfer); 2603 mutex_exit(&sc->sc_lock); 2604 2605 /* bail out on error, */ 2606 if (err && err != USBD_IN_PROGRESS) 2607 return (err); 2608 2609 /* XXX should check inuse here */ 2610 2611 /* insert into schedule, */ 2612 uhci_device_isoc_enter(xfer); 2613 2614 /* and start if the pipe wasn't running */ 2615 if (!err) 2616 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2617 2618 return (err); 2619 } 2620 2621 void 2622 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2623 { 2624 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2625 usbd_device_handle dev = upipe->pipe.device; 2626 uhci_softc_t *sc = dev->bus->hci_private; 2627 struct iso *iso = &upipe->u.iso; 2628 uhci_soft_td_t *std; 2629 u_int32_t buf, len, status, offs; 2630 int i, next, nframes; 2631 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2632 2633 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2634 "nframes=%d\n", 2635 iso->inuse, iso->next, xfer, xfer->nframes)); 2636 2637 if (sc->sc_dying) 2638 return; 2639 2640 if (xfer->status == USBD_IN_PROGRESS) { 2641 /* This request has already been entered into the frame list */ 2642 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2643 /* XXX */ 2644 } 2645 2646 #ifdef DIAGNOSTIC 2647 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2648 printf("uhci_device_isoc_enter: overflow!\n"); 2649 #endif 2650 2651 next = iso->next; 2652 if (next == -1) { 2653 /* Not in use yet, schedule it a few frames ahead. */ 2654 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2655 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2656 } 2657 2658 xfer->status = USBD_IN_PROGRESS; 2659 UXFER(xfer)->curframe = next; 2660 2661 buf = DMAADDR(&xfer->dmabuf, 0); 2662 offs = 0; 2663 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2664 UHCI_TD_ACTIVE | 2665 UHCI_TD_IOS); 2666 nframes = xfer->nframes; 2667 mutex_enter(&sc->sc_lock); 2668 for (i = 0; i < nframes; i++) { 2669 std = iso->stds[next]; 2670 if (++next >= UHCI_VFRAMELIST_COUNT) 2671 next = 0; 2672 len = xfer->frlengths[i]; 2673 std->td.td_buffer = htole32(buf); 2674 usb_syncmem(&xfer->dmabuf, offs, len, 2675 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2676 if (i == nframes - 1) 2677 status |= UHCI_TD_IOC; 2678 std->td.td_status = htole32(status); 2679 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2680 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2681 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2682 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2683 #ifdef UHCI_DEBUG 2684 if (uhcidebug > 5) { 2685 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2686 uhci_dump_td(std); 2687 } 2688 #endif 2689 buf += len; 2690 offs += len; 2691 } 2692 iso->next = next; 2693 iso->inuse += xfer->nframes; 2694 2695 mutex_exit(&sc->sc_lock); 2696 } 2697 2698 usbd_status 2699 uhci_device_isoc_start(usbd_xfer_handle xfer) 2700 { 2701 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2702 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2703 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2704 uhci_soft_td_t *end; 2705 int i; 2706 2707 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2708 2709 mutex_enter(&sc->sc_lock); 2710 2711 if (sc->sc_dying) { 2712 mutex_exit(&sc->sc_lock); 2713 return (USBD_IOERROR); 2714 } 2715 2716 #ifdef DIAGNOSTIC 2717 if (xfer->status != USBD_IN_PROGRESS) 2718 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2719 #endif 2720 2721 /* Find the last TD */ 2722 i = UXFER(xfer)->curframe + xfer->nframes; 2723 if (i >= UHCI_VFRAMELIST_COUNT) 2724 i -= UHCI_VFRAMELIST_COUNT; 2725 end = upipe->u.iso.stds[i]; 2726 2727 #ifdef DIAGNOSTIC 2728 if (end == NULL) { 2729 printf("uhci_device_isoc_start: end == NULL\n"); 2730 return (USBD_INVAL); 2731 } 2732 #endif 2733 2734 /* Set up interrupt info. */ 2735 ii->xfer = xfer; 2736 ii->stdstart = end; 2737 ii->stdend = end; 2738 #ifdef DIAGNOSTIC 2739 if (!ii->isdone) 2740 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2741 ii->isdone = 0; 2742 #endif 2743 uhci_add_intr_info(sc, ii); 2744 2745 mutex_exit(&sc->sc_lock); 2746 2747 return (USBD_IN_PROGRESS); 2748 } 2749 2750 void 2751 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2752 { 2753 #ifdef DIAGNOSTIC 2754 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2755 #endif 2756 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2757 uhci_soft_td_t **stds = upipe->u.iso.stds; 2758 uhci_soft_td_t *std; 2759 int i, n, nframes, maxlen, len; 2760 2761 KASSERT(mutex_owned(&sc->sc_lock)); 2762 2763 /* Transfer is already done. */ 2764 if (xfer->status != USBD_NOT_STARTED && 2765 xfer->status != USBD_IN_PROGRESS) { 2766 return; 2767 } 2768 2769 /* Give xfer the requested abort code. */ 2770 xfer->status = USBD_CANCELLED; 2771 2772 /* make hardware ignore it, */ 2773 nframes = xfer->nframes; 2774 n = UXFER(xfer)->curframe; 2775 maxlen = 0; 2776 for (i = 0; i < nframes; i++) { 2777 std = stds[n]; 2778 usb_syncmem(&std->dma, 2779 std->offs + offsetof(uhci_td_t, td_status), 2780 sizeof(std->td.td_status), 2781 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2782 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2783 usb_syncmem(&std->dma, 2784 std->offs + offsetof(uhci_td_t, td_status), 2785 sizeof(std->td.td_status), 2786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2787 usb_syncmem(&std->dma, 2788 std->offs + offsetof(uhci_td_t, td_token), 2789 sizeof(std->td.td_token), 2790 BUS_DMASYNC_POSTWRITE); 2791 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2792 if (len > maxlen) 2793 maxlen = len; 2794 if (++n >= UHCI_VFRAMELIST_COUNT) 2795 n = 0; 2796 } 2797 2798 /* and wait until we are sure the hardware has finished. */ 2799 delay(maxlen); 2800 2801 #ifdef DIAGNOSTIC 2802 UXFER(xfer)->iinfo.isdone = 1; 2803 #endif 2804 /* Run callback and remove from interrupt list. */ 2805 usb_transfer_complete(xfer); 2806 2807 KASSERT(mutex_owned(&sc->sc_lock)); 2808 } 2809 2810 void 2811 uhci_device_isoc_close(usbd_pipe_handle pipe) 2812 { 2813 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2814 usbd_device_handle dev = upipe->pipe.device; 2815 uhci_softc_t *sc = dev->bus->hci_private; 2816 uhci_soft_td_t *std, *vstd; 2817 struct iso *iso; 2818 int i; 2819 2820 KASSERT(mutex_owned(&sc->sc_lock)); 2821 2822 /* 2823 * Make sure all TDs are marked as inactive. 2824 * Wait for completion. 2825 * Unschedule. 2826 * Deallocate. 2827 */ 2828 iso = &upipe->u.iso; 2829 2830 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2831 std = iso->stds[i]; 2832 usb_syncmem(&std->dma, 2833 std->offs + offsetof(uhci_td_t, td_status), 2834 sizeof(std->td.td_status), 2835 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2836 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2837 usb_syncmem(&std->dma, 2838 std->offs + offsetof(uhci_td_t, td_status), 2839 sizeof(std->td.td_status), 2840 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2841 } 2842 /* wait for completion */ 2843 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2844 2845 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2846 std = iso->stds[i]; 2847 for (vstd = sc->sc_vframes[i].htd; 2848 vstd != NULL && vstd->link.std != std; 2849 vstd = vstd->link.std) 2850 ; 2851 if (vstd == NULL) { 2852 /*panic*/ 2853 printf("uhci_device_isoc_close: %p not found\n", std); 2854 mutex_exit(&sc->sc_lock); 2855 return; 2856 } 2857 vstd->link = std->link; 2858 usb_syncmem(&std->dma, 2859 std->offs + offsetof(uhci_td_t, td_link), 2860 sizeof(std->td.td_link), 2861 BUS_DMASYNC_POSTWRITE); 2862 vstd->td.td_link = std->td.td_link; 2863 usb_syncmem(&vstd->dma, 2864 vstd->offs + offsetof(uhci_td_t, td_link), 2865 sizeof(vstd->td.td_link), 2866 BUS_DMASYNC_PREWRITE); 2867 uhci_free_std(sc, std); 2868 } 2869 2870 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2871 } 2872 2873 usbd_status 2874 uhci_setup_isoc(usbd_pipe_handle pipe) 2875 { 2876 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2877 usbd_device_handle dev = upipe->pipe.device; 2878 uhci_softc_t *sc = dev->bus->hci_private; 2879 int addr = upipe->pipe.device->address; 2880 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2881 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2882 uhci_soft_td_t *std, *vstd; 2883 u_int32_t token; 2884 struct iso *iso; 2885 int i; 2886 2887 iso = &upipe->u.iso; 2888 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2889 sizeof (uhci_soft_td_t *), 2890 KM_SLEEP); 2891 if (iso->stds == NULL) 2892 return USBD_NOMEM; 2893 2894 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2895 UHCI_TD_OUT(0, endpt, addr, 0); 2896 2897 mutex_enter(&sc->sc_lock); 2898 2899 /* Allocate the TDs and mark as inactive; */ 2900 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2901 std = uhci_alloc_std(sc); 2902 if (std == 0) 2903 goto bad; 2904 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2905 std->td.td_token = htole32(token); 2906 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2907 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2908 iso->stds[i] = std; 2909 } 2910 2911 /* Insert TDs into schedule. */ 2912 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2913 std = iso->stds[i]; 2914 vstd = sc->sc_vframes[i].htd; 2915 usb_syncmem(&vstd->dma, 2916 vstd->offs + offsetof(uhci_td_t, td_link), 2917 sizeof(vstd->td.td_link), 2918 BUS_DMASYNC_POSTWRITE); 2919 std->link = vstd->link; 2920 std->td.td_link = vstd->td.td_link; 2921 usb_syncmem(&std->dma, 2922 std->offs + offsetof(uhci_td_t, td_link), 2923 sizeof(std->td.td_link), 2924 BUS_DMASYNC_PREWRITE); 2925 vstd->link.std = std; 2926 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2927 usb_syncmem(&vstd->dma, 2928 vstd->offs + offsetof(uhci_td_t, td_link), 2929 sizeof(vstd->td.td_link), 2930 BUS_DMASYNC_PREWRITE); 2931 } 2932 mutex_exit(&sc->sc_lock); 2933 2934 iso->next = -1; 2935 iso->inuse = 0; 2936 2937 return (USBD_NORMAL_COMPLETION); 2938 2939 bad: 2940 while (--i >= 0) 2941 uhci_free_std(sc, iso->stds[i]); 2942 mutex_exit(&sc->sc_lock); 2943 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2944 return (USBD_NOMEM); 2945 } 2946 2947 void 2948 uhci_device_isoc_done(usbd_xfer_handle xfer) 2949 { 2950 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2951 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2952 int i, offs; 2953 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2954 2955 2956 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2957 xfer->actlen, xfer->busy_free)); 2958 2959 if (ii->xfer != xfer) 2960 /* Not on interrupt list, ignore it. */ 2961 return; 2962 2963 if (!uhci_active_intr_info(ii)) 2964 return; 2965 2966 #ifdef DIAGNOSTIC 2967 if (ii->stdend == NULL) { 2968 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2969 #ifdef UHCI_DEBUG 2970 uhci_dump_ii(ii); 2971 #endif 2972 return; 2973 } 2974 #endif 2975 2976 /* Turn off the interrupt since it is active even if the TD is not. */ 2977 usb_syncmem(&ii->stdend->dma, 2978 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2979 sizeof(ii->stdend->td.td_status), 2980 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2981 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2982 usb_syncmem(&ii->stdend->dma, 2983 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2984 sizeof(ii->stdend->td.td_status), 2985 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2986 2987 uhci_del_intr_info(ii); /* remove from active list */ 2988 2989 offs = 0; 2990 for (i = 0; i < xfer->nframes; i++) { 2991 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 2992 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2993 offs += xfer->frlengths[i]; 2994 } 2995 } 2996 2997 void 2998 uhci_device_intr_done(usbd_xfer_handle xfer) 2999 { 3000 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3001 uhci_softc_t *sc = ii->sc; 3002 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3003 uhci_soft_qh_t *sqh; 3004 int i, npoll, isread; 3005 3006 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3007 3008 KASSERT(mutex_owned(&sc->sc_lock)); 3009 3010 npoll = upipe->u.intr.npoll; 3011 for(i = 0; i < npoll; i++) { 3012 sqh = upipe->u.intr.qhs[i]; 3013 sqh->elink = NULL; 3014 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3015 usb_syncmem(&sqh->dma, 3016 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3017 sizeof(sqh->qh.qh_elink), 3018 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3019 } 3020 uhci_free_std_chain(sc, ii->stdstart, NULL); 3021 3022 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3023 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3024 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3025 3026 /* XXX Wasteful. */ 3027 if (xfer->pipe->repeat) { 3028 uhci_soft_td_t *data, *dataend; 3029 3030 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3031 3032 /* This alloc cannot fail since we freed the chain above. */ 3033 uhci_alloc_std_chain(upipe, sc, xfer->length, 3034 upipe->u.intr.isread, xfer->flags, 3035 &xfer->dmabuf, &data, &dataend); 3036 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3037 usb_syncmem(&dataend->dma, 3038 dataend->offs + offsetof(uhci_td_t, td_status), 3039 sizeof(dataend->td.td_status), 3040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3041 3042 #ifdef UHCI_DEBUG 3043 if (uhcidebug > 10) { 3044 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3045 uhci_dump_tds(data); 3046 uhci_dump_qh(upipe->u.intr.qhs[0]); 3047 } 3048 #endif 3049 3050 ii->stdstart = data; 3051 ii->stdend = dataend; 3052 #ifdef DIAGNOSTIC 3053 if (!ii->isdone) { 3054 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3055 } 3056 ii->isdone = 0; 3057 #endif 3058 for (i = 0; i < npoll; i++) { 3059 sqh = upipe->u.intr.qhs[i]; 3060 sqh->elink = data; 3061 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3062 usb_syncmem(&sqh->dma, 3063 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3064 sizeof(sqh->qh.qh_elink), 3065 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3066 } 3067 xfer->status = USBD_IN_PROGRESS; 3068 /* The ii is already on the examined list, just leave it. */ 3069 } else { 3070 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3071 if (uhci_active_intr_info(ii)) 3072 uhci_del_intr_info(ii); 3073 } 3074 } 3075 3076 /* Deallocate request data structures */ 3077 void 3078 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3079 { 3080 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3081 uhci_softc_t *sc = ii->sc; 3082 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3083 int len = UGETW(xfer->request.wLength); 3084 int isread = (xfer->request.bmRequestType & UT_READ); 3085 3086 KASSERT(mutex_owned(&sc->sc_lock)); 3087 3088 #ifdef DIAGNOSTIC 3089 if (!(xfer->rqflags & URQ_REQUEST)) 3090 panic("uhci_device_ctrl_done: not a request"); 3091 #endif 3092 3093 if (!uhci_active_intr_info(ii)) 3094 return; 3095 3096 uhci_del_intr_info(ii); /* remove from active list */ 3097 3098 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3099 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3100 else 3101 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3102 3103 if (upipe->u.ctl.length != 0) 3104 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3105 3106 if (len) { 3107 usb_syncmem(&xfer->dmabuf, 0, len, 3108 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3109 } 3110 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3111 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3112 3113 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3114 } 3115 3116 /* Deallocate request data structures */ 3117 void 3118 uhci_device_bulk_done(usbd_xfer_handle xfer) 3119 { 3120 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3121 uhci_softc_t *sc = ii->sc; 3122 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3123 3124 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3125 xfer, ii, sc, upipe)); 3126 3127 KASSERT(mutex_owned(&sc->sc_lock)); 3128 3129 if (!uhci_active_intr_info(ii)) 3130 return; 3131 3132 uhci_del_intr_info(ii); /* remove from active list */ 3133 3134 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3135 3136 uhci_free_std_chain(sc, ii->stdstart, NULL); 3137 3138 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3139 } 3140 3141 /* Add interrupt QH, called with vflock. */ 3142 void 3143 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3144 { 3145 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3146 uhci_soft_qh_t *eqh; 3147 3148 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3149 3150 eqh = vf->eqh; 3151 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3152 sizeof(eqh->qh.qh_hlink), 3153 BUS_DMASYNC_POSTWRITE); 3154 sqh->hlink = eqh->hlink; 3155 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3156 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3157 sizeof(sqh->qh.qh_hlink), 3158 BUS_DMASYNC_PREWRITE); 3159 eqh->hlink = sqh; 3160 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3161 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3162 sizeof(eqh->qh.qh_hlink), 3163 BUS_DMASYNC_PREWRITE); 3164 vf->eqh = sqh; 3165 vf->bandwidth++; 3166 } 3167 3168 /* Remove interrupt QH. */ 3169 void 3170 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3171 { 3172 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3173 uhci_soft_qh_t *pqh; 3174 3175 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3176 3177 /* See comment in uhci_remove_ctrl() */ 3178 3179 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3180 sizeof(sqh->qh.qh_elink), 3181 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3182 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3183 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3184 usb_syncmem(&sqh->dma, 3185 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3186 sizeof(sqh->qh.qh_elink), 3187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3188 delay(UHCI_QH_REMOVE_DELAY); 3189 } 3190 3191 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3192 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3193 sizeof(sqh->qh.qh_hlink), 3194 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3195 pqh->hlink = sqh->hlink; 3196 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3197 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3198 sizeof(pqh->qh.qh_hlink), 3199 BUS_DMASYNC_PREWRITE); 3200 delay(UHCI_QH_REMOVE_DELAY); 3201 if (vf->eqh == sqh) 3202 vf->eqh = pqh; 3203 vf->bandwidth--; 3204 } 3205 3206 usbd_status 3207 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3208 { 3209 uhci_soft_qh_t *sqh; 3210 int i, npoll; 3211 u_int bestbw, bw, bestoffs, offs; 3212 3213 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3214 if (ival == 0) { 3215 printf("uhci_device_setintr: 0 interval\n"); 3216 return (USBD_INVAL); 3217 } 3218 3219 if (ival > UHCI_VFRAMELIST_COUNT) 3220 ival = UHCI_VFRAMELIST_COUNT; 3221 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3222 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3223 3224 upipe->u.intr.npoll = npoll; 3225 upipe->u.intr.qhs = 3226 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3227 if (upipe->u.intr.qhs == NULL) 3228 return USBD_NOMEM; 3229 3230 /* 3231 * Figure out which offset in the schedule that has most 3232 * bandwidth left over. 3233 */ 3234 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3235 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3236 for (bw = i = 0; i < npoll; i++) 3237 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3238 if (bw < bestbw) { 3239 bestbw = bw; 3240 bestoffs = offs; 3241 } 3242 } 3243 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3244 3245 mutex_enter(&sc->sc_lock); 3246 for(i = 0; i < npoll; i++) { 3247 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3248 sqh->elink = NULL; 3249 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3250 usb_syncmem(&sqh->dma, 3251 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3252 sizeof(sqh->qh.qh_elink), 3253 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3254 sqh->pos = MOD(i * ival + bestoffs); 3255 } 3256 #undef MOD 3257 3258 /* Enter QHs into the controller data structures. */ 3259 for(i = 0; i < npoll; i++) 3260 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3261 mutex_exit(&sc->sc_lock); 3262 3263 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3264 return (USBD_NORMAL_COMPLETION); 3265 } 3266 3267 /* Open a new pipe. */ 3268 usbd_status 3269 uhci_open(usbd_pipe_handle pipe) 3270 { 3271 uhci_softc_t *sc = pipe->device->bus->hci_private; 3272 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3273 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3274 usbd_status err = USBD_NOMEM; 3275 int ival; 3276 3277 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3278 pipe, pipe->device->address, 3279 ed->bEndpointAddress, sc->sc_addr)); 3280 3281 if (sc->sc_dying) 3282 return USBD_IOERROR; 3283 3284 upipe->aborting = 0; 3285 /* toggle state needed for bulk endpoints */ 3286 upipe->nexttoggle = pipe->endpoint->datatoggle; 3287 3288 if (pipe->device->address == sc->sc_addr) { 3289 switch (ed->bEndpointAddress) { 3290 case USB_CONTROL_ENDPOINT: 3291 pipe->methods = &uhci_root_ctrl_methods; 3292 break; 3293 case UE_DIR_IN | UHCI_INTR_ENDPT: 3294 pipe->methods = &uhci_root_intr_methods; 3295 break; 3296 default: 3297 return (USBD_INVAL); 3298 } 3299 } else { 3300 switch (ed->bmAttributes & UE_XFERTYPE) { 3301 case UE_CONTROL: 3302 pipe->methods = &uhci_device_ctrl_methods; 3303 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3304 if (upipe->u.ctl.sqh == NULL) 3305 goto bad; 3306 upipe->u.ctl.setup = uhci_alloc_std(sc); 3307 if (upipe->u.ctl.setup == NULL) { 3308 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3309 goto bad; 3310 } 3311 upipe->u.ctl.stat = uhci_alloc_std(sc); 3312 if (upipe->u.ctl.stat == NULL) { 3313 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3314 uhci_free_std(sc, upipe->u.ctl.setup); 3315 goto bad; 3316 } 3317 err = usb_allocmem(&sc->sc_bus, 3318 sizeof(usb_device_request_t), 3319 0, &upipe->u.ctl.reqdma); 3320 if (err) { 3321 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3322 uhci_free_std(sc, upipe->u.ctl.setup); 3323 uhci_free_std(sc, upipe->u.ctl.stat); 3324 goto bad; 3325 } 3326 break; 3327 case UE_INTERRUPT: 3328 pipe->methods = &uhci_device_intr_methods; 3329 ival = pipe->interval; 3330 if (ival == USBD_DEFAULT_INTERVAL) 3331 ival = ed->bInterval; 3332 return (uhci_device_setintr(sc, upipe, ival)); 3333 case UE_ISOCHRONOUS: 3334 pipe->methods = &uhci_device_isoc_methods; 3335 return (uhci_setup_isoc(pipe)); 3336 case UE_BULK: 3337 pipe->methods = &uhci_device_bulk_methods; 3338 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3339 if (upipe->u.bulk.sqh == NULL) 3340 goto bad; 3341 break; 3342 } 3343 } 3344 return (USBD_NORMAL_COMPLETION); 3345 3346 bad: 3347 return USBD_NOMEM; 3348 } 3349 3350 /* 3351 * Data structures and routines to emulate the root hub. 3352 */ 3353 usb_device_descriptor_t uhci_devd = { 3354 USB_DEVICE_DESCRIPTOR_SIZE, 3355 UDESC_DEVICE, /* type */ 3356 {0x00, 0x01}, /* USB version */ 3357 UDCLASS_HUB, /* class */ 3358 UDSUBCLASS_HUB, /* subclass */ 3359 UDPROTO_FSHUB, /* protocol */ 3360 64, /* max packet */ 3361 {0},{0},{0x00,0x01}, /* device id */ 3362 1,2,0, /* string indicies */ 3363 1 /* # of configurations */ 3364 }; 3365 3366 const usb_config_descriptor_t uhci_confd = { 3367 USB_CONFIG_DESCRIPTOR_SIZE, 3368 UDESC_CONFIG, 3369 {USB_CONFIG_DESCRIPTOR_SIZE + 3370 USB_INTERFACE_DESCRIPTOR_SIZE + 3371 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3372 1, 3373 1, 3374 0, 3375 UC_ATTR_MBO | UC_SELF_POWERED, 3376 0 /* max power */ 3377 }; 3378 3379 const usb_interface_descriptor_t uhci_ifcd = { 3380 USB_INTERFACE_DESCRIPTOR_SIZE, 3381 UDESC_INTERFACE, 3382 0, 3383 0, 3384 1, 3385 UICLASS_HUB, 3386 UISUBCLASS_HUB, 3387 UIPROTO_FSHUB, 3388 0 3389 }; 3390 3391 const usb_endpoint_descriptor_t uhci_endpd = { 3392 USB_ENDPOINT_DESCRIPTOR_SIZE, 3393 UDESC_ENDPOINT, 3394 UE_DIR_IN | UHCI_INTR_ENDPT, 3395 UE_INTERRUPT, 3396 {8}, 3397 255 3398 }; 3399 3400 const usb_hub_descriptor_t uhci_hubd_piix = { 3401 USB_HUB_DESCRIPTOR_SIZE, 3402 UDESC_HUB, 3403 2, 3404 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3405 50, /* power on to power good */ 3406 0, 3407 { 0x00 }, /* both ports are removable */ 3408 { 0 }, 3409 }; 3410 3411 /* 3412 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3413 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3414 * should not be used by the USB subsystem. As we cannot issue a 3415 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3416 * will be enabled as part of the reset. 3417 * 3418 * On the VT83C572, the port cannot be successfully enabled until the 3419 * outstanding "port enable change" and "connection status change" 3420 * events have been reset. 3421 */ 3422 Static usbd_status 3423 uhci_portreset(uhci_softc_t *sc, int index) 3424 { 3425 int lim, port, x; 3426 3427 if (index == 1) 3428 port = UHCI_PORTSC1; 3429 else if (index == 2) 3430 port = UHCI_PORTSC2; 3431 else 3432 return (USBD_IOERROR); 3433 3434 x = URWMASK(UREAD2(sc, port)); 3435 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3436 3437 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3438 3439 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3440 index, UREAD2(sc, port))); 3441 3442 x = URWMASK(UREAD2(sc, port)); 3443 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3444 3445 delay(100); 3446 3447 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3448 index, UREAD2(sc, port))); 3449 3450 x = URWMASK(UREAD2(sc, port)); 3451 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3452 3453 for (lim = 10; --lim > 0;) { 3454 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3455 3456 x = UREAD2(sc, port); 3457 3458 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3459 index, lim, x)); 3460 3461 if (!(x & UHCI_PORTSC_CCS)) { 3462 /* 3463 * No device is connected (or was disconnected 3464 * during reset). Consider the port reset. 3465 * The delay must be long enough to ensure on 3466 * the initial iteration that the device 3467 * connection will have been registered. 50ms 3468 * appears to be sufficient, but 20ms is not. 3469 */ 3470 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3471 index, lim)); 3472 break; 3473 } 3474 3475 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3476 /* 3477 * Port enabled changed and/or connection 3478 * status changed were set. Reset either or 3479 * both raised flags (by writing a 1 to that 3480 * bit), and wait again for state to settle. 3481 */ 3482 UWRITE2(sc, port, URWMASK(x) | 3483 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3484 continue; 3485 } 3486 3487 if (x & UHCI_PORTSC_PE) 3488 /* Port is enabled */ 3489 break; 3490 3491 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3492 } 3493 3494 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3495 index, UREAD2(sc, port))); 3496 3497 if (lim <= 0) { 3498 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3499 return (USBD_TIMEOUT); 3500 } 3501 3502 sc->sc_isreset = 1; 3503 return (USBD_NORMAL_COMPLETION); 3504 } 3505 3506 /* 3507 * Simulate a hardware hub by handling all the necessary requests. 3508 */ 3509 usbd_status 3510 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3511 { 3512 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3513 usbd_status err; 3514 3515 /* Insert last in queue. */ 3516 mutex_enter(&sc->sc_lock); 3517 err = usb_insert_transfer(xfer); 3518 mutex_exit(&sc->sc_lock); 3519 if (err) 3520 return (err); 3521 3522 /* 3523 * Pipe isn't running (otherwise err would be USBD_INPROG), 3524 * so start it first. 3525 */ 3526 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3527 } 3528 3529 usbd_status 3530 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3531 { 3532 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3533 usb_device_request_t *req; 3534 void *buf = NULL; 3535 int port, x; 3536 int len, value, index, status, change, l, totlen = 0; 3537 usb_port_status_t ps; 3538 usbd_status err; 3539 3540 if (sc->sc_dying) 3541 return (USBD_IOERROR); 3542 3543 #ifdef DIAGNOSTIC 3544 if (!(xfer->rqflags & URQ_REQUEST)) 3545 panic("uhci_root_ctrl_start: not a request"); 3546 #endif 3547 req = &xfer->request; 3548 3549 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3550 req->bmRequestType, req->bRequest)); 3551 3552 len = UGETW(req->wLength); 3553 value = UGETW(req->wValue); 3554 index = UGETW(req->wIndex); 3555 3556 if (len != 0) 3557 buf = KERNADDR(&xfer->dmabuf, 0); 3558 3559 #define C(x,y) ((x) | ((y) << 8)) 3560 switch(C(req->bRequest, req->bmRequestType)) { 3561 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3562 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3563 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3564 /* 3565 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3566 * for the integrated root hub. 3567 */ 3568 break; 3569 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3570 if (len > 0) { 3571 *(u_int8_t *)buf = sc->sc_conf; 3572 totlen = 1; 3573 } 3574 break; 3575 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3576 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3577 if (len == 0) 3578 break; 3579 switch(value >> 8) { 3580 case UDESC_DEVICE: 3581 if ((value & 0xff) != 0) { 3582 err = USBD_IOERROR; 3583 goto ret; 3584 } 3585 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3586 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3587 memcpy(buf, &uhci_devd, l); 3588 break; 3589 case UDESC_CONFIG: 3590 if ((value & 0xff) != 0) { 3591 err = USBD_IOERROR; 3592 goto ret; 3593 } 3594 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3595 memcpy(buf, &uhci_confd, l); 3596 buf = (char *)buf + l; 3597 len -= l; 3598 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3599 totlen += l; 3600 memcpy(buf, &uhci_ifcd, l); 3601 buf = (char *)buf + l; 3602 len -= l; 3603 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3604 totlen += l; 3605 memcpy(buf, &uhci_endpd, l); 3606 break; 3607 case UDESC_STRING: 3608 #define sd ((usb_string_descriptor_t *)buf) 3609 switch (value & 0xff) { 3610 case 0: /* Language table */ 3611 totlen = usb_makelangtbl(sd, len); 3612 break; 3613 case 1: /* Vendor */ 3614 totlen = usb_makestrdesc(sd, len, 3615 sc->sc_vendor); 3616 break; 3617 case 2: /* Product */ 3618 totlen = usb_makestrdesc(sd, len, 3619 "UHCI root hub"); 3620 break; 3621 } 3622 #undef sd 3623 break; 3624 default: 3625 err = USBD_IOERROR; 3626 goto ret; 3627 } 3628 break; 3629 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3630 if (len > 0) { 3631 *(u_int8_t *)buf = 0; 3632 totlen = 1; 3633 } 3634 break; 3635 case C(UR_GET_STATUS, UT_READ_DEVICE): 3636 if (len > 1) { 3637 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3638 totlen = 2; 3639 } 3640 break; 3641 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3642 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3643 if (len > 1) { 3644 USETW(((usb_status_t *)buf)->wStatus, 0); 3645 totlen = 2; 3646 } 3647 break; 3648 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3649 if (value >= USB_MAX_DEVICES) { 3650 err = USBD_IOERROR; 3651 goto ret; 3652 } 3653 sc->sc_addr = value; 3654 break; 3655 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3656 if (value != 0 && value != 1) { 3657 err = USBD_IOERROR; 3658 goto ret; 3659 } 3660 sc->sc_conf = value; 3661 break; 3662 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3663 break; 3664 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3665 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3666 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3667 err = USBD_IOERROR; 3668 goto ret; 3669 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3670 break; 3671 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3672 break; 3673 /* Hub requests */ 3674 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3675 break; 3676 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3677 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3678 "port=%d feature=%d\n", 3679 index, value)); 3680 if (index == 1) 3681 port = UHCI_PORTSC1; 3682 else if (index == 2) 3683 port = UHCI_PORTSC2; 3684 else { 3685 err = USBD_IOERROR; 3686 goto ret; 3687 } 3688 switch(value) { 3689 case UHF_PORT_ENABLE: 3690 x = URWMASK(UREAD2(sc, port)); 3691 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3692 break; 3693 case UHF_PORT_SUSPEND: 3694 x = URWMASK(UREAD2(sc, port)); 3695 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3696 break; 3697 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3698 /* see USB2 spec ch. 7.1.7.7 */ 3699 usb_delay_ms(&sc->sc_bus, 20); 3700 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3701 /* 10ms resume delay must be provided by caller */ 3702 break; 3703 case UHF_PORT_RESET: 3704 x = URWMASK(UREAD2(sc, port)); 3705 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3706 break; 3707 case UHF_C_PORT_CONNECTION: 3708 x = URWMASK(UREAD2(sc, port)); 3709 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3710 break; 3711 case UHF_C_PORT_ENABLE: 3712 x = URWMASK(UREAD2(sc, port)); 3713 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3714 break; 3715 case UHF_C_PORT_OVER_CURRENT: 3716 x = URWMASK(UREAD2(sc, port)); 3717 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3718 break; 3719 case UHF_C_PORT_RESET: 3720 sc->sc_isreset = 0; 3721 err = USBD_NORMAL_COMPLETION; 3722 goto ret; 3723 case UHF_PORT_CONNECTION: 3724 case UHF_PORT_OVER_CURRENT: 3725 case UHF_PORT_POWER: 3726 case UHF_PORT_LOW_SPEED: 3727 case UHF_C_PORT_SUSPEND: 3728 default: 3729 err = USBD_IOERROR; 3730 goto ret; 3731 } 3732 break; 3733 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3734 if (index == 1) 3735 port = UHCI_PORTSC1; 3736 else if (index == 2) 3737 port = UHCI_PORTSC2; 3738 else { 3739 err = USBD_IOERROR; 3740 goto ret; 3741 } 3742 if (len > 0) { 3743 *(u_int8_t *)buf = 3744 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3745 UHCI_PORTSC_LS_SHIFT; 3746 totlen = 1; 3747 } 3748 break; 3749 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3750 if (len == 0) 3751 break; 3752 if ((value & 0xff) != 0) { 3753 err = USBD_IOERROR; 3754 goto ret; 3755 } 3756 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3757 totlen = l; 3758 memcpy(buf, &uhci_hubd_piix, l); 3759 break; 3760 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3761 if (len != 4) { 3762 err = USBD_IOERROR; 3763 goto ret; 3764 } 3765 memset(buf, 0, len); 3766 totlen = len; 3767 break; 3768 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3769 if (index == 1) 3770 port = UHCI_PORTSC1; 3771 else if (index == 2) 3772 port = UHCI_PORTSC2; 3773 else { 3774 err = USBD_IOERROR; 3775 goto ret; 3776 } 3777 if (len != 4) { 3778 err = USBD_IOERROR; 3779 goto ret; 3780 } 3781 x = UREAD2(sc, port); 3782 status = change = 0; 3783 if (x & UHCI_PORTSC_CCS) 3784 status |= UPS_CURRENT_CONNECT_STATUS; 3785 if (x & UHCI_PORTSC_CSC) 3786 change |= UPS_C_CONNECT_STATUS; 3787 if (x & UHCI_PORTSC_PE) 3788 status |= UPS_PORT_ENABLED; 3789 if (x & UHCI_PORTSC_POEDC) 3790 change |= UPS_C_PORT_ENABLED; 3791 if (x & UHCI_PORTSC_OCI) 3792 status |= UPS_OVERCURRENT_INDICATOR; 3793 if (x & UHCI_PORTSC_OCIC) 3794 change |= UPS_C_OVERCURRENT_INDICATOR; 3795 if (x & UHCI_PORTSC_SUSP) 3796 status |= UPS_SUSPEND; 3797 if (x & UHCI_PORTSC_LSDA) 3798 status |= UPS_LOW_SPEED; 3799 status |= UPS_PORT_POWER; 3800 if (sc->sc_isreset) 3801 change |= UPS_C_PORT_RESET; 3802 USETW(ps.wPortStatus, status); 3803 USETW(ps.wPortChange, change); 3804 l = min(len, sizeof ps); 3805 memcpy(buf, &ps, l); 3806 totlen = l; 3807 break; 3808 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3809 err = USBD_IOERROR; 3810 goto ret; 3811 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3812 break; 3813 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3814 if (index == 1) 3815 port = UHCI_PORTSC1; 3816 else if (index == 2) 3817 port = UHCI_PORTSC2; 3818 else { 3819 err = USBD_IOERROR; 3820 goto ret; 3821 } 3822 switch(value) { 3823 case UHF_PORT_ENABLE: 3824 x = URWMASK(UREAD2(sc, port)); 3825 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3826 break; 3827 case UHF_PORT_SUSPEND: 3828 x = URWMASK(UREAD2(sc, port)); 3829 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3830 break; 3831 case UHF_PORT_RESET: 3832 err = uhci_portreset(sc, index); 3833 goto ret; 3834 case UHF_PORT_POWER: 3835 /* Pretend we turned on power */ 3836 err = USBD_NORMAL_COMPLETION; 3837 goto ret; 3838 case UHF_C_PORT_CONNECTION: 3839 case UHF_C_PORT_ENABLE: 3840 case UHF_C_PORT_OVER_CURRENT: 3841 case UHF_PORT_CONNECTION: 3842 case UHF_PORT_OVER_CURRENT: 3843 case UHF_PORT_LOW_SPEED: 3844 case UHF_C_PORT_SUSPEND: 3845 case UHF_C_PORT_RESET: 3846 default: 3847 err = USBD_IOERROR; 3848 goto ret; 3849 } 3850 break; 3851 default: 3852 err = USBD_IOERROR; 3853 goto ret; 3854 } 3855 xfer->actlen = totlen; 3856 err = USBD_NORMAL_COMPLETION; 3857 ret: 3858 xfer->status = err; 3859 mutex_enter(&sc->sc_lock); 3860 usb_transfer_complete(xfer); 3861 mutex_exit(&sc->sc_lock); 3862 return (USBD_IN_PROGRESS); 3863 } 3864 3865 /* Abort a root control request. */ 3866 void 3867 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3868 { 3869 /* Nothing to do, all transfers are synchronous. */ 3870 } 3871 3872 /* Close the root pipe. */ 3873 void 3874 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3875 { 3876 DPRINTF(("uhci_root_ctrl_close\n")); 3877 } 3878 3879 /* Abort a root interrupt request. */ 3880 void 3881 uhci_root_intr_abort(usbd_xfer_handle xfer) 3882 { 3883 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3884 3885 KASSERT(mutex_owned(&sc->sc_lock)); 3886 3887 callout_stop(&sc->sc_poll_handle); 3888 sc->sc_intr_xfer = NULL; 3889 3890 if (xfer->pipe->intrxfer == xfer) { 3891 DPRINTF(("uhci_root_intr_abort: remove\n")); 3892 xfer->pipe->intrxfer = 0; 3893 } 3894 xfer->status = USBD_CANCELLED; 3895 #ifdef DIAGNOSTIC 3896 UXFER(xfer)->iinfo.isdone = 1; 3897 #endif 3898 usb_transfer_complete(xfer); 3899 } 3900 3901 usbd_status 3902 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3903 { 3904 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3905 usbd_status err; 3906 3907 /* Insert last in queue. */ 3908 mutex_enter(&sc->sc_lock); 3909 err = usb_insert_transfer(xfer); 3910 mutex_exit(&sc->sc_lock); 3911 if (err) 3912 return (err); 3913 3914 /* 3915 * Pipe isn't running (otherwise err would be USBD_INPROG), 3916 * start first 3917 */ 3918 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3919 } 3920 3921 /* Start a transfer on the root interrupt pipe */ 3922 usbd_status 3923 uhci_root_intr_start(usbd_xfer_handle xfer) 3924 { 3925 usbd_pipe_handle pipe = xfer->pipe; 3926 uhci_softc_t *sc = pipe->device->bus->hci_private; 3927 unsigned int ival; 3928 3929 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3930 xfer, xfer->length, xfer->flags)); 3931 3932 if (sc->sc_dying) 3933 return (USBD_IOERROR); 3934 3935 /* XXX temporary variable needed to avoid gcc3 warning */ 3936 ival = xfer->pipe->endpoint->edesc->bInterval; 3937 sc->sc_ival = mstohz(ival); 3938 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3939 sc->sc_intr_xfer = xfer; 3940 return (USBD_IN_PROGRESS); 3941 } 3942 3943 /* Close the root interrupt pipe. */ 3944 void 3945 uhci_root_intr_close(usbd_pipe_handle pipe) 3946 { 3947 uhci_softc_t *sc = pipe->device->bus->hci_private; 3948 3949 KASSERT(mutex_owned(&sc->sc_lock)); 3950 3951 callout_stop(&sc->sc_poll_handle); 3952 sc->sc_intr_xfer = NULL; 3953 DPRINTF(("uhci_root_intr_close\n")); 3954 } 3955
Indexes created Tue Sep 30 17:09:57 GMT 2025