uhci.c revision 1.264
1 /* $NetBSD: uhci.c,v 1.264 2014/08/05 06:35:24 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264 2014/08/05 06:35:24 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run, int locked); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, u_int16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 169 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 170 171 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 172 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 173 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 #ifdef UHCI_DEBUG 267 static __inline uint32_t 268 UREAD4(uhci_softc_t *sc, bus_size_t r) 269 { 270 271 UBARR(sc); 272 return bus_space_read_4(sc->iot, sc->ioh, r); 273 } 274 #endif 275 276 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 277 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 278 279 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 280 281 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 282 283 #define UHCI_INTR_ENDPT 1 284 285 const struct usbd_bus_methods uhci_bus_methods = { 286 .open_pipe = uhci_open, 287 .soft_intr = uhci_softintr, 288 .do_poll = uhci_poll, 289 .allocm = uhci_allocm, 290 .freem = uhci_freem, 291 .allocx = uhci_allocx, 292 .freex = uhci_freex, 293 .get_lock = uhci_get_lock, 294 .new_device = NULL, 295 }; 296 297 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 298 .transfer = uhci_root_ctrl_transfer, 299 .start = uhci_root_ctrl_start, 300 .abort = uhci_root_ctrl_abort, 301 .close = uhci_root_ctrl_close, 302 .cleartoggle = uhci_noop, 303 .done = uhci_root_ctrl_done, 304 }; 305 306 const struct usbd_pipe_methods uhci_root_intr_methods = { 307 .transfer = uhci_root_intr_transfer, 308 .start = uhci_root_intr_start, 309 .abort = uhci_root_intr_abort, 310 .close = uhci_root_intr_close, 311 .cleartoggle = uhci_noop, 312 .done = uhci_root_intr_done, 313 }; 314 315 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 316 .transfer = uhci_device_ctrl_transfer, 317 .start = uhci_device_ctrl_start, 318 .abort = uhci_device_ctrl_abort, 319 .close = uhci_device_ctrl_close, 320 .cleartoggle = uhci_noop, 321 .done = uhci_device_ctrl_done, 322 }; 323 324 const struct usbd_pipe_methods uhci_device_intr_methods = { 325 .transfer = uhci_device_intr_transfer, 326 .start = uhci_device_intr_start, 327 .abort = uhci_device_intr_abort, 328 .close = uhci_device_intr_close, 329 .cleartoggle = uhci_device_clear_toggle, 330 .done = uhci_device_intr_done, 331 }; 332 333 const struct usbd_pipe_methods uhci_device_bulk_methods = { 334 .transfer = uhci_device_bulk_transfer, 335 .start = uhci_device_bulk_start, 336 .abort = uhci_device_bulk_abort, 337 .close = uhci_device_bulk_close, 338 .cleartoggle = uhci_device_clear_toggle, 339 .done = uhci_device_bulk_done, 340 }; 341 342 const struct usbd_pipe_methods uhci_device_isoc_methods = { 343 .transfer = uhci_device_isoc_transfer, 344 .start = uhci_device_isoc_start, 345 .abort = uhci_device_isoc_abort, 346 .close = uhci_device_isoc_close, 347 .cleartoggle = uhci_noop, 348 .done = uhci_device_isoc_done, 349 }; 350 351 #define uhci_add_intr_info(sc, ii) \ 352 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 353 #define uhci_del_intr_info(ii) \ 354 do { \ 355 LIST_REMOVE((ii), list); \ 356 (ii)->list.le_prev = NULL; \ 357 } while (0) 358 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 359 360 static inline uhci_soft_qh_t * 361 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 362 { 363 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 364 365 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 366 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 367 usb_syncmem(&pqh->dma, 368 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 369 sizeof(pqh->qh.qh_hlink), 370 BUS_DMASYNC_POSTWRITE); 371 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 372 printf("uhci_find_prev_qh: QH not found\n"); 373 return (NULL); 374 } 375 #endif 376 } 377 return (pqh); 378 } 379 380 void 381 uhci_globalreset(uhci_softc_t *sc) 382 { 383 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 384 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 385 UHCICMD(sc, 0); /* do nothing */ 386 } 387 388 usbd_status 389 uhci_init(uhci_softc_t *sc) 390 { 391 usbd_status err; 392 int i, j; 393 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 394 uhci_soft_td_t *std; 395 396 DPRINTFN(1,("uhci_init: start\n")); 397 398 #ifdef UHCI_DEBUG 399 thesc = sc; 400 401 if (uhcidebug > 2) 402 uhci_dumpregs(sc); 403 #endif 404 405 sc->sc_suspend = PWR_RESUME; 406 407 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 408 uhci_globalreset(sc); /* reset the controller */ 409 uhci_reset(sc); 410 411 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 412 USB_MEM_RESERVE); 413 414 /* Allocate and initialize real frame array. */ 415 err = usb_allocmem(&sc->sc_bus, 416 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 417 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 418 if (err) 419 return (err); 420 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 421 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 422 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 423 424 /* 425 * Allocate a TD, inactive, that hangs from the last QH. 426 * This is to avoid a bug in the PIIX that makes it run berserk 427 * otherwise. 428 */ 429 std = uhci_alloc_std(sc); 430 if (std == NULL) 431 return (USBD_NOMEM); 432 std->link.std = NULL; 433 std->td.td_link = htole32(UHCI_PTR_T); 434 std->td.td_status = htole32(0); /* inactive */ 435 std->td.td_token = htole32(0); 436 std->td.td_buffer = htole32(0); 437 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 438 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 439 440 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 441 lsqh = uhci_alloc_sqh(sc); 442 if (lsqh == NULL) 443 return (USBD_NOMEM); 444 lsqh->hlink = NULL; 445 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 446 lsqh->elink = std; 447 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 448 sc->sc_last_qh = lsqh; 449 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 451 452 /* Allocate the dummy QH where bulk traffic will be queued. */ 453 bsqh = uhci_alloc_sqh(sc); 454 if (bsqh == NULL) 455 return (USBD_NOMEM); 456 bsqh->hlink = lsqh; 457 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 458 bsqh->elink = NULL; 459 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 460 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 461 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 463 464 /* Allocate dummy QH where high speed control traffic will be queued. */ 465 chsqh = uhci_alloc_sqh(sc); 466 if (chsqh == NULL) 467 return (USBD_NOMEM); 468 chsqh->hlink = bsqh; 469 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 470 chsqh->elink = NULL; 471 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 472 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 473 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 475 476 /* Allocate dummy QH where control traffic will be queued. */ 477 clsqh = uhci_alloc_sqh(sc); 478 if (clsqh == NULL) 479 return (USBD_NOMEM); 480 clsqh->hlink = chsqh; 481 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 482 clsqh->elink = NULL; 483 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 484 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 485 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 487 488 /* 489 * Make all (virtual) frame list pointers point to the interrupt 490 * queue heads and the interrupt queue heads at the control 491 * queue head and point the physical frame list to the virtual. 492 */ 493 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 494 std = uhci_alloc_std(sc); 495 sqh = uhci_alloc_sqh(sc); 496 if (std == NULL || sqh == NULL) 497 return (USBD_NOMEM); 498 std->link.sqh = sqh; 499 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 500 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 501 std->td.td_token = htole32(0); 502 std->td.td_buffer = htole32(0); 503 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 504 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 505 sqh->hlink = clsqh; 506 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 507 sqh->elink = NULL; 508 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 509 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 511 sc->sc_vframes[i].htd = std; 512 sc->sc_vframes[i].etd = std; 513 sc->sc_vframes[i].hqh = sqh; 514 sc->sc_vframes[i].eqh = sqh; 515 for (j = i; 516 j < UHCI_FRAMELIST_COUNT; 517 j += UHCI_VFRAMELIST_COUNT) 518 sc->sc_pframes[j] = htole32(std->physaddr); 519 } 520 usb_syncmem(&sc->sc_dma, 0, 521 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 522 BUS_DMASYNC_PREWRITE); 523 524 525 LIST_INIT(&sc->sc_intrhead); 526 527 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 528 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 529 530 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 531 532 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 533 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 534 cv_init(&sc->sc_softwake_cv, "uhciab"); 535 536 /* Set up the bus struct. */ 537 sc->sc_bus.methods = &uhci_bus_methods; 538 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 539 540 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 541 542 DPRINTFN(1,("uhci_init: enabling\n")); 543 544 err = uhci_run(sc, 1, 0); /* and here we go... */ 545 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 546 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 547 return err; 548 } 549 550 int 551 uhci_activate(device_t self, enum devact act) 552 { 553 struct uhci_softc *sc = device_private(self); 554 555 switch (act) { 556 case DVACT_DEACTIVATE: 557 sc->sc_dying = 1; 558 return 0; 559 default: 560 return EOPNOTSUPP; 561 } 562 } 563 564 void 565 uhci_childdet(device_t self, device_t child) 566 { 567 struct uhci_softc *sc = device_private(self); 568 569 KASSERT(sc->sc_child == child); 570 sc->sc_child = NULL; 571 } 572 573 int 574 uhci_detach(struct uhci_softc *sc, int flags) 575 { 576 int rv = 0; 577 578 if (sc->sc_child != NULL) 579 rv = config_detach(sc->sc_child, flags); 580 581 if (rv != 0) 582 return (rv); 583 584 callout_halt(&sc->sc_poll_handle, NULL); 585 callout_destroy(&sc->sc_poll_handle); 586 587 cv_destroy(&sc->sc_softwake_cv); 588 589 mutex_destroy(&sc->sc_lock); 590 mutex_destroy(&sc->sc_intr_lock); 591 592 pool_cache_destroy(sc->sc_xferpool); 593 594 /* XXX free other data structures XXX */ 595 596 return (rv); 597 } 598 599 usbd_status 600 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 601 { 602 struct uhci_softc *sc = bus->hci_private; 603 usbd_status status; 604 u_int32_t n; 605 606 /* 607 * XXX 608 * Since we are allocating a buffer we can assume that we will 609 * need TDs for it. Since we don't want to allocate those from 610 * an interrupt context, we allocate them here and free them again. 611 * This is no guarantee that we'll get the TDs next time... 612 */ 613 n = size / 8; 614 if (n > 16) { 615 u_int32_t i; 616 uhci_soft_td_t **stds; 617 618 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 619 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 620 if (!stds) 621 return USBD_NOMEM; 622 for(i = 0; i < n; i++) 623 stds[i] = uhci_alloc_std(sc); 624 for(i = 0; i < n; i++) 625 if (stds[i] != NULL) 626 uhci_free_std(sc, stds[i]); 627 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 628 } 629 630 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 631 if (status == USBD_NOMEM) 632 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 633 return status; 634 } 635 636 void 637 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 638 { 639 if (dma->block->flags & USB_DMA_RESERVE) { 640 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 641 dma); 642 return; 643 } 644 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 645 } 646 647 usbd_xfer_handle 648 uhci_allocx(struct usbd_bus *bus) 649 { 650 struct uhci_softc *sc = bus->hci_private; 651 usbd_xfer_handle xfer; 652 653 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 654 if (xfer != NULL) { 655 memset(xfer, 0, sizeof(struct uhci_xfer)); 656 UXFER(xfer)->iinfo.sc = sc; 657 #ifdef DIAGNOSTIC 658 UXFER(xfer)->iinfo.isdone = 1; 659 xfer->busy_free = XFER_BUSY; 660 #endif 661 } 662 return (xfer); 663 } 664 665 void 666 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 667 { 668 struct uhci_softc *sc = bus->hci_private; 669 670 #ifdef DIAGNOSTIC 671 if (xfer->busy_free != XFER_BUSY) { 672 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 673 xfer->busy_free); 674 } 675 xfer->busy_free = XFER_FREE; 676 if (!UXFER(xfer)->iinfo.isdone) { 677 printf("uhci_freex: !isdone\n"); 678 } 679 #endif 680 pool_cache_put(sc->sc_xferpool, xfer); 681 } 682 683 Static void 684 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 685 { 686 struct uhci_softc *sc = bus->hci_private; 687 688 *lock = &sc->sc_lock; 689 } 690 691 692 /* 693 * Handle suspend/resume. 694 * 695 * We need to switch to polling mode here, because this routine is 696 * called from an interrupt context. This is all right since we 697 * are almost suspended anyway. 698 */ 699 bool 700 uhci_resume(device_t dv, const pmf_qual_t *qual) 701 { 702 uhci_softc_t *sc = device_private(dv); 703 int cmd; 704 705 mutex_spin_enter(&sc->sc_intr_lock); 706 707 cmd = UREAD2(sc, UHCI_CMD); 708 sc->sc_bus.use_polling++; 709 UWRITE2(sc, UHCI_INTR, 0); 710 uhci_globalreset(sc); 711 uhci_reset(sc); 712 if (cmd & UHCI_CMD_RS) 713 uhci_run(sc, 0, 1); 714 715 /* restore saved state */ 716 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 717 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 718 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 719 720 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 721 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 722 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 723 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 724 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 725 UHCICMD(sc, UHCI_CMD_MAXP); 726 uhci_run(sc, 1, 1); /* and start traffic again */ 727 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 728 sc->sc_bus.use_polling--; 729 if (sc->sc_intr_xfer != NULL) 730 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 731 sc->sc_intr_xfer); 732 #ifdef UHCI_DEBUG 733 if (uhcidebug > 2) 734 uhci_dumpregs(sc); 735 #endif 736 737 sc->sc_suspend = PWR_RESUME; 738 mutex_spin_exit(&sc->sc_intr_lock); 739 740 return true; 741 } 742 743 bool 744 uhci_suspend(device_t dv, const pmf_qual_t *qual) 745 { 746 uhci_softc_t *sc = device_private(dv); 747 int cmd; 748 749 mutex_spin_enter(&sc->sc_intr_lock); 750 751 cmd = UREAD2(sc, UHCI_CMD); 752 753 #ifdef UHCI_DEBUG 754 if (uhcidebug > 2) 755 uhci_dumpregs(sc); 756 #endif 757 if (sc->sc_intr_xfer != NULL) 758 callout_stop(&sc->sc_poll_handle); 759 sc->sc_suspend = PWR_SUSPEND; 760 sc->sc_bus.use_polling++; 761 762 uhci_run(sc, 0, 1); /* stop the controller */ 763 cmd &= ~UHCI_CMD_RS; 764 765 /* save some state if BIOS doesn't */ 766 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 767 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 768 769 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 770 771 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 772 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 773 sc->sc_bus.use_polling--; 774 775 mutex_spin_exit(&sc->sc_intr_lock); 776 777 return true; 778 } 779 780 #ifdef UHCI_DEBUG 781 Static void 782 uhci_dumpregs(uhci_softc_t *sc) 783 { 784 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 785 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 786 device_xname(sc->sc_dev), 787 UREAD2(sc, UHCI_CMD), 788 UREAD2(sc, UHCI_STS), 789 UREAD2(sc, UHCI_INTR), 790 UREAD2(sc, UHCI_FRNUM), 791 UREAD4(sc, UHCI_FLBASEADDR), 792 UREAD1(sc, UHCI_SOF), 793 UREAD2(sc, UHCI_PORTSC1), 794 UREAD2(sc, UHCI_PORTSC2))); 795 } 796 797 void 798 uhci_dump_td(uhci_soft_td_t *p) 799 { 800 char sbuf[128], sbuf2[128]; 801 802 803 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 805 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 806 "token=0x%08lx buffer=0x%08lx\n", 807 p, (long)p->physaddr, 808 (long)le32toh(p->td.td_link), 809 (long)le32toh(p->td.td_status), 810 (long)le32toh(p->td.td_token), 811 (long)le32toh(p->td.td_buffer))); 812 813 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 814 (u_int32_t)le32toh(p->td.td_link)); 815 snprintb(sbuf2, sizeof(sbuf2), 816 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 817 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 818 (u_int32_t)le32toh(p->td.td_status)); 819 820 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 821 "D=%d,maxlen=%d\n", sbuf, sbuf2, 822 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 823 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 824 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 825 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 826 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 827 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 828 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 829 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 830 BUS_DMASYNC_PREREAD); 831 } 832 833 void 834 uhci_dump_qh(uhci_soft_qh_t *sqh) 835 { 836 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 837 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 838 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 839 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 840 le32toh(sqh->qh.qh_elink))); 841 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 842 } 843 844 845 #if 1 846 void 847 uhci_dump(void) 848 { 849 uhci_dump_all(thesc); 850 } 851 #endif 852 853 void 854 uhci_dump_all(uhci_softc_t *sc) 855 { 856 uhci_dumpregs(sc); 857 printf("intrs=%d\n", sc->sc_bus.no_intrs); 858 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 859 uhci_dump_qhs(sc->sc_lctl_start); 860 } 861 862 863 void 864 uhci_dump_qhs(uhci_soft_qh_t *sqh) 865 { 866 uhci_dump_qh(sqh); 867 868 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 869 * Traverses sideways first, then down. 870 * 871 * QH1 872 * QH2 873 * No QH 874 * TD2.1 875 * TD2.2 876 * TD1.1 877 * etc. 878 * 879 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 880 */ 881 882 883 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 884 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 885 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 886 uhci_dump_qhs(sqh->hlink); 887 else 888 DPRINTF(("No QH\n")); 889 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 890 891 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 892 uhci_dump_tds(sqh->elink); 893 else 894 DPRINTF(("No TD\n")); 895 } 896 897 void 898 uhci_dump_tds(uhci_soft_td_t *std) 899 { 900 uhci_soft_td_t *td; 901 int stop; 902 903 for(td = std; td != NULL; td = td->link.std) { 904 uhci_dump_td(td); 905 906 /* Check whether the link pointer in this TD marks 907 * the link pointer as end of queue. This avoids 908 * printing the free list in case the queue/TD has 909 * already been moved there (seatbelt). 910 */ 911 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 912 sizeof(td->td.td_link), 913 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 914 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 915 le32toh(td->td.td_link) == 0); 916 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 917 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 918 if (stop) 919 break; 920 } 921 } 922 923 Static void 924 uhci_dump_ii(uhci_intr_info_t *ii) 925 { 926 usbd_pipe_handle pipe; 927 usb_endpoint_descriptor_t *ed; 928 usbd_device_handle dev; 929 930 #ifdef DIAGNOSTIC 931 #define DONE ii->isdone 932 #else 933 #define DONE 0 934 #endif 935 if (ii == NULL) { 936 printf("ii NULL\n"); 937 return; 938 } 939 if (ii->xfer == NULL) { 940 printf("ii %p: done=%d xfer=NULL\n", 941 ii, DONE); 942 return; 943 } 944 pipe = ii->xfer->pipe; 945 if (pipe == NULL) { 946 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 947 ii, DONE, ii->xfer); 948 return; 949 } 950 if (pipe->endpoint == NULL) { 951 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 952 ii, DONE, ii->xfer, pipe); 953 return; 954 } 955 if (pipe->device == NULL) { 956 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 957 ii, DONE, ii->xfer, pipe); 958 return; 959 } 960 ed = pipe->endpoint->edesc; 961 dev = pipe->device; 962 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 963 ii, DONE, ii->xfer, dev, 964 UGETW(dev->ddesc.idVendor), 965 UGETW(dev->ddesc.idProduct), 966 dev->address, pipe, 967 ed->bEndpointAddress, ed->bmAttributes); 968 #undef DONE 969 } 970 971 void uhci_dump_iis(struct uhci_softc *sc); 972 void 973 uhci_dump_iis(struct uhci_softc *sc) 974 { 975 uhci_intr_info_t *ii; 976 977 printf("intr_info list:\n"); 978 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 979 uhci_dump_ii(ii); 980 } 981 982 void iidump(void); 983 void iidump(void) { uhci_dump_iis(thesc); } 984 985 #endif 986 987 /* 988 * This routine is executed periodically and simulates interrupts 989 * from the root controller interrupt pipe for port status change. 990 */ 991 void 992 uhci_poll_hub(void *addr) 993 { 994 usbd_xfer_handle xfer = addr; 995 usbd_pipe_handle pipe = xfer->pipe; 996 uhci_softc_t *sc; 997 u_char *p; 998 999 DPRINTFN(20, ("uhci_poll_hub\n")); 1000 1001 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1002 return; /* device has detached */ 1003 sc = pipe->device->bus->hci_private; 1004 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1005 1006 p = KERNADDR(&xfer->dmabuf, 0); 1007 p[0] = 0; 1008 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<1; 1010 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1011 p[0] |= 1<<2; 1012 if (p[0] == 0) 1013 /* No change, try again in a while */ 1014 return; 1015 1016 xfer->actlen = 1; 1017 xfer->status = USBD_NORMAL_COMPLETION; 1018 mutex_enter(&sc->sc_lock); 1019 usb_transfer_complete(xfer); 1020 mutex_exit(&sc->sc_lock); 1021 } 1022 1023 void 1024 uhci_root_intr_done(usbd_xfer_handle xfer) 1025 { 1026 } 1027 1028 void 1029 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1030 { 1031 } 1032 1033 /* 1034 * Let the last QH loop back to the high speed control transfer QH. 1035 * This is what intel calls "bandwidth reclamation" and improves 1036 * USB performance a lot for some devices. 1037 * If we are already looping, just count it. 1038 */ 1039 void 1040 uhci_add_loop(uhci_softc_t *sc) { 1041 #ifdef UHCI_DEBUG 1042 if (uhcinoloop) 1043 return; 1044 #endif 1045 if (++sc->sc_loops == 1) { 1046 DPRINTFN(5,("uhci_start_loop: add\n")); 1047 /* Note, we don't loop back the soft pointer. */ 1048 sc->sc_last_qh->qh.qh_hlink = 1049 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1050 usb_syncmem(&sc->sc_last_qh->dma, 1051 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1052 sizeof(sc->sc_last_qh->qh.qh_hlink), 1053 BUS_DMASYNC_PREWRITE); 1054 } 1055 } 1056 1057 void 1058 uhci_rem_loop(uhci_softc_t *sc) { 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (--sc->sc_loops == 0) { 1064 DPRINTFN(5,("uhci_end_loop: remove\n")); 1065 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1066 usb_syncmem(&sc->sc_last_qh->dma, 1067 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1068 sizeof(sc->sc_last_qh->qh.qh_hlink), 1069 BUS_DMASYNC_PREWRITE); 1070 } 1071 } 1072 1073 /* Add high speed control QH, called with lock held. */ 1074 void 1075 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1076 { 1077 uhci_soft_qh_t *eqh; 1078 1079 KASSERT(mutex_owned(&sc->sc_lock)); 1080 1081 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1082 eqh = sc->sc_hctl_end; 1083 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1084 sizeof(eqh->qh.qh_hlink), 1085 BUS_DMASYNC_POSTWRITE); 1086 sqh->hlink = eqh->hlink; 1087 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1088 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1089 BUS_DMASYNC_PREWRITE); 1090 eqh->hlink = sqh; 1091 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1092 sc->sc_hctl_end = sqh; 1093 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1094 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1095 #ifdef UHCI_CTL_LOOP 1096 uhci_add_loop(sc); 1097 #endif 1098 } 1099 1100 /* Remove high speed control QH, called with lock held. */ 1101 void 1102 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1103 { 1104 uhci_soft_qh_t *pqh; 1105 uint32_t elink; 1106 1107 KASSERT(mutex_owned(&sc->sc_lock)); 1108 1109 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1110 #ifdef UHCI_CTL_LOOP 1111 uhci_rem_loop(sc); 1112 #endif 1113 /* 1114 * The T bit should be set in the elink of the QH so that the HC 1115 * doesn't follow the pointer. This condition may fail if the 1116 * the transferred packet was short so that the QH still points 1117 * at the last used TD. 1118 * In this case we set the T bit and wait a little for the HC 1119 * to stop looking at the TD. 1120 * Note that if the TD chain is large enough, the controller 1121 * may still be looking at the chain at the end of this function. 1122 * uhci_free_std_chain() will make sure the controller stops 1123 * looking at it quickly, but until then we should not change 1124 * sqh->hlink. 1125 */ 1126 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1127 sizeof(sqh->qh.qh_elink), 1128 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1129 elink = le32toh(sqh->qh.qh_elink); 1130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1131 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1132 if (!(elink & UHCI_PTR_T)) { 1133 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1134 usb_syncmem(&sqh->dma, 1135 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1136 sizeof(sqh->qh.qh_elink), 1137 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1138 delay(UHCI_QH_REMOVE_DELAY); 1139 } 1140 1141 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1142 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1143 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1144 pqh->hlink = sqh->hlink; 1145 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1146 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1147 sizeof(pqh->qh.qh_hlink), 1148 BUS_DMASYNC_PREWRITE); 1149 delay(UHCI_QH_REMOVE_DELAY); 1150 if (sc->sc_hctl_end == sqh) 1151 sc->sc_hctl_end = pqh; 1152 } 1153 1154 /* Add low speed control QH, called with lock held. */ 1155 void 1156 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1157 { 1158 uhci_soft_qh_t *eqh; 1159 1160 KASSERT(mutex_owned(&sc->sc_lock)); 1161 1162 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1163 eqh = sc->sc_lctl_end; 1164 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1165 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1166 sqh->hlink = eqh->hlink; 1167 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1168 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1169 BUS_DMASYNC_PREWRITE); 1170 eqh->hlink = sqh; 1171 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1172 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1173 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1174 sc->sc_lctl_end = sqh; 1175 } 1176 1177 /* Remove low speed control QH, called with lock held. */ 1178 void 1179 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1180 { 1181 uhci_soft_qh_t *pqh; 1182 uint32_t elink; 1183 1184 KASSERT(mutex_owned(&sc->sc_lock)); 1185 1186 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1187 /* See comment in uhci_remove_hs_ctrl() */ 1188 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1189 sizeof(sqh->qh.qh_elink), 1190 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1191 elink = le32toh(sqh->qh.qh_elink); 1192 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1193 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1194 if (!(elink & UHCI_PTR_T)) { 1195 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1196 usb_syncmem(&sqh->dma, 1197 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1198 sizeof(sqh->qh.qh_elink), 1199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1200 delay(UHCI_QH_REMOVE_DELAY); 1201 } 1202 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1203 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1204 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1205 pqh->hlink = sqh->hlink; 1206 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1207 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1208 sizeof(pqh->qh.qh_hlink), 1209 BUS_DMASYNC_PREWRITE); 1210 delay(UHCI_QH_REMOVE_DELAY); 1211 if (sc->sc_lctl_end == sqh) 1212 sc->sc_lctl_end = pqh; 1213 } 1214 1215 /* Add bulk QH, called with lock held. */ 1216 void 1217 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1218 { 1219 uhci_soft_qh_t *eqh; 1220 1221 KASSERT(mutex_owned(&sc->sc_lock)); 1222 1223 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1224 eqh = sc->sc_bulk_end; 1225 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1226 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1227 sqh->hlink = eqh->hlink; 1228 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1229 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1230 BUS_DMASYNC_PREWRITE); 1231 eqh->hlink = sqh; 1232 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1233 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1234 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1235 sc->sc_bulk_end = sqh; 1236 uhci_add_loop(sc); 1237 } 1238 1239 /* Remove bulk QH, called with lock held. */ 1240 void 1241 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1242 { 1243 uhci_soft_qh_t *pqh; 1244 1245 KASSERT(mutex_owned(&sc->sc_lock)); 1246 1247 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1248 uhci_rem_loop(sc); 1249 /* See comment in uhci_remove_hs_ctrl() */ 1250 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1251 sizeof(sqh->qh.qh_elink), 1252 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1253 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1254 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1255 usb_syncmem(&sqh->dma, 1256 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1257 sizeof(sqh->qh.qh_elink), 1258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1259 delay(UHCI_QH_REMOVE_DELAY); 1260 } 1261 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1262 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1263 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1264 pqh->hlink = sqh->hlink; 1265 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1266 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1267 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1268 delay(UHCI_QH_REMOVE_DELAY); 1269 if (sc->sc_bulk_end == sqh) 1270 sc->sc_bulk_end = pqh; 1271 } 1272 1273 Static int uhci_intr1(uhci_softc_t *); 1274 1275 int 1276 uhci_intr(void *arg) 1277 { 1278 uhci_softc_t *sc = arg; 1279 int ret = 0; 1280 1281 mutex_spin_enter(&sc->sc_intr_lock); 1282 1283 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1284 goto done; 1285 1286 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1287 #ifdef DIAGNOSTIC 1288 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1289 #endif 1290 goto done; 1291 } 1292 1293 ret = uhci_intr1(sc); 1294 1295 done: 1296 mutex_spin_exit(&sc->sc_intr_lock); 1297 return ret; 1298 } 1299 1300 int 1301 uhci_intr1(uhci_softc_t *sc) 1302 { 1303 int status; 1304 int ack; 1305 1306 #ifdef UHCI_DEBUG 1307 if (uhcidebug > 15) { 1308 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1309 uhci_dumpregs(sc); 1310 } 1311 #endif 1312 1313 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1314 1315 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1316 if (status == 0) /* The interrupt was not for us. */ 1317 return (0); 1318 1319 if (sc->sc_suspend != PWR_RESUME) { 1320 #ifdef DIAGNOSTIC 1321 printf("%s: interrupt while not operating ignored\n", 1322 device_xname(sc->sc_dev)); 1323 #endif 1324 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1325 return (0); 1326 } 1327 1328 ack = 0; 1329 if (status & UHCI_STS_USBINT) 1330 ack |= UHCI_STS_USBINT; 1331 if (status & UHCI_STS_USBEI) 1332 ack |= UHCI_STS_USBEI; 1333 if (status & UHCI_STS_RD) { 1334 ack |= UHCI_STS_RD; 1335 #ifdef UHCI_DEBUG 1336 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1337 #endif 1338 } 1339 if (status & UHCI_STS_HSE) { 1340 ack |= UHCI_STS_HSE; 1341 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1342 } 1343 if (status & UHCI_STS_HCPE) { 1344 ack |= UHCI_STS_HCPE; 1345 printf("%s: host controller process error\n", 1346 device_xname(sc->sc_dev)); 1347 } 1348 1349 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1350 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1351 /* no acknowledge needed */ 1352 if (!sc->sc_dying) { 1353 printf("%s: host controller halted\n", 1354 device_xname(sc->sc_dev)); 1355 #ifdef UHCI_DEBUG 1356 uhci_dump_all(sc); 1357 #endif 1358 } 1359 sc->sc_dying = 1; 1360 } 1361 1362 if (!ack) 1363 return (0); /* nothing to acknowledge */ 1364 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1365 1366 sc->sc_bus.no_intrs++; 1367 usb_schedsoftintr(&sc->sc_bus); 1368 1369 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1370 1371 return (1); 1372 } 1373 1374 void 1375 uhci_softintr(void *v) 1376 { 1377 struct usbd_bus *bus = v; 1378 uhci_softc_t *sc = bus->hci_private; 1379 uhci_intr_info_t *ii, *nextii; 1380 1381 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1382 1383 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1384 1385 /* 1386 * Interrupts on UHCI really suck. When the host controller 1387 * interrupts because a transfer is completed there is no 1388 * way of knowing which transfer it was. You can scan down 1389 * the TDs and QHs of the previous frame to limit the search, 1390 * but that assumes that the interrupt was not delayed by more 1391 * than 1 ms, which may not always be true (e.g. after debug 1392 * output on a slow console). 1393 * We scan all interrupt descriptors to see if any have 1394 * completed. 1395 */ 1396 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1397 nextii = LIST_NEXT(ii, list); 1398 uhci_check_intr(sc, ii); 1399 } 1400 1401 if (sc->sc_softwake) { 1402 sc->sc_softwake = 0; 1403 cv_broadcast(&sc->sc_softwake_cv); 1404 } 1405 } 1406 1407 /* Check for an interrupt. */ 1408 void 1409 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1410 { 1411 uhci_soft_td_t *std, *lstd; 1412 u_int32_t status; 1413 1414 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1415 #ifdef DIAGNOSTIC 1416 if (ii == NULL) { 1417 printf("uhci_check_intr: no ii? %p\n", ii); 1418 return; 1419 } 1420 #endif 1421 if (ii->xfer->status == USBD_CANCELLED || 1422 ii->xfer->status == USBD_TIMEOUT) { 1423 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1424 return; 1425 } 1426 1427 if (ii->stdstart == NULL) 1428 return; 1429 lstd = ii->stdend; 1430 #ifdef DIAGNOSTIC 1431 if (lstd == NULL) { 1432 printf("uhci_check_intr: std==0\n"); 1433 return; 1434 } 1435 #endif 1436 usb_syncmem(&lstd->dma, 1437 lstd->offs + offsetof(uhci_td_t, td_status), 1438 sizeof(lstd->td.td_status), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 status = le32toh(lstd->td.td_status); 1441 usb_syncmem(&lstd->dma, 1442 lstd->offs + offsetof(uhci_td_t, td_status), 1443 sizeof(lstd->td.td_status), 1444 BUS_DMASYNC_PREREAD); 1445 1446 /* If the last TD is not marked active we can complete */ 1447 if (!(status & UHCI_TD_ACTIVE)) { 1448 done: 1449 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1450 callout_stop(&ii->xfer->timeout_handle); 1451 uhci_idone(ii); 1452 return; 1453 } 1454 1455 /* 1456 * If the last TD is still active we need to check whether there 1457 * is an error somewhere in the middle, or whether there was a 1458 * short packet (SPD and not ACTIVE). 1459 */ 1460 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1461 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1462 usb_syncmem(&std->dma, 1463 std->offs + offsetof(uhci_td_t, td_status), 1464 sizeof(std->td.td_status), 1465 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1466 status = le32toh(std->td.td_status); 1467 usb_syncmem(&std->dma, 1468 std->offs + offsetof(uhci_td_t, td_status), 1469 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1470 1471 /* If there's an active TD the xfer isn't done. */ 1472 if (status & UHCI_TD_ACTIVE) { 1473 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1474 __func__, ii, std)); 1475 return; 1476 } 1477 1478 /* Any kind of error makes the xfer done. */ 1479 if (status & UHCI_TD_STALLED) 1480 goto done; 1481 1482 /* 1483 * If the data phase of a control transfer is short, we need 1484 * to complete the status stage 1485 */ 1486 usbd_xfer_handle xfer = ii->xfer; 1487 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1488 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1489 1490 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1491 struct uhci_pipe *upipe = 1492 (struct uhci_pipe *)xfer->pipe; 1493 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1494 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1495 1496 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1497 "phase needs completion\n", __func__, ii, 1498 ii->stdstart)); 1499 1500 sqh->qh.qh_elink = 1501 htole32(stat->physaddr | UHCI_PTR_TD); 1502 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1503 BUS_DMASYNC_PREWRITE); 1504 break; 1505 } 1506 1507 /* We want short packets, and it is short: it's done */ 1508 usb_syncmem(&std->dma, 1509 std->offs + offsetof(uhci_td_t, td_token), 1510 sizeof(std->td.td_token), 1511 BUS_DMASYNC_POSTWRITE); 1512 1513 if ((status & UHCI_TD_SPD) && 1514 UHCI_TD_GET_ACTLEN(status) < 1515 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1516 goto done; 1517 } 1518 } 1519 } 1520 1521 /* Called with USB lock held. */ 1522 void 1523 uhci_idone(uhci_intr_info_t *ii) 1524 { 1525 usbd_xfer_handle xfer = ii->xfer; 1526 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1527 #ifdef DIAGNOSTIC 1528 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1529 #endif 1530 uhci_soft_td_t *std; 1531 u_int32_t status = 0, nstatus; 1532 int actlen; 1533 1534 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1535 1536 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1537 #ifdef DIAGNOSTIC 1538 { 1539 /* XXX SMP? */ 1540 int s = splhigh(); 1541 if (ii->isdone) { 1542 splx(s); 1543 #ifdef UHCI_DEBUG 1544 printf("uhci_idone: ii is done!\n "); 1545 uhci_dump_ii(ii); 1546 #else 1547 printf("uhci_idone: ii=%p is done!\n", ii); 1548 #endif 1549 return; 1550 } 1551 ii->isdone = 1; 1552 splx(s); 1553 } 1554 #endif 1555 1556 if (xfer->nframes != 0) { 1557 /* Isoc transfer, do things differently. */ 1558 uhci_soft_td_t **stds = upipe->u.iso.stds; 1559 int i, n, nframes, len; 1560 1561 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1562 1563 nframes = xfer->nframes; 1564 actlen = 0; 1565 n = UXFER(xfer)->curframe; 1566 for (i = 0; i < nframes; i++) { 1567 std = stds[n]; 1568 #ifdef UHCI_DEBUG 1569 if (uhcidebug > 5) { 1570 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1571 uhci_dump_td(std); 1572 } 1573 #endif 1574 if (++n >= UHCI_VFRAMELIST_COUNT) 1575 n = 0; 1576 usb_syncmem(&std->dma, 1577 std->offs + offsetof(uhci_td_t, td_status), 1578 sizeof(std->td.td_status), 1579 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1580 status = le32toh(std->td.td_status); 1581 len = UHCI_TD_GET_ACTLEN(status); 1582 xfer->frlengths[i] = len; 1583 actlen += len; 1584 } 1585 upipe->u.iso.inuse -= nframes; 1586 xfer->actlen = actlen; 1587 xfer->status = USBD_NORMAL_COMPLETION; 1588 goto end; 1589 } 1590 1591 #ifdef UHCI_DEBUG 1592 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1593 ii, xfer, upipe)); 1594 if (uhcidebug > 10) 1595 uhci_dump_tds(ii->stdstart); 1596 #endif 1597 1598 /* The transfer is done, compute actual length and status. */ 1599 actlen = 0; 1600 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1601 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1602 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1603 nstatus = le32toh(std->td.td_status); 1604 if (nstatus & UHCI_TD_ACTIVE) 1605 break; 1606 1607 status = nstatus; 1608 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1609 UHCI_TD_PID_SETUP) 1610 actlen += UHCI_TD_GET_ACTLEN(status); 1611 else { 1612 /* 1613 * UHCI will report CRCTO in addition to a STALL or NAK 1614 * for a SETUP transaction. See section 3.2.2, "TD 1615 * CONTROL AND STATUS". 1616 */ 1617 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1618 status &= ~UHCI_TD_CRCTO; 1619 } 1620 } 1621 /* If there are left over TDs we need to update the toggle. */ 1622 if (std != NULL) 1623 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1624 1625 status &= UHCI_TD_ERROR; 1626 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1627 actlen, status)); 1628 xfer->actlen = actlen; 1629 if (status != 0) { 1630 #ifdef UHCI_DEBUG 1631 char sbuf[128]; 1632 1633 snprintb(sbuf, sizeof(sbuf), 1634 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1635 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(u_int32_t)status); 1636 1637 DPRINTFN((status == UHCI_TD_STALLED)*10, 1638 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1639 "status 0x%s\n", 1640 xfer->pipe->device->address, 1641 xfer->pipe->endpoint->edesc->bEndpointAddress, 1642 sbuf)); 1643 #endif 1644 1645 if (status == UHCI_TD_STALLED) 1646 xfer->status = USBD_STALLED; 1647 else 1648 xfer->status = USBD_IOERROR; /* more info XXX */ 1649 } else { 1650 xfer->status = USBD_NORMAL_COMPLETION; 1651 } 1652 1653 end: 1654 usb_transfer_complete(xfer); 1655 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1656 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1657 } 1658 1659 /* 1660 * Called when a request does not complete. 1661 */ 1662 void 1663 uhci_timeout(void *addr) 1664 { 1665 uhci_intr_info_t *ii = addr; 1666 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1667 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1668 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1669 1670 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1671 1672 if (sc->sc_dying) { 1673 mutex_enter(&sc->sc_lock); 1674 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1675 mutex_exit(&sc->sc_lock); 1676 return; 1677 } 1678 1679 /* Execute the abort in a process context. */ 1680 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1681 USB_TASKQ_MPSAFE); 1682 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1683 USB_TASKQ_HC); 1684 } 1685 1686 void 1687 uhci_timeout_task(void *addr) 1688 { 1689 usbd_xfer_handle xfer = addr; 1690 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1691 1692 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1693 1694 mutex_enter(&sc->sc_lock); 1695 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1696 mutex_exit(&sc->sc_lock); 1697 } 1698 1699 /* 1700 * Wait here until controller claims to have an interrupt. 1701 * Then call uhci_intr and return. Use timeout to avoid waiting 1702 * too long. 1703 * Only used during boot when interrupts are not enabled yet. 1704 */ 1705 void 1706 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1707 { 1708 int timo = xfer->timeout; 1709 uhci_intr_info_t *ii; 1710 1711 mutex_enter(&sc->sc_lock); 1712 1713 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1714 1715 xfer->status = USBD_IN_PROGRESS; 1716 for (; timo >= 0; timo--) { 1717 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1718 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1719 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1720 mutex_spin_enter(&sc->sc_intr_lock); 1721 uhci_intr1(sc); 1722 mutex_spin_exit(&sc->sc_intr_lock); 1723 if (xfer->status != USBD_IN_PROGRESS) 1724 goto done; 1725 } 1726 } 1727 1728 /* Timeout */ 1729 DPRINTF(("uhci_waitintr: timeout\n")); 1730 for (ii = LIST_FIRST(&sc->sc_intrhead); 1731 ii != NULL && ii->xfer != xfer; 1732 ii = LIST_NEXT(ii, list)) 1733 ; 1734 #ifdef DIAGNOSTIC 1735 if (ii == NULL) 1736 panic("uhci_waitintr: lost intr_info"); 1737 #endif 1738 uhci_idone(ii); 1739 1740 done: 1741 mutex_exit(&sc->sc_lock); 1742 } 1743 1744 void 1745 uhci_poll(struct usbd_bus *bus) 1746 { 1747 uhci_softc_t *sc = bus->hci_private; 1748 1749 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1750 mutex_spin_enter(&sc->sc_intr_lock); 1751 uhci_intr1(sc); 1752 mutex_spin_exit(&sc->sc_intr_lock); 1753 } 1754 } 1755 1756 void 1757 uhci_reset(uhci_softc_t *sc) 1758 { 1759 int n; 1760 1761 UHCICMD(sc, UHCI_CMD_HCRESET); 1762 /* The reset bit goes low when the controller is done. */ 1763 for (n = 0; n < UHCI_RESET_TIMEOUT && 1764 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1765 usb_delay_ms(&sc->sc_bus, 1); 1766 if (n >= UHCI_RESET_TIMEOUT) 1767 printf("%s: controller did not reset\n", 1768 device_xname(sc->sc_dev)); 1769 } 1770 1771 usbd_status 1772 uhci_run(uhci_softc_t *sc, int run, int locked) 1773 { 1774 int n, running; 1775 u_int16_t cmd; 1776 1777 run = run != 0; 1778 if (!locked) 1779 mutex_spin_enter(&sc->sc_intr_lock); 1780 DPRINTF(("uhci_run: setting run=%d\n", run)); 1781 cmd = UREAD2(sc, UHCI_CMD); 1782 if (run) 1783 cmd |= UHCI_CMD_RS; 1784 else 1785 cmd &= ~UHCI_CMD_RS; 1786 UHCICMD(sc, cmd); 1787 for(n = 0; n < 10; n++) { 1788 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1789 /* return when we've entered the state we want */ 1790 if (run == running) { 1791 if (!locked) 1792 mutex_spin_exit(&sc->sc_intr_lock); 1793 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1794 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1795 return (USBD_NORMAL_COMPLETION); 1796 } 1797 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1798 } 1799 if (!locked) 1800 mutex_spin_exit(&sc->sc_intr_lock); 1801 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1802 run ? "start" : "stop"); 1803 return (USBD_IOERROR); 1804 } 1805 1806 /* 1807 * Memory management routines. 1808 * uhci_alloc_std allocates TDs 1809 * uhci_alloc_sqh allocates QHs 1810 * These two routines do their own free list management, 1811 * partly for speed, partly because allocating DMAable memory 1812 * has page size granularaity so much memory would be wasted if 1813 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1814 */ 1815 1816 uhci_soft_td_t * 1817 uhci_alloc_std(uhci_softc_t *sc) 1818 { 1819 uhci_soft_td_t *std; 1820 usbd_status err; 1821 int i, offs; 1822 usb_dma_t dma; 1823 1824 if (sc->sc_freetds == NULL) { 1825 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1826 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1827 UHCI_TD_ALIGN, &dma); 1828 if (err) 1829 return (0); 1830 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1831 offs = i * UHCI_STD_SIZE; 1832 std = KERNADDR(&dma, offs); 1833 std->physaddr = DMAADDR(&dma, offs); 1834 std->dma = dma; 1835 std->offs = offs; 1836 std->link.std = sc->sc_freetds; 1837 sc->sc_freetds = std; 1838 } 1839 } 1840 std = sc->sc_freetds; 1841 sc->sc_freetds = std->link.std; 1842 memset(&std->td, 0, sizeof(uhci_td_t)); 1843 return std; 1844 } 1845 1846 void 1847 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1848 { 1849 #ifdef DIAGNOSTIC 1850 #define TD_IS_FREE 0x12345678 1851 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1852 printf("uhci_free_std: freeing free TD %p\n", std); 1853 return; 1854 } 1855 std->td.td_token = htole32(TD_IS_FREE); 1856 #endif 1857 std->link.std = sc->sc_freetds; 1858 sc->sc_freetds = std; 1859 } 1860 1861 uhci_soft_qh_t * 1862 uhci_alloc_sqh(uhci_softc_t *sc) 1863 { 1864 uhci_soft_qh_t *sqh; 1865 usbd_status err; 1866 int i, offs; 1867 usb_dma_t dma; 1868 1869 if (sc->sc_freeqhs == NULL) { 1870 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1871 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1872 UHCI_QH_ALIGN, &dma); 1873 if (err) 1874 return (0); 1875 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1876 offs = i * UHCI_SQH_SIZE; 1877 sqh = KERNADDR(&dma, offs); 1878 sqh->physaddr = DMAADDR(&dma, offs); 1879 sqh->dma = dma; 1880 sqh->offs = offs; 1881 sqh->hlink = sc->sc_freeqhs; 1882 sc->sc_freeqhs = sqh; 1883 } 1884 } 1885 sqh = sc->sc_freeqhs; 1886 sc->sc_freeqhs = sqh->hlink; 1887 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1888 return (sqh); 1889 } 1890 1891 void 1892 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1893 { 1894 sqh->hlink = sc->sc_freeqhs; 1895 sc->sc_freeqhs = sqh; 1896 } 1897 1898 void 1899 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1900 uhci_soft_td_t *stdend) 1901 { 1902 uhci_soft_td_t *p; 1903 uint32_t td_link; 1904 1905 /* 1906 * to avoid race condition with the controller which may be looking 1907 * at this chain, we need to first invalidate all links, and 1908 * then wait for the controller to move to another queue 1909 */ 1910 for (p = std; p != stdend; p = p->link.std) { 1911 usb_syncmem(&p->dma, 1912 p->offs + offsetof(uhci_td_t, td_link), 1913 sizeof(p->td.td_link), 1914 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1915 td_link = le32toh(p->td.td_link); 1916 usb_syncmem(&p->dma, 1917 p->offs + offsetof(uhci_td_t, td_link), 1918 sizeof(p->td.td_link), 1919 BUS_DMASYNC_PREREAD); 1920 if ((td_link & UHCI_PTR_T) == 0) { 1921 p->td.td_link = htole32(UHCI_PTR_T); 1922 usb_syncmem(&p->dma, 1923 p->offs + offsetof(uhci_td_t, td_link), 1924 sizeof(p->td.td_link), 1925 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1926 } 1927 } 1928 delay(UHCI_QH_REMOVE_DELAY); 1929 1930 for (; std != stdend; std = p) { 1931 p = std->link.std; 1932 uhci_free_std(sc, std); 1933 } 1934 } 1935 1936 usbd_status 1937 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1938 int rd, u_int16_t flags, usb_dma_t *dma, 1939 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1940 { 1941 uhci_soft_td_t *p, *lastp; 1942 uhci_physaddr_t lastlink; 1943 int i, ntd, l, tog, maxp; 1944 u_int32_t status; 1945 int addr = upipe->pipe.device->address; 1946 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1947 1948 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1949 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1950 upipe->pipe.device->speed, flags)); 1951 1952 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1953 1954 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1955 if (maxp == 0) { 1956 printf("uhci_alloc_std_chain: maxp=0\n"); 1957 return (USBD_INVAL); 1958 } 1959 ntd = (len + maxp - 1) / maxp; 1960 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1961 ntd++; 1962 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1963 if (ntd == 0) { 1964 *sp = *ep = 0; 1965 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1966 return (USBD_NORMAL_COMPLETION); 1967 } 1968 tog = upipe->nexttoggle; 1969 if (ntd % 2 == 0) 1970 tog ^= 1; 1971 upipe->nexttoggle = tog ^ 1; 1972 lastp = NULL; 1973 lastlink = UHCI_PTR_T; 1974 ntd--; 1975 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1976 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1977 status |= UHCI_TD_LS; 1978 if (flags & USBD_SHORT_XFER_OK) 1979 status |= UHCI_TD_SPD; 1980 usb_syncmem(dma, 0, len, 1981 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1982 for (i = ntd; i >= 0; i--) { 1983 p = uhci_alloc_std(sc); 1984 if (p == NULL) { 1985 KASSERT(lastp != NULL); 1986 uhci_free_std_chain(sc, lastp, NULL); 1987 return (USBD_NOMEM); 1988 } 1989 p->link.std = lastp; 1990 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1991 lastp = p; 1992 lastlink = p->physaddr; 1993 p->td.td_status = htole32(status); 1994 if (i == ntd) { 1995 /* last TD */ 1996 l = len % maxp; 1997 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1998 l = maxp; 1999 *ep = p; 2000 } else 2001 l = maxp; 2002 p->td.td_token = 2003 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 2004 UHCI_TD_OUT(l, endpt, addr, tog)); 2005 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2006 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 2007 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2008 tog ^= 1; 2009 } 2010 *sp = lastp; 2011 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 2012 upipe->nexttoggle)); 2013 return (USBD_NORMAL_COMPLETION); 2014 } 2015 2016 void 2017 uhci_device_clear_toggle(usbd_pipe_handle pipe) 2018 { 2019 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2020 upipe->nexttoggle = 0; 2021 } 2022 2023 void 2024 uhci_noop(usbd_pipe_handle pipe) 2025 { 2026 } 2027 2028 usbd_status 2029 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 2030 { 2031 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2032 usbd_status err; 2033 2034 /* Insert last in queue. */ 2035 mutex_enter(&sc->sc_lock); 2036 err = usb_insert_transfer(xfer); 2037 mutex_exit(&sc->sc_lock); 2038 if (err) 2039 return (err); 2040 2041 /* 2042 * Pipe isn't running (otherwise err would be USBD_INPROG), 2043 * so start it first. 2044 */ 2045 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2046 } 2047 2048 usbd_status 2049 uhci_device_bulk_start(usbd_xfer_handle xfer) 2050 { 2051 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2052 usbd_device_handle dev = upipe->pipe.device; 2053 uhci_softc_t *sc = dev->bus->hci_private; 2054 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2055 uhci_soft_td_t *data, *dataend; 2056 uhci_soft_qh_t *sqh; 2057 usbd_status err; 2058 int len, isread, endpt; 2059 2060 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2061 xfer, xfer->length, xfer->flags, ii)); 2062 2063 if (sc->sc_dying) 2064 return (USBD_IOERROR); 2065 2066 #ifdef DIAGNOSTIC 2067 if (xfer->rqflags & URQ_REQUEST) 2068 panic("uhci_device_bulk_transfer: a request"); 2069 #endif 2070 2071 mutex_enter(&sc->sc_lock); 2072 2073 len = xfer->length; 2074 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2075 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2076 sqh = upipe->u.bulk.sqh; 2077 2078 upipe->u.bulk.isread = isread; 2079 upipe->u.bulk.length = len; 2080 2081 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2082 &xfer->dmabuf, &data, &dataend); 2083 if (err) { 2084 mutex_exit(&sc->sc_lock); 2085 return (err); 2086 } 2087 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2088 usb_syncmem(&dataend->dma, 2089 dataend->offs + offsetof(uhci_td_t, td_status), 2090 sizeof(dataend->td.td_status), 2091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2092 2093 2094 #ifdef UHCI_DEBUG 2095 if (uhcidebug > 8) { 2096 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2097 uhci_dump_tds(data); 2098 } 2099 #endif 2100 2101 /* Set up interrupt info. */ 2102 ii->xfer = xfer; 2103 ii->stdstart = data; 2104 ii->stdend = dataend; 2105 #ifdef DIAGNOSTIC 2106 if (!ii->isdone) { 2107 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2108 } 2109 ii->isdone = 0; 2110 #endif 2111 2112 sqh->elink = data; 2113 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2114 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2115 2116 uhci_add_bulk(sc, sqh); 2117 uhci_add_intr_info(sc, ii); 2118 2119 if (xfer->timeout && !sc->sc_bus.use_polling) { 2120 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2121 uhci_timeout, ii); 2122 } 2123 xfer->status = USBD_IN_PROGRESS; 2124 2125 #ifdef UHCI_DEBUG 2126 if (uhcidebug > 10) { 2127 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2128 uhci_dump_tds(data); 2129 } 2130 #endif 2131 2132 if (sc->sc_bus.use_polling) 2133 uhci_waitintr(sc, xfer); 2134 2135 mutex_exit(&sc->sc_lock); 2136 return (USBD_IN_PROGRESS); 2137 } 2138 2139 /* Abort a device bulk request. */ 2140 void 2141 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2142 { 2143 #ifdef DIAGNOSTIC 2144 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2145 #endif 2146 2147 KASSERT(mutex_owned(&sc->sc_lock)); 2148 2149 DPRINTF(("uhci_device_bulk_abort:\n")); 2150 uhci_abort_xfer(xfer, USBD_CANCELLED); 2151 } 2152 2153 /* 2154 * Abort a device request. 2155 * If this routine is called at splusb() it guarantees that the request 2156 * will be removed from the hardware scheduling and that the callback 2157 * for it will be called with USBD_CANCELLED status. 2158 * It's impossible to guarantee that the requested transfer will not 2159 * have happened since the hardware runs concurrently. 2160 * If the transaction has already happened we rely on the ordinary 2161 * interrupt processing to process it. 2162 * XXX This is most probably wrong. 2163 * XXXMRG this doesn't make sense anymore. 2164 */ 2165 void 2166 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2167 { 2168 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2169 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2170 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2171 uhci_soft_td_t *std; 2172 int wake; 2173 2174 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2175 2176 KASSERT(mutex_owned(&sc->sc_lock)); 2177 2178 if (sc->sc_dying) { 2179 /* If we're dying, just do the software part. */ 2180 xfer->status = status; /* make software ignore it */ 2181 callout_stop(&xfer->timeout_handle); 2182 usb_transfer_complete(xfer); 2183 return; 2184 } 2185 2186 if (cpu_intr_p() || cpu_softintr_p()) 2187 panic("uhci_abort_xfer: not in process context"); 2188 2189 /* 2190 * If an abort is already in progress then just wait for it to 2191 * complete and return. 2192 */ 2193 if (xfer->hcflags & UXFER_ABORTING) { 2194 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2195 #ifdef DIAGNOSTIC 2196 if (status == USBD_TIMEOUT) 2197 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2198 #endif 2199 /* Override the status which might be USBD_TIMEOUT. */ 2200 xfer->status = status; 2201 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2202 xfer->hcflags |= UXFER_ABORTWAIT; 2203 while (xfer->hcflags & UXFER_ABORTING) 2204 cv_wait(&xfer->hccv, &sc->sc_lock); 2205 goto done; 2206 } 2207 xfer->hcflags |= UXFER_ABORTING; 2208 2209 /* 2210 * Step 1: Make interrupt routine and hardware ignore xfer. 2211 */ 2212 xfer->status = status; /* make software ignore it */ 2213 callout_stop(&xfer->timeout_handle); 2214 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2215 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2216 usb_syncmem(&std->dma, 2217 std->offs + offsetof(uhci_td_t, td_status), 2218 sizeof(std->td.td_status), 2219 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2220 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2221 usb_syncmem(&std->dma, 2222 std->offs + offsetof(uhci_td_t, td_status), 2223 sizeof(std->td.td_status), 2224 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2225 } 2226 2227 /* 2228 * Step 2: Wait until we know hardware has finished any possible 2229 * use of the xfer. Also make sure the soft interrupt routine 2230 * has run. 2231 */ 2232 /* Hardware finishes in 1ms */ 2233 usb_delay_ms_locked(upipe->pipe.device->bus, 2, &sc->sc_lock); 2234 sc->sc_softwake = 1; 2235 usb_schedsoftintr(&sc->sc_bus); 2236 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2237 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2238 2239 /* 2240 * Step 3: Execute callback. 2241 */ 2242 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2243 #ifdef DIAGNOSTIC 2244 ii->isdone = 1; 2245 #endif 2246 wake = xfer->hcflags & UXFER_ABORTWAIT; 2247 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2248 usb_transfer_complete(xfer); 2249 if (wake) 2250 cv_broadcast(&xfer->hccv); 2251 done: 2252 KASSERT(mutex_owned(&sc->sc_lock)); 2253 } 2254 2255 /* Close a device bulk pipe. */ 2256 void 2257 uhci_device_bulk_close(usbd_pipe_handle pipe) 2258 { 2259 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2260 usbd_device_handle dev = upipe->pipe.device; 2261 uhci_softc_t *sc = dev->bus->hci_private; 2262 2263 KASSERT(mutex_owned(&sc->sc_lock)); 2264 2265 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2266 2267 pipe->endpoint->datatoggle = upipe->nexttoggle; 2268 } 2269 2270 usbd_status 2271 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2272 { 2273 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2274 usbd_status err; 2275 2276 /* Insert last in queue. */ 2277 mutex_enter(&sc->sc_lock); 2278 err = usb_insert_transfer(xfer); 2279 mutex_exit(&sc->sc_lock); 2280 if (err) 2281 return (err); 2282 2283 /* 2284 * Pipe isn't running (otherwise err would be USBD_INPROG), 2285 * so start it first. 2286 */ 2287 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2288 } 2289 2290 usbd_status 2291 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2292 { 2293 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2294 usbd_status err; 2295 2296 if (sc->sc_dying) 2297 return (USBD_IOERROR); 2298 2299 #ifdef DIAGNOSTIC 2300 if (!(xfer->rqflags & URQ_REQUEST)) 2301 panic("uhci_device_ctrl_transfer: not a request"); 2302 #endif 2303 2304 mutex_enter(&sc->sc_lock); 2305 err = uhci_device_request(xfer); 2306 mutex_exit(&sc->sc_lock); 2307 if (err) 2308 return (err); 2309 2310 if (sc->sc_bus.use_polling) 2311 uhci_waitintr(sc, xfer); 2312 return (USBD_IN_PROGRESS); 2313 } 2314 2315 usbd_status 2316 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2317 { 2318 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2319 usbd_status err; 2320 2321 /* Insert last in queue. */ 2322 mutex_enter(&sc->sc_lock); 2323 err = usb_insert_transfer(xfer); 2324 mutex_exit(&sc->sc_lock); 2325 if (err) 2326 return (err); 2327 2328 /* 2329 * Pipe isn't running (otherwise err would be USBD_INPROG), 2330 * so start it first. 2331 */ 2332 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2333 } 2334 2335 usbd_status 2336 uhci_device_intr_start(usbd_xfer_handle xfer) 2337 { 2338 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2339 usbd_device_handle dev = upipe->pipe.device; 2340 uhci_softc_t *sc = dev->bus->hci_private; 2341 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2342 uhci_soft_td_t *data, *dataend; 2343 uhci_soft_qh_t *sqh; 2344 usbd_status err; 2345 int isread, endpt; 2346 int i; 2347 2348 if (sc->sc_dying) 2349 return (USBD_IOERROR); 2350 2351 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2352 xfer, xfer->length, xfer->flags)); 2353 2354 #ifdef DIAGNOSTIC 2355 if (xfer->rqflags & URQ_REQUEST) 2356 panic("uhci_device_intr_transfer: a request"); 2357 #endif 2358 2359 mutex_enter(&sc->sc_lock); 2360 2361 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2362 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2363 2364 upipe->u.intr.isread = isread; 2365 2366 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2367 xfer->flags, &xfer->dmabuf, &data, 2368 &dataend); 2369 if (err) { 2370 mutex_exit(&sc->sc_lock); 2371 return (err); 2372 } 2373 2374 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2375 usb_syncmem(&dataend->dma, 2376 dataend->offs + offsetof(uhci_td_t, td_status), 2377 sizeof(dataend->td.td_status), 2378 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2379 2380 #ifdef UHCI_DEBUG 2381 if (uhcidebug > 10) { 2382 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2383 uhci_dump_tds(data); 2384 uhci_dump_qh(upipe->u.intr.qhs[0]); 2385 } 2386 #endif 2387 2388 /* Set up interrupt info. */ 2389 ii->xfer = xfer; 2390 ii->stdstart = data; 2391 ii->stdend = dataend; 2392 #ifdef DIAGNOSTIC 2393 if (!ii->isdone) { 2394 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2395 } 2396 ii->isdone = 0; 2397 #endif 2398 2399 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2400 upipe->u.intr.qhs[0])); 2401 for (i = 0; i < upipe->u.intr.npoll; i++) { 2402 sqh = upipe->u.intr.qhs[i]; 2403 sqh->elink = data; 2404 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2405 usb_syncmem(&sqh->dma, 2406 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2407 sizeof(sqh->qh.qh_elink), 2408 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2409 } 2410 uhci_add_intr_info(sc, ii); 2411 xfer->status = USBD_IN_PROGRESS; 2412 mutex_exit(&sc->sc_lock); 2413 2414 #ifdef UHCI_DEBUG 2415 if (uhcidebug > 10) { 2416 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2417 uhci_dump_tds(data); 2418 uhci_dump_qh(upipe->u.intr.qhs[0]); 2419 } 2420 #endif 2421 2422 return (USBD_IN_PROGRESS); 2423 } 2424 2425 /* Abort a device control request. */ 2426 void 2427 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2428 { 2429 #ifdef DIAGNOSTIC 2430 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2431 #endif 2432 2433 KASSERT(mutex_owned(&sc->sc_lock)); 2434 2435 DPRINTF(("uhci_device_ctrl_abort:\n")); 2436 uhci_abort_xfer(xfer, USBD_CANCELLED); 2437 } 2438 2439 /* Close a device control pipe. */ 2440 void 2441 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2442 { 2443 } 2444 2445 /* Abort a device interrupt request. */ 2446 void 2447 uhci_device_intr_abort(usbd_xfer_handle xfer) 2448 { 2449 #ifdef DIAGNOSTIC 2450 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2451 #endif 2452 2453 KASSERT(mutex_owned(&sc->sc_lock)); 2454 KASSERT(xfer->pipe->intrxfer == xfer); 2455 2456 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2457 2458 uhci_abort_xfer(xfer, USBD_CANCELLED); 2459 } 2460 2461 /* Close a device interrupt pipe. */ 2462 void 2463 uhci_device_intr_close(usbd_pipe_handle pipe) 2464 { 2465 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2466 uhci_softc_t *sc = pipe->device->bus->hci_private; 2467 int i, npoll; 2468 2469 KASSERT(mutex_owned(&sc->sc_lock)); 2470 2471 /* Unlink descriptors from controller data structures. */ 2472 npoll = upipe->u.intr.npoll; 2473 for (i = 0; i < npoll; i++) 2474 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2475 2476 /* 2477 * We now have to wait for any activity on the physical 2478 * descriptors to stop. 2479 */ 2480 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2481 2482 for(i = 0; i < npoll; i++) 2483 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2484 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2485 2486 /* XXX free other resources */ 2487 } 2488 2489 usbd_status 2490 uhci_device_request(usbd_xfer_handle xfer) 2491 { 2492 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2493 usb_device_request_t *req = &xfer->request; 2494 usbd_device_handle dev = upipe->pipe.device; 2495 uhci_softc_t *sc = dev->bus->hci_private; 2496 int addr = dev->address; 2497 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2498 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2499 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2500 uhci_soft_qh_t *sqh; 2501 int len; 2502 u_int32_t ls; 2503 usbd_status err; 2504 int isread; 2505 2506 KASSERT(mutex_owned(&sc->sc_lock)); 2507 2508 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2509 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2510 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2511 UGETW(req->wIndex), UGETW(req->wLength), 2512 addr, endpt)); 2513 2514 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2515 isread = req->bmRequestType & UT_READ; 2516 len = UGETW(req->wLength); 2517 2518 setup = upipe->u.ctl.setup; 2519 stat = upipe->u.ctl.stat; 2520 sqh = upipe->u.ctl.sqh; 2521 2522 /* Set up data transaction */ 2523 if (len != 0) { 2524 upipe->nexttoggle = 1; 2525 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2526 &xfer->dmabuf, &data, &dataend); 2527 if (err) 2528 return (err); 2529 next = data; 2530 dataend->link.std = stat; 2531 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2532 usb_syncmem(&dataend->dma, 2533 dataend->offs + offsetof(uhci_td_t, td_link), 2534 sizeof(dataend->td.td_link), 2535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2536 } else { 2537 next = stat; 2538 } 2539 upipe->u.ctl.length = len; 2540 2541 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2542 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2543 2544 setup->link.std = next; 2545 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2546 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2547 UHCI_TD_ACTIVE); 2548 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2549 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2550 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2551 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2552 2553 stat->link.std = NULL; 2554 stat->td.td_link = htole32(UHCI_PTR_T); 2555 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2556 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2557 stat->td.td_token = 2558 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2559 UHCI_TD_IN (0, endpt, addr, 1)); 2560 stat->td.td_buffer = htole32(0); 2561 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2562 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2563 2564 #ifdef UHCI_DEBUG 2565 if (uhcidebug > 10) { 2566 DPRINTF(("uhci_device_request: before transfer\n")); 2567 uhci_dump_tds(setup); 2568 } 2569 #endif 2570 2571 /* Set up interrupt info. */ 2572 ii->xfer = xfer; 2573 ii->stdstart = setup; 2574 ii->stdend = stat; 2575 #ifdef DIAGNOSTIC 2576 if (!ii->isdone) { 2577 printf("uhci_device_request: not done, ii=%p\n", ii); 2578 } 2579 ii->isdone = 0; 2580 #endif 2581 2582 sqh->elink = setup; 2583 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2584 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2585 2586 if (dev->speed == USB_SPEED_LOW) 2587 uhci_add_ls_ctrl(sc, sqh); 2588 else 2589 uhci_add_hs_ctrl(sc, sqh); 2590 uhci_add_intr_info(sc, ii); 2591 #ifdef UHCI_DEBUG 2592 if (uhcidebug > 12) { 2593 uhci_soft_td_t *std; 2594 uhci_soft_qh_t *xqh; 2595 uhci_soft_qh_t *sxqh; 2596 int maxqh = 0; 2597 uhci_physaddr_t link; 2598 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2599 for (std = sc->sc_vframes[0].htd, link = 0; 2600 (link & UHCI_PTR_QH) == 0; 2601 std = std->link.std) { 2602 link = le32toh(std->td.td_link); 2603 uhci_dump_td(std); 2604 } 2605 sxqh = (uhci_soft_qh_t *)std; 2606 uhci_dump_qh(sxqh); 2607 for (xqh = sxqh; 2608 xqh != NULL; 2609 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2610 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2611 uhci_dump_qh(xqh); 2612 } 2613 DPRINTF(("Enqueued QH:\n")); 2614 uhci_dump_qh(sqh); 2615 uhci_dump_tds(sqh->elink); 2616 } 2617 #endif 2618 if (xfer->timeout && !sc->sc_bus.use_polling) { 2619 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2620 uhci_timeout, ii); 2621 } 2622 xfer->status = USBD_IN_PROGRESS; 2623 2624 return (USBD_NORMAL_COMPLETION); 2625 } 2626 2627 usbd_status 2628 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2629 { 2630 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2631 usbd_status err; 2632 2633 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2634 2635 /* Put it on our queue, */ 2636 mutex_enter(&sc->sc_lock); 2637 err = usb_insert_transfer(xfer); 2638 mutex_exit(&sc->sc_lock); 2639 2640 /* bail out on error, */ 2641 if (err && err != USBD_IN_PROGRESS) 2642 return (err); 2643 2644 /* XXX should check inuse here */ 2645 2646 /* insert into schedule, */ 2647 uhci_device_isoc_enter(xfer); 2648 2649 /* and start if the pipe wasn't running */ 2650 if (!err) 2651 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2652 2653 return (err); 2654 } 2655 2656 void 2657 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2658 { 2659 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2660 usbd_device_handle dev = upipe->pipe.device; 2661 uhci_softc_t *sc = dev->bus->hci_private; 2662 struct iso *iso = &upipe->u.iso; 2663 uhci_soft_td_t *std; 2664 u_int32_t buf, len, status, offs; 2665 int i, next, nframes; 2666 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2667 2668 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2669 "nframes=%d\n", 2670 iso->inuse, iso->next, xfer, xfer->nframes)); 2671 2672 if (sc->sc_dying) 2673 return; 2674 2675 if (xfer->status == USBD_IN_PROGRESS) { 2676 /* This request has already been entered into the frame list */ 2677 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2678 /* XXX */ 2679 } 2680 2681 #ifdef DIAGNOSTIC 2682 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2683 printf("uhci_device_isoc_enter: overflow!\n"); 2684 #endif 2685 2686 next = iso->next; 2687 if (next == -1) { 2688 /* Not in use yet, schedule it a few frames ahead. */ 2689 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2690 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2691 } 2692 2693 xfer->status = USBD_IN_PROGRESS; 2694 UXFER(xfer)->curframe = next; 2695 2696 buf = DMAADDR(&xfer->dmabuf, 0); 2697 offs = 0; 2698 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2699 UHCI_TD_ACTIVE | 2700 UHCI_TD_IOS); 2701 nframes = xfer->nframes; 2702 mutex_enter(&sc->sc_lock); 2703 for (i = 0; i < nframes; i++) { 2704 std = iso->stds[next]; 2705 if (++next >= UHCI_VFRAMELIST_COUNT) 2706 next = 0; 2707 len = xfer->frlengths[i]; 2708 std->td.td_buffer = htole32(buf); 2709 usb_syncmem(&xfer->dmabuf, offs, len, 2710 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2711 if (i == nframes - 1) 2712 status |= UHCI_TD_IOC; 2713 std->td.td_status = htole32(status); 2714 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2715 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2716 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2717 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2718 #ifdef UHCI_DEBUG 2719 if (uhcidebug > 5) { 2720 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2721 uhci_dump_td(std); 2722 } 2723 #endif 2724 buf += len; 2725 offs += len; 2726 } 2727 iso->next = next; 2728 iso->inuse += xfer->nframes; 2729 2730 mutex_exit(&sc->sc_lock); 2731 } 2732 2733 usbd_status 2734 uhci_device_isoc_start(usbd_xfer_handle xfer) 2735 { 2736 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2737 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2738 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2739 uhci_soft_td_t *end; 2740 int i; 2741 2742 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2743 2744 mutex_enter(&sc->sc_lock); 2745 2746 if (sc->sc_dying) { 2747 mutex_exit(&sc->sc_lock); 2748 return (USBD_IOERROR); 2749 } 2750 2751 #ifdef DIAGNOSTIC 2752 if (xfer->status != USBD_IN_PROGRESS) 2753 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2754 #endif 2755 2756 /* Find the last TD */ 2757 i = UXFER(xfer)->curframe + xfer->nframes; 2758 if (i >= UHCI_VFRAMELIST_COUNT) 2759 i -= UHCI_VFRAMELIST_COUNT; 2760 end = upipe->u.iso.stds[i]; 2761 2762 #ifdef DIAGNOSTIC 2763 if (end == NULL) { 2764 printf("uhci_device_isoc_start: end == NULL\n"); 2765 return (USBD_INVAL); 2766 } 2767 #endif 2768 2769 /* Set up interrupt info. */ 2770 ii->xfer = xfer; 2771 ii->stdstart = end; 2772 ii->stdend = end; 2773 #ifdef DIAGNOSTIC 2774 if (!ii->isdone) 2775 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2776 ii->isdone = 0; 2777 #endif 2778 uhci_add_intr_info(sc, ii); 2779 2780 mutex_exit(&sc->sc_lock); 2781 2782 return (USBD_IN_PROGRESS); 2783 } 2784 2785 void 2786 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2787 { 2788 #ifdef DIAGNOSTIC 2789 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2790 #endif 2791 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2792 uhci_soft_td_t **stds = upipe->u.iso.stds; 2793 uhci_soft_td_t *std; 2794 int i, n, nframes, maxlen, len; 2795 2796 KASSERT(mutex_owned(&sc->sc_lock)); 2797 2798 /* Transfer is already done. */ 2799 if (xfer->status != USBD_NOT_STARTED && 2800 xfer->status != USBD_IN_PROGRESS) { 2801 return; 2802 } 2803 2804 /* Give xfer the requested abort code. */ 2805 xfer->status = USBD_CANCELLED; 2806 2807 /* make hardware ignore it, */ 2808 nframes = xfer->nframes; 2809 n = UXFER(xfer)->curframe; 2810 maxlen = 0; 2811 for (i = 0; i < nframes; i++) { 2812 std = stds[n]; 2813 usb_syncmem(&std->dma, 2814 std->offs + offsetof(uhci_td_t, td_status), 2815 sizeof(std->td.td_status), 2816 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2817 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2818 usb_syncmem(&std->dma, 2819 std->offs + offsetof(uhci_td_t, td_status), 2820 sizeof(std->td.td_status), 2821 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2822 usb_syncmem(&std->dma, 2823 std->offs + offsetof(uhci_td_t, td_token), 2824 sizeof(std->td.td_token), 2825 BUS_DMASYNC_POSTWRITE); 2826 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2827 if (len > maxlen) 2828 maxlen = len; 2829 if (++n >= UHCI_VFRAMELIST_COUNT) 2830 n = 0; 2831 } 2832 2833 /* and wait until we are sure the hardware has finished. */ 2834 delay(maxlen); 2835 2836 #ifdef DIAGNOSTIC 2837 UXFER(xfer)->iinfo.isdone = 1; 2838 #endif 2839 /* Run callback and remove from interrupt list. */ 2840 usb_transfer_complete(xfer); 2841 2842 KASSERT(mutex_owned(&sc->sc_lock)); 2843 } 2844 2845 void 2846 uhci_device_isoc_close(usbd_pipe_handle pipe) 2847 { 2848 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2849 usbd_device_handle dev = upipe->pipe.device; 2850 uhci_softc_t *sc = dev->bus->hci_private; 2851 uhci_soft_td_t *std, *vstd; 2852 struct iso *iso; 2853 int i; 2854 2855 KASSERT(mutex_owned(&sc->sc_lock)); 2856 2857 /* 2858 * Make sure all TDs are marked as inactive. 2859 * Wait for completion. 2860 * Unschedule. 2861 * Deallocate. 2862 */ 2863 iso = &upipe->u.iso; 2864 2865 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2866 std = iso->stds[i]; 2867 usb_syncmem(&std->dma, 2868 std->offs + offsetof(uhci_td_t, td_status), 2869 sizeof(std->td.td_status), 2870 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2871 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2872 usb_syncmem(&std->dma, 2873 std->offs + offsetof(uhci_td_t, td_status), 2874 sizeof(std->td.td_status), 2875 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2876 } 2877 /* wait for completion */ 2878 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2879 2880 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2881 std = iso->stds[i]; 2882 for (vstd = sc->sc_vframes[i].htd; 2883 vstd != NULL && vstd->link.std != std; 2884 vstd = vstd->link.std) 2885 ; 2886 if (vstd == NULL) { 2887 /*panic*/ 2888 printf("uhci_device_isoc_close: %p not found\n", std); 2889 mutex_exit(&sc->sc_lock); 2890 return; 2891 } 2892 vstd->link = std->link; 2893 usb_syncmem(&std->dma, 2894 std->offs + offsetof(uhci_td_t, td_link), 2895 sizeof(std->td.td_link), 2896 BUS_DMASYNC_POSTWRITE); 2897 vstd->td.td_link = std->td.td_link; 2898 usb_syncmem(&vstd->dma, 2899 vstd->offs + offsetof(uhci_td_t, td_link), 2900 sizeof(vstd->td.td_link), 2901 BUS_DMASYNC_PREWRITE); 2902 uhci_free_std(sc, std); 2903 } 2904 2905 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2906 } 2907 2908 usbd_status 2909 uhci_setup_isoc(usbd_pipe_handle pipe) 2910 { 2911 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2912 usbd_device_handle dev = upipe->pipe.device; 2913 uhci_softc_t *sc = dev->bus->hci_private; 2914 int addr = upipe->pipe.device->address; 2915 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2916 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2917 uhci_soft_td_t *std, *vstd; 2918 u_int32_t token; 2919 struct iso *iso; 2920 int i; 2921 2922 iso = &upipe->u.iso; 2923 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2924 sizeof (uhci_soft_td_t *), 2925 KM_SLEEP); 2926 if (iso->stds == NULL) 2927 return USBD_NOMEM; 2928 2929 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2930 UHCI_TD_OUT(0, endpt, addr, 0); 2931 2932 mutex_enter(&sc->sc_lock); 2933 2934 /* Allocate the TDs and mark as inactive; */ 2935 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2936 std = uhci_alloc_std(sc); 2937 if (std == 0) 2938 goto bad; 2939 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2940 std->td.td_token = htole32(token); 2941 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2942 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2943 iso->stds[i] = std; 2944 } 2945 2946 /* Insert TDs into schedule. */ 2947 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2948 std = iso->stds[i]; 2949 vstd = sc->sc_vframes[i].htd; 2950 usb_syncmem(&vstd->dma, 2951 vstd->offs + offsetof(uhci_td_t, td_link), 2952 sizeof(vstd->td.td_link), 2953 BUS_DMASYNC_POSTWRITE); 2954 std->link = vstd->link; 2955 std->td.td_link = vstd->td.td_link; 2956 usb_syncmem(&std->dma, 2957 std->offs + offsetof(uhci_td_t, td_link), 2958 sizeof(std->td.td_link), 2959 BUS_DMASYNC_PREWRITE); 2960 vstd->link.std = std; 2961 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2962 usb_syncmem(&vstd->dma, 2963 vstd->offs + offsetof(uhci_td_t, td_link), 2964 sizeof(vstd->td.td_link), 2965 BUS_DMASYNC_PREWRITE); 2966 } 2967 mutex_exit(&sc->sc_lock); 2968 2969 iso->next = -1; 2970 iso->inuse = 0; 2971 2972 return (USBD_NORMAL_COMPLETION); 2973 2974 bad: 2975 while (--i >= 0) 2976 uhci_free_std(sc, iso->stds[i]); 2977 mutex_exit(&sc->sc_lock); 2978 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2979 return (USBD_NOMEM); 2980 } 2981 2982 void 2983 uhci_device_isoc_done(usbd_xfer_handle xfer) 2984 { 2985 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2986 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2987 int i, offs; 2988 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2989 2990 2991 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2992 xfer->actlen, xfer->busy_free)); 2993 2994 if (ii->xfer != xfer) 2995 /* Not on interrupt list, ignore it. */ 2996 return; 2997 2998 if (!uhci_active_intr_info(ii)) 2999 return; 3000 3001 #ifdef DIAGNOSTIC 3002 if (ii->stdend == NULL) { 3003 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 3004 #ifdef UHCI_DEBUG 3005 uhci_dump_ii(ii); 3006 #endif 3007 return; 3008 } 3009 #endif 3010 3011 /* Turn off the interrupt since it is active even if the TD is not. */ 3012 usb_syncmem(&ii->stdend->dma, 3013 ii->stdend->offs + offsetof(uhci_td_t, td_status), 3014 sizeof(ii->stdend->td.td_status), 3015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3016 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3017 usb_syncmem(&ii->stdend->dma, 3018 ii->stdend->offs + offsetof(uhci_td_t, td_status), 3019 sizeof(ii->stdend->td.td_status), 3020 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3021 3022 uhci_del_intr_info(ii); /* remove from active list */ 3023 3024 offs = 0; 3025 for (i = 0; i < xfer->nframes; i++) { 3026 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 3027 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3028 offs += xfer->frlengths[i]; 3029 } 3030 } 3031 3032 void 3033 uhci_device_intr_done(usbd_xfer_handle xfer) 3034 { 3035 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3036 uhci_softc_t *sc = ii->sc; 3037 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3038 uhci_soft_qh_t *sqh; 3039 int i, npoll, isread; 3040 3041 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3042 3043 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3044 3045 npoll = upipe->u.intr.npoll; 3046 for(i = 0; i < npoll; i++) { 3047 sqh = upipe->u.intr.qhs[i]; 3048 sqh->elink = NULL; 3049 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3050 usb_syncmem(&sqh->dma, 3051 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3052 sizeof(sqh->qh.qh_elink), 3053 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3054 } 3055 uhci_free_std_chain(sc, ii->stdstart, NULL); 3056 3057 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3058 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3059 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3060 3061 /* XXX Wasteful. */ 3062 if (xfer->pipe->repeat) { 3063 uhci_soft_td_t *data, *dataend; 3064 3065 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3066 3067 /* This alloc cannot fail since we freed the chain above. */ 3068 uhci_alloc_std_chain(upipe, sc, xfer->length, 3069 upipe->u.intr.isread, xfer->flags, 3070 &xfer->dmabuf, &data, &dataend); 3071 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3072 usb_syncmem(&dataend->dma, 3073 dataend->offs + offsetof(uhci_td_t, td_status), 3074 sizeof(dataend->td.td_status), 3075 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3076 3077 #ifdef UHCI_DEBUG 3078 if (uhcidebug > 10) { 3079 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3080 uhci_dump_tds(data); 3081 uhci_dump_qh(upipe->u.intr.qhs[0]); 3082 } 3083 #endif 3084 3085 ii->stdstart = data; 3086 ii->stdend = dataend; 3087 #ifdef DIAGNOSTIC 3088 if (!ii->isdone) { 3089 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3090 } 3091 ii->isdone = 0; 3092 #endif 3093 for (i = 0; i < npoll; i++) { 3094 sqh = upipe->u.intr.qhs[i]; 3095 sqh->elink = data; 3096 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3097 usb_syncmem(&sqh->dma, 3098 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3099 sizeof(sqh->qh.qh_elink), 3100 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3101 } 3102 xfer->status = USBD_IN_PROGRESS; 3103 /* The ii is already on the examined list, just leave it. */ 3104 } else { 3105 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3106 if (uhci_active_intr_info(ii)) 3107 uhci_del_intr_info(ii); 3108 } 3109 } 3110 3111 /* Deallocate request data structures */ 3112 void 3113 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3114 { 3115 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3116 uhci_softc_t *sc = ii->sc; 3117 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3118 int len = UGETW(xfer->request.wLength); 3119 int isread = (xfer->request.bmRequestType & UT_READ); 3120 3121 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3122 3123 #ifdef DIAGNOSTIC 3124 if (!(xfer->rqflags & URQ_REQUEST)) 3125 panic("uhci_device_ctrl_done: not a request"); 3126 #endif 3127 3128 if (!uhci_active_intr_info(ii)) 3129 return; 3130 3131 uhci_del_intr_info(ii); /* remove from active list */ 3132 3133 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3134 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3135 else 3136 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3137 3138 if (upipe->u.ctl.length != 0) 3139 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3140 3141 if (len) { 3142 usb_syncmem(&xfer->dmabuf, 0, len, 3143 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3144 } 3145 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3146 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3147 3148 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3149 } 3150 3151 /* Deallocate request data structures */ 3152 void 3153 uhci_device_bulk_done(usbd_xfer_handle xfer) 3154 { 3155 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3156 uhci_softc_t *sc = ii->sc; 3157 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3158 3159 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3160 xfer, ii, sc, upipe)); 3161 3162 KASSERT(mutex_owned(&sc->sc_lock)); 3163 3164 if (!uhci_active_intr_info(ii)) 3165 return; 3166 3167 uhci_del_intr_info(ii); /* remove from active list */ 3168 3169 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3170 3171 uhci_free_std_chain(sc, ii->stdstart, NULL); 3172 3173 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3174 } 3175 3176 /* Add interrupt QH, called with vflock. */ 3177 void 3178 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3179 { 3180 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3181 uhci_soft_qh_t *eqh; 3182 3183 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3184 3185 eqh = vf->eqh; 3186 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3187 sizeof(eqh->qh.qh_hlink), 3188 BUS_DMASYNC_POSTWRITE); 3189 sqh->hlink = eqh->hlink; 3190 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3191 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3192 sizeof(sqh->qh.qh_hlink), 3193 BUS_DMASYNC_PREWRITE); 3194 eqh->hlink = sqh; 3195 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3196 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3197 sizeof(eqh->qh.qh_hlink), 3198 BUS_DMASYNC_PREWRITE); 3199 vf->eqh = sqh; 3200 vf->bandwidth++; 3201 } 3202 3203 /* Remove interrupt QH. */ 3204 void 3205 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3206 { 3207 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3208 uhci_soft_qh_t *pqh; 3209 3210 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3211 3212 /* See comment in uhci_remove_ctrl() */ 3213 3214 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3215 sizeof(sqh->qh.qh_elink), 3216 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3217 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3218 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3219 usb_syncmem(&sqh->dma, 3220 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3221 sizeof(sqh->qh.qh_elink), 3222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3223 delay(UHCI_QH_REMOVE_DELAY); 3224 } 3225 3226 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3227 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3228 sizeof(sqh->qh.qh_hlink), 3229 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3230 pqh->hlink = sqh->hlink; 3231 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3232 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3233 sizeof(pqh->qh.qh_hlink), 3234 BUS_DMASYNC_PREWRITE); 3235 delay(UHCI_QH_REMOVE_DELAY); 3236 if (vf->eqh == sqh) 3237 vf->eqh = pqh; 3238 vf->bandwidth--; 3239 } 3240 3241 usbd_status 3242 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3243 { 3244 uhci_soft_qh_t *sqh; 3245 int i, npoll; 3246 u_int bestbw, bw, bestoffs, offs; 3247 3248 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3249 if (ival == 0) { 3250 printf("uhci_device_setintr: 0 interval\n"); 3251 return (USBD_INVAL); 3252 } 3253 3254 if (ival > UHCI_VFRAMELIST_COUNT) 3255 ival = UHCI_VFRAMELIST_COUNT; 3256 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3257 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3258 3259 upipe->u.intr.npoll = npoll; 3260 upipe->u.intr.qhs = 3261 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3262 if (upipe->u.intr.qhs == NULL) 3263 return USBD_NOMEM; 3264 3265 /* 3266 * Figure out which offset in the schedule that has most 3267 * bandwidth left over. 3268 */ 3269 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3270 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3271 for (bw = i = 0; i < npoll; i++) 3272 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3273 if (bw < bestbw) { 3274 bestbw = bw; 3275 bestoffs = offs; 3276 } 3277 } 3278 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3279 3280 mutex_enter(&sc->sc_lock); 3281 for(i = 0; i < npoll; i++) { 3282 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3283 sqh->elink = NULL; 3284 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3285 usb_syncmem(&sqh->dma, 3286 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3287 sizeof(sqh->qh.qh_elink), 3288 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3289 sqh->pos = MOD(i * ival + bestoffs); 3290 } 3291 #undef MOD 3292 3293 /* Enter QHs into the controller data structures. */ 3294 for(i = 0; i < npoll; i++) 3295 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3296 mutex_exit(&sc->sc_lock); 3297 3298 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3299 return (USBD_NORMAL_COMPLETION); 3300 } 3301 3302 /* Open a new pipe. */ 3303 usbd_status 3304 uhci_open(usbd_pipe_handle pipe) 3305 { 3306 uhci_softc_t *sc = pipe->device->bus->hci_private; 3307 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3308 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3309 usbd_status err = USBD_NOMEM; 3310 int ival; 3311 3312 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3313 pipe, pipe->device->address, 3314 ed->bEndpointAddress, sc->sc_addr)); 3315 3316 if (sc->sc_dying) 3317 return USBD_IOERROR; 3318 3319 upipe->aborting = 0; 3320 /* toggle state needed for bulk endpoints */ 3321 upipe->nexttoggle = pipe->endpoint->datatoggle; 3322 3323 if (pipe->device->address == sc->sc_addr) { 3324 switch (ed->bEndpointAddress) { 3325 case USB_CONTROL_ENDPOINT: 3326 pipe->methods = &uhci_root_ctrl_methods; 3327 break; 3328 case UE_DIR_IN | UHCI_INTR_ENDPT: 3329 pipe->methods = &uhci_root_intr_methods; 3330 break; 3331 default: 3332 return (USBD_INVAL); 3333 } 3334 } else { 3335 switch (ed->bmAttributes & UE_XFERTYPE) { 3336 case UE_CONTROL: 3337 pipe->methods = &uhci_device_ctrl_methods; 3338 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3339 if (upipe->u.ctl.sqh == NULL) 3340 goto bad; 3341 upipe->u.ctl.setup = uhci_alloc_std(sc); 3342 if (upipe->u.ctl.setup == NULL) { 3343 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3344 goto bad; 3345 } 3346 upipe->u.ctl.stat = uhci_alloc_std(sc); 3347 if (upipe->u.ctl.stat == NULL) { 3348 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3349 uhci_free_std(sc, upipe->u.ctl.setup); 3350 goto bad; 3351 } 3352 err = usb_allocmem(&sc->sc_bus, 3353 sizeof(usb_device_request_t), 3354 0, &upipe->u.ctl.reqdma); 3355 if (err) { 3356 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3357 uhci_free_std(sc, upipe->u.ctl.setup); 3358 uhci_free_std(sc, upipe->u.ctl.stat); 3359 goto bad; 3360 } 3361 break; 3362 case UE_INTERRUPT: 3363 pipe->methods = &uhci_device_intr_methods; 3364 ival = pipe->interval; 3365 if (ival == USBD_DEFAULT_INTERVAL) 3366 ival = ed->bInterval; 3367 return (uhci_device_setintr(sc, upipe, ival)); 3368 case UE_ISOCHRONOUS: 3369 pipe->methods = &uhci_device_isoc_methods; 3370 return (uhci_setup_isoc(pipe)); 3371 case UE_BULK: 3372 pipe->methods = &uhci_device_bulk_methods; 3373 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3374 if (upipe->u.bulk.sqh == NULL) 3375 goto bad; 3376 break; 3377 } 3378 } 3379 return (USBD_NORMAL_COMPLETION); 3380 3381 bad: 3382 return USBD_NOMEM; 3383 } 3384 3385 /* 3386 * Data structures and routines to emulate the root hub. 3387 */ 3388 usb_device_descriptor_t uhci_devd = { 3389 USB_DEVICE_DESCRIPTOR_SIZE, 3390 UDESC_DEVICE, /* type */ 3391 {0x00, 0x01}, /* USB version */ 3392 UDCLASS_HUB, /* class */ 3393 UDSUBCLASS_HUB, /* subclass */ 3394 UDPROTO_FSHUB, /* protocol */ 3395 64, /* max packet */ 3396 {0},{0},{0x00,0x01}, /* device id */ 3397 1,2,0, /* string indicies */ 3398 1 /* # of configurations */ 3399 }; 3400 3401 const usb_config_descriptor_t uhci_confd = { 3402 USB_CONFIG_DESCRIPTOR_SIZE, 3403 UDESC_CONFIG, 3404 {USB_CONFIG_DESCRIPTOR_SIZE + 3405 USB_INTERFACE_DESCRIPTOR_SIZE + 3406 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3407 1, 3408 1, 3409 0, 3410 UC_ATTR_MBO | UC_SELF_POWERED, 3411 0 /* max power */ 3412 }; 3413 3414 const usb_interface_descriptor_t uhci_ifcd = { 3415 USB_INTERFACE_DESCRIPTOR_SIZE, 3416 UDESC_INTERFACE, 3417 0, 3418 0, 3419 1, 3420 UICLASS_HUB, 3421 UISUBCLASS_HUB, 3422 UIPROTO_FSHUB, 3423 0 3424 }; 3425 3426 const usb_endpoint_descriptor_t uhci_endpd = { 3427 USB_ENDPOINT_DESCRIPTOR_SIZE, 3428 UDESC_ENDPOINT, 3429 UE_DIR_IN | UHCI_INTR_ENDPT, 3430 UE_INTERRUPT, 3431 {8}, 3432 255 3433 }; 3434 3435 const usb_hub_descriptor_t uhci_hubd_piix = { 3436 USB_HUB_DESCRIPTOR_SIZE, 3437 UDESC_HUB, 3438 2, 3439 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3440 50, /* power on to power good */ 3441 0, 3442 { 0x00 }, /* both ports are removable */ 3443 { 0 }, 3444 }; 3445 3446 /* 3447 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3448 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3449 * should not be used by the USB subsystem. As we cannot issue a 3450 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3451 * will be enabled as part of the reset. 3452 * 3453 * On the VT83C572, the port cannot be successfully enabled until the 3454 * outstanding "port enable change" and "connection status change" 3455 * events have been reset. 3456 */ 3457 Static usbd_status 3458 uhci_portreset(uhci_softc_t *sc, int index) 3459 { 3460 int lim, port, x; 3461 3462 if (index == 1) 3463 port = UHCI_PORTSC1; 3464 else if (index == 2) 3465 port = UHCI_PORTSC2; 3466 else 3467 return (USBD_IOERROR); 3468 3469 x = URWMASK(UREAD2(sc, port)); 3470 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3471 3472 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3473 3474 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3475 index, UREAD2(sc, port))); 3476 3477 x = URWMASK(UREAD2(sc, port)); 3478 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3479 3480 delay(100); 3481 3482 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3483 index, UREAD2(sc, port))); 3484 3485 x = URWMASK(UREAD2(sc, port)); 3486 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3487 3488 for (lim = 10; --lim > 0;) { 3489 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3490 3491 x = UREAD2(sc, port); 3492 3493 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3494 index, lim, x)); 3495 3496 if (!(x & UHCI_PORTSC_CCS)) { 3497 /* 3498 * No device is connected (or was disconnected 3499 * during reset). Consider the port reset. 3500 * The delay must be long enough to ensure on 3501 * the initial iteration that the device 3502 * connection will have been registered. 50ms 3503 * appears to be sufficient, but 20ms is not. 3504 */ 3505 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3506 index, lim)); 3507 break; 3508 } 3509 3510 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3511 /* 3512 * Port enabled changed and/or connection 3513 * status changed were set. Reset either or 3514 * both raised flags (by writing a 1 to that 3515 * bit), and wait again for state to settle. 3516 */ 3517 UWRITE2(sc, port, URWMASK(x) | 3518 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3519 continue; 3520 } 3521 3522 if (x & UHCI_PORTSC_PE) 3523 /* Port is enabled */ 3524 break; 3525 3526 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3527 } 3528 3529 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3530 index, UREAD2(sc, port))); 3531 3532 if (lim <= 0) { 3533 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3534 return (USBD_TIMEOUT); 3535 } 3536 3537 sc->sc_isreset = 1; 3538 return (USBD_NORMAL_COMPLETION); 3539 } 3540 3541 /* 3542 * Simulate a hardware hub by handling all the necessary requests. 3543 */ 3544 usbd_status 3545 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3546 { 3547 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3548 usbd_status err; 3549 3550 /* Insert last in queue. */ 3551 mutex_enter(&sc->sc_lock); 3552 err = usb_insert_transfer(xfer); 3553 mutex_exit(&sc->sc_lock); 3554 if (err) 3555 return (err); 3556 3557 /* 3558 * Pipe isn't running (otherwise err would be USBD_INPROG), 3559 * so start it first. 3560 */ 3561 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3562 } 3563 3564 usbd_status 3565 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3566 { 3567 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3568 usb_device_request_t *req; 3569 void *buf = NULL; 3570 int port, x; 3571 int len, value, index, status, change, l, totlen = 0; 3572 usb_port_status_t ps; 3573 usbd_status err; 3574 3575 if (sc->sc_dying) 3576 return (USBD_IOERROR); 3577 3578 #ifdef DIAGNOSTIC 3579 if (!(xfer->rqflags & URQ_REQUEST)) 3580 panic("uhci_root_ctrl_start: not a request"); 3581 #endif 3582 req = &xfer->request; 3583 3584 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3585 req->bmRequestType, req->bRequest)); 3586 3587 len = UGETW(req->wLength); 3588 value = UGETW(req->wValue); 3589 index = UGETW(req->wIndex); 3590 3591 if (len != 0) 3592 buf = KERNADDR(&xfer->dmabuf, 0); 3593 3594 #define C(x,y) ((x) | ((y) << 8)) 3595 switch(C(req->bRequest, req->bmRequestType)) { 3596 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3597 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3598 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3599 /* 3600 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3601 * for the integrated root hub. 3602 */ 3603 break; 3604 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3605 if (len > 0) { 3606 *(u_int8_t *)buf = sc->sc_conf; 3607 totlen = 1; 3608 } 3609 break; 3610 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3611 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3612 if (len == 0) 3613 break; 3614 switch(value >> 8) { 3615 case UDESC_DEVICE: 3616 if ((value & 0xff) != 0) { 3617 err = USBD_IOERROR; 3618 goto ret; 3619 } 3620 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3621 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3622 memcpy(buf, &uhci_devd, l); 3623 break; 3624 case UDESC_CONFIG: 3625 if ((value & 0xff) != 0) { 3626 err = USBD_IOERROR; 3627 goto ret; 3628 } 3629 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3630 memcpy(buf, &uhci_confd, l); 3631 buf = (char *)buf + l; 3632 len -= l; 3633 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3634 totlen += l; 3635 memcpy(buf, &uhci_ifcd, l); 3636 buf = (char *)buf + l; 3637 len -= l; 3638 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3639 totlen += l; 3640 memcpy(buf, &uhci_endpd, l); 3641 break; 3642 case UDESC_STRING: 3643 #define sd ((usb_string_descriptor_t *)buf) 3644 switch (value & 0xff) { 3645 case 0: /* Language table */ 3646 totlen = usb_makelangtbl(sd, len); 3647 break; 3648 case 1: /* Vendor */ 3649 totlen = usb_makestrdesc(sd, len, 3650 sc->sc_vendor); 3651 break; 3652 case 2: /* Product */ 3653 totlen = usb_makestrdesc(sd, len, 3654 "UHCI root hub"); 3655 break; 3656 } 3657 #undef sd 3658 break; 3659 default: 3660 err = USBD_IOERROR; 3661 goto ret; 3662 } 3663 break; 3664 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3665 if (len > 0) { 3666 *(u_int8_t *)buf = 0; 3667 totlen = 1; 3668 } 3669 break; 3670 case C(UR_GET_STATUS, UT_READ_DEVICE): 3671 if (len > 1) { 3672 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3673 totlen = 2; 3674 } 3675 break; 3676 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3677 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3678 if (len > 1) { 3679 USETW(((usb_status_t *)buf)->wStatus, 0); 3680 totlen = 2; 3681 } 3682 break; 3683 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3684 if (value >= USB_MAX_DEVICES) { 3685 err = USBD_IOERROR; 3686 goto ret; 3687 } 3688 sc->sc_addr = value; 3689 break; 3690 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3691 if (value != 0 && value != 1) { 3692 err = USBD_IOERROR; 3693 goto ret; 3694 } 3695 sc->sc_conf = value; 3696 break; 3697 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3698 break; 3699 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3700 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3701 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3702 err = USBD_IOERROR; 3703 goto ret; 3704 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3705 break; 3706 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3707 break; 3708 /* Hub requests */ 3709 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3710 break; 3711 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3712 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3713 "port=%d feature=%d\n", 3714 index, value)); 3715 if (index == 1) 3716 port = UHCI_PORTSC1; 3717 else if (index == 2) 3718 port = UHCI_PORTSC2; 3719 else { 3720 err = USBD_IOERROR; 3721 goto ret; 3722 } 3723 switch(value) { 3724 case UHF_PORT_ENABLE: 3725 x = URWMASK(UREAD2(sc, port)); 3726 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3727 break; 3728 case UHF_PORT_SUSPEND: 3729 x = URWMASK(UREAD2(sc, port)); 3730 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3731 break; 3732 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3733 /* see USB2 spec ch. 7.1.7.7 */ 3734 usb_delay_ms(&sc->sc_bus, 20); 3735 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3736 /* 10ms resume delay must be provided by caller */ 3737 break; 3738 case UHF_PORT_RESET: 3739 x = URWMASK(UREAD2(sc, port)); 3740 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3741 break; 3742 case UHF_C_PORT_CONNECTION: 3743 x = URWMASK(UREAD2(sc, port)); 3744 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3745 break; 3746 case UHF_C_PORT_ENABLE: 3747 x = URWMASK(UREAD2(sc, port)); 3748 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3749 break; 3750 case UHF_C_PORT_OVER_CURRENT: 3751 x = URWMASK(UREAD2(sc, port)); 3752 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3753 break; 3754 case UHF_C_PORT_RESET: 3755 sc->sc_isreset = 0; 3756 err = USBD_NORMAL_COMPLETION; 3757 goto ret; 3758 case UHF_PORT_CONNECTION: 3759 case UHF_PORT_OVER_CURRENT: 3760 case UHF_PORT_POWER: 3761 case UHF_PORT_LOW_SPEED: 3762 case UHF_C_PORT_SUSPEND: 3763 default: 3764 err = USBD_IOERROR; 3765 goto ret; 3766 } 3767 break; 3768 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3769 if (index == 1) 3770 port = UHCI_PORTSC1; 3771 else if (index == 2) 3772 port = UHCI_PORTSC2; 3773 else { 3774 err = USBD_IOERROR; 3775 goto ret; 3776 } 3777 if (len > 0) { 3778 *(u_int8_t *)buf = 3779 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3780 UHCI_PORTSC_LS_SHIFT; 3781 totlen = 1; 3782 } 3783 break; 3784 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3785 if (len == 0) 3786 break; 3787 if ((value & 0xff) != 0) { 3788 err = USBD_IOERROR; 3789 goto ret; 3790 } 3791 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3792 totlen = l; 3793 memcpy(buf, &uhci_hubd_piix, l); 3794 break; 3795 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3796 if (len != 4) { 3797 err = USBD_IOERROR; 3798 goto ret; 3799 } 3800 memset(buf, 0, len); 3801 totlen = len; 3802 break; 3803 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3804 if (index == 1) 3805 port = UHCI_PORTSC1; 3806 else if (index == 2) 3807 port = UHCI_PORTSC2; 3808 else { 3809 err = USBD_IOERROR; 3810 goto ret; 3811 } 3812 if (len != 4) { 3813 err = USBD_IOERROR; 3814 goto ret; 3815 } 3816 x = UREAD2(sc, port); 3817 status = change = 0; 3818 if (x & UHCI_PORTSC_CCS) 3819 status |= UPS_CURRENT_CONNECT_STATUS; 3820 if (x & UHCI_PORTSC_CSC) 3821 change |= UPS_C_CONNECT_STATUS; 3822 if (x & UHCI_PORTSC_PE) 3823 status |= UPS_PORT_ENABLED; 3824 if (x & UHCI_PORTSC_POEDC) 3825 change |= UPS_C_PORT_ENABLED; 3826 if (x & UHCI_PORTSC_OCI) 3827 status |= UPS_OVERCURRENT_INDICATOR; 3828 if (x & UHCI_PORTSC_OCIC) 3829 change |= UPS_C_OVERCURRENT_INDICATOR; 3830 if (x & UHCI_PORTSC_SUSP) 3831 status |= UPS_SUSPEND; 3832 if (x & UHCI_PORTSC_LSDA) 3833 status |= UPS_LOW_SPEED; 3834 status |= UPS_PORT_POWER; 3835 if (sc->sc_isreset) 3836 change |= UPS_C_PORT_RESET; 3837 USETW(ps.wPortStatus, status); 3838 USETW(ps.wPortChange, change); 3839 l = min(len, sizeof ps); 3840 memcpy(buf, &ps, l); 3841 totlen = l; 3842 break; 3843 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3844 err = USBD_IOERROR; 3845 goto ret; 3846 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3847 break; 3848 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3849 if (index == 1) 3850 port = UHCI_PORTSC1; 3851 else if (index == 2) 3852 port = UHCI_PORTSC2; 3853 else { 3854 err = USBD_IOERROR; 3855 goto ret; 3856 } 3857 switch(value) { 3858 case UHF_PORT_ENABLE: 3859 x = URWMASK(UREAD2(sc, port)); 3860 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3861 break; 3862 case UHF_PORT_SUSPEND: 3863 x = URWMASK(UREAD2(sc, port)); 3864 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3865 break; 3866 case UHF_PORT_RESET: 3867 err = uhci_portreset(sc, index); 3868 goto ret; 3869 case UHF_PORT_POWER: 3870 /* Pretend we turned on power */ 3871 err = USBD_NORMAL_COMPLETION; 3872 goto ret; 3873 case UHF_C_PORT_CONNECTION: 3874 case UHF_C_PORT_ENABLE: 3875 case UHF_C_PORT_OVER_CURRENT: 3876 case UHF_PORT_CONNECTION: 3877 case UHF_PORT_OVER_CURRENT: 3878 case UHF_PORT_LOW_SPEED: 3879 case UHF_C_PORT_SUSPEND: 3880 case UHF_C_PORT_RESET: 3881 default: 3882 err = USBD_IOERROR; 3883 goto ret; 3884 } 3885 break; 3886 default: 3887 err = USBD_IOERROR; 3888 goto ret; 3889 } 3890 xfer->actlen = totlen; 3891 err = USBD_NORMAL_COMPLETION; 3892 ret: 3893 xfer->status = err; 3894 mutex_enter(&sc->sc_lock); 3895 usb_transfer_complete(xfer); 3896 mutex_exit(&sc->sc_lock); 3897 return (USBD_IN_PROGRESS); 3898 } 3899 3900 /* Abort a root control request. */ 3901 void 3902 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3903 { 3904 /* Nothing to do, all transfers are synchronous. */ 3905 } 3906 3907 /* Close the root pipe. */ 3908 void 3909 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3910 { 3911 DPRINTF(("uhci_root_ctrl_close\n")); 3912 } 3913 3914 /* Abort a root interrupt request. */ 3915 void 3916 uhci_root_intr_abort(usbd_xfer_handle xfer) 3917 { 3918 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3919 3920 KASSERT(mutex_owned(&sc->sc_lock)); 3921 KASSERT(xfer->pipe->intrxfer == xfer); 3922 3923 callout_stop(&sc->sc_poll_handle); 3924 sc->sc_intr_xfer = NULL; 3925 3926 xfer->status = USBD_CANCELLED; 3927 #ifdef DIAGNOSTIC 3928 UXFER(xfer)->iinfo.isdone = 1; 3929 #endif 3930 usb_transfer_complete(xfer); 3931 } 3932 3933 usbd_status 3934 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3935 { 3936 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3937 usbd_status err; 3938 3939 /* Insert last in queue. */ 3940 mutex_enter(&sc->sc_lock); 3941 err = usb_insert_transfer(xfer); 3942 mutex_exit(&sc->sc_lock); 3943 if (err) 3944 return (err); 3945 3946 /* 3947 * Pipe isn't running (otherwise err would be USBD_INPROG), 3948 * start first 3949 */ 3950 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3951 } 3952 3953 /* Start a transfer on the root interrupt pipe */ 3954 usbd_status 3955 uhci_root_intr_start(usbd_xfer_handle xfer) 3956 { 3957 usbd_pipe_handle pipe = xfer->pipe; 3958 uhci_softc_t *sc = pipe->device->bus->hci_private; 3959 unsigned int ival; 3960 3961 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3962 xfer, xfer->length, xfer->flags)); 3963 3964 if (sc->sc_dying) 3965 return (USBD_IOERROR); 3966 3967 /* XXX temporary variable needed to avoid gcc3 warning */ 3968 ival = xfer->pipe->endpoint->edesc->bInterval; 3969 sc->sc_ival = mstohz(ival); 3970 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3971 sc->sc_intr_xfer = xfer; 3972 return (USBD_IN_PROGRESS); 3973 } 3974 3975 /* Close the root interrupt pipe. */ 3976 void 3977 uhci_root_intr_close(usbd_pipe_handle pipe) 3978 { 3979 uhci_softc_t *sc = pipe->device->bus->hci_private; 3980 3981 KASSERT(mutex_owned(&sc->sc_lock)); 3982 3983 callout_stop(&sc->sc_poll_handle); 3984 sc->sc_intr_xfer = NULL; 3985 DPRINTF(("uhci_root_intr_close\n")); 3986 } 3987
Indexes created Tue Sep 30 17:09:57 GMT 2025