uhci.c revision 1.264.4.11
1 /* $NetBSD: uhci.c,v 1.264.4.11 2014/12/03 23:05:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.11 2014/12/03 23:05:06 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run, int locked); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 169 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 170 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 171 172 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 173 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 174 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 175 Static void uhci_device_ctrl_close(usbd_pipe_handle); 176 Static void uhci_device_ctrl_done(usbd_xfer_handle); 177 178 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 179 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 180 Static void uhci_device_intr_abort(usbd_xfer_handle); 181 Static void uhci_device_intr_close(usbd_pipe_handle); 182 Static void uhci_device_intr_done(usbd_xfer_handle); 183 184 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 185 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 186 Static void uhci_device_bulk_abort(usbd_xfer_handle); 187 Static void uhci_device_bulk_close(usbd_pipe_handle); 188 Static void uhci_device_bulk_done(usbd_xfer_handle); 189 190 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 191 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 192 Static void uhci_device_isoc_abort(usbd_xfer_handle); 193 Static void uhci_device_isoc_close(usbd_pipe_handle); 194 Static void uhci_device_isoc_done(usbd_xfer_handle); 195 196 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 197 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 198 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 199 Static void uhci_root_ctrl_close(usbd_pipe_handle); 200 Static void uhci_root_ctrl_done(usbd_xfer_handle); 201 202 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 203 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 204 Static void uhci_root_intr_abort(usbd_xfer_handle); 205 Static void uhci_root_intr_close(usbd_pipe_handle); 206 Static void uhci_root_intr_done(usbd_xfer_handle); 207 208 Static usbd_status uhci_open(usbd_pipe_handle); 209 Static void uhci_poll(struct usbd_bus *); 210 Static void uhci_softintr(void *); 211 212 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 213 214 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 215 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 216 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 217 struct uhci_pipe *pipe, int ival); 218 219 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 220 Static void uhci_noop(usbd_pipe_handle pipe); 221 222 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 223 uhci_soft_qh_t *); 224 225 #ifdef UHCI_DEBUG 226 Static void uhci_dump_all(uhci_softc_t *); 227 Static void uhci_dumpregs(uhci_softc_t *); 228 Static void uhci_dump_qhs(uhci_soft_qh_t *); 229 Static void uhci_dump_qh(uhci_soft_qh_t *); 230 Static void uhci_dump_tds(uhci_soft_td_t *); 231 Static void uhci_dump_td(uhci_soft_td_t *); 232 Static void uhci_dump_ii(uhci_intr_info_t *ii); 233 void uhci_dump(void); 234 #endif 235 236 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 237 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 238 #define UWRITE1(sc, r, x) \ 239 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 240 } while (/*CONSTCOND*/0) 241 #define UWRITE2(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE4(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 static __inline uint8_t 248 UREAD1(uhci_softc_t *sc, bus_size_t r) 249 { 250 251 UBARR(sc); 252 return bus_space_read_1(sc->iot, sc->ioh, r); 253 } 254 255 static __inline uint16_t 256 UREAD2(uhci_softc_t *sc, bus_size_t r) 257 { 258 259 UBARR(sc); 260 return bus_space_read_2(sc->iot, sc->ioh, r); 261 } 262 263 #ifdef UHCI_DEBUG 264 static __inline uint32_t 265 UREAD4(uhci_softc_t *sc, bus_size_t r) 266 { 267 268 UBARR(sc); 269 return bus_space_read_4(sc->iot, sc->ioh, r); 270 } 271 #endif 272 273 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 274 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 275 276 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 277 278 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 279 280 #define UHCI_INTR_ENDPT 1 281 282 const struct usbd_bus_methods uhci_bus_methods = { 283 .ubm_open = uhci_open, 284 .ubm_softint = uhci_softintr, 285 .ubm_dopoll = uhci_poll, 286 .ubm_allocx = uhci_allocx, 287 .ubm_freex = uhci_freex, 288 .ubm_getlock = uhci_get_lock, 289 .ubm_newdev = NULL, 290 }; 291 292 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 293 .upm_transfer = uhci_root_ctrl_transfer, 294 .upm_start = uhci_root_ctrl_start, 295 .upm_abort = uhci_root_ctrl_abort, 296 .upm_close = uhci_root_ctrl_close, 297 .upm_cleartoggle = uhci_noop, 298 .upm_done = uhci_root_ctrl_done, 299 }; 300 301 const struct usbd_pipe_methods uhci_root_intr_methods = { 302 .upm_transfer = uhci_root_intr_transfer, 303 .upm_start = uhci_root_intr_start, 304 .upm_abort = uhci_root_intr_abort, 305 .upm_close = uhci_root_intr_close, 306 .upm_cleartoggle = uhci_noop, 307 .upm_done = uhci_root_intr_done, 308 }; 309 310 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 311 .upm_transfer = uhci_device_ctrl_transfer, 312 .upm_start = uhci_device_ctrl_start, 313 .upm_abort = uhci_device_ctrl_abort, 314 .upm_close = uhci_device_ctrl_close, 315 .upm_cleartoggle = uhci_noop, 316 .upm_done = uhci_device_ctrl_done, 317 }; 318 319 const struct usbd_pipe_methods uhci_device_intr_methods = { 320 .upm_transfer = uhci_device_intr_transfer, 321 .upm_start = uhci_device_intr_start, 322 .upm_abort = uhci_device_intr_abort, 323 .upm_close = uhci_device_intr_close, 324 .upm_cleartoggle = uhci_device_clear_toggle, 325 .upm_done = uhci_device_intr_done, 326 }; 327 328 const struct usbd_pipe_methods uhci_device_bulk_methods = { 329 .upm_transfer = uhci_device_bulk_transfer, 330 .upm_start = uhci_device_bulk_start, 331 .upm_abort = uhci_device_bulk_abort, 332 .upm_close = uhci_device_bulk_close, 333 .upm_cleartoggle = uhci_device_clear_toggle, 334 .upm_done = uhci_device_bulk_done, 335 }; 336 337 const struct usbd_pipe_methods uhci_device_isoc_methods = { 338 .upm_transfer = uhci_device_isoc_transfer, 339 .upm_start = uhci_device_isoc_start, 340 .upm_abort = uhci_device_isoc_abort, 341 .upm_close = uhci_device_isoc_close, 342 .upm_cleartoggle = uhci_noop, 343 .upm_done = uhci_device_isoc_done, 344 }; 345 346 #define uhci_add_intr_info(sc, ii) \ 347 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 348 #define uhci_del_intr_info(ii) \ 349 do { \ 350 LIST_REMOVE((ii), list); \ 351 (ii)->list.le_prev = NULL; \ 352 } while (0) 353 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 354 355 static inline uhci_soft_qh_t * 356 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 357 { 358 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 359 360 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 361 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 362 usb_syncmem(&pqh->dma, 363 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 364 sizeof(pqh->qh.qh_hlink), 365 BUS_DMASYNC_POSTWRITE); 366 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 367 printf("uhci_find_prev_qh: QH not found\n"); 368 return (NULL); 369 } 370 #endif 371 } 372 return (pqh); 373 } 374 375 void 376 uhci_globalreset(uhci_softc_t *sc) 377 { 378 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 379 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 380 UHCICMD(sc, 0); /* do nothing */ 381 } 382 383 usbd_status 384 uhci_init(uhci_softc_t *sc) 385 { 386 usbd_status err; 387 int i, j; 388 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 389 uhci_soft_td_t *std; 390 391 DPRINTFN(1,("uhci_init: start\n")); 392 393 #ifdef UHCI_DEBUG 394 thesc = sc; 395 396 if (uhcidebug > 2) 397 uhci_dumpregs(sc); 398 #endif 399 400 sc->sc_suspend = PWR_RESUME; 401 402 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 403 uhci_globalreset(sc); /* reset the controller */ 404 uhci_reset(sc); 405 406 /* Allocate and initialize real frame array. */ 407 err = usb_allocmem(&sc->sc_bus, 408 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 409 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 410 if (err) 411 return (err); 412 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 413 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 414 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 415 416 /* 417 * Allocate a TD, inactive, that hangs from the last QH. 418 * This is to avoid a bug in the PIIX that makes it run berserk 419 * otherwise. 420 */ 421 std = uhci_alloc_std(sc); 422 if (std == NULL) 423 return (USBD_NOMEM); 424 std->link.std = NULL; 425 std->td.td_link = htole32(UHCI_PTR_T); 426 std->td.td_status = htole32(0); /* inactive */ 427 std->td.td_token = htole32(0); 428 std->td.td_buffer = htole32(0); 429 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 430 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 431 432 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 433 lsqh = uhci_alloc_sqh(sc); 434 if (lsqh == NULL) 435 return (USBD_NOMEM); 436 lsqh->hlink = NULL; 437 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 438 lsqh->elink = std; 439 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 440 sc->sc_last_qh = lsqh; 441 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 442 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 443 444 /* Allocate the dummy QH where bulk traffic will be queued. */ 445 bsqh = uhci_alloc_sqh(sc); 446 if (bsqh == NULL) 447 return (USBD_NOMEM); 448 bsqh->hlink = lsqh; 449 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 450 bsqh->elink = NULL; 451 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 452 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 453 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 455 456 /* Allocate dummy QH where high speed control traffic will be queued. */ 457 chsqh = uhci_alloc_sqh(sc); 458 if (chsqh == NULL) 459 return (USBD_NOMEM); 460 chsqh->hlink = bsqh; 461 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 462 chsqh->elink = NULL; 463 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 464 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 465 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 467 468 /* Allocate dummy QH where control traffic will be queued. */ 469 clsqh = uhci_alloc_sqh(sc); 470 if (clsqh == NULL) 471 return (USBD_NOMEM); 472 clsqh->hlink = chsqh; 473 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 474 clsqh->elink = NULL; 475 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 476 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 477 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 479 480 /* 481 * Make all (virtual) frame list pointers point to the interrupt 482 * queue heads and the interrupt queue heads at the control 483 * queue head and point the physical frame list to the virtual. 484 */ 485 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 486 std = uhci_alloc_std(sc); 487 sqh = uhci_alloc_sqh(sc); 488 if (std == NULL || sqh == NULL) 489 return (USBD_NOMEM); 490 std->link.sqh = sqh; 491 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 492 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 493 std->td.td_token = htole32(0); 494 std->td.td_buffer = htole32(0); 495 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 496 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 497 sqh->hlink = clsqh; 498 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 499 sqh->elink = NULL; 500 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 501 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 sc->sc_vframes[i].htd = std; 504 sc->sc_vframes[i].etd = std; 505 sc->sc_vframes[i].hqh = sqh; 506 sc->sc_vframes[i].eqh = sqh; 507 for (j = i; 508 j < UHCI_FRAMELIST_COUNT; 509 j += UHCI_VFRAMELIST_COUNT) 510 sc->sc_pframes[j] = htole32(std->physaddr); 511 } 512 usb_syncmem(&sc->sc_dma, 0, 513 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 514 BUS_DMASYNC_PREWRITE); 515 516 517 LIST_INIT(&sc->sc_intrhead); 518 519 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 520 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 521 522 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 523 524 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 525 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 526 cv_init(&sc->sc_softwake_cv, "uhciab"); 527 528 /* Set up the bus struct. */ 529 sc->sc_bus.ub_methods = &uhci_bus_methods; 530 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 531 sc->sc_bus.ub_usedma = true; 532 533 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 534 535 DPRINTFN(1,("uhci_init: enabling\n")); 536 537 err = uhci_run(sc, 1, 0); /* and here we go... */ 538 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 539 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 540 return err; 541 } 542 543 int 544 uhci_activate(device_t self, enum devact act) 545 { 546 struct uhci_softc *sc = device_private(self); 547 548 switch (act) { 549 case DVACT_DEACTIVATE: 550 sc->sc_dying = 1; 551 return 0; 552 default: 553 return EOPNOTSUPP; 554 } 555 } 556 557 void 558 uhci_childdet(device_t self, device_t child) 559 { 560 struct uhci_softc *sc = device_private(self); 561 562 KASSERT(sc->sc_child == child); 563 sc->sc_child = NULL; 564 } 565 566 int 567 uhci_detach(struct uhci_softc *sc, int flags) 568 { 569 int rv = 0; 570 571 if (sc->sc_child != NULL) 572 rv = config_detach(sc->sc_child, flags); 573 574 if (rv != 0) 575 return (rv); 576 577 callout_halt(&sc->sc_poll_handle, NULL); 578 callout_destroy(&sc->sc_poll_handle); 579 580 cv_destroy(&sc->sc_softwake_cv); 581 582 mutex_destroy(&sc->sc_lock); 583 mutex_destroy(&sc->sc_intr_lock); 584 585 pool_cache_destroy(sc->sc_xferpool); 586 587 /* XXX free other data structures XXX */ 588 589 return (rv); 590 } 591 592 usbd_xfer_handle 593 uhci_allocx(struct usbd_bus *bus) 594 { 595 struct uhci_softc *sc = bus->ub_hcpriv; 596 usbd_xfer_handle xfer; 597 598 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 599 if (xfer != NULL) { 600 memset(xfer, 0, sizeof(struct uhci_xfer)); 601 UXFER(xfer)->iinfo.sc = sc; 602 #ifdef DIAGNOSTIC 603 UXFER(xfer)->iinfo.isdone = 1; 604 xfer->ux_state = XFER_BUSY; 605 #endif 606 } 607 return (xfer); 608 } 609 610 void 611 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 612 { 613 struct uhci_softc *sc = bus->ub_hcpriv; 614 615 #ifdef DIAGNOSTIC 616 if (xfer->ux_state != XFER_BUSY) { 617 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 618 xfer->ux_state); 619 } 620 xfer->ux_state = XFER_FREE; 621 if (!UXFER(xfer)->iinfo.isdone) { 622 printf("uhci_freex: !isdone\n"); 623 } 624 #endif 625 pool_cache_put(sc->sc_xferpool, xfer); 626 } 627 628 Static void 629 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 630 { 631 struct uhci_softc *sc = bus->ub_hcpriv; 632 633 *lock = &sc->sc_lock; 634 } 635 636 637 /* 638 * Handle suspend/resume. 639 * 640 * We need to switch to polling mode here, because this routine is 641 * called from an interrupt context. This is all right since we 642 * are almost suspended anyway. 643 */ 644 bool 645 uhci_resume(device_t dv, const pmf_qual_t *qual) 646 { 647 uhci_softc_t *sc = device_private(dv); 648 int cmd; 649 650 mutex_spin_enter(&sc->sc_intr_lock); 651 652 cmd = UREAD2(sc, UHCI_CMD); 653 sc->sc_bus.ub_usepolling++; 654 UWRITE2(sc, UHCI_INTR, 0); 655 uhci_globalreset(sc); 656 uhci_reset(sc); 657 if (cmd & UHCI_CMD_RS) 658 uhci_run(sc, 0, 1); 659 660 /* restore saved state */ 661 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 662 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 663 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 664 665 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 666 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 667 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 668 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 669 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 670 UHCICMD(sc, UHCI_CMD_MAXP); 671 uhci_run(sc, 1, 1); /* and start traffic again */ 672 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 673 sc->sc_bus.ub_usepolling--; 674 if (sc->sc_intr_xfer != NULL) 675 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 676 sc->sc_intr_xfer); 677 #ifdef UHCI_DEBUG 678 if (uhcidebug > 2) 679 uhci_dumpregs(sc); 680 #endif 681 682 sc->sc_suspend = PWR_RESUME; 683 mutex_spin_exit(&sc->sc_intr_lock); 684 685 return true; 686 } 687 688 bool 689 uhci_suspend(device_t dv, const pmf_qual_t *qual) 690 { 691 uhci_softc_t *sc = device_private(dv); 692 int cmd; 693 694 mutex_spin_enter(&sc->sc_intr_lock); 695 696 cmd = UREAD2(sc, UHCI_CMD); 697 698 #ifdef UHCI_DEBUG 699 if (uhcidebug > 2) 700 uhci_dumpregs(sc); 701 #endif 702 if (sc->sc_intr_xfer != NULL) 703 callout_stop(&sc->sc_poll_handle); 704 sc->sc_suspend = PWR_SUSPEND; 705 sc->sc_bus.ub_usepolling++; 706 707 uhci_run(sc, 0, 1); /* stop the controller */ 708 cmd &= ~UHCI_CMD_RS; 709 710 /* save some state if BIOS doesn't */ 711 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 712 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 713 714 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 715 716 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 717 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 718 sc->sc_bus.ub_usepolling--; 719 720 mutex_spin_exit(&sc->sc_intr_lock); 721 722 return true; 723 } 724 725 #ifdef UHCI_DEBUG 726 Static void 727 uhci_dumpregs(uhci_softc_t *sc) 728 { 729 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 730 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 731 device_xname(sc->sc_dev), 732 UREAD2(sc, UHCI_CMD), 733 UREAD2(sc, UHCI_STS), 734 UREAD2(sc, UHCI_INTR), 735 UREAD2(sc, UHCI_FRNUM), 736 UREAD4(sc, UHCI_FLBASEADDR), 737 UREAD1(sc, UHCI_SOF), 738 UREAD2(sc, UHCI_PORTSC1), 739 UREAD2(sc, UHCI_PORTSC2))); 740 } 741 742 void 743 uhci_dump_td(uhci_soft_td_t *p) 744 { 745 char sbuf[128], sbuf2[128]; 746 747 748 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 749 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 750 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 751 "token=0x%08lx buffer=0x%08lx\n", 752 p, (long)p->physaddr, 753 (long)le32toh(p->td.td_link), 754 (long)le32toh(p->td.td_status), 755 (long)le32toh(p->td.td_token), 756 (long)le32toh(p->td.td_buffer))); 757 758 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 759 (uint32_t)le32toh(p->td.td_link)); 760 snprintb(sbuf2, sizeof(sbuf2), 761 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 762 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 763 (uint32_t)le32toh(p->td.td_status)); 764 765 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 766 "D=%d,maxlen=%d\n", sbuf, sbuf2, 767 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 768 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 769 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 770 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 771 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 772 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 773 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 774 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 775 BUS_DMASYNC_PREREAD); 776 } 777 778 void 779 uhci_dump_qh(uhci_soft_qh_t *sqh) 780 { 781 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 782 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 783 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 784 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 785 le32toh(sqh->qh.qh_elink))); 786 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 787 } 788 789 790 #if 1 791 void 792 uhci_dump(void) 793 { 794 uhci_dump_all(thesc); 795 } 796 #endif 797 798 void 799 uhci_dump_all(uhci_softc_t *sc) 800 { 801 uhci_dumpregs(sc); 802 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 803 uhci_dump_qhs(sc->sc_lctl_start); 804 } 805 806 807 void 808 uhci_dump_qhs(uhci_soft_qh_t *sqh) 809 { 810 uhci_dump_qh(sqh); 811 812 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 813 * Traverses sideways first, then down. 814 * 815 * QH1 816 * QH2 817 * No QH 818 * TD2.1 819 * TD2.2 820 * TD1.1 821 * etc. 822 * 823 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 824 */ 825 826 827 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 828 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 829 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 830 uhci_dump_qhs(sqh->hlink); 831 else 832 DPRINTF(("No QH\n")); 833 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 834 835 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 836 uhci_dump_tds(sqh->elink); 837 else 838 DPRINTF(("No TD\n")); 839 } 840 841 void 842 uhci_dump_tds(uhci_soft_td_t *std) 843 { 844 uhci_soft_td_t *td; 845 int stop; 846 847 for(td = std; td != NULL; td = td->link.std) { 848 uhci_dump_td(td); 849 850 /* Check whether the link pointer in this TD marks 851 * the link pointer as end of queue. This avoids 852 * printing the free list in case the queue/TD has 853 * already been moved there (seatbelt). 854 */ 855 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 856 sizeof(td->td.td_link), 857 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 858 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 859 le32toh(td->td.td_link) == 0); 860 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 861 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 862 if (stop) 863 break; 864 } 865 } 866 867 Static void 868 uhci_dump_ii(uhci_intr_info_t *ii) 869 { 870 usbd_pipe_handle pipe; 871 usb_endpoint_descriptor_t *ed; 872 usbd_device_handle dev; 873 874 #ifdef DIAGNOSTIC 875 #define DONE ii->isdone 876 #else 877 #define DONE 0 878 #endif 879 if (ii == NULL) { 880 printf("ii NULL\n"); 881 return; 882 } 883 if (ii->xfer == NULL) { 884 printf("ii %p: done=%d xfer=NULL\n", 885 ii, DONE); 886 return; 887 } 888 pipe = ii->xfer->ux_pipe; 889 if (pipe == NULL) { 890 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 891 ii, DONE, ii->xfer); 892 return; 893 } 894 if (pipe->up_endpoint == NULL) { 895 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 896 ii, DONE, ii->xfer, pipe); 897 return; 898 } 899 if (pipe->up_dev == NULL) { 900 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 901 ii, DONE, ii->xfer, pipe); 902 return; 903 } 904 ed = pipe->up_endpoint->ue_edesc; 905 dev = pipe->up_dev; 906 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 907 ii, DONE, ii->xfer, dev, 908 UGETW(dev->ud_ddesc.idVendor), 909 UGETW(dev->ud_ddesc.idProduct), 910 dev->ud_addr, pipe, 911 ed->bEndpointAddress, ed->bmAttributes); 912 #undef DONE 913 } 914 915 void uhci_dump_iis(struct uhci_softc *sc); 916 void 917 uhci_dump_iis(struct uhci_softc *sc) 918 { 919 uhci_intr_info_t *ii; 920 921 printf("intr_info list:\n"); 922 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 923 uhci_dump_ii(ii); 924 } 925 926 void iidump(void); 927 void iidump(void) { uhci_dump_iis(thesc); } 928 929 #endif 930 931 /* 932 * This routine is executed periodically and simulates interrupts 933 * from the root controller interrupt pipe for port status change. 934 */ 935 void 936 uhci_poll_hub(void *addr) 937 { 938 usbd_xfer_handle xfer = addr; 939 usbd_pipe_handle pipe = xfer->ux_pipe; 940 uhci_softc_t *sc; 941 u_char *p; 942 943 DPRINTFN(20, ("uhci_poll_hub\n")); 944 945 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 946 return; /* device has detached */ 947 sc = pipe->up_dev->ud_bus->ub_hcpriv; 948 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 949 950 p = xfer->ux_buf; 951 p[0] = 0; 952 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 953 p[0] |= 1<<1; 954 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 955 p[0] |= 1<<2; 956 if (p[0] == 0) 957 /* No change, try again in a while */ 958 return; 959 960 xfer->ux_actlen = 1; 961 xfer->ux_status = USBD_NORMAL_COMPLETION; 962 mutex_enter(&sc->sc_lock); 963 usb_transfer_complete(xfer); 964 mutex_exit(&sc->sc_lock); 965 } 966 967 void 968 uhci_root_intr_done(usbd_xfer_handle xfer) 969 { 970 } 971 972 void 973 uhci_root_ctrl_done(usbd_xfer_handle xfer) 974 { 975 } 976 977 /* 978 * Let the last QH loop back to the high speed control transfer QH. 979 * This is what intel calls "bandwidth reclamation" and improves 980 * USB performance a lot for some devices. 981 * If we are already looping, just count it. 982 */ 983 void 984 uhci_add_loop(uhci_softc_t *sc) { 985 #ifdef UHCI_DEBUG 986 if (uhcinoloop) 987 return; 988 #endif 989 if (++sc->sc_loops == 1) { 990 DPRINTFN(5,("uhci_start_loop: add\n")); 991 /* Note, we don't loop back the soft pointer. */ 992 sc->sc_last_qh->qh.qh_hlink = 993 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 994 usb_syncmem(&sc->sc_last_qh->dma, 995 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 996 sizeof(sc->sc_last_qh->qh.qh_hlink), 997 BUS_DMASYNC_PREWRITE); 998 } 999 } 1000 1001 void 1002 uhci_rem_loop(uhci_softc_t *sc) { 1003 #ifdef UHCI_DEBUG 1004 if (uhcinoloop) 1005 return; 1006 #endif 1007 if (--sc->sc_loops == 0) { 1008 DPRINTFN(5,("uhci_end_loop: remove\n")); 1009 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1010 usb_syncmem(&sc->sc_last_qh->dma, 1011 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1012 sizeof(sc->sc_last_qh->qh.qh_hlink), 1013 BUS_DMASYNC_PREWRITE); 1014 } 1015 } 1016 1017 /* Add high speed control QH, called with lock held. */ 1018 void 1019 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1020 { 1021 uhci_soft_qh_t *eqh; 1022 1023 KASSERT(mutex_owned(&sc->sc_lock)); 1024 1025 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1026 eqh = sc->sc_hctl_end; 1027 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1028 sizeof(eqh->qh.qh_hlink), 1029 BUS_DMASYNC_POSTWRITE); 1030 sqh->hlink = eqh->hlink; 1031 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1032 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1033 BUS_DMASYNC_PREWRITE); 1034 eqh->hlink = sqh; 1035 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1036 sc->sc_hctl_end = sqh; 1037 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1038 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1039 #ifdef UHCI_CTL_LOOP 1040 uhci_add_loop(sc); 1041 #endif 1042 } 1043 1044 /* Remove high speed control QH, called with lock held. */ 1045 void 1046 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1047 { 1048 uhci_soft_qh_t *pqh; 1049 uint32_t elink; 1050 1051 KASSERT(mutex_owned(&sc->sc_lock)); 1052 1053 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1054 #ifdef UHCI_CTL_LOOP 1055 uhci_rem_loop(sc); 1056 #endif 1057 /* 1058 * The T bit should be set in the elink of the QH so that the HC 1059 * doesn't follow the pointer. This condition may fail if the 1060 * the transferred packet was short so that the QH still points 1061 * at the last used TD. 1062 * In this case we set the T bit and wait a little for the HC 1063 * to stop looking at the TD. 1064 * Note that if the TD chain is large enough, the controller 1065 * may still be looking at the chain at the end of this function. 1066 * uhci_free_std_chain() will make sure the controller stops 1067 * looking at it quickly, but until then we should not change 1068 * sqh->hlink. 1069 */ 1070 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1071 sizeof(sqh->qh.qh_elink), 1072 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1073 elink = le32toh(sqh->qh.qh_elink); 1074 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1075 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1076 if (!(elink & UHCI_PTR_T)) { 1077 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1078 usb_syncmem(&sqh->dma, 1079 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1080 sizeof(sqh->qh.qh_elink), 1081 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1082 delay(UHCI_QH_REMOVE_DELAY); 1083 } 1084 1085 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1086 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1087 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1088 pqh->hlink = sqh->hlink; 1089 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1090 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1091 sizeof(pqh->qh.qh_hlink), 1092 BUS_DMASYNC_PREWRITE); 1093 delay(UHCI_QH_REMOVE_DELAY); 1094 if (sc->sc_hctl_end == sqh) 1095 sc->sc_hctl_end = pqh; 1096 } 1097 1098 /* Add low speed control QH, called with lock held. */ 1099 void 1100 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1101 { 1102 uhci_soft_qh_t *eqh; 1103 1104 KASSERT(mutex_owned(&sc->sc_lock)); 1105 1106 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1107 eqh = sc->sc_lctl_end; 1108 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1109 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1110 sqh->hlink = eqh->hlink; 1111 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1112 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1113 BUS_DMASYNC_PREWRITE); 1114 eqh->hlink = sqh; 1115 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1116 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1117 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1118 sc->sc_lctl_end = sqh; 1119 } 1120 1121 /* Remove low speed control QH, called with lock held. */ 1122 void 1123 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1124 { 1125 uhci_soft_qh_t *pqh; 1126 uint32_t elink; 1127 1128 KASSERT(mutex_owned(&sc->sc_lock)); 1129 1130 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1131 /* See comment in uhci_remove_hs_ctrl() */ 1132 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1133 sizeof(sqh->qh.qh_elink), 1134 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1135 elink = le32toh(sqh->qh.qh_elink); 1136 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1137 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1138 if (!(elink & UHCI_PTR_T)) { 1139 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1140 usb_syncmem(&sqh->dma, 1141 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1142 sizeof(sqh->qh.qh_elink), 1143 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1144 delay(UHCI_QH_REMOVE_DELAY); 1145 } 1146 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1147 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1148 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1149 pqh->hlink = sqh->hlink; 1150 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1151 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1152 sizeof(pqh->qh.qh_hlink), 1153 BUS_DMASYNC_PREWRITE); 1154 delay(UHCI_QH_REMOVE_DELAY); 1155 if (sc->sc_lctl_end == sqh) 1156 sc->sc_lctl_end = pqh; 1157 } 1158 1159 /* Add bulk QH, called with lock held. */ 1160 void 1161 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1162 { 1163 uhci_soft_qh_t *eqh; 1164 1165 KASSERT(mutex_owned(&sc->sc_lock)); 1166 1167 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1168 eqh = sc->sc_bulk_end; 1169 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1170 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1171 sqh->hlink = eqh->hlink; 1172 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1173 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1174 BUS_DMASYNC_PREWRITE); 1175 eqh->hlink = sqh; 1176 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1177 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1178 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1179 sc->sc_bulk_end = sqh; 1180 uhci_add_loop(sc); 1181 } 1182 1183 /* Remove bulk QH, called with lock held. */ 1184 void 1185 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1186 { 1187 uhci_soft_qh_t *pqh; 1188 1189 KASSERT(mutex_owned(&sc->sc_lock)); 1190 1191 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1192 uhci_rem_loop(sc); 1193 /* See comment in uhci_remove_hs_ctrl() */ 1194 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1195 sizeof(sqh->qh.qh_elink), 1196 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1197 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1198 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1199 usb_syncmem(&sqh->dma, 1200 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1201 sizeof(sqh->qh.qh_elink), 1202 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1203 delay(UHCI_QH_REMOVE_DELAY); 1204 } 1205 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1206 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1207 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1208 pqh->hlink = sqh->hlink; 1209 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1210 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1211 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1212 delay(UHCI_QH_REMOVE_DELAY); 1213 if (sc->sc_bulk_end == sqh) 1214 sc->sc_bulk_end = pqh; 1215 } 1216 1217 Static int uhci_intr1(uhci_softc_t *); 1218 1219 int 1220 uhci_intr(void *arg) 1221 { 1222 uhci_softc_t *sc = arg; 1223 int ret = 0; 1224 1225 mutex_spin_enter(&sc->sc_intr_lock); 1226 1227 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1228 goto done; 1229 1230 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1231 #ifdef DIAGNOSTIC 1232 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1233 #endif 1234 goto done; 1235 } 1236 1237 ret = uhci_intr1(sc); 1238 1239 done: 1240 mutex_spin_exit(&sc->sc_intr_lock); 1241 return ret; 1242 } 1243 1244 int 1245 uhci_intr1(uhci_softc_t *sc) 1246 { 1247 int status; 1248 int ack; 1249 1250 #ifdef UHCI_DEBUG 1251 if (uhcidebug > 15) { 1252 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1253 uhci_dumpregs(sc); 1254 } 1255 #endif 1256 1257 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1258 1259 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1260 if (status == 0) /* The interrupt was not for us. */ 1261 return (0); 1262 1263 if (sc->sc_suspend != PWR_RESUME) { 1264 #ifdef DIAGNOSTIC 1265 printf("%s: interrupt while not operating ignored\n", 1266 device_xname(sc->sc_dev)); 1267 #endif 1268 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1269 return (0); 1270 } 1271 1272 ack = 0; 1273 if (status & UHCI_STS_USBINT) 1274 ack |= UHCI_STS_USBINT; 1275 if (status & UHCI_STS_USBEI) 1276 ack |= UHCI_STS_USBEI; 1277 if (status & UHCI_STS_RD) { 1278 ack |= UHCI_STS_RD; 1279 #ifdef UHCI_DEBUG 1280 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1281 #endif 1282 } 1283 if (status & UHCI_STS_HSE) { 1284 ack |= UHCI_STS_HSE; 1285 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1286 } 1287 if (status & UHCI_STS_HCPE) { 1288 ack |= UHCI_STS_HCPE; 1289 printf("%s: host controller process error\n", 1290 device_xname(sc->sc_dev)); 1291 } 1292 1293 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1294 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1295 /* no acknowledge needed */ 1296 if (!sc->sc_dying) { 1297 printf("%s: host controller halted\n", 1298 device_xname(sc->sc_dev)); 1299 #ifdef UHCI_DEBUG 1300 uhci_dump_all(sc); 1301 #endif 1302 } 1303 sc->sc_dying = 1; 1304 } 1305 1306 if (!ack) 1307 return (0); /* nothing to acknowledge */ 1308 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1309 1310 usb_schedsoftintr(&sc->sc_bus); 1311 1312 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1313 1314 return (1); 1315 } 1316 1317 void 1318 uhci_softintr(void *v) 1319 { 1320 struct usbd_bus *bus = v; 1321 uhci_softc_t *sc = bus->ub_hcpriv; 1322 uhci_intr_info_t *ii, *nextii; 1323 1324 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1325 1326 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1327 1328 /* 1329 * Interrupts on UHCI really suck. When the host controller 1330 * interrupts because a transfer is completed there is no 1331 * way of knowing which transfer it was. You can scan down 1332 * the TDs and QHs of the previous frame to limit the search, 1333 * but that assumes that the interrupt was not delayed by more 1334 * than 1 ms, which may not always be true (e.g. after debug 1335 * output on a slow console). 1336 * We scan all interrupt descriptors to see if any have 1337 * completed. 1338 */ 1339 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1340 nextii = LIST_NEXT(ii, list); 1341 uhci_check_intr(sc, ii); 1342 } 1343 1344 if (sc->sc_softwake) { 1345 sc->sc_softwake = 0; 1346 cv_broadcast(&sc->sc_softwake_cv); 1347 } 1348 } 1349 1350 /* Check for an interrupt. */ 1351 void 1352 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1353 { 1354 uhci_soft_td_t *std, *lstd; 1355 uint32_t status; 1356 1357 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1358 #ifdef DIAGNOSTIC 1359 if (ii == NULL) { 1360 printf("uhci_check_intr: no ii? %p\n", ii); 1361 return; 1362 } 1363 #endif 1364 if (ii->xfer->ux_status == USBD_CANCELLED || 1365 ii->xfer->ux_status == USBD_TIMEOUT) { 1366 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1367 return; 1368 } 1369 1370 if (ii->stdstart == NULL) 1371 return; 1372 lstd = ii->stdend; 1373 #ifdef DIAGNOSTIC 1374 if (lstd == NULL) { 1375 printf("uhci_check_intr: std==0\n"); 1376 return; 1377 } 1378 #endif 1379 usb_syncmem(&lstd->dma, 1380 lstd->offs + offsetof(uhci_td_t, td_status), 1381 sizeof(lstd->td.td_status), 1382 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1383 status = le32toh(lstd->td.td_status); 1384 usb_syncmem(&lstd->dma, 1385 lstd->offs + offsetof(uhci_td_t, td_status), 1386 sizeof(lstd->td.td_status), 1387 BUS_DMASYNC_PREREAD); 1388 1389 /* If the last TD is not marked active we can complete */ 1390 if (!(status & UHCI_TD_ACTIVE)) { 1391 done: 1392 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1393 callout_stop(&ii->xfer->ux_callout); 1394 uhci_idone(ii); 1395 return; 1396 } 1397 1398 /* 1399 * If the last TD is still active we need to check whether there 1400 * is an error somewhere in the middle, or whether there was a 1401 * short packet (SPD and not ACTIVE). 1402 */ 1403 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1404 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1405 usb_syncmem(&std->dma, 1406 std->offs + offsetof(uhci_td_t, td_status), 1407 sizeof(std->td.td_status), 1408 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1409 status = le32toh(std->td.td_status); 1410 usb_syncmem(&std->dma, 1411 std->offs + offsetof(uhci_td_t, td_status), 1412 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1413 1414 /* If there's an active TD the xfer isn't done. */ 1415 if (status & UHCI_TD_ACTIVE) { 1416 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1417 __func__, ii, std)); 1418 return; 1419 } 1420 1421 /* Any kind of error makes the xfer done. */ 1422 if (status & UHCI_TD_STALLED) 1423 goto done; 1424 1425 /* 1426 * If the data phase of a control transfer is short, we need 1427 * to complete the status stage 1428 */ 1429 usbd_xfer_handle xfer = ii->xfer; 1430 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1431 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1432 1433 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1434 struct uhci_pipe *upipe = 1435 (struct uhci_pipe *)xfer->ux_pipe; 1436 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1437 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1438 1439 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1440 "phase needs completion\n", __func__, ii, 1441 ii->stdstart)); 1442 1443 sqh->qh.qh_elink = 1444 htole32(stat->physaddr | UHCI_PTR_TD); 1445 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1446 BUS_DMASYNC_PREWRITE); 1447 break; 1448 } 1449 1450 /* We want short packets, and it is short: it's done */ 1451 usb_syncmem(&std->dma, 1452 std->offs + offsetof(uhci_td_t, td_token), 1453 sizeof(std->td.td_token), 1454 BUS_DMASYNC_POSTWRITE); 1455 1456 if ((status & UHCI_TD_SPD) && 1457 UHCI_TD_GET_ACTLEN(status) < 1458 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1459 goto done; 1460 } 1461 } 1462 } 1463 1464 /* Called with USB lock held. */ 1465 void 1466 uhci_idone(uhci_intr_info_t *ii) 1467 { 1468 usbd_xfer_handle xfer = ii->xfer; 1469 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1470 #ifdef DIAGNOSTIC 1471 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1472 #endif 1473 uhci_soft_td_t *std; 1474 uint32_t status = 0, nstatus; 1475 int actlen; 1476 1477 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1478 1479 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1480 #ifdef DIAGNOSTIC 1481 { 1482 /* XXX SMP? */ 1483 int s = splhigh(); 1484 if (ii->isdone) { 1485 splx(s); 1486 #ifdef UHCI_DEBUG 1487 printf("uhci_idone: ii is done!\n "); 1488 uhci_dump_ii(ii); 1489 #else 1490 printf("uhci_idone: ii=%p is done!\n", ii); 1491 #endif 1492 return; 1493 } 1494 ii->isdone = 1; 1495 splx(s); 1496 } 1497 #endif 1498 1499 if (xfer->ux_nframes != 0) { 1500 /* Isoc transfer, do things differently. */ 1501 uhci_soft_td_t **stds = upipe->u.iso.stds; 1502 int i, n, nframes, len; 1503 1504 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1505 1506 nframes = xfer->ux_nframes; 1507 actlen = 0; 1508 n = UXFER(xfer)->curframe; 1509 for (i = 0; i < nframes; i++) { 1510 std = stds[n]; 1511 #ifdef UHCI_DEBUG 1512 if (uhcidebug > 5) { 1513 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1514 uhci_dump_td(std); 1515 } 1516 #endif 1517 if (++n >= UHCI_VFRAMELIST_COUNT) 1518 n = 0; 1519 usb_syncmem(&std->dma, 1520 std->offs + offsetof(uhci_td_t, td_status), 1521 sizeof(std->td.td_status), 1522 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1523 status = le32toh(std->td.td_status); 1524 len = UHCI_TD_GET_ACTLEN(status); 1525 xfer->ux_frlengths[i] = len; 1526 actlen += len; 1527 } 1528 upipe->u.iso.inuse -= nframes; 1529 xfer->ux_actlen = actlen; 1530 xfer->ux_status = USBD_NORMAL_COMPLETION; 1531 goto end; 1532 } 1533 1534 #ifdef UHCI_DEBUG 1535 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1536 ii, xfer, upipe)); 1537 if (uhcidebug > 10) 1538 uhci_dump_tds(ii->stdstart); 1539 #endif 1540 1541 /* The transfer is done, compute actual length and status. */ 1542 actlen = 0; 1543 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1544 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1545 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1546 nstatus = le32toh(std->td.td_status); 1547 if (nstatus & UHCI_TD_ACTIVE) 1548 break; 1549 1550 status = nstatus; 1551 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1552 UHCI_TD_PID_SETUP) 1553 actlen += UHCI_TD_GET_ACTLEN(status); 1554 else { 1555 /* 1556 * UHCI will report CRCTO in addition to a STALL or NAK 1557 * for a SETUP transaction. See section 3.2.2, "TD 1558 * CONTROL AND STATUS". 1559 */ 1560 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1561 status &= ~UHCI_TD_CRCTO; 1562 } 1563 } 1564 /* If there are left over TDs we need to update the toggle. */ 1565 if (std != NULL) 1566 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1567 1568 status &= UHCI_TD_ERROR; 1569 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1570 actlen, status)); 1571 xfer->ux_actlen = actlen; 1572 if (status != 0) { 1573 #ifdef UHCI_DEBUG 1574 char sbuf[128]; 1575 1576 snprintb(sbuf, sizeof(sbuf), 1577 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1578 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status); 1579 1580 DPRINTFN((status == UHCI_TD_STALLED)*10, 1581 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1582 "status 0x%s\n", 1583 xfer->ux_pipe->up_dev->ud_addr, 1584 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1585 sbuf)); 1586 #endif 1587 1588 if (status == UHCI_TD_STALLED) 1589 xfer->ux_status = USBD_STALLED; 1590 else 1591 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1592 } else { 1593 xfer->ux_status = USBD_NORMAL_COMPLETION; 1594 } 1595 1596 end: 1597 usb_transfer_complete(xfer); 1598 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1599 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1600 } 1601 1602 /* 1603 * Called when a request does not complete. 1604 */ 1605 void 1606 uhci_timeout(void *addr) 1607 { 1608 uhci_intr_info_t *ii = addr; 1609 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1610 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe; 1611 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1612 1613 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1614 1615 if (sc->sc_dying) { 1616 mutex_enter(&sc->sc_lock); 1617 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1618 mutex_exit(&sc->sc_lock); 1619 return; 1620 } 1621 1622 /* Execute the abort in a process context. */ 1623 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1624 USB_TASKQ_MPSAFE); 1625 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1626 USB_TASKQ_HC); 1627 } 1628 1629 void 1630 uhci_timeout_task(void *addr) 1631 { 1632 usbd_xfer_handle xfer = addr; 1633 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1634 1635 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1636 1637 mutex_enter(&sc->sc_lock); 1638 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1639 mutex_exit(&sc->sc_lock); 1640 } 1641 1642 /* 1643 * Wait here until controller claims to have an interrupt. 1644 * Then call uhci_intr and return. Use timeout to avoid waiting 1645 * too long. 1646 * Only used during boot when interrupts are not enabled yet. 1647 */ 1648 void 1649 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1650 { 1651 int timo = xfer->ux_timeout; 1652 uhci_intr_info_t *ii; 1653 1654 mutex_enter(&sc->sc_lock); 1655 1656 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1657 1658 xfer->ux_status = USBD_IN_PROGRESS; 1659 for (; timo >= 0; timo--) { 1660 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1661 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1662 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1663 mutex_spin_enter(&sc->sc_intr_lock); 1664 uhci_intr1(sc); 1665 mutex_spin_exit(&sc->sc_intr_lock); 1666 if (xfer->ux_status != USBD_IN_PROGRESS) 1667 goto done; 1668 } 1669 } 1670 1671 /* Timeout */ 1672 DPRINTF(("uhci_waitintr: timeout\n")); 1673 for (ii = LIST_FIRST(&sc->sc_intrhead); 1674 ii != NULL && ii->xfer != xfer; 1675 ii = LIST_NEXT(ii, list)) 1676 ; 1677 #ifdef DIAGNOSTIC 1678 if (ii == NULL) 1679 panic("uhci_waitintr: lost intr_info"); 1680 #endif 1681 uhci_idone(ii); 1682 1683 done: 1684 mutex_exit(&sc->sc_lock); 1685 } 1686 1687 void 1688 uhci_poll(struct usbd_bus *bus) 1689 { 1690 uhci_softc_t *sc = bus->ub_hcpriv; 1691 1692 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1693 mutex_spin_enter(&sc->sc_intr_lock); 1694 uhci_intr1(sc); 1695 mutex_spin_exit(&sc->sc_intr_lock); 1696 } 1697 } 1698 1699 void 1700 uhci_reset(uhci_softc_t *sc) 1701 { 1702 int n; 1703 1704 UHCICMD(sc, UHCI_CMD_HCRESET); 1705 /* The reset bit goes low when the controller is done. */ 1706 for (n = 0; n < UHCI_RESET_TIMEOUT && 1707 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1708 usb_delay_ms(&sc->sc_bus, 1); 1709 if (n >= UHCI_RESET_TIMEOUT) 1710 printf("%s: controller did not reset\n", 1711 device_xname(sc->sc_dev)); 1712 } 1713 1714 usbd_status 1715 uhci_run(uhci_softc_t *sc, int run, int locked) 1716 { 1717 int n, running; 1718 uint16_t cmd; 1719 1720 run = run != 0; 1721 if (!locked) 1722 mutex_spin_enter(&sc->sc_intr_lock); 1723 DPRINTF(("uhci_run: setting run=%d\n", run)); 1724 cmd = UREAD2(sc, UHCI_CMD); 1725 if (run) 1726 cmd |= UHCI_CMD_RS; 1727 else 1728 cmd &= ~UHCI_CMD_RS; 1729 UHCICMD(sc, cmd); 1730 for(n = 0; n < 10; n++) { 1731 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1732 /* return when we've entered the state we want */ 1733 if (run == running) { 1734 if (!locked) 1735 mutex_spin_exit(&sc->sc_intr_lock); 1736 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1737 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1738 return (USBD_NORMAL_COMPLETION); 1739 } 1740 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1741 } 1742 if (!locked) 1743 mutex_spin_exit(&sc->sc_intr_lock); 1744 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1745 run ? "start" : "stop"); 1746 return (USBD_IOERROR); 1747 } 1748 1749 /* 1750 * Memory management routines. 1751 * uhci_alloc_std allocates TDs 1752 * uhci_alloc_sqh allocates QHs 1753 * These two routines do their own free list management, 1754 * partly for speed, partly because allocating DMAable memory 1755 * has page size granularaity so much memory would be wasted if 1756 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1757 */ 1758 1759 uhci_soft_td_t * 1760 uhci_alloc_std(uhci_softc_t *sc) 1761 { 1762 uhci_soft_td_t *std; 1763 usbd_status err; 1764 int i, offs; 1765 usb_dma_t dma; 1766 1767 if (sc->sc_freetds == NULL) { 1768 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1769 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1770 UHCI_TD_ALIGN, &dma); 1771 if (err) 1772 return (0); 1773 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1774 offs = i * UHCI_STD_SIZE; 1775 std = KERNADDR(&dma, offs); 1776 std->physaddr = DMAADDR(&dma, offs); 1777 std->dma = dma; 1778 std->offs = offs; 1779 std->link.std = sc->sc_freetds; 1780 sc->sc_freetds = std; 1781 } 1782 } 1783 std = sc->sc_freetds; 1784 sc->sc_freetds = std->link.std; 1785 memset(&std->td, 0, sizeof(uhci_td_t)); 1786 return std; 1787 } 1788 1789 void 1790 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1791 { 1792 #ifdef DIAGNOSTIC 1793 #define TD_IS_FREE 0x12345678 1794 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1795 printf("uhci_free_std: freeing free TD %p\n", std); 1796 return; 1797 } 1798 std->td.td_token = htole32(TD_IS_FREE); 1799 #endif 1800 std->link.std = sc->sc_freetds; 1801 sc->sc_freetds = std; 1802 } 1803 1804 uhci_soft_qh_t * 1805 uhci_alloc_sqh(uhci_softc_t *sc) 1806 { 1807 uhci_soft_qh_t *sqh; 1808 usbd_status err; 1809 int i, offs; 1810 usb_dma_t dma; 1811 1812 if (sc->sc_freeqhs == NULL) { 1813 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1814 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1815 UHCI_QH_ALIGN, &dma); 1816 if (err) 1817 return (0); 1818 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1819 offs = i * UHCI_SQH_SIZE; 1820 sqh = KERNADDR(&dma, offs); 1821 sqh->physaddr = DMAADDR(&dma, offs); 1822 sqh->dma = dma; 1823 sqh->offs = offs; 1824 sqh->hlink = sc->sc_freeqhs; 1825 sc->sc_freeqhs = sqh; 1826 } 1827 } 1828 sqh = sc->sc_freeqhs; 1829 sc->sc_freeqhs = sqh->hlink; 1830 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1831 return (sqh); 1832 } 1833 1834 void 1835 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1836 { 1837 sqh->hlink = sc->sc_freeqhs; 1838 sc->sc_freeqhs = sqh; 1839 } 1840 1841 void 1842 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1843 uhci_soft_td_t *stdend) 1844 { 1845 uhci_soft_td_t *p; 1846 uint32_t td_link; 1847 1848 /* 1849 * to avoid race condition with the controller which may be looking 1850 * at this chain, we need to first invalidate all links, and 1851 * then wait for the controller to move to another queue 1852 */ 1853 for (p = std; p != stdend; p = p->link.std) { 1854 usb_syncmem(&p->dma, 1855 p->offs + offsetof(uhci_td_t, td_link), 1856 sizeof(p->td.td_link), 1857 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1858 td_link = le32toh(p->td.td_link); 1859 usb_syncmem(&p->dma, 1860 p->offs + offsetof(uhci_td_t, td_link), 1861 sizeof(p->td.td_link), 1862 BUS_DMASYNC_PREREAD); 1863 if ((td_link & UHCI_PTR_T) == 0) { 1864 p->td.td_link = htole32(UHCI_PTR_T); 1865 usb_syncmem(&p->dma, 1866 p->offs + offsetof(uhci_td_t, td_link), 1867 sizeof(p->td.td_link), 1868 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1869 } 1870 } 1871 delay(UHCI_QH_REMOVE_DELAY); 1872 1873 for (; std != stdend; std = p) { 1874 p = std->link.std; 1875 uhci_free_std(sc, std); 1876 } 1877 } 1878 1879 usbd_status 1880 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1881 int rd, uint16_t flags, usb_dma_t *dma, 1882 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1883 { 1884 uhci_soft_td_t *p, *lastp; 1885 uhci_physaddr_t lastlink; 1886 int i, ntd, l, tog, maxp; 1887 uint32_t status; 1888 int addr = upipe->pipe.up_dev->ud_addr; 1889 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1890 1891 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1892 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1893 upipe->pipe.up_dev->ud_speed, flags)); 1894 1895 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1896 1897 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1898 if (maxp == 0) { 1899 printf("uhci_alloc_std_chain: maxp=0\n"); 1900 return (USBD_INVAL); 1901 } 1902 ntd = (len + maxp - 1) / maxp; 1903 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1904 ntd++; 1905 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1906 if (ntd == 0) { 1907 *sp = *ep = 0; 1908 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1909 return (USBD_NORMAL_COMPLETION); 1910 } 1911 tog = upipe->nexttoggle; 1912 if (ntd % 2 == 0) 1913 tog ^= 1; 1914 upipe->nexttoggle = tog ^ 1; 1915 lastp = NULL; 1916 lastlink = UHCI_PTR_T; 1917 ntd--; 1918 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1919 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1920 status |= UHCI_TD_LS; 1921 if (flags & USBD_SHORT_XFER_OK) 1922 status |= UHCI_TD_SPD; 1923 usb_syncmem(dma, 0, len, 1924 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1925 for (i = ntd; i >= 0; i--) { 1926 p = uhci_alloc_std(sc); 1927 if (p == NULL) { 1928 KASSERT(lastp != NULL); 1929 uhci_free_std_chain(sc, lastp, NULL); 1930 return (USBD_NOMEM); 1931 } 1932 p->link.std = lastp; 1933 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1934 lastp = p; 1935 lastlink = p->physaddr; 1936 p->td.td_status = htole32(status); 1937 if (i == ntd) { 1938 /* last TD */ 1939 l = len % maxp; 1940 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1941 l = maxp; 1942 *ep = p; 1943 } else 1944 l = maxp; 1945 p->td.td_token = 1946 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1947 UHCI_TD_OUT(l, endpt, addr, tog)); 1948 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1949 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1950 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1951 tog ^= 1; 1952 } 1953 *sp = lastp; 1954 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1955 upipe->nexttoggle)); 1956 return (USBD_NORMAL_COMPLETION); 1957 } 1958 1959 void 1960 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1961 { 1962 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1963 upipe->nexttoggle = 0; 1964 } 1965 1966 void 1967 uhci_noop(usbd_pipe_handle pipe) 1968 { 1969 } 1970 1971 usbd_status 1972 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1973 { 1974 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1975 usbd_status err; 1976 1977 /* Insert last in queue. */ 1978 mutex_enter(&sc->sc_lock); 1979 err = usb_insert_transfer(xfer); 1980 mutex_exit(&sc->sc_lock); 1981 if (err) 1982 return (err); 1983 1984 /* 1985 * Pipe isn't running (otherwise err would be USBD_INPROG), 1986 * so start it first. 1987 */ 1988 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 1989 } 1990 1991 usbd_status 1992 uhci_device_bulk_start(usbd_xfer_handle xfer) 1993 { 1994 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1995 usbd_device_handle dev = upipe->pipe.up_dev; 1996 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1997 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1998 uhci_soft_td_t *data, *dataend; 1999 uhci_soft_qh_t *sqh; 2000 usbd_status err; 2001 int len, isread, endpt; 2002 2003 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2004 xfer, xfer->ux_length, xfer->ux_flags, ii)); 2005 2006 if (sc->sc_dying) 2007 return (USBD_IOERROR); 2008 2009 #ifdef DIAGNOSTIC 2010 if (xfer->ux_rqflags & URQ_REQUEST) 2011 panic("uhci_device_bulk_transfer: a request"); 2012 #endif 2013 2014 mutex_enter(&sc->sc_lock); 2015 2016 len = xfer->ux_length; 2017 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2018 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2019 sqh = upipe->u.bulk.sqh; 2020 2021 upipe->u.bulk.isread = isread; 2022 upipe->u.bulk.length = len; 2023 2024 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2025 &xfer->ux_dmabuf, &data, &dataend); 2026 if (err) { 2027 mutex_exit(&sc->sc_lock); 2028 return (err); 2029 } 2030 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2031 usb_syncmem(&dataend->dma, 2032 dataend->offs + offsetof(uhci_td_t, td_status), 2033 sizeof(dataend->td.td_status), 2034 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2035 2036 2037 #ifdef UHCI_DEBUG 2038 if (uhcidebug > 8) { 2039 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2040 uhci_dump_tds(data); 2041 } 2042 #endif 2043 2044 /* Set up interrupt info. */ 2045 ii->xfer = xfer; 2046 ii->stdstart = data; 2047 ii->stdend = dataend; 2048 #ifdef DIAGNOSTIC 2049 if (!ii->isdone) { 2050 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2051 } 2052 ii->isdone = 0; 2053 #endif 2054 2055 sqh->elink = data; 2056 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2057 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2058 2059 uhci_add_bulk(sc, sqh); 2060 uhci_add_intr_info(sc, ii); 2061 2062 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2063 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2064 uhci_timeout, ii); 2065 } 2066 xfer->ux_status = USBD_IN_PROGRESS; 2067 2068 #ifdef UHCI_DEBUG 2069 if (uhcidebug > 10) { 2070 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2071 uhci_dump_tds(data); 2072 } 2073 #endif 2074 2075 if (sc->sc_bus.ub_usepolling) 2076 uhci_waitintr(sc, xfer); 2077 2078 mutex_exit(&sc->sc_lock); 2079 return (USBD_IN_PROGRESS); 2080 } 2081 2082 /* Abort a device bulk request. */ 2083 void 2084 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2085 { 2086 #ifdef DIAGNOSTIC 2087 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2088 #endif 2089 2090 KASSERT(mutex_owned(&sc->sc_lock)); 2091 2092 DPRINTF(("uhci_device_bulk_abort:\n")); 2093 uhci_abort_xfer(xfer, USBD_CANCELLED); 2094 } 2095 2096 /* 2097 * Abort a device request. 2098 * If this routine is called at splusb() it guarantees that the request 2099 * will be removed from the hardware scheduling and that the callback 2100 * for it will be called with USBD_CANCELLED status. 2101 * It's impossible to guarantee that the requested transfer will not 2102 * have happened since the hardware runs concurrently. 2103 * If the transaction has already happened we rely on the ordinary 2104 * interrupt processing to process it. 2105 * XXX This is most probably wrong. 2106 * XXXMRG this doesn't make sense anymore. 2107 */ 2108 void 2109 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2110 { 2111 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2112 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2113 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2114 uhci_soft_td_t *std; 2115 int wake; 2116 2117 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2118 2119 KASSERT(mutex_owned(&sc->sc_lock)); 2120 ASSERT_SLEEPABLE(); 2121 2122 if (sc->sc_dying) { 2123 /* If we're dying, just do the software part. */ 2124 xfer->ux_status = status; /* make software ignore it */ 2125 callout_stop(&xfer->ux_callout); 2126 usb_transfer_complete(xfer); 2127 return; 2128 } 2129 2130 /* 2131 * If an abort is already in progress then just wait for it to 2132 * complete and return. 2133 */ 2134 if (xfer->ux_hcflags & UXFER_ABORTING) { 2135 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2136 #ifdef DIAGNOSTIC 2137 if (status == USBD_TIMEOUT) 2138 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2139 #endif 2140 /* Override the status which might be USBD_TIMEOUT. */ 2141 xfer->ux_status = status; 2142 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2143 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2144 while (xfer->ux_hcflags & UXFER_ABORTING) 2145 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2146 goto done; 2147 } 2148 xfer->ux_hcflags |= UXFER_ABORTING; 2149 2150 /* 2151 * Step 1: Make interrupt routine and hardware ignore xfer. 2152 */ 2153 xfer->ux_status = status; /* make software ignore it */ 2154 callout_stop(&xfer->ux_callout); 2155 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2156 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2157 usb_syncmem(&std->dma, 2158 std->offs + offsetof(uhci_td_t, td_status), 2159 sizeof(std->td.td_status), 2160 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2161 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2162 usb_syncmem(&std->dma, 2163 std->offs + offsetof(uhci_td_t, td_status), 2164 sizeof(std->td.td_status), 2165 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2166 } 2167 2168 /* 2169 * Step 2: Wait until we know hardware has finished any possible 2170 * use of the xfer. Also make sure the soft interrupt routine 2171 * has run. 2172 */ 2173 /* Hardware finishes in 1ms */ 2174 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2175 sc->sc_softwake = 1; 2176 usb_schedsoftintr(&sc->sc_bus); 2177 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2178 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2179 2180 /* 2181 * Step 3: Execute callback. 2182 */ 2183 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2184 #ifdef DIAGNOSTIC 2185 ii->isdone = 1; 2186 #endif 2187 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2188 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2189 usb_transfer_complete(xfer); 2190 if (wake) 2191 cv_broadcast(&xfer->ux_hccv); 2192 done: 2193 KASSERT(mutex_owned(&sc->sc_lock)); 2194 } 2195 2196 /* Close a device bulk pipe. */ 2197 void 2198 uhci_device_bulk_close(usbd_pipe_handle pipe) 2199 { 2200 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2201 usbd_device_handle dev = upipe->pipe.up_dev; 2202 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2203 2204 KASSERT(mutex_owned(&sc->sc_lock)); 2205 2206 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2207 2208 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2209 } 2210 2211 usbd_status 2212 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2213 { 2214 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2215 usbd_status err; 2216 2217 /* Insert last in queue. */ 2218 mutex_enter(&sc->sc_lock); 2219 err = usb_insert_transfer(xfer); 2220 mutex_exit(&sc->sc_lock); 2221 if (err) 2222 return (err); 2223 2224 /* 2225 * Pipe isn't running (otherwise err would be USBD_INPROG), 2226 * so start it first. 2227 */ 2228 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2229 } 2230 2231 usbd_status 2232 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2233 { 2234 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2235 usbd_status err; 2236 2237 if (sc->sc_dying) 2238 return (USBD_IOERROR); 2239 2240 #ifdef DIAGNOSTIC 2241 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2242 panic("uhci_device_ctrl_transfer: not a request"); 2243 #endif 2244 2245 mutex_enter(&sc->sc_lock); 2246 err = uhci_device_request(xfer); 2247 mutex_exit(&sc->sc_lock); 2248 if (err) 2249 return (err); 2250 2251 if (sc->sc_bus.ub_usepolling) 2252 uhci_waitintr(sc, xfer); 2253 return (USBD_IN_PROGRESS); 2254 } 2255 2256 usbd_status 2257 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2258 { 2259 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2260 usbd_status err; 2261 2262 /* Insert last in queue. */ 2263 mutex_enter(&sc->sc_lock); 2264 err = usb_insert_transfer(xfer); 2265 mutex_exit(&sc->sc_lock); 2266 if (err) 2267 return (err); 2268 2269 /* 2270 * Pipe isn't running (otherwise err would be USBD_INPROG), 2271 * so start it first. 2272 */ 2273 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2274 } 2275 2276 usbd_status 2277 uhci_device_intr_start(usbd_xfer_handle xfer) 2278 { 2279 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2280 usbd_device_handle dev = upipe->pipe.up_dev; 2281 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2282 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2283 uhci_soft_td_t *data, *dataend; 2284 uhci_soft_qh_t *sqh; 2285 usbd_status err; 2286 int isread, endpt; 2287 int i; 2288 2289 if (sc->sc_dying) 2290 return (USBD_IOERROR); 2291 2292 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2293 xfer, xfer->ux_length, xfer->ux_flags)); 2294 2295 #ifdef DIAGNOSTIC 2296 if (xfer->ux_rqflags & URQ_REQUEST) 2297 panic("uhci_device_intr_transfer: a request"); 2298 #endif 2299 2300 mutex_enter(&sc->sc_lock); 2301 2302 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2303 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2304 2305 upipe->u.intr.isread = isread; 2306 2307 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2308 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2309 &dataend); 2310 if (err) { 2311 mutex_exit(&sc->sc_lock); 2312 return (err); 2313 } 2314 2315 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2316 usb_syncmem(&dataend->dma, 2317 dataend->offs + offsetof(uhci_td_t, td_status), 2318 sizeof(dataend->td.td_status), 2319 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2320 2321 #ifdef UHCI_DEBUG 2322 if (uhcidebug > 10) { 2323 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2324 uhci_dump_tds(data); 2325 uhci_dump_qh(upipe->u.intr.qhs[0]); 2326 } 2327 #endif 2328 2329 /* Set up interrupt info. */ 2330 ii->xfer = xfer; 2331 ii->stdstart = data; 2332 ii->stdend = dataend; 2333 #ifdef DIAGNOSTIC 2334 if (!ii->isdone) { 2335 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2336 } 2337 ii->isdone = 0; 2338 #endif 2339 2340 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2341 upipe->u.intr.qhs[0])); 2342 for (i = 0; i < upipe->u.intr.npoll; i++) { 2343 sqh = upipe->u.intr.qhs[i]; 2344 sqh->elink = data; 2345 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2346 usb_syncmem(&sqh->dma, 2347 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2348 sizeof(sqh->qh.qh_elink), 2349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2350 } 2351 uhci_add_intr_info(sc, ii); 2352 xfer->ux_status = USBD_IN_PROGRESS; 2353 mutex_exit(&sc->sc_lock); 2354 2355 #ifdef UHCI_DEBUG 2356 if (uhcidebug > 10) { 2357 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2358 uhci_dump_tds(data); 2359 uhci_dump_qh(upipe->u.intr.qhs[0]); 2360 } 2361 #endif 2362 2363 return (USBD_IN_PROGRESS); 2364 } 2365 2366 /* Abort a device control request. */ 2367 void 2368 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2369 { 2370 #ifdef DIAGNOSTIC 2371 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2372 #endif 2373 2374 KASSERT(mutex_owned(&sc->sc_lock)); 2375 2376 DPRINTF(("uhci_device_ctrl_abort:\n")); 2377 uhci_abort_xfer(xfer, USBD_CANCELLED); 2378 } 2379 2380 /* Close a device control pipe. */ 2381 void 2382 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2383 { 2384 } 2385 2386 /* Abort a device interrupt request. */ 2387 void 2388 uhci_device_intr_abort(usbd_xfer_handle xfer) 2389 { 2390 #ifdef DIAGNOSTIC 2391 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2392 #endif 2393 2394 KASSERT(mutex_owned(&sc->sc_lock)); 2395 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2396 2397 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2398 2399 uhci_abort_xfer(xfer, USBD_CANCELLED); 2400 } 2401 2402 /* Close a device interrupt pipe. */ 2403 void 2404 uhci_device_intr_close(usbd_pipe_handle pipe) 2405 { 2406 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2407 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2408 int i, npoll; 2409 2410 KASSERT(mutex_owned(&sc->sc_lock)); 2411 2412 /* Unlink descriptors from controller data structures. */ 2413 npoll = upipe->u.intr.npoll; 2414 for (i = 0; i < npoll; i++) 2415 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2416 2417 /* 2418 * We now have to wait for any activity on the physical 2419 * descriptors to stop. 2420 */ 2421 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2422 2423 for(i = 0; i < npoll; i++) 2424 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2425 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2426 2427 /* XXX free other resources */ 2428 } 2429 2430 usbd_status 2431 uhci_device_request(usbd_xfer_handle xfer) 2432 { 2433 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2434 usb_device_request_t *req = &xfer->ux_request; 2435 usbd_device_handle dev = upipe->pipe.up_dev; 2436 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2437 int addr = dev->ud_addr; 2438 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2439 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2440 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2441 uhci_soft_qh_t *sqh; 2442 int len; 2443 uint32_t ls; 2444 usbd_status err; 2445 int isread; 2446 2447 KASSERT(mutex_owned(&sc->sc_lock)); 2448 2449 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2450 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2451 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2452 UGETW(req->wIndex), UGETW(req->wLength), 2453 addr, endpt)); 2454 2455 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2456 isread = req->bmRequestType & UT_READ; 2457 len = UGETW(req->wLength); 2458 2459 setup = upipe->u.ctl.setup; 2460 stat = upipe->u.ctl.stat; 2461 sqh = upipe->u.ctl.sqh; 2462 2463 /* Set up data transaction */ 2464 if (len != 0) { 2465 upipe->nexttoggle = 1; 2466 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2467 &xfer->ux_dmabuf, &data, &dataend); 2468 if (err) 2469 return (err); 2470 next = data; 2471 dataend->link.std = stat; 2472 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2473 usb_syncmem(&dataend->dma, 2474 dataend->offs + offsetof(uhci_td_t, td_link), 2475 sizeof(dataend->td.td_link), 2476 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2477 } else { 2478 next = stat; 2479 } 2480 upipe->u.ctl.length = len; 2481 2482 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2483 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2484 2485 setup->link.std = next; 2486 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2487 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2488 UHCI_TD_ACTIVE); 2489 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2490 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2491 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2492 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2493 2494 stat->link.std = NULL; 2495 stat->td.td_link = htole32(UHCI_PTR_T); 2496 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2497 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2498 stat->td.td_token = 2499 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2500 UHCI_TD_IN (0, endpt, addr, 1)); 2501 stat->td.td_buffer = htole32(0); 2502 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2504 2505 #ifdef UHCI_DEBUG 2506 if (uhcidebug > 10) { 2507 DPRINTF(("uhci_device_request: before transfer\n")); 2508 uhci_dump_tds(setup); 2509 } 2510 #endif 2511 2512 /* Set up interrupt info. */ 2513 ii->xfer = xfer; 2514 ii->stdstart = setup; 2515 ii->stdend = stat; 2516 #ifdef DIAGNOSTIC 2517 if (!ii->isdone) { 2518 printf("uhci_device_request: not done, ii=%p\n", ii); 2519 } 2520 ii->isdone = 0; 2521 #endif 2522 2523 sqh->elink = setup; 2524 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2525 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2526 2527 if (dev->ud_speed == USB_SPEED_LOW) 2528 uhci_add_ls_ctrl(sc, sqh); 2529 else 2530 uhci_add_hs_ctrl(sc, sqh); 2531 uhci_add_intr_info(sc, ii); 2532 #ifdef UHCI_DEBUG 2533 if (uhcidebug > 12) { 2534 uhci_soft_td_t *std; 2535 uhci_soft_qh_t *xqh; 2536 uhci_soft_qh_t *sxqh; 2537 int maxqh = 0; 2538 uhci_physaddr_t link; 2539 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2540 for (std = sc->sc_vframes[0].htd, link = 0; 2541 (link & UHCI_PTR_QH) == 0; 2542 std = std->link.std) { 2543 link = le32toh(std->td.td_link); 2544 uhci_dump_td(std); 2545 } 2546 sxqh = (uhci_soft_qh_t *)std; 2547 uhci_dump_qh(sxqh); 2548 for (xqh = sxqh; 2549 xqh != NULL; 2550 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2551 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2552 uhci_dump_qh(xqh); 2553 } 2554 DPRINTF(("Enqueued QH:\n")); 2555 uhci_dump_qh(sqh); 2556 uhci_dump_tds(sqh->elink); 2557 } 2558 #endif 2559 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2560 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2561 uhci_timeout, ii); 2562 } 2563 xfer->ux_status = USBD_IN_PROGRESS; 2564 2565 return (USBD_NORMAL_COMPLETION); 2566 } 2567 2568 usbd_status 2569 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2570 { 2571 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2572 usbd_status err; 2573 2574 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2575 2576 /* Put it on our queue, */ 2577 mutex_enter(&sc->sc_lock); 2578 err = usb_insert_transfer(xfer); 2579 mutex_exit(&sc->sc_lock); 2580 2581 /* bail out on error, */ 2582 if (err && err != USBD_IN_PROGRESS) 2583 return (err); 2584 2585 /* XXX should check inuse here */ 2586 2587 /* insert into schedule, */ 2588 uhci_device_isoc_enter(xfer); 2589 2590 /* and start if the pipe wasn't running */ 2591 if (!err) 2592 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2593 2594 return (err); 2595 } 2596 2597 void 2598 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2599 { 2600 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2601 usbd_device_handle dev = upipe->pipe.up_dev; 2602 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2603 struct iso *iso = &upipe->u.iso; 2604 uhci_soft_td_t *std; 2605 uint32_t buf, len, status, offs; 2606 int i, next, nframes; 2607 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2608 2609 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2610 "nframes=%d\n", 2611 iso->inuse, iso->next, xfer, xfer->ux_nframes)); 2612 2613 if (sc->sc_dying) 2614 return; 2615 2616 if (xfer->ux_status == USBD_IN_PROGRESS) { 2617 /* This request has already been entered into the frame list */ 2618 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2619 /* XXX */ 2620 } 2621 2622 #ifdef DIAGNOSTIC 2623 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2624 printf("uhci_device_isoc_enter: overflow!\n"); 2625 #endif 2626 2627 next = iso->next; 2628 if (next == -1) { 2629 /* Not in use yet, schedule it a few frames ahead. */ 2630 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2631 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2632 } 2633 2634 xfer->ux_status = USBD_IN_PROGRESS; 2635 UXFER(xfer)->curframe = next; 2636 2637 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2638 offs = 0; 2639 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2640 UHCI_TD_ACTIVE | 2641 UHCI_TD_IOS); 2642 nframes = xfer->ux_nframes; 2643 mutex_enter(&sc->sc_lock); 2644 for (i = 0; i < nframes; i++) { 2645 std = iso->stds[next]; 2646 if (++next >= UHCI_VFRAMELIST_COUNT) 2647 next = 0; 2648 len = xfer->ux_frlengths[i]; 2649 std->td.td_buffer = htole32(buf); 2650 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2651 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2652 if (i == nframes - 1) 2653 status |= UHCI_TD_IOC; 2654 std->td.td_status = htole32(status); 2655 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2656 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2657 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2658 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2659 #ifdef UHCI_DEBUG 2660 if (uhcidebug > 5) { 2661 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2662 uhci_dump_td(std); 2663 } 2664 #endif 2665 buf += len; 2666 offs += len; 2667 } 2668 iso->next = next; 2669 iso->inuse += xfer->ux_nframes; 2670 2671 mutex_exit(&sc->sc_lock); 2672 } 2673 2674 usbd_status 2675 uhci_device_isoc_start(usbd_xfer_handle xfer) 2676 { 2677 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2678 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2679 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2680 uhci_soft_td_t *end; 2681 int i; 2682 2683 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2684 2685 mutex_enter(&sc->sc_lock); 2686 2687 if (sc->sc_dying) { 2688 mutex_exit(&sc->sc_lock); 2689 return (USBD_IOERROR); 2690 } 2691 2692 #ifdef DIAGNOSTIC 2693 if (xfer->ux_status != USBD_IN_PROGRESS) 2694 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2695 #endif 2696 2697 /* Find the last TD */ 2698 i = UXFER(xfer)->curframe + xfer->ux_nframes; 2699 if (i >= UHCI_VFRAMELIST_COUNT) 2700 i -= UHCI_VFRAMELIST_COUNT; 2701 end = upipe->u.iso.stds[i]; 2702 2703 #ifdef DIAGNOSTIC 2704 if (end == NULL) { 2705 printf("uhci_device_isoc_start: end == NULL\n"); 2706 return (USBD_INVAL); 2707 } 2708 #endif 2709 2710 /* Set up interrupt info. */ 2711 ii->xfer = xfer; 2712 ii->stdstart = end; 2713 ii->stdend = end; 2714 #ifdef DIAGNOSTIC 2715 if (!ii->isdone) 2716 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2717 ii->isdone = 0; 2718 #endif 2719 uhci_add_intr_info(sc, ii); 2720 2721 mutex_exit(&sc->sc_lock); 2722 2723 return (USBD_IN_PROGRESS); 2724 } 2725 2726 void 2727 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2728 { 2729 #ifdef DIAGNOSTIC 2730 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2731 #endif 2732 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2733 uhci_soft_td_t **stds = upipe->u.iso.stds; 2734 uhci_soft_td_t *std; 2735 int i, n, nframes, maxlen, len; 2736 2737 KASSERT(mutex_owned(&sc->sc_lock)); 2738 2739 /* Transfer is already done. */ 2740 if (xfer->ux_status != USBD_NOT_STARTED && 2741 xfer->ux_status != USBD_IN_PROGRESS) { 2742 return; 2743 } 2744 2745 /* Give xfer the requested abort code. */ 2746 xfer->ux_status = USBD_CANCELLED; 2747 2748 /* make hardware ignore it, */ 2749 nframes = xfer->ux_nframes; 2750 n = UXFER(xfer)->curframe; 2751 maxlen = 0; 2752 for (i = 0; i < nframes; i++) { 2753 std = stds[n]; 2754 usb_syncmem(&std->dma, 2755 std->offs + offsetof(uhci_td_t, td_status), 2756 sizeof(std->td.td_status), 2757 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2758 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2759 usb_syncmem(&std->dma, 2760 std->offs + offsetof(uhci_td_t, td_status), 2761 sizeof(std->td.td_status), 2762 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2763 usb_syncmem(&std->dma, 2764 std->offs + offsetof(uhci_td_t, td_token), 2765 sizeof(std->td.td_token), 2766 BUS_DMASYNC_POSTWRITE); 2767 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2768 if (len > maxlen) 2769 maxlen = len; 2770 if (++n >= UHCI_VFRAMELIST_COUNT) 2771 n = 0; 2772 } 2773 2774 /* and wait until we are sure the hardware has finished. */ 2775 delay(maxlen); 2776 2777 #ifdef DIAGNOSTIC 2778 UXFER(xfer)->iinfo.isdone = 1; 2779 #endif 2780 /* Run callback and remove from interrupt list. */ 2781 usb_transfer_complete(xfer); 2782 2783 KASSERT(mutex_owned(&sc->sc_lock)); 2784 } 2785 2786 void 2787 uhci_device_isoc_close(usbd_pipe_handle pipe) 2788 { 2789 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2790 usbd_device_handle dev = upipe->pipe.up_dev; 2791 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2792 uhci_soft_td_t *std, *vstd; 2793 struct iso *iso; 2794 int i; 2795 2796 KASSERT(mutex_owned(&sc->sc_lock)); 2797 2798 /* 2799 * Make sure all TDs are marked as inactive. 2800 * Wait for completion. 2801 * Unschedule. 2802 * Deallocate. 2803 */ 2804 iso = &upipe->u.iso; 2805 2806 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2807 std = iso->stds[i]; 2808 usb_syncmem(&std->dma, 2809 std->offs + offsetof(uhci_td_t, td_status), 2810 sizeof(std->td.td_status), 2811 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2812 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2813 usb_syncmem(&std->dma, 2814 std->offs + offsetof(uhci_td_t, td_status), 2815 sizeof(std->td.td_status), 2816 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2817 } 2818 /* wait for completion */ 2819 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2820 2821 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2822 std = iso->stds[i]; 2823 for (vstd = sc->sc_vframes[i].htd; 2824 vstd != NULL && vstd->link.std != std; 2825 vstd = vstd->link.std) 2826 ; 2827 if (vstd == NULL) { 2828 /*panic*/ 2829 printf("uhci_device_isoc_close: %p not found\n", std); 2830 mutex_exit(&sc->sc_lock); 2831 return; 2832 } 2833 vstd->link = std->link; 2834 usb_syncmem(&std->dma, 2835 std->offs + offsetof(uhci_td_t, td_link), 2836 sizeof(std->td.td_link), 2837 BUS_DMASYNC_POSTWRITE); 2838 vstd->td.td_link = std->td.td_link; 2839 usb_syncmem(&vstd->dma, 2840 vstd->offs + offsetof(uhci_td_t, td_link), 2841 sizeof(vstd->td.td_link), 2842 BUS_DMASYNC_PREWRITE); 2843 uhci_free_std(sc, std); 2844 } 2845 2846 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2847 } 2848 2849 usbd_status 2850 uhci_setup_isoc(usbd_pipe_handle pipe) 2851 { 2852 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2853 usbd_device_handle dev = upipe->pipe.up_dev; 2854 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2855 int addr = upipe->pipe.up_dev->ud_addr; 2856 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2857 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2858 uhci_soft_td_t *std, *vstd; 2859 uint32_t token; 2860 struct iso *iso; 2861 int i; 2862 2863 iso = &upipe->u.iso; 2864 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2865 sizeof (uhci_soft_td_t *), 2866 KM_SLEEP); 2867 if (iso->stds == NULL) 2868 return USBD_NOMEM; 2869 2870 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2871 UHCI_TD_OUT(0, endpt, addr, 0); 2872 2873 mutex_enter(&sc->sc_lock); 2874 2875 /* Allocate the TDs and mark as inactive; */ 2876 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2877 std = uhci_alloc_std(sc); 2878 if (std == 0) 2879 goto bad; 2880 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2881 std->td.td_token = htole32(token); 2882 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2883 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2884 iso->stds[i] = std; 2885 } 2886 2887 /* Insert TDs into schedule. */ 2888 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2889 std = iso->stds[i]; 2890 vstd = sc->sc_vframes[i].htd; 2891 usb_syncmem(&vstd->dma, 2892 vstd->offs + offsetof(uhci_td_t, td_link), 2893 sizeof(vstd->td.td_link), 2894 BUS_DMASYNC_POSTWRITE); 2895 std->link = vstd->link; 2896 std->td.td_link = vstd->td.td_link; 2897 usb_syncmem(&std->dma, 2898 std->offs + offsetof(uhci_td_t, td_link), 2899 sizeof(std->td.td_link), 2900 BUS_DMASYNC_PREWRITE); 2901 vstd->link.std = std; 2902 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2903 usb_syncmem(&vstd->dma, 2904 vstd->offs + offsetof(uhci_td_t, td_link), 2905 sizeof(vstd->td.td_link), 2906 BUS_DMASYNC_PREWRITE); 2907 } 2908 mutex_exit(&sc->sc_lock); 2909 2910 iso->next = -1; 2911 iso->inuse = 0; 2912 2913 return (USBD_NORMAL_COMPLETION); 2914 2915 bad: 2916 while (--i >= 0) 2917 uhci_free_std(sc, iso->stds[i]); 2918 mutex_exit(&sc->sc_lock); 2919 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2920 return (USBD_NOMEM); 2921 } 2922 2923 void 2924 uhci_device_isoc_done(usbd_xfer_handle xfer) 2925 { 2926 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2927 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2928 int i, offs; 2929 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2930 2931 2932 DPRINTFN(4, ("uhci_isoc_done: length=%d, ux_state=0x%08x\n", 2933 xfer->ux_actlen, xfer->ux_state)); 2934 2935 if (ii->xfer != xfer) 2936 /* Not on interrupt list, ignore it. */ 2937 return; 2938 2939 if (!uhci_active_intr_info(ii)) 2940 return; 2941 2942 #ifdef DIAGNOSTIC 2943 if (ii->stdend == NULL) { 2944 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2945 #ifdef UHCI_DEBUG 2946 uhci_dump_ii(ii); 2947 #endif 2948 return; 2949 } 2950 #endif 2951 2952 /* Turn off the interrupt since it is active even if the TD is not. */ 2953 usb_syncmem(&ii->stdend->dma, 2954 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2955 sizeof(ii->stdend->td.td_status), 2956 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2957 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2958 usb_syncmem(&ii->stdend->dma, 2959 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2960 sizeof(ii->stdend->td.td_status), 2961 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2962 2963 uhci_del_intr_info(ii); /* remove from active list */ 2964 2965 offs = 0; 2966 for (i = 0; i < xfer->ux_nframes; i++) { 2967 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2968 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2969 offs += xfer->ux_frlengths[i]; 2970 } 2971 } 2972 2973 void 2974 uhci_device_intr_done(usbd_xfer_handle xfer) 2975 { 2976 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2977 uhci_softc_t *sc = ii->sc; 2978 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2979 uhci_soft_qh_t *sqh; 2980 int i, npoll, isread; 2981 2982 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->ux_actlen)); 2983 2984 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2985 2986 npoll = upipe->u.intr.npoll; 2987 for(i = 0; i < npoll; i++) { 2988 sqh = upipe->u.intr.qhs[i]; 2989 sqh->elink = NULL; 2990 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2991 usb_syncmem(&sqh->dma, 2992 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2993 sizeof(sqh->qh.qh_elink), 2994 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2995 } 2996 uhci_free_std_chain(sc, ii->stdstart, NULL); 2997 2998 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2999 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3000 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3001 3002 /* XXX Wasteful. */ 3003 if (xfer->ux_pipe->up_repeat) { 3004 uhci_soft_td_t *data, *dataend; 3005 3006 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3007 3008 /* This alloc cannot fail since we freed the chain above. */ 3009 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3010 upipe->u.intr.isread, xfer->ux_flags, 3011 &xfer->ux_dmabuf, &data, &dataend); 3012 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3013 usb_syncmem(&dataend->dma, 3014 dataend->offs + offsetof(uhci_td_t, td_status), 3015 sizeof(dataend->td.td_status), 3016 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3017 3018 #ifdef UHCI_DEBUG 3019 if (uhcidebug > 10) { 3020 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3021 uhci_dump_tds(data); 3022 uhci_dump_qh(upipe->u.intr.qhs[0]); 3023 } 3024 #endif 3025 3026 ii->stdstart = data; 3027 ii->stdend = dataend; 3028 #ifdef DIAGNOSTIC 3029 if (!ii->isdone) { 3030 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3031 } 3032 ii->isdone = 0; 3033 #endif 3034 for (i = 0; i < npoll; i++) { 3035 sqh = upipe->u.intr.qhs[i]; 3036 sqh->elink = data; 3037 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3038 usb_syncmem(&sqh->dma, 3039 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3040 sizeof(sqh->qh.qh_elink), 3041 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3042 } 3043 xfer->ux_status = USBD_IN_PROGRESS; 3044 /* The ii is already on the examined list, just leave it. */ 3045 } else { 3046 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3047 if (uhci_active_intr_info(ii)) 3048 uhci_del_intr_info(ii); 3049 } 3050 } 3051 3052 /* Deallocate request data structures */ 3053 void 3054 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3055 { 3056 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3057 uhci_softc_t *sc = ii->sc; 3058 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3059 int len = UGETW(xfer->ux_request.wLength); 3060 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3061 3062 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3063 3064 #ifdef DIAGNOSTIC 3065 if (!(xfer->ux_rqflags & URQ_REQUEST)) 3066 panic("uhci_device_ctrl_done: not a request"); 3067 #endif 3068 3069 if (!uhci_active_intr_info(ii)) 3070 return; 3071 3072 uhci_del_intr_info(ii); /* remove from active list */ 3073 3074 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3075 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3076 else 3077 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3078 3079 if (upipe->u.ctl.length != 0) 3080 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3081 3082 if (len) { 3083 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3084 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3085 } 3086 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3087 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3088 3089 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->ux_actlen)); 3090 } 3091 3092 /* Deallocate request data structures */ 3093 void 3094 uhci_device_bulk_done(usbd_xfer_handle xfer) 3095 { 3096 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3097 uhci_softc_t *sc = ii->sc; 3098 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3099 3100 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3101 xfer, ii, sc, upipe)); 3102 3103 KASSERT(mutex_owned(&sc->sc_lock)); 3104 3105 if (!uhci_active_intr_info(ii)) 3106 return; 3107 3108 uhci_del_intr_info(ii); /* remove from active list */ 3109 3110 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3111 3112 uhci_free_std_chain(sc, ii->stdstart, NULL); 3113 3114 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->ux_actlen)); 3115 } 3116 3117 /* Add interrupt QH, called with vflock. */ 3118 void 3119 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3120 { 3121 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3122 uhci_soft_qh_t *eqh; 3123 3124 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3125 3126 eqh = vf->eqh; 3127 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3128 sizeof(eqh->qh.qh_hlink), 3129 BUS_DMASYNC_POSTWRITE); 3130 sqh->hlink = eqh->hlink; 3131 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3132 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3133 sizeof(sqh->qh.qh_hlink), 3134 BUS_DMASYNC_PREWRITE); 3135 eqh->hlink = sqh; 3136 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3137 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3138 sizeof(eqh->qh.qh_hlink), 3139 BUS_DMASYNC_PREWRITE); 3140 vf->eqh = sqh; 3141 vf->bandwidth++; 3142 } 3143 3144 /* Remove interrupt QH. */ 3145 void 3146 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3147 { 3148 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3149 uhci_soft_qh_t *pqh; 3150 3151 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3152 3153 /* See comment in uhci_remove_ctrl() */ 3154 3155 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3156 sizeof(sqh->qh.qh_elink), 3157 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3158 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3159 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3160 usb_syncmem(&sqh->dma, 3161 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3162 sizeof(sqh->qh.qh_elink), 3163 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3164 delay(UHCI_QH_REMOVE_DELAY); 3165 } 3166 3167 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3168 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3169 sizeof(sqh->qh.qh_hlink), 3170 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3171 pqh->hlink = sqh->hlink; 3172 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3173 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3174 sizeof(pqh->qh.qh_hlink), 3175 BUS_DMASYNC_PREWRITE); 3176 delay(UHCI_QH_REMOVE_DELAY); 3177 if (vf->eqh == sqh) 3178 vf->eqh = pqh; 3179 vf->bandwidth--; 3180 } 3181 3182 usbd_status 3183 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3184 { 3185 uhci_soft_qh_t *sqh; 3186 int i, npoll; 3187 u_int bestbw, bw, bestoffs, offs; 3188 3189 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3190 if (ival == 0) { 3191 printf("uhci_device_setintr: 0 interval\n"); 3192 return (USBD_INVAL); 3193 } 3194 3195 if (ival > UHCI_VFRAMELIST_COUNT) 3196 ival = UHCI_VFRAMELIST_COUNT; 3197 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3198 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3199 3200 upipe->u.intr.npoll = npoll; 3201 upipe->u.intr.qhs = 3202 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3203 if (upipe->u.intr.qhs == NULL) 3204 return USBD_NOMEM; 3205 3206 /* 3207 * Figure out which offset in the schedule that has most 3208 * bandwidth left over. 3209 */ 3210 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3211 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3212 for (bw = i = 0; i < npoll; i++) 3213 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3214 if (bw < bestbw) { 3215 bestbw = bw; 3216 bestoffs = offs; 3217 } 3218 } 3219 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3220 3221 mutex_enter(&sc->sc_lock); 3222 for(i = 0; i < npoll; i++) { 3223 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3224 sqh->elink = NULL; 3225 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3226 usb_syncmem(&sqh->dma, 3227 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3228 sizeof(sqh->qh.qh_elink), 3229 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3230 sqh->pos = MOD(i * ival + bestoffs); 3231 } 3232 #undef MOD 3233 3234 /* Enter QHs into the controller data structures. */ 3235 for(i = 0; i < npoll; i++) 3236 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3237 mutex_exit(&sc->sc_lock); 3238 3239 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3240 return (USBD_NORMAL_COMPLETION); 3241 } 3242 3243 /* Open a new pipe. */ 3244 usbd_status 3245 uhci_open(usbd_pipe_handle pipe) 3246 { 3247 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3248 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3249 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3250 usbd_status err = USBD_NOMEM; 3251 int ival; 3252 3253 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3254 pipe, pipe->up_dev->ud_addr, 3255 ed->bEndpointAddress, sc->sc_addr)); 3256 3257 if (sc->sc_dying) 3258 return USBD_IOERROR; 3259 3260 upipe->aborting = 0; 3261 /* toggle state needed for bulk endpoints */ 3262 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3263 3264 if (pipe->up_dev->ud_addr == sc->sc_addr) { 3265 switch (ed->bEndpointAddress) { 3266 case USB_CONTROL_ENDPOINT: 3267 pipe->up_methods = &uhci_root_ctrl_methods; 3268 break; 3269 case UE_DIR_IN | UHCI_INTR_ENDPT: 3270 pipe->up_methods = &uhci_root_intr_methods; 3271 break; 3272 default: 3273 return (USBD_INVAL); 3274 } 3275 } else { 3276 switch (ed->bmAttributes & UE_XFERTYPE) { 3277 case UE_CONTROL: 3278 pipe->up_methods = &uhci_device_ctrl_methods; 3279 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3280 if (upipe->u.ctl.sqh == NULL) 3281 goto bad; 3282 upipe->u.ctl.setup = uhci_alloc_std(sc); 3283 if (upipe->u.ctl.setup == NULL) { 3284 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3285 goto bad; 3286 } 3287 upipe->u.ctl.stat = uhci_alloc_std(sc); 3288 if (upipe->u.ctl.stat == NULL) { 3289 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3290 uhci_free_std(sc, upipe->u.ctl.setup); 3291 goto bad; 3292 } 3293 err = usb_allocmem(&sc->sc_bus, 3294 sizeof(usb_device_request_t), 3295 0, &upipe->u.ctl.reqdma); 3296 if (err) { 3297 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3298 uhci_free_std(sc, upipe->u.ctl.setup); 3299 uhci_free_std(sc, upipe->u.ctl.stat); 3300 goto bad; 3301 } 3302 break; 3303 case UE_INTERRUPT: 3304 pipe->up_methods = &uhci_device_intr_methods; 3305 ival = pipe->up_interval; 3306 if (ival == USBD_DEFAULT_INTERVAL) 3307 ival = ed->bInterval; 3308 return (uhci_device_setintr(sc, upipe, ival)); 3309 case UE_ISOCHRONOUS: 3310 pipe->up_methods = &uhci_device_isoc_methods; 3311 return (uhci_setup_isoc(pipe)); 3312 case UE_BULK: 3313 pipe->up_methods = &uhci_device_bulk_methods; 3314 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3315 if (upipe->u.bulk.sqh == NULL) 3316 goto bad; 3317 break; 3318 } 3319 } 3320 return (USBD_NORMAL_COMPLETION); 3321 3322 bad: 3323 return USBD_NOMEM; 3324 } 3325 3326 /* 3327 * Data structures and routines to emulate the root hub. 3328 */ 3329 usb_device_descriptor_t uhci_devd = { 3330 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 3331 .bDescriptorType = UDESC_DEVICE, 3332 .bcdUSB = {0x00, 0x01}, 3333 .bDeviceClass = UDCLASS_HUB, 3334 .bDeviceSubClass = UDSUBCLASS_HUB, 3335 .bDeviceProtocol = UDPROTO_FSHUB, 3336 .bMaxPacketSize = 64, 3337 .idVendor = {0}, 3338 .idProduct = {0}, 3339 .bcdDevice = {0x00,0x01}, 3340 .iManufacturer = 1, 3341 .iProduct = 2, 3342 .iSerialNumber = 0, 3343 .bNumConfigurations = 1 3344 }; 3345 3346 const usb_config_descriptor_t uhci_confd = { 3347 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 3348 .bDescriptorType = UDESC_CONFIG, 3349 .wTotalLength = USETWD( 3350 USB_CONFIG_DESCRIPTOR_SIZE + 3351 USB_INTERFACE_DESCRIPTOR_SIZE + 3352 USB_ENDPOINT_DESCRIPTOR_SIZE), 3353 .bNumInterface = 1, 3354 .bConfigurationValue = 1, 3355 .iConfiguration = 0, 3356 .bmAttributes = UC_ATTR_MBO | UC_SELF_POWERED, 3357 .bMaxPower = 0 3358 }; 3359 3360 const usb_interface_descriptor_t uhci_ifcd = { 3361 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 3362 .bDescriptorType = UDESC_INTERFACE, 3363 .bInterfaceNumber = 0, 3364 .bAlternateSetting = 0, 3365 .bNumEndpoints = 1, 3366 .bInterfaceClass = UICLASS_HUB, 3367 .bInterfaceSubClass = UISUBCLASS_HUB, 3368 .bInterfaceProtocol = UIPROTO_FSHUB, 3369 .iInterface = 0 3370 }; 3371 3372 const usb_endpoint_descriptor_t uhci_endpd = { 3373 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 3374 .bDescriptorType = UDESC_ENDPOINT, 3375 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 3376 .bmAttributes = UE_INTERRUPT, 3377 .wMaxPacketSize = USETWD(8), 3378 .bInterval = 255 3379 }; 3380 3381 const usb_hub_descriptor_t uhci_hubd_piix = { 3382 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 3383 .bDescriptorType = UDESC_HUB, 3384 .bNbrPorts = 2, 3385 .wHubCharacteristics = USETWD(UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL), 3386 .bPwrOn2PwrGood = 50, 3387 .bHubContrCurrent = 0, 3388 .DeviceRemovable = { 0x00 }, 3389 .PortPowerCtrlMask = { 0 }, 3390 }; 3391 3392 /* 3393 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3394 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3395 * should not be used by the USB subsystem. As we cannot issue a 3396 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3397 * will be enabled as part of the reset. 3398 * 3399 * On the VT83C572, the port cannot be successfully enabled until the 3400 * outstanding "port enable change" and "connection status change" 3401 * events have been reset. 3402 */ 3403 Static usbd_status 3404 uhci_portreset(uhci_softc_t *sc, int index) 3405 { 3406 int lim, port, x; 3407 3408 if (index == 1) 3409 port = UHCI_PORTSC1; 3410 else if (index == 2) 3411 port = UHCI_PORTSC2; 3412 else 3413 return (USBD_IOERROR); 3414 3415 x = URWMASK(UREAD2(sc, port)); 3416 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3417 3418 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3419 3420 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3421 index, UREAD2(sc, port))); 3422 3423 x = URWMASK(UREAD2(sc, port)); 3424 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3425 3426 delay(100); 3427 3428 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3429 index, UREAD2(sc, port))); 3430 3431 x = URWMASK(UREAD2(sc, port)); 3432 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3433 3434 for (lim = 10; --lim > 0;) { 3435 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3436 3437 x = UREAD2(sc, port); 3438 3439 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3440 index, lim, x)); 3441 3442 if (!(x & UHCI_PORTSC_CCS)) { 3443 /* 3444 * No device is connected (or was disconnected 3445 * during reset). Consider the port reset. 3446 * The delay must be long enough to ensure on 3447 * the initial iteration that the device 3448 * connection will have been registered. 50ms 3449 * appears to be sufficient, but 20ms is not. 3450 */ 3451 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3452 index, lim)); 3453 break; 3454 } 3455 3456 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3457 /* 3458 * Port enabled changed and/or connection 3459 * status changed were set. Reset either or 3460 * both raised flags (by writing a 1 to that 3461 * bit), and wait again for state to settle. 3462 */ 3463 UWRITE2(sc, port, URWMASK(x) | 3464 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3465 continue; 3466 } 3467 3468 if (x & UHCI_PORTSC_PE) 3469 /* Port is enabled */ 3470 break; 3471 3472 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3473 } 3474 3475 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3476 index, UREAD2(sc, port))); 3477 3478 if (lim <= 0) { 3479 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3480 return (USBD_TIMEOUT); 3481 } 3482 3483 sc->sc_isreset = 1; 3484 return (USBD_NORMAL_COMPLETION); 3485 } 3486 3487 /* 3488 * Simulate a hardware hub by handling all the necessary requests. 3489 */ 3490 usbd_status 3491 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3492 { 3493 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3494 usbd_status err; 3495 3496 /* Insert last in queue. */ 3497 mutex_enter(&sc->sc_lock); 3498 err = usb_insert_transfer(xfer); 3499 mutex_exit(&sc->sc_lock); 3500 if (err) 3501 return (err); 3502 3503 /* 3504 * Pipe isn't running (otherwise err would be USBD_INPROG), 3505 * so start it first. 3506 */ 3507 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 3508 } 3509 3510 usbd_status 3511 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3512 { 3513 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3514 usb_device_request_t *req; 3515 void *buf = NULL; 3516 int port, x; 3517 int len, value, index, status, change, l, totlen = 0; 3518 usb_port_status_t ps; 3519 usbd_status err; 3520 3521 if (sc->sc_dying) 3522 return (USBD_IOERROR); 3523 3524 #ifdef DIAGNOSTIC 3525 if (!(xfer->ux_rqflags & URQ_REQUEST)) 3526 panic("uhci_root_ctrl_start: not a request"); 3527 #endif 3528 req = &xfer->ux_request; 3529 3530 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3531 req->bmRequestType, req->bRequest)); 3532 3533 len = UGETW(req->wLength); 3534 value = UGETW(req->wValue); 3535 index = UGETW(req->wIndex); 3536 3537 if (len != 0) 3538 buf = xfer->ux_buf; 3539 3540 #define C(x,y) ((x) | ((y) << 8)) 3541 switch(C(req->bRequest, req->bmRequestType)) { 3542 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3543 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3544 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3545 /* 3546 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3547 * for the integrated root hub. 3548 */ 3549 break; 3550 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3551 if (len > 0) { 3552 *(uint8_t *)buf = sc->sc_conf; 3553 totlen = 1; 3554 } 3555 break; 3556 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3557 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3558 if (len == 0) 3559 break; 3560 switch(value >> 8) { 3561 case UDESC_DEVICE: 3562 if ((value & 0xff) != 0) { 3563 err = USBD_IOERROR; 3564 goto ret; 3565 } 3566 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3567 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3568 memcpy(buf, &uhci_devd, l); 3569 break; 3570 case UDESC_CONFIG: 3571 if ((value & 0xff) != 0) { 3572 err = USBD_IOERROR; 3573 goto ret; 3574 } 3575 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3576 memcpy(buf, &uhci_confd, l); 3577 buf = (char *)buf + l; 3578 len -= l; 3579 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3580 totlen += l; 3581 memcpy(buf, &uhci_ifcd, l); 3582 buf = (char *)buf + l; 3583 len -= l; 3584 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3585 totlen += l; 3586 memcpy(buf, &uhci_endpd, l); 3587 break; 3588 case UDESC_STRING: 3589 #define sd ((usb_string_descriptor_t *)buf) 3590 switch (value & 0xff) { 3591 case 0: /* Language table */ 3592 totlen = usb_makelangtbl(sd, len); 3593 break; 3594 case 1: /* Vendor */ 3595 totlen = usb_makestrdesc(sd, len, 3596 sc->sc_vendor); 3597 break; 3598 case 2: /* Product */ 3599 totlen = usb_makestrdesc(sd, len, 3600 "UHCI root hub"); 3601 break; 3602 } 3603 #undef sd 3604 break; 3605 default: 3606 err = USBD_IOERROR; 3607 goto ret; 3608 } 3609 break; 3610 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3611 if (len > 0) { 3612 *(uint8_t *)buf = 0; 3613 totlen = 1; 3614 } 3615 break; 3616 case C(UR_GET_STATUS, UT_READ_DEVICE): 3617 if (len > 1) { 3618 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3619 totlen = 2; 3620 } 3621 break; 3622 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3623 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3624 if (len > 1) { 3625 USETW(((usb_status_t *)buf)->wStatus, 0); 3626 totlen = 2; 3627 } 3628 break; 3629 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3630 if (value >= USB_MAX_DEVICES) { 3631 err = USBD_IOERROR; 3632 goto ret; 3633 } 3634 sc->sc_addr = value; 3635 break; 3636 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3637 if (value != 0 && value != 1) { 3638 err = USBD_IOERROR; 3639 goto ret; 3640 } 3641 sc->sc_conf = value; 3642 break; 3643 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3644 break; 3645 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3646 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3647 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3648 err = USBD_IOERROR; 3649 goto ret; 3650 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3651 break; 3652 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3653 break; 3654 /* Hub requests */ 3655 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3656 break; 3657 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3658 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3659 "port=%d feature=%d\n", 3660 index, value)); 3661 if (index == 1) 3662 port = UHCI_PORTSC1; 3663 else if (index == 2) 3664 port = UHCI_PORTSC2; 3665 else { 3666 err = USBD_IOERROR; 3667 goto ret; 3668 } 3669 switch(value) { 3670 case UHF_PORT_ENABLE: 3671 x = URWMASK(UREAD2(sc, port)); 3672 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3673 break; 3674 case UHF_PORT_SUSPEND: 3675 x = URWMASK(UREAD2(sc, port)); 3676 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3677 break; 3678 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3679 /* see USB2 spec ch. 7.1.7.7 */ 3680 usb_delay_ms(&sc->sc_bus, 20); 3681 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3682 /* 10ms resume delay must be provided by caller */ 3683 break; 3684 case UHF_PORT_RESET: 3685 x = URWMASK(UREAD2(sc, port)); 3686 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3687 break; 3688 case UHF_C_PORT_CONNECTION: 3689 x = URWMASK(UREAD2(sc, port)); 3690 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3691 break; 3692 case UHF_C_PORT_ENABLE: 3693 x = URWMASK(UREAD2(sc, port)); 3694 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3695 break; 3696 case UHF_C_PORT_OVER_CURRENT: 3697 x = URWMASK(UREAD2(sc, port)); 3698 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3699 break; 3700 case UHF_C_PORT_RESET: 3701 sc->sc_isreset = 0; 3702 err = USBD_NORMAL_COMPLETION; 3703 goto ret; 3704 case UHF_PORT_CONNECTION: 3705 case UHF_PORT_OVER_CURRENT: 3706 case UHF_PORT_POWER: 3707 case UHF_PORT_LOW_SPEED: 3708 case UHF_C_PORT_SUSPEND: 3709 default: 3710 err = USBD_IOERROR; 3711 goto ret; 3712 } 3713 break; 3714 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3715 if (index == 1) 3716 port = UHCI_PORTSC1; 3717 else if (index == 2) 3718 port = UHCI_PORTSC2; 3719 else { 3720 err = USBD_IOERROR; 3721 goto ret; 3722 } 3723 if (len > 0) { 3724 *(uint8_t *)buf = 3725 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3726 UHCI_PORTSC_LS_SHIFT; 3727 totlen = 1; 3728 } 3729 break; 3730 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3731 if (len == 0) 3732 break; 3733 if ((value & 0xff) != 0) { 3734 err = USBD_IOERROR; 3735 goto ret; 3736 } 3737 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3738 totlen = l; 3739 memcpy(buf, &uhci_hubd_piix, l); 3740 break; 3741 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3742 if (len != 4) { 3743 err = USBD_IOERROR; 3744 goto ret; 3745 } 3746 memset(buf, 0, len); 3747 totlen = len; 3748 break; 3749 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3750 if (index == 1) 3751 port = UHCI_PORTSC1; 3752 else if (index == 2) 3753 port = UHCI_PORTSC2; 3754 else { 3755 err = USBD_IOERROR; 3756 goto ret; 3757 } 3758 if (len != 4) { 3759 err = USBD_IOERROR; 3760 goto ret; 3761 } 3762 x = UREAD2(sc, port); 3763 status = change = 0; 3764 if (x & UHCI_PORTSC_CCS) 3765 status |= UPS_CURRENT_CONNECT_STATUS; 3766 if (x & UHCI_PORTSC_CSC) 3767 change |= UPS_C_CONNECT_STATUS; 3768 if (x & UHCI_PORTSC_PE) 3769 status |= UPS_PORT_ENABLED; 3770 if (x & UHCI_PORTSC_POEDC) 3771 change |= UPS_C_PORT_ENABLED; 3772 if (x & UHCI_PORTSC_OCI) 3773 status |= UPS_OVERCURRENT_INDICATOR; 3774 if (x & UHCI_PORTSC_OCIC) 3775 change |= UPS_C_OVERCURRENT_INDICATOR; 3776 if (x & UHCI_PORTSC_SUSP) 3777 status |= UPS_SUSPEND; 3778 if (x & UHCI_PORTSC_LSDA) 3779 status |= UPS_LOW_SPEED; 3780 status |= UPS_PORT_POWER; 3781 if (sc->sc_isreset) 3782 change |= UPS_C_PORT_RESET; 3783 USETW(ps.wPortStatus, status); 3784 USETW(ps.wPortChange, change); 3785 l = min(len, sizeof ps); 3786 memcpy(buf, &ps, l); 3787 totlen = l; 3788 break; 3789 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3790 err = USBD_IOERROR; 3791 goto ret; 3792 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3793 break; 3794 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3795 if (index == 1) 3796 port = UHCI_PORTSC1; 3797 else if (index == 2) 3798 port = UHCI_PORTSC2; 3799 else { 3800 err = USBD_IOERROR; 3801 goto ret; 3802 } 3803 switch(value) { 3804 case UHF_PORT_ENABLE: 3805 x = URWMASK(UREAD2(sc, port)); 3806 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3807 break; 3808 case UHF_PORT_SUSPEND: 3809 x = URWMASK(UREAD2(sc, port)); 3810 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3811 break; 3812 case UHF_PORT_RESET: 3813 err = uhci_portreset(sc, index); 3814 goto ret; 3815 case UHF_PORT_POWER: 3816 /* Pretend we turned on power */ 3817 err = USBD_NORMAL_COMPLETION; 3818 goto ret; 3819 case UHF_C_PORT_CONNECTION: 3820 case UHF_C_PORT_ENABLE: 3821 case UHF_C_PORT_OVER_CURRENT: 3822 case UHF_PORT_CONNECTION: 3823 case UHF_PORT_OVER_CURRENT: 3824 case UHF_PORT_LOW_SPEED: 3825 case UHF_C_PORT_SUSPEND: 3826 case UHF_C_PORT_RESET: 3827 default: 3828 err = USBD_IOERROR; 3829 goto ret; 3830 } 3831 break; 3832 default: 3833 err = USBD_IOERROR; 3834 goto ret; 3835 } 3836 xfer->ux_actlen = totlen; 3837 err = USBD_NORMAL_COMPLETION; 3838 ret: 3839 xfer->ux_status = err; 3840 mutex_enter(&sc->sc_lock); 3841 usb_transfer_complete(xfer); 3842 mutex_exit(&sc->sc_lock); 3843 return (USBD_IN_PROGRESS); 3844 } 3845 3846 /* Abort a root control request. */ 3847 void 3848 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3849 { 3850 /* Nothing to do, all transfers are synchronous. */ 3851 } 3852 3853 /* Close the root pipe. */ 3854 void 3855 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3856 { 3857 DPRINTF(("uhci_root_ctrl_close\n")); 3858 } 3859 3860 /* Abort a root interrupt request. */ 3861 void 3862 uhci_root_intr_abort(usbd_xfer_handle xfer) 3863 { 3864 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3865 3866 KASSERT(mutex_owned(&sc->sc_lock)); 3867 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3868 3869 callout_stop(&sc->sc_poll_handle); 3870 sc->sc_intr_xfer = NULL; 3871 3872 xfer->ux_status = USBD_CANCELLED; 3873 #ifdef DIAGNOSTIC 3874 UXFER(xfer)->iinfo.isdone = 1; 3875 #endif 3876 usb_transfer_complete(xfer); 3877 } 3878 3879 usbd_status 3880 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3881 { 3882 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3883 usbd_status err; 3884 3885 /* Insert last in queue. */ 3886 mutex_enter(&sc->sc_lock); 3887 err = usb_insert_transfer(xfer); 3888 mutex_exit(&sc->sc_lock); 3889 if (err) 3890 return (err); 3891 3892 /* 3893 * Pipe isn't running (otherwise err would be USBD_INPROG), 3894 * start first 3895 */ 3896 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 3897 } 3898 3899 /* Start a transfer on the root interrupt pipe */ 3900 usbd_status 3901 uhci_root_intr_start(usbd_xfer_handle xfer) 3902 { 3903 usbd_pipe_handle pipe = xfer->ux_pipe; 3904 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3905 unsigned int ival; 3906 3907 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3908 xfer, xfer->ux_length, xfer->ux_flags)); 3909 3910 if (sc->sc_dying) 3911 return (USBD_IOERROR); 3912 3913 /* XXX temporary variable needed to avoid gcc3 warning */ 3914 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3915 sc->sc_ival = mstohz(ival); 3916 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3917 sc->sc_intr_xfer = xfer; 3918 return (USBD_IN_PROGRESS); 3919 } 3920 3921 /* Close the root interrupt pipe. */ 3922 void 3923 uhci_root_intr_close(usbd_pipe_handle pipe) 3924 { 3925 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3926 3927 KASSERT(mutex_owned(&sc->sc_lock)); 3928 3929 callout_stop(&sc->sc_poll_handle); 3930 sc->sc_intr_xfer = NULL; 3931 DPRINTF(("uhci_root_intr_close\n")); 3932 } 3933
Indexes created Tue Sep 30 20:09:53 GMT 2025