uhci.c revision 1.264.4.14
1 /* $NetBSD: uhci.c,v 1.264.4.14 2014/12/05 13:23:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.14 2014/12/05 13:23:38 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run, int locked); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 169 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 170 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 171 Static int uhci_roothub_ctrl(struct usbd_bus *, 172 usb_device_request_t *, void *, int); 173 174 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 175 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 176 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 177 Static void uhci_device_ctrl_close(usbd_pipe_handle); 178 Static void uhci_device_ctrl_done(usbd_xfer_handle); 179 180 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 182 Static void uhci_device_intr_abort(usbd_xfer_handle); 183 Static void uhci_device_intr_close(usbd_pipe_handle); 184 Static void uhci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 187 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 188 Static void uhci_device_bulk_abort(usbd_xfer_handle); 189 Static void uhci_device_bulk_close(usbd_pipe_handle); 190 Static void uhci_device_bulk_done(usbd_xfer_handle); 191 192 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 193 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 194 Static void uhci_device_isoc_abort(usbd_xfer_handle); 195 Static void uhci_device_isoc_close(usbd_pipe_handle); 196 Static void uhci_device_isoc_done(usbd_xfer_handle); 197 198 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 199 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 200 Static void uhci_root_intr_abort(usbd_xfer_handle); 201 Static void uhci_root_intr_close(usbd_pipe_handle); 202 Static void uhci_root_intr_done(usbd_xfer_handle); 203 204 Static usbd_status uhci_open(usbd_pipe_handle); 205 Static void uhci_poll(struct usbd_bus *); 206 Static void uhci_softintr(void *); 207 208 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 209 210 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 211 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 212 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 213 struct uhci_pipe *pipe, int ival); 214 215 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 216 Static void uhci_noop(usbd_pipe_handle pipe); 217 218 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 219 uhci_soft_qh_t *); 220 221 #ifdef UHCI_DEBUG 222 Static void uhci_dump_all(uhci_softc_t *); 223 Static void uhci_dumpregs(uhci_softc_t *); 224 Static void uhci_dump_qhs(uhci_soft_qh_t *); 225 Static void uhci_dump_qh(uhci_soft_qh_t *); 226 Static void uhci_dump_tds(uhci_soft_td_t *); 227 Static void uhci_dump_td(uhci_soft_td_t *); 228 Static void uhci_dump_ii(uhci_intr_info_t *ii); 229 void uhci_dump(void); 230 #endif 231 232 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 233 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 234 #define UWRITE1(sc, r, x) \ 235 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 236 } while (/*CONSTCOND*/0) 237 #define UWRITE2(sc, r, x) \ 238 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 239 } while (/*CONSTCOND*/0) 240 #define UWRITE4(sc, r, x) \ 241 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 242 } while (/*CONSTCOND*/0) 243 static __inline uint8_t 244 UREAD1(uhci_softc_t *sc, bus_size_t r) 245 { 246 247 UBARR(sc); 248 return bus_space_read_1(sc->iot, sc->ioh, r); 249 } 250 251 static __inline uint16_t 252 UREAD2(uhci_softc_t *sc, bus_size_t r) 253 { 254 255 UBARR(sc); 256 return bus_space_read_2(sc->iot, sc->ioh, r); 257 } 258 259 #ifdef UHCI_DEBUG 260 static __inline uint32_t 261 UREAD4(uhci_softc_t *sc, bus_size_t r) 262 { 263 264 UBARR(sc); 265 return bus_space_read_4(sc->iot, sc->ioh, r); 266 } 267 #endif 268 269 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 270 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 271 272 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 273 274 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 275 276 const struct usbd_bus_methods uhci_bus_methods = { 277 .ubm_open = uhci_open, 278 .ubm_softint = uhci_softintr, 279 .ubm_dopoll = uhci_poll, 280 .ubm_allocx = uhci_allocx, 281 .ubm_freex = uhci_freex, 282 .ubm_getlock = uhci_get_lock, 283 .ubm_rhctrl = uhci_roothub_ctrl, 284 }; 285 286 const struct usbd_pipe_methods uhci_root_intr_methods = { 287 .upm_transfer = uhci_root_intr_transfer, 288 .upm_start = uhci_root_intr_start, 289 .upm_abort = uhci_root_intr_abort, 290 .upm_close = uhci_root_intr_close, 291 .upm_cleartoggle = uhci_noop, 292 .upm_done = uhci_root_intr_done, 293 }; 294 295 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 296 .upm_transfer = uhci_device_ctrl_transfer, 297 .upm_start = uhci_device_ctrl_start, 298 .upm_abort = uhci_device_ctrl_abort, 299 .upm_close = uhci_device_ctrl_close, 300 .upm_cleartoggle = uhci_noop, 301 .upm_done = uhci_device_ctrl_done, 302 }; 303 304 const struct usbd_pipe_methods uhci_device_intr_methods = { 305 .upm_transfer = uhci_device_intr_transfer, 306 .upm_start = uhci_device_intr_start, 307 .upm_abort = uhci_device_intr_abort, 308 .upm_close = uhci_device_intr_close, 309 .upm_cleartoggle = uhci_device_clear_toggle, 310 .upm_done = uhci_device_intr_done, 311 }; 312 313 const struct usbd_pipe_methods uhci_device_bulk_methods = { 314 .upm_transfer = uhci_device_bulk_transfer, 315 .upm_start = uhci_device_bulk_start, 316 .upm_abort = uhci_device_bulk_abort, 317 .upm_close = uhci_device_bulk_close, 318 .upm_cleartoggle = uhci_device_clear_toggle, 319 .upm_done = uhci_device_bulk_done, 320 }; 321 322 const struct usbd_pipe_methods uhci_device_isoc_methods = { 323 .upm_transfer = uhci_device_isoc_transfer, 324 .upm_start = uhci_device_isoc_start, 325 .upm_abort = uhci_device_isoc_abort, 326 .upm_close = uhci_device_isoc_close, 327 .upm_cleartoggle = uhci_noop, 328 .upm_done = uhci_device_isoc_done, 329 }; 330 331 #define uhci_add_intr_info(sc, ii) \ 332 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 333 #define uhci_del_intr_info(ii) \ 334 do { \ 335 LIST_REMOVE((ii), list); \ 336 (ii)->list.le_prev = NULL; \ 337 } while (0) 338 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 339 340 static inline uhci_soft_qh_t * 341 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 342 { 343 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 344 345 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 346 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 347 usb_syncmem(&pqh->dma, 348 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 349 sizeof(pqh->qh.qh_hlink), 350 BUS_DMASYNC_POSTWRITE); 351 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 352 printf("uhci_find_prev_qh: QH not found\n"); 353 return NULL; 354 } 355 #endif 356 } 357 return pqh; 358 } 359 360 void 361 uhci_globalreset(uhci_softc_t *sc) 362 { 363 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 364 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 365 UHCICMD(sc, 0); /* do nothing */ 366 } 367 368 int 369 uhci_init(uhci_softc_t *sc) 370 { 371 usbd_status err; 372 int i, j; 373 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 374 uhci_soft_td_t *std; 375 376 DPRINTFN(1,("uhci_init: start\n")); 377 378 #ifdef UHCI_DEBUG 379 thesc = sc; 380 381 if (uhcidebug > 2) 382 uhci_dumpregs(sc); 383 #endif 384 385 sc->sc_suspend = PWR_RESUME; 386 387 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 388 uhci_globalreset(sc); /* reset the controller */ 389 uhci_reset(sc); 390 391 /* Allocate and initialize real frame array. */ 392 err = usb_allocmem(&sc->sc_bus, 393 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 394 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 395 if (err) 396 return err; 397 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 398 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 399 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 400 401 /* 402 * Allocate a TD, inactive, that hangs from the last QH. 403 * This is to avoid a bug in the PIIX that makes it run berserk 404 * otherwise. 405 */ 406 std = uhci_alloc_std(sc); 407 if (std == NULL) 408 return ENOMEM; 409 std->link.std = NULL; 410 std->td.td_link = htole32(UHCI_PTR_T); 411 std->td.td_status = htole32(0); /* inactive */ 412 std->td.td_token = htole32(0); 413 std->td.td_buffer = htole32(0); 414 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 415 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 416 417 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 418 lsqh = uhci_alloc_sqh(sc); 419 if (lsqh == NULL) 420 return ENOMEM; 421 lsqh->hlink = NULL; 422 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 423 lsqh->elink = std; 424 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 425 sc->sc_last_qh = lsqh; 426 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 427 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 428 429 /* Allocate the dummy QH where bulk traffic will be queued. */ 430 bsqh = uhci_alloc_sqh(sc); 431 if (bsqh == NULL) 432 return ENOMEM; 433 bsqh->hlink = lsqh; 434 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 435 bsqh->elink = NULL; 436 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 437 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 438 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 439 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 440 441 /* Allocate dummy QH where high speed control traffic will be queued. */ 442 chsqh = uhci_alloc_sqh(sc); 443 if (chsqh == NULL) 444 return ENOMEM; 445 chsqh->hlink = bsqh; 446 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 447 chsqh->elink = NULL; 448 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 449 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 450 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 452 453 /* Allocate dummy QH where control traffic will be queued. */ 454 clsqh = uhci_alloc_sqh(sc); 455 if (clsqh == NULL) 456 return ENOMEM; 457 clsqh->hlink = chsqh; 458 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 459 clsqh->elink = NULL; 460 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 461 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 462 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 463 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 464 465 /* 466 * Make all (virtual) frame list pointers point to the interrupt 467 * queue heads and the interrupt queue heads at the control 468 * queue head and point the physical frame list to the virtual. 469 */ 470 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 471 std = uhci_alloc_std(sc); 472 sqh = uhci_alloc_sqh(sc); 473 if (std == NULL || sqh == NULL) 474 return USBD_NOMEM; 475 std->link.sqh = sqh; 476 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 477 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 478 std->td.td_token = htole32(0); 479 std->td.td_buffer = htole32(0); 480 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 482 sqh->hlink = clsqh; 483 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 484 sqh->elink = NULL; 485 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 486 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 488 sc->sc_vframes[i].htd = std; 489 sc->sc_vframes[i].etd = std; 490 sc->sc_vframes[i].hqh = sqh; 491 sc->sc_vframes[i].eqh = sqh; 492 for (j = i; 493 j < UHCI_FRAMELIST_COUNT; 494 j += UHCI_VFRAMELIST_COUNT) 495 sc->sc_pframes[j] = htole32(std->physaddr); 496 } 497 usb_syncmem(&sc->sc_dma, 0, 498 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 499 BUS_DMASYNC_PREWRITE); 500 501 502 LIST_INIT(&sc->sc_intrhead); 503 504 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 505 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 506 507 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 508 509 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 510 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 511 cv_init(&sc->sc_softwake_cv, "uhciab"); 512 513 /* Set up the bus struct. */ 514 sc->sc_bus.ub_methods = &uhci_bus_methods; 515 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 516 sc->sc_bus.ub_usedma = true; 517 518 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 519 520 DPRINTFN(1,("uhci_init: enabling\n")); 521 522 err = uhci_run(sc, 1, 0); /* and here we go... */ 523 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 524 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 525 return err; 526 } 527 528 int 529 uhci_activate(device_t self, enum devact act) 530 { 531 struct uhci_softc *sc = device_private(self); 532 533 switch (act) { 534 case DVACT_DEACTIVATE: 535 sc->sc_dying = 1; 536 return 0; 537 default: 538 return EOPNOTSUPP; 539 } 540 } 541 542 void 543 uhci_childdet(device_t self, device_t child) 544 { 545 struct uhci_softc *sc = device_private(self); 546 547 KASSERT(sc->sc_child == child); 548 sc->sc_child = NULL; 549 } 550 551 int 552 uhci_detach(struct uhci_softc *sc, int flags) 553 { 554 int rv = 0; 555 556 if (sc->sc_child != NULL) 557 rv = config_detach(sc->sc_child, flags); 558 559 if (rv != 0) 560 return rv; 561 562 callout_halt(&sc->sc_poll_handle, NULL); 563 callout_destroy(&sc->sc_poll_handle); 564 565 cv_destroy(&sc->sc_softwake_cv); 566 567 mutex_destroy(&sc->sc_lock); 568 mutex_destroy(&sc->sc_intr_lock); 569 570 pool_cache_destroy(sc->sc_xferpool); 571 572 /* XXX free other data structures XXX */ 573 574 return rv; 575 } 576 577 usbd_xfer_handle 578 uhci_allocx(struct usbd_bus *bus) 579 { 580 struct uhci_softc *sc = bus->ub_hcpriv; 581 usbd_xfer_handle xfer; 582 583 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 584 if (xfer != NULL) { 585 memset(xfer, 0, sizeof(struct uhci_xfer)); 586 UXFER(xfer)->iinfo.sc = sc; 587 #ifdef DIAGNOSTIC 588 UXFER(xfer)->iinfo.isdone = 1; 589 xfer->ux_state = XFER_BUSY; 590 #endif 591 } 592 return xfer; 593 } 594 595 void 596 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 597 { 598 struct uhci_softc *sc = bus->ub_hcpriv; 599 600 #ifdef DIAGNOSTIC 601 if (xfer->ux_state != XFER_BUSY) { 602 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 603 xfer->ux_state); 604 } 605 xfer->ux_state = XFER_FREE; 606 if (!UXFER(xfer)->iinfo.isdone) { 607 printf("uhci_freex: !isdone\n"); 608 } 609 #endif 610 pool_cache_put(sc->sc_xferpool, xfer); 611 } 612 613 Static void 614 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 615 { 616 struct uhci_softc *sc = bus->ub_hcpriv; 617 618 *lock = &sc->sc_lock; 619 } 620 621 622 /* 623 * Handle suspend/resume. 624 * 625 * We need to switch to polling mode here, because this routine is 626 * called from an interrupt context. This is all right since we 627 * are almost suspended anyway. 628 */ 629 bool 630 uhci_resume(device_t dv, const pmf_qual_t *qual) 631 { 632 uhci_softc_t *sc = device_private(dv); 633 int cmd; 634 635 mutex_spin_enter(&sc->sc_intr_lock); 636 637 cmd = UREAD2(sc, UHCI_CMD); 638 sc->sc_bus.ub_usepolling++; 639 UWRITE2(sc, UHCI_INTR, 0); 640 uhci_globalreset(sc); 641 uhci_reset(sc); 642 if (cmd & UHCI_CMD_RS) 643 uhci_run(sc, 0, 1); 644 645 /* restore saved state */ 646 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 647 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 648 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 649 650 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 651 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 652 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 653 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 654 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 655 UHCICMD(sc, UHCI_CMD_MAXP); 656 uhci_run(sc, 1, 1); /* and start traffic again */ 657 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 658 sc->sc_bus.ub_usepolling--; 659 if (sc->sc_intr_xfer != NULL) 660 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 661 sc->sc_intr_xfer); 662 #ifdef UHCI_DEBUG 663 if (uhcidebug > 2) 664 uhci_dumpregs(sc); 665 #endif 666 667 sc->sc_suspend = PWR_RESUME; 668 mutex_spin_exit(&sc->sc_intr_lock); 669 670 return true; 671 } 672 673 bool 674 uhci_suspend(device_t dv, const pmf_qual_t *qual) 675 { 676 uhci_softc_t *sc = device_private(dv); 677 int cmd; 678 679 mutex_spin_enter(&sc->sc_intr_lock); 680 681 cmd = UREAD2(sc, UHCI_CMD); 682 683 #ifdef UHCI_DEBUG 684 if (uhcidebug > 2) 685 uhci_dumpregs(sc); 686 #endif 687 if (sc->sc_intr_xfer != NULL) 688 callout_stop(&sc->sc_poll_handle); 689 sc->sc_suspend = PWR_SUSPEND; 690 sc->sc_bus.ub_usepolling++; 691 692 uhci_run(sc, 0, 1); /* stop the controller */ 693 cmd &= ~UHCI_CMD_RS; 694 695 /* save some state if BIOS doesn't */ 696 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 697 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 698 699 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 700 701 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 702 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 703 sc->sc_bus.ub_usepolling--; 704 705 mutex_spin_exit(&sc->sc_intr_lock); 706 707 return true; 708 } 709 710 #ifdef UHCI_DEBUG 711 Static void 712 uhci_dumpregs(uhci_softc_t *sc) 713 { 714 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 715 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 716 device_xname(sc->sc_dev), 717 UREAD2(sc, UHCI_CMD), 718 UREAD2(sc, UHCI_STS), 719 UREAD2(sc, UHCI_INTR), 720 UREAD2(sc, UHCI_FRNUM), 721 UREAD4(sc, UHCI_FLBASEADDR), 722 UREAD1(sc, UHCI_SOF), 723 UREAD2(sc, UHCI_PORTSC1), 724 UREAD2(sc, UHCI_PORTSC2))); 725 } 726 727 void 728 uhci_dump_td(uhci_soft_td_t *p) 729 { 730 char sbuf[128], sbuf2[128]; 731 732 733 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 734 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 735 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 736 "token=0x%08lx buffer=0x%08lx\n", 737 p, (long)p->physaddr, 738 (long)le32toh(p->td.td_link), 739 (long)le32toh(p->td.td_status), 740 (long)le32toh(p->td.td_token), 741 (long)le32toh(p->td.td_buffer))); 742 743 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 744 (uint32_t)le32toh(p->td.td_link)); 745 snprintb(sbuf2, sizeof(sbuf2), 746 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 747 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 748 (uint32_t)le32toh(p->td.td_status)); 749 750 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 751 "D=%d,maxlen=%d\n", sbuf, sbuf2, 752 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 753 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 754 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 755 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 756 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 757 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 758 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 759 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 760 BUS_DMASYNC_PREREAD); 761 } 762 763 void 764 uhci_dump_qh(uhci_soft_qh_t *sqh) 765 { 766 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 768 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 769 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 770 le32toh(sqh->qh.qh_elink))); 771 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 772 } 773 774 775 #if 1 776 void 777 uhci_dump(void) 778 { 779 uhci_dump_all(thesc); 780 } 781 #endif 782 783 void 784 uhci_dump_all(uhci_softc_t *sc) 785 { 786 uhci_dumpregs(sc); 787 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 788 uhci_dump_qhs(sc->sc_lctl_start); 789 } 790 791 792 void 793 uhci_dump_qhs(uhci_soft_qh_t *sqh) 794 { 795 uhci_dump_qh(sqh); 796 797 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 798 * Traverses sideways first, then down. 799 * 800 * QH1 801 * QH2 802 * No QH 803 * TD2.1 804 * TD2.2 805 * TD1.1 806 * etc. 807 * 808 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 809 */ 810 811 812 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 813 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 814 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 815 uhci_dump_qhs(sqh->hlink); 816 else 817 DPRINTF(("No QH\n")); 818 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 819 820 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 821 uhci_dump_tds(sqh->elink); 822 else 823 DPRINTF(("No TD\n")); 824 } 825 826 void 827 uhci_dump_tds(uhci_soft_td_t *std) 828 { 829 uhci_soft_td_t *td; 830 int stop; 831 832 for(td = std; td != NULL; td = td->link.std) { 833 uhci_dump_td(td); 834 835 /* Check whether the link pointer in this TD marks 836 * the link pointer as end of queue. This avoids 837 * printing the free list in case the queue/TD has 838 * already been moved there (seatbelt). 839 */ 840 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 841 sizeof(td->td.td_link), 842 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 843 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 844 le32toh(td->td.td_link) == 0); 845 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 846 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 847 if (stop) 848 break; 849 } 850 } 851 852 Static void 853 uhci_dump_ii(uhci_intr_info_t *ii) 854 { 855 usbd_pipe_handle pipe; 856 usb_endpoint_descriptor_t *ed; 857 usbd_device_handle dev; 858 859 #ifdef DIAGNOSTIC 860 #define DONE ii->isdone 861 #else 862 #define DONE 0 863 #endif 864 if (ii == NULL) { 865 printf("ii NULL\n"); 866 return; 867 } 868 if (ii->xfer == NULL) { 869 printf("ii %p: done=%d xfer=NULL\n", 870 ii, DONE); 871 return; 872 } 873 pipe = ii->xfer->ux_pipe; 874 if (pipe == NULL) { 875 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 876 ii, DONE, ii->xfer); 877 return; 878 } 879 if (pipe->up_endpoint == NULL) { 880 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 881 ii, DONE, ii->xfer, pipe); 882 return; 883 } 884 if (pipe->up_dev == NULL) { 885 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 886 ii, DONE, ii->xfer, pipe); 887 return; 888 } 889 ed = pipe->up_endpoint->ue_edesc; 890 dev = pipe->up_dev; 891 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 892 ii, DONE, ii->xfer, dev, 893 UGETW(dev->ud_ddesc.idVendor), 894 UGETW(dev->ud_ddesc.idProduct), 895 dev->ud_addr, pipe, 896 ed->bEndpointAddress, ed->bmAttributes); 897 #undef DONE 898 } 899 900 void uhci_dump_iis(struct uhci_softc *sc); 901 void 902 uhci_dump_iis(struct uhci_softc *sc) 903 { 904 uhci_intr_info_t *ii; 905 906 printf("intr_info list:\n"); 907 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 908 uhci_dump_ii(ii); 909 } 910 911 void iidump(void); 912 void iidump(void) { uhci_dump_iis(thesc); } 913 914 #endif 915 916 /* 917 * This routine is executed periodically and simulates interrupts 918 * from the root controller interrupt pipe for port status change. 919 */ 920 void 921 uhci_poll_hub(void *addr) 922 { 923 usbd_xfer_handle xfer = addr; 924 usbd_pipe_handle pipe = xfer->ux_pipe; 925 uhci_softc_t *sc; 926 u_char *p; 927 928 DPRINTFN(20, ("uhci_poll_hub\n")); 929 930 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 931 return; /* device has detached */ 932 sc = pipe->up_dev->ud_bus->ub_hcpriv; 933 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 934 935 p = xfer->ux_buf; 936 p[0] = 0; 937 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 938 p[0] |= 1<<1; 939 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 940 p[0] |= 1<<2; 941 if (p[0] == 0) 942 /* No change, try again in a while */ 943 return; 944 945 xfer->ux_actlen = 1; 946 xfer->ux_status = USBD_NORMAL_COMPLETION; 947 mutex_enter(&sc->sc_lock); 948 usb_transfer_complete(xfer); 949 mutex_exit(&sc->sc_lock); 950 } 951 952 void 953 uhci_root_intr_done(usbd_xfer_handle xfer) 954 { 955 } 956 957 /* 958 * Let the last QH loop back to the high speed control transfer QH. 959 * This is what intel calls "bandwidth reclamation" and improves 960 * USB performance a lot for some devices. 961 * If we are already looping, just count it. 962 */ 963 void 964 uhci_add_loop(uhci_softc_t *sc) { 965 #ifdef UHCI_DEBUG 966 if (uhcinoloop) 967 return; 968 #endif 969 if (++sc->sc_loops == 1) { 970 DPRINTFN(5,("uhci_start_loop: add\n")); 971 /* Note, we don't loop back the soft pointer. */ 972 sc->sc_last_qh->qh.qh_hlink = 973 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 974 usb_syncmem(&sc->sc_last_qh->dma, 975 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 976 sizeof(sc->sc_last_qh->qh.qh_hlink), 977 BUS_DMASYNC_PREWRITE); 978 } 979 } 980 981 void 982 uhci_rem_loop(uhci_softc_t *sc) { 983 #ifdef UHCI_DEBUG 984 if (uhcinoloop) 985 return; 986 #endif 987 if (--sc->sc_loops == 0) { 988 DPRINTFN(5,("uhci_end_loop: remove\n")); 989 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 990 usb_syncmem(&sc->sc_last_qh->dma, 991 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 992 sizeof(sc->sc_last_qh->qh.qh_hlink), 993 BUS_DMASYNC_PREWRITE); 994 } 995 } 996 997 /* Add high speed control QH, called with lock held. */ 998 void 999 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1000 { 1001 uhci_soft_qh_t *eqh; 1002 1003 KASSERT(mutex_owned(&sc->sc_lock)); 1004 1005 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1006 eqh = sc->sc_hctl_end; 1007 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1008 sizeof(eqh->qh.qh_hlink), 1009 BUS_DMASYNC_POSTWRITE); 1010 sqh->hlink = eqh->hlink; 1011 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1012 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1013 BUS_DMASYNC_PREWRITE); 1014 eqh->hlink = sqh; 1015 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1016 sc->sc_hctl_end = sqh; 1017 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1018 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1019 #ifdef UHCI_CTL_LOOP 1020 uhci_add_loop(sc); 1021 #endif 1022 } 1023 1024 /* Remove high speed control QH, called with lock held. */ 1025 void 1026 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1027 { 1028 uhci_soft_qh_t *pqh; 1029 uint32_t elink; 1030 1031 KASSERT(mutex_owned(&sc->sc_lock)); 1032 1033 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1034 #ifdef UHCI_CTL_LOOP 1035 uhci_rem_loop(sc); 1036 #endif 1037 /* 1038 * The T bit should be set in the elink of the QH so that the HC 1039 * doesn't follow the pointer. This condition may fail if the 1040 * the transferred packet was short so that the QH still points 1041 * at the last used TD. 1042 * In this case we set the T bit and wait a little for the HC 1043 * to stop looking at the TD. 1044 * Note that if the TD chain is large enough, the controller 1045 * may still be looking at the chain at the end of this function. 1046 * uhci_free_std_chain() will make sure the controller stops 1047 * looking at it quickly, but until then we should not change 1048 * sqh->hlink. 1049 */ 1050 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1051 sizeof(sqh->qh.qh_elink), 1052 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1053 elink = le32toh(sqh->qh.qh_elink); 1054 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1055 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1056 if (!(elink & UHCI_PTR_T)) { 1057 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1058 usb_syncmem(&sqh->dma, 1059 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1060 sizeof(sqh->qh.qh_elink), 1061 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1062 delay(UHCI_QH_REMOVE_DELAY); 1063 } 1064 1065 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1066 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1067 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1068 pqh->hlink = sqh->hlink; 1069 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1070 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1071 sizeof(pqh->qh.qh_hlink), 1072 BUS_DMASYNC_PREWRITE); 1073 delay(UHCI_QH_REMOVE_DELAY); 1074 if (sc->sc_hctl_end == sqh) 1075 sc->sc_hctl_end = pqh; 1076 } 1077 1078 /* Add low speed control QH, called with lock held. */ 1079 void 1080 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1081 { 1082 uhci_soft_qh_t *eqh; 1083 1084 KASSERT(mutex_owned(&sc->sc_lock)); 1085 1086 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1087 eqh = sc->sc_lctl_end; 1088 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1089 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1090 sqh->hlink = eqh->hlink; 1091 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1092 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1093 BUS_DMASYNC_PREWRITE); 1094 eqh->hlink = sqh; 1095 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1096 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1097 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1098 sc->sc_lctl_end = sqh; 1099 } 1100 1101 /* Remove low speed control QH, called with lock held. */ 1102 void 1103 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1104 { 1105 uhci_soft_qh_t *pqh; 1106 uint32_t elink; 1107 1108 KASSERT(mutex_owned(&sc->sc_lock)); 1109 1110 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1111 /* See comment in uhci_remove_hs_ctrl() */ 1112 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1113 sizeof(sqh->qh.qh_elink), 1114 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1115 elink = le32toh(sqh->qh.qh_elink); 1116 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1117 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1118 if (!(elink & UHCI_PTR_T)) { 1119 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1120 usb_syncmem(&sqh->dma, 1121 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1122 sizeof(sqh->qh.qh_elink), 1123 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1124 delay(UHCI_QH_REMOVE_DELAY); 1125 } 1126 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1127 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1128 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1129 pqh->hlink = sqh->hlink; 1130 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1131 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1132 sizeof(pqh->qh.qh_hlink), 1133 BUS_DMASYNC_PREWRITE); 1134 delay(UHCI_QH_REMOVE_DELAY); 1135 if (sc->sc_lctl_end == sqh) 1136 sc->sc_lctl_end = pqh; 1137 } 1138 1139 /* Add bulk QH, called with lock held. */ 1140 void 1141 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1142 { 1143 uhci_soft_qh_t *eqh; 1144 1145 KASSERT(mutex_owned(&sc->sc_lock)); 1146 1147 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1148 eqh = sc->sc_bulk_end; 1149 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1150 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1151 sqh->hlink = eqh->hlink; 1152 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1153 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1154 BUS_DMASYNC_PREWRITE); 1155 eqh->hlink = sqh; 1156 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1157 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1158 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1159 sc->sc_bulk_end = sqh; 1160 uhci_add_loop(sc); 1161 } 1162 1163 /* Remove bulk QH, called with lock held. */ 1164 void 1165 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1166 { 1167 uhci_soft_qh_t *pqh; 1168 1169 KASSERT(mutex_owned(&sc->sc_lock)); 1170 1171 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1172 uhci_rem_loop(sc); 1173 /* See comment in uhci_remove_hs_ctrl() */ 1174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1175 sizeof(sqh->qh.qh_elink), 1176 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1177 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1178 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1179 usb_syncmem(&sqh->dma, 1180 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1181 sizeof(sqh->qh.qh_elink), 1182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1183 delay(UHCI_QH_REMOVE_DELAY); 1184 } 1185 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1186 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1187 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1188 pqh->hlink = sqh->hlink; 1189 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1190 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1191 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1192 delay(UHCI_QH_REMOVE_DELAY); 1193 if (sc->sc_bulk_end == sqh) 1194 sc->sc_bulk_end = pqh; 1195 } 1196 1197 Static int uhci_intr1(uhci_softc_t *); 1198 1199 int 1200 uhci_intr(void *arg) 1201 { 1202 uhci_softc_t *sc = arg; 1203 int ret = 0; 1204 1205 mutex_spin_enter(&sc->sc_intr_lock); 1206 1207 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1208 goto done; 1209 1210 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1211 #ifdef DIAGNOSTIC 1212 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1213 #endif 1214 goto done; 1215 } 1216 1217 ret = uhci_intr1(sc); 1218 1219 done: 1220 mutex_spin_exit(&sc->sc_intr_lock); 1221 return ret; 1222 } 1223 1224 int 1225 uhci_intr1(uhci_softc_t *sc) 1226 { 1227 int status; 1228 int ack; 1229 1230 #ifdef UHCI_DEBUG 1231 if (uhcidebug > 15) { 1232 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1233 uhci_dumpregs(sc); 1234 } 1235 #endif 1236 1237 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1238 1239 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1240 if (status == 0) /* The interrupt was not for us. */ 1241 return 0; 1242 1243 if (sc->sc_suspend != PWR_RESUME) { 1244 #ifdef DIAGNOSTIC 1245 printf("%s: interrupt while not operating ignored\n", 1246 device_xname(sc->sc_dev)); 1247 #endif 1248 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1249 return 0; 1250 } 1251 1252 ack = 0; 1253 if (status & UHCI_STS_USBINT) 1254 ack |= UHCI_STS_USBINT; 1255 if (status & UHCI_STS_USBEI) 1256 ack |= UHCI_STS_USBEI; 1257 if (status & UHCI_STS_RD) { 1258 ack |= UHCI_STS_RD; 1259 #ifdef UHCI_DEBUG 1260 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1261 #endif 1262 } 1263 if (status & UHCI_STS_HSE) { 1264 ack |= UHCI_STS_HSE; 1265 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1266 } 1267 if (status & UHCI_STS_HCPE) { 1268 ack |= UHCI_STS_HCPE; 1269 printf("%s: host controller process error\n", 1270 device_xname(sc->sc_dev)); 1271 } 1272 1273 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1274 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1275 /* no acknowledge needed */ 1276 if (!sc->sc_dying) { 1277 printf("%s: host controller halted\n", 1278 device_xname(sc->sc_dev)); 1279 #ifdef UHCI_DEBUG 1280 uhci_dump_all(sc); 1281 #endif 1282 } 1283 sc->sc_dying = 1; 1284 } 1285 1286 if (!ack) 1287 return 0; /* nothing to acknowledge */ 1288 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1289 1290 usb_schedsoftintr(&sc->sc_bus); 1291 1292 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1293 1294 return 1; 1295 } 1296 1297 void 1298 uhci_softintr(void *v) 1299 { 1300 struct usbd_bus *bus = v; 1301 uhci_softc_t *sc = bus->ub_hcpriv; 1302 uhci_intr_info_t *ii, *nextii; 1303 1304 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1305 1306 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1307 1308 /* 1309 * Interrupts on UHCI really suck. When the host controller 1310 * interrupts because a transfer is completed there is no 1311 * way of knowing which transfer it was. You can scan down 1312 * the TDs and QHs of the previous frame to limit the search, 1313 * but that assumes that the interrupt was not delayed by more 1314 * than 1 ms, which may not always be true (e.g. after debug 1315 * output on a slow console). 1316 * We scan all interrupt descriptors to see if any have 1317 * completed. 1318 */ 1319 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1320 nextii = LIST_NEXT(ii, list); 1321 uhci_check_intr(sc, ii); 1322 } 1323 1324 if (sc->sc_softwake) { 1325 sc->sc_softwake = 0; 1326 cv_broadcast(&sc->sc_softwake_cv); 1327 } 1328 } 1329 1330 /* Check for an interrupt. */ 1331 void 1332 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1333 { 1334 uhci_soft_td_t *std, *lstd; 1335 uint32_t status; 1336 1337 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1338 #ifdef DIAGNOSTIC 1339 if (ii == NULL) { 1340 printf("uhci_check_intr: no ii? %p\n", ii); 1341 return; 1342 } 1343 #endif 1344 if (ii->xfer->ux_status == USBD_CANCELLED || 1345 ii->xfer->ux_status == USBD_TIMEOUT) { 1346 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1347 return; 1348 } 1349 1350 if (ii->stdstart == NULL) 1351 return; 1352 lstd = ii->stdend; 1353 #ifdef DIAGNOSTIC 1354 if (lstd == NULL) { 1355 printf("uhci_check_intr: std==0\n"); 1356 return; 1357 } 1358 #endif 1359 usb_syncmem(&lstd->dma, 1360 lstd->offs + offsetof(uhci_td_t, td_status), 1361 sizeof(lstd->td.td_status), 1362 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1363 status = le32toh(lstd->td.td_status); 1364 usb_syncmem(&lstd->dma, 1365 lstd->offs + offsetof(uhci_td_t, td_status), 1366 sizeof(lstd->td.td_status), 1367 BUS_DMASYNC_PREREAD); 1368 1369 /* If the last TD is not marked active we can complete */ 1370 if (!(status & UHCI_TD_ACTIVE)) { 1371 done: 1372 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1373 callout_stop(&ii->xfer->ux_callout); 1374 uhci_idone(ii); 1375 return; 1376 } 1377 1378 /* 1379 * If the last TD is still active we need to check whether there 1380 * is an error somewhere in the middle, or whether there was a 1381 * short packet (SPD and not ACTIVE). 1382 */ 1383 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1384 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1385 usb_syncmem(&std->dma, 1386 std->offs + offsetof(uhci_td_t, td_status), 1387 sizeof(std->td.td_status), 1388 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1389 status = le32toh(std->td.td_status); 1390 usb_syncmem(&std->dma, 1391 std->offs + offsetof(uhci_td_t, td_status), 1392 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1393 1394 /* If there's an active TD the xfer isn't done. */ 1395 if (status & UHCI_TD_ACTIVE) { 1396 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1397 __func__, ii, std)); 1398 return; 1399 } 1400 1401 /* Any kind of error makes the xfer done. */ 1402 if (status & UHCI_TD_STALLED) 1403 goto done; 1404 1405 /* 1406 * If the data phase of a control transfer is short, we need 1407 * to complete the status stage 1408 */ 1409 usbd_xfer_handle xfer = ii->xfer; 1410 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1411 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1412 1413 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1414 struct uhci_pipe *upipe = 1415 (struct uhci_pipe *)xfer->ux_pipe; 1416 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1417 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1418 1419 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1420 "phase needs completion\n", __func__, ii, 1421 ii->stdstart)); 1422 1423 sqh->qh.qh_elink = 1424 htole32(stat->physaddr | UHCI_PTR_TD); 1425 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1426 BUS_DMASYNC_PREWRITE); 1427 break; 1428 } 1429 1430 /* We want short packets, and it is short: it's done */ 1431 usb_syncmem(&std->dma, 1432 std->offs + offsetof(uhci_td_t, td_token), 1433 sizeof(std->td.td_token), 1434 BUS_DMASYNC_POSTWRITE); 1435 1436 if ((status & UHCI_TD_SPD) && 1437 UHCI_TD_GET_ACTLEN(status) < 1438 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1439 goto done; 1440 } 1441 } 1442 } 1443 1444 /* Called with USB lock held. */ 1445 void 1446 uhci_idone(uhci_intr_info_t *ii) 1447 { 1448 usbd_xfer_handle xfer = ii->xfer; 1449 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1450 #ifdef DIAGNOSTIC 1451 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1452 #endif 1453 uhci_soft_td_t *std; 1454 uint32_t status = 0, nstatus; 1455 int actlen; 1456 1457 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1458 1459 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1460 #ifdef DIAGNOSTIC 1461 { 1462 /* XXX SMP? */ 1463 int s = splhigh(); 1464 if (ii->isdone) { 1465 splx(s); 1466 #ifdef UHCI_DEBUG 1467 printf("uhci_idone: ii is done!\n "); 1468 uhci_dump_ii(ii); 1469 #else 1470 printf("uhci_idone: ii=%p is done!\n", ii); 1471 #endif 1472 return; 1473 } 1474 ii->isdone = 1; 1475 splx(s); 1476 } 1477 #endif 1478 1479 if (xfer->ux_nframes != 0) { 1480 /* Isoc transfer, do things differently. */ 1481 uhci_soft_td_t **stds = upipe->u.iso.stds; 1482 int i, n, nframes, len; 1483 1484 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1485 1486 nframes = xfer->ux_nframes; 1487 actlen = 0; 1488 n = UXFER(xfer)->curframe; 1489 for (i = 0; i < nframes; i++) { 1490 std = stds[n]; 1491 #ifdef UHCI_DEBUG 1492 if (uhcidebug > 5) { 1493 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1494 uhci_dump_td(std); 1495 } 1496 #endif 1497 if (++n >= UHCI_VFRAMELIST_COUNT) 1498 n = 0; 1499 usb_syncmem(&std->dma, 1500 std->offs + offsetof(uhci_td_t, td_status), 1501 sizeof(std->td.td_status), 1502 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1503 status = le32toh(std->td.td_status); 1504 len = UHCI_TD_GET_ACTLEN(status); 1505 xfer->ux_frlengths[i] = len; 1506 actlen += len; 1507 } 1508 upipe->u.iso.inuse -= nframes; 1509 xfer->ux_actlen = actlen; 1510 xfer->ux_status = USBD_NORMAL_COMPLETION; 1511 goto end; 1512 } 1513 1514 #ifdef UHCI_DEBUG 1515 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1516 ii, xfer, upipe)); 1517 if (uhcidebug > 10) 1518 uhci_dump_tds(ii->stdstart); 1519 #endif 1520 1521 /* The transfer is done, compute actual length and status. */ 1522 actlen = 0; 1523 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1524 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1525 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1526 nstatus = le32toh(std->td.td_status); 1527 if (nstatus & UHCI_TD_ACTIVE) 1528 break; 1529 1530 status = nstatus; 1531 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1532 UHCI_TD_PID_SETUP) 1533 actlen += UHCI_TD_GET_ACTLEN(status); 1534 else { 1535 /* 1536 * UHCI will report CRCTO in addition to a STALL or NAK 1537 * for a SETUP transaction. See section 3.2.2, "TD 1538 * CONTROL AND STATUS". 1539 */ 1540 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1541 status &= ~UHCI_TD_CRCTO; 1542 } 1543 } 1544 /* If there are left over TDs we need to update the toggle. */ 1545 if (std != NULL) 1546 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1547 1548 status &= UHCI_TD_ERROR; 1549 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1550 actlen, status)); 1551 xfer->ux_actlen = actlen; 1552 if (status != 0) { 1553 #ifdef UHCI_DEBUG 1554 char sbuf[128]; 1555 1556 snprintb(sbuf, sizeof(sbuf), 1557 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1558 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status); 1559 1560 DPRINTFN((status == UHCI_TD_STALLED)*10, 1561 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1562 "status 0x%s\n", 1563 xfer->ux_pipe->up_dev->ud_addr, 1564 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1565 sbuf)); 1566 #endif 1567 1568 if (status == UHCI_TD_STALLED) 1569 xfer->ux_status = USBD_STALLED; 1570 else 1571 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1572 } else { 1573 xfer->ux_status = USBD_NORMAL_COMPLETION; 1574 } 1575 1576 end: 1577 usb_transfer_complete(xfer); 1578 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1579 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1580 } 1581 1582 /* 1583 * Called when a request does not complete. 1584 */ 1585 void 1586 uhci_timeout(void *addr) 1587 { 1588 uhci_intr_info_t *ii = addr; 1589 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1590 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe; 1591 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1592 1593 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1594 1595 if (sc->sc_dying) { 1596 mutex_enter(&sc->sc_lock); 1597 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1598 mutex_exit(&sc->sc_lock); 1599 return; 1600 } 1601 1602 /* Execute the abort in a process context. */ 1603 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1604 USB_TASKQ_MPSAFE); 1605 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1606 USB_TASKQ_HC); 1607 } 1608 1609 void 1610 uhci_timeout_task(void *addr) 1611 { 1612 usbd_xfer_handle xfer = addr; 1613 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1614 1615 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1616 1617 mutex_enter(&sc->sc_lock); 1618 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1619 mutex_exit(&sc->sc_lock); 1620 } 1621 1622 /* 1623 * Wait here until controller claims to have an interrupt. 1624 * Then call uhci_intr and return. Use timeout to avoid waiting 1625 * too long. 1626 * Only used during boot when interrupts are not enabled yet. 1627 */ 1628 void 1629 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1630 { 1631 int timo = xfer->ux_timeout; 1632 uhci_intr_info_t *ii; 1633 1634 mutex_enter(&sc->sc_lock); 1635 1636 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1637 1638 xfer->ux_status = USBD_IN_PROGRESS; 1639 for (; timo >= 0; timo--) { 1640 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1641 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1642 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1643 mutex_spin_enter(&sc->sc_intr_lock); 1644 uhci_intr1(sc); 1645 mutex_spin_exit(&sc->sc_intr_lock); 1646 if (xfer->ux_status != USBD_IN_PROGRESS) 1647 goto done; 1648 } 1649 } 1650 1651 /* Timeout */ 1652 DPRINTF(("uhci_waitintr: timeout\n")); 1653 for (ii = LIST_FIRST(&sc->sc_intrhead); 1654 ii != NULL && ii->xfer != xfer; 1655 ii = LIST_NEXT(ii, list)) 1656 ; 1657 #ifdef DIAGNOSTIC 1658 if (ii == NULL) 1659 panic("uhci_waitintr: lost intr_info"); 1660 #endif 1661 uhci_idone(ii); 1662 1663 done: 1664 mutex_exit(&sc->sc_lock); 1665 } 1666 1667 void 1668 uhci_poll(struct usbd_bus *bus) 1669 { 1670 uhci_softc_t *sc = bus->ub_hcpriv; 1671 1672 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1673 mutex_spin_enter(&sc->sc_intr_lock); 1674 uhci_intr1(sc); 1675 mutex_spin_exit(&sc->sc_intr_lock); 1676 } 1677 } 1678 1679 void 1680 uhci_reset(uhci_softc_t *sc) 1681 { 1682 int n; 1683 1684 UHCICMD(sc, UHCI_CMD_HCRESET); 1685 /* The reset bit goes low when the controller is done. */ 1686 for (n = 0; n < UHCI_RESET_TIMEOUT && 1687 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1688 usb_delay_ms(&sc->sc_bus, 1); 1689 if (n >= UHCI_RESET_TIMEOUT) 1690 printf("%s: controller did not reset\n", 1691 device_xname(sc->sc_dev)); 1692 } 1693 1694 usbd_status 1695 uhci_run(uhci_softc_t *sc, int run, int locked) 1696 { 1697 int n, running; 1698 uint16_t cmd; 1699 1700 run = run != 0; 1701 if (!locked) 1702 mutex_spin_enter(&sc->sc_intr_lock); 1703 DPRINTF(("uhci_run: setting run=%d\n", run)); 1704 cmd = UREAD2(sc, UHCI_CMD); 1705 if (run) 1706 cmd |= UHCI_CMD_RS; 1707 else 1708 cmd &= ~UHCI_CMD_RS; 1709 UHCICMD(sc, cmd); 1710 for(n = 0; n < 10; n++) { 1711 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1712 /* return when we've entered the state we want */ 1713 if (run == running) { 1714 if (!locked) 1715 mutex_spin_exit(&sc->sc_intr_lock); 1716 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1717 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1718 return USBD_NORMAL_COMPLETION; 1719 } 1720 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1721 } 1722 if (!locked) 1723 mutex_spin_exit(&sc->sc_intr_lock); 1724 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1725 run ? "start" : "stop"); 1726 return USBD_IOERROR; 1727 } 1728 1729 /* 1730 * Memory management routines. 1731 * uhci_alloc_std allocates TDs 1732 * uhci_alloc_sqh allocates QHs 1733 * These two routines do their own free list management, 1734 * partly for speed, partly because allocating DMAable memory 1735 * has page size granularaity so much memory would be wasted if 1736 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1737 */ 1738 1739 uhci_soft_td_t * 1740 uhci_alloc_std(uhci_softc_t *sc) 1741 { 1742 uhci_soft_td_t *std; 1743 usbd_status err; 1744 int i, offs; 1745 usb_dma_t dma; 1746 1747 if (sc->sc_freetds == NULL) { 1748 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1749 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1750 UHCI_TD_ALIGN, &dma); 1751 if (err) 1752 return 0; 1753 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1754 offs = i * UHCI_STD_SIZE; 1755 std = KERNADDR(&dma, offs); 1756 std->physaddr = DMAADDR(&dma, offs); 1757 std->dma = dma; 1758 std->offs = offs; 1759 std->link.std = sc->sc_freetds; 1760 sc->sc_freetds = std; 1761 } 1762 } 1763 std = sc->sc_freetds; 1764 sc->sc_freetds = std->link.std; 1765 memset(&std->td, 0, sizeof(uhci_td_t)); 1766 return std; 1767 } 1768 1769 void 1770 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1771 { 1772 #ifdef DIAGNOSTIC 1773 #define TD_IS_FREE 0x12345678 1774 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1775 printf("uhci_free_std: freeing free TD %p\n", std); 1776 return; 1777 } 1778 std->td.td_token = htole32(TD_IS_FREE); 1779 #endif 1780 std->link.std = sc->sc_freetds; 1781 sc->sc_freetds = std; 1782 } 1783 1784 uhci_soft_qh_t * 1785 uhci_alloc_sqh(uhci_softc_t *sc) 1786 { 1787 uhci_soft_qh_t *sqh; 1788 usbd_status err; 1789 int i, offs; 1790 usb_dma_t dma; 1791 1792 if (sc->sc_freeqhs == NULL) { 1793 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1794 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1795 UHCI_QH_ALIGN, &dma); 1796 if (err) 1797 return 0; 1798 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1799 offs = i * UHCI_SQH_SIZE; 1800 sqh = KERNADDR(&dma, offs); 1801 sqh->physaddr = DMAADDR(&dma, offs); 1802 sqh->dma = dma; 1803 sqh->offs = offs; 1804 sqh->hlink = sc->sc_freeqhs; 1805 sc->sc_freeqhs = sqh; 1806 } 1807 } 1808 sqh = sc->sc_freeqhs; 1809 sc->sc_freeqhs = sqh->hlink; 1810 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1811 return sqh; 1812 } 1813 1814 void 1815 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1816 { 1817 sqh->hlink = sc->sc_freeqhs; 1818 sc->sc_freeqhs = sqh; 1819 } 1820 1821 void 1822 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1823 uhci_soft_td_t *stdend) 1824 { 1825 uhci_soft_td_t *p; 1826 uint32_t td_link; 1827 1828 /* 1829 * to avoid race condition with the controller which may be looking 1830 * at this chain, we need to first invalidate all links, and 1831 * then wait for the controller to move to another queue 1832 */ 1833 for (p = std; p != stdend; p = p->link.std) { 1834 usb_syncmem(&p->dma, 1835 p->offs + offsetof(uhci_td_t, td_link), 1836 sizeof(p->td.td_link), 1837 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1838 td_link = le32toh(p->td.td_link); 1839 usb_syncmem(&p->dma, 1840 p->offs + offsetof(uhci_td_t, td_link), 1841 sizeof(p->td.td_link), 1842 BUS_DMASYNC_PREREAD); 1843 if ((td_link & UHCI_PTR_T) == 0) { 1844 p->td.td_link = htole32(UHCI_PTR_T); 1845 usb_syncmem(&p->dma, 1846 p->offs + offsetof(uhci_td_t, td_link), 1847 sizeof(p->td.td_link), 1848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1849 } 1850 } 1851 delay(UHCI_QH_REMOVE_DELAY); 1852 1853 for (; std != stdend; std = p) { 1854 p = std->link.std; 1855 uhci_free_std(sc, std); 1856 } 1857 } 1858 1859 usbd_status 1860 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1861 int rd, uint16_t flags, usb_dma_t *dma, 1862 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1863 { 1864 uhci_soft_td_t *p, *lastp; 1865 uhci_physaddr_t lastlink; 1866 int i, ntd, l, tog, maxp; 1867 uint32_t status; 1868 int addr = upipe->pipe.up_dev->ud_addr; 1869 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1870 1871 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1872 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1873 upipe->pipe.up_dev->ud_speed, flags)); 1874 1875 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1876 1877 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1878 if (maxp == 0) { 1879 printf("uhci_alloc_std_chain: maxp=0\n"); 1880 return USBD_INVAL; 1881 } 1882 ntd = (len + maxp - 1) / maxp; 1883 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1884 ntd++; 1885 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1886 if (ntd == 0) { 1887 *sp = *ep = 0; 1888 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1889 return USBD_NORMAL_COMPLETION; 1890 } 1891 tog = upipe->nexttoggle; 1892 if (ntd % 2 == 0) 1893 tog ^= 1; 1894 upipe->nexttoggle = tog ^ 1; 1895 lastp = NULL; 1896 lastlink = UHCI_PTR_T; 1897 ntd--; 1898 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1899 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1900 status |= UHCI_TD_LS; 1901 if (flags & USBD_SHORT_XFER_OK) 1902 status |= UHCI_TD_SPD; 1903 usb_syncmem(dma, 0, len, 1904 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1905 for (i = ntd; i >= 0; i--) { 1906 p = uhci_alloc_std(sc); 1907 if (p == NULL) { 1908 KASSERT(lastp != NULL); 1909 uhci_free_std_chain(sc, lastp, NULL); 1910 return USBD_NOMEM; 1911 } 1912 p->link.std = lastp; 1913 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1914 lastp = p; 1915 lastlink = p->physaddr; 1916 p->td.td_status = htole32(status); 1917 if (i == ntd) { 1918 /* last TD */ 1919 l = len % maxp; 1920 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1921 l = maxp; 1922 *ep = p; 1923 } else 1924 l = maxp; 1925 p->td.td_token = 1926 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1927 UHCI_TD_OUT(l, endpt, addr, tog)); 1928 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1929 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1930 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1931 tog ^= 1; 1932 } 1933 *sp = lastp; 1934 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1935 upipe->nexttoggle)); 1936 return USBD_NORMAL_COMPLETION; 1937 } 1938 1939 void 1940 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1941 { 1942 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1943 upipe->nexttoggle = 0; 1944 } 1945 1946 void 1947 uhci_noop(usbd_pipe_handle pipe) 1948 { 1949 } 1950 1951 usbd_status 1952 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1953 { 1954 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1955 usbd_status err; 1956 1957 /* Insert last in queue. */ 1958 mutex_enter(&sc->sc_lock); 1959 err = usb_insert_transfer(xfer); 1960 mutex_exit(&sc->sc_lock); 1961 if (err) 1962 return err; 1963 1964 /* 1965 * Pipe isn't running (otherwise err would be USBD_INPROG), 1966 * so start it first. 1967 */ 1968 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1969 } 1970 1971 usbd_status 1972 uhci_device_bulk_start(usbd_xfer_handle xfer) 1973 { 1974 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1975 usbd_device_handle dev = upipe->pipe.up_dev; 1976 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1977 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1978 uhci_soft_td_t *data, *dataend; 1979 uhci_soft_qh_t *sqh; 1980 usbd_status err; 1981 int len, isread, endpt; 1982 1983 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1984 xfer, xfer->ux_length, xfer->ux_flags, ii)); 1985 1986 if (sc->sc_dying) 1987 return USBD_IOERROR; 1988 1989 #ifdef DIAGNOSTIC 1990 if (xfer->ux_rqflags & URQ_REQUEST) 1991 panic("uhci_device_bulk_transfer: a request"); 1992 #endif 1993 1994 mutex_enter(&sc->sc_lock); 1995 1996 len = xfer->ux_length; 1997 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1998 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 1999 sqh = upipe->u.bulk.sqh; 2000 2001 upipe->u.bulk.isread = isread; 2002 upipe->u.bulk.length = len; 2003 2004 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2005 &xfer->ux_dmabuf, &data, &dataend); 2006 if (err) { 2007 mutex_exit(&sc->sc_lock); 2008 return err; 2009 } 2010 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2011 usb_syncmem(&dataend->dma, 2012 dataend->offs + offsetof(uhci_td_t, td_status), 2013 sizeof(dataend->td.td_status), 2014 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2015 2016 2017 #ifdef UHCI_DEBUG 2018 if (uhcidebug > 8) { 2019 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2020 uhci_dump_tds(data); 2021 } 2022 #endif 2023 2024 /* Set up interrupt info. */ 2025 ii->xfer = xfer; 2026 ii->stdstart = data; 2027 ii->stdend = dataend; 2028 #ifdef DIAGNOSTIC 2029 if (!ii->isdone) { 2030 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2031 } 2032 ii->isdone = 0; 2033 #endif 2034 2035 sqh->elink = data; 2036 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2037 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2038 2039 uhci_add_bulk(sc, sqh); 2040 uhci_add_intr_info(sc, ii); 2041 2042 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2043 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2044 uhci_timeout, ii); 2045 } 2046 xfer->ux_status = USBD_IN_PROGRESS; 2047 2048 #ifdef UHCI_DEBUG 2049 if (uhcidebug > 10) { 2050 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2051 uhci_dump_tds(data); 2052 } 2053 #endif 2054 2055 if (sc->sc_bus.ub_usepolling) 2056 uhci_waitintr(sc, xfer); 2057 2058 mutex_exit(&sc->sc_lock); 2059 return USBD_IN_PROGRESS; 2060 } 2061 2062 /* Abort a device bulk request. */ 2063 void 2064 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2065 { 2066 #ifdef DIAGNOSTIC 2067 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2068 #endif 2069 2070 KASSERT(mutex_owned(&sc->sc_lock)); 2071 2072 DPRINTF(("uhci_device_bulk_abort:\n")); 2073 uhci_abort_xfer(xfer, USBD_CANCELLED); 2074 } 2075 2076 /* 2077 * Abort a device request. 2078 * If this routine is called at splusb() it guarantees that the request 2079 * will be removed from the hardware scheduling and that the callback 2080 * for it will be called with USBD_CANCELLED status. 2081 * It's impossible to guarantee that the requested transfer will not 2082 * have happened since the hardware runs concurrently. 2083 * If the transaction has already happened we rely on the ordinary 2084 * interrupt processing to process it. 2085 * XXX This is most probably wrong. 2086 * XXXMRG this doesn't make sense anymore. 2087 */ 2088 void 2089 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2090 { 2091 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2092 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2093 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2094 uhci_soft_td_t *std; 2095 int wake; 2096 2097 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2098 2099 KASSERT(mutex_owned(&sc->sc_lock)); 2100 ASSERT_SLEEPABLE(); 2101 2102 if (sc->sc_dying) { 2103 /* If we're dying, just do the software part. */ 2104 xfer->ux_status = status; /* make software ignore it */ 2105 callout_stop(&xfer->ux_callout); 2106 usb_transfer_complete(xfer); 2107 return; 2108 } 2109 2110 /* 2111 * If an abort is already in progress then just wait for it to 2112 * complete and return. 2113 */ 2114 if (xfer->ux_hcflags & UXFER_ABORTING) { 2115 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2116 #ifdef DIAGNOSTIC 2117 if (status == USBD_TIMEOUT) 2118 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2119 #endif 2120 /* Override the status which might be USBD_TIMEOUT. */ 2121 xfer->ux_status = status; 2122 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2123 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2124 while (xfer->ux_hcflags & UXFER_ABORTING) 2125 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2126 goto done; 2127 } 2128 xfer->ux_hcflags |= UXFER_ABORTING; 2129 2130 /* 2131 * Step 1: Make interrupt routine and hardware ignore xfer. 2132 */ 2133 xfer->ux_status = status; /* make software ignore it */ 2134 callout_stop(&xfer->ux_callout); 2135 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2136 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2137 usb_syncmem(&std->dma, 2138 std->offs + offsetof(uhci_td_t, td_status), 2139 sizeof(std->td.td_status), 2140 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2141 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2142 usb_syncmem(&std->dma, 2143 std->offs + offsetof(uhci_td_t, td_status), 2144 sizeof(std->td.td_status), 2145 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2146 } 2147 2148 /* 2149 * Step 2: Wait until we know hardware has finished any possible 2150 * use of the xfer. Also make sure the soft interrupt routine 2151 * has run. 2152 */ 2153 /* Hardware finishes in 1ms */ 2154 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2155 sc->sc_softwake = 1; 2156 usb_schedsoftintr(&sc->sc_bus); 2157 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2158 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2159 2160 /* 2161 * Step 3: Execute callback. 2162 */ 2163 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2164 #ifdef DIAGNOSTIC 2165 ii->isdone = 1; 2166 #endif 2167 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2168 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2169 usb_transfer_complete(xfer); 2170 if (wake) 2171 cv_broadcast(&xfer->ux_hccv); 2172 done: 2173 KASSERT(mutex_owned(&sc->sc_lock)); 2174 } 2175 2176 /* Close a device bulk pipe. */ 2177 void 2178 uhci_device_bulk_close(usbd_pipe_handle pipe) 2179 { 2180 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2181 usbd_device_handle dev = upipe->pipe.up_dev; 2182 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2183 2184 KASSERT(mutex_owned(&sc->sc_lock)); 2185 2186 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2187 2188 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2189 } 2190 2191 usbd_status 2192 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2193 { 2194 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2195 usbd_status err; 2196 2197 /* Insert last in queue. */ 2198 mutex_enter(&sc->sc_lock); 2199 err = usb_insert_transfer(xfer); 2200 mutex_exit(&sc->sc_lock); 2201 if (err) 2202 return err; 2203 2204 /* 2205 * Pipe isn't running (otherwise err would be USBD_INPROG), 2206 * so start it first. 2207 */ 2208 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2209 } 2210 2211 usbd_status 2212 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2213 { 2214 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2215 usbd_status err; 2216 2217 if (sc->sc_dying) 2218 return USBD_IOERROR; 2219 2220 #ifdef DIAGNOSTIC 2221 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2222 panic("uhci_device_ctrl_transfer: not a request"); 2223 #endif 2224 2225 mutex_enter(&sc->sc_lock); 2226 err = uhci_device_request(xfer); 2227 mutex_exit(&sc->sc_lock); 2228 if (err) 2229 return err; 2230 2231 if (sc->sc_bus.ub_usepolling) 2232 uhci_waitintr(sc, xfer); 2233 return USBD_IN_PROGRESS; 2234 } 2235 2236 usbd_status 2237 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2238 { 2239 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2240 usbd_status err; 2241 2242 /* Insert last in queue. */ 2243 mutex_enter(&sc->sc_lock); 2244 err = usb_insert_transfer(xfer); 2245 mutex_exit(&sc->sc_lock); 2246 if (err) 2247 return err; 2248 2249 /* 2250 * Pipe isn't running (otherwise err would be USBD_INPROG), 2251 * so start it first. 2252 */ 2253 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2254 } 2255 2256 usbd_status 2257 uhci_device_intr_start(usbd_xfer_handle xfer) 2258 { 2259 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2260 usbd_device_handle dev = upipe->pipe.up_dev; 2261 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2262 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2263 uhci_soft_td_t *data, *dataend; 2264 uhci_soft_qh_t *sqh; 2265 usbd_status err; 2266 int isread, endpt; 2267 int i; 2268 2269 if (sc->sc_dying) 2270 return USBD_IOERROR; 2271 2272 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2273 xfer, xfer->ux_length, xfer->ux_flags)); 2274 2275 #ifdef DIAGNOSTIC 2276 if (xfer->ux_rqflags & URQ_REQUEST) 2277 panic("uhci_device_intr_transfer: a request"); 2278 #endif 2279 2280 mutex_enter(&sc->sc_lock); 2281 2282 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2283 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2284 2285 upipe->u.intr.isread = isread; 2286 2287 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2288 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2289 &dataend); 2290 if (err) { 2291 mutex_exit(&sc->sc_lock); 2292 return err; 2293 } 2294 2295 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2296 usb_syncmem(&dataend->dma, 2297 dataend->offs + offsetof(uhci_td_t, td_status), 2298 sizeof(dataend->td.td_status), 2299 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2300 2301 #ifdef UHCI_DEBUG 2302 if (uhcidebug > 10) { 2303 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2304 uhci_dump_tds(data); 2305 uhci_dump_qh(upipe->u.intr.qhs[0]); 2306 } 2307 #endif 2308 2309 /* Set up interrupt info. */ 2310 ii->xfer = xfer; 2311 ii->stdstart = data; 2312 ii->stdend = dataend; 2313 #ifdef DIAGNOSTIC 2314 if (!ii->isdone) { 2315 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2316 } 2317 ii->isdone = 0; 2318 #endif 2319 2320 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2321 upipe->u.intr.qhs[0])); 2322 for (i = 0; i < upipe->u.intr.npoll; i++) { 2323 sqh = upipe->u.intr.qhs[i]; 2324 sqh->elink = data; 2325 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2326 usb_syncmem(&sqh->dma, 2327 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2328 sizeof(sqh->qh.qh_elink), 2329 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2330 } 2331 uhci_add_intr_info(sc, ii); 2332 xfer->ux_status = USBD_IN_PROGRESS; 2333 mutex_exit(&sc->sc_lock); 2334 2335 #ifdef UHCI_DEBUG 2336 if (uhcidebug > 10) { 2337 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2338 uhci_dump_tds(data); 2339 uhci_dump_qh(upipe->u.intr.qhs[0]); 2340 } 2341 #endif 2342 2343 return USBD_IN_PROGRESS; 2344 } 2345 2346 /* Abort a device control request. */ 2347 void 2348 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2349 { 2350 #ifdef DIAGNOSTIC 2351 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2352 #endif 2353 2354 KASSERT(mutex_owned(&sc->sc_lock)); 2355 2356 DPRINTF(("uhci_device_ctrl_abort:\n")); 2357 uhci_abort_xfer(xfer, USBD_CANCELLED); 2358 } 2359 2360 /* Close a device control pipe. */ 2361 void 2362 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2363 { 2364 } 2365 2366 /* Abort a device interrupt request. */ 2367 void 2368 uhci_device_intr_abort(usbd_xfer_handle xfer) 2369 { 2370 #ifdef DIAGNOSTIC 2371 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2372 #endif 2373 2374 KASSERT(mutex_owned(&sc->sc_lock)); 2375 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2376 2377 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2378 2379 uhci_abort_xfer(xfer, USBD_CANCELLED); 2380 } 2381 2382 /* Close a device interrupt pipe. */ 2383 void 2384 uhci_device_intr_close(usbd_pipe_handle pipe) 2385 { 2386 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2387 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2388 int i, npoll; 2389 2390 KASSERT(mutex_owned(&sc->sc_lock)); 2391 2392 /* Unlink descriptors from controller data structures. */ 2393 npoll = upipe->u.intr.npoll; 2394 for (i = 0; i < npoll; i++) 2395 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2396 2397 /* 2398 * We now have to wait for any activity on the physical 2399 * descriptors to stop. 2400 */ 2401 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2402 2403 for(i = 0; i < npoll; i++) 2404 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2405 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2406 2407 /* XXX free other resources */ 2408 } 2409 2410 usbd_status 2411 uhci_device_request(usbd_xfer_handle xfer) 2412 { 2413 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2414 usb_device_request_t *req = &xfer->ux_request; 2415 usbd_device_handle dev = upipe->pipe.up_dev; 2416 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2417 int addr = dev->ud_addr; 2418 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2419 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2420 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2421 uhci_soft_qh_t *sqh; 2422 int len; 2423 uint32_t ls; 2424 usbd_status err; 2425 int isread; 2426 2427 KASSERT(mutex_owned(&sc->sc_lock)); 2428 2429 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2430 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2431 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2432 UGETW(req->wIndex), UGETW(req->wLength), 2433 addr, endpt)); 2434 2435 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2436 isread = req->bmRequestType & UT_READ; 2437 len = UGETW(req->wLength); 2438 2439 setup = upipe->u.ctl.setup; 2440 stat = upipe->u.ctl.stat; 2441 sqh = upipe->u.ctl.sqh; 2442 2443 /* Set up data transaction */ 2444 if (len != 0) { 2445 upipe->nexttoggle = 1; 2446 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2447 &xfer->ux_dmabuf, &data, &dataend); 2448 if (err) 2449 return err; 2450 next = data; 2451 dataend->link.std = stat; 2452 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2453 usb_syncmem(&dataend->dma, 2454 dataend->offs + offsetof(uhci_td_t, td_link), 2455 sizeof(dataend->td.td_link), 2456 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2457 } else { 2458 next = stat; 2459 } 2460 upipe->u.ctl.length = len; 2461 2462 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2463 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2464 2465 setup->link.std = next; 2466 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2467 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2468 UHCI_TD_ACTIVE); 2469 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2470 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2471 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2472 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2473 2474 stat->link.std = NULL; 2475 stat->td.td_link = htole32(UHCI_PTR_T); 2476 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2477 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2478 stat->td.td_token = 2479 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2480 UHCI_TD_IN (0, endpt, addr, 1)); 2481 stat->td.td_buffer = htole32(0); 2482 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2484 2485 #ifdef UHCI_DEBUG 2486 if (uhcidebug > 10) { 2487 DPRINTF(("uhci_device_request: before transfer\n")); 2488 uhci_dump_tds(setup); 2489 } 2490 #endif 2491 2492 /* Set up interrupt info. */ 2493 ii->xfer = xfer; 2494 ii->stdstart = setup; 2495 ii->stdend = stat; 2496 #ifdef DIAGNOSTIC 2497 if (!ii->isdone) { 2498 printf("uhci_device_request: not done, ii=%p\n", ii); 2499 } 2500 ii->isdone = 0; 2501 #endif 2502 2503 sqh->elink = setup; 2504 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2505 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2506 2507 if (dev->ud_speed == USB_SPEED_LOW) 2508 uhci_add_ls_ctrl(sc, sqh); 2509 else 2510 uhci_add_hs_ctrl(sc, sqh); 2511 uhci_add_intr_info(sc, ii); 2512 #ifdef UHCI_DEBUG 2513 if (uhcidebug > 12) { 2514 uhci_soft_td_t *std; 2515 uhci_soft_qh_t *xqh; 2516 uhci_soft_qh_t *sxqh; 2517 int maxqh = 0; 2518 uhci_physaddr_t link; 2519 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2520 for (std = sc->sc_vframes[0].htd, link = 0; 2521 (link & UHCI_PTR_QH) == 0; 2522 std = std->link.std) { 2523 link = le32toh(std->td.td_link); 2524 uhci_dump_td(std); 2525 } 2526 sxqh = (uhci_soft_qh_t *)std; 2527 uhci_dump_qh(sxqh); 2528 for (xqh = sxqh; 2529 xqh != NULL; 2530 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2531 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2532 uhci_dump_qh(xqh); 2533 } 2534 DPRINTF(("Enqueued QH:\n")); 2535 uhci_dump_qh(sqh); 2536 uhci_dump_tds(sqh->elink); 2537 } 2538 #endif 2539 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2540 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2541 uhci_timeout, ii); 2542 } 2543 xfer->ux_status = USBD_IN_PROGRESS; 2544 2545 return USBD_NORMAL_COMPLETION; 2546 } 2547 2548 usbd_status 2549 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2550 { 2551 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2552 usbd_status err; 2553 2554 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2555 2556 /* Put it on our queue, */ 2557 mutex_enter(&sc->sc_lock); 2558 err = usb_insert_transfer(xfer); 2559 mutex_exit(&sc->sc_lock); 2560 2561 /* bail out on error, */ 2562 if (err && err != USBD_IN_PROGRESS) 2563 return err; 2564 2565 /* XXX should check inuse here */ 2566 2567 /* insert into schedule, */ 2568 uhci_device_isoc_enter(xfer); 2569 2570 /* and start if the pipe wasn't running */ 2571 if (!err) 2572 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2573 2574 return err; 2575 } 2576 2577 void 2578 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2579 { 2580 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2581 usbd_device_handle dev = upipe->pipe.up_dev; 2582 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2583 struct iso *iso = &upipe->u.iso; 2584 uhci_soft_td_t *std; 2585 uint32_t buf, len, status, offs; 2586 int i, next, nframes; 2587 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2588 2589 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2590 "nframes=%d\n", 2591 iso->inuse, iso->next, xfer, xfer->ux_nframes)); 2592 2593 if (sc->sc_dying) 2594 return; 2595 2596 if (xfer->ux_status == USBD_IN_PROGRESS) { 2597 /* This request has already been entered into the frame list */ 2598 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2599 /* XXX */ 2600 } 2601 2602 #ifdef DIAGNOSTIC 2603 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2604 printf("uhci_device_isoc_enter: overflow!\n"); 2605 #endif 2606 2607 next = iso->next; 2608 if (next == -1) { 2609 /* Not in use yet, schedule it a few frames ahead. */ 2610 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2611 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2612 } 2613 2614 xfer->ux_status = USBD_IN_PROGRESS; 2615 UXFER(xfer)->curframe = next; 2616 2617 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2618 offs = 0; 2619 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2620 UHCI_TD_ACTIVE | 2621 UHCI_TD_IOS); 2622 nframes = xfer->ux_nframes; 2623 mutex_enter(&sc->sc_lock); 2624 for (i = 0; i < nframes; i++) { 2625 std = iso->stds[next]; 2626 if (++next >= UHCI_VFRAMELIST_COUNT) 2627 next = 0; 2628 len = xfer->ux_frlengths[i]; 2629 std->td.td_buffer = htole32(buf); 2630 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2631 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2632 if (i == nframes - 1) 2633 status |= UHCI_TD_IOC; 2634 std->td.td_status = htole32(status); 2635 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2636 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2637 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2638 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2639 #ifdef UHCI_DEBUG 2640 if (uhcidebug > 5) { 2641 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2642 uhci_dump_td(std); 2643 } 2644 #endif 2645 buf += len; 2646 offs += len; 2647 } 2648 iso->next = next; 2649 iso->inuse += xfer->ux_nframes; 2650 2651 mutex_exit(&sc->sc_lock); 2652 } 2653 2654 usbd_status 2655 uhci_device_isoc_start(usbd_xfer_handle xfer) 2656 { 2657 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2658 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2659 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2660 uhci_soft_td_t *end; 2661 int i; 2662 2663 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2664 2665 mutex_enter(&sc->sc_lock); 2666 2667 if (sc->sc_dying) { 2668 mutex_exit(&sc->sc_lock); 2669 return USBD_IOERROR; 2670 } 2671 2672 #ifdef DIAGNOSTIC 2673 if (xfer->ux_status != USBD_IN_PROGRESS) 2674 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2675 #endif 2676 2677 /* Find the last TD */ 2678 i = UXFER(xfer)->curframe + xfer->ux_nframes; 2679 if (i >= UHCI_VFRAMELIST_COUNT) 2680 i -= UHCI_VFRAMELIST_COUNT; 2681 end = upipe->u.iso.stds[i]; 2682 2683 #ifdef DIAGNOSTIC 2684 if (end == NULL) { 2685 printf("uhci_device_isoc_start: end == NULL\n"); 2686 return USBD_INVAL; 2687 } 2688 #endif 2689 2690 /* Set up interrupt info. */ 2691 ii->xfer = xfer; 2692 ii->stdstart = end; 2693 ii->stdend = end; 2694 #ifdef DIAGNOSTIC 2695 if (!ii->isdone) 2696 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2697 ii->isdone = 0; 2698 #endif 2699 uhci_add_intr_info(sc, ii); 2700 2701 mutex_exit(&sc->sc_lock); 2702 2703 return USBD_IN_PROGRESS; 2704 } 2705 2706 void 2707 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2708 { 2709 #ifdef DIAGNOSTIC 2710 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2711 #endif 2712 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2713 uhci_soft_td_t **stds = upipe->u.iso.stds; 2714 uhci_soft_td_t *std; 2715 int i, n, nframes, maxlen, len; 2716 2717 KASSERT(mutex_owned(&sc->sc_lock)); 2718 2719 /* Transfer is already done. */ 2720 if (xfer->ux_status != USBD_NOT_STARTED && 2721 xfer->ux_status != USBD_IN_PROGRESS) { 2722 return; 2723 } 2724 2725 /* Give xfer the requested abort code. */ 2726 xfer->ux_status = USBD_CANCELLED; 2727 2728 /* make hardware ignore it, */ 2729 nframes = xfer->ux_nframes; 2730 n = UXFER(xfer)->curframe; 2731 maxlen = 0; 2732 for (i = 0; i < nframes; i++) { 2733 std = stds[n]; 2734 usb_syncmem(&std->dma, 2735 std->offs + offsetof(uhci_td_t, td_status), 2736 sizeof(std->td.td_status), 2737 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2738 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2739 usb_syncmem(&std->dma, 2740 std->offs + offsetof(uhci_td_t, td_status), 2741 sizeof(std->td.td_status), 2742 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2743 usb_syncmem(&std->dma, 2744 std->offs + offsetof(uhci_td_t, td_token), 2745 sizeof(std->td.td_token), 2746 BUS_DMASYNC_POSTWRITE); 2747 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2748 if (len > maxlen) 2749 maxlen = len; 2750 if (++n >= UHCI_VFRAMELIST_COUNT) 2751 n = 0; 2752 } 2753 2754 /* and wait until we are sure the hardware has finished. */ 2755 delay(maxlen); 2756 2757 #ifdef DIAGNOSTIC 2758 UXFER(xfer)->iinfo.isdone = 1; 2759 #endif 2760 /* Run callback and remove from interrupt list. */ 2761 usb_transfer_complete(xfer); 2762 2763 KASSERT(mutex_owned(&sc->sc_lock)); 2764 } 2765 2766 void 2767 uhci_device_isoc_close(usbd_pipe_handle pipe) 2768 { 2769 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2770 usbd_device_handle dev = upipe->pipe.up_dev; 2771 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2772 uhci_soft_td_t *std, *vstd; 2773 struct iso *iso; 2774 int i; 2775 2776 KASSERT(mutex_owned(&sc->sc_lock)); 2777 2778 /* 2779 * Make sure all TDs are marked as inactive. 2780 * Wait for completion. 2781 * Unschedule. 2782 * Deallocate. 2783 */ 2784 iso = &upipe->u.iso; 2785 2786 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2787 std = iso->stds[i]; 2788 usb_syncmem(&std->dma, 2789 std->offs + offsetof(uhci_td_t, td_status), 2790 sizeof(std->td.td_status), 2791 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2792 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2793 usb_syncmem(&std->dma, 2794 std->offs + offsetof(uhci_td_t, td_status), 2795 sizeof(std->td.td_status), 2796 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2797 } 2798 /* wait for completion */ 2799 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2800 2801 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2802 std = iso->stds[i]; 2803 for (vstd = sc->sc_vframes[i].htd; 2804 vstd != NULL && vstd->link.std != std; 2805 vstd = vstd->link.std) 2806 ; 2807 if (vstd == NULL) { 2808 /*panic*/ 2809 printf("uhci_device_isoc_close: %p not found\n", std); 2810 mutex_exit(&sc->sc_lock); 2811 return; 2812 } 2813 vstd->link = std->link; 2814 usb_syncmem(&std->dma, 2815 std->offs + offsetof(uhci_td_t, td_link), 2816 sizeof(std->td.td_link), 2817 BUS_DMASYNC_POSTWRITE); 2818 vstd->td.td_link = std->td.td_link; 2819 usb_syncmem(&vstd->dma, 2820 vstd->offs + offsetof(uhci_td_t, td_link), 2821 sizeof(vstd->td.td_link), 2822 BUS_DMASYNC_PREWRITE); 2823 uhci_free_std(sc, std); 2824 } 2825 2826 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2827 } 2828 2829 usbd_status 2830 uhci_setup_isoc(usbd_pipe_handle pipe) 2831 { 2832 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2833 usbd_device_handle dev = upipe->pipe.up_dev; 2834 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2835 int addr = upipe->pipe.up_dev->ud_addr; 2836 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2837 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2838 uhci_soft_td_t *std, *vstd; 2839 uint32_t token; 2840 struct iso *iso; 2841 int i; 2842 2843 iso = &upipe->u.iso; 2844 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2845 sizeof (uhci_soft_td_t *), 2846 KM_SLEEP); 2847 if (iso->stds == NULL) 2848 return USBD_NOMEM; 2849 2850 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2851 UHCI_TD_OUT(0, endpt, addr, 0); 2852 2853 mutex_enter(&sc->sc_lock); 2854 2855 /* Allocate the TDs and mark as inactive; */ 2856 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2857 std = uhci_alloc_std(sc); 2858 if (std == 0) 2859 goto bad; 2860 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2861 std->td.td_token = htole32(token); 2862 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2864 iso->stds[i] = std; 2865 } 2866 2867 /* Insert TDs into schedule. */ 2868 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2869 std = iso->stds[i]; 2870 vstd = sc->sc_vframes[i].htd; 2871 usb_syncmem(&vstd->dma, 2872 vstd->offs + offsetof(uhci_td_t, td_link), 2873 sizeof(vstd->td.td_link), 2874 BUS_DMASYNC_POSTWRITE); 2875 std->link = vstd->link; 2876 std->td.td_link = vstd->td.td_link; 2877 usb_syncmem(&std->dma, 2878 std->offs + offsetof(uhci_td_t, td_link), 2879 sizeof(std->td.td_link), 2880 BUS_DMASYNC_PREWRITE); 2881 vstd->link.std = std; 2882 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2883 usb_syncmem(&vstd->dma, 2884 vstd->offs + offsetof(uhci_td_t, td_link), 2885 sizeof(vstd->td.td_link), 2886 BUS_DMASYNC_PREWRITE); 2887 } 2888 mutex_exit(&sc->sc_lock); 2889 2890 iso->next = -1; 2891 iso->inuse = 0; 2892 2893 return USBD_NORMAL_COMPLETION; 2894 2895 bad: 2896 while (--i >= 0) 2897 uhci_free_std(sc, iso->stds[i]); 2898 mutex_exit(&sc->sc_lock); 2899 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2900 return USBD_NOMEM; 2901 } 2902 2903 void 2904 uhci_device_isoc_done(usbd_xfer_handle xfer) 2905 { 2906 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2907 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2908 int i, offs; 2909 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2910 2911 2912 DPRINTFN(4, ("uhci_isoc_done: length=%d, ux_state=0x%08x\n", 2913 xfer->ux_actlen, xfer->ux_state)); 2914 2915 if (ii->xfer != xfer) 2916 /* Not on interrupt list, ignore it. */ 2917 return; 2918 2919 if (!uhci_active_intr_info(ii)) 2920 return; 2921 2922 #ifdef DIAGNOSTIC 2923 if (ii->stdend == NULL) { 2924 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2925 #ifdef UHCI_DEBUG 2926 uhci_dump_ii(ii); 2927 #endif 2928 return; 2929 } 2930 #endif 2931 2932 /* Turn off the interrupt since it is active even if the TD is not. */ 2933 usb_syncmem(&ii->stdend->dma, 2934 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2935 sizeof(ii->stdend->td.td_status), 2936 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2937 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2938 usb_syncmem(&ii->stdend->dma, 2939 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2940 sizeof(ii->stdend->td.td_status), 2941 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2942 2943 uhci_del_intr_info(ii); /* remove from active list */ 2944 2945 offs = 0; 2946 for (i = 0; i < xfer->ux_nframes; i++) { 2947 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2948 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2949 offs += xfer->ux_frlengths[i]; 2950 } 2951 } 2952 2953 void 2954 uhci_device_intr_done(usbd_xfer_handle xfer) 2955 { 2956 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2957 uhci_softc_t *sc = ii->sc; 2958 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2959 uhci_soft_qh_t *sqh; 2960 int i, npoll, isread; 2961 2962 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->ux_actlen)); 2963 2964 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2965 2966 npoll = upipe->u.intr.npoll; 2967 for(i = 0; i < npoll; i++) { 2968 sqh = upipe->u.intr.qhs[i]; 2969 sqh->elink = NULL; 2970 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2971 usb_syncmem(&sqh->dma, 2972 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2973 sizeof(sqh->qh.qh_elink), 2974 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2975 } 2976 uhci_free_std_chain(sc, ii->stdstart, NULL); 2977 2978 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2979 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2980 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2981 2982 /* XXX Wasteful. */ 2983 if (xfer->ux_pipe->up_repeat) { 2984 uhci_soft_td_t *data, *dataend; 2985 2986 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2987 2988 /* This alloc cannot fail since we freed the chain above. */ 2989 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 2990 upipe->u.intr.isread, xfer->ux_flags, 2991 &xfer->ux_dmabuf, &data, &dataend); 2992 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2993 usb_syncmem(&dataend->dma, 2994 dataend->offs + offsetof(uhci_td_t, td_status), 2995 sizeof(dataend->td.td_status), 2996 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2997 2998 #ifdef UHCI_DEBUG 2999 if (uhcidebug > 10) { 3000 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3001 uhci_dump_tds(data); 3002 uhci_dump_qh(upipe->u.intr.qhs[0]); 3003 } 3004 #endif 3005 3006 ii->stdstart = data; 3007 ii->stdend = dataend; 3008 #ifdef DIAGNOSTIC 3009 if (!ii->isdone) { 3010 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3011 } 3012 ii->isdone = 0; 3013 #endif 3014 for (i = 0; i < npoll; i++) { 3015 sqh = upipe->u.intr.qhs[i]; 3016 sqh->elink = data; 3017 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3018 usb_syncmem(&sqh->dma, 3019 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3020 sizeof(sqh->qh.qh_elink), 3021 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3022 } 3023 xfer->ux_status = USBD_IN_PROGRESS; 3024 /* The ii is already on the examined list, just leave it. */ 3025 } else { 3026 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3027 if (uhci_active_intr_info(ii)) 3028 uhci_del_intr_info(ii); 3029 } 3030 } 3031 3032 /* Deallocate request data structures */ 3033 void 3034 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3035 { 3036 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3037 uhci_softc_t *sc = ii->sc; 3038 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3039 int len = UGETW(xfer->ux_request.wLength); 3040 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3041 3042 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3043 3044 #ifdef DIAGNOSTIC 3045 if (!(xfer->ux_rqflags & URQ_REQUEST)) 3046 panic("uhci_device_ctrl_done: not a request"); 3047 #endif 3048 3049 if (!uhci_active_intr_info(ii)) 3050 return; 3051 3052 uhci_del_intr_info(ii); /* remove from active list */ 3053 3054 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3055 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3056 else 3057 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3058 3059 if (upipe->u.ctl.length != 0) 3060 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3061 3062 if (len) { 3063 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3064 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3065 } 3066 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3067 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3068 3069 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->ux_actlen)); 3070 } 3071 3072 /* Deallocate request data structures */ 3073 void 3074 uhci_device_bulk_done(usbd_xfer_handle xfer) 3075 { 3076 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3077 uhci_softc_t *sc = ii->sc; 3078 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3079 3080 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3081 xfer, ii, sc, upipe)); 3082 3083 KASSERT(mutex_owned(&sc->sc_lock)); 3084 3085 if (!uhci_active_intr_info(ii)) 3086 return; 3087 3088 uhci_del_intr_info(ii); /* remove from active list */ 3089 3090 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3091 3092 uhci_free_std_chain(sc, ii->stdstart, NULL); 3093 3094 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->ux_actlen)); 3095 } 3096 3097 /* Add interrupt QH, called with vflock. */ 3098 void 3099 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3100 { 3101 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3102 uhci_soft_qh_t *eqh; 3103 3104 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3105 3106 eqh = vf->eqh; 3107 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3108 sizeof(eqh->qh.qh_hlink), 3109 BUS_DMASYNC_POSTWRITE); 3110 sqh->hlink = eqh->hlink; 3111 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3112 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3113 sizeof(sqh->qh.qh_hlink), 3114 BUS_DMASYNC_PREWRITE); 3115 eqh->hlink = sqh; 3116 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3117 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3118 sizeof(eqh->qh.qh_hlink), 3119 BUS_DMASYNC_PREWRITE); 3120 vf->eqh = sqh; 3121 vf->bandwidth++; 3122 } 3123 3124 /* Remove interrupt QH. */ 3125 void 3126 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3127 { 3128 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3129 uhci_soft_qh_t *pqh; 3130 3131 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3132 3133 /* See comment in uhci_remove_ctrl() */ 3134 3135 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3136 sizeof(sqh->qh.qh_elink), 3137 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3138 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3139 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3140 usb_syncmem(&sqh->dma, 3141 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3142 sizeof(sqh->qh.qh_elink), 3143 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3144 delay(UHCI_QH_REMOVE_DELAY); 3145 } 3146 3147 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3148 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3149 sizeof(sqh->qh.qh_hlink), 3150 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3151 pqh->hlink = sqh->hlink; 3152 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3153 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3154 sizeof(pqh->qh.qh_hlink), 3155 BUS_DMASYNC_PREWRITE); 3156 delay(UHCI_QH_REMOVE_DELAY); 3157 if (vf->eqh == sqh) 3158 vf->eqh = pqh; 3159 vf->bandwidth--; 3160 } 3161 3162 usbd_status 3163 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3164 { 3165 uhci_soft_qh_t *sqh; 3166 int i, npoll; 3167 u_int bestbw, bw, bestoffs, offs; 3168 3169 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3170 if (ival == 0) { 3171 printf("uhci_device_setintr: 0 interval\n"); 3172 return USBD_INVAL; 3173 } 3174 3175 if (ival > UHCI_VFRAMELIST_COUNT) 3176 ival = UHCI_VFRAMELIST_COUNT; 3177 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3178 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3179 3180 upipe->u.intr.npoll = npoll; 3181 upipe->u.intr.qhs = 3182 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3183 if (upipe->u.intr.qhs == NULL) 3184 return USBD_NOMEM; 3185 3186 /* 3187 * Figure out which offset in the schedule that has most 3188 * bandwidth left over. 3189 */ 3190 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3191 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3192 for (bw = i = 0; i < npoll; i++) 3193 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3194 if (bw < bestbw) { 3195 bestbw = bw; 3196 bestoffs = offs; 3197 } 3198 } 3199 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3200 3201 mutex_enter(&sc->sc_lock); 3202 for(i = 0; i < npoll; i++) { 3203 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3204 sqh->elink = NULL; 3205 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3206 usb_syncmem(&sqh->dma, 3207 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3208 sizeof(sqh->qh.qh_elink), 3209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3210 sqh->pos = MOD(i * ival + bestoffs); 3211 } 3212 #undef MOD 3213 3214 /* Enter QHs into the controller data structures. */ 3215 for(i = 0; i < npoll; i++) 3216 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3217 mutex_exit(&sc->sc_lock); 3218 3219 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3220 return USBD_NORMAL_COMPLETION; 3221 } 3222 3223 /* Open a new pipe. */ 3224 usbd_status 3225 uhci_open(usbd_pipe_handle pipe) 3226 { 3227 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3228 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3229 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3230 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3231 usbd_status err = USBD_NOMEM; 3232 int ival; 3233 3234 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3235 pipe, pipe->up_dev->ud_addr, 3236 ed->bEndpointAddress, bus->ub_rhaddr)); 3237 3238 if (sc->sc_dying) 3239 return USBD_IOERROR; 3240 3241 upipe->aborting = 0; 3242 /* toggle state needed for bulk endpoints */ 3243 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3244 3245 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3246 switch (ed->bEndpointAddress) { 3247 case USB_CONTROL_ENDPOINT: 3248 pipe->up_methods = &roothub_ctrl_methods; 3249 break; 3250 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3251 pipe->up_methods = &uhci_root_intr_methods; 3252 break; 3253 default: 3254 return USBD_INVAL; 3255 } 3256 } else { 3257 switch (ed->bmAttributes & UE_XFERTYPE) { 3258 case UE_CONTROL: 3259 pipe->up_methods = &uhci_device_ctrl_methods; 3260 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3261 if (upipe->u.ctl.sqh == NULL) 3262 goto bad; 3263 upipe->u.ctl.setup = uhci_alloc_std(sc); 3264 if (upipe->u.ctl.setup == NULL) { 3265 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3266 goto bad; 3267 } 3268 upipe->u.ctl.stat = uhci_alloc_std(sc); 3269 if (upipe->u.ctl.stat == NULL) { 3270 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3271 uhci_free_std(sc, upipe->u.ctl.setup); 3272 goto bad; 3273 } 3274 err = usb_allocmem(&sc->sc_bus, 3275 sizeof(usb_device_request_t), 3276 0, &upipe->u.ctl.reqdma); 3277 if (err) { 3278 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3279 uhci_free_std(sc, upipe->u.ctl.setup); 3280 uhci_free_std(sc, upipe->u.ctl.stat); 3281 goto bad; 3282 } 3283 break; 3284 case UE_INTERRUPT: 3285 pipe->up_methods = &uhci_device_intr_methods; 3286 ival = pipe->up_interval; 3287 if (ival == USBD_DEFAULT_INTERVAL) 3288 ival = ed->bInterval; 3289 return uhci_device_setintr(sc, upipe, ival); 3290 case UE_ISOCHRONOUS: 3291 pipe->up_methods = &uhci_device_isoc_methods; 3292 return uhci_setup_isoc(pipe); 3293 case UE_BULK: 3294 pipe->up_methods = &uhci_device_bulk_methods; 3295 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3296 if (upipe->u.bulk.sqh == NULL) 3297 goto bad; 3298 break; 3299 } 3300 } 3301 return USBD_NORMAL_COMPLETION; 3302 3303 bad: 3304 return USBD_NOMEM; 3305 } 3306 3307 /* 3308 * Data structures and routines to emulate the root hub. 3309 */ 3310 /* 3311 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3312 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3313 * should not be used by the USB subsystem. As we cannot issue a 3314 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3315 * will be enabled as part of the reset. 3316 * 3317 * On the VT83C572, the port cannot be successfully enabled until the 3318 * outstanding "port enable change" and "connection status change" 3319 * events have been reset. 3320 */ 3321 Static usbd_status 3322 uhci_portreset(uhci_softc_t *sc, int index) 3323 { 3324 int lim, port, x; 3325 3326 if (index == 1) 3327 port = UHCI_PORTSC1; 3328 else if (index == 2) 3329 port = UHCI_PORTSC2; 3330 else 3331 return USBD_IOERROR; 3332 3333 x = URWMASK(UREAD2(sc, port)); 3334 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3335 3336 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3337 3338 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3339 index, UREAD2(sc, port))); 3340 3341 x = URWMASK(UREAD2(sc, port)); 3342 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3343 3344 delay(100); 3345 3346 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3347 index, UREAD2(sc, port))); 3348 3349 x = URWMASK(UREAD2(sc, port)); 3350 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3351 3352 for (lim = 10; --lim > 0;) { 3353 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3354 3355 x = UREAD2(sc, port); 3356 3357 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3358 index, lim, x)); 3359 3360 if (!(x & UHCI_PORTSC_CCS)) { 3361 /* 3362 * No device is connected (or was disconnected 3363 * during reset). Consider the port reset. 3364 * The delay must be long enough to ensure on 3365 * the initial iteration that the device 3366 * connection will have been registered. 50ms 3367 * appears to be sufficient, but 20ms is not. 3368 */ 3369 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3370 index, lim)); 3371 break; 3372 } 3373 3374 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3375 /* 3376 * Port enabled changed and/or connection 3377 * status changed were set. Reset either or 3378 * both raised flags (by writing a 1 to that 3379 * bit), and wait again for state to settle. 3380 */ 3381 UWRITE2(sc, port, URWMASK(x) | 3382 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3383 continue; 3384 } 3385 3386 if (x & UHCI_PORTSC_PE) 3387 /* Port is enabled */ 3388 break; 3389 3390 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3391 } 3392 3393 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3394 index, UREAD2(sc, port))); 3395 3396 if (lim <= 0) { 3397 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3398 return USBD_TIMEOUT; 3399 } 3400 3401 sc->sc_isreset = 1; 3402 return USBD_NORMAL_COMPLETION; 3403 } 3404 3405 Static int 3406 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3407 void *buf, int buflen) 3408 { 3409 uhci_softc_t *sc = bus->ub_hcpriv; 3410 int port, x; 3411 int status, change, totlen = 0; 3412 uint16_t len, value, index; 3413 usb_port_status_t ps; 3414 usbd_status err; 3415 3416 if (sc->sc_dying) 3417 return -1; 3418 3419 DPRINTFN(2,("%s: type=0x%02x request=%02x\n", __func__, 3420 req->bmRequestType, req->bRequest)); 3421 3422 len = UGETW(req->wLength); 3423 value = UGETW(req->wValue); 3424 index = UGETW(req->wIndex); 3425 3426 #define C(x,y) ((x) | ((y) << 8)) 3427 switch (C(req->bRequest, req->bmRequestType)) { 3428 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3429 DPRINTFN(2,("%s: wValue=0x%04x\n", __func__, value)); 3430 if (len == 0) 3431 break; 3432 switch (value) { 3433 case C(0, UDESC_DEVICE): { 3434 usb_device_descriptor_t devd; 3435 3436 totlen = min(buflen, sizeof(devd)); 3437 memcpy(&devd, buf, totlen); 3438 USETW(devd.idVendor, sc->sc_id_vendor); 3439 memcpy(buf, &devd, totlen); 3440 break; 3441 } 3442 case C(1, UDESC_STRING): 3443 #define sd ((usb_string_descriptor_t *)buf) 3444 /* Vendor */ 3445 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3446 break; 3447 case C(2, UDESC_STRING): 3448 /* Product */ 3449 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3450 break; 3451 #undef sd 3452 default: 3453 /* default from usbroothub */ 3454 return buflen; 3455 } 3456 break; 3457 3458 /* Hub requests */ 3459 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3460 break; 3461 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3462 DPRINTFN(3, ("%s: UR_CLEAR_PORT_FEATURE " 3463 "port=%d feature=%d\n", __func__, 3464 index, value)); 3465 if (index == 1) 3466 port = UHCI_PORTSC1; 3467 else if (index == 2) 3468 port = UHCI_PORTSC2; 3469 else { 3470 return -1; 3471 } 3472 switch(value) { 3473 case UHF_PORT_ENABLE: 3474 x = URWMASK(UREAD2(sc, port)); 3475 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3476 break; 3477 case UHF_PORT_SUSPEND: 3478 x = URWMASK(UREAD2(sc, port)); 3479 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3480 break; 3481 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3482 /* see USB2 spec ch. 7.1.7.7 */ 3483 usb_delay_ms(&sc->sc_bus, 20); 3484 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3485 /* 10ms resume delay must be provided by caller */ 3486 break; 3487 case UHF_PORT_RESET: 3488 x = URWMASK(UREAD2(sc, port)); 3489 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3490 break; 3491 case UHF_C_PORT_CONNECTION: 3492 x = URWMASK(UREAD2(sc, port)); 3493 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3494 break; 3495 case UHF_C_PORT_ENABLE: 3496 x = URWMASK(UREAD2(sc, port)); 3497 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3498 break; 3499 case UHF_C_PORT_OVER_CURRENT: 3500 x = URWMASK(UREAD2(sc, port)); 3501 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3502 break; 3503 case UHF_C_PORT_RESET: 3504 sc->sc_isreset = 0; 3505 return -1; 3506 case UHF_PORT_CONNECTION: 3507 case UHF_PORT_OVER_CURRENT: 3508 case UHF_PORT_POWER: 3509 case UHF_PORT_LOW_SPEED: 3510 case UHF_C_PORT_SUSPEND: 3511 default: 3512 return -1; 3513 } 3514 break; 3515 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3516 if (index == 1) 3517 port = UHCI_PORTSC1; 3518 else if (index == 2) 3519 port = UHCI_PORTSC2; 3520 else { 3521 return -1; 3522 } 3523 if (len > 0) { 3524 *(uint8_t *)buf = 3525 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3526 UHCI_PORTSC_LS_SHIFT; 3527 totlen = 1; 3528 } 3529 break; 3530 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3531 if (len == 0) 3532 break; 3533 if ((value & 0xff) != 0) { 3534 return -1; 3535 } 3536 usb_hub_descriptor_t hubd; 3537 3538 totlen = min(buflen, sizeof(hubd)); 3539 memcpy(&hubd, buf, totlen); 3540 hubd.bNbrPorts = 2; 3541 memcpy(buf, &hubd, totlen); 3542 break; 3543 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3544 if (len != 4) { 3545 return -1; 3546 } 3547 memset(buf, 0, len); 3548 totlen = len; 3549 break; 3550 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3551 if (index == 1) 3552 port = UHCI_PORTSC1; 3553 else if (index == 2) 3554 port = UHCI_PORTSC2; 3555 else { 3556 return -1; 3557 } 3558 if (len != 4) { 3559 return -1; 3560 } 3561 x = UREAD2(sc, port); 3562 status = change = 0; 3563 if (x & UHCI_PORTSC_CCS) 3564 status |= UPS_CURRENT_CONNECT_STATUS; 3565 if (x & UHCI_PORTSC_CSC) 3566 change |= UPS_C_CONNECT_STATUS; 3567 if (x & UHCI_PORTSC_PE) 3568 status |= UPS_PORT_ENABLED; 3569 if (x & UHCI_PORTSC_POEDC) 3570 change |= UPS_C_PORT_ENABLED; 3571 if (x & UHCI_PORTSC_OCI) 3572 status |= UPS_OVERCURRENT_INDICATOR; 3573 if (x & UHCI_PORTSC_OCIC) 3574 change |= UPS_C_OVERCURRENT_INDICATOR; 3575 if (x & UHCI_PORTSC_SUSP) 3576 status |= UPS_SUSPEND; 3577 if (x & UHCI_PORTSC_LSDA) 3578 status |= UPS_LOW_SPEED; 3579 status |= UPS_PORT_POWER; 3580 if (sc->sc_isreset) 3581 change |= UPS_C_PORT_RESET; 3582 USETW(ps.wPortStatus, status); 3583 USETW(ps.wPortChange, change); 3584 totlen = min(len, sizeof(ps)); 3585 memcpy(buf, &ps, totlen); 3586 break; 3587 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3588 return -1; 3589 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3590 break; 3591 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3592 if (index == 1) 3593 port = UHCI_PORTSC1; 3594 else if (index == 2) 3595 port = UHCI_PORTSC2; 3596 else { 3597 return -1; 3598 } 3599 switch(value) { 3600 case UHF_PORT_ENABLE: 3601 x = URWMASK(UREAD2(sc, port)); 3602 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3603 break; 3604 case UHF_PORT_SUSPEND: 3605 x = URWMASK(UREAD2(sc, port)); 3606 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3607 break; 3608 case UHF_PORT_RESET: 3609 err = uhci_portreset(sc, index); 3610 if (err != USBD_NORMAL_COMPLETION) 3611 return -1; 3612 return 0; 3613 case UHF_PORT_POWER: 3614 /* Pretend we turned on power */ 3615 return 0; 3616 case UHF_C_PORT_CONNECTION: 3617 case UHF_C_PORT_ENABLE: 3618 case UHF_C_PORT_OVER_CURRENT: 3619 case UHF_PORT_CONNECTION: 3620 case UHF_PORT_OVER_CURRENT: 3621 case UHF_PORT_LOW_SPEED: 3622 case UHF_C_PORT_SUSPEND: 3623 case UHF_C_PORT_RESET: 3624 default: 3625 return -1; 3626 } 3627 break; 3628 default: 3629 /* default from usbroothub */ 3630 return buflen; 3631 } 3632 3633 return totlen; 3634 } 3635 3636 /* Abort a root interrupt request. */ 3637 void 3638 uhci_root_intr_abort(usbd_xfer_handle xfer) 3639 { 3640 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3641 3642 KASSERT(mutex_owned(&sc->sc_lock)); 3643 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3644 3645 callout_stop(&sc->sc_poll_handle); 3646 sc->sc_intr_xfer = NULL; 3647 3648 xfer->ux_status = USBD_CANCELLED; 3649 #ifdef DIAGNOSTIC 3650 UXFER(xfer)->iinfo.isdone = 1; 3651 #endif 3652 usb_transfer_complete(xfer); 3653 } 3654 3655 usbd_status 3656 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3657 { 3658 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3659 usbd_status err; 3660 3661 /* Insert last in queue. */ 3662 mutex_enter(&sc->sc_lock); 3663 err = usb_insert_transfer(xfer); 3664 mutex_exit(&sc->sc_lock); 3665 if (err) 3666 return err; 3667 3668 /* 3669 * Pipe isn't running (otherwise err would be USBD_INPROG), 3670 * start first 3671 */ 3672 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3673 } 3674 3675 /* Start a transfer on the root interrupt pipe */ 3676 usbd_status 3677 uhci_root_intr_start(usbd_xfer_handle xfer) 3678 { 3679 usbd_pipe_handle pipe = xfer->ux_pipe; 3680 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3681 unsigned int ival; 3682 3683 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3684 xfer, xfer->ux_length, xfer->ux_flags)); 3685 3686 if (sc->sc_dying) 3687 return USBD_IOERROR; 3688 3689 /* XXX temporary variable needed to avoid gcc3 warning */ 3690 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3691 sc->sc_ival = mstohz(ival); 3692 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3693 sc->sc_intr_xfer = xfer; 3694 return USBD_IN_PROGRESS; 3695 } 3696 3697 /* Close the root interrupt pipe. */ 3698 void 3699 uhci_root_intr_close(usbd_pipe_handle pipe) 3700 { 3701 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3702 3703 KASSERT(mutex_owned(&sc->sc_lock)); 3704 3705 callout_stop(&sc->sc_poll_handle); 3706 sc->sc_intr_xfer = NULL; 3707 DPRINTF(("uhci_root_intr_close\n")); 3708 } 3709
Indexes created Tue Sep 30 17:09:57 GMT 2025