uhci.c revision 1.264.4.17
1 /* $NetBSD: uhci.c,v 1.264.4.17 2015/02/01 11:13:46 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.17 2015/02/01 11:13:46 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int, int); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *); 163 Static void uhci_rem_loop(uhci_softc_t *); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 169 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 170 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 171 Static int uhci_roothub_ctrl(struct usbd_bus *, 172 usb_device_request_t *, void *, int); 173 174 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 175 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 176 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 177 Static void uhci_device_ctrl_close(usbd_pipe_handle); 178 Static void uhci_device_ctrl_done(usbd_xfer_handle); 179 180 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 182 Static void uhci_device_intr_abort(usbd_xfer_handle); 183 Static void uhci_device_intr_close(usbd_pipe_handle); 184 Static void uhci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 187 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 188 Static void uhci_device_bulk_abort(usbd_xfer_handle); 189 Static void uhci_device_bulk_close(usbd_pipe_handle); 190 Static void uhci_device_bulk_done(usbd_xfer_handle); 191 192 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 193 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 194 Static void uhci_device_isoc_abort(usbd_xfer_handle); 195 Static void uhci_device_isoc_close(usbd_pipe_handle); 196 Static void uhci_device_isoc_done(usbd_xfer_handle); 197 198 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 199 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 200 Static void uhci_root_intr_abort(usbd_xfer_handle); 201 Static void uhci_root_intr_close(usbd_pipe_handle); 202 Static void uhci_root_intr_done(usbd_xfer_handle); 203 204 Static usbd_status uhci_open(usbd_pipe_handle); 205 Static void uhci_poll(struct usbd_bus *); 206 Static void uhci_softintr(void *); 207 208 Static usbd_status uhci_device_request(usbd_xfer_handle); 209 210 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 211 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 212 Static usbd_status uhci_device_setintr(uhci_softc_t *, 213 struct uhci_pipe *, int); 214 215 Static void uhci_device_clear_toggle(usbd_pipe_handle); 216 Static void uhci_noop(usbd_pipe_handle); 217 218 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 219 uhci_soft_qh_t *); 220 221 #ifdef UHCI_DEBUG 222 Static void uhci_dump_all(uhci_softc_t *); 223 Static void uhci_dumpregs(uhci_softc_t *); 224 Static void uhci_dump_qhs(uhci_soft_qh_t *); 225 Static void uhci_dump_qh(uhci_soft_qh_t *); 226 Static void uhci_dump_tds(uhci_soft_td_t *); 227 Static void uhci_dump_td(uhci_soft_td_t *); 228 Static void uhci_dump_ii(uhci_intr_info_t *); 229 void uhci_dump(void); 230 #endif 231 232 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 233 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 234 #define UWRITE1(sc, r, x) \ 235 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 236 } while (/*CONSTCOND*/0) 237 #define UWRITE2(sc, r, x) \ 238 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 239 } while (/*CONSTCOND*/0) 240 #define UWRITE4(sc, r, x) \ 241 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 242 } while (/*CONSTCOND*/0) 243 static __inline uint8_t 244 UREAD1(uhci_softc_t *sc, bus_size_t r) 245 { 246 247 UBARR(sc); 248 return bus_space_read_1(sc->iot, sc->ioh, r); 249 } 250 251 static __inline uint16_t 252 UREAD2(uhci_softc_t *sc, bus_size_t r) 253 { 254 255 UBARR(sc); 256 return bus_space_read_2(sc->iot, sc->ioh, r); 257 } 258 259 #ifdef UHCI_DEBUG 260 static __inline uint32_t 261 UREAD4(uhci_softc_t *sc, bus_size_t r) 262 { 263 264 UBARR(sc); 265 return bus_space_read_4(sc->iot, sc->ioh, r); 266 } 267 #endif 268 269 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 270 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 271 272 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 273 274 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 275 276 const struct usbd_bus_methods uhci_bus_methods = { 277 .ubm_open = uhci_open, 278 .ubm_softint = uhci_softintr, 279 .ubm_dopoll = uhci_poll, 280 .ubm_allocx = uhci_allocx, 281 .ubm_freex = uhci_freex, 282 .ubm_getlock = uhci_get_lock, 283 .ubm_rhctrl = uhci_roothub_ctrl, 284 }; 285 286 const struct usbd_pipe_methods uhci_root_intr_methods = { 287 .upm_transfer = uhci_root_intr_transfer, 288 .upm_start = uhci_root_intr_start, 289 .upm_abort = uhci_root_intr_abort, 290 .upm_close = uhci_root_intr_close, 291 .upm_cleartoggle = uhci_noop, 292 .upm_done = uhci_root_intr_done, 293 }; 294 295 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 296 .upm_transfer = uhci_device_ctrl_transfer, 297 .upm_start = uhci_device_ctrl_start, 298 .upm_abort = uhci_device_ctrl_abort, 299 .upm_close = uhci_device_ctrl_close, 300 .upm_cleartoggle = uhci_noop, 301 .upm_done = uhci_device_ctrl_done, 302 }; 303 304 const struct usbd_pipe_methods uhci_device_intr_methods = { 305 .upm_transfer = uhci_device_intr_transfer, 306 .upm_start = uhci_device_intr_start, 307 .upm_abort = uhci_device_intr_abort, 308 .upm_close = uhci_device_intr_close, 309 .upm_cleartoggle = uhci_device_clear_toggle, 310 .upm_done = uhci_device_intr_done, 311 }; 312 313 const struct usbd_pipe_methods uhci_device_bulk_methods = { 314 .upm_transfer = uhci_device_bulk_transfer, 315 .upm_start = uhci_device_bulk_start, 316 .upm_abort = uhci_device_bulk_abort, 317 .upm_close = uhci_device_bulk_close, 318 .upm_cleartoggle = uhci_device_clear_toggle, 319 .upm_done = uhci_device_bulk_done, 320 }; 321 322 const struct usbd_pipe_methods uhci_device_isoc_methods = { 323 .upm_transfer = uhci_device_isoc_transfer, 324 .upm_start = uhci_device_isoc_start, 325 .upm_abort = uhci_device_isoc_abort, 326 .upm_close = uhci_device_isoc_close, 327 .upm_cleartoggle = uhci_noop, 328 .upm_done = uhci_device_isoc_done, 329 }; 330 331 #define uhci_add_intr_info(sc, ii) \ 332 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 333 #define uhci_del_intr_info(ii) \ 334 do { \ 335 LIST_REMOVE((ii), list); \ 336 (ii)->list.le_prev = NULL; \ 337 } while (0) 338 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 339 340 static inline uhci_soft_qh_t * 341 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 342 { 343 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 344 345 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 346 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 347 usb_syncmem(&pqh->dma, 348 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 349 sizeof(pqh->qh.qh_hlink), 350 BUS_DMASYNC_POSTWRITE); 351 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 352 printf("uhci_find_prev_qh: QH not found\n"); 353 return NULL; 354 } 355 #endif 356 } 357 return pqh; 358 } 359 360 void 361 uhci_globalreset(uhci_softc_t *sc) 362 { 363 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 364 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 365 UHCICMD(sc, 0); /* do nothing */ 366 } 367 368 int 369 uhci_init(uhci_softc_t *sc) 370 { 371 usbd_status err; 372 int i, j; 373 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 374 uhci_soft_td_t *std; 375 376 DPRINTFN(1,("uhci_init: start\n")); 377 378 #ifdef UHCI_DEBUG 379 thesc = sc; 380 381 if (uhcidebug > 2) 382 uhci_dumpregs(sc); 383 #endif 384 385 sc->sc_suspend = PWR_RESUME; 386 387 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 388 uhci_globalreset(sc); /* reset the controller */ 389 uhci_reset(sc); 390 391 /* Allocate and initialize real frame array. */ 392 err = usb_allocmem(&sc->sc_bus, 393 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 394 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 395 if (err) 396 return err; 397 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 398 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 399 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 400 401 /* 402 * Allocate a TD, inactive, that hangs from the last QH. 403 * This is to avoid a bug in the PIIX that makes it run berserk 404 * otherwise. 405 */ 406 std = uhci_alloc_std(sc); 407 if (std == NULL) 408 return ENOMEM; 409 std->link.std = NULL; 410 std->td.td_link = htole32(UHCI_PTR_T); 411 std->td.td_status = htole32(0); /* inactive */ 412 std->td.td_token = htole32(0); 413 std->td.td_buffer = htole32(0); 414 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 415 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 416 417 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 418 lsqh = uhci_alloc_sqh(sc); 419 if (lsqh == NULL) 420 return ENOMEM; 421 lsqh->hlink = NULL; 422 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 423 lsqh->elink = std; 424 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 425 sc->sc_last_qh = lsqh; 426 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 427 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 428 429 /* Allocate the dummy QH where bulk traffic will be queued. */ 430 bsqh = uhci_alloc_sqh(sc); 431 if (bsqh == NULL) 432 return ENOMEM; 433 bsqh->hlink = lsqh; 434 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 435 bsqh->elink = NULL; 436 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 437 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 438 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 439 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 440 441 /* Allocate dummy QH where high speed control traffic will be queued. */ 442 chsqh = uhci_alloc_sqh(sc); 443 if (chsqh == NULL) 444 return ENOMEM; 445 chsqh->hlink = bsqh; 446 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 447 chsqh->elink = NULL; 448 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 449 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 450 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 452 453 /* Allocate dummy QH where control traffic will be queued. */ 454 clsqh = uhci_alloc_sqh(sc); 455 if (clsqh == NULL) 456 return ENOMEM; 457 clsqh->hlink = chsqh; 458 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 459 clsqh->elink = NULL; 460 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 461 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 462 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 463 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 464 465 /* 466 * Make all (virtual) frame list pointers point to the interrupt 467 * queue heads and the interrupt queue heads at the control 468 * queue head and point the physical frame list to the virtual. 469 */ 470 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 471 std = uhci_alloc_std(sc); 472 sqh = uhci_alloc_sqh(sc); 473 if (std == NULL || sqh == NULL) 474 return USBD_NOMEM; 475 std->link.sqh = sqh; 476 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 477 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 478 std->td.td_token = htole32(0); 479 std->td.td_buffer = htole32(0); 480 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 482 sqh->hlink = clsqh; 483 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 484 sqh->elink = NULL; 485 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 486 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 488 sc->sc_vframes[i].htd = std; 489 sc->sc_vframes[i].etd = std; 490 sc->sc_vframes[i].hqh = sqh; 491 sc->sc_vframes[i].eqh = sqh; 492 for (j = i; 493 j < UHCI_FRAMELIST_COUNT; 494 j += UHCI_VFRAMELIST_COUNT) 495 sc->sc_pframes[j] = htole32(std->physaddr); 496 } 497 usb_syncmem(&sc->sc_dma, 0, 498 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 499 BUS_DMASYNC_PREWRITE); 500 501 502 LIST_INIT(&sc->sc_intrhead); 503 504 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 505 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 506 507 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 508 509 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 510 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 511 cv_init(&sc->sc_softwake_cv, "uhciab"); 512 513 /* Set up the bus struct. */ 514 sc->sc_bus.ub_methods = &uhci_bus_methods; 515 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 516 sc->sc_bus.ub_usedma = true; 517 518 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 519 520 DPRINTFN(1,("uhci_init: enabling\n")); 521 522 err = uhci_run(sc, 1, 0); /* and here we go... */ 523 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 524 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 525 return err; 526 } 527 528 int 529 uhci_activate(device_t self, enum devact act) 530 { 531 struct uhci_softc *sc = device_private(self); 532 533 switch (act) { 534 case DVACT_DEACTIVATE: 535 sc->sc_dying = 1; 536 return 0; 537 default: 538 return EOPNOTSUPP; 539 } 540 } 541 542 void 543 uhci_childdet(device_t self, device_t child) 544 { 545 struct uhci_softc *sc = device_private(self); 546 547 KASSERT(sc->sc_child == child); 548 sc->sc_child = NULL; 549 } 550 551 int 552 uhci_detach(struct uhci_softc *sc, int flags) 553 { 554 int rv = 0; 555 556 if (sc->sc_child != NULL) 557 rv = config_detach(sc->sc_child, flags); 558 559 if (rv != 0) 560 return rv; 561 562 callout_halt(&sc->sc_poll_handle, NULL); 563 callout_destroy(&sc->sc_poll_handle); 564 565 cv_destroy(&sc->sc_softwake_cv); 566 567 mutex_destroy(&sc->sc_lock); 568 mutex_destroy(&sc->sc_intr_lock); 569 570 pool_cache_destroy(sc->sc_xferpool); 571 572 /* XXX free other data structures XXX */ 573 574 return rv; 575 } 576 577 usbd_xfer_handle 578 uhci_allocx(struct usbd_bus *bus) 579 { 580 struct uhci_softc *sc = bus->ub_hcpriv; 581 usbd_xfer_handle xfer; 582 583 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 584 if (xfer != NULL) { 585 memset(xfer, 0, sizeof(struct uhci_xfer)); 586 UXFER(xfer)->iinfo.sc = sc; 587 #ifdef DIAGNOSTIC 588 UXFER(xfer)->iinfo.isdone = 1; 589 xfer->ux_state = XFER_BUSY; 590 #endif 591 } 592 return xfer; 593 } 594 595 void 596 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 597 { 598 struct uhci_softc *sc = bus->ub_hcpriv; 599 600 #ifdef DIAGNOSTIC 601 if (xfer->ux_state != XFER_BUSY) { 602 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 603 xfer->ux_state); 604 } 605 xfer->ux_state = XFER_FREE; 606 if (!UXFER(xfer)->iinfo.isdone) { 607 printf("uhci_freex: !isdone\n"); 608 } 609 #endif 610 pool_cache_put(sc->sc_xferpool, xfer); 611 } 612 613 Static void 614 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 615 { 616 struct uhci_softc *sc = bus->ub_hcpriv; 617 618 *lock = &sc->sc_lock; 619 } 620 621 622 /* 623 * Handle suspend/resume. 624 * 625 * We need to switch to polling mode here, because this routine is 626 * called from an interrupt context. This is all right since we 627 * are almost suspended anyway. 628 */ 629 bool 630 uhci_resume(device_t dv, const pmf_qual_t *qual) 631 { 632 uhci_softc_t *sc = device_private(dv); 633 int cmd; 634 635 mutex_spin_enter(&sc->sc_intr_lock); 636 637 cmd = UREAD2(sc, UHCI_CMD); 638 sc->sc_bus.ub_usepolling++; 639 UWRITE2(sc, UHCI_INTR, 0); 640 uhci_globalreset(sc); 641 uhci_reset(sc); 642 if (cmd & UHCI_CMD_RS) 643 uhci_run(sc, 0, 1); 644 645 /* restore saved state */ 646 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 647 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 648 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 649 650 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 651 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 652 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 653 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 654 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 655 UHCICMD(sc, UHCI_CMD_MAXP); 656 uhci_run(sc, 1, 1); /* and start traffic again */ 657 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 658 sc->sc_bus.ub_usepolling--; 659 if (sc->sc_intr_xfer != NULL) 660 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 661 sc->sc_intr_xfer); 662 #ifdef UHCI_DEBUG 663 if (uhcidebug > 2) 664 uhci_dumpregs(sc); 665 #endif 666 667 sc->sc_suspend = PWR_RESUME; 668 mutex_spin_exit(&sc->sc_intr_lock); 669 670 return true; 671 } 672 673 bool 674 uhci_suspend(device_t dv, const pmf_qual_t *qual) 675 { 676 uhci_softc_t *sc = device_private(dv); 677 int cmd; 678 679 mutex_spin_enter(&sc->sc_intr_lock); 680 681 cmd = UREAD2(sc, UHCI_CMD); 682 683 #ifdef UHCI_DEBUG 684 if (uhcidebug > 2) 685 uhci_dumpregs(sc); 686 #endif 687 if (sc->sc_intr_xfer != NULL) 688 callout_stop(&sc->sc_poll_handle); 689 sc->sc_suspend = PWR_SUSPEND; 690 sc->sc_bus.ub_usepolling++; 691 692 uhci_run(sc, 0, 1); /* stop the controller */ 693 cmd &= ~UHCI_CMD_RS; 694 695 /* save some state if BIOS doesn't */ 696 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 697 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 698 699 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 700 701 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 702 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 703 sc->sc_bus.ub_usepolling--; 704 705 mutex_spin_exit(&sc->sc_intr_lock); 706 707 return true; 708 } 709 710 #ifdef UHCI_DEBUG 711 Static void 712 uhci_dumpregs(uhci_softc_t *sc) 713 { 714 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 715 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 716 device_xname(sc->sc_dev), 717 UREAD2(sc, UHCI_CMD), 718 UREAD2(sc, UHCI_STS), 719 UREAD2(sc, UHCI_INTR), 720 UREAD2(sc, UHCI_FRNUM), 721 UREAD4(sc, UHCI_FLBASEADDR), 722 UREAD1(sc, UHCI_SOF), 723 UREAD2(sc, UHCI_PORTSC1), 724 UREAD2(sc, UHCI_PORTSC2))); 725 } 726 727 void 728 uhci_dump_td(uhci_soft_td_t *p) 729 { 730 char sbuf[128], sbuf2[128]; 731 732 733 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 734 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 735 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 736 "token=0x%08lx buffer=0x%08lx\n", 737 p, (long)p->physaddr, 738 (long)le32toh(p->td.td_link), 739 (long)le32toh(p->td.td_status), 740 (long)le32toh(p->td.td_token), 741 (long)le32toh(p->td.td_buffer))); 742 743 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 744 (uint32_t)le32toh(p->td.td_link)); 745 snprintb(sbuf2, sizeof(sbuf2), 746 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 747 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 748 (uint32_t)le32toh(p->td.td_status)); 749 750 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 751 "D=%d,maxlen=%d\n", sbuf, sbuf2, 752 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 753 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 754 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 755 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 756 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 757 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 758 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 759 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 760 BUS_DMASYNC_PREREAD); 761 } 762 763 void 764 uhci_dump_qh(uhci_soft_qh_t *sqh) 765 { 766 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 768 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 769 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 770 le32toh(sqh->qh.qh_elink))); 771 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 772 } 773 774 775 #if 1 776 void 777 uhci_dump(void) 778 { 779 uhci_dump_all(thesc); 780 } 781 #endif 782 783 void 784 uhci_dump_all(uhci_softc_t *sc) 785 { 786 uhci_dumpregs(sc); 787 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 788 uhci_dump_qhs(sc->sc_lctl_start); 789 } 790 791 792 void 793 uhci_dump_qhs(uhci_soft_qh_t *sqh) 794 { 795 uhci_dump_qh(sqh); 796 797 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 798 * Traverses sideways first, then down. 799 * 800 * QH1 801 * QH2 802 * No QH 803 * TD2.1 804 * TD2.2 805 * TD1.1 806 * etc. 807 * 808 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 809 */ 810 811 812 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 813 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 814 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 815 uhci_dump_qhs(sqh->hlink); 816 else 817 DPRINTF(("No QH\n")); 818 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 819 820 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 821 uhci_dump_tds(sqh->elink); 822 else 823 DPRINTF(("No TD\n")); 824 } 825 826 void 827 uhci_dump_tds(uhci_soft_td_t *std) 828 { 829 uhci_soft_td_t *td; 830 int stop; 831 832 for(td = std; td != NULL; td = td->link.std) { 833 uhci_dump_td(td); 834 835 /* Check whether the link pointer in this TD marks 836 * the link pointer as end of queue. This avoids 837 * printing the free list in case the queue/TD has 838 * already been moved there (seatbelt). 839 */ 840 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 841 sizeof(td->td.td_link), 842 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 843 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 844 le32toh(td->td.td_link) == 0); 845 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 846 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 847 if (stop) 848 break; 849 } 850 } 851 852 Static void 853 uhci_dump_ii(uhci_intr_info_t *ii) 854 { 855 usbd_pipe_handle pipe; 856 usb_endpoint_descriptor_t *ed; 857 usbd_device_handle dev; 858 859 #ifdef DIAGNOSTIC 860 #define DONE ii->isdone 861 #else 862 #define DONE 0 863 #endif 864 if (ii == NULL) { 865 printf("ii NULL\n"); 866 return; 867 } 868 if (ii->xfer == NULL) { 869 printf("ii %p: done=%d xfer=NULL\n", 870 ii, DONE); 871 return; 872 } 873 pipe = ii->xfer->ux_pipe; 874 if (pipe == NULL) { 875 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 876 ii, DONE, ii->xfer); 877 return; 878 } 879 if (pipe->up_endpoint == NULL) { 880 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 881 ii, DONE, ii->xfer, pipe); 882 return; 883 } 884 if (pipe->up_dev == NULL) { 885 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 886 ii, DONE, ii->xfer, pipe); 887 return; 888 } 889 ed = pipe->up_endpoint->ue_edesc; 890 dev = pipe->up_dev; 891 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 892 ii, DONE, ii->xfer, dev, 893 UGETW(dev->ud_ddesc.idVendor), 894 UGETW(dev->ud_ddesc.idProduct), 895 dev->ud_addr, pipe, 896 ed->bEndpointAddress, ed->bmAttributes); 897 #undef DONE 898 } 899 900 void uhci_dump_iis(struct uhci_softc *sc); 901 void 902 uhci_dump_iis(struct uhci_softc *sc) 903 { 904 uhci_intr_info_t *ii; 905 906 printf("intr_info list:\n"); 907 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 908 uhci_dump_ii(ii); 909 } 910 911 void iidump(void); 912 void iidump(void) { uhci_dump_iis(thesc); } 913 914 #endif 915 916 /* 917 * This routine is executed periodically and simulates interrupts 918 * from the root controller interrupt pipe for port status change. 919 */ 920 void 921 uhci_poll_hub(void *addr) 922 { 923 usbd_xfer_handle xfer = addr; 924 usbd_pipe_handle pipe = xfer->ux_pipe; 925 uhci_softc_t *sc; 926 u_char *p; 927 928 DPRINTFN(20, ("uhci_poll_hub\n")); 929 930 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 931 return; /* device has detached */ 932 sc = pipe->up_dev->ud_bus->ub_hcpriv; 933 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 934 935 p = xfer->ux_buf; 936 p[0] = 0; 937 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 938 p[0] |= 1<<1; 939 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 940 p[0] |= 1<<2; 941 if (p[0] == 0) 942 /* No change, try again in a while */ 943 return; 944 945 xfer->ux_actlen = 1; 946 xfer->ux_status = USBD_NORMAL_COMPLETION; 947 mutex_enter(&sc->sc_lock); 948 usb_transfer_complete(xfer); 949 mutex_exit(&sc->sc_lock); 950 } 951 952 void 953 uhci_root_intr_done(usbd_xfer_handle xfer) 954 { 955 } 956 957 /* 958 * Let the last QH loop back to the high speed control transfer QH. 959 * This is what intel calls "bandwidth reclamation" and improves 960 * USB performance a lot for some devices. 961 * If we are already looping, just count it. 962 */ 963 void 964 uhci_add_loop(uhci_softc_t *sc) 965 { 966 #ifdef UHCI_DEBUG 967 if (uhcinoloop) 968 return; 969 #endif 970 if (++sc->sc_loops == 1) { 971 DPRINTFN(5,("uhci_start_loop: add\n")); 972 /* Note, we don't loop back the soft pointer. */ 973 sc->sc_last_qh->qh.qh_hlink = 974 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 975 usb_syncmem(&sc->sc_last_qh->dma, 976 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 977 sizeof(sc->sc_last_qh->qh.qh_hlink), 978 BUS_DMASYNC_PREWRITE); 979 } 980 } 981 982 void 983 uhci_rem_loop(uhci_softc_t *sc) 984 { 985 #ifdef UHCI_DEBUG 986 if (uhcinoloop) 987 return; 988 #endif 989 if (--sc->sc_loops == 0) { 990 DPRINTFN(5,("uhci_end_loop: remove\n")); 991 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 992 usb_syncmem(&sc->sc_last_qh->dma, 993 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 994 sizeof(sc->sc_last_qh->qh.qh_hlink), 995 BUS_DMASYNC_PREWRITE); 996 } 997 } 998 999 /* Add high speed control QH, called with lock held. */ 1000 void 1001 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1002 { 1003 uhci_soft_qh_t *eqh; 1004 1005 KASSERT(mutex_owned(&sc->sc_lock)); 1006 1007 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1008 eqh = sc->sc_hctl_end; 1009 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1010 sizeof(eqh->qh.qh_hlink), 1011 BUS_DMASYNC_POSTWRITE); 1012 sqh->hlink = eqh->hlink; 1013 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1014 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1015 BUS_DMASYNC_PREWRITE); 1016 eqh->hlink = sqh; 1017 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1018 sc->sc_hctl_end = sqh; 1019 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1020 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1021 #ifdef UHCI_CTL_LOOP 1022 uhci_add_loop(sc); 1023 #endif 1024 } 1025 1026 /* Remove high speed control QH, called with lock held. */ 1027 void 1028 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1029 { 1030 uhci_soft_qh_t *pqh; 1031 uint32_t elink; 1032 1033 KASSERT(mutex_owned(&sc->sc_lock)); 1034 1035 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1036 #ifdef UHCI_CTL_LOOP 1037 uhci_rem_loop(sc); 1038 #endif 1039 /* 1040 * The T bit should be set in the elink of the QH so that the HC 1041 * doesn't follow the pointer. This condition may fail if the 1042 * the transferred packet was short so that the QH still points 1043 * at the last used TD. 1044 * In this case we set the T bit and wait a little for the HC 1045 * to stop looking at the TD. 1046 * Note that if the TD chain is large enough, the controller 1047 * may still be looking at the chain at the end of this function. 1048 * uhci_free_std_chain() will make sure the controller stops 1049 * looking at it quickly, but until then we should not change 1050 * sqh->hlink. 1051 */ 1052 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1053 sizeof(sqh->qh.qh_elink), 1054 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1055 elink = le32toh(sqh->qh.qh_elink); 1056 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1057 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1058 if (!(elink & UHCI_PTR_T)) { 1059 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1060 usb_syncmem(&sqh->dma, 1061 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1062 sizeof(sqh->qh.qh_elink), 1063 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1064 delay(UHCI_QH_REMOVE_DELAY); 1065 } 1066 1067 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1068 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1069 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1070 pqh->hlink = sqh->hlink; 1071 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1072 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1073 sizeof(pqh->qh.qh_hlink), 1074 BUS_DMASYNC_PREWRITE); 1075 delay(UHCI_QH_REMOVE_DELAY); 1076 if (sc->sc_hctl_end == sqh) 1077 sc->sc_hctl_end = pqh; 1078 } 1079 1080 /* Add low speed control QH, called with lock held. */ 1081 void 1082 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1083 { 1084 uhci_soft_qh_t *eqh; 1085 1086 KASSERT(mutex_owned(&sc->sc_lock)); 1087 1088 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1089 eqh = sc->sc_lctl_end; 1090 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1091 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1092 sqh->hlink = eqh->hlink; 1093 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1094 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1095 BUS_DMASYNC_PREWRITE); 1096 eqh->hlink = sqh; 1097 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1098 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1099 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1100 sc->sc_lctl_end = sqh; 1101 } 1102 1103 /* Remove low speed control QH, called with lock held. */ 1104 void 1105 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1106 { 1107 uhci_soft_qh_t *pqh; 1108 uint32_t elink; 1109 1110 KASSERT(mutex_owned(&sc->sc_lock)); 1111 1112 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1113 /* See comment in uhci_remove_hs_ctrl() */ 1114 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1115 sizeof(sqh->qh.qh_elink), 1116 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1117 elink = le32toh(sqh->qh.qh_elink); 1118 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1119 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1120 if (!(elink & UHCI_PTR_T)) { 1121 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1122 usb_syncmem(&sqh->dma, 1123 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1124 sizeof(sqh->qh.qh_elink), 1125 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1126 delay(UHCI_QH_REMOVE_DELAY); 1127 } 1128 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1129 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1130 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1131 pqh->hlink = sqh->hlink; 1132 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1133 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1134 sizeof(pqh->qh.qh_hlink), 1135 BUS_DMASYNC_PREWRITE); 1136 delay(UHCI_QH_REMOVE_DELAY); 1137 if (sc->sc_lctl_end == sqh) 1138 sc->sc_lctl_end = pqh; 1139 } 1140 1141 /* Add bulk QH, called with lock held. */ 1142 void 1143 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1144 { 1145 uhci_soft_qh_t *eqh; 1146 1147 KASSERT(mutex_owned(&sc->sc_lock)); 1148 1149 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1150 eqh = sc->sc_bulk_end; 1151 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1152 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1153 sqh->hlink = eqh->hlink; 1154 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1155 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1156 BUS_DMASYNC_PREWRITE); 1157 eqh->hlink = sqh; 1158 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1159 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1160 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1161 sc->sc_bulk_end = sqh; 1162 uhci_add_loop(sc); 1163 } 1164 1165 /* Remove bulk QH, called with lock held. */ 1166 void 1167 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1168 { 1169 uhci_soft_qh_t *pqh; 1170 1171 KASSERT(mutex_owned(&sc->sc_lock)); 1172 1173 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1174 uhci_rem_loop(sc); 1175 /* See comment in uhci_remove_hs_ctrl() */ 1176 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1177 sizeof(sqh->qh.qh_elink), 1178 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1179 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1180 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1181 usb_syncmem(&sqh->dma, 1182 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1183 sizeof(sqh->qh.qh_elink), 1184 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1185 delay(UHCI_QH_REMOVE_DELAY); 1186 } 1187 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1188 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1189 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1190 pqh->hlink = sqh->hlink; 1191 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1192 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1193 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1194 delay(UHCI_QH_REMOVE_DELAY); 1195 if (sc->sc_bulk_end == sqh) 1196 sc->sc_bulk_end = pqh; 1197 } 1198 1199 Static int uhci_intr1(uhci_softc_t *); 1200 1201 int 1202 uhci_intr(void *arg) 1203 { 1204 uhci_softc_t *sc = arg; 1205 int ret = 0; 1206 1207 mutex_spin_enter(&sc->sc_intr_lock); 1208 1209 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1210 goto done; 1211 1212 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1213 #ifdef DIAGNOSTIC 1214 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1215 #endif 1216 goto done; 1217 } 1218 1219 ret = uhci_intr1(sc); 1220 1221 done: 1222 mutex_spin_exit(&sc->sc_intr_lock); 1223 return ret; 1224 } 1225 1226 int 1227 uhci_intr1(uhci_softc_t *sc) 1228 { 1229 int status; 1230 int ack; 1231 1232 #ifdef UHCI_DEBUG 1233 if (uhcidebug > 15) { 1234 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1235 uhci_dumpregs(sc); 1236 } 1237 #endif 1238 1239 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1240 1241 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1242 if (status == 0) /* The interrupt was not for us. */ 1243 return 0; 1244 1245 if (sc->sc_suspend != PWR_RESUME) { 1246 #ifdef DIAGNOSTIC 1247 printf("%s: interrupt while not operating ignored\n", 1248 device_xname(sc->sc_dev)); 1249 #endif 1250 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1251 return 0; 1252 } 1253 1254 ack = 0; 1255 if (status & UHCI_STS_USBINT) 1256 ack |= UHCI_STS_USBINT; 1257 if (status & UHCI_STS_USBEI) 1258 ack |= UHCI_STS_USBEI; 1259 if (status & UHCI_STS_RD) { 1260 ack |= UHCI_STS_RD; 1261 #ifdef UHCI_DEBUG 1262 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1263 #endif 1264 } 1265 if (status & UHCI_STS_HSE) { 1266 ack |= UHCI_STS_HSE; 1267 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1268 } 1269 if (status & UHCI_STS_HCPE) { 1270 ack |= UHCI_STS_HCPE; 1271 printf("%s: host controller process error\n", 1272 device_xname(sc->sc_dev)); 1273 } 1274 1275 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1276 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1277 /* no acknowledge needed */ 1278 if (!sc->sc_dying) { 1279 printf("%s: host controller halted\n", 1280 device_xname(sc->sc_dev)); 1281 #ifdef UHCI_DEBUG 1282 uhci_dump_all(sc); 1283 #endif 1284 } 1285 sc->sc_dying = 1; 1286 } 1287 1288 if (!ack) 1289 return 0; /* nothing to acknowledge */ 1290 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1291 1292 usb_schedsoftintr(&sc->sc_bus); 1293 1294 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1295 1296 return 1; 1297 } 1298 1299 void 1300 uhci_softintr(void *v) 1301 { 1302 struct usbd_bus *bus = v; 1303 uhci_softc_t *sc = bus->ub_hcpriv; 1304 uhci_intr_info_t *ii, *nextii; 1305 1306 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1307 1308 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1309 1310 /* 1311 * Interrupts on UHCI really suck. When the host controller 1312 * interrupts because a transfer is completed there is no 1313 * way of knowing which transfer it was. You can scan down 1314 * the TDs and QHs of the previous frame to limit the search, 1315 * but that assumes that the interrupt was not delayed by more 1316 * than 1 ms, which may not always be true (e.g. after debug 1317 * output on a slow console). 1318 * We scan all interrupt descriptors to see if any have 1319 * completed. 1320 */ 1321 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1322 nextii = LIST_NEXT(ii, list); 1323 uhci_check_intr(sc, ii); 1324 } 1325 1326 if (sc->sc_softwake) { 1327 sc->sc_softwake = 0; 1328 cv_broadcast(&sc->sc_softwake_cv); 1329 } 1330 } 1331 1332 /* Check for an interrupt. */ 1333 void 1334 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1335 { 1336 uhci_soft_td_t *std, *lstd; 1337 uint32_t status; 1338 1339 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1340 #ifdef DIAGNOSTIC 1341 if (ii == NULL) { 1342 printf("uhci_check_intr: no ii? %p\n", ii); 1343 return; 1344 } 1345 #endif 1346 if (ii->xfer->ux_status == USBD_CANCELLED || 1347 ii->xfer->ux_status == USBD_TIMEOUT) { 1348 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1349 return; 1350 } 1351 1352 if (ii->stdstart == NULL) 1353 return; 1354 lstd = ii->stdend; 1355 #ifdef DIAGNOSTIC 1356 if (lstd == NULL) { 1357 printf("uhci_check_intr: std==0\n"); 1358 return; 1359 } 1360 #endif 1361 usb_syncmem(&lstd->dma, 1362 lstd->offs + offsetof(uhci_td_t, td_status), 1363 sizeof(lstd->td.td_status), 1364 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1365 status = le32toh(lstd->td.td_status); 1366 usb_syncmem(&lstd->dma, 1367 lstd->offs + offsetof(uhci_td_t, td_status), 1368 sizeof(lstd->td.td_status), 1369 BUS_DMASYNC_PREREAD); 1370 1371 /* If the last TD is not marked active we can complete */ 1372 if (!(status & UHCI_TD_ACTIVE)) { 1373 done: 1374 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1375 callout_stop(&ii->xfer->ux_callout); 1376 uhci_idone(ii); 1377 return; 1378 } 1379 1380 /* 1381 * If the last TD is still active we need to check whether there 1382 * is an error somewhere in the middle, or whether there was a 1383 * short packet (SPD and not ACTIVE). 1384 */ 1385 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1386 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1387 usb_syncmem(&std->dma, 1388 std->offs + offsetof(uhci_td_t, td_status), 1389 sizeof(std->td.td_status), 1390 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1391 status = le32toh(std->td.td_status); 1392 usb_syncmem(&std->dma, 1393 std->offs + offsetof(uhci_td_t, td_status), 1394 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1395 1396 /* If there's an active TD the xfer isn't done. */ 1397 if (status & UHCI_TD_ACTIVE) { 1398 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1399 __func__, ii, std)); 1400 return; 1401 } 1402 1403 /* Any kind of error makes the xfer done. */ 1404 if (status & UHCI_TD_STALLED) 1405 goto done; 1406 1407 /* 1408 * If the data phase of a control transfer is short, we need 1409 * to complete the status stage 1410 */ 1411 usbd_xfer_handle xfer = ii->xfer; 1412 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1413 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1414 1415 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1416 struct uhci_pipe *upipe = 1417 (struct uhci_pipe *)xfer->ux_pipe; 1418 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1419 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1420 1421 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1422 "phase needs completion\n", __func__, ii, 1423 ii->stdstart)); 1424 1425 sqh->qh.qh_elink = 1426 htole32(stat->physaddr | UHCI_PTR_TD); 1427 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1428 BUS_DMASYNC_PREWRITE); 1429 break; 1430 } 1431 1432 /* We want short packets, and it is short: it's done */ 1433 usb_syncmem(&std->dma, 1434 std->offs + offsetof(uhci_td_t, td_token), 1435 sizeof(std->td.td_token), 1436 BUS_DMASYNC_POSTWRITE); 1437 1438 if ((status & UHCI_TD_SPD) && 1439 UHCI_TD_GET_ACTLEN(status) < 1440 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1441 goto done; 1442 } 1443 } 1444 } 1445 1446 /* Called with USB lock held. */ 1447 void 1448 uhci_idone(uhci_intr_info_t *ii) 1449 { 1450 usbd_xfer_handle xfer = ii->xfer; 1451 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1452 #ifdef DIAGNOSTIC 1453 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1454 #endif 1455 uhci_soft_td_t *std; 1456 uint32_t status = 0, nstatus; 1457 int actlen; 1458 1459 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1460 1461 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1462 #ifdef DIAGNOSTIC 1463 { 1464 /* XXX SMP? */ 1465 int s = splhigh(); 1466 if (ii->isdone) { 1467 splx(s); 1468 #ifdef UHCI_DEBUG 1469 printf("uhci_idone: ii is done!\n "); 1470 uhci_dump_ii(ii); 1471 #else 1472 printf("uhci_idone: ii=%p is done!\n", ii); 1473 #endif 1474 return; 1475 } 1476 ii->isdone = 1; 1477 splx(s); 1478 } 1479 #endif 1480 1481 if (xfer->ux_nframes != 0) { 1482 /* Isoc transfer, do things differently. */ 1483 uhci_soft_td_t **stds = upipe->u.iso.stds; 1484 int i, n, nframes, len; 1485 1486 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1487 1488 nframes = xfer->ux_nframes; 1489 actlen = 0; 1490 n = UXFER(xfer)->curframe; 1491 for (i = 0; i < nframes; i++) { 1492 std = stds[n]; 1493 #ifdef UHCI_DEBUG 1494 if (uhcidebug > 5) { 1495 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1496 uhci_dump_td(std); 1497 } 1498 #endif 1499 if (++n >= UHCI_VFRAMELIST_COUNT) 1500 n = 0; 1501 usb_syncmem(&std->dma, 1502 std->offs + offsetof(uhci_td_t, td_status), 1503 sizeof(std->td.td_status), 1504 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1505 status = le32toh(std->td.td_status); 1506 len = UHCI_TD_GET_ACTLEN(status); 1507 xfer->ux_frlengths[i] = len; 1508 actlen += len; 1509 } 1510 upipe->u.iso.inuse -= nframes; 1511 xfer->ux_actlen = actlen; 1512 xfer->ux_status = USBD_NORMAL_COMPLETION; 1513 goto end; 1514 } 1515 1516 #ifdef UHCI_DEBUG 1517 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1518 ii, xfer, upipe)); 1519 if (uhcidebug > 10) 1520 uhci_dump_tds(ii->stdstart); 1521 #endif 1522 1523 /* The transfer is done, compute actual length and status. */ 1524 actlen = 0; 1525 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1526 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1527 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1528 nstatus = le32toh(std->td.td_status); 1529 if (nstatus & UHCI_TD_ACTIVE) 1530 break; 1531 1532 status = nstatus; 1533 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1534 UHCI_TD_PID_SETUP) 1535 actlen += UHCI_TD_GET_ACTLEN(status); 1536 else { 1537 /* 1538 * UHCI will report CRCTO in addition to a STALL or NAK 1539 * for a SETUP transaction. See section 3.2.2, "TD 1540 * CONTROL AND STATUS". 1541 */ 1542 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1543 status &= ~UHCI_TD_CRCTO; 1544 } 1545 } 1546 /* If there are left over TDs we need to update the toggle. */ 1547 if (std != NULL) 1548 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1549 1550 status &= UHCI_TD_ERROR; 1551 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1552 actlen, status)); 1553 xfer->ux_actlen = actlen; 1554 if (status != 0) { 1555 #ifdef UHCI_DEBUG 1556 char sbuf[128]; 1557 1558 snprintb(sbuf, sizeof(sbuf), 1559 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1560 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status); 1561 1562 DPRINTFN((status == UHCI_TD_STALLED)*10, 1563 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1564 "status 0x%s\n", 1565 xfer->ux_pipe->up_dev->ud_addr, 1566 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1567 sbuf)); 1568 #endif 1569 1570 if (status == UHCI_TD_STALLED) 1571 xfer->ux_status = USBD_STALLED; 1572 else 1573 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1574 } else { 1575 xfer->ux_status = USBD_NORMAL_COMPLETION; 1576 } 1577 1578 end: 1579 usb_transfer_complete(xfer); 1580 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1581 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1582 } 1583 1584 /* 1585 * Called when a request does not complete. 1586 */ 1587 void 1588 uhci_timeout(void *addr) 1589 { 1590 uhci_intr_info_t *ii = addr; 1591 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1592 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe; 1593 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1594 1595 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1596 1597 if (sc->sc_dying) { 1598 mutex_enter(&sc->sc_lock); 1599 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1600 mutex_exit(&sc->sc_lock); 1601 return; 1602 } 1603 1604 /* Execute the abort in a process context. */ 1605 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1606 USB_TASKQ_MPSAFE); 1607 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1608 USB_TASKQ_HC); 1609 } 1610 1611 void 1612 uhci_timeout_task(void *addr) 1613 { 1614 usbd_xfer_handle xfer = addr; 1615 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1616 1617 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1618 1619 mutex_enter(&sc->sc_lock); 1620 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1621 mutex_exit(&sc->sc_lock); 1622 } 1623 1624 /* 1625 * Wait here until controller claims to have an interrupt. 1626 * Then call uhci_intr and return. Use timeout to avoid waiting 1627 * too long. 1628 * Only used during boot when interrupts are not enabled yet. 1629 */ 1630 void 1631 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1632 { 1633 int timo = xfer->ux_timeout; 1634 uhci_intr_info_t *ii; 1635 1636 mutex_enter(&sc->sc_lock); 1637 1638 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1639 1640 xfer->ux_status = USBD_IN_PROGRESS; 1641 for (; timo >= 0; timo--) { 1642 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1643 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1644 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1645 mutex_spin_enter(&sc->sc_intr_lock); 1646 uhci_intr1(sc); 1647 mutex_spin_exit(&sc->sc_intr_lock); 1648 if (xfer->ux_status != USBD_IN_PROGRESS) 1649 goto done; 1650 } 1651 } 1652 1653 /* Timeout */ 1654 DPRINTF(("uhci_waitintr: timeout\n")); 1655 for (ii = LIST_FIRST(&sc->sc_intrhead); 1656 ii != NULL && ii->xfer != xfer; 1657 ii = LIST_NEXT(ii, list)) 1658 ; 1659 #ifdef DIAGNOSTIC 1660 if (ii == NULL) 1661 panic("uhci_waitintr: lost intr_info"); 1662 #endif 1663 uhci_idone(ii); 1664 1665 done: 1666 mutex_exit(&sc->sc_lock); 1667 } 1668 1669 void 1670 uhci_poll(struct usbd_bus *bus) 1671 { 1672 uhci_softc_t *sc = bus->ub_hcpriv; 1673 1674 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1675 mutex_spin_enter(&sc->sc_intr_lock); 1676 uhci_intr1(sc); 1677 mutex_spin_exit(&sc->sc_intr_lock); 1678 } 1679 } 1680 1681 void 1682 uhci_reset(uhci_softc_t *sc) 1683 { 1684 int n; 1685 1686 UHCICMD(sc, UHCI_CMD_HCRESET); 1687 /* The reset bit goes low when the controller is done. */ 1688 for (n = 0; n < UHCI_RESET_TIMEOUT && 1689 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1690 usb_delay_ms(&sc->sc_bus, 1); 1691 if (n >= UHCI_RESET_TIMEOUT) 1692 printf("%s: controller did not reset\n", 1693 device_xname(sc->sc_dev)); 1694 } 1695 1696 usbd_status 1697 uhci_run(uhci_softc_t *sc, int run, int locked) 1698 { 1699 int n, running; 1700 uint16_t cmd; 1701 1702 run = run != 0; 1703 if (!locked) 1704 mutex_spin_enter(&sc->sc_intr_lock); 1705 DPRINTF(("uhci_run: setting run=%d\n", run)); 1706 cmd = UREAD2(sc, UHCI_CMD); 1707 if (run) 1708 cmd |= UHCI_CMD_RS; 1709 else 1710 cmd &= ~UHCI_CMD_RS; 1711 UHCICMD(sc, cmd); 1712 for(n = 0; n < 10; n++) { 1713 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1714 /* return when we've entered the state we want */ 1715 if (run == running) { 1716 if (!locked) 1717 mutex_spin_exit(&sc->sc_intr_lock); 1718 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1719 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1720 return USBD_NORMAL_COMPLETION; 1721 } 1722 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1723 } 1724 if (!locked) 1725 mutex_spin_exit(&sc->sc_intr_lock); 1726 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1727 run ? "start" : "stop"); 1728 return USBD_IOERROR; 1729 } 1730 1731 /* 1732 * Memory management routines. 1733 * uhci_alloc_std allocates TDs 1734 * uhci_alloc_sqh allocates QHs 1735 * These two routines do their own free list management, 1736 * partly for speed, partly because allocating DMAable memory 1737 * has page size granularaity so much memory would be wasted if 1738 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1739 */ 1740 1741 uhci_soft_td_t * 1742 uhci_alloc_std(uhci_softc_t *sc) 1743 { 1744 uhci_soft_td_t *std; 1745 usbd_status err; 1746 int i, offs; 1747 usb_dma_t dma; 1748 1749 if (sc->sc_freetds == NULL) { 1750 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1751 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1752 UHCI_TD_ALIGN, &dma); 1753 if (err) 1754 return 0; 1755 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1756 offs = i * UHCI_STD_SIZE; 1757 std = KERNADDR(&dma, offs); 1758 std->physaddr = DMAADDR(&dma, offs); 1759 std->dma = dma; 1760 std->offs = offs; 1761 std->link.std = sc->sc_freetds; 1762 sc->sc_freetds = std; 1763 } 1764 } 1765 std = sc->sc_freetds; 1766 sc->sc_freetds = std->link.std; 1767 memset(&std->td, 0, sizeof(uhci_td_t)); 1768 return std; 1769 } 1770 1771 void 1772 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1773 { 1774 #ifdef DIAGNOSTIC 1775 #define TD_IS_FREE 0x12345678 1776 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1777 printf("uhci_free_std: freeing free TD %p\n", std); 1778 return; 1779 } 1780 std->td.td_token = htole32(TD_IS_FREE); 1781 #endif 1782 std->link.std = sc->sc_freetds; 1783 sc->sc_freetds = std; 1784 } 1785 1786 uhci_soft_qh_t * 1787 uhci_alloc_sqh(uhci_softc_t *sc) 1788 { 1789 uhci_soft_qh_t *sqh; 1790 usbd_status err; 1791 int i, offs; 1792 usb_dma_t dma; 1793 1794 if (sc->sc_freeqhs == NULL) { 1795 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1796 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1797 UHCI_QH_ALIGN, &dma); 1798 if (err) 1799 return 0; 1800 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1801 offs = i * UHCI_SQH_SIZE; 1802 sqh = KERNADDR(&dma, offs); 1803 sqh->physaddr = DMAADDR(&dma, offs); 1804 sqh->dma = dma; 1805 sqh->offs = offs; 1806 sqh->hlink = sc->sc_freeqhs; 1807 sc->sc_freeqhs = sqh; 1808 } 1809 } 1810 sqh = sc->sc_freeqhs; 1811 sc->sc_freeqhs = sqh->hlink; 1812 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1813 return sqh; 1814 } 1815 1816 void 1817 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1818 { 1819 sqh->hlink = sc->sc_freeqhs; 1820 sc->sc_freeqhs = sqh; 1821 } 1822 1823 void 1824 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1825 uhci_soft_td_t *stdend) 1826 { 1827 uhci_soft_td_t *p; 1828 uint32_t td_link; 1829 1830 /* 1831 * to avoid race condition with the controller which may be looking 1832 * at this chain, we need to first invalidate all links, and 1833 * then wait for the controller to move to another queue 1834 */ 1835 for (p = std; p != stdend; p = p->link.std) { 1836 usb_syncmem(&p->dma, 1837 p->offs + offsetof(uhci_td_t, td_link), 1838 sizeof(p->td.td_link), 1839 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1840 td_link = le32toh(p->td.td_link); 1841 usb_syncmem(&p->dma, 1842 p->offs + offsetof(uhci_td_t, td_link), 1843 sizeof(p->td.td_link), 1844 BUS_DMASYNC_PREREAD); 1845 if ((td_link & UHCI_PTR_T) == 0) { 1846 p->td.td_link = htole32(UHCI_PTR_T); 1847 usb_syncmem(&p->dma, 1848 p->offs + offsetof(uhci_td_t, td_link), 1849 sizeof(p->td.td_link), 1850 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1851 } 1852 } 1853 delay(UHCI_QH_REMOVE_DELAY); 1854 1855 for (; std != stdend; std = p) { 1856 p = std->link.std; 1857 uhci_free_std(sc, std); 1858 } 1859 } 1860 1861 usbd_status 1862 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1863 int rd, uint16_t flags, usb_dma_t *dma, 1864 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1865 { 1866 uhci_soft_td_t *p, *lastp; 1867 uhci_physaddr_t lastlink; 1868 int i, ntd, l, tog, maxp; 1869 uint32_t status; 1870 int addr = upipe->pipe.up_dev->ud_addr; 1871 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1872 1873 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1874 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1875 upipe->pipe.up_dev->ud_speed, flags)); 1876 1877 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1878 1879 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1880 if (maxp == 0) { 1881 printf("uhci_alloc_std_chain: maxp=0\n"); 1882 return USBD_INVAL; 1883 } 1884 ntd = (len + maxp - 1) / maxp; 1885 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1886 ntd++; 1887 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1888 if (ntd == 0) { 1889 *sp = *ep = 0; 1890 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1891 return USBD_NORMAL_COMPLETION; 1892 } 1893 tog = upipe->nexttoggle; 1894 if (ntd % 2 == 0) 1895 tog ^= 1; 1896 upipe->nexttoggle = tog ^ 1; 1897 lastp = NULL; 1898 lastlink = UHCI_PTR_T; 1899 ntd--; 1900 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1901 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1902 status |= UHCI_TD_LS; 1903 if (flags & USBD_SHORT_XFER_OK) 1904 status |= UHCI_TD_SPD; 1905 usb_syncmem(dma, 0, len, 1906 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1907 for (i = ntd; i >= 0; i--) { 1908 p = uhci_alloc_std(sc); 1909 if (p == NULL) { 1910 KASSERT(lastp != NULL); 1911 uhci_free_std_chain(sc, lastp, NULL); 1912 return USBD_NOMEM; 1913 } 1914 p->link.std = lastp; 1915 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1916 lastp = p; 1917 lastlink = p->physaddr; 1918 p->td.td_status = htole32(status); 1919 if (i == ntd) { 1920 /* last TD */ 1921 l = len % maxp; 1922 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1923 l = maxp; 1924 *ep = p; 1925 } else 1926 l = maxp; 1927 p->td.td_token = 1928 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1929 UHCI_TD_OUT(l, endpt, addr, tog)); 1930 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1931 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1932 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1933 tog ^= 1; 1934 } 1935 *sp = lastp; 1936 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1937 upipe->nexttoggle)); 1938 return USBD_NORMAL_COMPLETION; 1939 } 1940 1941 void 1942 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1943 { 1944 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1945 upipe->nexttoggle = 0; 1946 } 1947 1948 void 1949 uhci_noop(usbd_pipe_handle pipe) 1950 { 1951 } 1952 1953 usbd_status 1954 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1955 { 1956 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1957 usbd_status err; 1958 1959 /* Insert last in queue. */ 1960 mutex_enter(&sc->sc_lock); 1961 err = usb_insert_transfer(xfer); 1962 mutex_exit(&sc->sc_lock); 1963 if (err) 1964 return err; 1965 1966 /* 1967 * Pipe isn't running (otherwise err would be USBD_INPROG), 1968 * so start it first. 1969 */ 1970 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1971 } 1972 1973 usbd_status 1974 uhci_device_bulk_start(usbd_xfer_handle xfer) 1975 { 1976 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1977 usbd_device_handle dev = upipe->pipe.up_dev; 1978 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1979 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1980 uhci_soft_td_t *data, *dataend; 1981 uhci_soft_qh_t *sqh; 1982 usbd_status err; 1983 int len, isread, endpt; 1984 1985 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1986 xfer, xfer->ux_length, xfer->ux_flags, ii)); 1987 1988 if (sc->sc_dying) 1989 return USBD_IOERROR; 1990 1991 #ifdef DIAGNOSTIC 1992 if (xfer->ux_rqflags & URQ_REQUEST) 1993 panic("uhci_device_bulk_transfer: a request"); 1994 #endif 1995 1996 mutex_enter(&sc->sc_lock); 1997 1998 len = xfer->ux_length; 1999 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2000 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2001 sqh = upipe->u.bulk.sqh; 2002 2003 upipe->u.bulk.isread = isread; 2004 upipe->u.bulk.length = len; 2005 2006 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2007 &xfer->ux_dmabuf, &data, &dataend); 2008 if (err) { 2009 mutex_exit(&sc->sc_lock); 2010 return err; 2011 } 2012 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2013 usb_syncmem(&dataend->dma, 2014 dataend->offs + offsetof(uhci_td_t, td_status), 2015 sizeof(dataend->td.td_status), 2016 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2017 2018 2019 #ifdef UHCI_DEBUG 2020 if (uhcidebug > 8) { 2021 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2022 uhci_dump_tds(data); 2023 } 2024 #endif 2025 2026 /* Set up interrupt info. */ 2027 ii->xfer = xfer; 2028 ii->stdstart = data; 2029 ii->stdend = dataend; 2030 #ifdef DIAGNOSTIC 2031 if (!ii->isdone) { 2032 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2033 } 2034 ii->isdone = 0; 2035 #endif 2036 2037 sqh->elink = data; 2038 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2039 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2040 2041 uhci_add_bulk(sc, sqh); 2042 uhci_add_intr_info(sc, ii); 2043 2044 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2045 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2046 uhci_timeout, ii); 2047 } 2048 xfer->ux_status = USBD_IN_PROGRESS; 2049 2050 #ifdef UHCI_DEBUG 2051 if (uhcidebug > 10) { 2052 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2053 uhci_dump_tds(data); 2054 } 2055 #endif 2056 2057 if (sc->sc_bus.ub_usepolling) 2058 uhci_waitintr(sc, xfer); 2059 2060 mutex_exit(&sc->sc_lock); 2061 return USBD_IN_PROGRESS; 2062 } 2063 2064 /* Abort a device bulk request. */ 2065 void 2066 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2067 { 2068 #ifdef DIAGNOSTIC 2069 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2070 #endif 2071 2072 KASSERT(mutex_owned(&sc->sc_lock)); 2073 2074 DPRINTF(("uhci_device_bulk_abort:\n")); 2075 uhci_abort_xfer(xfer, USBD_CANCELLED); 2076 } 2077 2078 /* 2079 * Abort a device request. 2080 * If this routine is called at splusb() it guarantees that the request 2081 * will be removed from the hardware scheduling and that the callback 2082 * for it will be called with USBD_CANCELLED status. 2083 * It's impossible to guarantee that the requested transfer will not 2084 * have happened since the hardware runs concurrently. 2085 * If the transaction has already happened we rely on the ordinary 2086 * interrupt processing to process it. 2087 * XXX This is most probably wrong. 2088 * XXXMRG this doesn't make sense anymore. 2089 */ 2090 void 2091 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2092 { 2093 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2094 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2095 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2096 uhci_soft_td_t *std; 2097 int wake; 2098 2099 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2100 2101 KASSERT(mutex_owned(&sc->sc_lock)); 2102 ASSERT_SLEEPABLE(); 2103 2104 if (sc->sc_dying) { 2105 /* If we're dying, just do the software part. */ 2106 xfer->ux_status = status; /* make software ignore it */ 2107 callout_stop(&xfer->ux_callout); 2108 usb_transfer_complete(xfer); 2109 return; 2110 } 2111 2112 /* 2113 * If an abort is already in progress then just wait for it to 2114 * complete and return. 2115 */ 2116 if (xfer->ux_hcflags & UXFER_ABORTING) { 2117 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2118 #ifdef DIAGNOSTIC 2119 if (status == USBD_TIMEOUT) 2120 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2121 #endif 2122 /* Override the status which might be USBD_TIMEOUT. */ 2123 xfer->ux_status = status; 2124 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2125 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2126 while (xfer->ux_hcflags & UXFER_ABORTING) 2127 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2128 goto done; 2129 } 2130 xfer->ux_hcflags |= UXFER_ABORTING; 2131 2132 /* 2133 * Step 1: Make interrupt routine and hardware ignore xfer. 2134 */ 2135 xfer->ux_status = status; /* make software ignore it */ 2136 callout_stop(&xfer->ux_callout); 2137 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2138 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2139 usb_syncmem(&std->dma, 2140 std->offs + offsetof(uhci_td_t, td_status), 2141 sizeof(std->td.td_status), 2142 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2143 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2144 usb_syncmem(&std->dma, 2145 std->offs + offsetof(uhci_td_t, td_status), 2146 sizeof(std->td.td_status), 2147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2148 } 2149 2150 /* 2151 * Step 2: Wait until we know hardware has finished any possible 2152 * use of the xfer. Also make sure the soft interrupt routine 2153 * has run. 2154 */ 2155 /* Hardware finishes in 1ms */ 2156 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2157 sc->sc_softwake = 1; 2158 usb_schedsoftintr(&sc->sc_bus); 2159 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2160 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2161 2162 /* 2163 * Step 3: Execute callback. 2164 */ 2165 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2166 #ifdef DIAGNOSTIC 2167 ii->isdone = 1; 2168 #endif 2169 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2170 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2171 usb_transfer_complete(xfer); 2172 if (wake) 2173 cv_broadcast(&xfer->ux_hccv); 2174 done: 2175 KASSERT(mutex_owned(&sc->sc_lock)); 2176 } 2177 2178 /* Close a device bulk pipe. */ 2179 void 2180 uhci_device_bulk_close(usbd_pipe_handle pipe) 2181 { 2182 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2183 usbd_device_handle dev = upipe->pipe.up_dev; 2184 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2185 2186 KASSERT(mutex_owned(&sc->sc_lock)); 2187 2188 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2189 2190 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2191 } 2192 2193 usbd_status 2194 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2195 { 2196 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2197 usbd_status err; 2198 2199 /* Insert last in queue. */ 2200 mutex_enter(&sc->sc_lock); 2201 err = usb_insert_transfer(xfer); 2202 mutex_exit(&sc->sc_lock); 2203 if (err) 2204 return err; 2205 2206 /* 2207 * Pipe isn't running (otherwise err would be USBD_INPROG), 2208 * so start it first. 2209 */ 2210 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2211 } 2212 2213 usbd_status 2214 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2215 { 2216 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2217 usbd_status err; 2218 2219 if (sc->sc_dying) 2220 return USBD_IOERROR; 2221 2222 #ifdef DIAGNOSTIC 2223 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2224 panic("uhci_device_ctrl_transfer: not a request"); 2225 #endif 2226 2227 mutex_enter(&sc->sc_lock); 2228 err = uhci_device_request(xfer); 2229 mutex_exit(&sc->sc_lock); 2230 if (err) 2231 return err; 2232 2233 if (sc->sc_bus.ub_usepolling) 2234 uhci_waitintr(sc, xfer); 2235 return USBD_IN_PROGRESS; 2236 } 2237 2238 usbd_status 2239 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2240 { 2241 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2242 usbd_status err; 2243 2244 /* Insert last in queue. */ 2245 mutex_enter(&sc->sc_lock); 2246 err = usb_insert_transfer(xfer); 2247 mutex_exit(&sc->sc_lock); 2248 if (err) 2249 return err; 2250 2251 /* 2252 * Pipe isn't running (otherwise err would be USBD_INPROG), 2253 * so start it first. 2254 */ 2255 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2256 } 2257 2258 usbd_status 2259 uhci_device_intr_start(usbd_xfer_handle xfer) 2260 { 2261 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2262 usbd_device_handle dev = upipe->pipe.up_dev; 2263 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2264 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2265 uhci_soft_td_t *data, *dataend; 2266 uhci_soft_qh_t *sqh; 2267 usbd_status err; 2268 int isread, endpt; 2269 int i; 2270 2271 if (sc->sc_dying) 2272 return USBD_IOERROR; 2273 2274 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2275 xfer, xfer->ux_length, xfer->ux_flags)); 2276 2277 #ifdef DIAGNOSTIC 2278 if (xfer->ux_rqflags & URQ_REQUEST) 2279 panic("uhci_device_intr_transfer: a request"); 2280 #endif 2281 2282 mutex_enter(&sc->sc_lock); 2283 2284 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2285 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2286 2287 upipe->u.intr.isread = isread; 2288 2289 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2290 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2291 &dataend); 2292 if (err) { 2293 mutex_exit(&sc->sc_lock); 2294 return err; 2295 } 2296 2297 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2298 usb_syncmem(&dataend->dma, 2299 dataend->offs + offsetof(uhci_td_t, td_status), 2300 sizeof(dataend->td.td_status), 2301 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2302 2303 #ifdef UHCI_DEBUG 2304 if (uhcidebug > 10) { 2305 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2306 uhci_dump_tds(data); 2307 uhci_dump_qh(upipe->u.intr.qhs[0]); 2308 } 2309 #endif 2310 2311 /* Set up interrupt info. */ 2312 ii->xfer = xfer; 2313 ii->stdstart = data; 2314 ii->stdend = dataend; 2315 #ifdef DIAGNOSTIC 2316 if (!ii->isdone) { 2317 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2318 } 2319 ii->isdone = 0; 2320 #endif 2321 2322 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2323 upipe->u.intr.qhs[0])); 2324 for (i = 0; i < upipe->u.intr.npoll; i++) { 2325 sqh = upipe->u.intr.qhs[i]; 2326 sqh->elink = data; 2327 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2328 usb_syncmem(&sqh->dma, 2329 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2330 sizeof(sqh->qh.qh_elink), 2331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2332 } 2333 uhci_add_intr_info(sc, ii); 2334 xfer->ux_status = USBD_IN_PROGRESS; 2335 mutex_exit(&sc->sc_lock); 2336 2337 #ifdef UHCI_DEBUG 2338 if (uhcidebug > 10) { 2339 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2340 uhci_dump_tds(data); 2341 uhci_dump_qh(upipe->u.intr.qhs[0]); 2342 } 2343 #endif 2344 2345 return USBD_IN_PROGRESS; 2346 } 2347 2348 /* Abort a device control request. */ 2349 void 2350 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2351 { 2352 #ifdef DIAGNOSTIC 2353 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2354 #endif 2355 2356 KASSERT(mutex_owned(&sc->sc_lock)); 2357 2358 DPRINTF(("uhci_device_ctrl_abort:\n")); 2359 uhci_abort_xfer(xfer, USBD_CANCELLED); 2360 } 2361 2362 /* Close a device control pipe. */ 2363 void 2364 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2365 { 2366 } 2367 2368 /* Abort a device interrupt request. */ 2369 void 2370 uhci_device_intr_abort(usbd_xfer_handle xfer) 2371 { 2372 #ifdef DIAGNOSTIC 2373 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2374 #endif 2375 2376 KASSERT(mutex_owned(&sc->sc_lock)); 2377 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2378 2379 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2380 2381 uhci_abort_xfer(xfer, USBD_CANCELLED); 2382 } 2383 2384 /* Close a device interrupt pipe. */ 2385 void 2386 uhci_device_intr_close(usbd_pipe_handle pipe) 2387 { 2388 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2389 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2390 int i, npoll; 2391 2392 KASSERT(mutex_owned(&sc->sc_lock)); 2393 2394 /* Unlink descriptors from controller data structures. */ 2395 npoll = upipe->u.intr.npoll; 2396 for (i = 0; i < npoll; i++) 2397 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2398 2399 /* 2400 * We now have to wait for any activity on the physical 2401 * descriptors to stop. 2402 */ 2403 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2404 2405 for(i = 0; i < npoll; i++) 2406 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2407 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2408 2409 /* XXX free other resources */ 2410 } 2411 2412 usbd_status 2413 uhci_device_request(usbd_xfer_handle xfer) 2414 { 2415 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2416 usb_device_request_t *req = &xfer->ux_request; 2417 usbd_device_handle dev = upipe->pipe.up_dev; 2418 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2419 int addr = dev->ud_addr; 2420 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2421 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2422 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2423 uhci_soft_qh_t *sqh; 2424 int len; 2425 uint32_t ls; 2426 usbd_status err; 2427 int isread; 2428 2429 KASSERT(mutex_owned(&sc->sc_lock)); 2430 2431 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2432 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2433 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2434 UGETW(req->wIndex), UGETW(req->wLength), 2435 addr, endpt)); 2436 2437 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2438 isread = req->bmRequestType & UT_READ; 2439 len = UGETW(req->wLength); 2440 2441 setup = upipe->u.ctl.setup; 2442 stat = upipe->u.ctl.stat; 2443 sqh = upipe->u.ctl.sqh; 2444 2445 /* Set up data transaction */ 2446 if (len != 0) { 2447 upipe->nexttoggle = 1; 2448 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2449 &xfer->ux_dmabuf, &data, &dataend); 2450 if (err) 2451 return err; 2452 next = data; 2453 dataend->link.std = stat; 2454 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2455 usb_syncmem(&dataend->dma, 2456 dataend->offs + offsetof(uhci_td_t, td_link), 2457 sizeof(dataend->td.td_link), 2458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2459 } else { 2460 next = stat; 2461 } 2462 upipe->u.ctl.length = len; 2463 2464 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2465 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2466 2467 setup->link.std = next; 2468 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2469 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2470 UHCI_TD_ACTIVE); 2471 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2472 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2473 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2475 2476 stat->link.std = NULL; 2477 stat->td.td_link = htole32(UHCI_PTR_T); 2478 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2479 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2480 stat->td.td_token = 2481 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2482 UHCI_TD_IN (0, endpt, addr, 1)); 2483 stat->td.td_buffer = htole32(0); 2484 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2486 2487 #ifdef UHCI_DEBUG 2488 if (uhcidebug > 10) { 2489 DPRINTF(("uhci_device_request: before transfer\n")); 2490 uhci_dump_tds(setup); 2491 } 2492 #endif 2493 2494 /* Set up interrupt info. */ 2495 ii->xfer = xfer; 2496 ii->stdstart = setup; 2497 ii->stdend = stat; 2498 #ifdef DIAGNOSTIC 2499 if (!ii->isdone) { 2500 printf("uhci_device_request: not done, ii=%p\n", ii); 2501 } 2502 ii->isdone = 0; 2503 #endif 2504 2505 sqh->elink = setup; 2506 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2507 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2508 2509 if (dev->ud_speed == USB_SPEED_LOW) 2510 uhci_add_ls_ctrl(sc, sqh); 2511 else 2512 uhci_add_hs_ctrl(sc, sqh); 2513 uhci_add_intr_info(sc, ii); 2514 #ifdef UHCI_DEBUG 2515 if (uhcidebug > 12) { 2516 uhci_soft_td_t *std; 2517 uhci_soft_qh_t *xqh; 2518 uhci_soft_qh_t *sxqh; 2519 int maxqh = 0; 2520 uhci_physaddr_t link; 2521 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2522 for (std = sc->sc_vframes[0].htd, link = 0; 2523 (link & UHCI_PTR_QH) == 0; 2524 std = std->link.std) { 2525 link = le32toh(std->td.td_link); 2526 uhci_dump_td(std); 2527 } 2528 sxqh = (uhci_soft_qh_t *)std; 2529 uhci_dump_qh(sxqh); 2530 for (xqh = sxqh; 2531 xqh != NULL; 2532 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2533 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2534 uhci_dump_qh(xqh); 2535 } 2536 DPRINTF(("Enqueued QH:\n")); 2537 uhci_dump_qh(sqh); 2538 uhci_dump_tds(sqh->elink); 2539 } 2540 #endif 2541 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2542 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2543 uhci_timeout, ii); 2544 } 2545 xfer->ux_status = USBD_IN_PROGRESS; 2546 2547 return USBD_NORMAL_COMPLETION; 2548 } 2549 2550 usbd_status 2551 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2552 { 2553 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2554 usbd_status err; 2555 2556 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2557 2558 /* Put it on our queue, */ 2559 mutex_enter(&sc->sc_lock); 2560 err = usb_insert_transfer(xfer); 2561 mutex_exit(&sc->sc_lock); 2562 2563 /* bail out on error, */ 2564 if (err && err != USBD_IN_PROGRESS) 2565 return err; 2566 2567 /* XXX should check inuse here */ 2568 2569 /* insert into schedule, */ 2570 uhci_device_isoc_enter(xfer); 2571 2572 /* and start if the pipe wasn't running */ 2573 if (!err) 2574 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2575 2576 return err; 2577 } 2578 2579 void 2580 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2581 { 2582 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2583 usbd_device_handle dev = upipe->pipe.up_dev; 2584 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2585 struct iso *iso = &upipe->u.iso; 2586 uhci_soft_td_t *std; 2587 uint32_t buf, len, status, offs; 2588 int i, next, nframes; 2589 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2590 2591 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2592 "nframes=%d\n", 2593 iso->inuse, iso->next, xfer, xfer->ux_nframes)); 2594 2595 if (sc->sc_dying) 2596 return; 2597 2598 if (xfer->ux_status == USBD_IN_PROGRESS) { 2599 /* This request has already been entered into the frame list */ 2600 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2601 /* XXX */ 2602 } 2603 2604 #ifdef DIAGNOSTIC 2605 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2606 printf("uhci_device_isoc_enter: overflow!\n"); 2607 #endif 2608 2609 next = iso->next; 2610 if (next == -1) { 2611 /* Not in use yet, schedule it a few frames ahead. */ 2612 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2613 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2614 } 2615 2616 xfer->ux_status = USBD_IN_PROGRESS; 2617 UXFER(xfer)->curframe = next; 2618 2619 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2620 offs = 0; 2621 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2622 UHCI_TD_ACTIVE | 2623 UHCI_TD_IOS); 2624 nframes = xfer->ux_nframes; 2625 mutex_enter(&sc->sc_lock); 2626 for (i = 0; i < nframes; i++) { 2627 std = iso->stds[next]; 2628 if (++next >= UHCI_VFRAMELIST_COUNT) 2629 next = 0; 2630 len = xfer->ux_frlengths[i]; 2631 std->td.td_buffer = htole32(buf); 2632 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2633 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2634 if (i == nframes - 1) 2635 status |= UHCI_TD_IOC; 2636 std->td.td_status = htole32(status); 2637 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2638 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2639 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2640 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2641 #ifdef UHCI_DEBUG 2642 if (uhcidebug > 5) { 2643 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2644 uhci_dump_td(std); 2645 } 2646 #endif 2647 buf += len; 2648 offs += len; 2649 } 2650 iso->next = next; 2651 iso->inuse += xfer->ux_nframes; 2652 2653 mutex_exit(&sc->sc_lock); 2654 } 2655 2656 usbd_status 2657 uhci_device_isoc_start(usbd_xfer_handle xfer) 2658 { 2659 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2660 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2661 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2662 uhci_soft_td_t *end; 2663 int i; 2664 2665 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2666 2667 mutex_enter(&sc->sc_lock); 2668 2669 if (sc->sc_dying) { 2670 mutex_exit(&sc->sc_lock); 2671 return USBD_IOERROR; 2672 } 2673 2674 #ifdef DIAGNOSTIC 2675 if (xfer->ux_status != USBD_IN_PROGRESS) 2676 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2677 #endif 2678 2679 /* Find the last TD */ 2680 i = UXFER(xfer)->curframe + xfer->ux_nframes; 2681 if (i >= UHCI_VFRAMELIST_COUNT) 2682 i -= UHCI_VFRAMELIST_COUNT; 2683 end = upipe->u.iso.stds[i]; 2684 2685 #ifdef DIAGNOSTIC 2686 if (end == NULL) { 2687 printf("uhci_device_isoc_start: end == NULL\n"); 2688 return USBD_INVAL; 2689 } 2690 #endif 2691 2692 /* Set up interrupt info. */ 2693 ii->xfer = xfer; 2694 ii->stdstart = end; 2695 ii->stdend = end; 2696 #ifdef DIAGNOSTIC 2697 if (!ii->isdone) 2698 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2699 ii->isdone = 0; 2700 #endif 2701 uhci_add_intr_info(sc, ii); 2702 2703 mutex_exit(&sc->sc_lock); 2704 2705 return USBD_IN_PROGRESS; 2706 } 2707 2708 void 2709 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2710 { 2711 #ifdef DIAGNOSTIC 2712 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2713 #endif 2714 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2715 uhci_soft_td_t **stds = upipe->u.iso.stds; 2716 uhci_soft_td_t *std; 2717 int i, n, nframes, maxlen, len; 2718 2719 KASSERT(mutex_owned(&sc->sc_lock)); 2720 2721 /* Transfer is already done. */ 2722 if (xfer->ux_status != USBD_NOT_STARTED && 2723 xfer->ux_status != USBD_IN_PROGRESS) { 2724 return; 2725 } 2726 2727 /* Give xfer the requested abort code. */ 2728 xfer->ux_status = USBD_CANCELLED; 2729 2730 /* make hardware ignore it, */ 2731 nframes = xfer->ux_nframes; 2732 n = UXFER(xfer)->curframe; 2733 maxlen = 0; 2734 for (i = 0; i < nframes; i++) { 2735 std = stds[n]; 2736 usb_syncmem(&std->dma, 2737 std->offs + offsetof(uhci_td_t, td_status), 2738 sizeof(std->td.td_status), 2739 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2740 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2741 usb_syncmem(&std->dma, 2742 std->offs + offsetof(uhci_td_t, td_status), 2743 sizeof(std->td.td_status), 2744 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2745 usb_syncmem(&std->dma, 2746 std->offs + offsetof(uhci_td_t, td_token), 2747 sizeof(std->td.td_token), 2748 BUS_DMASYNC_POSTWRITE); 2749 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2750 if (len > maxlen) 2751 maxlen = len; 2752 if (++n >= UHCI_VFRAMELIST_COUNT) 2753 n = 0; 2754 } 2755 2756 /* and wait until we are sure the hardware has finished. */ 2757 delay(maxlen); 2758 2759 #ifdef DIAGNOSTIC 2760 UXFER(xfer)->iinfo.isdone = 1; 2761 #endif 2762 /* Run callback and remove from interrupt list. */ 2763 usb_transfer_complete(xfer); 2764 2765 KASSERT(mutex_owned(&sc->sc_lock)); 2766 } 2767 2768 void 2769 uhci_device_isoc_close(usbd_pipe_handle pipe) 2770 { 2771 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2772 usbd_device_handle dev = upipe->pipe.up_dev; 2773 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2774 uhci_soft_td_t *std, *vstd; 2775 struct iso *iso; 2776 int i; 2777 2778 KASSERT(mutex_owned(&sc->sc_lock)); 2779 2780 /* 2781 * Make sure all TDs are marked as inactive. 2782 * Wait for completion. 2783 * Unschedule. 2784 * Deallocate. 2785 */ 2786 iso = &upipe->u.iso; 2787 2788 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2789 std = iso->stds[i]; 2790 usb_syncmem(&std->dma, 2791 std->offs + offsetof(uhci_td_t, td_status), 2792 sizeof(std->td.td_status), 2793 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2794 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2795 usb_syncmem(&std->dma, 2796 std->offs + offsetof(uhci_td_t, td_status), 2797 sizeof(std->td.td_status), 2798 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2799 } 2800 /* wait for completion */ 2801 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2802 2803 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2804 std = iso->stds[i]; 2805 for (vstd = sc->sc_vframes[i].htd; 2806 vstd != NULL && vstd->link.std != std; 2807 vstd = vstd->link.std) 2808 ; 2809 if (vstd == NULL) { 2810 /*panic*/ 2811 printf("uhci_device_isoc_close: %p not found\n", std); 2812 mutex_exit(&sc->sc_lock); 2813 return; 2814 } 2815 vstd->link = std->link; 2816 usb_syncmem(&std->dma, 2817 std->offs + offsetof(uhci_td_t, td_link), 2818 sizeof(std->td.td_link), 2819 BUS_DMASYNC_POSTWRITE); 2820 vstd->td.td_link = std->td.td_link; 2821 usb_syncmem(&vstd->dma, 2822 vstd->offs + offsetof(uhci_td_t, td_link), 2823 sizeof(vstd->td.td_link), 2824 BUS_DMASYNC_PREWRITE); 2825 uhci_free_std(sc, std); 2826 } 2827 2828 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2829 } 2830 2831 usbd_status 2832 uhci_setup_isoc(usbd_pipe_handle pipe) 2833 { 2834 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2835 usbd_device_handle dev = upipe->pipe.up_dev; 2836 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2837 int addr = upipe->pipe.up_dev->ud_addr; 2838 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2839 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2840 uhci_soft_td_t *std, *vstd; 2841 uint32_t token; 2842 struct iso *iso; 2843 int i; 2844 2845 iso = &upipe->u.iso; 2846 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2847 sizeof (uhci_soft_td_t *), 2848 KM_SLEEP); 2849 if (iso->stds == NULL) 2850 return USBD_NOMEM; 2851 2852 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2853 UHCI_TD_OUT(0, endpt, addr, 0); 2854 2855 mutex_enter(&sc->sc_lock); 2856 2857 /* Allocate the TDs and mark as inactive; */ 2858 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2859 std = uhci_alloc_std(sc); 2860 if (std == 0) 2861 goto bad; 2862 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2863 std->td.td_token = htole32(token); 2864 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2865 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2866 iso->stds[i] = std; 2867 } 2868 2869 /* Insert TDs into schedule. */ 2870 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2871 std = iso->stds[i]; 2872 vstd = sc->sc_vframes[i].htd; 2873 usb_syncmem(&vstd->dma, 2874 vstd->offs + offsetof(uhci_td_t, td_link), 2875 sizeof(vstd->td.td_link), 2876 BUS_DMASYNC_POSTWRITE); 2877 std->link = vstd->link; 2878 std->td.td_link = vstd->td.td_link; 2879 usb_syncmem(&std->dma, 2880 std->offs + offsetof(uhci_td_t, td_link), 2881 sizeof(std->td.td_link), 2882 BUS_DMASYNC_PREWRITE); 2883 vstd->link.std = std; 2884 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2885 usb_syncmem(&vstd->dma, 2886 vstd->offs + offsetof(uhci_td_t, td_link), 2887 sizeof(vstd->td.td_link), 2888 BUS_DMASYNC_PREWRITE); 2889 } 2890 mutex_exit(&sc->sc_lock); 2891 2892 iso->next = -1; 2893 iso->inuse = 0; 2894 2895 return USBD_NORMAL_COMPLETION; 2896 2897 bad: 2898 while (--i >= 0) 2899 uhci_free_std(sc, iso->stds[i]); 2900 mutex_exit(&sc->sc_lock); 2901 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2902 return USBD_NOMEM; 2903 } 2904 2905 void 2906 uhci_device_isoc_done(usbd_xfer_handle xfer) 2907 { 2908 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2909 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2910 int i, offs; 2911 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2912 2913 2914 DPRINTFN(4, ("uhci_isoc_done: length=%d, ux_state=0x%08x\n", 2915 xfer->ux_actlen, xfer->ux_state)); 2916 2917 if (ii->xfer != xfer) 2918 /* Not on interrupt list, ignore it. */ 2919 return; 2920 2921 if (!uhci_active_intr_info(ii)) 2922 return; 2923 2924 #ifdef DIAGNOSTIC 2925 if (ii->stdend == NULL) { 2926 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2927 #ifdef UHCI_DEBUG 2928 uhci_dump_ii(ii); 2929 #endif 2930 return; 2931 } 2932 #endif 2933 2934 /* Turn off the interrupt since it is active even if the TD is not. */ 2935 usb_syncmem(&ii->stdend->dma, 2936 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2937 sizeof(ii->stdend->td.td_status), 2938 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2939 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2940 usb_syncmem(&ii->stdend->dma, 2941 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2942 sizeof(ii->stdend->td.td_status), 2943 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2944 2945 uhci_del_intr_info(ii); /* remove from active list */ 2946 2947 offs = 0; 2948 for (i = 0; i < xfer->ux_nframes; i++) { 2949 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2950 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2951 offs += xfer->ux_frlengths[i]; 2952 } 2953 } 2954 2955 void 2956 uhci_device_intr_done(usbd_xfer_handle xfer) 2957 { 2958 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2959 uhci_softc_t *sc = ii->sc; 2960 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2961 uhci_soft_qh_t *sqh; 2962 int i, npoll, isread; 2963 2964 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->ux_actlen)); 2965 2966 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2967 2968 npoll = upipe->u.intr.npoll; 2969 for(i = 0; i < npoll; i++) { 2970 sqh = upipe->u.intr.qhs[i]; 2971 sqh->elink = NULL; 2972 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2973 usb_syncmem(&sqh->dma, 2974 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2975 sizeof(sqh->qh.qh_elink), 2976 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2977 } 2978 uhci_free_std_chain(sc, ii->stdstart, NULL); 2979 2980 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2981 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2982 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2983 2984 /* XXX Wasteful. */ 2985 if (xfer->ux_pipe->up_repeat) { 2986 uhci_soft_td_t *data, *dataend; 2987 2988 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2989 2990 /* This alloc cannot fail since we freed the chain above. */ 2991 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 2992 upipe->u.intr.isread, xfer->ux_flags, 2993 &xfer->ux_dmabuf, &data, &dataend); 2994 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2995 usb_syncmem(&dataend->dma, 2996 dataend->offs + offsetof(uhci_td_t, td_status), 2997 sizeof(dataend->td.td_status), 2998 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2999 3000 #ifdef UHCI_DEBUG 3001 if (uhcidebug > 10) { 3002 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3003 uhci_dump_tds(data); 3004 uhci_dump_qh(upipe->u.intr.qhs[0]); 3005 } 3006 #endif 3007 3008 ii->stdstart = data; 3009 ii->stdend = dataend; 3010 #ifdef DIAGNOSTIC 3011 if (!ii->isdone) { 3012 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3013 } 3014 ii->isdone = 0; 3015 #endif 3016 for (i = 0; i < npoll; i++) { 3017 sqh = upipe->u.intr.qhs[i]; 3018 sqh->elink = data; 3019 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3020 usb_syncmem(&sqh->dma, 3021 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3022 sizeof(sqh->qh.qh_elink), 3023 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3024 } 3025 xfer->ux_status = USBD_IN_PROGRESS; 3026 /* The ii is already on the examined list, just leave it. */ 3027 } else { 3028 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3029 if (uhci_active_intr_info(ii)) 3030 uhci_del_intr_info(ii); 3031 } 3032 } 3033 3034 /* Deallocate request data structures */ 3035 void 3036 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3037 { 3038 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3039 uhci_softc_t *sc = ii->sc; 3040 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3041 int len = UGETW(xfer->ux_request.wLength); 3042 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3043 3044 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3045 3046 #ifdef DIAGNOSTIC 3047 if (!(xfer->ux_rqflags & URQ_REQUEST)) 3048 panic("uhci_device_ctrl_done: not a request"); 3049 #endif 3050 3051 if (!uhci_active_intr_info(ii)) 3052 return; 3053 3054 uhci_del_intr_info(ii); /* remove from active list */ 3055 3056 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3057 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3058 else 3059 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3060 3061 if (upipe->u.ctl.length != 0) 3062 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3063 3064 if (len) { 3065 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3066 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3067 } 3068 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3069 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3070 3071 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->ux_actlen)); 3072 } 3073 3074 /* Deallocate request data structures */ 3075 void 3076 uhci_device_bulk_done(usbd_xfer_handle xfer) 3077 { 3078 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3079 uhci_softc_t *sc = ii->sc; 3080 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3081 3082 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3083 xfer, ii, sc, upipe)); 3084 3085 KASSERT(mutex_owned(&sc->sc_lock)); 3086 3087 if (!uhci_active_intr_info(ii)) 3088 return; 3089 3090 uhci_del_intr_info(ii); /* remove from active list */ 3091 3092 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3093 3094 uhci_free_std_chain(sc, ii->stdstart, NULL); 3095 3096 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->ux_actlen)); 3097 } 3098 3099 /* Add interrupt QH, called with vflock. */ 3100 void 3101 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3102 { 3103 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3104 uhci_soft_qh_t *eqh; 3105 3106 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3107 3108 eqh = vf->eqh; 3109 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3110 sizeof(eqh->qh.qh_hlink), 3111 BUS_DMASYNC_POSTWRITE); 3112 sqh->hlink = eqh->hlink; 3113 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3114 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3115 sizeof(sqh->qh.qh_hlink), 3116 BUS_DMASYNC_PREWRITE); 3117 eqh->hlink = sqh; 3118 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3119 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3120 sizeof(eqh->qh.qh_hlink), 3121 BUS_DMASYNC_PREWRITE); 3122 vf->eqh = sqh; 3123 vf->bandwidth++; 3124 } 3125 3126 /* Remove interrupt QH. */ 3127 void 3128 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3129 { 3130 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3131 uhci_soft_qh_t *pqh; 3132 3133 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3134 3135 /* See comment in uhci_remove_ctrl() */ 3136 3137 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3138 sizeof(sqh->qh.qh_elink), 3139 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3140 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3141 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3142 usb_syncmem(&sqh->dma, 3143 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3144 sizeof(sqh->qh.qh_elink), 3145 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3146 delay(UHCI_QH_REMOVE_DELAY); 3147 } 3148 3149 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3150 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3151 sizeof(sqh->qh.qh_hlink), 3152 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3153 pqh->hlink = sqh->hlink; 3154 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3155 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3156 sizeof(pqh->qh.qh_hlink), 3157 BUS_DMASYNC_PREWRITE); 3158 delay(UHCI_QH_REMOVE_DELAY); 3159 if (vf->eqh == sqh) 3160 vf->eqh = pqh; 3161 vf->bandwidth--; 3162 } 3163 3164 usbd_status 3165 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3166 { 3167 uhci_soft_qh_t *sqh; 3168 int i, npoll; 3169 u_int bestbw, bw, bestoffs, offs; 3170 3171 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3172 if (ival == 0) { 3173 printf("uhci_device_setintr: 0 interval\n"); 3174 return USBD_INVAL; 3175 } 3176 3177 if (ival > UHCI_VFRAMELIST_COUNT) 3178 ival = UHCI_VFRAMELIST_COUNT; 3179 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3180 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3181 3182 upipe->u.intr.npoll = npoll; 3183 upipe->u.intr.qhs = 3184 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3185 if (upipe->u.intr.qhs == NULL) 3186 return USBD_NOMEM; 3187 3188 /* 3189 * Figure out which offset in the schedule that has most 3190 * bandwidth left over. 3191 */ 3192 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3193 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3194 for (bw = i = 0; i < npoll; i++) 3195 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3196 if (bw < bestbw) { 3197 bestbw = bw; 3198 bestoffs = offs; 3199 } 3200 } 3201 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3202 3203 mutex_enter(&sc->sc_lock); 3204 for(i = 0; i < npoll; i++) { 3205 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3206 sqh->elink = NULL; 3207 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3208 usb_syncmem(&sqh->dma, 3209 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3210 sizeof(sqh->qh.qh_elink), 3211 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3212 sqh->pos = MOD(i * ival + bestoffs); 3213 } 3214 #undef MOD 3215 3216 /* Enter QHs into the controller data structures. */ 3217 for(i = 0; i < npoll; i++) 3218 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3219 mutex_exit(&sc->sc_lock); 3220 3221 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3222 return USBD_NORMAL_COMPLETION; 3223 } 3224 3225 /* Open a new pipe. */ 3226 usbd_status 3227 uhci_open(usbd_pipe_handle pipe) 3228 { 3229 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3230 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3231 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3232 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3233 usbd_status err = USBD_NOMEM; 3234 int ival; 3235 3236 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3237 pipe, pipe->up_dev->ud_addr, 3238 ed->bEndpointAddress, bus->ub_rhaddr)); 3239 3240 if (sc->sc_dying) 3241 return USBD_IOERROR; 3242 3243 upipe->aborting = 0; 3244 /* toggle state needed for bulk endpoints */ 3245 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3246 3247 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3248 switch (ed->bEndpointAddress) { 3249 case USB_CONTROL_ENDPOINT: 3250 pipe->up_methods = &roothub_ctrl_methods; 3251 break; 3252 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3253 pipe->up_methods = &uhci_root_intr_methods; 3254 break; 3255 default: 3256 return USBD_INVAL; 3257 } 3258 } else { 3259 switch (ed->bmAttributes & UE_XFERTYPE) { 3260 case UE_CONTROL: 3261 pipe->up_methods = &uhci_device_ctrl_methods; 3262 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3263 if (upipe->u.ctl.sqh == NULL) 3264 goto bad; 3265 upipe->u.ctl.setup = uhci_alloc_std(sc); 3266 if (upipe->u.ctl.setup == NULL) { 3267 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3268 goto bad; 3269 } 3270 upipe->u.ctl.stat = uhci_alloc_std(sc); 3271 if (upipe->u.ctl.stat == NULL) { 3272 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3273 uhci_free_std(sc, upipe->u.ctl.setup); 3274 goto bad; 3275 } 3276 err = usb_allocmem(&sc->sc_bus, 3277 sizeof(usb_device_request_t), 3278 0, &upipe->u.ctl.reqdma); 3279 if (err) { 3280 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3281 uhci_free_std(sc, upipe->u.ctl.setup); 3282 uhci_free_std(sc, upipe->u.ctl.stat); 3283 goto bad; 3284 } 3285 break; 3286 case UE_INTERRUPT: 3287 pipe->up_methods = &uhci_device_intr_methods; 3288 ival = pipe->up_interval; 3289 if (ival == USBD_DEFAULT_INTERVAL) 3290 ival = ed->bInterval; 3291 return uhci_device_setintr(sc, upipe, ival); 3292 case UE_ISOCHRONOUS: 3293 pipe->up_methods = &uhci_device_isoc_methods; 3294 return uhci_setup_isoc(pipe); 3295 case UE_BULK: 3296 pipe->up_methods = &uhci_device_bulk_methods; 3297 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3298 if (upipe->u.bulk.sqh == NULL) 3299 goto bad; 3300 break; 3301 } 3302 } 3303 return USBD_NORMAL_COMPLETION; 3304 3305 bad: 3306 return USBD_NOMEM; 3307 } 3308 3309 /* 3310 * Data structures and routines to emulate the root hub. 3311 */ 3312 /* 3313 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3314 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3315 * should not be used by the USB subsystem. As we cannot issue a 3316 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3317 * will be enabled as part of the reset. 3318 * 3319 * On the VT83C572, the port cannot be successfully enabled until the 3320 * outstanding "port enable change" and "connection status change" 3321 * events have been reset. 3322 */ 3323 Static usbd_status 3324 uhci_portreset(uhci_softc_t *sc, int index) 3325 { 3326 int lim, port, x; 3327 3328 if (index == 1) 3329 port = UHCI_PORTSC1; 3330 else if (index == 2) 3331 port = UHCI_PORTSC2; 3332 else 3333 return USBD_IOERROR; 3334 3335 x = URWMASK(UREAD2(sc, port)); 3336 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3337 3338 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3339 3340 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3341 index, UREAD2(sc, port))); 3342 3343 x = URWMASK(UREAD2(sc, port)); 3344 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3345 3346 delay(100); 3347 3348 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3349 index, UREAD2(sc, port))); 3350 3351 x = URWMASK(UREAD2(sc, port)); 3352 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3353 3354 for (lim = 10; --lim > 0;) { 3355 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3356 3357 x = UREAD2(sc, port); 3358 3359 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3360 index, lim, x)); 3361 3362 if (!(x & UHCI_PORTSC_CCS)) { 3363 /* 3364 * No device is connected (or was disconnected 3365 * during reset). Consider the port reset. 3366 * The delay must be long enough to ensure on 3367 * the initial iteration that the device 3368 * connection will have been registered. 50ms 3369 * appears to be sufficient, but 20ms is not. 3370 */ 3371 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3372 index, lim)); 3373 break; 3374 } 3375 3376 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3377 /* 3378 * Port enabled changed and/or connection 3379 * status changed were set. Reset either or 3380 * both raised flags (by writing a 1 to that 3381 * bit), and wait again for state to settle. 3382 */ 3383 UWRITE2(sc, port, URWMASK(x) | 3384 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3385 continue; 3386 } 3387 3388 if (x & UHCI_PORTSC_PE) 3389 /* Port is enabled */ 3390 break; 3391 3392 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3393 } 3394 3395 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3396 index, UREAD2(sc, port))); 3397 3398 if (lim <= 0) { 3399 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3400 return USBD_TIMEOUT; 3401 } 3402 3403 sc->sc_isreset = 1; 3404 return USBD_NORMAL_COMPLETION; 3405 } 3406 3407 Static int 3408 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3409 void *buf, int buflen) 3410 { 3411 uhci_softc_t *sc = bus->ub_hcpriv; 3412 int port, x; 3413 int status, change, totlen = 0; 3414 uint16_t len, value, index; 3415 usb_port_status_t ps; 3416 usbd_status err; 3417 3418 if (sc->sc_dying) 3419 return -1; 3420 3421 DPRINTFN(2,("%s: type=0x%02x request=%02x\n", __func__, 3422 req->bmRequestType, req->bRequest)); 3423 3424 len = UGETW(req->wLength); 3425 value = UGETW(req->wValue); 3426 index = UGETW(req->wIndex); 3427 3428 #define C(x,y) ((x) | ((y) << 8)) 3429 switch (C(req->bRequest, req->bmRequestType)) { 3430 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3431 DPRINTFN(2,("%s: wValue=0x%04x\n", __func__, value)); 3432 if (len == 0) 3433 break; 3434 switch (value) { 3435 case C(0, UDESC_DEVICE): { 3436 usb_device_descriptor_t devd; 3437 3438 totlen = min(buflen, sizeof(devd)); 3439 memcpy(&devd, buf, totlen); 3440 USETW(devd.idVendor, sc->sc_id_vendor); 3441 memcpy(buf, &devd, totlen); 3442 break; 3443 } 3444 case C(1, UDESC_STRING): 3445 #define sd ((usb_string_descriptor_t *)buf) 3446 /* Vendor */ 3447 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3448 break; 3449 case C(2, UDESC_STRING): 3450 /* Product */ 3451 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3452 break; 3453 #undef sd 3454 default: 3455 /* default from usbroothub */ 3456 return buflen; 3457 } 3458 break; 3459 3460 /* Hub requests */ 3461 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3462 break; 3463 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3464 DPRINTFN(3, ("%s: UR_CLEAR_PORT_FEATURE " 3465 "port=%d feature=%d\n", __func__, 3466 index, value)); 3467 if (index == 1) 3468 port = UHCI_PORTSC1; 3469 else if (index == 2) 3470 port = UHCI_PORTSC2; 3471 else { 3472 return -1; 3473 } 3474 switch(value) { 3475 case UHF_PORT_ENABLE: 3476 x = URWMASK(UREAD2(sc, port)); 3477 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3478 break; 3479 case UHF_PORT_SUSPEND: 3480 x = URWMASK(UREAD2(sc, port)); 3481 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3482 break; 3483 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3484 /* see USB2 spec ch. 7.1.7.7 */ 3485 usb_delay_ms(&sc->sc_bus, 20); 3486 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3487 /* 10ms resume delay must be provided by caller */ 3488 break; 3489 case UHF_PORT_RESET: 3490 x = URWMASK(UREAD2(sc, port)); 3491 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3492 break; 3493 case UHF_C_PORT_CONNECTION: 3494 x = URWMASK(UREAD2(sc, port)); 3495 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3496 break; 3497 case UHF_C_PORT_ENABLE: 3498 x = URWMASK(UREAD2(sc, port)); 3499 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3500 break; 3501 case UHF_C_PORT_OVER_CURRENT: 3502 x = URWMASK(UREAD2(sc, port)); 3503 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3504 break; 3505 case UHF_C_PORT_RESET: 3506 sc->sc_isreset = 0; 3507 break; 3508 case UHF_PORT_CONNECTION: 3509 case UHF_PORT_OVER_CURRENT: 3510 case UHF_PORT_POWER: 3511 case UHF_PORT_LOW_SPEED: 3512 case UHF_C_PORT_SUSPEND: 3513 default: 3514 return -1; 3515 } 3516 break; 3517 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3518 if (index == 1) 3519 port = UHCI_PORTSC1; 3520 else if (index == 2) 3521 port = UHCI_PORTSC2; 3522 else { 3523 return -1; 3524 } 3525 if (len > 0) { 3526 *(uint8_t *)buf = 3527 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3528 UHCI_PORTSC_LS_SHIFT; 3529 totlen = 1; 3530 } 3531 break; 3532 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3533 if (len == 0) 3534 break; 3535 if ((value & 0xff) != 0) { 3536 return -1; 3537 } 3538 usb_hub_descriptor_t hubd; 3539 3540 totlen = min(buflen, sizeof(hubd)); 3541 memcpy(&hubd, buf, totlen); 3542 hubd.bNbrPorts = 2; 3543 memcpy(buf, &hubd, totlen); 3544 break; 3545 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3546 if (len != 4) { 3547 return -1; 3548 } 3549 memset(buf, 0, len); 3550 totlen = len; 3551 break; 3552 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3553 if (index == 1) 3554 port = UHCI_PORTSC1; 3555 else if (index == 2) 3556 port = UHCI_PORTSC2; 3557 else { 3558 return -1; 3559 } 3560 if (len != 4) { 3561 return -1; 3562 } 3563 x = UREAD2(sc, port); 3564 status = change = 0; 3565 if (x & UHCI_PORTSC_CCS) 3566 status |= UPS_CURRENT_CONNECT_STATUS; 3567 if (x & UHCI_PORTSC_CSC) 3568 change |= UPS_C_CONNECT_STATUS; 3569 if (x & UHCI_PORTSC_PE) 3570 status |= UPS_PORT_ENABLED; 3571 if (x & UHCI_PORTSC_POEDC) 3572 change |= UPS_C_PORT_ENABLED; 3573 if (x & UHCI_PORTSC_OCI) 3574 status |= UPS_OVERCURRENT_INDICATOR; 3575 if (x & UHCI_PORTSC_OCIC) 3576 change |= UPS_C_OVERCURRENT_INDICATOR; 3577 if (x & UHCI_PORTSC_SUSP) 3578 status |= UPS_SUSPEND; 3579 if (x & UHCI_PORTSC_LSDA) 3580 status |= UPS_LOW_SPEED; 3581 status |= UPS_PORT_POWER; 3582 if (sc->sc_isreset) 3583 change |= UPS_C_PORT_RESET; 3584 USETW(ps.wPortStatus, status); 3585 USETW(ps.wPortChange, change); 3586 totlen = min(len, sizeof(ps)); 3587 memcpy(buf, &ps, totlen); 3588 break; 3589 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3590 return -1; 3591 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3592 break; 3593 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3594 if (index == 1) 3595 port = UHCI_PORTSC1; 3596 else if (index == 2) 3597 port = UHCI_PORTSC2; 3598 else { 3599 return -1; 3600 } 3601 switch(value) { 3602 case UHF_PORT_ENABLE: 3603 x = URWMASK(UREAD2(sc, port)); 3604 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3605 break; 3606 case UHF_PORT_SUSPEND: 3607 x = URWMASK(UREAD2(sc, port)); 3608 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3609 break; 3610 case UHF_PORT_RESET: 3611 err = uhci_portreset(sc, index); 3612 if (err != USBD_NORMAL_COMPLETION) 3613 return -1; 3614 return 0; 3615 case UHF_PORT_POWER: 3616 /* Pretend we turned on power */ 3617 return 0; 3618 case UHF_C_PORT_CONNECTION: 3619 case UHF_C_PORT_ENABLE: 3620 case UHF_C_PORT_OVER_CURRENT: 3621 case UHF_PORT_CONNECTION: 3622 case UHF_PORT_OVER_CURRENT: 3623 case UHF_PORT_LOW_SPEED: 3624 case UHF_C_PORT_SUSPEND: 3625 case UHF_C_PORT_RESET: 3626 default: 3627 return -1; 3628 } 3629 break; 3630 default: 3631 /* default from usbroothub */ 3632 return buflen; 3633 } 3634 3635 return totlen; 3636 } 3637 3638 /* Abort a root interrupt request. */ 3639 void 3640 uhci_root_intr_abort(usbd_xfer_handle xfer) 3641 { 3642 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3643 3644 KASSERT(mutex_owned(&sc->sc_lock)); 3645 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3646 3647 callout_stop(&sc->sc_poll_handle); 3648 sc->sc_intr_xfer = NULL; 3649 3650 xfer->ux_status = USBD_CANCELLED; 3651 #ifdef DIAGNOSTIC 3652 UXFER(xfer)->iinfo.isdone = 1; 3653 #endif 3654 usb_transfer_complete(xfer); 3655 } 3656 3657 usbd_status 3658 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3659 { 3660 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3661 usbd_status err; 3662 3663 /* Insert last in queue. */ 3664 mutex_enter(&sc->sc_lock); 3665 err = usb_insert_transfer(xfer); 3666 mutex_exit(&sc->sc_lock); 3667 if (err) 3668 return err; 3669 3670 /* 3671 * Pipe isn't running (otherwise err would be USBD_INPROG), 3672 * start first 3673 */ 3674 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3675 } 3676 3677 /* Start a transfer on the root interrupt pipe */ 3678 usbd_status 3679 uhci_root_intr_start(usbd_xfer_handle xfer) 3680 { 3681 usbd_pipe_handle pipe = xfer->ux_pipe; 3682 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3683 unsigned int ival; 3684 3685 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3686 xfer, xfer->ux_length, xfer->ux_flags)); 3687 3688 if (sc->sc_dying) 3689 return USBD_IOERROR; 3690 3691 /* XXX temporary variable needed to avoid gcc3 warning */ 3692 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3693 sc->sc_ival = mstohz(ival); 3694 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3695 sc->sc_intr_xfer = xfer; 3696 return USBD_IN_PROGRESS; 3697 } 3698 3699 /* Close the root interrupt pipe. */ 3700 void 3701 uhci_root_intr_close(usbd_pipe_handle pipe) 3702 { 3703 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3704 3705 KASSERT(mutex_owned(&sc->sc_lock)); 3706 3707 callout_stop(&sc->sc_poll_handle); 3708 sc->sc_intr_xfer = NULL; 3709 DPRINTF(("uhci_root_intr_close\n")); 3710 } 3711
Indexes created Tue Sep 30 17:09:57 GMT 2025