uhci.c revision 1.264.4.19
1 /* $NetBSD: uhci.c,v 1.264.4.19 2015/02/01 12:08:15 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.19 2015/02/01 12:08:15 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/proc.h> 54 #include <sys/queue.h> 55 #include <sys/bus.h> 56 #include <sys/cpu.h> 57 58 #include <machine/endian.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usb_mem.h> 64 #include <dev/usb/usb_quirks.h> 65 66 #include <dev/usb/uhcireg.h> 67 #include <dev/usb/uhcivar.h> 68 #include <dev/usb/usbroothub.h> 69 70 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 71 /*#define UHCI_CTL_LOOP */ 72 73 74 75 #ifdef UHCI_DEBUG 76 uhci_softc_t *thesc; 77 #define DPRINTF(x) if (uhcidebug) printf x 78 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 79 int uhcidebug = 0; 80 int uhcinoloop = 0; 81 #else 82 #define DPRINTF(x) 83 #define DPRINTFN(n,x) 84 #endif 85 86 /* 87 * The UHCI controller is little endian, so on big endian machines 88 * the data stored in memory needs to be swapped. 89 */ 90 91 struct uhci_pipe { 92 struct usbd_pipe pipe; 93 int nexttoggle; 94 95 u_char aborting; 96 usbd_xfer_handle abortstart, abortend; 97 98 /* Info needed for different pipe kinds. */ 99 union { 100 /* Control pipe */ 101 struct { 102 uhci_soft_qh_t *sqh; 103 usb_dma_t reqdma; 104 uhci_soft_td_t *setup, *stat; 105 u_int length; 106 } ctl; 107 /* Interrupt pipe */ 108 struct { 109 int npoll; 110 int isread; 111 uhci_soft_qh_t **qhs; 112 } intr; 113 /* Bulk pipe */ 114 struct { 115 uhci_soft_qh_t *sqh; 116 u_int length; 117 int isread; 118 } bulk; 119 /* Iso pipe */ 120 struct iso { 121 uhci_soft_td_t **stds; 122 int next, inuse; 123 } iso; 124 } u; 125 }; 126 127 Static void uhci_globalreset(uhci_softc_t *); 128 Static usbd_status uhci_portreset(uhci_softc_t*, int); 129 Static void uhci_reset(uhci_softc_t *); 130 Static usbd_status uhci_run(uhci_softc_t *, int, int); 131 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 132 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 133 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 134 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 135 #if 0 136 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 137 uhci_intr_info_t *); 138 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 139 #endif 140 141 Static void uhci_free_std_chain(uhci_softc_t *, 142 uhci_soft_td_t *, uhci_soft_td_t *); 143 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 144 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 145 uhci_soft_td_t **, uhci_soft_td_t **); 146 Static void uhci_poll_hub(void *); 147 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 148 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 149 Static void uhci_idone(uhci_intr_info_t *); 150 151 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status); 152 153 Static void uhci_timeout(void *); 154 Static void uhci_timeout_task(void *); 155 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 156 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 159 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_add_loop(uhci_softc_t *); 162 Static void uhci_rem_loop(uhci_softc_t *); 163 164 Static usbd_status uhci_setup_isoc(usbd_pipe_handle); 165 Static void uhci_device_isoc_enter(usbd_xfer_handle); 166 167 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 168 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 169 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 170 Static int uhci_roothub_ctrl(struct usbd_bus *, 171 usb_device_request_t *, void *, int); 172 173 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 174 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 175 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 176 Static void uhci_device_ctrl_close(usbd_pipe_handle); 177 Static void uhci_device_ctrl_done(usbd_xfer_handle); 178 179 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 180 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 181 Static void uhci_device_intr_abort(usbd_xfer_handle); 182 Static void uhci_device_intr_close(usbd_pipe_handle); 183 Static void uhci_device_intr_done(usbd_xfer_handle); 184 185 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 186 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 187 Static void uhci_device_bulk_abort(usbd_xfer_handle); 188 Static void uhci_device_bulk_close(usbd_pipe_handle); 189 Static void uhci_device_bulk_done(usbd_xfer_handle); 190 191 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 192 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 193 Static void uhci_device_isoc_abort(usbd_xfer_handle); 194 Static void uhci_device_isoc_close(usbd_pipe_handle); 195 Static void uhci_device_isoc_done(usbd_xfer_handle); 196 197 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 198 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 199 Static void uhci_root_intr_abort(usbd_xfer_handle); 200 Static void uhci_root_intr_close(usbd_pipe_handle); 201 Static void uhci_root_intr_done(usbd_xfer_handle); 202 203 Static usbd_status uhci_open(usbd_pipe_handle); 204 Static void uhci_poll(struct usbd_bus *); 205 Static void uhci_softintr(void *); 206 207 Static usbd_status uhci_device_request(usbd_xfer_handle); 208 209 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 210 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 211 Static usbd_status uhci_device_setintr(uhci_softc_t *, 212 struct uhci_pipe *, int); 213 214 Static void uhci_device_clear_toggle(usbd_pipe_handle); 215 Static void uhci_noop(usbd_pipe_handle); 216 217 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 218 uhci_soft_qh_t *); 219 220 #ifdef UHCI_DEBUG 221 Static void uhci_dump_all(uhci_softc_t *); 222 Static void uhci_dumpregs(uhci_softc_t *); 223 Static void uhci_dump_qhs(uhci_soft_qh_t *); 224 Static void uhci_dump_qh(uhci_soft_qh_t *); 225 Static void uhci_dump_tds(uhci_soft_td_t *); 226 Static void uhci_dump_td(uhci_soft_td_t *); 227 Static void uhci_dump_ii(uhci_intr_info_t *); 228 void uhci_dump(void); 229 #endif 230 231 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 232 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 233 #define UWRITE1(sc, r, x) \ 234 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 235 } while (/*CONSTCOND*/0) 236 #define UWRITE2(sc, r, x) \ 237 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 238 } while (/*CONSTCOND*/0) 239 #define UWRITE4(sc, r, x) \ 240 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 241 } while (/*CONSTCOND*/0) 242 static __inline uint8_t 243 UREAD1(uhci_softc_t *sc, bus_size_t r) 244 { 245 246 UBARR(sc); 247 return bus_space_read_1(sc->iot, sc->ioh, r); 248 } 249 250 static __inline uint16_t 251 UREAD2(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_2(sc->iot, sc->ioh, r); 256 } 257 258 #ifdef UHCI_DEBUG 259 static __inline uint32_t 260 UREAD4(uhci_softc_t *sc, bus_size_t r) 261 { 262 263 UBARR(sc); 264 return bus_space_read_4(sc->iot, sc->ioh, r); 265 } 266 #endif 267 268 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 269 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 270 271 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 272 273 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 274 275 const struct usbd_bus_methods uhci_bus_methods = { 276 .ubm_open = uhci_open, 277 .ubm_softint = uhci_softintr, 278 .ubm_dopoll = uhci_poll, 279 .ubm_allocx = uhci_allocx, 280 .ubm_freex = uhci_freex, 281 .ubm_getlock = uhci_get_lock, 282 .ubm_rhctrl = uhci_roothub_ctrl, 283 }; 284 285 const struct usbd_pipe_methods uhci_root_intr_methods = { 286 .upm_transfer = uhci_root_intr_transfer, 287 .upm_start = uhci_root_intr_start, 288 .upm_abort = uhci_root_intr_abort, 289 .upm_close = uhci_root_intr_close, 290 .upm_cleartoggle = uhci_noop, 291 .upm_done = uhci_root_intr_done, 292 }; 293 294 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 295 .upm_transfer = uhci_device_ctrl_transfer, 296 .upm_start = uhci_device_ctrl_start, 297 .upm_abort = uhci_device_ctrl_abort, 298 .upm_close = uhci_device_ctrl_close, 299 .upm_cleartoggle = uhci_noop, 300 .upm_done = uhci_device_ctrl_done, 301 }; 302 303 const struct usbd_pipe_methods uhci_device_intr_methods = { 304 .upm_transfer = uhci_device_intr_transfer, 305 .upm_start = uhci_device_intr_start, 306 .upm_abort = uhci_device_intr_abort, 307 .upm_close = uhci_device_intr_close, 308 .upm_cleartoggle = uhci_device_clear_toggle, 309 .upm_done = uhci_device_intr_done, 310 }; 311 312 const struct usbd_pipe_methods uhci_device_bulk_methods = { 313 .upm_transfer = uhci_device_bulk_transfer, 314 .upm_start = uhci_device_bulk_start, 315 .upm_abort = uhci_device_bulk_abort, 316 .upm_close = uhci_device_bulk_close, 317 .upm_cleartoggle = uhci_device_clear_toggle, 318 .upm_done = uhci_device_bulk_done, 319 }; 320 321 const struct usbd_pipe_methods uhci_device_isoc_methods = { 322 .upm_transfer = uhci_device_isoc_transfer, 323 .upm_start = uhci_device_isoc_start, 324 .upm_abort = uhci_device_isoc_abort, 325 .upm_close = uhci_device_isoc_close, 326 .upm_cleartoggle = uhci_noop, 327 .upm_done = uhci_device_isoc_done, 328 }; 329 330 #define uhci_add_intr_info(sc, ii) \ 331 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 332 #define uhci_del_intr_info(ii) \ 333 do { \ 334 LIST_REMOVE((ii), list); \ 335 (ii)->list.le_prev = NULL; \ 336 } while (0) 337 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 338 339 static inline uhci_soft_qh_t * 340 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 341 { 342 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 343 344 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 345 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 346 usb_syncmem(&pqh->dma, 347 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 348 sizeof(pqh->qh.qh_hlink), 349 BUS_DMASYNC_POSTWRITE); 350 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 351 printf("uhci_find_prev_qh: QH not found\n"); 352 return NULL; 353 } 354 #endif 355 } 356 return pqh; 357 } 358 359 void 360 uhci_globalreset(uhci_softc_t *sc) 361 { 362 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 363 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 364 UHCICMD(sc, 0); /* do nothing */ 365 } 366 367 int 368 uhci_init(uhci_softc_t *sc) 369 { 370 usbd_status err; 371 int i, j; 372 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 373 uhci_soft_td_t *std; 374 375 DPRINTFN(1,("uhci_init: start\n")); 376 377 #ifdef UHCI_DEBUG 378 thesc = sc; 379 380 if (uhcidebug > 2) 381 uhci_dumpregs(sc); 382 #endif 383 384 sc->sc_suspend = PWR_RESUME; 385 386 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 387 uhci_globalreset(sc); /* reset the controller */ 388 uhci_reset(sc); 389 390 /* Allocate and initialize real frame array. */ 391 err = usb_allocmem(&sc->sc_bus, 392 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 393 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 394 if (err) 395 return err; 396 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 397 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 398 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 399 400 /* 401 * Allocate a TD, inactive, that hangs from the last QH. 402 * This is to avoid a bug in the PIIX that makes it run berserk 403 * otherwise. 404 */ 405 std = uhci_alloc_std(sc); 406 if (std == NULL) 407 return ENOMEM; 408 std->link.std = NULL; 409 std->td.td_link = htole32(UHCI_PTR_T); 410 std->td.td_status = htole32(0); /* inactive */ 411 std->td.td_token = htole32(0); 412 std->td.td_buffer = htole32(0); 413 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 414 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 415 416 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 417 lsqh = uhci_alloc_sqh(sc); 418 if (lsqh == NULL) 419 return ENOMEM; 420 lsqh->hlink = NULL; 421 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 422 lsqh->elink = std; 423 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 424 sc->sc_last_qh = lsqh; 425 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 426 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 427 428 /* Allocate the dummy QH where bulk traffic will be queued. */ 429 bsqh = uhci_alloc_sqh(sc); 430 if (bsqh == NULL) 431 return ENOMEM; 432 bsqh->hlink = lsqh; 433 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 434 bsqh->elink = NULL; 435 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 436 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 437 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 438 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 439 440 /* Allocate dummy QH where high speed control traffic will be queued. */ 441 chsqh = uhci_alloc_sqh(sc); 442 if (chsqh == NULL) 443 return ENOMEM; 444 chsqh->hlink = bsqh; 445 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 446 chsqh->elink = NULL; 447 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 448 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 449 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 451 452 /* Allocate dummy QH where control traffic will be queued. */ 453 clsqh = uhci_alloc_sqh(sc); 454 if (clsqh == NULL) 455 return ENOMEM; 456 clsqh->hlink = chsqh; 457 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 458 clsqh->elink = NULL; 459 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 460 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 461 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 463 464 /* 465 * Make all (virtual) frame list pointers point to the interrupt 466 * queue heads and the interrupt queue heads at the control 467 * queue head and point the physical frame list to the virtual. 468 */ 469 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 470 std = uhci_alloc_std(sc); 471 sqh = uhci_alloc_sqh(sc); 472 if (std == NULL || sqh == NULL) 473 return USBD_NOMEM; 474 std->link.sqh = sqh; 475 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 476 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 477 std->td.td_token = htole32(0); 478 std->td.td_buffer = htole32(0); 479 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 481 sqh->hlink = clsqh; 482 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 483 sqh->elink = NULL; 484 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 485 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 487 sc->sc_vframes[i].htd = std; 488 sc->sc_vframes[i].etd = std; 489 sc->sc_vframes[i].hqh = sqh; 490 sc->sc_vframes[i].eqh = sqh; 491 for (j = i; 492 j < UHCI_FRAMELIST_COUNT; 493 j += UHCI_VFRAMELIST_COUNT) 494 sc->sc_pframes[j] = htole32(std->physaddr); 495 } 496 usb_syncmem(&sc->sc_dma, 0, 497 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 498 BUS_DMASYNC_PREWRITE); 499 500 501 LIST_INIT(&sc->sc_intrhead); 502 503 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 504 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 505 506 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 507 508 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 509 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 510 cv_init(&sc->sc_softwake_cv, "uhciab"); 511 512 /* Set up the bus struct. */ 513 sc->sc_bus.ub_methods = &uhci_bus_methods; 514 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 515 sc->sc_bus.ub_usedma = true; 516 517 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 518 519 DPRINTFN(1,("uhci_init: enabling\n")); 520 521 err = uhci_run(sc, 1, 0); /* and here we go... */ 522 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 523 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 524 return err; 525 } 526 527 int 528 uhci_activate(device_t self, enum devact act) 529 { 530 struct uhci_softc *sc = device_private(self); 531 532 switch (act) { 533 case DVACT_DEACTIVATE: 534 sc->sc_dying = 1; 535 return 0; 536 default: 537 return EOPNOTSUPP; 538 } 539 } 540 541 void 542 uhci_childdet(device_t self, device_t child) 543 { 544 struct uhci_softc *sc = device_private(self); 545 546 KASSERT(sc->sc_child == child); 547 sc->sc_child = NULL; 548 } 549 550 int 551 uhci_detach(struct uhci_softc *sc, int flags) 552 { 553 int rv = 0; 554 555 if (sc->sc_child != NULL) 556 rv = config_detach(sc->sc_child, flags); 557 558 if (rv != 0) 559 return rv; 560 561 callout_halt(&sc->sc_poll_handle, NULL); 562 callout_destroy(&sc->sc_poll_handle); 563 564 cv_destroy(&sc->sc_softwake_cv); 565 566 mutex_destroy(&sc->sc_lock); 567 mutex_destroy(&sc->sc_intr_lock); 568 569 pool_cache_destroy(sc->sc_xferpool); 570 571 /* XXX free other data structures XXX */ 572 573 return rv; 574 } 575 576 usbd_xfer_handle 577 uhci_allocx(struct usbd_bus *bus) 578 { 579 struct uhci_softc *sc = bus->ub_hcpriv; 580 usbd_xfer_handle xfer; 581 582 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 583 if (xfer != NULL) { 584 memset(xfer, 0, sizeof(struct uhci_xfer)); 585 UXFER(xfer)->iinfo.sc = sc; 586 #ifdef DIAGNOSTIC 587 UXFER(xfer)->iinfo.isdone = 1; 588 xfer->ux_state = XFER_BUSY; 589 #endif 590 } 591 return xfer; 592 } 593 594 void 595 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 596 { 597 struct uhci_softc *sc = bus->ub_hcpriv; 598 599 #ifdef DIAGNOSTIC 600 if (xfer->ux_state != XFER_BUSY) { 601 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 602 xfer->ux_state); 603 } 604 xfer->ux_state = XFER_FREE; 605 if (!UXFER(xfer)->iinfo.isdone) { 606 printf("uhci_freex: !isdone\n"); 607 } 608 #endif 609 pool_cache_put(sc->sc_xferpool, xfer); 610 } 611 612 Static void 613 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 614 { 615 struct uhci_softc *sc = bus->ub_hcpriv; 616 617 *lock = &sc->sc_lock; 618 } 619 620 621 /* 622 * Handle suspend/resume. 623 * 624 * We need to switch to polling mode here, because this routine is 625 * called from an interrupt context. This is all right since we 626 * are almost suspended anyway. 627 */ 628 bool 629 uhci_resume(device_t dv, const pmf_qual_t *qual) 630 { 631 uhci_softc_t *sc = device_private(dv); 632 int cmd; 633 634 mutex_spin_enter(&sc->sc_intr_lock); 635 636 cmd = UREAD2(sc, UHCI_CMD); 637 sc->sc_bus.ub_usepolling++; 638 UWRITE2(sc, UHCI_INTR, 0); 639 uhci_globalreset(sc); 640 uhci_reset(sc); 641 if (cmd & UHCI_CMD_RS) 642 uhci_run(sc, 0, 1); 643 644 /* restore saved state */ 645 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 646 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 647 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 648 649 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 650 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 651 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 652 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 653 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 654 UHCICMD(sc, UHCI_CMD_MAXP); 655 uhci_run(sc, 1, 1); /* and start traffic again */ 656 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 657 sc->sc_bus.ub_usepolling--; 658 if (sc->sc_intr_xfer != NULL) 659 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 660 sc->sc_intr_xfer); 661 #ifdef UHCI_DEBUG 662 if (uhcidebug > 2) 663 uhci_dumpregs(sc); 664 #endif 665 666 sc->sc_suspend = PWR_RESUME; 667 mutex_spin_exit(&sc->sc_intr_lock); 668 669 return true; 670 } 671 672 bool 673 uhci_suspend(device_t dv, const pmf_qual_t *qual) 674 { 675 uhci_softc_t *sc = device_private(dv); 676 int cmd; 677 678 mutex_spin_enter(&sc->sc_intr_lock); 679 680 cmd = UREAD2(sc, UHCI_CMD); 681 682 #ifdef UHCI_DEBUG 683 if (uhcidebug > 2) 684 uhci_dumpregs(sc); 685 #endif 686 if (sc->sc_intr_xfer != NULL) 687 callout_stop(&sc->sc_poll_handle); 688 sc->sc_suspend = PWR_SUSPEND; 689 sc->sc_bus.ub_usepolling++; 690 691 uhci_run(sc, 0, 1); /* stop the controller */ 692 cmd &= ~UHCI_CMD_RS; 693 694 /* save some state if BIOS doesn't */ 695 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 696 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 697 698 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 699 700 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 701 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 702 sc->sc_bus.ub_usepolling--; 703 704 mutex_spin_exit(&sc->sc_intr_lock); 705 706 return true; 707 } 708 709 #ifdef UHCI_DEBUG 710 Static void 711 uhci_dumpregs(uhci_softc_t *sc) 712 { 713 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 714 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 715 device_xname(sc->sc_dev), 716 UREAD2(sc, UHCI_CMD), 717 UREAD2(sc, UHCI_STS), 718 UREAD2(sc, UHCI_INTR), 719 UREAD2(sc, UHCI_FRNUM), 720 UREAD4(sc, UHCI_FLBASEADDR), 721 UREAD1(sc, UHCI_SOF), 722 UREAD2(sc, UHCI_PORTSC1), 723 UREAD2(sc, UHCI_PORTSC2))); 724 } 725 726 void 727 uhci_dump_td(uhci_soft_td_t *p) 728 { 729 char sbuf[128], sbuf2[128]; 730 731 732 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 733 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 734 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 735 "token=0x%08lx buffer=0x%08lx\n", 736 p, (long)p->physaddr, 737 (long)le32toh(p->td.td_link), 738 (long)le32toh(p->td.td_status), 739 (long)le32toh(p->td.td_token), 740 (long)le32toh(p->td.td_buffer))); 741 742 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 743 (uint32_t)le32toh(p->td.td_link)); 744 snprintb(sbuf2, sizeof(sbuf2), 745 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 746 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 747 (uint32_t)le32toh(p->td.td_status)); 748 749 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 750 "D=%d,maxlen=%d\n", sbuf, sbuf2, 751 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 752 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 753 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 754 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 755 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 756 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 757 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 758 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 759 BUS_DMASYNC_PREREAD); 760 } 761 762 void 763 uhci_dump_qh(uhci_soft_qh_t *sqh) 764 { 765 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 766 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 767 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 768 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 769 le32toh(sqh->qh.qh_elink))); 770 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 771 } 772 773 774 #if 1 775 void 776 uhci_dump(void) 777 { 778 uhci_dump_all(thesc); 779 } 780 #endif 781 782 void 783 uhci_dump_all(uhci_softc_t *sc) 784 { 785 uhci_dumpregs(sc); 786 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 787 uhci_dump_qhs(sc->sc_lctl_start); 788 } 789 790 791 void 792 uhci_dump_qhs(uhci_soft_qh_t *sqh) 793 { 794 uhci_dump_qh(sqh); 795 796 /* 797 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 798 * Traverses sideways first, then down. 799 * 800 * QH1 801 * QH2 802 * No QH 803 * TD2.1 804 * TD2.2 805 * TD1.1 806 * etc. 807 * 808 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 809 */ 810 811 812 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 813 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 814 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 815 uhci_dump_qhs(sqh->hlink); 816 else 817 DPRINTF(("No QH\n")); 818 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 819 820 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 821 uhci_dump_tds(sqh->elink); 822 else 823 DPRINTF(("No TD\n")); 824 } 825 826 void 827 uhci_dump_tds(uhci_soft_td_t *std) 828 { 829 uhci_soft_td_t *td; 830 int stop; 831 832 for(td = std; td != NULL; td = td->link.std) { 833 uhci_dump_td(td); 834 835 /* 836 * Check whether the link pointer in this TD marks 837 * the link pointer as end of queue. This avoids 838 * printing the free list in case the queue/TD has 839 * already been moved there (seatbelt). 840 */ 841 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 842 sizeof(td->td.td_link), 843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 844 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 845 le32toh(td->td.td_link) == 0); 846 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 847 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 848 if (stop) 849 break; 850 } 851 } 852 853 Static void 854 uhci_dump_ii(uhci_intr_info_t *ii) 855 { 856 usbd_pipe_handle pipe; 857 usb_endpoint_descriptor_t *ed; 858 usbd_device_handle dev; 859 860 #ifdef DIAGNOSTIC 861 #define DONE ii->isdone 862 #else 863 #define DONE 0 864 #endif 865 if (ii == NULL) { 866 printf("ii NULL\n"); 867 return; 868 } 869 if (ii->xfer == NULL) { 870 printf("ii %p: done=%d xfer=NULL\n", 871 ii, DONE); 872 return; 873 } 874 pipe = ii->xfer->ux_pipe; 875 if (pipe == NULL) { 876 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 877 ii, DONE, ii->xfer); 878 return; 879 } 880 if (pipe->up_endpoint == NULL) { 881 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 882 ii, DONE, ii->xfer, pipe); 883 return; 884 } 885 if (pipe->up_dev == NULL) { 886 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 887 ii, DONE, ii->xfer, pipe); 888 return; 889 } 890 ed = pipe->up_endpoint->ue_edesc; 891 dev = pipe->up_dev; 892 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 893 ii, DONE, ii->xfer, dev, 894 UGETW(dev->ud_ddesc.idVendor), 895 UGETW(dev->ud_ddesc.idProduct), 896 dev->ud_addr, pipe, 897 ed->bEndpointAddress, ed->bmAttributes); 898 #undef DONE 899 } 900 901 void uhci_dump_iis(struct uhci_softc *sc); 902 void 903 uhci_dump_iis(struct uhci_softc *sc) 904 { 905 uhci_intr_info_t *ii; 906 907 printf("intr_info list:\n"); 908 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 909 uhci_dump_ii(ii); 910 } 911 912 void iidump(void); 913 void iidump(void) { uhci_dump_iis(thesc); } 914 915 #endif 916 917 /* 918 * This routine is executed periodically and simulates interrupts 919 * from the root controller interrupt pipe for port status change. 920 */ 921 void 922 uhci_poll_hub(void *addr) 923 { 924 usbd_xfer_handle xfer = addr; 925 usbd_pipe_handle pipe = xfer->ux_pipe; 926 uhci_softc_t *sc; 927 u_char *p; 928 929 DPRINTFN(20, ("uhci_poll_hub\n")); 930 931 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 932 return; /* device has detached */ 933 sc = pipe->up_dev->ud_bus->ub_hcpriv; 934 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 935 936 p = xfer->ux_buf; 937 p[0] = 0; 938 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 939 p[0] |= 1<<1; 940 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 941 p[0] |= 1<<2; 942 if (p[0] == 0) 943 /* No change, try again in a while */ 944 return; 945 946 xfer->ux_actlen = 1; 947 xfer->ux_status = USBD_NORMAL_COMPLETION; 948 mutex_enter(&sc->sc_lock); 949 usb_transfer_complete(xfer); 950 mutex_exit(&sc->sc_lock); 951 } 952 953 void 954 uhci_root_intr_done(usbd_xfer_handle xfer) 955 { 956 } 957 958 /* 959 * Let the last QH loop back to the high speed control transfer QH. 960 * This is what intel calls "bandwidth reclamation" and improves 961 * USB performance a lot for some devices. 962 * If we are already looping, just count it. 963 */ 964 void 965 uhci_add_loop(uhci_softc_t *sc) 966 { 967 #ifdef UHCI_DEBUG 968 if (uhcinoloop) 969 return; 970 #endif 971 if (++sc->sc_loops == 1) { 972 DPRINTFN(5,("uhci_start_loop: add\n")); 973 /* Note, we don't loop back the soft pointer. */ 974 sc->sc_last_qh->qh.qh_hlink = 975 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 976 usb_syncmem(&sc->sc_last_qh->dma, 977 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 978 sizeof(sc->sc_last_qh->qh.qh_hlink), 979 BUS_DMASYNC_PREWRITE); 980 } 981 } 982 983 void 984 uhci_rem_loop(uhci_softc_t *sc) 985 { 986 #ifdef UHCI_DEBUG 987 if (uhcinoloop) 988 return; 989 #endif 990 if (--sc->sc_loops == 0) { 991 DPRINTFN(5,("uhci_end_loop: remove\n")); 992 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 993 usb_syncmem(&sc->sc_last_qh->dma, 994 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 995 sizeof(sc->sc_last_qh->qh.qh_hlink), 996 BUS_DMASYNC_PREWRITE); 997 } 998 } 999 1000 /* Add high speed control QH, called with lock held. */ 1001 void 1002 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1003 { 1004 uhci_soft_qh_t *eqh; 1005 1006 KASSERT(mutex_owned(&sc->sc_lock)); 1007 1008 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1009 eqh = sc->sc_hctl_end; 1010 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1011 sizeof(eqh->qh.qh_hlink), 1012 BUS_DMASYNC_POSTWRITE); 1013 sqh->hlink = eqh->hlink; 1014 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1015 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1016 BUS_DMASYNC_PREWRITE); 1017 eqh->hlink = sqh; 1018 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1019 sc->sc_hctl_end = sqh; 1020 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1021 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1022 #ifdef UHCI_CTL_LOOP 1023 uhci_add_loop(sc); 1024 #endif 1025 } 1026 1027 /* Remove high speed control QH, called with lock held. */ 1028 void 1029 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1030 { 1031 uhci_soft_qh_t *pqh; 1032 uint32_t elink; 1033 1034 KASSERT(mutex_owned(&sc->sc_lock)); 1035 1036 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1037 #ifdef UHCI_CTL_LOOP 1038 uhci_rem_loop(sc); 1039 #endif 1040 /* 1041 * The T bit should be set in the elink of the QH so that the HC 1042 * doesn't follow the pointer. This condition may fail if the 1043 * the transferred packet was short so that the QH still points 1044 * at the last used TD. 1045 * In this case we set the T bit and wait a little for the HC 1046 * to stop looking at the TD. 1047 * Note that if the TD chain is large enough, the controller 1048 * may still be looking at the chain at the end of this function. 1049 * uhci_free_std_chain() will make sure the controller stops 1050 * looking at it quickly, but until then we should not change 1051 * sqh->hlink. 1052 */ 1053 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1054 sizeof(sqh->qh.qh_elink), 1055 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1056 elink = le32toh(sqh->qh.qh_elink); 1057 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1058 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1059 if (!(elink & UHCI_PTR_T)) { 1060 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1061 usb_syncmem(&sqh->dma, 1062 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1063 sizeof(sqh->qh.qh_elink), 1064 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1065 delay(UHCI_QH_REMOVE_DELAY); 1066 } 1067 1068 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1069 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1070 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1071 pqh->hlink = sqh->hlink; 1072 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1073 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1074 sizeof(pqh->qh.qh_hlink), 1075 BUS_DMASYNC_PREWRITE); 1076 delay(UHCI_QH_REMOVE_DELAY); 1077 if (sc->sc_hctl_end == sqh) 1078 sc->sc_hctl_end = pqh; 1079 } 1080 1081 /* Add low speed control QH, called with lock held. */ 1082 void 1083 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1084 { 1085 uhci_soft_qh_t *eqh; 1086 1087 KASSERT(mutex_owned(&sc->sc_lock)); 1088 1089 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1090 eqh = sc->sc_lctl_end; 1091 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1092 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1093 sqh->hlink = eqh->hlink; 1094 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1095 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1096 BUS_DMASYNC_PREWRITE); 1097 eqh->hlink = sqh; 1098 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1099 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1100 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1101 sc->sc_lctl_end = sqh; 1102 } 1103 1104 /* Remove low speed control QH, called with lock held. */ 1105 void 1106 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1107 { 1108 uhci_soft_qh_t *pqh; 1109 uint32_t elink; 1110 1111 KASSERT(mutex_owned(&sc->sc_lock)); 1112 1113 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1114 /* See comment in uhci_remove_hs_ctrl() */ 1115 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1116 sizeof(sqh->qh.qh_elink), 1117 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1118 elink = le32toh(sqh->qh.qh_elink); 1119 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1120 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1121 if (!(elink & UHCI_PTR_T)) { 1122 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1123 usb_syncmem(&sqh->dma, 1124 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1125 sizeof(sqh->qh.qh_elink), 1126 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1127 delay(UHCI_QH_REMOVE_DELAY); 1128 } 1129 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1131 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1132 pqh->hlink = sqh->hlink; 1133 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1134 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1135 sizeof(pqh->qh.qh_hlink), 1136 BUS_DMASYNC_PREWRITE); 1137 delay(UHCI_QH_REMOVE_DELAY); 1138 if (sc->sc_lctl_end == sqh) 1139 sc->sc_lctl_end = pqh; 1140 } 1141 1142 /* Add bulk QH, called with lock held. */ 1143 void 1144 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1145 { 1146 uhci_soft_qh_t *eqh; 1147 1148 KASSERT(mutex_owned(&sc->sc_lock)); 1149 1150 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1151 eqh = sc->sc_bulk_end; 1152 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1153 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1154 sqh->hlink = eqh->hlink; 1155 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1156 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1157 BUS_DMASYNC_PREWRITE); 1158 eqh->hlink = sqh; 1159 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1160 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1161 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1162 sc->sc_bulk_end = sqh; 1163 uhci_add_loop(sc); 1164 } 1165 1166 /* Remove bulk QH, called with lock held. */ 1167 void 1168 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1169 { 1170 uhci_soft_qh_t *pqh; 1171 1172 KASSERT(mutex_owned(&sc->sc_lock)); 1173 1174 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1175 uhci_rem_loop(sc); 1176 /* See comment in uhci_remove_hs_ctrl() */ 1177 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1178 sizeof(sqh->qh.qh_elink), 1179 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1180 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1181 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1182 usb_syncmem(&sqh->dma, 1183 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1184 sizeof(sqh->qh.qh_elink), 1185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1186 delay(UHCI_QH_REMOVE_DELAY); 1187 } 1188 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1189 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1190 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1191 pqh->hlink = sqh->hlink; 1192 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1193 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1194 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1195 delay(UHCI_QH_REMOVE_DELAY); 1196 if (sc->sc_bulk_end == sqh) 1197 sc->sc_bulk_end = pqh; 1198 } 1199 1200 Static int uhci_intr1(uhci_softc_t *); 1201 1202 int 1203 uhci_intr(void *arg) 1204 { 1205 uhci_softc_t *sc = arg; 1206 int ret = 0; 1207 1208 mutex_spin_enter(&sc->sc_intr_lock); 1209 1210 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1211 goto done; 1212 1213 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1214 #ifdef DIAGNOSTIC 1215 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1216 #endif 1217 goto done; 1218 } 1219 1220 ret = uhci_intr1(sc); 1221 1222 done: 1223 mutex_spin_exit(&sc->sc_intr_lock); 1224 return ret; 1225 } 1226 1227 int 1228 uhci_intr1(uhci_softc_t *sc) 1229 { 1230 int status; 1231 int ack; 1232 1233 #ifdef UHCI_DEBUG 1234 if (uhcidebug > 15) { 1235 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1236 uhci_dumpregs(sc); 1237 } 1238 #endif 1239 1240 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1241 1242 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1243 if (status == 0) /* The interrupt was not for us. */ 1244 return 0; 1245 1246 if (sc->sc_suspend != PWR_RESUME) { 1247 #ifdef DIAGNOSTIC 1248 printf("%s: interrupt while not operating ignored\n", 1249 device_xname(sc->sc_dev)); 1250 #endif 1251 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1252 return 0; 1253 } 1254 1255 ack = 0; 1256 if (status & UHCI_STS_USBINT) 1257 ack |= UHCI_STS_USBINT; 1258 if (status & UHCI_STS_USBEI) 1259 ack |= UHCI_STS_USBEI; 1260 if (status & UHCI_STS_RD) { 1261 ack |= UHCI_STS_RD; 1262 #ifdef UHCI_DEBUG 1263 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1264 #endif 1265 } 1266 if (status & UHCI_STS_HSE) { 1267 ack |= UHCI_STS_HSE; 1268 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1269 } 1270 if (status & UHCI_STS_HCPE) { 1271 ack |= UHCI_STS_HCPE; 1272 printf("%s: host controller process error\n", 1273 device_xname(sc->sc_dev)); 1274 } 1275 1276 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1277 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1278 /* no acknowledge needed */ 1279 if (!sc->sc_dying) { 1280 printf("%s: host controller halted\n", 1281 device_xname(sc->sc_dev)); 1282 #ifdef UHCI_DEBUG 1283 uhci_dump_all(sc); 1284 #endif 1285 } 1286 sc->sc_dying = 1; 1287 } 1288 1289 if (!ack) 1290 return 0; /* nothing to acknowledge */ 1291 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1292 1293 usb_schedsoftintr(&sc->sc_bus); 1294 1295 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1296 1297 return 1; 1298 } 1299 1300 void 1301 uhci_softintr(void *v) 1302 { 1303 struct usbd_bus *bus = v; 1304 uhci_softc_t *sc = bus->ub_hcpriv; 1305 uhci_intr_info_t *ii, *nextii; 1306 1307 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1308 1309 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1310 1311 /* 1312 * Interrupts on UHCI really suck. When the host controller 1313 * interrupts because a transfer is completed there is no 1314 * way of knowing which transfer it was. You can scan down 1315 * the TDs and QHs of the previous frame to limit the search, 1316 * but that assumes that the interrupt was not delayed by more 1317 * than 1 ms, which may not always be true (e.g. after debug 1318 * output on a slow console). 1319 * We scan all interrupt descriptors to see if any have 1320 * completed. 1321 */ 1322 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1323 nextii = LIST_NEXT(ii, list); 1324 uhci_check_intr(sc, ii); 1325 } 1326 1327 if (sc->sc_softwake) { 1328 sc->sc_softwake = 0; 1329 cv_broadcast(&sc->sc_softwake_cv); 1330 } 1331 } 1332 1333 /* Check for an interrupt. */ 1334 void 1335 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1336 { 1337 uhci_soft_td_t *std, *lstd; 1338 uint32_t status; 1339 1340 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1341 #ifdef DIAGNOSTIC 1342 if (ii == NULL) { 1343 printf("uhci_check_intr: no ii? %p\n", ii); 1344 return; 1345 } 1346 #endif 1347 if (ii->xfer->ux_status == USBD_CANCELLED || 1348 ii->xfer->ux_status == USBD_TIMEOUT) { 1349 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1350 return; 1351 } 1352 1353 if (ii->stdstart == NULL) 1354 return; 1355 lstd = ii->stdend; 1356 #ifdef DIAGNOSTIC 1357 if (lstd == NULL) { 1358 printf("uhci_check_intr: std==0\n"); 1359 return; 1360 } 1361 #endif 1362 usb_syncmem(&lstd->dma, 1363 lstd->offs + offsetof(uhci_td_t, td_status), 1364 sizeof(lstd->td.td_status), 1365 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1366 status = le32toh(lstd->td.td_status); 1367 usb_syncmem(&lstd->dma, 1368 lstd->offs + offsetof(uhci_td_t, td_status), 1369 sizeof(lstd->td.td_status), 1370 BUS_DMASYNC_PREREAD); 1371 1372 /* If the last TD is not marked active we can complete */ 1373 if (!(status & UHCI_TD_ACTIVE)) { 1374 done: 1375 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1376 callout_stop(&ii->xfer->ux_callout); 1377 uhci_idone(ii); 1378 return; 1379 } 1380 1381 /* 1382 * If the last TD is still active we need to check whether there 1383 * is an error somewhere in the middle, or whether there was a 1384 * short packet (SPD and not ACTIVE). 1385 */ 1386 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1387 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1388 usb_syncmem(&std->dma, 1389 std->offs + offsetof(uhci_td_t, td_status), 1390 sizeof(std->td.td_status), 1391 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1392 status = le32toh(std->td.td_status); 1393 usb_syncmem(&std->dma, 1394 std->offs + offsetof(uhci_td_t, td_status), 1395 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1396 1397 /* If there's an active TD the xfer isn't done. */ 1398 if (status & UHCI_TD_ACTIVE) { 1399 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1400 __func__, ii, std)); 1401 return; 1402 } 1403 1404 /* Any kind of error makes the xfer done. */ 1405 if (status & UHCI_TD_STALLED) 1406 goto done; 1407 1408 /* 1409 * If the data phase of a control transfer is short, we need 1410 * to complete the status stage 1411 */ 1412 usbd_xfer_handle xfer = ii->xfer; 1413 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1414 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1415 1416 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1417 struct uhci_pipe *upipe = 1418 (struct uhci_pipe *)xfer->ux_pipe; 1419 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1420 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1421 1422 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1423 "phase needs completion\n", __func__, ii, 1424 ii->stdstart)); 1425 1426 sqh->qh.qh_elink = 1427 htole32(stat->physaddr | UHCI_PTR_TD); 1428 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1429 BUS_DMASYNC_PREWRITE); 1430 break; 1431 } 1432 1433 /* We want short packets, and it is short: it's done */ 1434 usb_syncmem(&std->dma, 1435 std->offs + offsetof(uhci_td_t, td_token), 1436 sizeof(std->td.td_token), 1437 BUS_DMASYNC_POSTWRITE); 1438 1439 if ((status & UHCI_TD_SPD) && 1440 UHCI_TD_GET_ACTLEN(status) < 1441 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1442 goto done; 1443 } 1444 } 1445 } 1446 1447 /* Called with USB lock held. */ 1448 void 1449 uhci_idone(uhci_intr_info_t *ii) 1450 { 1451 usbd_xfer_handle xfer = ii->xfer; 1452 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1453 #ifdef DIAGNOSTIC 1454 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1455 #endif 1456 uhci_soft_td_t *std; 1457 uint32_t status = 0, nstatus; 1458 int actlen; 1459 1460 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1461 1462 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1463 #ifdef DIAGNOSTIC 1464 { 1465 /* XXX SMP? */ 1466 int s = splhigh(); 1467 if (ii->isdone) { 1468 splx(s); 1469 #ifdef UHCI_DEBUG 1470 printf("uhci_idone: ii is done!\n "); 1471 uhci_dump_ii(ii); 1472 #else 1473 printf("uhci_idone: ii=%p is done!\n", ii); 1474 #endif 1475 return; 1476 } 1477 ii->isdone = 1; 1478 splx(s); 1479 } 1480 #endif 1481 1482 if (xfer->ux_nframes != 0) { 1483 /* Isoc transfer, do things differently. */ 1484 uhci_soft_td_t **stds = upipe->u.iso.stds; 1485 int i, n, nframes, len; 1486 1487 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1488 1489 nframes = xfer->ux_nframes; 1490 actlen = 0; 1491 n = UXFER(xfer)->curframe; 1492 for (i = 0; i < nframes; i++) { 1493 std = stds[n]; 1494 #ifdef UHCI_DEBUG 1495 if (uhcidebug > 5) { 1496 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1497 uhci_dump_td(std); 1498 } 1499 #endif 1500 if (++n >= UHCI_VFRAMELIST_COUNT) 1501 n = 0; 1502 usb_syncmem(&std->dma, 1503 std->offs + offsetof(uhci_td_t, td_status), 1504 sizeof(std->td.td_status), 1505 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1506 status = le32toh(std->td.td_status); 1507 len = UHCI_TD_GET_ACTLEN(status); 1508 xfer->ux_frlengths[i] = len; 1509 actlen += len; 1510 } 1511 upipe->u.iso.inuse -= nframes; 1512 xfer->ux_actlen = actlen; 1513 xfer->ux_status = USBD_NORMAL_COMPLETION; 1514 goto end; 1515 } 1516 1517 #ifdef UHCI_DEBUG 1518 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1519 ii, xfer, upipe)); 1520 if (uhcidebug > 10) 1521 uhci_dump_tds(ii->stdstart); 1522 #endif 1523 1524 /* The transfer is done, compute actual length and status. */ 1525 actlen = 0; 1526 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1527 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1528 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1529 nstatus = le32toh(std->td.td_status); 1530 if (nstatus & UHCI_TD_ACTIVE) 1531 break; 1532 1533 status = nstatus; 1534 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1535 UHCI_TD_PID_SETUP) 1536 actlen += UHCI_TD_GET_ACTLEN(status); 1537 else { 1538 /* 1539 * UHCI will report CRCTO in addition to a STALL or NAK 1540 * for a SETUP transaction. See section 3.2.2, "TD 1541 * CONTROL AND STATUS". 1542 */ 1543 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1544 status &= ~UHCI_TD_CRCTO; 1545 } 1546 } 1547 /* If there are left over TDs we need to update the toggle. */ 1548 if (std != NULL) 1549 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1550 1551 status &= UHCI_TD_ERROR; 1552 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1553 actlen, status)); 1554 xfer->ux_actlen = actlen; 1555 if (status != 0) { 1556 #ifdef UHCI_DEBUG 1557 char sbuf[128]; 1558 1559 snprintb(sbuf, sizeof(sbuf), 1560 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1561 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status); 1562 1563 DPRINTFN((status == UHCI_TD_STALLED)*10, 1564 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1565 "status 0x%s\n", 1566 xfer->ux_pipe->up_dev->ud_addr, 1567 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1568 sbuf)); 1569 #endif 1570 1571 if (status == UHCI_TD_STALLED) 1572 xfer->ux_status = USBD_STALLED; 1573 else 1574 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1575 } else { 1576 xfer->ux_status = USBD_NORMAL_COMPLETION; 1577 } 1578 1579 end: 1580 usb_transfer_complete(xfer); 1581 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1582 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1583 } 1584 1585 /* 1586 * Called when a request does not complete. 1587 */ 1588 void 1589 uhci_timeout(void *addr) 1590 { 1591 uhci_intr_info_t *ii = addr; 1592 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1593 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe; 1594 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1595 1596 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1597 1598 if (sc->sc_dying) { 1599 mutex_enter(&sc->sc_lock); 1600 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1601 mutex_exit(&sc->sc_lock); 1602 return; 1603 } 1604 1605 /* Execute the abort in a process context. */ 1606 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1607 USB_TASKQ_MPSAFE); 1608 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1609 USB_TASKQ_HC); 1610 } 1611 1612 void 1613 uhci_timeout_task(void *addr) 1614 { 1615 usbd_xfer_handle xfer = addr; 1616 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1617 1618 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1619 1620 mutex_enter(&sc->sc_lock); 1621 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1622 mutex_exit(&sc->sc_lock); 1623 } 1624 1625 /* 1626 * Wait here until controller claims to have an interrupt. 1627 * Then call uhci_intr and return. Use timeout to avoid waiting 1628 * too long. 1629 * Only used during boot when interrupts are not enabled yet. 1630 */ 1631 void 1632 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1633 { 1634 int timo = xfer->ux_timeout; 1635 uhci_intr_info_t *ii; 1636 1637 mutex_enter(&sc->sc_lock); 1638 1639 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1640 1641 xfer->ux_status = USBD_IN_PROGRESS; 1642 for (; timo >= 0; timo--) { 1643 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1644 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1645 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1646 mutex_spin_enter(&sc->sc_intr_lock); 1647 uhci_intr1(sc); 1648 mutex_spin_exit(&sc->sc_intr_lock); 1649 if (xfer->ux_status != USBD_IN_PROGRESS) 1650 goto done; 1651 } 1652 } 1653 1654 /* Timeout */ 1655 DPRINTF(("uhci_waitintr: timeout\n")); 1656 for (ii = LIST_FIRST(&sc->sc_intrhead); 1657 ii != NULL && ii->xfer != xfer; 1658 ii = LIST_NEXT(ii, list)) 1659 ; 1660 #ifdef DIAGNOSTIC 1661 if (ii == NULL) 1662 panic("uhci_waitintr: lost intr_info"); 1663 #endif 1664 uhci_idone(ii); 1665 1666 done: 1667 mutex_exit(&sc->sc_lock); 1668 } 1669 1670 void 1671 uhci_poll(struct usbd_bus *bus) 1672 { 1673 uhci_softc_t *sc = bus->ub_hcpriv; 1674 1675 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1676 mutex_spin_enter(&sc->sc_intr_lock); 1677 uhci_intr1(sc); 1678 mutex_spin_exit(&sc->sc_intr_lock); 1679 } 1680 } 1681 1682 void 1683 uhci_reset(uhci_softc_t *sc) 1684 { 1685 int n; 1686 1687 UHCICMD(sc, UHCI_CMD_HCRESET); 1688 /* The reset bit goes low when the controller is done. */ 1689 for (n = 0; n < UHCI_RESET_TIMEOUT && 1690 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1691 usb_delay_ms(&sc->sc_bus, 1); 1692 if (n >= UHCI_RESET_TIMEOUT) 1693 printf("%s: controller did not reset\n", 1694 device_xname(sc->sc_dev)); 1695 } 1696 1697 usbd_status 1698 uhci_run(uhci_softc_t *sc, int run, int locked) 1699 { 1700 int n, running; 1701 uint16_t cmd; 1702 1703 run = run != 0; 1704 if (!locked) 1705 mutex_spin_enter(&sc->sc_intr_lock); 1706 DPRINTF(("uhci_run: setting run=%d\n", run)); 1707 cmd = UREAD2(sc, UHCI_CMD); 1708 if (run) 1709 cmd |= UHCI_CMD_RS; 1710 else 1711 cmd &= ~UHCI_CMD_RS; 1712 UHCICMD(sc, cmd); 1713 for(n = 0; n < 10; n++) { 1714 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1715 /* return when we've entered the state we want */ 1716 if (run == running) { 1717 if (!locked) 1718 mutex_spin_exit(&sc->sc_intr_lock); 1719 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1720 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1721 return USBD_NORMAL_COMPLETION; 1722 } 1723 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1724 } 1725 if (!locked) 1726 mutex_spin_exit(&sc->sc_intr_lock); 1727 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1728 run ? "start" : "stop"); 1729 return USBD_IOERROR; 1730 } 1731 1732 /* 1733 * Memory management routines. 1734 * uhci_alloc_std allocates TDs 1735 * uhci_alloc_sqh allocates QHs 1736 * These two routines do their own free list management, 1737 * partly for speed, partly because allocating DMAable memory 1738 * has page size granularaity so much memory would be wasted if 1739 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1740 */ 1741 1742 uhci_soft_td_t * 1743 uhci_alloc_std(uhci_softc_t *sc) 1744 { 1745 uhci_soft_td_t *std; 1746 usbd_status err; 1747 int i, offs; 1748 usb_dma_t dma; 1749 1750 if (sc->sc_freetds == NULL) { 1751 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1752 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1753 UHCI_TD_ALIGN, &dma); 1754 if (err) 1755 return 0; 1756 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1757 offs = i * UHCI_STD_SIZE; 1758 std = KERNADDR(&dma, offs); 1759 std->physaddr = DMAADDR(&dma, offs); 1760 std->dma = dma; 1761 std->offs = offs; 1762 std->link.std = sc->sc_freetds; 1763 sc->sc_freetds = std; 1764 } 1765 } 1766 std = sc->sc_freetds; 1767 sc->sc_freetds = std->link.std; 1768 memset(&std->td, 0, sizeof(uhci_td_t)); 1769 return std; 1770 } 1771 1772 void 1773 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1774 { 1775 #ifdef DIAGNOSTIC 1776 #define TD_IS_FREE 0x12345678 1777 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1778 printf("uhci_free_std: freeing free TD %p\n", std); 1779 return; 1780 } 1781 std->td.td_token = htole32(TD_IS_FREE); 1782 #endif 1783 std->link.std = sc->sc_freetds; 1784 sc->sc_freetds = std; 1785 } 1786 1787 uhci_soft_qh_t * 1788 uhci_alloc_sqh(uhci_softc_t *sc) 1789 { 1790 uhci_soft_qh_t *sqh; 1791 usbd_status err; 1792 int i, offs; 1793 usb_dma_t dma; 1794 1795 if (sc->sc_freeqhs == NULL) { 1796 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1797 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1798 UHCI_QH_ALIGN, &dma); 1799 if (err) 1800 return 0; 1801 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1802 offs = i * UHCI_SQH_SIZE; 1803 sqh = KERNADDR(&dma, offs); 1804 sqh->physaddr = DMAADDR(&dma, offs); 1805 sqh->dma = dma; 1806 sqh->offs = offs; 1807 sqh->hlink = sc->sc_freeqhs; 1808 sc->sc_freeqhs = sqh; 1809 } 1810 } 1811 sqh = sc->sc_freeqhs; 1812 sc->sc_freeqhs = sqh->hlink; 1813 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1814 return sqh; 1815 } 1816 1817 void 1818 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1819 { 1820 sqh->hlink = sc->sc_freeqhs; 1821 sc->sc_freeqhs = sqh; 1822 } 1823 1824 void 1825 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1826 uhci_soft_td_t *stdend) 1827 { 1828 uhci_soft_td_t *p; 1829 uint32_t td_link; 1830 1831 /* 1832 * to avoid race condition with the controller which may be looking 1833 * at this chain, we need to first invalidate all links, and 1834 * then wait for the controller to move to another queue 1835 */ 1836 for (p = std; p != stdend; p = p->link.std) { 1837 usb_syncmem(&p->dma, 1838 p->offs + offsetof(uhci_td_t, td_link), 1839 sizeof(p->td.td_link), 1840 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1841 td_link = le32toh(p->td.td_link); 1842 usb_syncmem(&p->dma, 1843 p->offs + offsetof(uhci_td_t, td_link), 1844 sizeof(p->td.td_link), 1845 BUS_DMASYNC_PREREAD); 1846 if ((td_link & UHCI_PTR_T) == 0) { 1847 p->td.td_link = htole32(UHCI_PTR_T); 1848 usb_syncmem(&p->dma, 1849 p->offs + offsetof(uhci_td_t, td_link), 1850 sizeof(p->td.td_link), 1851 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1852 } 1853 } 1854 delay(UHCI_QH_REMOVE_DELAY); 1855 1856 for (; std != stdend; std = p) { 1857 p = std->link.std; 1858 uhci_free_std(sc, std); 1859 } 1860 } 1861 1862 usbd_status 1863 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1864 int rd, uint16_t flags, usb_dma_t *dma, 1865 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1866 { 1867 uhci_soft_td_t *p, *lastp; 1868 uhci_physaddr_t lastlink; 1869 int i, ntd, l, tog, maxp; 1870 uint32_t status; 1871 int addr = upipe->pipe.up_dev->ud_addr; 1872 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1873 1874 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1875 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1876 upipe->pipe.up_dev->ud_speed, flags)); 1877 1878 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1879 1880 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1881 if (maxp == 0) { 1882 printf("uhci_alloc_std_chain: maxp=0\n"); 1883 return USBD_INVAL; 1884 } 1885 ntd = (len + maxp - 1) / maxp; 1886 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1887 ntd++; 1888 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1889 if (ntd == 0) { 1890 *sp = *ep = 0; 1891 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1892 return USBD_NORMAL_COMPLETION; 1893 } 1894 tog = upipe->nexttoggle; 1895 if (ntd % 2 == 0) 1896 tog ^= 1; 1897 upipe->nexttoggle = tog ^ 1; 1898 lastp = NULL; 1899 lastlink = UHCI_PTR_T; 1900 ntd--; 1901 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1902 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1903 status |= UHCI_TD_LS; 1904 if (flags & USBD_SHORT_XFER_OK) 1905 status |= UHCI_TD_SPD; 1906 usb_syncmem(dma, 0, len, 1907 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1908 for (i = ntd; i >= 0; i--) { 1909 p = uhci_alloc_std(sc); 1910 if (p == NULL) { 1911 KASSERT(lastp != NULL); 1912 uhci_free_std_chain(sc, lastp, NULL); 1913 return USBD_NOMEM; 1914 } 1915 p->link.std = lastp; 1916 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1917 lastp = p; 1918 lastlink = p->physaddr; 1919 p->td.td_status = htole32(status); 1920 if (i == ntd) { 1921 /* last TD */ 1922 l = len % maxp; 1923 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1924 l = maxp; 1925 *ep = p; 1926 } else 1927 l = maxp; 1928 p->td.td_token = 1929 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1930 UHCI_TD_OUT(l, endpt, addr, tog)); 1931 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1932 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1933 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1934 tog ^= 1; 1935 } 1936 *sp = lastp; 1937 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1938 upipe->nexttoggle)); 1939 return USBD_NORMAL_COMPLETION; 1940 } 1941 1942 void 1943 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1944 { 1945 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1946 upipe->nexttoggle = 0; 1947 } 1948 1949 void 1950 uhci_noop(usbd_pipe_handle pipe) 1951 { 1952 } 1953 1954 usbd_status 1955 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1956 { 1957 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1958 usbd_status err; 1959 1960 /* Insert last in queue. */ 1961 mutex_enter(&sc->sc_lock); 1962 err = usb_insert_transfer(xfer); 1963 mutex_exit(&sc->sc_lock); 1964 if (err) 1965 return err; 1966 1967 /* 1968 * Pipe isn't running (otherwise err would be USBD_INPROG), 1969 * so start it first. 1970 */ 1971 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1972 } 1973 1974 usbd_status 1975 uhci_device_bulk_start(usbd_xfer_handle xfer) 1976 { 1977 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1978 usbd_device_handle dev = upipe->pipe.up_dev; 1979 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1980 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1981 uhci_soft_td_t *data, *dataend; 1982 uhci_soft_qh_t *sqh; 1983 usbd_status err; 1984 int len, isread, endpt; 1985 1986 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1987 xfer, xfer->ux_length, xfer->ux_flags, ii)); 1988 1989 if (sc->sc_dying) 1990 return USBD_IOERROR; 1991 1992 #ifdef DIAGNOSTIC 1993 if (xfer->ux_rqflags & URQ_REQUEST) 1994 panic("uhci_device_bulk_transfer: a request"); 1995 #endif 1996 1997 mutex_enter(&sc->sc_lock); 1998 1999 len = xfer->ux_length; 2000 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2001 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2002 sqh = upipe->u.bulk.sqh; 2003 2004 upipe->u.bulk.isread = isread; 2005 upipe->u.bulk.length = len; 2006 2007 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2008 &xfer->ux_dmabuf, &data, &dataend); 2009 if (err) { 2010 mutex_exit(&sc->sc_lock); 2011 return err; 2012 } 2013 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2014 usb_syncmem(&dataend->dma, 2015 dataend->offs + offsetof(uhci_td_t, td_status), 2016 sizeof(dataend->td.td_status), 2017 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2018 2019 2020 #ifdef UHCI_DEBUG 2021 if (uhcidebug > 8) { 2022 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2023 uhci_dump_tds(data); 2024 } 2025 #endif 2026 2027 /* Set up interrupt info. */ 2028 ii->xfer = xfer; 2029 ii->stdstart = data; 2030 ii->stdend = dataend; 2031 #ifdef DIAGNOSTIC 2032 if (!ii->isdone) { 2033 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2034 } 2035 ii->isdone = 0; 2036 #endif 2037 2038 sqh->elink = data; 2039 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2040 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2041 2042 uhci_add_bulk(sc, sqh); 2043 uhci_add_intr_info(sc, ii); 2044 2045 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2046 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2047 uhci_timeout, ii); 2048 } 2049 xfer->ux_status = USBD_IN_PROGRESS; 2050 2051 #ifdef UHCI_DEBUG 2052 if (uhcidebug > 10) { 2053 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2054 uhci_dump_tds(data); 2055 } 2056 #endif 2057 2058 if (sc->sc_bus.ub_usepolling) 2059 uhci_waitintr(sc, xfer); 2060 2061 mutex_exit(&sc->sc_lock); 2062 return USBD_IN_PROGRESS; 2063 } 2064 2065 /* Abort a device bulk request. */ 2066 void 2067 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2068 { 2069 #ifdef DIAGNOSTIC 2070 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2071 #endif 2072 2073 KASSERT(mutex_owned(&sc->sc_lock)); 2074 2075 DPRINTF(("uhci_device_bulk_abort:\n")); 2076 uhci_abort_xfer(xfer, USBD_CANCELLED); 2077 } 2078 2079 /* 2080 * Abort a device request. 2081 * If this routine is called at splusb() it guarantees that the request 2082 * will be removed from the hardware scheduling and that the callback 2083 * for it will be called with USBD_CANCELLED status. 2084 * It's impossible to guarantee that the requested transfer will not 2085 * have happened since the hardware runs concurrently. 2086 * If the transaction has already happened we rely on the ordinary 2087 * interrupt processing to process it. 2088 * XXX This is most probably wrong. 2089 * XXXMRG this doesn't make sense anymore. 2090 */ 2091 void 2092 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2093 { 2094 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2095 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2096 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2097 uhci_soft_td_t *std; 2098 int wake; 2099 2100 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2101 2102 KASSERT(mutex_owned(&sc->sc_lock)); 2103 ASSERT_SLEEPABLE(); 2104 2105 if (sc->sc_dying) { 2106 /* If we're dying, just do the software part. */ 2107 xfer->ux_status = status; /* make software ignore it */ 2108 callout_stop(&xfer->ux_callout); 2109 usb_transfer_complete(xfer); 2110 return; 2111 } 2112 2113 /* 2114 * If an abort is already in progress then just wait for it to 2115 * complete and return. 2116 */ 2117 if (xfer->ux_hcflags & UXFER_ABORTING) { 2118 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2119 #ifdef DIAGNOSTIC 2120 if (status == USBD_TIMEOUT) 2121 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2122 #endif 2123 /* Override the status which might be USBD_TIMEOUT. */ 2124 xfer->ux_status = status; 2125 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2126 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2127 while (xfer->ux_hcflags & UXFER_ABORTING) 2128 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2129 goto done; 2130 } 2131 xfer->ux_hcflags |= UXFER_ABORTING; 2132 2133 /* 2134 * Step 1: Make interrupt routine and hardware ignore xfer. 2135 */ 2136 xfer->ux_status = status; /* make software ignore it */ 2137 callout_stop(&xfer->ux_callout); 2138 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2139 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2140 usb_syncmem(&std->dma, 2141 std->offs + offsetof(uhci_td_t, td_status), 2142 sizeof(std->td.td_status), 2143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2144 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2145 usb_syncmem(&std->dma, 2146 std->offs + offsetof(uhci_td_t, td_status), 2147 sizeof(std->td.td_status), 2148 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2149 } 2150 2151 /* 2152 * Step 2: Wait until we know hardware has finished any possible 2153 * use of the xfer. Also make sure the soft interrupt routine 2154 * has run. 2155 */ 2156 /* Hardware finishes in 1ms */ 2157 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2158 sc->sc_softwake = 1; 2159 usb_schedsoftintr(&sc->sc_bus); 2160 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2161 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2162 2163 /* 2164 * Step 3: Execute callback. 2165 */ 2166 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2167 #ifdef DIAGNOSTIC 2168 ii->isdone = 1; 2169 #endif 2170 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2171 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2172 usb_transfer_complete(xfer); 2173 if (wake) 2174 cv_broadcast(&xfer->ux_hccv); 2175 done: 2176 KASSERT(mutex_owned(&sc->sc_lock)); 2177 } 2178 2179 /* Close a device bulk pipe. */ 2180 void 2181 uhci_device_bulk_close(usbd_pipe_handle pipe) 2182 { 2183 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2184 usbd_device_handle dev = upipe->pipe.up_dev; 2185 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2186 2187 KASSERT(mutex_owned(&sc->sc_lock)); 2188 2189 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2190 2191 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2192 } 2193 2194 usbd_status 2195 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2196 { 2197 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2198 usbd_status err; 2199 2200 /* Insert last in queue. */ 2201 mutex_enter(&sc->sc_lock); 2202 err = usb_insert_transfer(xfer); 2203 mutex_exit(&sc->sc_lock); 2204 if (err) 2205 return err; 2206 2207 /* 2208 * Pipe isn't running (otherwise err would be USBD_INPROG), 2209 * so start it first. 2210 */ 2211 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2212 } 2213 2214 usbd_status 2215 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2216 { 2217 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2218 usbd_status err; 2219 2220 if (sc->sc_dying) 2221 return USBD_IOERROR; 2222 2223 #ifdef DIAGNOSTIC 2224 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2225 panic("uhci_device_ctrl_transfer: not a request"); 2226 #endif 2227 2228 mutex_enter(&sc->sc_lock); 2229 err = uhci_device_request(xfer); 2230 mutex_exit(&sc->sc_lock); 2231 if (err) 2232 return err; 2233 2234 if (sc->sc_bus.ub_usepolling) 2235 uhci_waitintr(sc, xfer); 2236 return USBD_IN_PROGRESS; 2237 } 2238 2239 usbd_status 2240 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2241 { 2242 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2243 usbd_status err; 2244 2245 /* Insert last in queue. */ 2246 mutex_enter(&sc->sc_lock); 2247 err = usb_insert_transfer(xfer); 2248 mutex_exit(&sc->sc_lock); 2249 if (err) 2250 return err; 2251 2252 /* 2253 * Pipe isn't running (otherwise err would be USBD_INPROG), 2254 * so start it first. 2255 */ 2256 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2257 } 2258 2259 usbd_status 2260 uhci_device_intr_start(usbd_xfer_handle xfer) 2261 { 2262 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2263 usbd_device_handle dev = upipe->pipe.up_dev; 2264 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2265 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2266 uhci_soft_td_t *data, *dataend; 2267 uhci_soft_qh_t *sqh; 2268 usbd_status err; 2269 int isread, endpt; 2270 int i; 2271 2272 if (sc->sc_dying) 2273 return USBD_IOERROR; 2274 2275 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2276 xfer, xfer->ux_length, xfer->ux_flags)); 2277 2278 #ifdef DIAGNOSTIC 2279 if (xfer->ux_rqflags & URQ_REQUEST) 2280 panic("uhci_device_intr_transfer: a request"); 2281 #endif 2282 2283 mutex_enter(&sc->sc_lock); 2284 2285 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2286 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2287 2288 upipe->u.intr.isread = isread; 2289 2290 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2291 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2292 &dataend); 2293 if (err) { 2294 mutex_exit(&sc->sc_lock); 2295 return err; 2296 } 2297 2298 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2299 usb_syncmem(&dataend->dma, 2300 dataend->offs + offsetof(uhci_td_t, td_status), 2301 sizeof(dataend->td.td_status), 2302 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2303 2304 #ifdef UHCI_DEBUG 2305 if (uhcidebug > 10) { 2306 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2307 uhci_dump_tds(data); 2308 uhci_dump_qh(upipe->u.intr.qhs[0]); 2309 } 2310 #endif 2311 2312 /* Set up interrupt info. */ 2313 ii->xfer = xfer; 2314 ii->stdstart = data; 2315 ii->stdend = dataend; 2316 #ifdef DIAGNOSTIC 2317 if (!ii->isdone) { 2318 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2319 } 2320 ii->isdone = 0; 2321 #endif 2322 2323 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2324 upipe->u.intr.qhs[0])); 2325 for (i = 0; i < upipe->u.intr.npoll; i++) { 2326 sqh = upipe->u.intr.qhs[i]; 2327 sqh->elink = data; 2328 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2329 usb_syncmem(&sqh->dma, 2330 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2331 sizeof(sqh->qh.qh_elink), 2332 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2333 } 2334 uhci_add_intr_info(sc, ii); 2335 xfer->ux_status = USBD_IN_PROGRESS; 2336 mutex_exit(&sc->sc_lock); 2337 2338 #ifdef UHCI_DEBUG 2339 if (uhcidebug > 10) { 2340 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2341 uhci_dump_tds(data); 2342 uhci_dump_qh(upipe->u.intr.qhs[0]); 2343 } 2344 #endif 2345 2346 return USBD_IN_PROGRESS; 2347 } 2348 2349 /* Abort a device control request. */ 2350 void 2351 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2352 { 2353 #ifdef DIAGNOSTIC 2354 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2355 #endif 2356 2357 KASSERT(mutex_owned(&sc->sc_lock)); 2358 2359 DPRINTF(("uhci_device_ctrl_abort:\n")); 2360 uhci_abort_xfer(xfer, USBD_CANCELLED); 2361 } 2362 2363 /* Close a device control pipe. */ 2364 void 2365 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2366 { 2367 } 2368 2369 /* Abort a device interrupt request. */ 2370 void 2371 uhci_device_intr_abort(usbd_xfer_handle xfer) 2372 { 2373 #ifdef DIAGNOSTIC 2374 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2375 #endif 2376 2377 KASSERT(mutex_owned(&sc->sc_lock)); 2378 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2379 2380 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2381 2382 uhci_abort_xfer(xfer, USBD_CANCELLED); 2383 } 2384 2385 /* Close a device interrupt pipe. */ 2386 void 2387 uhci_device_intr_close(usbd_pipe_handle pipe) 2388 { 2389 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2390 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2391 int i, npoll; 2392 2393 KASSERT(mutex_owned(&sc->sc_lock)); 2394 2395 /* Unlink descriptors from controller data structures. */ 2396 npoll = upipe->u.intr.npoll; 2397 for (i = 0; i < npoll; i++) 2398 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2399 2400 /* 2401 * We now have to wait for any activity on the physical 2402 * descriptors to stop. 2403 */ 2404 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2405 2406 for(i = 0; i < npoll; i++) 2407 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2408 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2409 2410 /* XXX free other resources */ 2411 } 2412 2413 usbd_status 2414 uhci_device_request(usbd_xfer_handle xfer) 2415 { 2416 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2417 usb_device_request_t *req = &xfer->ux_request; 2418 usbd_device_handle dev = upipe->pipe.up_dev; 2419 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2420 int addr = dev->ud_addr; 2421 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2422 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2423 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2424 uhci_soft_qh_t *sqh; 2425 int len; 2426 uint32_t ls; 2427 usbd_status err; 2428 int isread; 2429 2430 KASSERT(mutex_owned(&sc->sc_lock)); 2431 2432 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2433 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2434 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2435 UGETW(req->wIndex), UGETW(req->wLength), 2436 addr, endpt)); 2437 2438 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2439 isread = req->bmRequestType & UT_READ; 2440 len = UGETW(req->wLength); 2441 2442 setup = upipe->u.ctl.setup; 2443 stat = upipe->u.ctl.stat; 2444 sqh = upipe->u.ctl.sqh; 2445 2446 /* Set up data transaction */ 2447 if (len != 0) { 2448 upipe->nexttoggle = 1; 2449 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2450 &xfer->ux_dmabuf, &data, &dataend); 2451 if (err) 2452 return err; 2453 next = data; 2454 dataend->link.std = stat; 2455 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2456 usb_syncmem(&dataend->dma, 2457 dataend->offs + offsetof(uhci_td_t, td_link), 2458 sizeof(dataend->td.td_link), 2459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2460 } else { 2461 next = stat; 2462 } 2463 upipe->u.ctl.length = len; 2464 2465 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2466 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2467 2468 setup->link.std = next; 2469 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2470 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2471 UHCI_TD_ACTIVE); 2472 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2473 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2474 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2475 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2476 2477 stat->link.std = NULL; 2478 stat->td.td_link = htole32(UHCI_PTR_T); 2479 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2480 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2481 stat->td.td_token = 2482 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2483 UHCI_TD_IN (0, endpt, addr, 1)); 2484 stat->td.td_buffer = htole32(0); 2485 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2487 2488 #ifdef UHCI_DEBUG 2489 if (uhcidebug > 10) { 2490 DPRINTF(("uhci_device_request: before transfer\n")); 2491 uhci_dump_tds(setup); 2492 } 2493 #endif 2494 2495 /* Set up interrupt info. */ 2496 ii->xfer = xfer; 2497 ii->stdstart = setup; 2498 ii->stdend = stat; 2499 #ifdef DIAGNOSTIC 2500 if (!ii->isdone) { 2501 printf("uhci_device_request: not done, ii=%p\n", ii); 2502 } 2503 ii->isdone = 0; 2504 #endif 2505 2506 sqh->elink = setup; 2507 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2508 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2509 2510 if (dev->ud_speed == USB_SPEED_LOW) 2511 uhci_add_ls_ctrl(sc, sqh); 2512 else 2513 uhci_add_hs_ctrl(sc, sqh); 2514 uhci_add_intr_info(sc, ii); 2515 #ifdef UHCI_DEBUG 2516 if (uhcidebug > 12) { 2517 uhci_soft_td_t *std; 2518 uhci_soft_qh_t *xqh; 2519 uhci_soft_qh_t *sxqh; 2520 int maxqh = 0; 2521 uhci_physaddr_t link; 2522 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2523 for (std = sc->sc_vframes[0].htd, link = 0; 2524 (link & UHCI_PTR_QH) == 0; 2525 std = std->link.std) { 2526 link = le32toh(std->td.td_link); 2527 uhci_dump_td(std); 2528 } 2529 sxqh = (uhci_soft_qh_t *)std; 2530 uhci_dump_qh(sxqh); 2531 for (xqh = sxqh; 2532 xqh != NULL; 2533 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2534 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2535 uhci_dump_qh(xqh); 2536 } 2537 DPRINTF(("Enqueued QH:\n")); 2538 uhci_dump_qh(sqh); 2539 uhci_dump_tds(sqh->elink); 2540 } 2541 #endif 2542 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2543 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2544 uhci_timeout, ii); 2545 } 2546 xfer->ux_status = USBD_IN_PROGRESS; 2547 2548 return USBD_NORMAL_COMPLETION; 2549 } 2550 2551 usbd_status 2552 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2553 { 2554 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2555 usbd_status err; 2556 2557 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2558 2559 /* Put it on our queue, */ 2560 mutex_enter(&sc->sc_lock); 2561 err = usb_insert_transfer(xfer); 2562 mutex_exit(&sc->sc_lock); 2563 2564 /* bail out on error, */ 2565 if (err && err != USBD_IN_PROGRESS) 2566 return err; 2567 2568 /* XXX should check inuse here */ 2569 2570 /* insert into schedule, */ 2571 uhci_device_isoc_enter(xfer); 2572 2573 /* and start if the pipe wasn't running */ 2574 if (!err) 2575 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2576 2577 return err; 2578 } 2579 2580 void 2581 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2582 { 2583 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2584 usbd_device_handle dev = upipe->pipe.up_dev; 2585 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2586 struct iso *iso = &upipe->u.iso; 2587 uhci_soft_td_t *std; 2588 uint32_t buf, len, status, offs; 2589 int i, next, nframes; 2590 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2591 2592 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2593 "nframes=%d\n", 2594 iso->inuse, iso->next, xfer, xfer->ux_nframes)); 2595 2596 if (sc->sc_dying) 2597 return; 2598 2599 if (xfer->ux_status == USBD_IN_PROGRESS) { 2600 /* This request has already been entered into the frame list */ 2601 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2602 /* XXX */ 2603 } 2604 2605 #ifdef DIAGNOSTIC 2606 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2607 printf("uhci_device_isoc_enter: overflow!\n"); 2608 #endif 2609 2610 next = iso->next; 2611 if (next == -1) { 2612 /* Not in use yet, schedule it a few frames ahead. */ 2613 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2614 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2615 } 2616 2617 xfer->ux_status = USBD_IN_PROGRESS; 2618 UXFER(xfer)->curframe = next; 2619 2620 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2621 offs = 0; 2622 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2623 UHCI_TD_ACTIVE | 2624 UHCI_TD_IOS); 2625 nframes = xfer->ux_nframes; 2626 mutex_enter(&sc->sc_lock); 2627 for (i = 0; i < nframes; i++) { 2628 std = iso->stds[next]; 2629 if (++next >= UHCI_VFRAMELIST_COUNT) 2630 next = 0; 2631 len = xfer->ux_frlengths[i]; 2632 std->td.td_buffer = htole32(buf); 2633 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2634 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2635 if (i == nframes - 1) 2636 status |= UHCI_TD_IOC; 2637 std->td.td_status = htole32(status); 2638 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2639 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2640 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2641 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2642 #ifdef UHCI_DEBUG 2643 if (uhcidebug > 5) { 2644 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2645 uhci_dump_td(std); 2646 } 2647 #endif 2648 buf += len; 2649 offs += len; 2650 } 2651 iso->next = next; 2652 iso->inuse += xfer->ux_nframes; 2653 2654 mutex_exit(&sc->sc_lock); 2655 } 2656 2657 usbd_status 2658 uhci_device_isoc_start(usbd_xfer_handle xfer) 2659 { 2660 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2661 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2662 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2663 uhci_soft_td_t *end; 2664 int i; 2665 2666 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2667 2668 mutex_enter(&sc->sc_lock); 2669 2670 if (sc->sc_dying) { 2671 mutex_exit(&sc->sc_lock); 2672 return USBD_IOERROR; 2673 } 2674 2675 #ifdef DIAGNOSTIC 2676 if (xfer->ux_status != USBD_IN_PROGRESS) 2677 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2678 #endif 2679 2680 /* Find the last TD */ 2681 i = UXFER(xfer)->curframe + xfer->ux_nframes; 2682 if (i >= UHCI_VFRAMELIST_COUNT) 2683 i -= UHCI_VFRAMELIST_COUNT; 2684 end = upipe->u.iso.stds[i]; 2685 2686 #ifdef DIAGNOSTIC 2687 if (end == NULL) { 2688 printf("uhci_device_isoc_start: end == NULL\n"); 2689 return USBD_INVAL; 2690 } 2691 #endif 2692 2693 /* Set up interrupt info. */ 2694 ii->xfer = xfer; 2695 ii->stdstart = end; 2696 ii->stdend = end; 2697 #ifdef DIAGNOSTIC 2698 if (!ii->isdone) 2699 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2700 ii->isdone = 0; 2701 #endif 2702 uhci_add_intr_info(sc, ii); 2703 2704 mutex_exit(&sc->sc_lock); 2705 2706 return USBD_IN_PROGRESS; 2707 } 2708 2709 void 2710 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2711 { 2712 #ifdef DIAGNOSTIC 2713 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2714 #endif 2715 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2716 uhci_soft_td_t **stds = upipe->u.iso.stds; 2717 uhci_soft_td_t *std; 2718 int i, n, nframes, maxlen, len; 2719 2720 KASSERT(mutex_owned(&sc->sc_lock)); 2721 2722 /* Transfer is already done. */ 2723 if (xfer->ux_status != USBD_NOT_STARTED && 2724 xfer->ux_status != USBD_IN_PROGRESS) { 2725 return; 2726 } 2727 2728 /* Give xfer the requested abort code. */ 2729 xfer->ux_status = USBD_CANCELLED; 2730 2731 /* make hardware ignore it, */ 2732 nframes = xfer->ux_nframes; 2733 n = UXFER(xfer)->curframe; 2734 maxlen = 0; 2735 for (i = 0; i < nframes; i++) { 2736 std = stds[n]; 2737 usb_syncmem(&std->dma, 2738 std->offs + offsetof(uhci_td_t, td_status), 2739 sizeof(std->td.td_status), 2740 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2741 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2742 usb_syncmem(&std->dma, 2743 std->offs + offsetof(uhci_td_t, td_status), 2744 sizeof(std->td.td_status), 2745 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2746 usb_syncmem(&std->dma, 2747 std->offs + offsetof(uhci_td_t, td_token), 2748 sizeof(std->td.td_token), 2749 BUS_DMASYNC_POSTWRITE); 2750 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2751 if (len > maxlen) 2752 maxlen = len; 2753 if (++n >= UHCI_VFRAMELIST_COUNT) 2754 n = 0; 2755 } 2756 2757 /* and wait until we are sure the hardware has finished. */ 2758 delay(maxlen); 2759 2760 #ifdef DIAGNOSTIC 2761 UXFER(xfer)->iinfo.isdone = 1; 2762 #endif 2763 /* Run callback and remove from interrupt list. */ 2764 usb_transfer_complete(xfer); 2765 2766 KASSERT(mutex_owned(&sc->sc_lock)); 2767 } 2768 2769 void 2770 uhci_device_isoc_close(usbd_pipe_handle pipe) 2771 { 2772 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2773 usbd_device_handle dev = upipe->pipe.up_dev; 2774 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2775 uhci_soft_td_t *std, *vstd; 2776 struct iso *iso; 2777 int i; 2778 2779 KASSERT(mutex_owned(&sc->sc_lock)); 2780 2781 /* 2782 * Make sure all TDs are marked as inactive. 2783 * Wait for completion. 2784 * Unschedule. 2785 * Deallocate. 2786 */ 2787 iso = &upipe->u.iso; 2788 2789 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2790 std = iso->stds[i]; 2791 usb_syncmem(&std->dma, 2792 std->offs + offsetof(uhci_td_t, td_status), 2793 sizeof(std->td.td_status), 2794 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2795 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2796 usb_syncmem(&std->dma, 2797 std->offs + offsetof(uhci_td_t, td_status), 2798 sizeof(std->td.td_status), 2799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2800 } 2801 /* wait for completion */ 2802 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2803 2804 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2805 std = iso->stds[i]; 2806 for (vstd = sc->sc_vframes[i].htd; 2807 vstd != NULL && vstd->link.std != std; 2808 vstd = vstd->link.std) 2809 ; 2810 if (vstd == NULL) { 2811 /*panic*/ 2812 printf("uhci_device_isoc_close: %p not found\n", std); 2813 mutex_exit(&sc->sc_lock); 2814 return; 2815 } 2816 vstd->link = std->link; 2817 usb_syncmem(&std->dma, 2818 std->offs + offsetof(uhci_td_t, td_link), 2819 sizeof(std->td.td_link), 2820 BUS_DMASYNC_POSTWRITE); 2821 vstd->td.td_link = std->td.td_link; 2822 usb_syncmem(&vstd->dma, 2823 vstd->offs + offsetof(uhci_td_t, td_link), 2824 sizeof(vstd->td.td_link), 2825 BUS_DMASYNC_PREWRITE); 2826 uhci_free_std(sc, std); 2827 } 2828 2829 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2830 } 2831 2832 usbd_status 2833 uhci_setup_isoc(usbd_pipe_handle pipe) 2834 { 2835 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2836 usbd_device_handle dev = upipe->pipe.up_dev; 2837 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2838 int addr = upipe->pipe.up_dev->ud_addr; 2839 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2840 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2841 uhci_soft_td_t *std, *vstd; 2842 uint32_t token; 2843 struct iso *iso; 2844 int i; 2845 2846 iso = &upipe->u.iso; 2847 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2848 sizeof (uhci_soft_td_t *), 2849 KM_SLEEP); 2850 if (iso->stds == NULL) 2851 return USBD_NOMEM; 2852 2853 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2854 UHCI_TD_OUT(0, endpt, addr, 0); 2855 2856 mutex_enter(&sc->sc_lock); 2857 2858 /* Allocate the TDs and mark as inactive; */ 2859 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2860 std = uhci_alloc_std(sc); 2861 if (std == 0) 2862 goto bad; 2863 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2864 std->td.td_token = htole32(token); 2865 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2867 iso->stds[i] = std; 2868 } 2869 2870 /* Insert TDs into schedule. */ 2871 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2872 std = iso->stds[i]; 2873 vstd = sc->sc_vframes[i].htd; 2874 usb_syncmem(&vstd->dma, 2875 vstd->offs + offsetof(uhci_td_t, td_link), 2876 sizeof(vstd->td.td_link), 2877 BUS_DMASYNC_POSTWRITE); 2878 std->link = vstd->link; 2879 std->td.td_link = vstd->td.td_link; 2880 usb_syncmem(&std->dma, 2881 std->offs + offsetof(uhci_td_t, td_link), 2882 sizeof(std->td.td_link), 2883 BUS_DMASYNC_PREWRITE); 2884 vstd->link.std = std; 2885 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2886 usb_syncmem(&vstd->dma, 2887 vstd->offs + offsetof(uhci_td_t, td_link), 2888 sizeof(vstd->td.td_link), 2889 BUS_DMASYNC_PREWRITE); 2890 } 2891 mutex_exit(&sc->sc_lock); 2892 2893 iso->next = -1; 2894 iso->inuse = 0; 2895 2896 return USBD_NORMAL_COMPLETION; 2897 2898 bad: 2899 while (--i >= 0) 2900 uhci_free_std(sc, iso->stds[i]); 2901 mutex_exit(&sc->sc_lock); 2902 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2903 return USBD_NOMEM; 2904 } 2905 2906 void 2907 uhci_device_isoc_done(usbd_xfer_handle xfer) 2908 { 2909 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2910 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2911 int i, offs; 2912 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2913 2914 2915 DPRINTFN(4, ("uhci_isoc_done: length=%d, ux_state=0x%08x\n", 2916 xfer->ux_actlen, xfer->ux_state)); 2917 2918 if (ii->xfer != xfer) 2919 /* Not on interrupt list, ignore it. */ 2920 return; 2921 2922 if (!uhci_active_intr_info(ii)) 2923 return; 2924 2925 #ifdef DIAGNOSTIC 2926 if (ii->stdend == NULL) { 2927 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2928 #ifdef UHCI_DEBUG 2929 uhci_dump_ii(ii); 2930 #endif 2931 return; 2932 } 2933 #endif 2934 2935 /* Turn off the interrupt since it is active even if the TD is not. */ 2936 usb_syncmem(&ii->stdend->dma, 2937 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2938 sizeof(ii->stdend->td.td_status), 2939 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2940 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2941 usb_syncmem(&ii->stdend->dma, 2942 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2943 sizeof(ii->stdend->td.td_status), 2944 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2945 2946 uhci_del_intr_info(ii); /* remove from active list */ 2947 2948 offs = 0; 2949 for (i = 0; i < xfer->ux_nframes; i++) { 2950 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2951 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2952 offs += xfer->ux_frlengths[i]; 2953 } 2954 } 2955 2956 void 2957 uhci_device_intr_done(usbd_xfer_handle xfer) 2958 { 2959 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2960 uhci_softc_t *sc = ii->sc; 2961 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2962 uhci_soft_qh_t *sqh; 2963 int i, npoll, isread; 2964 2965 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->ux_actlen)); 2966 2967 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2968 2969 npoll = upipe->u.intr.npoll; 2970 for(i = 0; i < npoll; i++) { 2971 sqh = upipe->u.intr.qhs[i]; 2972 sqh->elink = NULL; 2973 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2974 usb_syncmem(&sqh->dma, 2975 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2976 sizeof(sqh->qh.qh_elink), 2977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2978 } 2979 uhci_free_std_chain(sc, ii->stdstart, NULL); 2980 2981 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2982 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2983 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2984 2985 /* XXX Wasteful. */ 2986 if (xfer->ux_pipe->up_repeat) { 2987 uhci_soft_td_t *data, *dataend; 2988 2989 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2990 2991 /* This alloc cannot fail since we freed the chain above. */ 2992 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 2993 upipe->u.intr.isread, xfer->ux_flags, 2994 &xfer->ux_dmabuf, &data, &dataend); 2995 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2996 usb_syncmem(&dataend->dma, 2997 dataend->offs + offsetof(uhci_td_t, td_status), 2998 sizeof(dataend->td.td_status), 2999 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3000 3001 #ifdef UHCI_DEBUG 3002 if (uhcidebug > 10) { 3003 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3004 uhci_dump_tds(data); 3005 uhci_dump_qh(upipe->u.intr.qhs[0]); 3006 } 3007 #endif 3008 3009 ii->stdstart = data; 3010 ii->stdend = dataend; 3011 #ifdef DIAGNOSTIC 3012 if (!ii->isdone) { 3013 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3014 } 3015 ii->isdone = 0; 3016 #endif 3017 for (i = 0; i < npoll; i++) { 3018 sqh = upipe->u.intr.qhs[i]; 3019 sqh->elink = data; 3020 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3021 usb_syncmem(&sqh->dma, 3022 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3023 sizeof(sqh->qh.qh_elink), 3024 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3025 } 3026 xfer->ux_status = USBD_IN_PROGRESS; 3027 /* The ii is already on the examined list, just leave it. */ 3028 } else { 3029 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3030 if (uhci_active_intr_info(ii)) 3031 uhci_del_intr_info(ii); 3032 } 3033 } 3034 3035 /* Deallocate request data structures */ 3036 void 3037 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3038 { 3039 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3040 uhci_softc_t *sc = ii->sc; 3041 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3042 int len = UGETW(xfer->ux_request.wLength); 3043 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3044 3045 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3046 3047 #ifdef DIAGNOSTIC 3048 if (!(xfer->ux_rqflags & URQ_REQUEST)) 3049 panic("uhci_device_ctrl_done: not a request"); 3050 #endif 3051 3052 if (!uhci_active_intr_info(ii)) 3053 return; 3054 3055 uhci_del_intr_info(ii); /* remove from active list */ 3056 3057 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3058 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3059 else 3060 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3061 3062 if (upipe->u.ctl.length != 0) 3063 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3064 3065 if (len) { 3066 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3067 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3068 } 3069 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3070 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3071 3072 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->ux_actlen)); 3073 } 3074 3075 /* Deallocate request data structures */ 3076 void 3077 uhci_device_bulk_done(usbd_xfer_handle xfer) 3078 { 3079 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3080 uhci_softc_t *sc = ii->sc; 3081 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3082 3083 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3084 xfer, ii, sc, upipe)); 3085 3086 KASSERT(mutex_owned(&sc->sc_lock)); 3087 3088 if (!uhci_active_intr_info(ii)) 3089 return; 3090 3091 uhci_del_intr_info(ii); /* remove from active list */ 3092 3093 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3094 3095 uhci_free_std_chain(sc, ii->stdstart, NULL); 3096 3097 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->ux_actlen)); 3098 } 3099 3100 /* Add interrupt QH, called with vflock. */ 3101 void 3102 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3103 { 3104 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3105 uhci_soft_qh_t *eqh; 3106 3107 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3108 3109 eqh = vf->eqh; 3110 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3111 sizeof(eqh->qh.qh_hlink), 3112 BUS_DMASYNC_POSTWRITE); 3113 sqh->hlink = eqh->hlink; 3114 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3115 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3116 sizeof(sqh->qh.qh_hlink), 3117 BUS_DMASYNC_PREWRITE); 3118 eqh->hlink = sqh; 3119 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3120 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3121 sizeof(eqh->qh.qh_hlink), 3122 BUS_DMASYNC_PREWRITE); 3123 vf->eqh = sqh; 3124 vf->bandwidth++; 3125 } 3126 3127 /* Remove interrupt QH. */ 3128 void 3129 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3130 { 3131 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3132 uhci_soft_qh_t *pqh; 3133 3134 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3135 3136 /* See comment in uhci_remove_ctrl() */ 3137 3138 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3139 sizeof(sqh->qh.qh_elink), 3140 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3141 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3142 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3143 usb_syncmem(&sqh->dma, 3144 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3145 sizeof(sqh->qh.qh_elink), 3146 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3147 delay(UHCI_QH_REMOVE_DELAY); 3148 } 3149 3150 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3151 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3152 sizeof(sqh->qh.qh_hlink), 3153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3154 pqh->hlink = sqh->hlink; 3155 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3156 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3157 sizeof(pqh->qh.qh_hlink), 3158 BUS_DMASYNC_PREWRITE); 3159 delay(UHCI_QH_REMOVE_DELAY); 3160 if (vf->eqh == sqh) 3161 vf->eqh = pqh; 3162 vf->bandwidth--; 3163 } 3164 3165 usbd_status 3166 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3167 { 3168 uhci_soft_qh_t *sqh; 3169 int i, npoll; 3170 u_int bestbw, bw, bestoffs, offs; 3171 3172 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3173 if (ival == 0) { 3174 printf("uhci_device_setintr: 0 interval\n"); 3175 return USBD_INVAL; 3176 } 3177 3178 if (ival > UHCI_VFRAMELIST_COUNT) 3179 ival = UHCI_VFRAMELIST_COUNT; 3180 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3181 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3182 3183 upipe->u.intr.npoll = npoll; 3184 upipe->u.intr.qhs = 3185 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3186 if (upipe->u.intr.qhs == NULL) 3187 return USBD_NOMEM; 3188 3189 /* 3190 * Figure out which offset in the schedule that has most 3191 * bandwidth left over. 3192 */ 3193 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3194 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3195 for (bw = i = 0; i < npoll; i++) 3196 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3197 if (bw < bestbw) { 3198 bestbw = bw; 3199 bestoffs = offs; 3200 } 3201 } 3202 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3203 3204 mutex_enter(&sc->sc_lock); 3205 for(i = 0; i < npoll; i++) { 3206 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3207 sqh->elink = NULL; 3208 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3209 usb_syncmem(&sqh->dma, 3210 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3211 sizeof(sqh->qh.qh_elink), 3212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3213 sqh->pos = MOD(i * ival + bestoffs); 3214 } 3215 #undef MOD 3216 3217 /* Enter QHs into the controller data structures. */ 3218 for(i = 0; i < npoll; i++) 3219 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3220 mutex_exit(&sc->sc_lock); 3221 3222 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3223 return USBD_NORMAL_COMPLETION; 3224 } 3225 3226 /* Open a new pipe. */ 3227 usbd_status 3228 uhci_open(usbd_pipe_handle pipe) 3229 { 3230 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3231 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3232 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3233 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3234 usbd_status err = USBD_NOMEM; 3235 int ival; 3236 3237 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3238 pipe, pipe->up_dev->ud_addr, 3239 ed->bEndpointAddress, bus->ub_rhaddr)); 3240 3241 if (sc->sc_dying) 3242 return USBD_IOERROR; 3243 3244 upipe->aborting = 0; 3245 /* toggle state needed for bulk endpoints */ 3246 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3247 3248 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3249 switch (ed->bEndpointAddress) { 3250 case USB_CONTROL_ENDPOINT: 3251 pipe->up_methods = &roothub_ctrl_methods; 3252 break; 3253 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3254 pipe->up_methods = &uhci_root_intr_methods; 3255 break; 3256 default: 3257 return USBD_INVAL; 3258 } 3259 } else { 3260 switch (ed->bmAttributes & UE_XFERTYPE) { 3261 case UE_CONTROL: 3262 pipe->up_methods = &uhci_device_ctrl_methods; 3263 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3264 if (upipe->u.ctl.sqh == NULL) 3265 goto bad; 3266 upipe->u.ctl.setup = uhci_alloc_std(sc); 3267 if (upipe->u.ctl.setup == NULL) { 3268 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3269 goto bad; 3270 } 3271 upipe->u.ctl.stat = uhci_alloc_std(sc); 3272 if (upipe->u.ctl.stat == NULL) { 3273 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3274 uhci_free_std(sc, upipe->u.ctl.setup); 3275 goto bad; 3276 } 3277 err = usb_allocmem(&sc->sc_bus, 3278 sizeof(usb_device_request_t), 3279 0, &upipe->u.ctl.reqdma); 3280 if (err) { 3281 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3282 uhci_free_std(sc, upipe->u.ctl.setup); 3283 uhci_free_std(sc, upipe->u.ctl.stat); 3284 goto bad; 3285 } 3286 break; 3287 case UE_INTERRUPT: 3288 pipe->up_methods = &uhci_device_intr_methods; 3289 ival = pipe->up_interval; 3290 if (ival == USBD_DEFAULT_INTERVAL) 3291 ival = ed->bInterval; 3292 return uhci_device_setintr(sc, upipe, ival); 3293 case UE_ISOCHRONOUS: 3294 pipe->up_methods = &uhci_device_isoc_methods; 3295 return uhci_setup_isoc(pipe); 3296 case UE_BULK: 3297 pipe->up_methods = &uhci_device_bulk_methods; 3298 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3299 if (upipe->u.bulk.sqh == NULL) 3300 goto bad; 3301 break; 3302 } 3303 } 3304 return USBD_NORMAL_COMPLETION; 3305 3306 bad: 3307 return USBD_NOMEM; 3308 } 3309 3310 /* 3311 * Data structures and routines to emulate the root hub. 3312 */ 3313 /* 3314 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3315 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3316 * should not be used by the USB subsystem. As we cannot issue a 3317 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3318 * will be enabled as part of the reset. 3319 * 3320 * On the VT83C572, the port cannot be successfully enabled until the 3321 * outstanding "port enable change" and "connection status change" 3322 * events have been reset. 3323 */ 3324 Static usbd_status 3325 uhci_portreset(uhci_softc_t *sc, int index) 3326 { 3327 int lim, port, x; 3328 3329 if (index == 1) 3330 port = UHCI_PORTSC1; 3331 else if (index == 2) 3332 port = UHCI_PORTSC2; 3333 else 3334 return USBD_IOERROR; 3335 3336 x = URWMASK(UREAD2(sc, port)); 3337 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3338 3339 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3340 3341 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3342 index, UREAD2(sc, port))); 3343 3344 x = URWMASK(UREAD2(sc, port)); 3345 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3346 3347 delay(100); 3348 3349 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3350 index, UREAD2(sc, port))); 3351 3352 x = URWMASK(UREAD2(sc, port)); 3353 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3354 3355 for (lim = 10; --lim > 0;) { 3356 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3357 3358 x = UREAD2(sc, port); 3359 3360 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3361 index, lim, x)); 3362 3363 if (!(x & UHCI_PORTSC_CCS)) { 3364 /* 3365 * No device is connected (or was disconnected 3366 * during reset). Consider the port reset. 3367 * The delay must be long enough to ensure on 3368 * the initial iteration that the device 3369 * connection will have been registered. 50ms 3370 * appears to be sufficient, but 20ms is not. 3371 */ 3372 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3373 index, lim)); 3374 break; 3375 } 3376 3377 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3378 /* 3379 * Port enabled changed and/or connection 3380 * status changed were set. Reset either or 3381 * both raised flags (by writing a 1 to that 3382 * bit), and wait again for state to settle. 3383 */ 3384 UWRITE2(sc, port, URWMASK(x) | 3385 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3386 continue; 3387 } 3388 3389 if (x & UHCI_PORTSC_PE) 3390 /* Port is enabled */ 3391 break; 3392 3393 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3394 } 3395 3396 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3397 index, UREAD2(sc, port))); 3398 3399 if (lim <= 0) { 3400 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3401 return USBD_TIMEOUT; 3402 } 3403 3404 sc->sc_isreset = 1; 3405 return USBD_NORMAL_COMPLETION; 3406 } 3407 3408 Static int 3409 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3410 void *buf, int buflen) 3411 { 3412 uhci_softc_t *sc = bus->ub_hcpriv; 3413 int port, x; 3414 int status, change, totlen = 0; 3415 uint16_t len, value, index; 3416 usb_port_status_t ps; 3417 usbd_status err; 3418 3419 if (sc->sc_dying) 3420 return -1; 3421 3422 DPRINTFN(2,("%s: type=0x%02x request=%02x\n", __func__, 3423 req->bmRequestType, req->bRequest)); 3424 3425 len = UGETW(req->wLength); 3426 value = UGETW(req->wValue); 3427 index = UGETW(req->wIndex); 3428 3429 #define C(x,y) ((x) | ((y) << 8)) 3430 switch (C(req->bRequest, req->bmRequestType)) { 3431 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3432 DPRINTFN(2,("%s: wValue=0x%04x\n", __func__, value)); 3433 if (len == 0) 3434 break; 3435 switch (value) { 3436 case C(0, UDESC_DEVICE): { 3437 usb_device_descriptor_t devd; 3438 3439 totlen = min(buflen, sizeof(devd)); 3440 memcpy(&devd, buf, totlen); 3441 USETW(devd.idVendor, sc->sc_id_vendor); 3442 memcpy(buf, &devd, totlen); 3443 break; 3444 } 3445 case C(1, UDESC_STRING): 3446 #define sd ((usb_string_descriptor_t *)buf) 3447 /* Vendor */ 3448 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3449 break; 3450 case C(2, UDESC_STRING): 3451 /* Product */ 3452 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3453 break; 3454 #undef sd 3455 default: 3456 /* default from usbroothub */ 3457 return buflen; 3458 } 3459 break; 3460 3461 /* Hub requests */ 3462 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3463 break; 3464 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3465 DPRINTFN(3, ("%s: UR_CLEAR_PORT_FEATURE " 3466 "port=%d feature=%d\n", __func__, 3467 index, value)); 3468 if (index == 1) 3469 port = UHCI_PORTSC1; 3470 else if (index == 2) 3471 port = UHCI_PORTSC2; 3472 else { 3473 return -1; 3474 } 3475 switch(value) { 3476 case UHF_PORT_ENABLE: 3477 x = URWMASK(UREAD2(sc, port)); 3478 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3479 break; 3480 case UHF_PORT_SUSPEND: 3481 x = URWMASK(UREAD2(sc, port)); 3482 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3483 break; 3484 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3485 /* see USB2 spec ch. 7.1.7.7 */ 3486 usb_delay_ms(&sc->sc_bus, 20); 3487 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3488 /* 10ms resume delay must be provided by caller */ 3489 break; 3490 case UHF_PORT_RESET: 3491 x = URWMASK(UREAD2(sc, port)); 3492 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3493 break; 3494 case UHF_C_PORT_CONNECTION: 3495 x = URWMASK(UREAD2(sc, port)); 3496 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3497 break; 3498 case UHF_C_PORT_ENABLE: 3499 x = URWMASK(UREAD2(sc, port)); 3500 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3501 break; 3502 case UHF_C_PORT_OVER_CURRENT: 3503 x = URWMASK(UREAD2(sc, port)); 3504 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3505 break; 3506 case UHF_C_PORT_RESET: 3507 sc->sc_isreset = 0; 3508 break; 3509 case UHF_PORT_CONNECTION: 3510 case UHF_PORT_OVER_CURRENT: 3511 case UHF_PORT_POWER: 3512 case UHF_PORT_LOW_SPEED: 3513 case UHF_C_PORT_SUSPEND: 3514 default: 3515 return -1; 3516 } 3517 break; 3518 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3519 if (index == 1) 3520 port = UHCI_PORTSC1; 3521 else if (index == 2) 3522 port = UHCI_PORTSC2; 3523 else { 3524 return -1; 3525 } 3526 if (len > 0) { 3527 *(uint8_t *)buf = 3528 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3529 UHCI_PORTSC_LS_SHIFT; 3530 totlen = 1; 3531 } 3532 break; 3533 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3534 if (len == 0) 3535 break; 3536 if ((value & 0xff) != 0) { 3537 return -1; 3538 } 3539 usb_hub_descriptor_t hubd; 3540 3541 totlen = min(buflen, sizeof(hubd)); 3542 memcpy(&hubd, buf, totlen); 3543 hubd.bNbrPorts = 2; 3544 memcpy(buf, &hubd, totlen); 3545 break; 3546 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3547 if (len != 4) { 3548 return -1; 3549 } 3550 memset(buf, 0, len); 3551 totlen = len; 3552 break; 3553 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3554 if (index == 1) 3555 port = UHCI_PORTSC1; 3556 else if (index == 2) 3557 port = UHCI_PORTSC2; 3558 else { 3559 return -1; 3560 } 3561 if (len != 4) { 3562 return -1; 3563 } 3564 x = UREAD2(sc, port); 3565 status = change = 0; 3566 if (x & UHCI_PORTSC_CCS) 3567 status |= UPS_CURRENT_CONNECT_STATUS; 3568 if (x & UHCI_PORTSC_CSC) 3569 change |= UPS_C_CONNECT_STATUS; 3570 if (x & UHCI_PORTSC_PE) 3571 status |= UPS_PORT_ENABLED; 3572 if (x & UHCI_PORTSC_POEDC) 3573 change |= UPS_C_PORT_ENABLED; 3574 if (x & UHCI_PORTSC_OCI) 3575 status |= UPS_OVERCURRENT_INDICATOR; 3576 if (x & UHCI_PORTSC_OCIC) 3577 change |= UPS_C_OVERCURRENT_INDICATOR; 3578 if (x & UHCI_PORTSC_SUSP) 3579 status |= UPS_SUSPEND; 3580 if (x & UHCI_PORTSC_LSDA) 3581 status |= UPS_LOW_SPEED; 3582 status |= UPS_PORT_POWER; 3583 if (sc->sc_isreset) 3584 change |= UPS_C_PORT_RESET; 3585 USETW(ps.wPortStatus, status); 3586 USETW(ps.wPortChange, change); 3587 totlen = min(len, sizeof(ps)); 3588 memcpy(buf, &ps, totlen); 3589 break; 3590 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3591 return -1; 3592 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3593 break; 3594 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3595 if (index == 1) 3596 port = UHCI_PORTSC1; 3597 else if (index == 2) 3598 port = UHCI_PORTSC2; 3599 else { 3600 return -1; 3601 } 3602 switch(value) { 3603 case UHF_PORT_ENABLE: 3604 x = URWMASK(UREAD2(sc, port)); 3605 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3606 break; 3607 case UHF_PORT_SUSPEND: 3608 x = URWMASK(UREAD2(sc, port)); 3609 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3610 break; 3611 case UHF_PORT_RESET: 3612 err = uhci_portreset(sc, index); 3613 if (err != USBD_NORMAL_COMPLETION) 3614 return -1; 3615 return 0; 3616 case UHF_PORT_POWER: 3617 /* Pretend we turned on power */ 3618 return 0; 3619 case UHF_C_PORT_CONNECTION: 3620 case UHF_C_PORT_ENABLE: 3621 case UHF_C_PORT_OVER_CURRENT: 3622 case UHF_PORT_CONNECTION: 3623 case UHF_PORT_OVER_CURRENT: 3624 case UHF_PORT_LOW_SPEED: 3625 case UHF_C_PORT_SUSPEND: 3626 case UHF_C_PORT_RESET: 3627 default: 3628 return -1; 3629 } 3630 break; 3631 default: 3632 /* default from usbroothub */ 3633 return buflen; 3634 } 3635 3636 return totlen; 3637 } 3638 3639 /* Abort a root interrupt request. */ 3640 void 3641 uhci_root_intr_abort(usbd_xfer_handle xfer) 3642 { 3643 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3644 3645 KASSERT(mutex_owned(&sc->sc_lock)); 3646 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3647 3648 callout_stop(&sc->sc_poll_handle); 3649 sc->sc_intr_xfer = NULL; 3650 3651 xfer->ux_status = USBD_CANCELLED; 3652 #ifdef DIAGNOSTIC 3653 UXFER(xfer)->iinfo.isdone = 1; 3654 #endif 3655 usb_transfer_complete(xfer); 3656 } 3657 3658 usbd_status 3659 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3660 { 3661 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3662 usbd_status err; 3663 3664 /* Insert last in queue. */ 3665 mutex_enter(&sc->sc_lock); 3666 err = usb_insert_transfer(xfer); 3667 mutex_exit(&sc->sc_lock); 3668 if (err) 3669 return err; 3670 3671 /* 3672 * Pipe isn't running (otherwise err would be USBD_INPROG), 3673 * start first 3674 */ 3675 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3676 } 3677 3678 /* Start a transfer on the root interrupt pipe */ 3679 usbd_status 3680 uhci_root_intr_start(usbd_xfer_handle xfer) 3681 { 3682 usbd_pipe_handle pipe = xfer->ux_pipe; 3683 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3684 unsigned int ival; 3685 3686 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3687 xfer, xfer->ux_length, xfer->ux_flags)); 3688 3689 if (sc->sc_dying) 3690 return USBD_IOERROR; 3691 3692 /* XXX temporary variable needed to avoid gcc3 warning */ 3693 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3694 sc->sc_ival = mstohz(ival); 3695 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3696 sc->sc_intr_xfer = xfer; 3697 return USBD_IN_PROGRESS; 3698 } 3699 3700 /* Close the root interrupt pipe. */ 3701 void 3702 uhci_root_intr_close(usbd_pipe_handle pipe) 3703 { 3704 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3705 3706 KASSERT(mutex_owned(&sc->sc_lock)); 3707 3708 callout_stop(&sc->sc_poll_handle); 3709 sc->sc_intr_xfer = NULL; 3710 DPRINTF(("uhci_root_intr_close\n")); 3711 } 3712
Indexes created Tue Sep 30 20:09:53 GMT 2025