uhci.c revision 1.264.4.20
1 /* $NetBSD: uhci.c,v 1.264.4.20 2015/02/20 09:16:49 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.20 2015/02/20 09:16:49 skrll Exp $"); 46 47 #include <sys/param.h> 48 49 #include <sys/bus.h> 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/mutex.h> 55 #include <sys/proc.h> 56 #include <sys/queue.h> 57 #include <sys/select.h> 58 #include <sys/sysctl.h> 59 #include <sys/systm.h> 60 61 #include <machine/endian.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usb_mem.h> 67 #include <dev/usb/usb_quirks.h> 68 69 #include <dev/usb/uhcireg.h> 70 #include <dev/usb/uhcivar.h> 71 #include <dev/usb/usbroothub.h> 72 73 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 74 /*#define UHCI_CTL_LOOP */ 75 76 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 #define DPRINTF(x) if (uhcidebug) printf x 81 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 82 int uhcidebug = 0; 83 int uhcinoloop = 0; 84 #else 85 #define DPRINTF(x) 86 #define DPRINTFN(n,x) 87 #endif 88 89 /* 90 * The UHCI controller is little endian, so on big endian machines 91 * the data stored in memory needs to be swapped. 92 */ 93 94 struct uhci_pipe { 95 struct usbd_pipe pipe; 96 int nexttoggle; 97 98 u_char aborting; 99 usbd_xfer_handle abortstart, abortend; 100 101 /* Info needed for different pipe kinds. */ 102 union { 103 /* Control pipe */ 104 struct { 105 uhci_soft_qh_t *sqh; 106 usb_dma_t reqdma; 107 uhci_soft_td_t *setup, *stat; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 int npoll; 113 int isread; 114 uhci_soft_qh_t **qhs; 115 } intr; 116 /* Bulk pipe */ 117 struct { 118 uhci_soft_qh_t *sqh; 119 u_int length; 120 int isread; 121 } bulk; 122 /* Iso pipe */ 123 struct iso { 124 uhci_soft_td_t **stds; 125 int next, inuse; 126 } iso; 127 } u; 128 }; 129 130 Static void uhci_globalreset(uhci_softc_t *); 131 Static usbd_status uhci_portreset(uhci_softc_t*, int); 132 Static void uhci_reset(uhci_softc_t *); 133 Static usbd_status uhci_run(uhci_softc_t *, int, int); 134 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 135 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 136 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 137 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 138 #if 0 139 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 140 uhci_intr_info_t *); 141 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 142 #endif 143 144 Static void uhci_free_std_chain(uhci_softc_t *, 145 uhci_soft_td_t *, uhci_soft_td_t *); 146 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 147 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 148 uhci_soft_td_t **, uhci_soft_td_t **); 149 Static void uhci_poll_hub(void *); 150 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 151 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 152 Static void uhci_idone(uhci_intr_info_t *); 153 154 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status); 155 156 Static void uhci_timeout(void *); 157 Static void uhci_timeout_task(void *); 158 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 160 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 161 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 163 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 164 Static void uhci_add_loop(uhci_softc_t *); 165 Static void uhci_rem_loop(uhci_softc_t *); 166 167 Static usbd_status uhci_setup_isoc(usbd_pipe_handle); 168 Static void uhci_device_isoc_enter(usbd_xfer_handle); 169 170 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 171 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 172 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int uhci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 177 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 178 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 179 Static void uhci_device_ctrl_close(usbd_pipe_handle); 180 Static void uhci_device_ctrl_done(usbd_xfer_handle); 181 182 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 183 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 184 Static void uhci_device_intr_abort(usbd_xfer_handle); 185 Static void uhci_device_intr_close(usbd_pipe_handle); 186 Static void uhci_device_intr_done(usbd_xfer_handle); 187 188 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 189 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 190 Static void uhci_device_bulk_abort(usbd_xfer_handle); 191 Static void uhci_device_bulk_close(usbd_pipe_handle); 192 Static void uhci_device_bulk_done(usbd_xfer_handle); 193 194 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 195 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 196 Static void uhci_device_isoc_abort(usbd_xfer_handle); 197 Static void uhci_device_isoc_close(usbd_pipe_handle); 198 Static void uhci_device_isoc_done(usbd_xfer_handle); 199 200 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 201 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 202 Static void uhci_root_intr_abort(usbd_xfer_handle); 203 Static void uhci_root_intr_close(usbd_pipe_handle); 204 Static void uhci_root_intr_done(usbd_xfer_handle); 205 206 Static usbd_status uhci_open(usbd_pipe_handle); 207 Static void uhci_poll(struct usbd_bus *); 208 Static void uhci_softintr(void *); 209 210 Static usbd_status uhci_device_request(usbd_xfer_handle); 211 212 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 213 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 214 Static usbd_status uhci_device_setintr(uhci_softc_t *, 215 struct uhci_pipe *, int); 216 217 Static void uhci_device_clear_toggle(usbd_pipe_handle); 218 Static void uhci_noop(usbd_pipe_handle); 219 220 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 221 uhci_soft_qh_t *); 222 223 #ifdef UHCI_DEBUG 224 Static void uhci_dump_all(uhci_softc_t *); 225 Static void uhci_dumpregs(uhci_softc_t *); 226 Static void uhci_dump_qhs(uhci_soft_qh_t *); 227 Static void uhci_dump_qh(uhci_soft_qh_t *); 228 Static void uhci_dump_tds(uhci_soft_td_t *); 229 Static void uhci_dump_td(uhci_soft_td_t *); 230 Static void uhci_dump_ii(uhci_intr_info_t *); 231 void uhci_dump(void); 232 #endif 233 234 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 235 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 236 #define UWRITE1(sc, r, x) \ 237 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 238 } while (/*CONSTCOND*/0) 239 #define UWRITE2(sc, r, x) \ 240 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 241 } while (/*CONSTCOND*/0) 242 #define UWRITE4(sc, r, x) \ 243 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 244 } while (/*CONSTCOND*/0) 245 static __inline uint8_t 246 UREAD1(uhci_softc_t *sc, bus_size_t r) 247 { 248 249 UBARR(sc); 250 return bus_space_read_1(sc->iot, sc->ioh, r); 251 } 252 253 static __inline uint16_t 254 UREAD2(uhci_softc_t *sc, bus_size_t r) 255 { 256 257 UBARR(sc); 258 return bus_space_read_2(sc->iot, sc->ioh, r); 259 } 260 261 #ifdef UHCI_DEBUG 262 static __inline uint32_t 263 UREAD4(uhci_softc_t *sc, bus_size_t r) 264 { 265 266 UBARR(sc); 267 return bus_space_read_4(sc->iot, sc->ioh, r); 268 } 269 #endif 270 271 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 272 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 273 274 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 275 276 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 277 278 const struct usbd_bus_methods uhci_bus_methods = { 279 .ubm_open = uhci_open, 280 .ubm_softint = uhci_softintr, 281 .ubm_dopoll = uhci_poll, 282 .ubm_allocx = uhci_allocx, 283 .ubm_freex = uhci_freex, 284 .ubm_getlock = uhci_get_lock, 285 .ubm_rhctrl = uhci_roothub_ctrl, 286 }; 287 288 const struct usbd_pipe_methods uhci_root_intr_methods = { 289 .upm_transfer = uhci_root_intr_transfer, 290 .upm_start = uhci_root_intr_start, 291 .upm_abort = uhci_root_intr_abort, 292 .upm_close = uhci_root_intr_close, 293 .upm_cleartoggle = uhci_noop, 294 .upm_done = uhci_root_intr_done, 295 }; 296 297 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 298 .upm_transfer = uhci_device_ctrl_transfer, 299 .upm_start = uhci_device_ctrl_start, 300 .upm_abort = uhci_device_ctrl_abort, 301 .upm_close = uhci_device_ctrl_close, 302 .upm_cleartoggle = uhci_noop, 303 .upm_done = uhci_device_ctrl_done, 304 }; 305 306 const struct usbd_pipe_methods uhci_device_intr_methods = { 307 .upm_transfer = uhci_device_intr_transfer, 308 .upm_start = uhci_device_intr_start, 309 .upm_abort = uhci_device_intr_abort, 310 .upm_close = uhci_device_intr_close, 311 .upm_cleartoggle = uhci_device_clear_toggle, 312 .upm_done = uhci_device_intr_done, 313 }; 314 315 const struct usbd_pipe_methods uhci_device_bulk_methods = { 316 .upm_transfer = uhci_device_bulk_transfer, 317 .upm_start = uhci_device_bulk_start, 318 .upm_abort = uhci_device_bulk_abort, 319 .upm_close = uhci_device_bulk_close, 320 .upm_cleartoggle = uhci_device_clear_toggle, 321 .upm_done = uhci_device_bulk_done, 322 }; 323 324 const struct usbd_pipe_methods uhci_device_isoc_methods = { 325 .upm_transfer = uhci_device_isoc_transfer, 326 .upm_start = uhci_device_isoc_start, 327 .upm_abort = uhci_device_isoc_abort, 328 .upm_close = uhci_device_isoc_close, 329 .upm_cleartoggle = uhci_noop, 330 .upm_done = uhci_device_isoc_done, 331 }; 332 333 #define uhci_add_intr_info(sc, ii) \ 334 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 335 #define uhci_del_intr_info(ii) \ 336 do { \ 337 LIST_REMOVE((ii), list); \ 338 (ii)->list.le_prev = NULL; \ 339 } while (0) 340 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 341 342 static inline uhci_soft_qh_t * 343 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 344 { 345 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 346 347 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 348 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 349 usb_syncmem(&pqh->dma, 350 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 351 sizeof(pqh->qh.qh_hlink), 352 BUS_DMASYNC_POSTWRITE); 353 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 354 printf("uhci_find_prev_qh: QH not found\n"); 355 return NULL; 356 } 357 #endif 358 } 359 return pqh; 360 } 361 362 void 363 uhci_globalreset(uhci_softc_t *sc) 364 { 365 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 366 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 367 UHCICMD(sc, 0); /* do nothing */ 368 } 369 370 int 371 uhci_init(uhci_softc_t *sc) 372 { 373 usbd_status err; 374 int i, j; 375 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 376 uhci_soft_td_t *std; 377 378 DPRINTFN(1,("uhci_init: start\n")); 379 380 #ifdef UHCI_DEBUG 381 thesc = sc; 382 383 if (uhcidebug > 2) 384 uhci_dumpregs(sc); 385 #endif 386 387 sc->sc_suspend = PWR_RESUME; 388 389 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 390 uhci_globalreset(sc); /* reset the controller */ 391 uhci_reset(sc); 392 393 /* Allocate and initialize real frame array. */ 394 err = usb_allocmem(&sc->sc_bus, 395 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 396 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 397 if (err) 398 return err; 399 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 400 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 401 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 402 403 /* 404 * Allocate a TD, inactive, that hangs from the last QH. 405 * This is to avoid a bug in the PIIX that makes it run berserk 406 * otherwise. 407 */ 408 std = uhci_alloc_std(sc); 409 if (std == NULL) 410 return ENOMEM; 411 std->link.std = NULL; 412 std->td.td_link = htole32(UHCI_PTR_T); 413 std->td.td_status = htole32(0); /* inactive */ 414 std->td.td_token = htole32(0); 415 std->td.td_buffer = htole32(0); 416 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 418 419 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 420 lsqh = uhci_alloc_sqh(sc); 421 if (lsqh == NULL) 422 return ENOMEM; 423 lsqh->hlink = NULL; 424 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 425 lsqh->elink = std; 426 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 427 sc->sc_last_qh = lsqh; 428 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 429 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 430 431 /* Allocate the dummy QH where bulk traffic will be queued. */ 432 bsqh = uhci_alloc_sqh(sc); 433 if (bsqh == NULL) 434 return ENOMEM; 435 bsqh->hlink = lsqh; 436 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 437 bsqh->elink = NULL; 438 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 439 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 440 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 442 443 /* Allocate dummy QH where high speed control traffic will be queued. */ 444 chsqh = uhci_alloc_sqh(sc); 445 if (chsqh == NULL) 446 return ENOMEM; 447 chsqh->hlink = bsqh; 448 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 449 chsqh->elink = NULL; 450 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 451 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 452 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 453 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 454 455 /* Allocate dummy QH where control traffic will be queued. */ 456 clsqh = uhci_alloc_sqh(sc); 457 if (clsqh == NULL) 458 return ENOMEM; 459 clsqh->hlink = chsqh; 460 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 461 clsqh->elink = NULL; 462 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 463 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 464 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 465 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 466 467 /* 468 * Make all (virtual) frame list pointers point to the interrupt 469 * queue heads and the interrupt queue heads at the control 470 * queue head and point the physical frame list to the virtual. 471 */ 472 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 473 std = uhci_alloc_std(sc); 474 sqh = uhci_alloc_sqh(sc); 475 if (std == NULL || sqh == NULL) 476 return USBD_NOMEM; 477 std->link.sqh = sqh; 478 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 479 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 480 std->td.td_token = htole32(0); 481 std->td.td_buffer = htole32(0); 482 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 sqh->hlink = clsqh; 485 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 486 sqh->elink = NULL; 487 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 488 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 489 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 490 sc->sc_vframes[i].htd = std; 491 sc->sc_vframes[i].etd = std; 492 sc->sc_vframes[i].hqh = sqh; 493 sc->sc_vframes[i].eqh = sqh; 494 for (j = i; 495 j < UHCI_FRAMELIST_COUNT; 496 j += UHCI_VFRAMELIST_COUNT) 497 sc->sc_pframes[j] = htole32(std->physaddr); 498 } 499 usb_syncmem(&sc->sc_dma, 0, 500 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 501 BUS_DMASYNC_PREWRITE); 502 503 504 LIST_INIT(&sc->sc_intrhead); 505 506 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 507 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 508 509 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 510 511 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 512 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 513 cv_init(&sc->sc_softwake_cv, "uhciab"); 514 515 /* Set up the bus struct. */ 516 sc->sc_bus.ub_methods = &uhci_bus_methods; 517 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 518 sc->sc_bus.ub_usedma = true; 519 520 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 521 522 DPRINTFN(1,("uhci_init: enabling\n")); 523 524 err = uhci_run(sc, 1, 0); /* and here we go... */ 525 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 526 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 527 return err; 528 } 529 530 int 531 uhci_activate(device_t self, enum devact act) 532 { 533 struct uhci_softc *sc = device_private(self); 534 535 switch (act) { 536 case DVACT_DEACTIVATE: 537 sc->sc_dying = 1; 538 return 0; 539 default: 540 return EOPNOTSUPP; 541 } 542 } 543 544 void 545 uhci_childdet(device_t self, device_t child) 546 { 547 struct uhci_softc *sc = device_private(self); 548 549 KASSERT(sc->sc_child == child); 550 sc->sc_child = NULL; 551 } 552 553 int 554 uhci_detach(struct uhci_softc *sc, int flags) 555 { 556 int rv = 0; 557 558 if (sc->sc_child != NULL) 559 rv = config_detach(sc->sc_child, flags); 560 561 if (rv != 0) 562 return rv; 563 564 callout_halt(&sc->sc_poll_handle, NULL); 565 callout_destroy(&sc->sc_poll_handle); 566 567 cv_destroy(&sc->sc_softwake_cv); 568 569 mutex_destroy(&sc->sc_lock); 570 mutex_destroy(&sc->sc_intr_lock); 571 572 pool_cache_destroy(sc->sc_xferpool); 573 574 /* XXX free other data structures XXX */ 575 576 return rv; 577 } 578 579 usbd_xfer_handle 580 uhci_allocx(struct usbd_bus *bus) 581 { 582 struct uhci_softc *sc = bus->ub_hcpriv; 583 usbd_xfer_handle xfer; 584 585 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 586 if (xfer != NULL) { 587 memset(xfer, 0, sizeof(struct uhci_xfer)); 588 UXFER(xfer)->iinfo.sc = sc; 589 #ifdef DIAGNOSTIC 590 UXFER(xfer)->iinfo.isdone = 1; 591 xfer->ux_state = XFER_BUSY; 592 #endif 593 } 594 return xfer; 595 } 596 597 void 598 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 599 { 600 struct uhci_softc *sc = bus->ub_hcpriv; 601 602 #ifdef DIAGNOSTIC 603 if (xfer->ux_state != XFER_BUSY) { 604 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 605 xfer->ux_state); 606 } 607 xfer->ux_state = XFER_FREE; 608 if (!UXFER(xfer)->iinfo.isdone) { 609 printf("uhci_freex: !isdone\n"); 610 } 611 #endif 612 pool_cache_put(sc->sc_xferpool, xfer); 613 } 614 615 Static void 616 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 617 { 618 struct uhci_softc *sc = bus->ub_hcpriv; 619 620 *lock = &sc->sc_lock; 621 } 622 623 624 /* 625 * Handle suspend/resume. 626 * 627 * We need to switch to polling mode here, because this routine is 628 * called from an interrupt context. This is all right since we 629 * are almost suspended anyway. 630 */ 631 bool 632 uhci_resume(device_t dv, const pmf_qual_t *qual) 633 { 634 uhci_softc_t *sc = device_private(dv); 635 int cmd; 636 637 mutex_spin_enter(&sc->sc_intr_lock); 638 639 cmd = UREAD2(sc, UHCI_CMD); 640 sc->sc_bus.ub_usepolling++; 641 UWRITE2(sc, UHCI_INTR, 0); 642 uhci_globalreset(sc); 643 uhci_reset(sc); 644 if (cmd & UHCI_CMD_RS) 645 uhci_run(sc, 0, 1); 646 647 /* restore saved state */ 648 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 649 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 650 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 651 652 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 653 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 654 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 655 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 656 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 657 UHCICMD(sc, UHCI_CMD_MAXP); 658 uhci_run(sc, 1, 1); /* and start traffic again */ 659 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 660 sc->sc_bus.ub_usepolling--; 661 if (sc->sc_intr_xfer != NULL) 662 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 663 sc->sc_intr_xfer); 664 #ifdef UHCI_DEBUG 665 if (uhcidebug > 2) 666 uhci_dumpregs(sc); 667 #endif 668 669 sc->sc_suspend = PWR_RESUME; 670 mutex_spin_exit(&sc->sc_intr_lock); 671 672 return true; 673 } 674 675 bool 676 uhci_suspend(device_t dv, const pmf_qual_t *qual) 677 { 678 uhci_softc_t *sc = device_private(dv); 679 int cmd; 680 681 mutex_spin_enter(&sc->sc_intr_lock); 682 683 cmd = UREAD2(sc, UHCI_CMD); 684 685 #ifdef UHCI_DEBUG 686 if (uhcidebug > 2) 687 uhci_dumpregs(sc); 688 #endif 689 if (sc->sc_intr_xfer != NULL) 690 callout_stop(&sc->sc_poll_handle); 691 sc->sc_suspend = PWR_SUSPEND; 692 sc->sc_bus.ub_usepolling++; 693 694 uhci_run(sc, 0, 1); /* stop the controller */ 695 cmd &= ~UHCI_CMD_RS; 696 697 /* save some state if BIOS doesn't */ 698 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 699 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 700 701 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 702 703 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 704 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 705 sc->sc_bus.ub_usepolling--; 706 707 mutex_spin_exit(&sc->sc_intr_lock); 708 709 return true; 710 } 711 712 #ifdef UHCI_DEBUG 713 Static void 714 uhci_dumpregs(uhci_softc_t *sc) 715 { 716 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 717 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 718 device_xname(sc->sc_dev), 719 UREAD2(sc, UHCI_CMD), 720 UREAD2(sc, UHCI_STS), 721 UREAD2(sc, UHCI_INTR), 722 UREAD2(sc, UHCI_FRNUM), 723 UREAD4(sc, UHCI_FLBASEADDR), 724 UREAD1(sc, UHCI_SOF), 725 UREAD2(sc, UHCI_PORTSC1), 726 UREAD2(sc, UHCI_PORTSC2))); 727 } 728 729 void 730 uhci_dump_td(uhci_soft_td_t *p) 731 { 732 char sbuf[128], sbuf2[128]; 733 734 735 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 736 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 737 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 738 "token=0x%08lx buffer=0x%08lx\n", 739 p, (long)p->physaddr, 740 (long)le32toh(p->td.td_link), 741 (long)le32toh(p->td.td_status), 742 (long)le32toh(p->td.td_token), 743 (long)le32toh(p->td.td_buffer))); 744 745 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 746 (uint32_t)le32toh(p->td.td_link)); 747 snprintb(sbuf2, sizeof(sbuf2), 748 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 749 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 750 (uint32_t)le32toh(p->td.td_status)); 751 752 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 753 "D=%d,maxlen=%d\n", sbuf, sbuf2, 754 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 755 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 756 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 757 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 758 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 759 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 760 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 761 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 762 BUS_DMASYNC_PREREAD); 763 } 764 765 void 766 uhci_dump_qh(uhci_soft_qh_t *sqh) 767 { 768 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 769 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 770 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 771 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 772 le32toh(sqh->qh.qh_elink))); 773 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 774 } 775 776 777 #if 1 778 void 779 uhci_dump(void) 780 { 781 uhci_dump_all(thesc); 782 } 783 #endif 784 785 void 786 uhci_dump_all(uhci_softc_t *sc) 787 { 788 uhci_dumpregs(sc); 789 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 790 uhci_dump_qhs(sc->sc_lctl_start); 791 } 792 793 794 void 795 uhci_dump_qhs(uhci_soft_qh_t *sqh) 796 { 797 uhci_dump_qh(sqh); 798 799 /* 800 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 801 * Traverses sideways first, then down. 802 * 803 * QH1 804 * QH2 805 * No QH 806 * TD2.1 807 * TD2.2 808 * TD1.1 809 * etc. 810 * 811 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 812 */ 813 814 815 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 816 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 817 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 818 uhci_dump_qhs(sqh->hlink); 819 else 820 DPRINTF(("No QH\n")); 821 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 822 823 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 824 uhci_dump_tds(sqh->elink); 825 else 826 DPRINTF(("No TD\n")); 827 } 828 829 void 830 uhci_dump_tds(uhci_soft_td_t *std) 831 { 832 uhci_soft_td_t *td; 833 int stop; 834 835 for(td = std; td != NULL; td = td->link.std) { 836 uhci_dump_td(td); 837 838 /* 839 * Check whether the link pointer in this TD marks 840 * the link pointer as end of queue. This avoids 841 * printing the free list in case the queue/TD has 842 * already been moved there (seatbelt). 843 */ 844 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 845 sizeof(td->td.td_link), 846 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 847 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 848 le32toh(td->td.td_link) == 0); 849 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 850 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 851 if (stop) 852 break; 853 } 854 } 855 856 Static void 857 uhci_dump_ii(uhci_intr_info_t *ii) 858 { 859 usbd_pipe_handle pipe; 860 usb_endpoint_descriptor_t *ed; 861 usbd_device_handle dev; 862 863 #ifdef DIAGNOSTIC 864 #define DONE ii->isdone 865 #else 866 #define DONE 0 867 #endif 868 if (ii == NULL) { 869 printf("ii NULL\n"); 870 return; 871 } 872 if (ii->xfer == NULL) { 873 printf("ii %p: done=%d xfer=NULL\n", 874 ii, DONE); 875 return; 876 } 877 pipe = ii->xfer->ux_pipe; 878 if (pipe == NULL) { 879 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 880 ii, DONE, ii->xfer); 881 return; 882 } 883 if (pipe->up_endpoint == NULL) { 884 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 885 ii, DONE, ii->xfer, pipe); 886 return; 887 } 888 if (pipe->up_dev == NULL) { 889 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 890 ii, DONE, ii->xfer, pipe); 891 return; 892 } 893 ed = pipe->up_endpoint->ue_edesc; 894 dev = pipe->up_dev; 895 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 896 ii, DONE, ii->xfer, dev, 897 UGETW(dev->ud_ddesc.idVendor), 898 UGETW(dev->ud_ddesc.idProduct), 899 dev->ud_addr, pipe, 900 ed->bEndpointAddress, ed->bmAttributes); 901 #undef DONE 902 } 903 904 void uhci_dump_iis(struct uhci_softc *sc); 905 void 906 uhci_dump_iis(struct uhci_softc *sc) 907 { 908 uhci_intr_info_t *ii; 909 910 printf("intr_info list:\n"); 911 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 912 uhci_dump_ii(ii); 913 } 914 915 void iidump(void); 916 void iidump(void) { uhci_dump_iis(thesc); } 917 918 #endif 919 920 /* 921 * This routine is executed periodically and simulates interrupts 922 * from the root controller interrupt pipe for port status change. 923 */ 924 void 925 uhci_poll_hub(void *addr) 926 { 927 usbd_xfer_handle xfer = addr; 928 usbd_pipe_handle pipe = xfer->ux_pipe; 929 uhci_softc_t *sc; 930 u_char *p; 931 932 DPRINTFN(20, ("uhci_poll_hub\n")); 933 934 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 935 return; /* device has detached */ 936 sc = pipe->up_dev->ud_bus->ub_hcpriv; 937 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 938 939 p = xfer->ux_buf; 940 p[0] = 0; 941 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 942 p[0] |= 1<<1; 943 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 944 p[0] |= 1<<2; 945 if (p[0] == 0) 946 /* No change, try again in a while */ 947 return; 948 949 xfer->ux_actlen = 1; 950 xfer->ux_status = USBD_NORMAL_COMPLETION; 951 mutex_enter(&sc->sc_lock); 952 usb_transfer_complete(xfer); 953 mutex_exit(&sc->sc_lock); 954 } 955 956 void 957 uhci_root_intr_done(usbd_xfer_handle xfer) 958 { 959 } 960 961 /* 962 * Let the last QH loop back to the high speed control transfer QH. 963 * This is what intel calls "bandwidth reclamation" and improves 964 * USB performance a lot for some devices. 965 * If we are already looping, just count it. 966 */ 967 void 968 uhci_add_loop(uhci_softc_t *sc) 969 { 970 #ifdef UHCI_DEBUG 971 if (uhcinoloop) 972 return; 973 #endif 974 if (++sc->sc_loops == 1) { 975 DPRINTFN(5,("uhci_start_loop: add\n")); 976 /* Note, we don't loop back the soft pointer. */ 977 sc->sc_last_qh->qh.qh_hlink = 978 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 979 usb_syncmem(&sc->sc_last_qh->dma, 980 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 981 sizeof(sc->sc_last_qh->qh.qh_hlink), 982 BUS_DMASYNC_PREWRITE); 983 } 984 } 985 986 void 987 uhci_rem_loop(uhci_softc_t *sc) 988 { 989 #ifdef UHCI_DEBUG 990 if (uhcinoloop) 991 return; 992 #endif 993 if (--sc->sc_loops == 0) { 994 DPRINTFN(5,("uhci_end_loop: remove\n")); 995 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 996 usb_syncmem(&sc->sc_last_qh->dma, 997 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 998 sizeof(sc->sc_last_qh->qh.qh_hlink), 999 BUS_DMASYNC_PREWRITE); 1000 } 1001 } 1002 1003 /* Add high speed control QH, called with lock held. */ 1004 void 1005 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1006 { 1007 uhci_soft_qh_t *eqh; 1008 1009 KASSERT(mutex_owned(&sc->sc_lock)); 1010 1011 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1012 eqh = sc->sc_hctl_end; 1013 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1014 sizeof(eqh->qh.qh_hlink), 1015 BUS_DMASYNC_POSTWRITE); 1016 sqh->hlink = eqh->hlink; 1017 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1018 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1019 BUS_DMASYNC_PREWRITE); 1020 eqh->hlink = sqh; 1021 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1022 sc->sc_hctl_end = sqh; 1023 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1024 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1025 #ifdef UHCI_CTL_LOOP 1026 uhci_add_loop(sc); 1027 #endif 1028 } 1029 1030 /* Remove high speed control QH, called with lock held. */ 1031 void 1032 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1033 { 1034 uhci_soft_qh_t *pqh; 1035 uint32_t elink; 1036 1037 KASSERT(mutex_owned(&sc->sc_lock)); 1038 1039 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1040 #ifdef UHCI_CTL_LOOP 1041 uhci_rem_loop(sc); 1042 #endif 1043 /* 1044 * The T bit should be set in the elink of the QH so that the HC 1045 * doesn't follow the pointer. This condition may fail if the 1046 * the transferred packet was short so that the QH still points 1047 * at the last used TD. 1048 * In this case we set the T bit and wait a little for the HC 1049 * to stop looking at the TD. 1050 * Note that if the TD chain is large enough, the controller 1051 * may still be looking at the chain at the end of this function. 1052 * uhci_free_std_chain() will make sure the controller stops 1053 * looking at it quickly, but until then we should not change 1054 * sqh->hlink. 1055 */ 1056 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1057 sizeof(sqh->qh.qh_elink), 1058 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1059 elink = le32toh(sqh->qh.qh_elink); 1060 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1061 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1062 if (!(elink & UHCI_PTR_T)) { 1063 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1064 usb_syncmem(&sqh->dma, 1065 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1066 sizeof(sqh->qh.qh_elink), 1067 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1068 delay(UHCI_QH_REMOVE_DELAY); 1069 } 1070 1071 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1072 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1073 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1074 pqh->hlink = sqh->hlink; 1075 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1076 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1077 sizeof(pqh->qh.qh_hlink), 1078 BUS_DMASYNC_PREWRITE); 1079 delay(UHCI_QH_REMOVE_DELAY); 1080 if (sc->sc_hctl_end == sqh) 1081 sc->sc_hctl_end = pqh; 1082 } 1083 1084 /* Add low speed control QH, called with lock held. */ 1085 void 1086 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1087 { 1088 uhci_soft_qh_t *eqh; 1089 1090 KASSERT(mutex_owned(&sc->sc_lock)); 1091 1092 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1093 eqh = sc->sc_lctl_end; 1094 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1095 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1096 sqh->hlink = eqh->hlink; 1097 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1098 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1099 BUS_DMASYNC_PREWRITE); 1100 eqh->hlink = sqh; 1101 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1102 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1103 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1104 sc->sc_lctl_end = sqh; 1105 } 1106 1107 /* Remove low speed control QH, called with lock held. */ 1108 void 1109 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1110 { 1111 uhci_soft_qh_t *pqh; 1112 uint32_t elink; 1113 1114 KASSERT(mutex_owned(&sc->sc_lock)); 1115 1116 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1117 /* See comment in uhci_remove_hs_ctrl() */ 1118 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1119 sizeof(sqh->qh.qh_elink), 1120 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1121 elink = le32toh(sqh->qh.qh_elink); 1122 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1123 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1124 if (!(elink & UHCI_PTR_T)) { 1125 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1126 usb_syncmem(&sqh->dma, 1127 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1128 sizeof(sqh->qh.qh_elink), 1129 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1130 delay(UHCI_QH_REMOVE_DELAY); 1131 } 1132 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1133 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1134 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1135 pqh->hlink = sqh->hlink; 1136 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1137 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1138 sizeof(pqh->qh.qh_hlink), 1139 BUS_DMASYNC_PREWRITE); 1140 delay(UHCI_QH_REMOVE_DELAY); 1141 if (sc->sc_lctl_end == sqh) 1142 sc->sc_lctl_end = pqh; 1143 } 1144 1145 /* Add bulk QH, called with lock held. */ 1146 void 1147 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1148 { 1149 uhci_soft_qh_t *eqh; 1150 1151 KASSERT(mutex_owned(&sc->sc_lock)); 1152 1153 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1154 eqh = sc->sc_bulk_end; 1155 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1156 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1157 sqh->hlink = eqh->hlink; 1158 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1159 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1160 BUS_DMASYNC_PREWRITE); 1161 eqh->hlink = sqh; 1162 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1163 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1164 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1165 sc->sc_bulk_end = sqh; 1166 uhci_add_loop(sc); 1167 } 1168 1169 /* Remove bulk QH, called with lock held. */ 1170 void 1171 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1172 { 1173 uhci_soft_qh_t *pqh; 1174 1175 KASSERT(mutex_owned(&sc->sc_lock)); 1176 1177 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1178 uhci_rem_loop(sc); 1179 /* See comment in uhci_remove_hs_ctrl() */ 1180 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1181 sizeof(sqh->qh.qh_elink), 1182 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1183 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1184 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1185 usb_syncmem(&sqh->dma, 1186 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1187 sizeof(sqh->qh.qh_elink), 1188 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1189 delay(UHCI_QH_REMOVE_DELAY); 1190 } 1191 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1192 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1193 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1194 pqh->hlink = sqh->hlink; 1195 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1196 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1197 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1198 delay(UHCI_QH_REMOVE_DELAY); 1199 if (sc->sc_bulk_end == sqh) 1200 sc->sc_bulk_end = pqh; 1201 } 1202 1203 Static int uhci_intr1(uhci_softc_t *); 1204 1205 int 1206 uhci_intr(void *arg) 1207 { 1208 uhci_softc_t *sc = arg; 1209 int ret = 0; 1210 1211 mutex_spin_enter(&sc->sc_intr_lock); 1212 1213 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1214 goto done; 1215 1216 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1217 #ifdef DIAGNOSTIC 1218 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1219 #endif 1220 goto done; 1221 } 1222 1223 ret = uhci_intr1(sc); 1224 1225 done: 1226 mutex_spin_exit(&sc->sc_intr_lock); 1227 return ret; 1228 } 1229 1230 int 1231 uhci_intr1(uhci_softc_t *sc) 1232 { 1233 int status; 1234 int ack; 1235 1236 #ifdef UHCI_DEBUG 1237 if (uhcidebug > 15) { 1238 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1239 uhci_dumpregs(sc); 1240 } 1241 #endif 1242 1243 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1244 1245 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1246 if (status == 0) /* The interrupt was not for us. */ 1247 return 0; 1248 1249 if (sc->sc_suspend != PWR_RESUME) { 1250 #ifdef DIAGNOSTIC 1251 printf("%s: interrupt while not operating ignored\n", 1252 device_xname(sc->sc_dev)); 1253 #endif 1254 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1255 return 0; 1256 } 1257 1258 ack = 0; 1259 if (status & UHCI_STS_USBINT) 1260 ack |= UHCI_STS_USBINT; 1261 if (status & UHCI_STS_USBEI) 1262 ack |= UHCI_STS_USBEI; 1263 if (status & UHCI_STS_RD) { 1264 ack |= UHCI_STS_RD; 1265 #ifdef UHCI_DEBUG 1266 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1267 #endif 1268 } 1269 if (status & UHCI_STS_HSE) { 1270 ack |= UHCI_STS_HSE; 1271 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1272 } 1273 if (status & UHCI_STS_HCPE) { 1274 ack |= UHCI_STS_HCPE; 1275 printf("%s: host controller process error\n", 1276 device_xname(sc->sc_dev)); 1277 } 1278 1279 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1280 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1281 /* no acknowledge needed */ 1282 if (!sc->sc_dying) { 1283 printf("%s: host controller halted\n", 1284 device_xname(sc->sc_dev)); 1285 #ifdef UHCI_DEBUG 1286 uhci_dump_all(sc); 1287 #endif 1288 } 1289 sc->sc_dying = 1; 1290 } 1291 1292 if (!ack) 1293 return 0; /* nothing to acknowledge */ 1294 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1295 1296 usb_schedsoftintr(&sc->sc_bus); 1297 1298 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1299 1300 return 1; 1301 } 1302 1303 void 1304 uhci_softintr(void *v) 1305 { 1306 struct usbd_bus *bus = v; 1307 uhci_softc_t *sc = bus->ub_hcpriv; 1308 uhci_intr_info_t *ii, *nextii; 1309 1310 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1311 1312 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1313 1314 /* 1315 * Interrupts on UHCI really suck. When the host controller 1316 * interrupts because a transfer is completed there is no 1317 * way of knowing which transfer it was. You can scan down 1318 * the TDs and QHs of the previous frame to limit the search, 1319 * but that assumes that the interrupt was not delayed by more 1320 * than 1 ms, which may not always be true (e.g. after debug 1321 * output on a slow console). 1322 * We scan all interrupt descriptors to see if any have 1323 * completed. 1324 */ 1325 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1326 nextii = LIST_NEXT(ii, list); 1327 uhci_check_intr(sc, ii); 1328 } 1329 1330 if (sc->sc_softwake) { 1331 sc->sc_softwake = 0; 1332 cv_broadcast(&sc->sc_softwake_cv); 1333 } 1334 } 1335 1336 /* Check for an interrupt. */ 1337 void 1338 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1339 { 1340 uhci_soft_td_t *std, *lstd; 1341 uint32_t status; 1342 1343 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1344 #ifdef DIAGNOSTIC 1345 if (ii == NULL) { 1346 printf("uhci_check_intr: no ii? %p\n", ii); 1347 return; 1348 } 1349 #endif 1350 if (ii->xfer->ux_status == USBD_CANCELLED || 1351 ii->xfer->ux_status == USBD_TIMEOUT) { 1352 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1353 return; 1354 } 1355 1356 if (ii->stdstart == NULL) 1357 return; 1358 lstd = ii->stdend; 1359 #ifdef DIAGNOSTIC 1360 if (lstd == NULL) { 1361 printf("uhci_check_intr: std==0\n"); 1362 return; 1363 } 1364 #endif 1365 usb_syncmem(&lstd->dma, 1366 lstd->offs + offsetof(uhci_td_t, td_status), 1367 sizeof(lstd->td.td_status), 1368 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1369 status = le32toh(lstd->td.td_status); 1370 usb_syncmem(&lstd->dma, 1371 lstd->offs + offsetof(uhci_td_t, td_status), 1372 sizeof(lstd->td.td_status), 1373 BUS_DMASYNC_PREREAD); 1374 1375 /* If the last TD is not marked active we can complete */ 1376 if (!(status & UHCI_TD_ACTIVE)) { 1377 done: 1378 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1379 callout_stop(&ii->xfer->ux_callout); 1380 uhci_idone(ii); 1381 return; 1382 } 1383 1384 /* 1385 * If the last TD is still active we need to check whether there 1386 * is an error somewhere in the middle, or whether there was a 1387 * short packet (SPD and not ACTIVE). 1388 */ 1389 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1390 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1391 usb_syncmem(&std->dma, 1392 std->offs + offsetof(uhci_td_t, td_status), 1393 sizeof(std->td.td_status), 1394 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1395 status = le32toh(std->td.td_status); 1396 usb_syncmem(&std->dma, 1397 std->offs + offsetof(uhci_td_t, td_status), 1398 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1399 1400 /* If there's an active TD the xfer isn't done. */ 1401 if (status & UHCI_TD_ACTIVE) { 1402 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1403 __func__, ii, std)); 1404 return; 1405 } 1406 1407 /* Any kind of error makes the xfer done. */ 1408 if (status & UHCI_TD_STALLED) 1409 goto done; 1410 1411 /* 1412 * If the data phase of a control transfer is short, we need 1413 * to complete the status stage 1414 */ 1415 usbd_xfer_handle xfer = ii->xfer; 1416 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1417 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1418 1419 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1420 struct uhci_pipe *upipe = 1421 (struct uhci_pipe *)xfer->ux_pipe; 1422 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1423 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1424 1425 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1426 "phase needs completion\n", __func__, ii, 1427 ii->stdstart)); 1428 1429 sqh->qh.qh_elink = 1430 htole32(stat->physaddr | UHCI_PTR_TD); 1431 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1432 BUS_DMASYNC_PREWRITE); 1433 break; 1434 } 1435 1436 /* We want short packets, and it is short: it's done */ 1437 usb_syncmem(&std->dma, 1438 std->offs + offsetof(uhci_td_t, td_token), 1439 sizeof(std->td.td_token), 1440 BUS_DMASYNC_POSTWRITE); 1441 1442 if ((status & UHCI_TD_SPD) && 1443 UHCI_TD_GET_ACTLEN(status) < 1444 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1445 goto done; 1446 } 1447 } 1448 } 1449 1450 /* Called with USB lock held. */ 1451 void 1452 uhci_idone(uhci_intr_info_t *ii) 1453 { 1454 usbd_xfer_handle xfer = ii->xfer; 1455 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1456 #ifdef DIAGNOSTIC 1457 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1458 #endif 1459 uhci_soft_td_t *std; 1460 uint32_t status = 0, nstatus; 1461 int actlen; 1462 1463 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1464 1465 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1466 #ifdef DIAGNOSTIC 1467 { 1468 /* XXX SMP? */ 1469 int s = splhigh(); 1470 if (ii->isdone) { 1471 splx(s); 1472 #ifdef UHCI_DEBUG 1473 printf("uhci_idone: ii is done!\n "); 1474 uhci_dump_ii(ii); 1475 #else 1476 printf("uhci_idone: ii=%p is done!\n", ii); 1477 #endif 1478 return; 1479 } 1480 ii->isdone = 1; 1481 splx(s); 1482 } 1483 #endif 1484 1485 if (xfer->ux_nframes != 0) { 1486 /* Isoc transfer, do things differently. */ 1487 uhci_soft_td_t **stds = upipe->u.iso.stds; 1488 int i, n, nframes, len; 1489 1490 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1491 1492 nframes = xfer->ux_nframes; 1493 actlen = 0; 1494 n = UXFER(xfer)->curframe; 1495 for (i = 0; i < nframes; i++) { 1496 std = stds[n]; 1497 #ifdef UHCI_DEBUG 1498 if (uhcidebug > 5) { 1499 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1500 uhci_dump_td(std); 1501 } 1502 #endif 1503 if (++n >= UHCI_VFRAMELIST_COUNT) 1504 n = 0; 1505 usb_syncmem(&std->dma, 1506 std->offs + offsetof(uhci_td_t, td_status), 1507 sizeof(std->td.td_status), 1508 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1509 status = le32toh(std->td.td_status); 1510 len = UHCI_TD_GET_ACTLEN(status); 1511 xfer->ux_frlengths[i] = len; 1512 actlen += len; 1513 } 1514 upipe->u.iso.inuse -= nframes; 1515 xfer->ux_actlen = actlen; 1516 xfer->ux_status = USBD_NORMAL_COMPLETION; 1517 goto end; 1518 } 1519 1520 #ifdef UHCI_DEBUG 1521 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1522 ii, xfer, upipe)); 1523 if (uhcidebug > 10) 1524 uhci_dump_tds(ii->stdstart); 1525 #endif 1526 1527 /* The transfer is done, compute actual length and status. */ 1528 actlen = 0; 1529 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1530 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1531 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1532 nstatus = le32toh(std->td.td_status); 1533 if (nstatus & UHCI_TD_ACTIVE) 1534 break; 1535 1536 status = nstatus; 1537 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1538 UHCI_TD_PID_SETUP) 1539 actlen += UHCI_TD_GET_ACTLEN(status); 1540 else { 1541 /* 1542 * UHCI will report CRCTO in addition to a STALL or NAK 1543 * for a SETUP transaction. See section 3.2.2, "TD 1544 * CONTROL AND STATUS". 1545 */ 1546 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1547 status &= ~UHCI_TD_CRCTO; 1548 } 1549 } 1550 /* If there are left over TDs we need to update the toggle. */ 1551 if (std != NULL) 1552 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1553 1554 status &= UHCI_TD_ERROR; 1555 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1556 actlen, status)); 1557 xfer->ux_actlen = actlen; 1558 if (status != 0) { 1559 #ifdef UHCI_DEBUG 1560 char sbuf[128]; 1561 1562 snprintb(sbuf, sizeof(sbuf), 1563 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1564 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status); 1565 1566 DPRINTFN((status == UHCI_TD_STALLED)*10, 1567 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1568 "status 0x%s\n", 1569 xfer->ux_pipe->up_dev->ud_addr, 1570 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1571 sbuf)); 1572 #endif 1573 1574 if (status == UHCI_TD_STALLED) 1575 xfer->ux_status = USBD_STALLED; 1576 else 1577 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1578 } else { 1579 xfer->ux_status = USBD_NORMAL_COMPLETION; 1580 } 1581 1582 end: 1583 usb_transfer_complete(xfer); 1584 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1585 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1586 } 1587 1588 /* 1589 * Called when a request does not complete. 1590 */ 1591 void 1592 uhci_timeout(void *addr) 1593 { 1594 uhci_intr_info_t *ii = addr; 1595 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1596 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe; 1597 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1598 1599 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1600 1601 if (sc->sc_dying) { 1602 mutex_enter(&sc->sc_lock); 1603 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1604 mutex_exit(&sc->sc_lock); 1605 return; 1606 } 1607 1608 /* Execute the abort in a process context. */ 1609 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1610 USB_TASKQ_MPSAFE); 1611 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1612 USB_TASKQ_HC); 1613 } 1614 1615 void 1616 uhci_timeout_task(void *addr) 1617 { 1618 usbd_xfer_handle xfer = addr; 1619 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1620 1621 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1622 1623 mutex_enter(&sc->sc_lock); 1624 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1625 mutex_exit(&sc->sc_lock); 1626 } 1627 1628 /* 1629 * Wait here until controller claims to have an interrupt. 1630 * Then call uhci_intr and return. Use timeout to avoid waiting 1631 * too long. 1632 * Only used during boot when interrupts are not enabled yet. 1633 */ 1634 void 1635 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1636 { 1637 int timo = xfer->ux_timeout; 1638 uhci_intr_info_t *ii; 1639 1640 mutex_enter(&sc->sc_lock); 1641 1642 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1643 1644 xfer->ux_status = USBD_IN_PROGRESS; 1645 for (; timo >= 0; timo--) { 1646 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1647 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1648 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1649 mutex_spin_enter(&sc->sc_intr_lock); 1650 uhci_intr1(sc); 1651 mutex_spin_exit(&sc->sc_intr_lock); 1652 if (xfer->ux_status != USBD_IN_PROGRESS) 1653 goto done; 1654 } 1655 } 1656 1657 /* Timeout */ 1658 DPRINTF(("uhci_waitintr: timeout\n")); 1659 for (ii = LIST_FIRST(&sc->sc_intrhead); 1660 ii != NULL && ii->xfer != xfer; 1661 ii = LIST_NEXT(ii, list)) 1662 ; 1663 #ifdef DIAGNOSTIC 1664 if (ii == NULL) 1665 panic("uhci_waitintr: lost intr_info"); 1666 #endif 1667 uhci_idone(ii); 1668 1669 done: 1670 mutex_exit(&sc->sc_lock); 1671 } 1672 1673 void 1674 uhci_poll(struct usbd_bus *bus) 1675 { 1676 uhci_softc_t *sc = bus->ub_hcpriv; 1677 1678 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1679 mutex_spin_enter(&sc->sc_intr_lock); 1680 uhci_intr1(sc); 1681 mutex_spin_exit(&sc->sc_intr_lock); 1682 } 1683 } 1684 1685 void 1686 uhci_reset(uhci_softc_t *sc) 1687 { 1688 int n; 1689 1690 UHCICMD(sc, UHCI_CMD_HCRESET); 1691 /* The reset bit goes low when the controller is done. */ 1692 for (n = 0; n < UHCI_RESET_TIMEOUT && 1693 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1694 usb_delay_ms(&sc->sc_bus, 1); 1695 if (n >= UHCI_RESET_TIMEOUT) 1696 printf("%s: controller did not reset\n", 1697 device_xname(sc->sc_dev)); 1698 } 1699 1700 usbd_status 1701 uhci_run(uhci_softc_t *sc, int run, int locked) 1702 { 1703 int n, running; 1704 uint16_t cmd; 1705 1706 run = run != 0; 1707 if (!locked) 1708 mutex_spin_enter(&sc->sc_intr_lock); 1709 DPRINTF(("uhci_run: setting run=%d\n", run)); 1710 cmd = UREAD2(sc, UHCI_CMD); 1711 if (run) 1712 cmd |= UHCI_CMD_RS; 1713 else 1714 cmd &= ~UHCI_CMD_RS; 1715 UHCICMD(sc, cmd); 1716 for(n = 0; n < 10; n++) { 1717 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1718 /* return when we've entered the state we want */ 1719 if (run == running) { 1720 if (!locked) 1721 mutex_spin_exit(&sc->sc_intr_lock); 1722 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1723 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1724 return USBD_NORMAL_COMPLETION; 1725 } 1726 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1727 } 1728 if (!locked) 1729 mutex_spin_exit(&sc->sc_intr_lock); 1730 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1731 run ? "start" : "stop"); 1732 return USBD_IOERROR; 1733 } 1734 1735 /* 1736 * Memory management routines. 1737 * uhci_alloc_std allocates TDs 1738 * uhci_alloc_sqh allocates QHs 1739 * These two routines do their own free list management, 1740 * partly for speed, partly because allocating DMAable memory 1741 * has page size granularaity so much memory would be wasted if 1742 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1743 */ 1744 1745 uhci_soft_td_t * 1746 uhci_alloc_std(uhci_softc_t *sc) 1747 { 1748 uhci_soft_td_t *std; 1749 usbd_status err; 1750 int i, offs; 1751 usb_dma_t dma; 1752 1753 if (sc->sc_freetds == NULL) { 1754 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1755 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1756 UHCI_TD_ALIGN, &dma); 1757 if (err) 1758 return 0; 1759 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1760 offs = i * UHCI_STD_SIZE; 1761 std = KERNADDR(&dma, offs); 1762 std->physaddr = DMAADDR(&dma, offs); 1763 std->dma = dma; 1764 std->offs = offs; 1765 std->link.std = sc->sc_freetds; 1766 sc->sc_freetds = std; 1767 } 1768 } 1769 std = sc->sc_freetds; 1770 sc->sc_freetds = std->link.std; 1771 memset(&std->td, 0, sizeof(uhci_td_t)); 1772 return std; 1773 } 1774 1775 void 1776 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1777 { 1778 #ifdef DIAGNOSTIC 1779 #define TD_IS_FREE 0x12345678 1780 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1781 printf("uhci_free_std: freeing free TD %p\n", std); 1782 return; 1783 } 1784 std->td.td_token = htole32(TD_IS_FREE); 1785 #endif 1786 std->link.std = sc->sc_freetds; 1787 sc->sc_freetds = std; 1788 } 1789 1790 uhci_soft_qh_t * 1791 uhci_alloc_sqh(uhci_softc_t *sc) 1792 { 1793 uhci_soft_qh_t *sqh; 1794 usbd_status err; 1795 int i, offs; 1796 usb_dma_t dma; 1797 1798 if (sc->sc_freeqhs == NULL) { 1799 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1800 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1801 UHCI_QH_ALIGN, &dma); 1802 if (err) 1803 return 0; 1804 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1805 offs = i * UHCI_SQH_SIZE; 1806 sqh = KERNADDR(&dma, offs); 1807 sqh->physaddr = DMAADDR(&dma, offs); 1808 sqh->dma = dma; 1809 sqh->offs = offs; 1810 sqh->hlink = sc->sc_freeqhs; 1811 sc->sc_freeqhs = sqh; 1812 } 1813 } 1814 sqh = sc->sc_freeqhs; 1815 sc->sc_freeqhs = sqh->hlink; 1816 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1817 return sqh; 1818 } 1819 1820 void 1821 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1822 { 1823 sqh->hlink = sc->sc_freeqhs; 1824 sc->sc_freeqhs = sqh; 1825 } 1826 1827 void 1828 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1829 uhci_soft_td_t *stdend) 1830 { 1831 uhci_soft_td_t *p; 1832 uint32_t td_link; 1833 1834 /* 1835 * to avoid race condition with the controller which may be looking 1836 * at this chain, we need to first invalidate all links, and 1837 * then wait for the controller to move to another queue 1838 */ 1839 for (p = std; p != stdend; p = p->link.std) { 1840 usb_syncmem(&p->dma, 1841 p->offs + offsetof(uhci_td_t, td_link), 1842 sizeof(p->td.td_link), 1843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1844 td_link = le32toh(p->td.td_link); 1845 usb_syncmem(&p->dma, 1846 p->offs + offsetof(uhci_td_t, td_link), 1847 sizeof(p->td.td_link), 1848 BUS_DMASYNC_PREREAD); 1849 if ((td_link & UHCI_PTR_T) == 0) { 1850 p->td.td_link = htole32(UHCI_PTR_T); 1851 usb_syncmem(&p->dma, 1852 p->offs + offsetof(uhci_td_t, td_link), 1853 sizeof(p->td.td_link), 1854 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1855 } 1856 } 1857 delay(UHCI_QH_REMOVE_DELAY); 1858 1859 for (; std != stdend; std = p) { 1860 p = std->link.std; 1861 uhci_free_std(sc, std); 1862 } 1863 } 1864 1865 usbd_status 1866 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1867 int rd, uint16_t flags, usb_dma_t *dma, 1868 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1869 { 1870 uhci_soft_td_t *p, *lastp; 1871 uhci_physaddr_t lastlink; 1872 int i, ntd, l, tog, maxp; 1873 uint32_t status; 1874 int addr = upipe->pipe.up_dev->ud_addr; 1875 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1876 1877 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1878 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1879 upipe->pipe.up_dev->ud_speed, flags)); 1880 1881 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1882 1883 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1884 if (maxp == 0) { 1885 printf("uhci_alloc_std_chain: maxp=0\n"); 1886 return USBD_INVAL; 1887 } 1888 ntd = (len + maxp - 1) / maxp; 1889 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1890 ntd++; 1891 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1892 if (ntd == 0) { 1893 *sp = *ep = 0; 1894 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1895 return USBD_NORMAL_COMPLETION; 1896 } 1897 tog = upipe->nexttoggle; 1898 if (ntd % 2 == 0) 1899 tog ^= 1; 1900 upipe->nexttoggle = tog ^ 1; 1901 lastp = NULL; 1902 lastlink = UHCI_PTR_T; 1903 ntd--; 1904 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1905 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1906 status |= UHCI_TD_LS; 1907 if (flags & USBD_SHORT_XFER_OK) 1908 status |= UHCI_TD_SPD; 1909 usb_syncmem(dma, 0, len, 1910 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1911 for (i = ntd; i >= 0; i--) { 1912 p = uhci_alloc_std(sc); 1913 if (p == NULL) { 1914 KASSERT(lastp != NULL); 1915 uhci_free_std_chain(sc, lastp, NULL); 1916 return USBD_NOMEM; 1917 } 1918 p->link.std = lastp; 1919 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1920 lastp = p; 1921 lastlink = p->physaddr; 1922 p->td.td_status = htole32(status); 1923 if (i == ntd) { 1924 /* last TD */ 1925 l = len % maxp; 1926 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1927 l = maxp; 1928 *ep = p; 1929 } else 1930 l = maxp; 1931 p->td.td_token = 1932 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1933 UHCI_TD_OUT(l, endpt, addr, tog)); 1934 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1935 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1936 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1937 tog ^= 1; 1938 } 1939 *sp = lastp; 1940 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 1941 upipe->nexttoggle)); 1942 return USBD_NORMAL_COMPLETION; 1943 } 1944 1945 void 1946 uhci_device_clear_toggle(usbd_pipe_handle pipe) 1947 { 1948 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1949 upipe->nexttoggle = 0; 1950 } 1951 1952 void 1953 uhci_noop(usbd_pipe_handle pipe) 1954 { 1955 } 1956 1957 usbd_status 1958 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 1959 { 1960 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1961 usbd_status err; 1962 1963 /* Insert last in queue. */ 1964 mutex_enter(&sc->sc_lock); 1965 err = usb_insert_transfer(xfer); 1966 mutex_exit(&sc->sc_lock); 1967 if (err) 1968 return err; 1969 1970 /* 1971 * Pipe isn't running (otherwise err would be USBD_INPROG), 1972 * so start it first. 1973 */ 1974 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1975 } 1976 1977 usbd_status 1978 uhci_device_bulk_start(usbd_xfer_handle xfer) 1979 { 1980 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1981 usbd_device_handle dev = upipe->pipe.up_dev; 1982 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1983 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 1984 uhci_soft_td_t *data, *dataend; 1985 uhci_soft_qh_t *sqh; 1986 usbd_status err; 1987 int len, isread, endpt; 1988 1989 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 1990 xfer, xfer->ux_length, xfer->ux_flags, ii)); 1991 1992 if (sc->sc_dying) 1993 return USBD_IOERROR; 1994 1995 #ifdef DIAGNOSTIC 1996 if (xfer->ux_rqflags & URQ_REQUEST) 1997 panic("uhci_device_bulk_transfer: a request"); 1998 #endif 1999 2000 mutex_enter(&sc->sc_lock); 2001 2002 len = xfer->ux_length; 2003 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2004 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2005 sqh = upipe->u.bulk.sqh; 2006 2007 upipe->u.bulk.isread = isread; 2008 upipe->u.bulk.length = len; 2009 2010 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2011 &xfer->ux_dmabuf, &data, &dataend); 2012 if (err) { 2013 mutex_exit(&sc->sc_lock); 2014 return err; 2015 } 2016 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2017 usb_syncmem(&dataend->dma, 2018 dataend->offs + offsetof(uhci_td_t, td_status), 2019 sizeof(dataend->td.td_status), 2020 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2021 2022 2023 #ifdef UHCI_DEBUG 2024 if (uhcidebug > 8) { 2025 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2026 uhci_dump_tds(data); 2027 } 2028 #endif 2029 2030 /* Set up interrupt info. */ 2031 ii->xfer = xfer; 2032 ii->stdstart = data; 2033 ii->stdend = dataend; 2034 #ifdef DIAGNOSTIC 2035 if (!ii->isdone) { 2036 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2037 } 2038 ii->isdone = 0; 2039 #endif 2040 2041 sqh->elink = data; 2042 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2043 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2044 2045 uhci_add_bulk(sc, sqh); 2046 uhci_add_intr_info(sc, ii); 2047 2048 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2049 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2050 uhci_timeout, ii); 2051 } 2052 xfer->ux_status = USBD_IN_PROGRESS; 2053 2054 #ifdef UHCI_DEBUG 2055 if (uhcidebug > 10) { 2056 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2057 uhci_dump_tds(data); 2058 } 2059 #endif 2060 2061 if (sc->sc_bus.ub_usepolling) 2062 uhci_waitintr(sc, xfer); 2063 2064 mutex_exit(&sc->sc_lock); 2065 return USBD_IN_PROGRESS; 2066 } 2067 2068 /* Abort a device bulk request. */ 2069 void 2070 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2071 { 2072 #ifdef DIAGNOSTIC 2073 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2074 #endif 2075 2076 KASSERT(mutex_owned(&sc->sc_lock)); 2077 2078 DPRINTF(("uhci_device_bulk_abort:\n")); 2079 uhci_abort_xfer(xfer, USBD_CANCELLED); 2080 } 2081 2082 /* 2083 * Abort a device request. 2084 * If this routine is called at splusb() it guarantees that the request 2085 * will be removed from the hardware scheduling and that the callback 2086 * for it will be called with USBD_CANCELLED status. 2087 * It's impossible to guarantee that the requested transfer will not 2088 * have happened since the hardware runs concurrently. 2089 * If the transaction has already happened we rely on the ordinary 2090 * interrupt processing to process it. 2091 * XXX This is most probably wrong. 2092 * XXXMRG this doesn't make sense anymore. 2093 */ 2094 void 2095 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2096 { 2097 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2098 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2099 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2100 uhci_soft_td_t *std; 2101 int wake; 2102 2103 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2104 2105 KASSERT(mutex_owned(&sc->sc_lock)); 2106 ASSERT_SLEEPABLE(); 2107 2108 if (sc->sc_dying) { 2109 /* If we're dying, just do the software part. */ 2110 xfer->ux_status = status; /* make software ignore it */ 2111 callout_stop(&xfer->ux_callout); 2112 usb_transfer_complete(xfer); 2113 return; 2114 } 2115 2116 /* 2117 * If an abort is already in progress then just wait for it to 2118 * complete and return. 2119 */ 2120 if (xfer->ux_hcflags & UXFER_ABORTING) { 2121 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2122 #ifdef DIAGNOSTIC 2123 if (status == USBD_TIMEOUT) 2124 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2125 #endif 2126 /* Override the status which might be USBD_TIMEOUT. */ 2127 xfer->ux_status = status; 2128 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2129 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2130 while (xfer->ux_hcflags & UXFER_ABORTING) 2131 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2132 goto done; 2133 } 2134 xfer->ux_hcflags |= UXFER_ABORTING; 2135 2136 /* 2137 * Step 1: Make interrupt routine and hardware ignore xfer. 2138 */ 2139 xfer->ux_status = status; /* make software ignore it */ 2140 callout_stop(&xfer->ux_callout); 2141 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2142 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2143 usb_syncmem(&std->dma, 2144 std->offs + offsetof(uhci_td_t, td_status), 2145 sizeof(std->td.td_status), 2146 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2147 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2148 usb_syncmem(&std->dma, 2149 std->offs + offsetof(uhci_td_t, td_status), 2150 sizeof(std->td.td_status), 2151 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2152 } 2153 2154 /* 2155 * Step 2: Wait until we know hardware has finished any possible 2156 * use of the xfer. Also make sure the soft interrupt routine 2157 * has run. 2158 */ 2159 /* Hardware finishes in 1ms */ 2160 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2161 sc->sc_softwake = 1; 2162 usb_schedsoftintr(&sc->sc_bus); 2163 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2164 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2165 2166 /* 2167 * Step 3: Execute callback. 2168 */ 2169 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2170 #ifdef DIAGNOSTIC 2171 ii->isdone = 1; 2172 #endif 2173 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2174 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2175 usb_transfer_complete(xfer); 2176 if (wake) 2177 cv_broadcast(&xfer->ux_hccv); 2178 done: 2179 KASSERT(mutex_owned(&sc->sc_lock)); 2180 } 2181 2182 /* Close a device bulk pipe. */ 2183 void 2184 uhci_device_bulk_close(usbd_pipe_handle pipe) 2185 { 2186 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2187 usbd_device_handle dev = upipe->pipe.up_dev; 2188 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2189 2190 KASSERT(mutex_owned(&sc->sc_lock)); 2191 2192 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2193 2194 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2195 } 2196 2197 usbd_status 2198 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2199 { 2200 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2201 usbd_status err; 2202 2203 /* Insert last in queue. */ 2204 mutex_enter(&sc->sc_lock); 2205 err = usb_insert_transfer(xfer); 2206 mutex_exit(&sc->sc_lock); 2207 if (err) 2208 return err; 2209 2210 /* 2211 * Pipe isn't running (otherwise err would be USBD_INPROG), 2212 * so start it first. 2213 */ 2214 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2215 } 2216 2217 usbd_status 2218 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2219 { 2220 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2221 usbd_status err; 2222 2223 if (sc->sc_dying) 2224 return USBD_IOERROR; 2225 2226 #ifdef DIAGNOSTIC 2227 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2228 panic("uhci_device_ctrl_transfer: not a request"); 2229 #endif 2230 2231 mutex_enter(&sc->sc_lock); 2232 err = uhci_device_request(xfer); 2233 mutex_exit(&sc->sc_lock); 2234 if (err) 2235 return err; 2236 2237 if (sc->sc_bus.ub_usepolling) 2238 uhci_waitintr(sc, xfer); 2239 return USBD_IN_PROGRESS; 2240 } 2241 2242 usbd_status 2243 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2244 { 2245 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2246 usbd_status err; 2247 2248 /* Insert last in queue. */ 2249 mutex_enter(&sc->sc_lock); 2250 err = usb_insert_transfer(xfer); 2251 mutex_exit(&sc->sc_lock); 2252 if (err) 2253 return err; 2254 2255 /* 2256 * Pipe isn't running (otherwise err would be USBD_INPROG), 2257 * so start it first. 2258 */ 2259 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2260 } 2261 2262 usbd_status 2263 uhci_device_intr_start(usbd_xfer_handle xfer) 2264 { 2265 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2266 usbd_device_handle dev = upipe->pipe.up_dev; 2267 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2268 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2269 uhci_soft_td_t *data, *dataend; 2270 uhci_soft_qh_t *sqh; 2271 usbd_status err; 2272 int isread, endpt; 2273 int i; 2274 2275 if (sc->sc_dying) 2276 return USBD_IOERROR; 2277 2278 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2279 xfer, xfer->ux_length, xfer->ux_flags)); 2280 2281 #ifdef DIAGNOSTIC 2282 if (xfer->ux_rqflags & URQ_REQUEST) 2283 panic("uhci_device_intr_transfer: a request"); 2284 #endif 2285 2286 mutex_enter(&sc->sc_lock); 2287 2288 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2289 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2290 2291 upipe->u.intr.isread = isread; 2292 2293 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2294 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2295 &dataend); 2296 if (err) { 2297 mutex_exit(&sc->sc_lock); 2298 return err; 2299 } 2300 2301 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2302 usb_syncmem(&dataend->dma, 2303 dataend->offs + offsetof(uhci_td_t, td_status), 2304 sizeof(dataend->td.td_status), 2305 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2306 2307 #ifdef UHCI_DEBUG 2308 if (uhcidebug > 10) { 2309 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2310 uhci_dump_tds(data); 2311 uhci_dump_qh(upipe->u.intr.qhs[0]); 2312 } 2313 #endif 2314 2315 /* Set up interrupt info. */ 2316 ii->xfer = xfer; 2317 ii->stdstart = data; 2318 ii->stdend = dataend; 2319 #ifdef DIAGNOSTIC 2320 if (!ii->isdone) { 2321 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2322 } 2323 ii->isdone = 0; 2324 #endif 2325 2326 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2327 upipe->u.intr.qhs[0])); 2328 for (i = 0; i < upipe->u.intr.npoll; i++) { 2329 sqh = upipe->u.intr.qhs[i]; 2330 sqh->elink = data; 2331 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2332 usb_syncmem(&sqh->dma, 2333 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2334 sizeof(sqh->qh.qh_elink), 2335 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2336 } 2337 uhci_add_intr_info(sc, ii); 2338 xfer->ux_status = USBD_IN_PROGRESS; 2339 mutex_exit(&sc->sc_lock); 2340 2341 #ifdef UHCI_DEBUG 2342 if (uhcidebug > 10) { 2343 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2344 uhci_dump_tds(data); 2345 uhci_dump_qh(upipe->u.intr.qhs[0]); 2346 } 2347 #endif 2348 2349 return USBD_IN_PROGRESS; 2350 } 2351 2352 /* Abort a device control request. */ 2353 void 2354 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2355 { 2356 #ifdef DIAGNOSTIC 2357 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2358 #endif 2359 2360 KASSERT(mutex_owned(&sc->sc_lock)); 2361 2362 DPRINTF(("uhci_device_ctrl_abort:\n")); 2363 uhci_abort_xfer(xfer, USBD_CANCELLED); 2364 } 2365 2366 /* Close a device control pipe. */ 2367 void 2368 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2369 { 2370 } 2371 2372 /* Abort a device interrupt request. */ 2373 void 2374 uhci_device_intr_abort(usbd_xfer_handle xfer) 2375 { 2376 #ifdef DIAGNOSTIC 2377 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2378 #endif 2379 2380 KASSERT(mutex_owned(&sc->sc_lock)); 2381 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2382 2383 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2384 2385 uhci_abort_xfer(xfer, USBD_CANCELLED); 2386 } 2387 2388 /* Close a device interrupt pipe. */ 2389 void 2390 uhci_device_intr_close(usbd_pipe_handle pipe) 2391 { 2392 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2393 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2394 int i, npoll; 2395 2396 KASSERT(mutex_owned(&sc->sc_lock)); 2397 2398 /* Unlink descriptors from controller data structures. */ 2399 npoll = upipe->u.intr.npoll; 2400 for (i = 0; i < npoll; i++) 2401 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2402 2403 /* 2404 * We now have to wait for any activity on the physical 2405 * descriptors to stop. 2406 */ 2407 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2408 2409 for(i = 0; i < npoll; i++) 2410 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2411 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2412 2413 /* XXX free other resources */ 2414 } 2415 2416 usbd_status 2417 uhci_device_request(usbd_xfer_handle xfer) 2418 { 2419 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2420 usb_device_request_t *req = &xfer->ux_request; 2421 usbd_device_handle dev = upipe->pipe.up_dev; 2422 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2423 int addr = dev->ud_addr; 2424 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2425 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2426 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2427 uhci_soft_qh_t *sqh; 2428 int len; 2429 uint32_t ls; 2430 usbd_status err; 2431 int isread; 2432 2433 KASSERT(mutex_owned(&sc->sc_lock)); 2434 2435 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2436 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2437 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2438 UGETW(req->wIndex), UGETW(req->wLength), 2439 addr, endpt)); 2440 2441 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2442 isread = req->bmRequestType & UT_READ; 2443 len = UGETW(req->wLength); 2444 2445 setup = upipe->u.ctl.setup; 2446 stat = upipe->u.ctl.stat; 2447 sqh = upipe->u.ctl.sqh; 2448 2449 /* Set up data transaction */ 2450 if (len != 0) { 2451 upipe->nexttoggle = 1; 2452 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2453 &xfer->ux_dmabuf, &data, &dataend); 2454 if (err) 2455 return err; 2456 next = data; 2457 dataend->link.std = stat; 2458 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2459 usb_syncmem(&dataend->dma, 2460 dataend->offs + offsetof(uhci_td_t, td_link), 2461 sizeof(dataend->td.td_link), 2462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2463 } else { 2464 next = stat; 2465 } 2466 upipe->u.ctl.length = len; 2467 2468 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2469 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2470 2471 setup->link.std = next; 2472 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2473 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2474 UHCI_TD_ACTIVE); 2475 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2476 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2477 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2479 2480 stat->link.std = NULL; 2481 stat->td.td_link = htole32(UHCI_PTR_T); 2482 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2483 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2484 stat->td.td_token = 2485 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2486 UHCI_TD_IN (0, endpt, addr, 1)); 2487 stat->td.td_buffer = htole32(0); 2488 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2489 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2490 2491 #ifdef UHCI_DEBUG 2492 if (uhcidebug > 10) { 2493 DPRINTF(("uhci_device_request: before transfer\n")); 2494 uhci_dump_tds(setup); 2495 } 2496 #endif 2497 2498 /* Set up interrupt info. */ 2499 ii->xfer = xfer; 2500 ii->stdstart = setup; 2501 ii->stdend = stat; 2502 #ifdef DIAGNOSTIC 2503 if (!ii->isdone) { 2504 printf("uhci_device_request: not done, ii=%p\n", ii); 2505 } 2506 ii->isdone = 0; 2507 #endif 2508 2509 sqh->elink = setup; 2510 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2511 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2512 2513 if (dev->ud_speed == USB_SPEED_LOW) 2514 uhci_add_ls_ctrl(sc, sqh); 2515 else 2516 uhci_add_hs_ctrl(sc, sqh); 2517 uhci_add_intr_info(sc, ii); 2518 #ifdef UHCI_DEBUG 2519 if (uhcidebug > 12) { 2520 uhci_soft_td_t *std; 2521 uhci_soft_qh_t *xqh; 2522 uhci_soft_qh_t *sxqh; 2523 int maxqh = 0; 2524 uhci_physaddr_t link; 2525 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2526 for (std = sc->sc_vframes[0].htd, link = 0; 2527 (link & UHCI_PTR_QH) == 0; 2528 std = std->link.std) { 2529 link = le32toh(std->td.td_link); 2530 uhci_dump_td(std); 2531 } 2532 sxqh = (uhci_soft_qh_t *)std; 2533 uhci_dump_qh(sxqh); 2534 for (xqh = sxqh; 2535 xqh != NULL; 2536 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2537 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2538 uhci_dump_qh(xqh); 2539 } 2540 DPRINTF(("Enqueued QH:\n")); 2541 uhci_dump_qh(sqh); 2542 uhci_dump_tds(sqh->elink); 2543 } 2544 #endif 2545 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2546 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2547 uhci_timeout, ii); 2548 } 2549 xfer->ux_status = USBD_IN_PROGRESS; 2550 2551 return USBD_NORMAL_COMPLETION; 2552 } 2553 2554 usbd_status 2555 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2556 { 2557 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2558 usbd_status err; 2559 2560 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2561 2562 /* Put it on our queue, */ 2563 mutex_enter(&sc->sc_lock); 2564 err = usb_insert_transfer(xfer); 2565 mutex_exit(&sc->sc_lock); 2566 2567 /* bail out on error, */ 2568 if (err && err != USBD_IN_PROGRESS) 2569 return err; 2570 2571 /* XXX should check inuse here */ 2572 2573 /* insert into schedule, */ 2574 uhci_device_isoc_enter(xfer); 2575 2576 /* and start if the pipe wasn't running */ 2577 if (!err) 2578 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2579 2580 return err; 2581 } 2582 2583 void 2584 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2585 { 2586 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2587 usbd_device_handle dev = upipe->pipe.up_dev; 2588 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2589 struct iso *iso = &upipe->u.iso; 2590 uhci_soft_td_t *std; 2591 uint32_t buf, len, status, offs; 2592 int i, next, nframes; 2593 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2594 2595 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2596 "nframes=%d\n", 2597 iso->inuse, iso->next, xfer, xfer->ux_nframes)); 2598 2599 if (sc->sc_dying) 2600 return; 2601 2602 if (xfer->ux_status == USBD_IN_PROGRESS) { 2603 /* This request has already been entered into the frame list */ 2604 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2605 /* XXX */ 2606 } 2607 2608 #ifdef DIAGNOSTIC 2609 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2610 printf("uhci_device_isoc_enter: overflow!\n"); 2611 #endif 2612 2613 next = iso->next; 2614 if (next == -1) { 2615 /* Not in use yet, schedule it a few frames ahead. */ 2616 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2617 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2618 } 2619 2620 xfer->ux_status = USBD_IN_PROGRESS; 2621 UXFER(xfer)->curframe = next; 2622 2623 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2624 offs = 0; 2625 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2626 UHCI_TD_ACTIVE | 2627 UHCI_TD_IOS); 2628 nframes = xfer->ux_nframes; 2629 mutex_enter(&sc->sc_lock); 2630 for (i = 0; i < nframes; i++) { 2631 std = iso->stds[next]; 2632 if (++next >= UHCI_VFRAMELIST_COUNT) 2633 next = 0; 2634 len = xfer->ux_frlengths[i]; 2635 std->td.td_buffer = htole32(buf); 2636 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2637 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2638 if (i == nframes - 1) 2639 status |= UHCI_TD_IOC; 2640 std->td.td_status = htole32(status); 2641 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2642 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2643 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2644 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2645 #ifdef UHCI_DEBUG 2646 if (uhcidebug > 5) { 2647 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2648 uhci_dump_td(std); 2649 } 2650 #endif 2651 buf += len; 2652 offs += len; 2653 } 2654 iso->next = next; 2655 iso->inuse += xfer->ux_nframes; 2656 2657 mutex_exit(&sc->sc_lock); 2658 } 2659 2660 usbd_status 2661 uhci_device_isoc_start(usbd_xfer_handle xfer) 2662 { 2663 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2664 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2665 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2666 uhci_soft_td_t *end; 2667 int i; 2668 2669 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2670 2671 mutex_enter(&sc->sc_lock); 2672 2673 if (sc->sc_dying) { 2674 mutex_exit(&sc->sc_lock); 2675 return USBD_IOERROR; 2676 } 2677 2678 #ifdef DIAGNOSTIC 2679 if (xfer->ux_status != USBD_IN_PROGRESS) 2680 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2681 #endif 2682 2683 /* Find the last TD */ 2684 i = UXFER(xfer)->curframe + xfer->ux_nframes; 2685 if (i >= UHCI_VFRAMELIST_COUNT) 2686 i -= UHCI_VFRAMELIST_COUNT; 2687 end = upipe->u.iso.stds[i]; 2688 2689 #ifdef DIAGNOSTIC 2690 if (end == NULL) { 2691 printf("uhci_device_isoc_start: end == NULL\n"); 2692 return USBD_INVAL; 2693 } 2694 #endif 2695 2696 /* Set up interrupt info. */ 2697 ii->xfer = xfer; 2698 ii->stdstart = end; 2699 ii->stdend = end; 2700 #ifdef DIAGNOSTIC 2701 if (!ii->isdone) 2702 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2703 ii->isdone = 0; 2704 #endif 2705 uhci_add_intr_info(sc, ii); 2706 2707 mutex_exit(&sc->sc_lock); 2708 2709 return USBD_IN_PROGRESS; 2710 } 2711 2712 void 2713 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2714 { 2715 #ifdef DIAGNOSTIC 2716 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2717 #endif 2718 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2719 uhci_soft_td_t **stds = upipe->u.iso.stds; 2720 uhci_soft_td_t *std; 2721 int i, n, nframes, maxlen, len; 2722 2723 KASSERT(mutex_owned(&sc->sc_lock)); 2724 2725 /* Transfer is already done. */ 2726 if (xfer->ux_status != USBD_NOT_STARTED && 2727 xfer->ux_status != USBD_IN_PROGRESS) { 2728 return; 2729 } 2730 2731 /* Give xfer the requested abort code. */ 2732 xfer->ux_status = USBD_CANCELLED; 2733 2734 /* make hardware ignore it, */ 2735 nframes = xfer->ux_nframes; 2736 n = UXFER(xfer)->curframe; 2737 maxlen = 0; 2738 for (i = 0; i < nframes; i++) { 2739 std = stds[n]; 2740 usb_syncmem(&std->dma, 2741 std->offs + offsetof(uhci_td_t, td_status), 2742 sizeof(std->td.td_status), 2743 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2744 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2745 usb_syncmem(&std->dma, 2746 std->offs + offsetof(uhci_td_t, td_status), 2747 sizeof(std->td.td_status), 2748 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2749 usb_syncmem(&std->dma, 2750 std->offs + offsetof(uhci_td_t, td_token), 2751 sizeof(std->td.td_token), 2752 BUS_DMASYNC_POSTWRITE); 2753 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2754 if (len > maxlen) 2755 maxlen = len; 2756 if (++n >= UHCI_VFRAMELIST_COUNT) 2757 n = 0; 2758 } 2759 2760 /* and wait until we are sure the hardware has finished. */ 2761 delay(maxlen); 2762 2763 #ifdef DIAGNOSTIC 2764 UXFER(xfer)->iinfo.isdone = 1; 2765 #endif 2766 /* Run callback and remove from interrupt list. */ 2767 usb_transfer_complete(xfer); 2768 2769 KASSERT(mutex_owned(&sc->sc_lock)); 2770 } 2771 2772 void 2773 uhci_device_isoc_close(usbd_pipe_handle pipe) 2774 { 2775 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2776 usbd_device_handle dev = upipe->pipe.up_dev; 2777 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2778 uhci_soft_td_t *std, *vstd; 2779 struct iso *iso; 2780 int i; 2781 2782 KASSERT(mutex_owned(&sc->sc_lock)); 2783 2784 /* 2785 * Make sure all TDs are marked as inactive. 2786 * Wait for completion. 2787 * Unschedule. 2788 * Deallocate. 2789 */ 2790 iso = &upipe->u.iso; 2791 2792 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2793 std = iso->stds[i]; 2794 usb_syncmem(&std->dma, 2795 std->offs + offsetof(uhci_td_t, td_status), 2796 sizeof(std->td.td_status), 2797 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2798 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2799 usb_syncmem(&std->dma, 2800 std->offs + offsetof(uhci_td_t, td_status), 2801 sizeof(std->td.td_status), 2802 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2803 } 2804 /* wait for completion */ 2805 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2806 2807 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2808 std = iso->stds[i]; 2809 for (vstd = sc->sc_vframes[i].htd; 2810 vstd != NULL && vstd->link.std != std; 2811 vstd = vstd->link.std) 2812 ; 2813 if (vstd == NULL) { 2814 /*panic*/ 2815 printf("uhci_device_isoc_close: %p not found\n", std); 2816 mutex_exit(&sc->sc_lock); 2817 return; 2818 } 2819 vstd->link = std->link; 2820 usb_syncmem(&std->dma, 2821 std->offs + offsetof(uhci_td_t, td_link), 2822 sizeof(std->td.td_link), 2823 BUS_DMASYNC_POSTWRITE); 2824 vstd->td.td_link = std->td.td_link; 2825 usb_syncmem(&vstd->dma, 2826 vstd->offs + offsetof(uhci_td_t, td_link), 2827 sizeof(vstd->td.td_link), 2828 BUS_DMASYNC_PREWRITE); 2829 uhci_free_std(sc, std); 2830 } 2831 2832 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2833 } 2834 2835 usbd_status 2836 uhci_setup_isoc(usbd_pipe_handle pipe) 2837 { 2838 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2839 usbd_device_handle dev = upipe->pipe.up_dev; 2840 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2841 int addr = upipe->pipe.up_dev->ud_addr; 2842 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2843 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2844 uhci_soft_td_t *std, *vstd; 2845 uint32_t token; 2846 struct iso *iso; 2847 int i; 2848 2849 iso = &upipe->u.iso; 2850 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2851 sizeof (uhci_soft_td_t *), 2852 KM_SLEEP); 2853 if (iso->stds == NULL) 2854 return USBD_NOMEM; 2855 2856 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2857 UHCI_TD_OUT(0, endpt, addr, 0); 2858 2859 mutex_enter(&sc->sc_lock); 2860 2861 /* Allocate the TDs and mark as inactive; */ 2862 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2863 std = uhci_alloc_std(sc); 2864 if (std == 0) 2865 goto bad; 2866 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2867 std->td.td_token = htole32(token); 2868 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2869 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2870 iso->stds[i] = std; 2871 } 2872 2873 /* Insert TDs into schedule. */ 2874 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2875 std = iso->stds[i]; 2876 vstd = sc->sc_vframes[i].htd; 2877 usb_syncmem(&vstd->dma, 2878 vstd->offs + offsetof(uhci_td_t, td_link), 2879 sizeof(vstd->td.td_link), 2880 BUS_DMASYNC_POSTWRITE); 2881 std->link = vstd->link; 2882 std->td.td_link = vstd->td.td_link; 2883 usb_syncmem(&std->dma, 2884 std->offs + offsetof(uhci_td_t, td_link), 2885 sizeof(std->td.td_link), 2886 BUS_DMASYNC_PREWRITE); 2887 vstd->link.std = std; 2888 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2889 usb_syncmem(&vstd->dma, 2890 vstd->offs + offsetof(uhci_td_t, td_link), 2891 sizeof(vstd->td.td_link), 2892 BUS_DMASYNC_PREWRITE); 2893 } 2894 mutex_exit(&sc->sc_lock); 2895 2896 iso->next = -1; 2897 iso->inuse = 0; 2898 2899 return USBD_NORMAL_COMPLETION; 2900 2901 bad: 2902 while (--i >= 0) 2903 uhci_free_std(sc, iso->stds[i]); 2904 mutex_exit(&sc->sc_lock); 2905 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2906 return USBD_NOMEM; 2907 } 2908 2909 void 2910 uhci_device_isoc_done(usbd_xfer_handle xfer) 2911 { 2912 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2913 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2914 int i, offs; 2915 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2916 2917 2918 DPRINTFN(4, ("uhci_isoc_done: length=%d, ux_state=0x%08x\n", 2919 xfer->ux_actlen, xfer->ux_state)); 2920 2921 if (ii->xfer != xfer) 2922 /* Not on interrupt list, ignore it. */ 2923 return; 2924 2925 if (!uhci_active_intr_info(ii)) 2926 return; 2927 2928 #ifdef DIAGNOSTIC 2929 if (ii->stdend == NULL) { 2930 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2931 #ifdef UHCI_DEBUG 2932 uhci_dump_ii(ii); 2933 #endif 2934 return; 2935 } 2936 #endif 2937 2938 /* Turn off the interrupt since it is active even if the TD is not. */ 2939 usb_syncmem(&ii->stdend->dma, 2940 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2941 sizeof(ii->stdend->td.td_status), 2942 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2943 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2944 usb_syncmem(&ii->stdend->dma, 2945 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2946 sizeof(ii->stdend->td.td_status), 2947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2948 2949 uhci_del_intr_info(ii); /* remove from active list */ 2950 2951 offs = 0; 2952 for (i = 0; i < xfer->ux_nframes; i++) { 2953 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2954 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2955 offs += xfer->ux_frlengths[i]; 2956 } 2957 } 2958 2959 void 2960 uhci_device_intr_done(usbd_xfer_handle xfer) 2961 { 2962 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2963 uhci_softc_t *sc = ii->sc; 2964 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2965 uhci_soft_qh_t *sqh; 2966 int i, npoll, isread; 2967 2968 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->ux_actlen)); 2969 2970 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2971 2972 npoll = upipe->u.intr.npoll; 2973 for(i = 0; i < npoll; i++) { 2974 sqh = upipe->u.intr.qhs[i]; 2975 sqh->elink = NULL; 2976 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 2977 usb_syncmem(&sqh->dma, 2978 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2979 sizeof(sqh->qh.qh_elink), 2980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2981 } 2982 uhci_free_std_chain(sc, ii->stdstart, NULL); 2983 2984 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2985 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2986 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2987 2988 /* XXX Wasteful. */ 2989 if (xfer->ux_pipe->up_repeat) { 2990 uhci_soft_td_t *data, *dataend; 2991 2992 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 2993 2994 /* This alloc cannot fail since we freed the chain above. */ 2995 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 2996 upipe->u.intr.isread, xfer->ux_flags, 2997 &xfer->ux_dmabuf, &data, &dataend); 2998 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2999 usb_syncmem(&dataend->dma, 3000 dataend->offs + offsetof(uhci_td_t, td_status), 3001 sizeof(dataend->td.td_status), 3002 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3003 3004 #ifdef UHCI_DEBUG 3005 if (uhcidebug > 10) { 3006 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3007 uhci_dump_tds(data); 3008 uhci_dump_qh(upipe->u.intr.qhs[0]); 3009 } 3010 #endif 3011 3012 ii->stdstart = data; 3013 ii->stdend = dataend; 3014 #ifdef DIAGNOSTIC 3015 if (!ii->isdone) { 3016 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3017 } 3018 ii->isdone = 0; 3019 #endif 3020 for (i = 0; i < npoll; i++) { 3021 sqh = upipe->u.intr.qhs[i]; 3022 sqh->elink = data; 3023 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3024 usb_syncmem(&sqh->dma, 3025 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3026 sizeof(sqh->qh.qh_elink), 3027 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3028 } 3029 xfer->ux_status = USBD_IN_PROGRESS; 3030 /* The ii is already on the examined list, just leave it. */ 3031 } else { 3032 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3033 if (uhci_active_intr_info(ii)) 3034 uhci_del_intr_info(ii); 3035 } 3036 } 3037 3038 /* Deallocate request data structures */ 3039 void 3040 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3041 { 3042 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3043 uhci_softc_t *sc = ii->sc; 3044 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3045 int len = UGETW(xfer->ux_request.wLength); 3046 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3047 3048 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3049 3050 #ifdef DIAGNOSTIC 3051 if (!(xfer->ux_rqflags & URQ_REQUEST)) 3052 panic("uhci_device_ctrl_done: not a request"); 3053 #endif 3054 3055 if (!uhci_active_intr_info(ii)) 3056 return; 3057 3058 uhci_del_intr_info(ii); /* remove from active list */ 3059 3060 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3061 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3062 else 3063 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3064 3065 if (upipe->u.ctl.length != 0) 3066 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3067 3068 if (len) { 3069 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3070 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3071 } 3072 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3073 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3074 3075 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->ux_actlen)); 3076 } 3077 3078 /* Deallocate request data structures */ 3079 void 3080 uhci_device_bulk_done(usbd_xfer_handle xfer) 3081 { 3082 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3083 uhci_softc_t *sc = ii->sc; 3084 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3085 3086 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3087 xfer, ii, sc, upipe)); 3088 3089 KASSERT(mutex_owned(&sc->sc_lock)); 3090 3091 if (!uhci_active_intr_info(ii)) 3092 return; 3093 3094 uhci_del_intr_info(ii); /* remove from active list */ 3095 3096 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3097 3098 uhci_free_std_chain(sc, ii->stdstart, NULL); 3099 3100 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->ux_actlen)); 3101 } 3102 3103 /* Add interrupt QH, called with vflock. */ 3104 void 3105 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3106 { 3107 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3108 uhci_soft_qh_t *eqh; 3109 3110 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3111 3112 eqh = vf->eqh; 3113 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3114 sizeof(eqh->qh.qh_hlink), 3115 BUS_DMASYNC_POSTWRITE); 3116 sqh->hlink = eqh->hlink; 3117 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3118 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3119 sizeof(sqh->qh.qh_hlink), 3120 BUS_DMASYNC_PREWRITE); 3121 eqh->hlink = sqh; 3122 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3123 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3124 sizeof(eqh->qh.qh_hlink), 3125 BUS_DMASYNC_PREWRITE); 3126 vf->eqh = sqh; 3127 vf->bandwidth++; 3128 } 3129 3130 /* Remove interrupt QH. */ 3131 void 3132 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3133 { 3134 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3135 uhci_soft_qh_t *pqh; 3136 3137 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3138 3139 /* See comment in uhci_remove_ctrl() */ 3140 3141 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3142 sizeof(sqh->qh.qh_elink), 3143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3144 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3145 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3146 usb_syncmem(&sqh->dma, 3147 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3148 sizeof(sqh->qh.qh_elink), 3149 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3150 delay(UHCI_QH_REMOVE_DELAY); 3151 } 3152 3153 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3154 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3155 sizeof(sqh->qh.qh_hlink), 3156 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3157 pqh->hlink = sqh->hlink; 3158 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3159 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3160 sizeof(pqh->qh.qh_hlink), 3161 BUS_DMASYNC_PREWRITE); 3162 delay(UHCI_QH_REMOVE_DELAY); 3163 if (vf->eqh == sqh) 3164 vf->eqh = pqh; 3165 vf->bandwidth--; 3166 } 3167 3168 usbd_status 3169 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3170 { 3171 uhci_soft_qh_t *sqh; 3172 int i, npoll; 3173 u_int bestbw, bw, bestoffs, offs; 3174 3175 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3176 if (ival == 0) { 3177 printf("uhci_device_setintr: 0 interval\n"); 3178 return USBD_INVAL; 3179 } 3180 3181 if (ival > UHCI_VFRAMELIST_COUNT) 3182 ival = UHCI_VFRAMELIST_COUNT; 3183 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3184 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3185 3186 upipe->u.intr.npoll = npoll; 3187 upipe->u.intr.qhs = 3188 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3189 if (upipe->u.intr.qhs == NULL) 3190 return USBD_NOMEM; 3191 3192 /* 3193 * Figure out which offset in the schedule that has most 3194 * bandwidth left over. 3195 */ 3196 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3197 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3198 for (bw = i = 0; i < npoll; i++) 3199 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3200 if (bw < bestbw) { 3201 bestbw = bw; 3202 bestoffs = offs; 3203 } 3204 } 3205 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3206 3207 mutex_enter(&sc->sc_lock); 3208 for(i = 0; i < npoll; i++) { 3209 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3210 sqh->elink = NULL; 3211 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3212 usb_syncmem(&sqh->dma, 3213 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3214 sizeof(sqh->qh.qh_elink), 3215 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3216 sqh->pos = MOD(i * ival + bestoffs); 3217 } 3218 #undef MOD 3219 3220 /* Enter QHs into the controller data structures. */ 3221 for(i = 0; i < npoll; i++) 3222 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3223 mutex_exit(&sc->sc_lock); 3224 3225 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3226 return USBD_NORMAL_COMPLETION; 3227 } 3228 3229 /* Open a new pipe. */ 3230 usbd_status 3231 uhci_open(usbd_pipe_handle pipe) 3232 { 3233 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3234 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3235 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3236 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3237 usbd_status err = USBD_NOMEM; 3238 int ival; 3239 3240 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3241 pipe, pipe->up_dev->ud_addr, 3242 ed->bEndpointAddress, bus->ub_rhaddr)); 3243 3244 if (sc->sc_dying) 3245 return USBD_IOERROR; 3246 3247 upipe->aborting = 0; 3248 /* toggle state needed for bulk endpoints */ 3249 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3250 3251 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3252 switch (ed->bEndpointAddress) { 3253 case USB_CONTROL_ENDPOINT: 3254 pipe->up_methods = &roothub_ctrl_methods; 3255 break; 3256 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3257 pipe->up_methods = &uhci_root_intr_methods; 3258 break; 3259 default: 3260 return USBD_INVAL; 3261 } 3262 } else { 3263 switch (ed->bmAttributes & UE_XFERTYPE) { 3264 case UE_CONTROL: 3265 pipe->up_methods = &uhci_device_ctrl_methods; 3266 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3267 if (upipe->u.ctl.sqh == NULL) 3268 goto bad; 3269 upipe->u.ctl.setup = uhci_alloc_std(sc); 3270 if (upipe->u.ctl.setup == NULL) { 3271 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3272 goto bad; 3273 } 3274 upipe->u.ctl.stat = uhci_alloc_std(sc); 3275 if (upipe->u.ctl.stat == NULL) { 3276 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3277 uhci_free_std(sc, upipe->u.ctl.setup); 3278 goto bad; 3279 } 3280 err = usb_allocmem(&sc->sc_bus, 3281 sizeof(usb_device_request_t), 3282 0, &upipe->u.ctl.reqdma); 3283 if (err) { 3284 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3285 uhci_free_std(sc, upipe->u.ctl.setup); 3286 uhci_free_std(sc, upipe->u.ctl.stat); 3287 goto bad; 3288 } 3289 break; 3290 case UE_INTERRUPT: 3291 pipe->up_methods = &uhci_device_intr_methods; 3292 ival = pipe->up_interval; 3293 if (ival == USBD_DEFAULT_INTERVAL) 3294 ival = ed->bInterval; 3295 return uhci_device_setintr(sc, upipe, ival); 3296 case UE_ISOCHRONOUS: 3297 pipe->up_methods = &uhci_device_isoc_methods; 3298 return uhci_setup_isoc(pipe); 3299 case UE_BULK: 3300 pipe->up_methods = &uhci_device_bulk_methods; 3301 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3302 if (upipe->u.bulk.sqh == NULL) 3303 goto bad; 3304 break; 3305 } 3306 } 3307 return USBD_NORMAL_COMPLETION; 3308 3309 bad: 3310 return USBD_NOMEM; 3311 } 3312 3313 /* 3314 * Data structures and routines to emulate the root hub. 3315 */ 3316 /* 3317 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3318 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3319 * should not be used by the USB subsystem. As we cannot issue a 3320 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3321 * will be enabled as part of the reset. 3322 * 3323 * On the VT83C572, the port cannot be successfully enabled until the 3324 * outstanding "port enable change" and "connection status change" 3325 * events have been reset. 3326 */ 3327 Static usbd_status 3328 uhci_portreset(uhci_softc_t *sc, int index) 3329 { 3330 int lim, port, x; 3331 3332 if (index == 1) 3333 port = UHCI_PORTSC1; 3334 else if (index == 2) 3335 port = UHCI_PORTSC2; 3336 else 3337 return USBD_IOERROR; 3338 3339 x = URWMASK(UREAD2(sc, port)); 3340 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3341 3342 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3343 3344 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3345 index, UREAD2(sc, port))); 3346 3347 x = URWMASK(UREAD2(sc, port)); 3348 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3349 3350 delay(100); 3351 3352 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3353 index, UREAD2(sc, port))); 3354 3355 x = URWMASK(UREAD2(sc, port)); 3356 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3357 3358 for (lim = 10; --lim > 0;) { 3359 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3360 3361 x = UREAD2(sc, port); 3362 3363 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3364 index, lim, x)); 3365 3366 if (!(x & UHCI_PORTSC_CCS)) { 3367 /* 3368 * No device is connected (or was disconnected 3369 * during reset). Consider the port reset. 3370 * The delay must be long enough to ensure on 3371 * the initial iteration that the device 3372 * connection will have been registered. 50ms 3373 * appears to be sufficient, but 20ms is not. 3374 */ 3375 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3376 index, lim)); 3377 break; 3378 } 3379 3380 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3381 /* 3382 * Port enabled changed and/or connection 3383 * status changed were set. Reset either or 3384 * both raised flags (by writing a 1 to that 3385 * bit), and wait again for state to settle. 3386 */ 3387 UWRITE2(sc, port, URWMASK(x) | 3388 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3389 continue; 3390 } 3391 3392 if (x & UHCI_PORTSC_PE) 3393 /* Port is enabled */ 3394 break; 3395 3396 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3397 } 3398 3399 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3400 index, UREAD2(sc, port))); 3401 3402 if (lim <= 0) { 3403 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3404 return USBD_TIMEOUT; 3405 } 3406 3407 sc->sc_isreset = 1; 3408 return USBD_NORMAL_COMPLETION; 3409 } 3410 3411 Static int 3412 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3413 void *buf, int buflen) 3414 { 3415 uhci_softc_t *sc = bus->ub_hcpriv; 3416 int port, x; 3417 int status, change, totlen = 0; 3418 uint16_t len, value, index; 3419 usb_port_status_t ps; 3420 usbd_status err; 3421 3422 if (sc->sc_dying) 3423 return -1; 3424 3425 DPRINTFN(2,("%s: type=0x%02x request=%02x\n", __func__, 3426 req->bmRequestType, req->bRequest)); 3427 3428 len = UGETW(req->wLength); 3429 value = UGETW(req->wValue); 3430 index = UGETW(req->wIndex); 3431 3432 #define C(x,y) ((x) | ((y) << 8)) 3433 switch (C(req->bRequest, req->bmRequestType)) { 3434 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3435 DPRINTFN(2,("%s: wValue=0x%04x\n", __func__, value)); 3436 if (len == 0) 3437 break; 3438 switch (value) { 3439 case C(0, UDESC_DEVICE): { 3440 usb_device_descriptor_t devd; 3441 3442 totlen = min(buflen, sizeof(devd)); 3443 memcpy(&devd, buf, totlen); 3444 USETW(devd.idVendor, sc->sc_id_vendor); 3445 memcpy(buf, &devd, totlen); 3446 break; 3447 } 3448 case C(1, UDESC_STRING): 3449 #define sd ((usb_string_descriptor_t *)buf) 3450 /* Vendor */ 3451 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3452 break; 3453 case C(2, UDESC_STRING): 3454 /* Product */ 3455 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3456 break; 3457 #undef sd 3458 default: 3459 /* default from usbroothub */ 3460 return buflen; 3461 } 3462 break; 3463 3464 /* Hub requests */ 3465 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3466 break; 3467 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3468 DPRINTFN(3, ("%s: UR_CLEAR_PORT_FEATURE " 3469 "port=%d feature=%d\n", __func__, 3470 index, value)); 3471 if (index == 1) 3472 port = UHCI_PORTSC1; 3473 else if (index == 2) 3474 port = UHCI_PORTSC2; 3475 else { 3476 return -1; 3477 } 3478 switch(value) { 3479 case UHF_PORT_ENABLE: 3480 x = URWMASK(UREAD2(sc, port)); 3481 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3482 break; 3483 case UHF_PORT_SUSPEND: 3484 x = URWMASK(UREAD2(sc, port)); 3485 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3486 break; 3487 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3488 /* see USB2 spec ch. 7.1.7.7 */ 3489 usb_delay_ms(&sc->sc_bus, 20); 3490 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3491 /* 10ms resume delay must be provided by caller */ 3492 break; 3493 case UHF_PORT_RESET: 3494 x = URWMASK(UREAD2(sc, port)); 3495 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3496 break; 3497 case UHF_C_PORT_CONNECTION: 3498 x = URWMASK(UREAD2(sc, port)); 3499 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3500 break; 3501 case UHF_C_PORT_ENABLE: 3502 x = URWMASK(UREAD2(sc, port)); 3503 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3504 break; 3505 case UHF_C_PORT_OVER_CURRENT: 3506 x = URWMASK(UREAD2(sc, port)); 3507 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3508 break; 3509 case UHF_C_PORT_RESET: 3510 sc->sc_isreset = 0; 3511 break; 3512 case UHF_PORT_CONNECTION: 3513 case UHF_PORT_OVER_CURRENT: 3514 case UHF_PORT_POWER: 3515 case UHF_PORT_LOW_SPEED: 3516 case UHF_C_PORT_SUSPEND: 3517 default: 3518 return -1; 3519 } 3520 break; 3521 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3522 if (index == 1) 3523 port = UHCI_PORTSC1; 3524 else if (index == 2) 3525 port = UHCI_PORTSC2; 3526 else { 3527 return -1; 3528 } 3529 if (len > 0) { 3530 *(uint8_t *)buf = 3531 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3532 UHCI_PORTSC_LS_SHIFT; 3533 totlen = 1; 3534 } 3535 break; 3536 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3537 if (len == 0) 3538 break; 3539 if ((value & 0xff) != 0) { 3540 return -1; 3541 } 3542 usb_hub_descriptor_t hubd; 3543 3544 totlen = min(buflen, sizeof(hubd)); 3545 memcpy(&hubd, buf, totlen); 3546 hubd.bNbrPorts = 2; 3547 memcpy(buf, &hubd, totlen); 3548 break; 3549 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3550 if (len != 4) { 3551 return -1; 3552 } 3553 memset(buf, 0, len); 3554 totlen = len; 3555 break; 3556 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3557 if (index == 1) 3558 port = UHCI_PORTSC1; 3559 else if (index == 2) 3560 port = UHCI_PORTSC2; 3561 else { 3562 return -1; 3563 } 3564 if (len != 4) { 3565 return -1; 3566 } 3567 x = UREAD2(sc, port); 3568 status = change = 0; 3569 if (x & UHCI_PORTSC_CCS) 3570 status |= UPS_CURRENT_CONNECT_STATUS; 3571 if (x & UHCI_PORTSC_CSC) 3572 change |= UPS_C_CONNECT_STATUS; 3573 if (x & UHCI_PORTSC_PE) 3574 status |= UPS_PORT_ENABLED; 3575 if (x & UHCI_PORTSC_POEDC) 3576 change |= UPS_C_PORT_ENABLED; 3577 if (x & UHCI_PORTSC_OCI) 3578 status |= UPS_OVERCURRENT_INDICATOR; 3579 if (x & UHCI_PORTSC_OCIC) 3580 change |= UPS_C_OVERCURRENT_INDICATOR; 3581 if (x & UHCI_PORTSC_SUSP) 3582 status |= UPS_SUSPEND; 3583 if (x & UHCI_PORTSC_LSDA) 3584 status |= UPS_LOW_SPEED; 3585 status |= UPS_PORT_POWER; 3586 if (sc->sc_isreset) 3587 change |= UPS_C_PORT_RESET; 3588 USETW(ps.wPortStatus, status); 3589 USETW(ps.wPortChange, change); 3590 totlen = min(len, sizeof(ps)); 3591 memcpy(buf, &ps, totlen); 3592 break; 3593 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3594 return -1; 3595 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3596 break; 3597 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3598 if (index == 1) 3599 port = UHCI_PORTSC1; 3600 else if (index == 2) 3601 port = UHCI_PORTSC2; 3602 else { 3603 return -1; 3604 } 3605 switch(value) { 3606 case UHF_PORT_ENABLE: 3607 x = URWMASK(UREAD2(sc, port)); 3608 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3609 break; 3610 case UHF_PORT_SUSPEND: 3611 x = URWMASK(UREAD2(sc, port)); 3612 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3613 break; 3614 case UHF_PORT_RESET: 3615 err = uhci_portreset(sc, index); 3616 if (err != USBD_NORMAL_COMPLETION) 3617 return -1; 3618 return 0; 3619 case UHF_PORT_POWER: 3620 /* Pretend we turned on power */ 3621 return 0; 3622 case UHF_C_PORT_CONNECTION: 3623 case UHF_C_PORT_ENABLE: 3624 case UHF_C_PORT_OVER_CURRENT: 3625 case UHF_PORT_CONNECTION: 3626 case UHF_PORT_OVER_CURRENT: 3627 case UHF_PORT_LOW_SPEED: 3628 case UHF_C_PORT_SUSPEND: 3629 case UHF_C_PORT_RESET: 3630 default: 3631 return -1; 3632 } 3633 break; 3634 default: 3635 /* default from usbroothub */ 3636 return buflen; 3637 } 3638 3639 return totlen; 3640 } 3641 3642 /* Abort a root interrupt request. */ 3643 void 3644 uhci_root_intr_abort(usbd_xfer_handle xfer) 3645 { 3646 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3647 3648 KASSERT(mutex_owned(&sc->sc_lock)); 3649 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3650 3651 callout_stop(&sc->sc_poll_handle); 3652 sc->sc_intr_xfer = NULL; 3653 3654 xfer->ux_status = USBD_CANCELLED; 3655 #ifdef DIAGNOSTIC 3656 UXFER(xfer)->iinfo.isdone = 1; 3657 #endif 3658 usb_transfer_complete(xfer); 3659 } 3660 3661 usbd_status 3662 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3663 { 3664 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3665 usbd_status err; 3666 3667 /* Insert last in queue. */ 3668 mutex_enter(&sc->sc_lock); 3669 err = usb_insert_transfer(xfer); 3670 mutex_exit(&sc->sc_lock); 3671 if (err) 3672 return err; 3673 3674 /* 3675 * Pipe isn't running (otherwise err would be USBD_INPROG), 3676 * start first 3677 */ 3678 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3679 } 3680 3681 /* Start a transfer on the root interrupt pipe */ 3682 usbd_status 3683 uhci_root_intr_start(usbd_xfer_handle xfer) 3684 { 3685 usbd_pipe_handle pipe = xfer->ux_pipe; 3686 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3687 unsigned int ival; 3688 3689 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3690 xfer, xfer->ux_length, xfer->ux_flags)); 3691 3692 if (sc->sc_dying) 3693 return USBD_IOERROR; 3694 3695 /* XXX temporary variable needed to avoid gcc3 warning */ 3696 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3697 sc->sc_ival = mstohz(ival); 3698 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3699 sc->sc_intr_xfer = xfer; 3700 return USBD_IN_PROGRESS; 3701 } 3702 3703 /* Close the root interrupt pipe. */ 3704 void 3705 uhci_root_intr_close(usbd_pipe_handle pipe) 3706 { 3707 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3708 3709 KASSERT(mutex_owned(&sc->sc_lock)); 3710 3711 callout_stop(&sc->sc_poll_handle); 3712 sc->sc_intr_xfer = NULL; 3713 DPRINTF(("uhci_root_intr_close\n")); 3714 } 3715
Indexes created Tue Sep 30 20:09:53 GMT 2025