uhci.c revision 1.264.4.34
1 /* $NetBSD: uhci.c,v 1.264.4.34 2015/09/22 12:06:01 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.34 2015/09/22 12:06:01 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Isochronous pipe */ 158 struct isoc { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } isoc; 162 }; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static usbd_status uhci_run(uhci_softc_t *, int, int); 169 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 170 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, 180 uhci_soft_td_t *, uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 182 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 183 uhci_soft_td_t **, uhci_soft_td_t **); 184 Static void uhci_poll_hub(void *); 185 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 186 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 187 Static void uhci_idone(uhci_intr_info_t *); 188 189 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 190 191 Static void uhci_timeout(void *); 192 Static void uhci_timeout_task(void *); 193 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 194 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 195 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 197 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 198 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_add_loop(uhci_softc_t *); 200 Static void uhci_rem_loop(uhci_softc_t *); 201 202 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 203 Static void uhci_device_isoc_enter(struct usbd_xfer *); 204 205 Static struct usbd_xfer * uhci_allocx(struct usbd_bus *); 206 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 207 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 208 Static int uhci_roothub_ctrl(struct usbd_bus *, 209 usb_device_request_t *, void *, int); 210 211 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 212 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 213 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 214 Static void uhci_device_ctrl_close(struct usbd_pipe *); 215 Static void uhci_device_ctrl_done(struct usbd_xfer *); 216 217 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 218 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 219 Static void uhci_device_intr_abort(struct usbd_xfer *); 220 Static void uhci_device_intr_close(struct usbd_pipe *); 221 Static void uhci_device_intr_done(struct usbd_xfer *); 222 223 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 224 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 225 Static void uhci_device_bulk_abort(struct usbd_xfer *); 226 Static void uhci_device_bulk_close(struct usbd_pipe *); 227 Static void uhci_device_bulk_done(struct usbd_xfer *); 228 229 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 230 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 231 Static void uhci_device_isoc_abort(struct usbd_xfer *); 232 Static void uhci_device_isoc_close(struct usbd_pipe *); 233 Static void uhci_device_isoc_done(struct usbd_xfer *); 234 235 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 236 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 237 Static void uhci_root_intr_abort(struct usbd_xfer *); 238 Static void uhci_root_intr_close(struct usbd_pipe *); 239 Static void uhci_root_intr_done(struct usbd_xfer *); 240 241 Static usbd_status uhci_open(struct usbd_pipe *); 242 Static void uhci_poll(struct usbd_bus *); 243 Static void uhci_softintr(void *); 244 245 Static usbd_status uhci_device_request(struct usbd_xfer *); 246 247 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 248 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static usbd_status uhci_device_setintr(uhci_softc_t *, 250 struct uhci_pipe *, int); 251 252 Static void uhci_device_clear_toggle(struct usbd_pipe *); 253 Static void uhci_noop(struct usbd_pipe *); 254 255 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 256 uhci_soft_qh_t *); 257 258 #ifdef UHCI_DEBUG 259 Static void uhci_dump_all(uhci_softc_t *); 260 Static void uhci_dumpregs(uhci_softc_t *); 261 Static void uhci_dump_qhs(uhci_soft_qh_t *); 262 Static void uhci_dump_qh(uhci_soft_qh_t *); 263 Static void uhci_dump_tds(uhci_soft_td_t *); 264 Static void uhci_dump_td(uhci_soft_td_t *); 265 Static void uhci_dump_ii(uhci_intr_info_t *); 266 void uhci_dump(void); 267 #endif 268 269 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 270 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 271 #define UWRITE1(sc, r, x) \ 272 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 273 } while (/*CONSTCOND*/0) 274 #define UWRITE2(sc, r, x) \ 275 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 276 } while (/*CONSTCOND*/0) 277 #define UWRITE4(sc, r, x) \ 278 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 279 } while (/*CONSTCOND*/0) 280 static __inline uint8_t 281 UREAD1(uhci_softc_t *sc, bus_size_t r) 282 { 283 284 UBARR(sc); 285 return bus_space_read_1(sc->iot, sc->ioh, r); 286 } 287 288 static __inline uint16_t 289 UREAD2(uhci_softc_t *sc, bus_size_t r) 290 { 291 292 UBARR(sc); 293 return bus_space_read_2(sc->iot, sc->ioh, r); 294 } 295 296 #ifdef UHCI_DEBUG 297 static __inline uint32_t 298 UREAD4(uhci_softc_t *sc, bus_size_t r) 299 { 300 301 UBARR(sc); 302 return bus_space_read_4(sc->iot, sc->ioh, r); 303 } 304 #endif 305 306 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 307 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 308 309 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 310 311 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 312 313 const struct usbd_bus_methods uhci_bus_methods = { 314 .ubm_open = uhci_open, 315 .ubm_softint = uhci_softintr, 316 .ubm_dopoll = uhci_poll, 317 .ubm_allocx = uhci_allocx, 318 .ubm_freex = uhci_freex, 319 .ubm_getlock = uhci_get_lock, 320 .ubm_rhctrl = uhci_roothub_ctrl, 321 }; 322 323 const struct usbd_pipe_methods uhci_root_intr_methods = { 324 .upm_transfer = uhci_root_intr_transfer, 325 .upm_start = uhci_root_intr_start, 326 .upm_abort = uhci_root_intr_abort, 327 .upm_close = uhci_root_intr_close, 328 .upm_cleartoggle = uhci_noop, 329 .upm_done = uhci_root_intr_done, 330 }; 331 332 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 333 .upm_transfer = uhci_device_ctrl_transfer, 334 .upm_start = uhci_device_ctrl_start, 335 .upm_abort = uhci_device_ctrl_abort, 336 .upm_close = uhci_device_ctrl_close, 337 .upm_cleartoggle = uhci_noop, 338 .upm_done = uhci_device_ctrl_done, 339 }; 340 341 const struct usbd_pipe_methods uhci_device_intr_methods = { 342 .upm_transfer = uhci_device_intr_transfer, 343 .upm_start = uhci_device_intr_start, 344 .upm_abort = uhci_device_intr_abort, 345 .upm_close = uhci_device_intr_close, 346 .upm_cleartoggle = uhci_device_clear_toggle, 347 .upm_done = uhci_device_intr_done, 348 }; 349 350 const struct usbd_pipe_methods uhci_device_bulk_methods = { 351 .upm_transfer = uhci_device_bulk_transfer, 352 .upm_start = uhci_device_bulk_start, 353 .upm_abort = uhci_device_bulk_abort, 354 .upm_close = uhci_device_bulk_close, 355 .upm_cleartoggle = uhci_device_clear_toggle, 356 .upm_done = uhci_device_bulk_done, 357 }; 358 359 const struct usbd_pipe_methods uhci_device_isoc_methods = { 360 .upm_transfer = uhci_device_isoc_transfer, 361 .upm_start = uhci_device_isoc_start, 362 .upm_abort = uhci_device_isoc_abort, 363 .upm_close = uhci_device_isoc_close, 364 .upm_cleartoggle = uhci_noop, 365 .upm_done = uhci_device_isoc_done, 366 }; 367 368 #define uhci_add_intr_info(sc, ii) \ 369 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 370 #define uhci_del_intr_info(ii) \ 371 do { \ 372 LIST_REMOVE((ii), list); \ 373 (ii)->list.le_prev = NULL; \ 374 } while (0) 375 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 376 377 static inline uhci_soft_qh_t * 378 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 379 { 380 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 381 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 382 383 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 384 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 385 usb_syncmem(&pqh->dma, 386 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 387 sizeof(pqh->qh.qh_hlink), 388 BUS_DMASYNC_POSTWRITE); 389 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 390 printf("uhci_find_prev_qh: QH not found\n"); 391 return NULL; 392 } 393 #endif 394 } 395 return pqh; 396 } 397 398 void 399 uhci_globalreset(uhci_softc_t *sc) 400 { 401 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 402 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 403 UHCICMD(sc, 0); /* do nothing */ 404 } 405 406 int 407 uhci_init(uhci_softc_t *sc) 408 { 409 usbd_status err; 410 int i, j; 411 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 412 uhci_soft_td_t *std; 413 414 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 415 416 #ifdef UHCI_DEBUG 417 thesc = sc; 418 419 if (uhcidebug > 2) 420 uhci_dumpregs(sc); 421 #endif 422 423 sc->sc_suspend = PWR_RESUME; 424 425 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 426 uhci_globalreset(sc); /* reset the controller */ 427 uhci_reset(sc); 428 429 /* Allocate and initialize real frame array. */ 430 err = usb_allocmem(&sc->sc_bus, 431 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 432 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 433 if (err) 434 return err; 435 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 436 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 437 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 438 439 /* 440 * Allocate a TD, inactive, that hangs from the last QH. 441 * This is to avoid a bug in the PIIX that makes it run berserk 442 * otherwise. 443 */ 444 std = uhci_alloc_std(sc); 445 if (std == NULL) 446 return ENOMEM; 447 std->link.std = NULL; 448 std->td.td_link = htole32(UHCI_PTR_T); 449 std->td.td_status = htole32(0); /* inactive */ 450 std->td.td_token = htole32(0); 451 std->td.td_buffer = htole32(0); 452 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 453 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 454 455 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 456 lsqh = uhci_alloc_sqh(sc); 457 if (lsqh == NULL) 458 return ENOMEM; 459 lsqh->hlink = NULL; 460 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 461 lsqh->elink = std; 462 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 463 sc->sc_last_qh = lsqh; 464 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 465 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 466 467 /* Allocate the dummy QH where bulk traffic will be queued. */ 468 bsqh = uhci_alloc_sqh(sc); 469 if (bsqh == NULL) 470 return ENOMEM; 471 bsqh->hlink = lsqh; 472 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 473 bsqh->elink = NULL; 474 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 475 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 476 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 477 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 478 479 /* Allocate dummy QH where high speed control traffic will be queued. */ 480 chsqh = uhci_alloc_sqh(sc); 481 if (chsqh == NULL) 482 return ENOMEM; 483 chsqh->hlink = bsqh; 484 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 485 chsqh->elink = NULL; 486 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 487 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 488 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 489 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 490 491 /* Allocate dummy QH where control traffic will be queued. */ 492 clsqh = uhci_alloc_sqh(sc); 493 if (clsqh == NULL) 494 return ENOMEM; 495 clsqh->hlink = chsqh; 496 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 497 clsqh->elink = NULL; 498 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 499 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 500 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 502 503 /* 504 * Make all (virtual) frame list pointers point to the interrupt 505 * queue heads and the interrupt queue heads at the control 506 * queue head and point the physical frame list to the virtual. 507 */ 508 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 509 std = uhci_alloc_std(sc); 510 sqh = uhci_alloc_sqh(sc); 511 if (std == NULL || sqh == NULL) 512 return USBD_NOMEM; 513 std->link.sqh = sqh; 514 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 515 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 516 std->td.td_token = htole32(0); 517 std->td.td_buffer = htole32(0); 518 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 sqh->hlink = clsqh; 521 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 522 sqh->elink = NULL; 523 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 524 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 525 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 526 sc->sc_vframes[i].htd = std; 527 sc->sc_vframes[i].etd = std; 528 sc->sc_vframes[i].hqh = sqh; 529 sc->sc_vframes[i].eqh = sqh; 530 for (j = i; 531 j < UHCI_FRAMELIST_COUNT; 532 j += UHCI_VFRAMELIST_COUNT) 533 sc->sc_pframes[j] = htole32(std->physaddr); 534 } 535 usb_syncmem(&sc->sc_dma, 0, 536 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 537 BUS_DMASYNC_PREWRITE); 538 539 540 LIST_INIT(&sc->sc_intrhead); 541 542 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 543 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 544 545 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 546 547 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 548 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 549 cv_init(&sc->sc_softwake_cv, "uhciab"); 550 551 /* Set up the bus struct. */ 552 sc->sc_bus.ub_methods = &uhci_bus_methods; 553 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 554 sc->sc_bus.ub_usedma = true; 555 556 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 557 558 DPRINTF("Enabling...", 0, 0, 0, 0); 559 560 err = uhci_run(sc, 1, 0); /* and here we go... */ 561 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 562 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 563 return err; 564 } 565 566 int 567 uhci_activate(device_t self, enum devact act) 568 { 569 struct uhci_softc *sc = device_private(self); 570 571 switch (act) { 572 case DVACT_DEACTIVATE: 573 sc->sc_dying = 1; 574 return 0; 575 default: 576 return EOPNOTSUPP; 577 } 578 } 579 580 void 581 uhci_childdet(device_t self, device_t child) 582 { 583 struct uhci_softc *sc = device_private(self); 584 585 KASSERT(sc->sc_child == child); 586 sc->sc_child = NULL; 587 } 588 589 int 590 uhci_detach(struct uhci_softc *sc, int flags) 591 { 592 int rv = 0; 593 594 if (sc->sc_child != NULL) 595 rv = config_detach(sc->sc_child, flags); 596 597 if (rv != 0) 598 return rv; 599 600 callout_halt(&sc->sc_poll_handle, NULL); 601 callout_destroy(&sc->sc_poll_handle); 602 603 cv_destroy(&sc->sc_softwake_cv); 604 605 mutex_destroy(&sc->sc_lock); 606 mutex_destroy(&sc->sc_intr_lock); 607 608 pool_cache_destroy(sc->sc_xferpool); 609 610 /* XXX free other data structures XXX */ 611 612 return rv; 613 } 614 615 struct usbd_xfer * 616 uhci_allocx(struct usbd_bus *bus) 617 { 618 struct uhci_softc *sc = bus->ub_hcpriv; 619 struct usbd_xfer *xfer; 620 621 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 622 if (xfer != NULL) { 623 memset(xfer, 0, sizeof(struct uhci_xfer)); 624 625 struct uhci_xfer *uxfer = UXFER(xfer); 626 uxfer->iinfo.sc = sc; 627 #ifdef DIAGNOSTIC 628 uxfer->iinfo.isdone = true; 629 xfer->ux_state = XFER_BUSY; 630 #endif 631 } 632 return xfer; 633 } 634 635 void 636 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 637 { 638 struct uhci_softc *sc = bus->ub_hcpriv; 639 struct uhci_xfer *uxfer __diagused = UXFER(xfer); 640 641 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 642 xfer->ux_state); 643 KASSERTMSG(uxfer->iinfo.isdone, "xfer %p not done\n", xfer); 644 #ifdef DIAGNOSTIC 645 xfer->ux_state = XFER_FREE; 646 #endif 647 pool_cache_put(sc->sc_xferpool, xfer); 648 } 649 650 Static void 651 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 652 { 653 struct uhci_softc *sc = bus->ub_hcpriv; 654 655 *lock = &sc->sc_lock; 656 } 657 658 659 /* 660 * Handle suspend/resume. 661 * 662 * We need to switch to polling mode here, because this routine is 663 * called from an interrupt context. This is all right since we 664 * are almost suspended anyway. 665 */ 666 bool 667 uhci_resume(device_t dv, const pmf_qual_t *qual) 668 { 669 uhci_softc_t *sc = device_private(dv); 670 int cmd; 671 672 mutex_spin_enter(&sc->sc_intr_lock); 673 674 cmd = UREAD2(sc, UHCI_CMD); 675 sc->sc_bus.ub_usepolling++; 676 UWRITE2(sc, UHCI_INTR, 0); 677 uhci_globalreset(sc); 678 uhci_reset(sc); 679 if (cmd & UHCI_CMD_RS) 680 uhci_run(sc, 0, 1); 681 682 /* restore saved state */ 683 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 684 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 685 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 686 687 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 688 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 689 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 690 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 691 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 692 UHCICMD(sc, UHCI_CMD_MAXP); 693 uhci_run(sc, 1, 1); /* and start traffic again */ 694 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 695 sc->sc_bus.ub_usepolling--; 696 if (sc->sc_intr_xfer != NULL) 697 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 698 sc->sc_intr_xfer); 699 #ifdef UHCI_DEBUG 700 if (uhcidebug > 2) 701 uhci_dumpregs(sc); 702 #endif 703 704 sc->sc_suspend = PWR_RESUME; 705 mutex_spin_exit(&sc->sc_intr_lock); 706 707 return true; 708 } 709 710 bool 711 uhci_suspend(device_t dv, const pmf_qual_t *qual) 712 { 713 uhci_softc_t *sc = device_private(dv); 714 int cmd; 715 716 mutex_spin_enter(&sc->sc_intr_lock); 717 718 cmd = UREAD2(sc, UHCI_CMD); 719 720 #ifdef UHCI_DEBUG 721 if (uhcidebug > 2) 722 uhci_dumpregs(sc); 723 #endif 724 if (sc->sc_intr_xfer != NULL) 725 callout_stop(&sc->sc_poll_handle); 726 sc->sc_suspend = PWR_SUSPEND; 727 sc->sc_bus.ub_usepolling++; 728 729 uhci_run(sc, 0, 1); /* stop the controller */ 730 cmd &= ~UHCI_CMD_RS; 731 732 /* save some state if BIOS doesn't */ 733 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 734 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 735 736 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 737 738 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 739 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 740 sc->sc_bus.ub_usepolling--; 741 742 mutex_spin_exit(&sc->sc_intr_lock); 743 744 return true; 745 } 746 747 #ifdef UHCI_DEBUG 748 Static void 749 uhci_dumpregs(uhci_softc_t *sc) 750 { 751 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 752 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 753 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 754 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 755 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 756 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 757 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 758 } 759 760 void 761 uhci_dump_td(uhci_soft_td_t *p) 762 { 763 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 764 765 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 766 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 767 768 DPRINTF("TD(%p) at %08x", p, p->physaddr, 0, 0); 769 DPRINTF(" link=0x%08x status=0x%08x " 770 "token=0x%08x buffer=0x%08x", 771 le32toh(p->td.td_link), 772 le32toh(p->td.td_status), 773 le32toh(p->td.td_token), 774 le32toh(p->td.td_buffer)); 775 776 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 777 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 778 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 779 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 780 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 781 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 782 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 783 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 784 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 785 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 786 DPRINTF("ios =%d ls =%d spd =%d", 787 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 788 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 789 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 790 DPRINTF("errcnt =%d actlen =%d pid=%02x", 791 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 792 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 793 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 794 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 795 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 796 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 797 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 798 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 799 } 800 801 void 802 uhci_dump_qh(uhci_soft_qh_t *sqh) 803 { 804 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 805 806 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 807 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 808 809 DPRINTF("QH(%p) at %08x: hlink=%08x elink=%08x", sqh, 810 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 811 le32toh(sqh->qh.qh_elink)); 812 813 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 814 } 815 816 817 #if 1 818 void 819 uhci_dump(void) 820 { 821 uhci_dump_all(thesc); 822 } 823 #endif 824 825 void 826 uhci_dump_all(uhci_softc_t *sc) 827 { 828 uhci_dumpregs(sc); 829 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 830 uhci_dump_qhs(sc->sc_lctl_start); 831 } 832 833 834 void 835 uhci_dump_qhs(uhci_soft_qh_t *sqh) 836 { 837 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 838 839 uhci_dump_qh(sqh); 840 841 /* 842 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 843 * Traverses sideways first, then down. 844 * 845 * QH1 846 * QH2 847 * No QH 848 * TD2.1 849 * TD2.2 850 * TD1.1 851 * etc. 852 * 853 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 854 */ 855 856 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 857 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 858 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 859 uhci_dump_qhs(sqh->hlink); 860 else 861 DPRINTF("No QH", 0, 0, 0, 0); 862 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 863 864 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 865 uhci_dump_tds(sqh->elink); 866 else 867 DPRINTF("No QH", 0, 0, 0, 0); 868 } 869 870 void 871 uhci_dump_tds(uhci_soft_td_t *std) 872 { 873 uhci_soft_td_t *td; 874 int stop; 875 876 for (td = std; td != NULL; td = td->link.std) { 877 uhci_dump_td(td); 878 879 /* 880 * Check whether the link pointer in this TD marks 881 * the link pointer as end of queue. This avoids 882 * printing the free list in case the queue/TD has 883 * already been moved there (seatbelt). 884 */ 885 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 886 sizeof(td->td.td_link), 887 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 888 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 889 le32toh(td->td.td_link) == 0); 890 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 891 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 892 if (stop) 893 break; 894 } 895 } 896 897 Static void 898 uhci_dump_ii(uhci_intr_info_t *ii) 899 { 900 struct usbd_pipe *pipe; 901 usb_endpoint_descriptor_t *ed; 902 struct usbd_device *dev; 903 904 #ifdef DIAGNOSTIC 905 #define DONE ii->isdone 906 #else 907 #define DONE 0 908 #endif 909 if (ii == NULL) { 910 printf("ii NULL\n"); 911 return; 912 } 913 if (ii->xfer == NULL) { 914 printf("ii %p: done=%d xfer=NULL\n", 915 ii, DONE); 916 return; 917 } 918 pipe = ii->xfer->ux_pipe; 919 if (pipe == NULL) { 920 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 921 ii, DONE, ii->xfer); 922 return; 923 } 924 if (pipe->up_endpoint == NULL) { 925 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 926 ii, DONE, ii->xfer, pipe); 927 return; 928 } 929 if (pipe->up_dev == NULL) { 930 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 931 ii, DONE, ii->xfer, pipe); 932 return; 933 } 934 ed = pipe->up_endpoint->ue_edesc; 935 dev = pipe->up_dev; 936 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 937 ii, DONE, ii->xfer, dev, 938 UGETW(dev->ud_ddesc.idVendor), 939 UGETW(dev->ud_ddesc.idProduct), 940 dev->ud_addr, pipe, 941 ed->bEndpointAddress, ed->bmAttributes); 942 #undef DONE 943 } 944 945 void uhci_dump_iis(struct uhci_softc *sc); 946 void 947 uhci_dump_iis(struct uhci_softc *sc) 948 { 949 uhci_intr_info_t *ii; 950 951 printf("intr_info list:\n"); 952 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 953 uhci_dump_ii(ii); 954 } 955 956 void iidump(void); 957 void iidump(void) { uhci_dump_iis(thesc); } 958 959 #endif 960 961 /* 962 * This routine is executed periodically and simulates interrupts 963 * from the root controller interrupt pipe for port status change. 964 */ 965 void 966 uhci_poll_hub(void *addr) 967 { 968 struct usbd_xfer *xfer = addr; 969 struct usbd_pipe *pipe = xfer->ux_pipe; 970 uhci_softc_t *sc; 971 u_char *p; 972 973 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 974 975 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 976 return; /* device has detached */ 977 sc = pipe->up_dev->ud_bus->ub_hcpriv; 978 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 979 980 p = xfer->ux_buf; 981 p[0] = 0; 982 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 983 p[0] |= 1<<1; 984 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 985 p[0] |= 1<<2; 986 if (p[0] == 0) 987 /* No change, try again in a while */ 988 return; 989 990 xfer->ux_actlen = 1; 991 xfer->ux_status = USBD_NORMAL_COMPLETION; 992 mutex_enter(&sc->sc_lock); 993 usb_transfer_complete(xfer); 994 mutex_exit(&sc->sc_lock); 995 } 996 997 void 998 uhci_root_intr_done(struct usbd_xfer *xfer) 999 { 1000 } 1001 1002 /* 1003 * Let the last QH loop back to the high speed control transfer QH. 1004 * This is what intel calls "bandwidth reclamation" and improves 1005 * USB performance a lot for some devices. 1006 * If we are already looping, just count it. 1007 */ 1008 void 1009 uhci_add_loop(uhci_softc_t *sc) 1010 { 1011 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1012 1013 #ifdef UHCI_DEBUG 1014 if (uhcinoloop) 1015 return; 1016 #endif 1017 if (++sc->sc_loops == 1) { 1018 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1019 /* Note, we don't loop back the soft pointer. */ 1020 sc->sc_last_qh->qh.qh_hlink = 1021 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1022 usb_syncmem(&sc->sc_last_qh->dma, 1023 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1024 sizeof(sc->sc_last_qh->qh.qh_hlink), 1025 BUS_DMASYNC_PREWRITE); 1026 } 1027 } 1028 1029 void 1030 uhci_rem_loop(uhci_softc_t *sc) 1031 { 1032 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1033 1034 #ifdef UHCI_DEBUG 1035 if (uhcinoloop) 1036 return; 1037 #endif 1038 if (--sc->sc_loops == 0) { 1039 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1040 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1041 usb_syncmem(&sc->sc_last_qh->dma, 1042 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1043 sizeof(sc->sc_last_qh->qh.qh_hlink), 1044 BUS_DMASYNC_PREWRITE); 1045 } 1046 } 1047 1048 /* Add high speed control QH, called with lock held. */ 1049 void 1050 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1051 { 1052 uhci_soft_qh_t *eqh; 1053 1054 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1055 1056 KASSERT(mutex_owned(&sc->sc_lock)); 1057 1058 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1059 eqh = sc->sc_hctl_end; 1060 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1061 sizeof(eqh->qh.qh_hlink), 1062 BUS_DMASYNC_POSTWRITE); 1063 sqh->hlink = eqh->hlink; 1064 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1065 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1066 BUS_DMASYNC_PREWRITE); 1067 eqh->hlink = sqh; 1068 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1069 sc->sc_hctl_end = sqh; 1070 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1071 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1072 #ifdef UHCI_CTL_LOOP 1073 uhci_add_loop(sc); 1074 #endif 1075 } 1076 1077 /* Remove high speed control QH, called with lock held. */ 1078 void 1079 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1080 { 1081 uhci_soft_qh_t *pqh; 1082 uint32_t elink; 1083 1084 KASSERT(mutex_owned(&sc->sc_lock)); 1085 1086 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1087 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1088 #ifdef UHCI_CTL_LOOP 1089 uhci_rem_loop(sc); 1090 #endif 1091 /* 1092 * The T bit should be set in the elink of the QH so that the HC 1093 * doesn't follow the pointer. This condition may fail if the 1094 * the transferred packet was short so that the QH still points 1095 * at the last used TD. 1096 * In this case we set the T bit and wait a little for the HC 1097 * to stop looking at the TD. 1098 * Note that if the TD chain is large enough, the controller 1099 * may still be looking at the chain at the end of this function. 1100 * uhci_free_std_chain() will make sure the controller stops 1101 * looking at it quickly, but until then we should not change 1102 * sqh->hlink. 1103 */ 1104 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1105 sizeof(sqh->qh.qh_elink), 1106 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1107 elink = le32toh(sqh->qh.qh_elink); 1108 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1109 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1110 if (!(elink & UHCI_PTR_T)) { 1111 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1112 usb_syncmem(&sqh->dma, 1113 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1114 sizeof(sqh->qh.qh_elink), 1115 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1116 delay(UHCI_QH_REMOVE_DELAY); 1117 } 1118 1119 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1120 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1121 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1122 pqh->hlink = sqh->hlink; 1123 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1124 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1125 sizeof(pqh->qh.qh_hlink), 1126 BUS_DMASYNC_PREWRITE); 1127 delay(UHCI_QH_REMOVE_DELAY); 1128 if (sc->sc_hctl_end == sqh) 1129 sc->sc_hctl_end = pqh; 1130 } 1131 1132 /* Add low speed control QH, called with lock held. */ 1133 void 1134 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1135 { 1136 uhci_soft_qh_t *eqh; 1137 1138 KASSERT(mutex_owned(&sc->sc_lock)); 1139 1140 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1141 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1142 1143 eqh = sc->sc_lctl_end; 1144 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1145 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1146 sqh->hlink = eqh->hlink; 1147 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1148 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1149 BUS_DMASYNC_PREWRITE); 1150 eqh->hlink = sqh; 1151 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1152 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1153 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1154 sc->sc_lctl_end = sqh; 1155 } 1156 1157 /* Remove low speed control QH, called with lock held. */ 1158 void 1159 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1160 { 1161 uhci_soft_qh_t *pqh; 1162 uint32_t elink; 1163 1164 KASSERT(mutex_owned(&sc->sc_lock)); 1165 1166 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1167 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1168 1169 /* See comment in uhci_remove_hs_ctrl() */ 1170 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1171 sizeof(sqh->qh.qh_elink), 1172 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1173 elink = le32toh(sqh->qh.qh_elink); 1174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1175 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1176 if (!(elink & UHCI_PTR_T)) { 1177 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1178 usb_syncmem(&sqh->dma, 1179 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1180 sizeof(sqh->qh.qh_elink), 1181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1182 delay(UHCI_QH_REMOVE_DELAY); 1183 } 1184 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1185 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1186 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1187 pqh->hlink = sqh->hlink; 1188 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1189 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1190 sizeof(pqh->qh.qh_hlink), 1191 BUS_DMASYNC_PREWRITE); 1192 delay(UHCI_QH_REMOVE_DELAY); 1193 if (sc->sc_lctl_end == sqh) 1194 sc->sc_lctl_end = pqh; 1195 } 1196 1197 /* Add bulk QH, called with lock held. */ 1198 void 1199 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1200 { 1201 uhci_soft_qh_t *eqh; 1202 1203 KASSERT(mutex_owned(&sc->sc_lock)); 1204 1205 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1206 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1207 1208 eqh = sc->sc_bulk_end; 1209 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1210 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1211 sqh->hlink = eqh->hlink; 1212 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1213 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1214 BUS_DMASYNC_PREWRITE); 1215 eqh->hlink = sqh; 1216 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1217 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1218 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1219 sc->sc_bulk_end = sqh; 1220 uhci_add_loop(sc); 1221 } 1222 1223 /* Remove bulk QH, called with lock held. */ 1224 void 1225 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1226 { 1227 uhci_soft_qh_t *pqh; 1228 1229 KASSERT(mutex_owned(&sc->sc_lock)); 1230 1231 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1232 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1233 1234 uhci_rem_loop(sc); 1235 /* See comment in uhci_remove_hs_ctrl() */ 1236 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1237 sizeof(sqh->qh.qh_elink), 1238 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1239 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1240 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1241 usb_syncmem(&sqh->dma, 1242 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1243 sizeof(sqh->qh.qh_elink), 1244 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1245 delay(UHCI_QH_REMOVE_DELAY); 1246 } 1247 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1248 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1249 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1250 pqh->hlink = sqh->hlink; 1251 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1252 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1253 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1254 delay(UHCI_QH_REMOVE_DELAY); 1255 if (sc->sc_bulk_end == sqh) 1256 sc->sc_bulk_end = pqh; 1257 } 1258 1259 Static int uhci_intr1(uhci_softc_t *); 1260 1261 int 1262 uhci_intr(void *arg) 1263 { 1264 uhci_softc_t *sc = arg; 1265 int ret = 0; 1266 1267 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1268 1269 mutex_spin_enter(&sc->sc_intr_lock); 1270 1271 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1272 goto done; 1273 1274 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1275 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1276 goto done; 1277 } 1278 1279 ret = uhci_intr1(sc); 1280 1281 done: 1282 mutex_spin_exit(&sc->sc_intr_lock); 1283 return ret; 1284 } 1285 1286 int 1287 uhci_intr1(uhci_softc_t *sc) 1288 { 1289 int status; 1290 int ack; 1291 1292 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1293 1294 #ifdef UHCI_DEBUG 1295 if (uhcidebug > 15) { 1296 DPRINTF("sc %p", sc, 0, 0, 0); 1297 uhci_dumpregs(sc); 1298 } 1299 #endif 1300 1301 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1302 1303 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1304 if (status == 0) /* The interrupt was not for us. */ 1305 return 0; 1306 1307 if (sc->sc_suspend != PWR_RESUME) { 1308 #ifdef DIAGNOSTIC 1309 printf("%s: interrupt while not operating ignored\n", 1310 device_xname(sc->sc_dev)); 1311 #endif 1312 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1313 return 0; 1314 } 1315 1316 ack = 0; 1317 if (status & UHCI_STS_USBINT) 1318 ack |= UHCI_STS_USBINT; 1319 if (status & UHCI_STS_USBEI) 1320 ack |= UHCI_STS_USBEI; 1321 if (status & UHCI_STS_RD) { 1322 ack |= UHCI_STS_RD; 1323 #ifdef UHCI_DEBUG 1324 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1325 #endif 1326 } 1327 if (status & UHCI_STS_HSE) { 1328 ack |= UHCI_STS_HSE; 1329 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1330 } 1331 if (status & UHCI_STS_HCPE) { 1332 ack |= UHCI_STS_HCPE; 1333 printf("%s: host controller process error\n", 1334 device_xname(sc->sc_dev)); 1335 } 1336 1337 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1338 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1339 /* no acknowledge needed */ 1340 if (!sc->sc_dying) { 1341 printf("%s: host controller halted\n", 1342 device_xname(sc->sc_dev)); 1343 #ifdef UHCI_DEBUG 1344 uhci_dump_all(sc); 1345 #endif 1346 } 1347 sc->sc_dying = 1; 1348 } 1349 1350 if (!ack) 1351 return 0; /* nothing to acknowledge */ 1352 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1353 1354 usb_schedsoftintr(&sc->sc_bus); 1355 1356 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1357 1358 return 1; 1359 } 1360 1361 void 1362 uhci_softintr(void *v) 1363 { 1364 struct usbd_bus *bus = v; 1365 uhci_softc_t *sc = bus->ub_hcpriv; 1366 uhci_intr_info_t *ii, *nextii; 1367 1368 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1369 DPRINTF("sc %p", sc, 0, 0, 0); 1370 1371 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1372 1373 /* 1374 * Interrupts on UHCI really suck. When the host controller 1375 * interrupts because a transfer is completed there is no 1376 * way of knowing which transfer it was. You can scan down 1377 * the TDs and QHs of the previous frame to limit the search, 1378 * but that assumes that the interrupt was not delayed by more 1379 * than 1 ms, which may not always be true (e.g. after debug 1380 * output on a slow console). 1381 * We scan all interrupt descriptors to see if any have 1382 * completed. 1383 */ 1384 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1385 nextii = LIST_NEXT(ii, list); 1386 uhci_check_intr(sc, ii); 1387 } 1388 1389 if (sc->sc_softwake) { 1390 sc->sc_softwake = 0; 1391 cv_broadcast(&sc->sc_softwake_cv); 1392 } 1393 } 1394 1395 /* Check for an interrupt. */ 1396 void 1397 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1398 { 1399 uhci_soft_td_t *std, *lstd; 1400 uint32_t status; 1401 1402 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1403 DPRINTFN(15, "ii %p", ii, 0, 0, 0); 1404 1405 KASSERT(ii != NULL); 1406 1407 if (ii->xfer->ux_status == USBD_CANCELLED || 1408 ii->xfer->ux_status == USBD_TIMEOUT) { 1409 DPRINTF("aborted xfer %p", ii->xfer, 0, 0, 0); 1410 return; 1411 } 1412 1413 if (ii->stdstart == NULL) 1414 return; 1415 lstd = ii->stdend; 1416 1417 KASSERT(lstd != NULL); 1418 1419 usb_syncmem(&lstd->dma, 1420 lstd->offs + offsetof(uhci_td_t, td_status), 1421 sizeof(lstd->td.td_status), 1422 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1423 status = le32toh(lstd->td.td_status); 1424 usb_syncmem(&lstd->dma, 1425 lstd->offs + offsetof(uhci_td_t, td_status), 1426 sizeof(lstd->td.td_status), 1427 BUS_DMASYNC_PREREAD); 1428 1429 /* If the last TD is not marked active we can complete */ 1430 if (!(status & UHCI_TD_ACTIVE)) { 1431 done: 1432 DPRINTFN(12, "ii=%p done", ii, 0, 0, 0); 1433 1434 callout_stop(&ii->xfer->ux_callout); 1435 uhci_idone(ii); 1436 return; 1437 } 1438 1439 /* 1440 * If the last TD is still active we need to check whether there 1441 * is an error somewhere in the middle, or whether there was a 1442 * short packet (SPD and not ACTIVE). 1443 */ 1444 DPRINTFN(12, "active ii=%p", ii, 0, 0, 0); 1445 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1446 usb_syncmem(&std->dma, 1447 std->offs + offsetof(uhci_td_t, td_status), 1448 sizeof(std->td.td_status), 1449 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1450 status = le32toh(std->td.td_status); 1451 usb_syncmem(&std->dma, 1452 std->offs + offsetof(uhci_td_t, td_status), 1453 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1454 1455 /* If there's an active TD the xfer isn't done. */ 1456 if (status & UHCI_TD_ACTIVE) { 1457 DPRINTFN(12, "ii=%p std=%p still active", 1458 ii, std, 0, 0); 1459 return; 1460 } 1461 1462 /* Any kind of error makes the xfer done. */ 1463 if (status & UHCI_TD_STALLED) 1464 goto done; 1465 1466 /* 1467 * If the data phase of a control transfer is short, we need 1468 * to complete the status stage 1469 */ 1470 struct usbd_xfer *xfer = ii->xfer; 1471 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1472 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1473 1474 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1475 struct uhci_pipe *upipe = 1476 (struct uhci_pipe *)xfer->ux_pipe; 1477 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1478 uhci_soft_td_t *stat = upipe->ctrl.stat; 1479 1480 DPRINTFN(12, "ii=%p std=%p control status" 1481 "phase needs completion", ii, ii->stdstart, 0, 0); 1482 1483 sqh->qh.qh_elink = 1484 htole32(stat->physaddr | UHCI_PTR_TD); 1485 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1486 BUS_DMASYNC_PREWRITE); 1487 break; 1488 } 1489 1490 /* We want short packets, and it is short: it's done */ 1491 usb_syncmem(&std->dma, 1492 std->offs + offsetof(uhci_td_t, td_token), 1493 sizeof(std->td.td_token), 1494 BUS_DMASYNC_POSTWRITE); 1495 1496 if ((status & UHCI_TD_SPD) && 1497 UHCI_TD_GET_ACTLEN(status) < 1498 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1499 goto done; 1500 } 1501 } 1502 } 1503 1504 /* Called with USB lock held. */ 1505 void 1506 uhci_idone(uhci_intr_info_t *ii) 1507 { 1508 struct usbd_xfer *xfer = ii->xfer; 1509 uhci_softc_t *sc __diagused = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1510 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1511 uhci_soft_td_t *std; 1512 uint32_t status = 0, nstatus; 1513 int actlen; 1514 1515 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1516 1517 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1518 DPRINTFN(12, "ii=%p", ii, 0, 0, 0); 1519 1520 #ifdef DIAGNOSTIC 1521 #ifdef UHCI_DEBUG 1522 if (ii->isdone) { 1523 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1524 uhci_dump_ii(ii); 1525 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1526 } 1527 #endif 1528 KASSERT(!ii->isdone); 1529 ii->isdone = true; 1530 #endif 1531 1532 if (xfer->ux_nframes != 0) { 1533 /* Isoc transfer, do things differently. */ 1534 uhci_soft_td_t **stds = upipe->isoc.stds; 1535 int i, n, nframes, len; 1536 1537 DPRINTFN(5, "ii=%p isoc ready", ii, 0, 0, 0); 1538 1539 nframes = xfer->ux_nframes; 1540 actlen = 0; 1541 n = UXFER(xfer)->curframe; 1542 for (i = 0; i < nframes; i++) { 1543 std = stds[n]; 1544 #ifdef UHCI_DEBUG 1545 if (uhcidebug > 5) { 1546 DPRINTF("isoc TD %d", i, 0, 0, 0); 1547 uhci_dump_td(std); 1548 } 1549 #endif 1550 if (++n >= UHCI_VFRAMELIST_COUNT) 1551 n = 0; 1552 usb_syncmem(&std->dma, 1553 std->offs + offsetof(uhci_td_t, td_status), 1554 sizeof(std->td.td_status), 1555 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1556 status = le32toh(std->td.td_status); 1557 len = UHCI_TD_GET_ACTLEN(status); 1558 xfer->ux_frlengths[i] = len; 1559 actlen += len; 1560 } 1561 upipe->isoc.inuse -= nframes; 1562 xfer->ux_actlen = actlen; 1563 xfer->ux_status = USBD_NORMAL_COMPLETION; 1564 goto end; 1565 } 1566 1567 #ifdef UHCI_DEBUG 1568 DPRINTFN(10, "ii=%p, xfer=%p, pipe=%p ready", 1569 ii, xfer, upipe, 0); 1570 if (uhcidebug > 10) 1571 uhci_dump_tds(ii->stdstart); 1572 #endif 1573 1574 /* The transfer is done, compute actual length and status. */ 1575 actlen = 0; 1576 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1577 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1578 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1579 nstatus = le32toh(std->td.td_status); 1580 if (nstatus & UHCI_TD_ACTIVE) 1581 break; 1582 1583 status = nstatus; 1584 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1585 UHCI_TD_PID_SETUP) 1586 actlen += UHCI_TD_GET_ACTLEN(status); 1587 else { 1588 /* 1589 * UHCI will report CRCTO in addition to a STALL or NAK 1590 * for a SETUP transaction. See section 3.2.2, "TD 1591 * CONTROL AND STATUS". 1592 */ 1593 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1594 status &= ~UHCI_TD_CRCTO; 1595 } 1596 } 1597 /* If there are left over TDs we need to update the toggle. */ 1598 if (std != NULL) 1599 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1600 1601 status &= UHCI_TD_ERROR; 1602 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1603 xfer->ux_actlen = actlen; 1604 if (status != 0) { 1605 1606 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1607 "error, addr=%d, endpt=0x%02x", 1608 xfer->ux_pipe->up_dev->ud_addr, 1609 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1610 0, 0); 1611 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1612 "bitstuff=%d crcto =%d nak =%d babble =%d", 1613 status & UHCI_TD_BITSTUFF, 1614 status & UHCI_TD_CRCTO, 1615 status & UHCI_TD_NAK, 1616 status & UHCI_TD_BABBLE); 1617 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1618 "dbuffer =%d stalled =%d active =%d", 1619 status & UHCI_TD_DBUFFER, 1620 status & UHCI_TD_STALLED, 1621 status & UHCI_TD_ACTIVE, 1622 0); 1623 1624 if (status == UHCI_TD_STALLED) 1625 xfer->ux_status = USBD_STALLED; 1626 else 1627 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1628 } else { 1629 xfer->ux_status = USBD_NORMAL_COMPLETION; 1630 } 1631 1632 end: 1633 usb_transfer_complete(xfer); 1634 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1635 DPRINTFN(12, "ii=%p done", ii, 0, 0, 0); 1636 } 1637 1638 /* 1639 * Called when a request does not complete. 1640 */ 1641 void 1642 uhci_timeout(void *addr) 1643 { 1644 uhci_intr_info_t *ii = addr; 1645 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1646 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.ux_pipe; 1647 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 1648 1649 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1650 1651 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1652 1653 if (sc->sc_dying) { 1654 mutex_enter(&sc->sc_lock); 1655 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1656 mutex_exit(&sc->sc_lock); 1657 return; 1658 } 1659 1660 /* Execute the abort in a process context. */ 1661 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1662 USB_TASKQ_MPSAFE); 1663 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1664 USB_TASKQ_HC); 1665 } 1666 1667 void 1668 uhci_timeout_task(void *addr) 1669 { 1670 struct usbd_xfer *xfer = addr; 1671 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1672 1673 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1674 1675 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1676 1677 mutex_enter(&sc->sc_lock); 1678 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1679 mutex_exit(&sc->sc_lock); 1680 } 1681 1682 /* 1683 * Wait here until controller claims to have an interrupt. 1684 * Then call uhci_intr and return. Use timeout to avoid waiting 1685 * too long. 1686 * Only used during boot when interrupts are not enabled yet. 1687 */ 1688 void 1689 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1690 { 1691 int timo = xfer->ux_timeout; 1692 uhci_intr_info_t *ii; 1693 1694 mutex_enter(&sc->sc_lock); 1695 1696 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1697 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1698 1699 xfer->ux_status = USBD_IN_PROGRESS; 1700 for (; timo >= 0; timo--) { 1701 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1702 DPRINTFN(20, "0x%04x", 1703 UREAD2(sc, UHCI_STS), 0, 0, 0); 1704 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1705 mutex_spin_enter(&sc->sc_intr_lock); 1706 uhci_intr1(sc); 1707 mutex_spin_exit(&sc->sc_intr_lock); 1708 if (xfer->ux_status != USBD_IN_PROGRESS) 1709 goto done; 1710 } 1711 } 1712 1713 /* Timeout */ 1714 DPRINTF("timeout", 0, 0, 0, 0); 1715 for (ii = LIST_FIRST(&sc->sc_intrhead); 1716 ii != NULL && ii->xfer != xfer; 1717 ii = LIST_NEXT(ii, list)) 1718 ; 1719 1720 KASSERT(ii != NULL); 1721 1722 uhci_idone(ii); 1723 1724 done: 1725 mutex_exit(&sc->sc_lock); 1726 } 1727 1728 void 1729 uhci_poll(struct usbd_bus *bus) 1730 { 1731 uhci_softc_t *sc = bus->ub_hcpriv; 1732 1733 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1734 mutex_spin_enter(&sc->sc_intr_lock); 1735 uhci_intr1(sc); 1736 mutex_spin_exit(&sc->sc_intr_lock); 1737 } 1738 } 1739 1740 void 1741 uhci_reset(uhci_softc_t *sc) 1742 { 1743 int n; 1744 1745 UHCICMD(sc, UHCI_CMD_HCRESET); 1746 /* The reset bit goes low when the controller is done. */ 1747 for (n = 0; n < UHCI_RESET_TIMEOUT && 1748 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1749 usb_delay_ms(&sc->sc_bus, 1); 1750 if (n >= UHCI_RESET_TIMEOUT) 1751 printf("%s: controller did not reset\n", 1752 device_xname(sc->sc_dev)); 1753 } 1754 1755 usbd_status 1756 uhci_run(uhci_softc_t *sc, int run, int locked) 1757 { 1758 int n, running; 1759 uint16_t cmd; 1760 1761 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1762 1763 run = run != 0; 1764 if (!locked) 1765 mutex_spin_enter(&sc->sc_intr_lock); 1766 1767 DPRINTF("setting run=%d", run, 0, 0, 0); 1768 cmd = UREAD2(sc, UHCI_CMD); 1769 if (run) 1770 cmd |= UHCI_CMD_RS; 1771 else 1772 cmd &= ~UHCI_CMD_RS; 1773 UHCICMD(sc, cmd); 1774 for(n = 0; n < 10; n++) { 1775 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1776 /* return when we've entered the state we want */ 1777 if (run == running) { 1778 if (!locked) 1779 mutex_spin_exit(&sc->sc_intr_lock); 1780 DPRINTF("done cmd=0x%x sts=0x%x", 1781 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1782 return USBD_NORMAL_COMPLETION; 1783 } 1784 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1785 } 1786 if (!locked) 1787 mutex_spin_exit(&sc->sc_intr_lock); 1788 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1789 run ? "start" : "stop"); 1790 return USBD_IOERROR; 1791 } 1792 1793 /* 1794 * Memory management routines. 1795 * uhci_alloc_std allocates TDs 1796 * uhci_alloc_sqh allocates QHs 1797 * These two routines do their own free list management, 1798 * partly for speed, partly because allocating DMAable memory 1799 * has page size granularity so much memory would be wasted if 1800 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1801 */ 1802 1803 uhci_soft_td_t * 1804 uhci_alloc_std(uhci_softc_t *sc) 1805 { 1806 uhci_soft_td_t *std; 1807 usbd_status err; 1808 int i, offs; 1809 usb_dma_t dma; 1810 1811 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1812 1813 if (sc->sc_freetds == NULL) { 1814 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1815 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1816 UHCI_TD_ALIGN, &dma); 1817 if (err) 1818 return 0; 1819 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1820 offs = i * UHCI_STD_SIZE; 1821 std = KERNADDR(&dma, offs); 1822 std->physaddr = DMAADDR(&dma, offs); 1823 std->dma = dma; 1824 std->offs = offs; 1825 std->link.std = sc->sc_freetds; 1826 sc->sc_freetds = std; 1827 } 1828 } 1829 std = sc->sc_freetds; 1830 sc->sc_freetds = std->link.std; 1831 memset(&std->td, 0, sizeof(uhci_td_t)); 1832 return std; 1833 } 1834 1835 void 1836 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1837 { 1838 #ifdef DIAGNOSTIC 1839 #define TD_IS_FREE 0x12345678 1840 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1841 printf("uhci_free_std: freeing free TD %p\n", std); 1842 return; 1843 } 1844 std->td.td_token = htole32(TD_IS_FREE); 1845 #endif 1846 std->link.std = sc->sc_freetds; 1847 sc->sc_freetds = std; 1848 } 1849 1850 uhci_soft_qh_t * 1851 uhci_alloc_sqh(uhci_softc_t *sc) 1852 { 1853 uhci_soft_qh_t *sqh; 1854 usbd_status err; 1855 int i, offs; 1856 usb_dma_t dma; 1857 1858 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1859 1860 if (sc->sc_freeqhs == NULL) { 1861 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1862 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1863 UHCI_QH_ALIGN, &dma); 1864 if (err) 1865 return 0; 1866 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1867 offs = i * UHCI_SQH_SIZE; 1868 sqh = KERNADDR(&dma, offs); 1869 sqh->physaddr = DMAADDR(&dma, offs); 1870 sqh->dma = dma; 1871 sqh->offs = offs; 1872 sqh->hlink = sc->sc_freeqhs; 1873 sc->sc_freeqhs = sqh; 1874 } 1875 } 1876 sqh = sc->sc_freeqhs; 1877 sc->sc_freeqhs = sqh->hlink; 1878 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1879 return sqh; 1880 } 1881 1882 void 1883 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1884 { 1885 sqh->hlink = sc->sc_freeqhs; 1886 sc->sc_freeqhs = sqh; 1887 } 1888 1889 void 1890 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1891 uhci_soft_td_t *stdend) 1892 { 1893 uhci_soft_td_t *p; 1894 uint32_t td_link; 1895 1896 /* 1897 * to avoid race condition with the controller which may be looking 1898 * at this chain, we need to first invalidate all links, and 1899 * then wait for the controller to move to another queue 1900 */ 1901 for (p = std; p != stdend; p = p->link.std) { 1902 usb_syncmem(&p->dma, 1903 p->offs + offsetof(uhci_td_t, td_link), 1904 sizeof(p->td.td_link), 1905 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1906 td_link = le32toh(p->td.td_link); 1907 usb_syncmem(&p->dma, 1908 p->offs + offsetof(uhci_td_t, td_link), 1909 sizeof(p->td.td_link), 1910 BUS_DMASYNC_PREREAD); 1911 if ((td_link & UHCI_PTR_T) == 0) { 1912 p->td.td_link = htole32(UHCI_PTR_T); 1913 usb_syncmem(&p->dma, 1914 p->offs + offsetof(uhci_td_t, td_link), 1915 sizeof(p->td.td_link), 1916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1917 } 1918 } 1919 delay(UHCI_QH_REMOVE_DELAY); 1920 1921 for (; std != stdend; std = p) { 1922 p = std->link.std; 1923 uhci_free_std(sc, std); 1924 } 1925 } 1926 1927 usbd_status 1928 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1929 int rd, uint16_t flags, usb_dma_t *dma, 1930 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1931 { 1932 uhci_soft_td_t *p, *lastp; 1933 uhci_physaddr_t lastlink; 1934 int i, ntd, l, tog, maxp; 1935 uint32_t status; 1936 int addr = upipe->pipe.up_dev->ud_addr; 1937 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1938 1939 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1940 1941 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 1942 addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed); 1943 1944 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1945 1946 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1947 if (maxp == 0) { 1948 printf("uhci_alloc_std_chain: maxp=0\n"); 1949 return USBD_INVAL; 1950 } 1951 ntd = (len + maxp - 1) / maxp; 1952 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1953 ntd++; 1954 DPRINTFN(10, "maxp=%d ntd=%d", 1955 maxp, ntd, 0, 0); 1956 1957 if (ntd == 0) { 1958 *sp = *ep = NULL; 1959 DPRINTF("ntd=0", 0, 0, 0, 0); 1960 return USBD_NORMAL_COMPLETION; 1961 } 1962 tog = upipe->nexttoggle; 1963 if (ntd % 2 == 0) 1964 tog ^= 1; 1965 upipe->nexttoggle = tog ^ 1; 1966 lastp = NULL; 1967 lastlink = UHCI_PTR_T; 1968 ntd--; 1969 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1970 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1971 status |= UHCI_TD_LS; 1972 if (flags & USBD_SHORT_XFER_OK) 1973 status |= UHCI_TD_SPD; 1974 usb_syncmem(dma, 0, len, 1975 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1976 for (i = ntd; i >= 0; i--) { 1977 p = uhci_alloc_std(sc); 1978 if (p == NULL) { 1979 KASSERT(lastp != NULL); 1980 uhci_free_std_chain(sc, lastp, NULL); 1981 return USBD_NOMEM; 1982 } 1983 p->link.std = lastp; 1984 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1985 lastp = p; 1986 lastlink = p->physaddr; 1987 p->td.td_status = htole32(status); 1988 if (i == ntd) { 1989 /* last TD */ 1990 l = len % maxp; 1991 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1992 l = maxp; 1993 *ep = p; 1994 } else 1995 l = maxp; 1996 p->td.td_token = 1997 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1998 UHCI_TD_OUT(l, endpt, addr, tog)); 1999 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2000 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 2001 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2002 tog ^= 1; 2003 } 2004 *sp = lastp; 2005 DPRINTFN(10, "nexttog=%d", upipe->nexttoggle, 2006 0, 0, 0); 2007 2008 return USBD_NORMAL_COMPLETION; 2009 } 2010 2011 void 2012 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2013 { 2014 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2015 upipe->nexttoggle = 0; 2016 } 2017 2018 void 2019 uhci_noop(struct usbd_pipe *pipe) 2020 { 2021 } 2022 2023 usbd_status 2024 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2025 { 2026 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2027 usbd_status err; 2028 2029 /* Insert last in queue. */ 2030 mutex_enter(&sc->sc_lock); 2031 err = usb_insert_transfer(xfer); 2032 mutex_exit(&sc->sc_lock); 2033 if (err) 2034 return err; 2035 2036 /* 2037 * Pipe isn't running (otherwise err would be USBD_INPROG), 2038 * so start it first. 2039 */ 2040 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2041 } 2042 2043 usbd_status 2044 uhci_device_bulk_start(struct usbd_xfer *xfer) 2045 { 2046 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2047 struct usbd_device *dev = upipe->pipe.up_dev; 2048 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2049 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2050 uhci_soft_td_t *data, *dataend; 2051 uhci_soft_qh_t *sqh; 2052 usbd_status err; 2053 int len, isread, endpt; 2054 2055 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2056 DPRINTFN(3, "xfer=%p len=%d flags=%d ii=%p", 2057 xfer, xfer->ux_length, xfer->ux_flags, ii); 2058 2059 if (sc->sc_dying) 2060 return USBD_IOERROR; 2061 2062 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2063 2064 mutex_enter(&sc->sc_lock); 2065 2066 len = xfer->ux_length; 2067 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2068 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2069 sqh = upipe->bulk.sqh; 2070 2071 upipe->bulk.isread = isread; 2072 upipe->bulk.length = len; 2073 2074 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2075 &xfer->ux_dmabuf, &data, &dataend); 2076 if (err) { 2077 mutex_exit(&sc->sc_lock); 2078 return err; 2079 } 2080 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2081 usb_syncmem(&dataend->dma, 2082 dataend->offs + offsetof(uhci_td_t, td_status), 2083 sizeof(dataend->td.td_status), 2084 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2085 2086 2087 #ifdef UHCI_DEBUG 2088 if (uhcidebug > 8) { 2089 DPRINTFN(8, "data(1)", 0, 0, 0, 0); 2090 uhci_dump_tds(data); 2091 } 2092 #endif 2093 2094 /* Set up interrupt info. */ 2095 ii->xfer = xfer; 2096 ii->stdstart = data; 2097 ii->stdend = dataend; 2098 2099 KASSERT(ii->isdone); 2100 #ifdef DIAGNOSTIC 2101 ii->isdone = false; 2102 #endif 2103 2104 sqh->elink = data; 2105 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2106 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2107 2108 uhci_add_bulk(sc, sqh); 2109 uhci_add_intr_info(sc, ii); 2110 2111 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2112 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2113 uhci_timeout, ii); 2114 } 2115 xfer->ux_status = USBD_IN_PROGRESS; 2116 2117 #ifdef UHCI_DEBUG 2118 if (uhcidebug > 10) { 2119 DPRINTFN(10, "data(2)", 0, 0, 0, 0); 2120 uhci_dump_tds(data); 2121 } 2122 #endif 2123 2124 if (sc->sc_bus.ub_usepolling) 2125 uhci_waitintr(sc, xfer); 2126 2127 mutex_exit(&sc->sc_lock); 2128 return USBD_IN_PROGRESS; 2129 } 2130 2131 /* Abort a device bulk request. */ 2132 void 2133 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2134 { 2135 uhci_softc_t *sc __diagused = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2136 2137 KASSERT(mutex_owned(&sc->sc_lock)); 2138 2139 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2140 2141 uhci_abort_xfer(xfer, USBD_CANCELLED); 2142 } 2143 2144 /* 2145 * Abort a device request. 2146 * If this routine is called at splusb() it guarantees that the request 2147 * will be removed from the hardware scheduling and that the callback 2148 * for it will be called with USBD_CANCELLED status. 2149 * It's impossible to guarantee that the requested transfer will not 2150 * have happened since the hardware runs concurrently. 2151 * If the transaction has already happened we rely on the ordinary 2152 * interrupt processing to process it. 2153 * XXX This is most probably wrong. 2154 * XXXMRG this doesn't make sense anymore. 2155 */ 2156 void 2157 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2158 { 2159 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2160 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2161 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2162 uhci_soft_td_t *std; 2163 int wake; 2164 2165 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2166 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2167 2168 KASSERT(mutex_owned(&sc->sc_lock)); 2169 ASSERT_SLEEPABLE(); 2170 2171 if (sc->sc_dying) { 2172 /* If we're dying, just do the software part. */ 2173 xfer->ux_status = status; /* make software ignore it */ 2174 callout_stop(&xfer->ux_callout); 2175 usb_transfer_complete(xfer); 2176 return; 2177 } 2178 2179 /* 2180 * If an abort is already in progress then just wait for it to 2181 * complete and return. 2182 */ 2183 if (xfer->ux_hcflags & UXFER_ABORTING) { 2184 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2185 #ifdef DIAGNOSTIC 2186 if (status == USBD_TIMEOUT) 2187 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2188 #endif 2189 /* Override the status which might be USBD_TIMEOUT. */ 2190 xfer->ux_status = status; 2191 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2192 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2193 while (xfer->ux_hcflags & UXFER_ABORTING) 2194 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2195 goto done; 2196 } 2197 xfer->ux_hcflags |= UXFER_ABORTING; 2198 2199 /* 2200 * Step 1: Make interrupt routine and hardware ignore xfer. 2201 */ 2202 xfer->ux_status = status; /* make software ignore it */ 2203 callout_stop(&xfer->ux_callout); 2204 DPRINTF("stop ii=%p", ii, 0, 0, 0); 2205 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2206 usb_syncmem(&std->dma, 2207 std->offs + offsetof(uhci_td_t, td_status), 2208 sizeof(std->td.td_status), 2209 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2210 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2211 usb_syncmem(&std->dma, 2212 std->offs + offsetof(uhci_td_t, td_status), 2213 sizeof(std->td.td_status), 2214 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2215 } 2216 2217 /* 2218 * Step 2: Wait until we know hardware has finished any possible 2219 * use of the xfer. Also make sure the soft interrupt routine 2220 * has run. 2221 */ 2222 /* Hardware finishes in 1ms */ 2223 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2224 sc->sc_softwake = 1; 2225 usb_schedsoftintr(&sc->sc_bus); 2226 DPRINTF("cv_wait", 0, 0, 0, 0); 2227 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2228 2229 /* 2230 * Step 3: Execute callback. 2231 */ 2232 DPRINTF("callback", 0, 0, 0, 0); 2233 #ifdef DIAGNOSTIC 2234 ii->isdone = true; 2235 #endif 2236 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2237 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2238 usb_transfer_complete(xfer); 2239 if (wake) 2240 cv_broadcast(&xfer->ux_hccv); 2241 done: 2242 KASSERT(mutex_owned(&sc->sc_lock)); 2243 } 2244 2245 /* Close a device bulk pipe. */ 2246 void 2247 uhci_device_bulk_close(struct usbd_pipe *pipe) 2248 { 2249 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2250 struct usbd_device *dev = upipe->pipe.up_dev; 2251 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2252 2253 KASSERT(mutex_owned(&sc->sc_lock)); 2254 2255 uhci_free_sqh(sc, upipe->bulk.sqh); 2256 2257 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2258 } 2259 2260 usbd_status 2261 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2262 { 2263 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2264 usbd_status err; 2265 2266 /* Insert last in queue. */ 2267 mutex_enter(&sc->sc_lock); 2268 err = usb_insert_transfer(xfer); 2269 mutex_exit(&sc->sc_lock); 2270 if (err) 2271 return err; 2272 2273 /* 2274 * Pipe isn't running (otherwise err would be USBD_INPROG), 2275 * so start it first. 2276 */ 2277 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2278 } 2279 2280 usbd_status 2281 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2282 { 2283 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2284 usbd_status err; 2285 2286 if (sc->sc_dying) 2287 return USBD_IOERROR; 2288 2289 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2290 2291 mutex_enter(&sc->sc_lock); 2292 err = uhci_device_request(xfer); 2293 mutex_exit(&sc->sc_lock); 2294 if (err) 2295 return err; 2296 2297 if (sc->sc_bus.ub_usepolling) 2298 uhci_waitintr(sc, xfer); 2299 return USBD_IN_PROGRESS; 2300 } 2301 2302 usbd_status 2303 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2304 { 2305 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2306 usbd_status err; 2307 2308 /* Insert last in queue. */ 2309 mutex_enter(&sc->sc_lock); 2310 err = usb_insert_transfer(xfer); 2311 mutex_exit(&sc->sc_lock); 2312 if (err) 2313 return err; 2314 2315 /* 2316 * Pipe isn't running (otherwise err would be USBD_INPROG), 2317 * so start it first. 2318 */ 2319 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2320 } 2321 2322 usbd_status 2323 uhci_device_intr_start(struct usbd_xfer *xfer) 2324 { 2325 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2326 struct usbd_device *dev = upipe->pipe.up_dev; 2327 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2328 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2329 uhci_soft_td_t *data, *dataend; 2330 uhci_soft_qh_t *sqh; 2331 usbd_status err; 2332 int isread, endpt; 2333 int i; 2334 2335 if (sc->sc_dying) 2336 return USBD_IOERROR; 2337 2338 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2339 2340 DPRINTFN(3, "xfer=%p len=%d flags=%d", 2341 xfer, xfer->ux_length, xfer->ux_flags, 0); 2342 2343 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2344 2345 mutex_enter(&sc->sc_lock); 2346 2347 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2348 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2349 2350 upipe->intr.isread = isread; 2351 2352 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2353 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2354 &dataend); 2355 if (err) { 2356 mutex_exit(&sc->sc_lock); 2357 return err; 2358 } 2359 2360 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2361 usb_syncmem(&dataend->dma, 2362 dataend->offs + offsetof(uhci_td_t, td_status), 2363 sizeof(dataend->td.td_status), 2364 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2365 2366 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2367 #ifdef UHCI_DEBUG 2368 if (uhcidebug > 10) { 2369 uhci_dump_tds(data); 2370 uhci_dump_qh(upipe->intr.qhs[0]); 2371 } 2372 #endif 2373 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2374 2375 /* Set up interrupt info. */ 2376 ii->xfer = xfer; 2377 ii->stdstart = data; 2378 ii->stdend = dataend; 2379 KASSERT(ii->isdone); 2380 #ifdef DIAGNOSTIC 2381 ii->isdone = false; 2382 #endif 2383 2384 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2385 for (i = 0; i < upipe->intr.npoll; i++) { 2386 sqh = upipe->intr.qhs[i]; 2387 sqh->elink = data; 2388 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2389 usb_syncmem(&sqh->dma, 2390 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2391 sizeof(sqh->qh.qh_elink), 2392 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2393 } 2394 uhci_add_intr_info(sc, ii); 2395 xfer->ux_status = USBD_IN_PROGRESS; 2396 mutex_exit(&sc->sc_lock); 2397 2398 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2399 #ifdef UHCI_DEBUG 2400 if (uhcidebug > 10) { 2401 uhci_dump_tds(data); 2402 uhci_dump_qh(upipe->intr.qhs[0]); 2403 } 2404 #endif 2405 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2406 2407 return USBD_IN_PROGRESS; 2408 } 2409 2410 /* Abort a device control request. */ 2411 void 2412 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2413 { 2414 uhci_softc_t *sc __diagused = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2415 2416 KASSERT(mutex_owned(&sc->sc_lock)); 2417 2418 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2419 uhci_abort_xfer(xfer, USBD_CANCELLED); 2420 } 2421 2422 /* Close a device control pipe. */ 2423 void 2424 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2425 { 2426 } 2427 2428 /* Abort a device interrupt request. */ 2429 void 2430 uhci_device_intr_abort(struct usbd_xfer *xfer) 2431 { 2432 uhci_softc_t *sc __diagused = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2433 2434 KASSERT(mutex_owned(&sc->sc_lock)); 2435 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2436 2437 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2438 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2439 2440 uhci_abort_xfer(xfer, USBD_CANCELLED); 2441 } 2442 2443 /* Close a device interrupt pipe. */ 2444 void 2445 uhci_device_intr_close(struct usbd_pipe *pipe) 2446 { 2447 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2448 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2449 int i, npoll; 2450 2451 KASSERT(mutex_owned(&sc->sc_lock)); 2452 2453 /* Unlink descriptors from controller data structures. */ 2454 npoll = upipe->intr.npoll; 2455 for (i = 0; i < npoll; i++) 2456 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2457 2458 /* 2459 * We now have to wait for any activity on the physical 2460 * descriptors to stop. 2461 */ 2462 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2463 2464 for(i = 0; i < npoll; i++) 2465 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2466 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2467 2468 /* XXX free other resources */ 2469 } 2470 2471 usbd_status 2472 uhci_device_request(struct usbd_xfer *xfer) 2473 { 2474 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2475 usb_device_request_t *req = &xfer->ux_request; 2476 struct usbd_device *dev = upipe->pipe.up_dev; 2477 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2478 int addr = dev->ud_addr; 2479 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2480 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2481 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2482 uhci_soft_qh_t *sqh; 2483 int len; 2484 uint32_t ls; 2485 usbd_status err; 2486 int isread; 2487 2488 KASSERT(mutex_owned(&sc->sc_lock)); 2489 2490 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2491 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2492 "wValue=0x%04x, wIndex=0x%04x", 2493 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2494 UGETW(req->wIndex)); 2495 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2496 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2497 2498 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2499 isread = req->bmRequestType & UT_READ; 2500 len = UGETW(req->wLength); 2501 2502 setup = upipe->ctrl.setup; 2503 stat = upipe->ctrl.stat; 2504 sqh = upipe->ctrl.sqh; 2505 2506 /* Set up data transaction */ 2507 if (len != 0) { 2508 upipe->nexttoggle = 1; 2509 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2510 &xfer->ux_dmabuf, &data, &dataend); 2511 if (err) 2512 return err; 2513 next = data; 2514 dataend->link.std = stat; 2515 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2516 usb_syncmem(&dataend->dma, 2517 dataend->offs + offsetof(uhci_td_t, td_link), 2518 sizeof(dataend->td.td_link), 2519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2520 } else { 2521 next = stat; 2522 } 2523 upipe->ctrl.length = len; 2524 2525 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof *req); 2526 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2527 2528 setup->link.std = next; 2529 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2530 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2531 UHCI_TD_ACTIVE); 2532 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2533 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2534 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2536 2537 stat->link.std = NULL; 2538 stat->td.td_link = htole32(UHCI_PTR_T); 2539 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2540 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2541 stat->td.td_token = 2542 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2543 UHCI_TD_IN (0, endpt, addr, 1)); 2544 stat->td.td_buffer = htole32(0); 2545 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2546 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2547 2548 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2549 #ifdef UHCI_DEBUG 2550 if (uhcidebug > 10) { 2551 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2552 uhci_dump_tds(setup); 2553 } 2554 #endif 2555 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2556 2557 /* Set up interrupt info. */ 2558 ii->xfer = xfer; 2559 ii->stdstart = setup; 2560 ii->stdend = stat; 2561 KASSERT(ii->isdone); 2562 #ifdef DIAGNOSTIC 2563 ii->isdone = false; 2564 #endif 2565 2566 sqh->elink = setup; 2567 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2568 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2569 2570 if (dev->ud_speed == USB_SPEED_LOW) 2571 uhci_add_ls_ctrl(sc, sqh); 2572 else 2573 uhci_add_hs_ctrl(sc, sqh); 2574 uhci_add_intr_info(sc, ii); 2575 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2576 #ifdef UHCI_DEBUG 2577 if (uhcidebug > 12) { 2578 uhci_soft_td_t *std; 2579 uhci_soft_qh_t *xqh; 2580 uhci_soft_qh_t *sxqh; 2581 int maxqh = 0; 2582 uhci_physaddr_t link; 2583 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2584 for (std = sc->sc_vframes[0].htd, link = 0; 2585 (link & UHCI_PTR_QH) == 0; 2586 std = std->link.std) { 2587 link = le32toh(std->td.td_link); 2588 uhci_dump_td(std); 2589 } 2590 sxqh = (uhci_soft_qh_t *)std; 2591 uhci_dump_qh(sxqh); 2592 for (xqh = sxqh; 2593 xqh != NULL; 2594 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2595 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2596 uhci_dump_qh(xqh); 2597 } 2598 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2599 uhci_dump_qh(sqh); 2600 uhci_dump_tds(sqh->elink); 2601 } 2602 #endif 2603 DPRINTFN(12, "--- dump end ---", 0, 0, 0, 0); 2604 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2605 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2606 uhci_timeout, ii); 2607 } 2608 xfer->ux_status = USBD_IN_PROGRESS; 2609 2610 return USBD_NORMAL_COMPLETION; 2611 } 2612 2613 usbd_status 2614 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2615 { 2616 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2617 usbd_status err; 2618 2619 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2620 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2621 2622 /* Put it on our queue, */ 2623 mutex_enter(&sc->sc_lock); 2624 err = usb_insert_transfer(xfer); 2625 mutex_exit(&sc->sc_lock); 2626 2627 /* bail out on error, */ 2628 if (err && err != USBD_IN_PROGRESS) 2629 return err; 2630 2631 /* XXX should check inuse here */ 2632 2633 /* insert into schedule, */ 2634 uhci_device_isoc_enter(xfer); 2635 2636 /* and start if the pipe wasn't running */ 2637 if (!err) 2638 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2639 2640 return err; 2641 } 2642 2643 void 2644 uhci_device_isoc_enter(struct usbd_xfer *xfer) 2645 { 2646 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2647 struct usbd_device *dev = upipe->pipe.up_dev; 2648 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2649 struct isoc *isoc = &upipe->isoc; 2650 uhci_soft_td_t *std; 2651 uint32_t buf, len, status, offs; 2652 int i, next, nframes; 2653 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2654 2655 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2656 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2657 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2658 2659 if (sc->sc_dying) 2660 return; 2661 2662 if (xfer->ux_status == USBD_IN_PROGRESS) { 2663 /* This request has already been entered into the frame list */ 2664 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2665 /* XXX */ 2666 } 2667 2668 #ifdef DIAGNOSTIC 2669 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2670 printf("uhci_device_isoc_enter: overflow!\n"); 2671 #endif 2672 2673 next = isoc->next; 2674 if (next == -1) { 2675 /* Not in use yet, schedule it a few frames ahead. */ 2676 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2677 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2678 } 2679 2680 xfer->ux_status = USBD_IN_PROGRESS; 2681 UXFER(xfer)->curframe = next; 2682 2683 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2684 offs = 0; 2685 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2686 UHCI_TD_ACTIVE | 2687 UHCI_TD_IOS); 2688 nframes = xfer->ux_nframes; 2689 mutex_enter(&sc->sc_lock); 2690 for (i = 0; i < nframes; i++) { 2691 std = isoc->stds[next]; 2692 if (++next >= UHCI_VFRAMELIST_COUNT) 2693 next = 0; 2694 len = xfer->ux_frlengths[i]; 2695 std->td.td_buffer = htole32(buf); 2696 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2697 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2698 if (i == nframes - 1) 2699 status |= UHCI_TD_IOC; 2700 std->td.td_status = htole32(status); 2701 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2702 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2703 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2704 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2705 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2706 #ifdef UHCI_DEBUG 2707 if (uhcidebug > 5) { 2708 DPRINTF("TD %d", i, 0, 0, 0); 2709 uhci_dump_td(std); 2710 } 2711 #endif 2712 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2713 buf += len; 2714 offs += len; 2715 } 2716 isoc->next = next; 2717 isoc->inuse += xfer->ux_nframes; 2718 2719 mutex_exit(&sc->sc_lock); 2720 } 2721 2722 usbd_status 2723 uhci_device_isoc_start(struct usbd_xfer *xfer) 2724 { 2725 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2726 uhci_softc_t *sc = upipe->pipe.up_dev->ud_bus->ub_hcpriv; 2727 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2728 uhci_soft_td_t *end; 2729 int i; 2730 2731 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2732 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2733 2734 mutex_enter(&sc->sc_lock); 2735 2736 if (sc->sc_dying) { 2737 mutex_exit(&sc->sc_lock); 2738 return USBD_IOERROR; 2739 } 2740 2741 #ifdef DIAGNOSTIC 2742 if (xfer->ux_status != USBD_IN_PROGRESS) 2743 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2744 #endif 2745 2746 /* Find the last TD */ 2747 i = UXFER(xfer)->curframe + xfer->ux_nframes; 2748 if (i >= UHCI_VFRAMELIST_COUNT) 2749 i -= UHCI_VFRAMELIST_COUNT; 2750 end = upipe->isoc.stds[i]; 2751 2752 KASSERT(end != NULL); 2753 2754 /* Set up interrupt info. */ 2755 ii->xfer = xfer; 2756 ii->stdstart = end; 2757 ii->stdend = end; 2758 2759 KASSERT(ii->isdone); 2760 #ifdef DIAGNOSTIC 2761 ii->isdone = false; 2762 #endif 2763 uhci_add_intr_info(sc, ii); 2764 2765 mutex_exit(&sc->sc_lock); 2766 2767 return USBD_IN_PROGRESS; 2768 } 2769 2770 void 2771 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2772 { 2773 uhci_softc_t *sc __diagused = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2774 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2775 uhci_soft_td_t **stds = upipe->isoc.stds; 2776 uhci_soft_td_t *std; 2777 int i, n, nframes, maxlen, len; 2778 2779 KASSERT(mutex_owned(&sc->sc_lock)); 2780 2781 /* Transfer is already done. */ 2782 if (xfer->ux_status != USBD_NOT_STARTED && 2783 xfer->ux_status != USBD_IN_PROGRESS) { 2784 return; 2785 } 2786 2787 /* Give xfer the requested abort code. */ 2788 xfer->ux_status = USBD_CANCELLED; 2789 2790 /* make hardware ignore it, */ 2791 nframes = xfer->ux_nframes; 2792 n = UXFER(xfer)->curframe; 2793 maxlen = 0; 2794 for (i = 0; i < nframes; i++) { 2795 std = stds[n]; 2796 usb_syncmem(&std->dma, 2797 std->offs + offsetof(uhci_td_t, td_status), 2798 sizeof(std->td.td_status), 2799 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2800 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2801 usb_syncmem(&std->dma, 2802 std->offs + offsetof(uhci_td_t, td_status), 2803 sizeof(std->td.td_status), 2804 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2805 usb_syncmem(&std->dma, 2806 std->offs + offsetof(uhci_td_t, td_token), 2807 sizeof(std->td.td_token), 2808 BUS_DMASYNC_POSTWRITE); 2809 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2810 if (len > maxlen) 2811 maxlen = len; 2812 if (++n >= UHCI_VFRAMELIST_COUNT) 2813 n = 0; 2814 } 2815 2816 /* and wait until we are sure the hardware has finished. */ 2817 delay(maxlen); 2818 2819 #ifdef DIAGNOSTIC 2820 UXFER(xfer)->iinfo.isdone = true; 2821 #endif 2822 /* Run callback and remove from interrupt list. */ 2823 usb_transfer_complete(xfer); 2824 2825 KASSERT(mutex_owned(&sc->sc_lock)); 2826 } 2827 2828 void 2829 uhci_device_isoc_close(struct usbd_pipe *pipe) 2830 { 2831 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2832 struct usbd_device *dev = upipe->pipe.up_dev; 2833 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2834 uhci_soft_td_t *std, *vstd; 2835 struct isoc *isoc; 2836 int i; 2837 2838 KASSERT(mutex_owned(&sc->sc_lock)); 2839 2840 /* 2841 * Make sure all TDs are marked as inactive. 2842 * Wait for completion. 2843 * Unschedule. 2844 * Deallocate. 2845 */ 2846 isoc = &upipe->isoc; 2847 2848 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2849 std = isoc->stds[i]; 2850 usb_syncmem(&std->dma, 2851 std->offs + offsetof(uhci_td_t, td_status), 2852 sizeof(std->td.td_status), 2853 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2854 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2855 usb_syncmem(&std->dma, 2856 std->offs + offsetof(uhci_td_t, td_status), 2857 sizeof(std->td.td_status), 2858 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2859 } 2860 /* wait for completion */ 2861 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2862 2863 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2864 std = isoc->stds[i]; 2865 for (vstd = sc->sc_vframes[i].htd; 2866 vstd != NULL && vstd->link.std != std; 2867 vstd = vstd->link.std) 2868 ; 2869 if (vstd == NULL) { 2870 /*panic*/ 2871 printf("uhci_device_isoc_close: %p not found\n", std); 2872 mutex_exit(&sc->sc_lock); 2873 return; 2874 } 2875 vstd->link = std->link; 2876 usb_syncmem(&std->dma, 2877 std->offs + offsetof(uhci_td_t, td_link), 2878 sizeof(std->td.td_link), 2879 BUS_DMASYNC_POSTWRITE); 2880 vstd->td.td_link = std->td.td_link; 2881 usb_syncmem(&vstd->dma, 2882 vstd->offs + offsetof(uhci_td_t, td_link), 2883 sizeof(vstd->td.td_link), 2884 BUS_DMASYNC_PREWRITE); 2885 uhci_free_std(sc, std); 2886 } 2887 2888 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2889 } 2890 2891 usbd_status 2892 uhci_setup_isoc(struct usbd_pipe *pipe) 2893 { 2894 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2895 struct usbd_device *dev = upipe->pipe.up_dev; 2896 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2897 int addr = upipe->pipe.up_dev->ud_addr; 2898 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2899 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2900 uhci_soft_td_t *std, *vstd; 2901 uint32_t token; 2902 struct isoc *isoc; 2903 int i; 2904 2905 isoc = &upipe->isoc; 2906 isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2907 sizeof (uhci_soft_td_t *), 2908 KM_SLEEP); 2909 if (isoc->stds == NULL) 2910 return USBD_NOMEM; 2911 2912 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2913 UHCI_TD_OUT(0, endpt, addr, 0); 2914 2915 mutex_enter(&sc->sc_lock); 2916 2917 /* Allocate the TDs and mark as inactive; */ 2918 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2919 std = uhci_alloc_std(sc); 2920 if (std == 0) 2921 goto bad; 2922 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2923 std->td.td_token = htole32(token); 2924 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2925 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2926 isoc->stds[i] = std; 2927 } 2928 2929 /* Insert TDs into schedule. */ 2930 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2931 std = isoc->stds[i]; 2932 vstd = sc->sc_vframes[i].htd; 2933 usb_syncmem(&vstd->dma, 2934 vstd->offs + offsetof(uhci_td_t, td_link), 2935 sizeof(vstd->td.td_link), 2936 BUS_DMASYNC_POSTWRITE); 2937 std->link = vstd->link; 2938 std->td.td_link = vstd->td.td_link; 2939 usb_syncmem(&std->dma, 2940 std->offs + offsetof(uhci_td_t, td_link), 2941 sizeof(std->td.td_link), 2942 BUS_DMASYNC_PREWRITE); 2943 vstd->link.std = std; 2944 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2945 usb_syncmem(&vstd->dma, 2946 vstd->offs + offsetof(uhci_td_t, td_link), 2947 sizeof(vstd->td.td_link), 2948 BUS_DMASYNC_PREWRITE); 2949 } 2950 mutex_exit(&sc->sc_lock); 2951 2952 isoc->next = -1; 2953 isoc->inuse = 0; 2954 2955 return USBD_NORMAL_COMPLETION; 2956 2957 bad: 2958 while (--i >= 0) 2959 uhci_free_std(sc, isoc->stds[i]); 2960 mutex_exit(&sc->sc_lock); 2961 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2962 return USBD_NOMEM; 2963 } 2964 2965 void 2966 uhci_device_isoc_done(struct usbd_xfer *xfer) 2967 { 2968 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2969 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2970 int i, offs; 2971 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2972 2973 2974 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2975 DPRINTFN(4, "length=%d, ux_state=0x%08x", 2976 xfer->ux_actlen, xfer->ux_state, 0, 0); 2977 2978 if (ii->xfer != xfer) 2979 /* Not on interrupt list, ignore it. */ 2980 return; 2981 2982 if (!uhci_active_intr_info(ii)) 2983 return; 2984 2985 #ifdef DIAGNOSTIC 2986 if (ii->stdend == NULL) { 2987 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2988 #ifdef UHCI_DEBUG 2989 uhci_dump_ii(ii); 2990 #endif 2991 return; 2992 } 2993 #endif 2994 2995 /* Turn off the interrupt since it is active even if the TD is not. */ 2996 usb_syncmem(&ii->stdend->dma, 2997 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2998 sizeof(ii->stdend->td.td_status), 2999 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3000 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3001 usb_syncmem(&ii->stdend->dma, 3002 ii->stdend->offs + offsetof(uhci_td_t, td_status), 3003 sizeof(ii->stdend->td.td_status), 3004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3005 3006 uhci_del_intr_info(ii); /* remove from active list */ 3007 3008 offs = 0; 3009 for (i = 0; i < xfer->ux_nframes; i++) { 3010 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3011 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3012 offs += xfer->ux_frlengths[i]; 3013 } 3014 } 3015 3016 void 3017 uhci_device_intr_done(struct usbd_xfer *xfer) 3018 { 3019 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3020 uhci_softc_t *sc = ii->sc; 3021 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3022 uhci_soft_qh_t *sqh; 3023 int i, npoll, isread; 3024 3025 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3026 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3027 3028 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3029 3030 npoll = upipe->intr.npoll; 3031 for(i = 0; i < npoll; i++) { 3032 sqh = upipe->intr.qhs[i]; 3033 sqh->elink = NULL; 3034 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3035 usb_syncmem(&sqh->dma, 3036 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3037 sizeof(sqh->qh.qh_elink), 3038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3039 } 3040 uhci_free_std_chain(sc, ii->stdstart, NULL); 3041 3042 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3043 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3044 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3045 3046 /* XXX Wasteful. */ 3047 if (xfer->ux_pipe->up_repeat) { 3048 uhci_soft_td_t *data, *dataend; 3049 3050 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3051 3052 /* This alloc cannot fail since we freed the chain above. */ 3053 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3054 upipe->intr.isread, xfer->ux_flags, 3055 &xfer->ux_dmabuf, &data, &dataend); 3056 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3057 usb_syncmem(&dataend->dma, 3058 dataend->offs + offsetof(uhci_td_t, td_status), 3059 sizeof(dataend->td.td_status), 3060 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3061 3062 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 3063 #ifdef UHCI_DEBUG 3064 if (uhcidebug > 10) { 3065 uhci_dump_tds(data); 3066 uhci_dump_qh(upipe->intr.qhs[0]); 3067 } 3068 #endif 3069 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 3070 3071 ii->stdstart = data; 3072 ii->stdend = dataend; 3073 KASSERT(ii->isdone); 3074 #ifdef DIAGNOSTIC 3075 ii->isdone = false; 3076 #endif 3077 for (i = 0; i < npoll; i++) { 3078 sqh = upipe->intr.qhs[i]; 3079 sqh->elink = data; 3080 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3081 usb_syncmem(&sqh->dma, 3082 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3083 sizeof(sqh->qh.qh_elink), 3084 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3085 } 3086 xfer->ux_status = USBD_IN_PROGRESS; 3087 /* The ii is already on the examined list, just leave it. */ 3088 } else { 3089 DPRINTFN(5, "removing", 0, 0, 0, 0); 3090 if (uhci_active_intr_info(ii)) 3091 uhci_del_intr_info(ii); 3092 } 3093 } 3094 3095 /* Deallocate request data structures */ 3096 void 3097 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3098 { 3099 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3100 uhci_softc_t *sc = ii->sc; 3101 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3102 int len = UGETW(xfer->ux_request.wLength); 3103 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3104 3105 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3106 3107 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3108 3109 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3110 3111 if (!uhci_active_intr_info(ii)) 3112 return; 3113 3114 uhci_del_intr_info(ii); /* remove from active list */ 3115 3116 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3117 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3118 else 3119 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3120 3121 if (upipe->ctrl.length != 0) 3122 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3123 3124 if (len) { 3125 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3126 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3127 } 3128 usb_syncmem(&upipe->ctrl.reqdma, 0, 3129 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3130 3131 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3132 } 3133 3134 /* Deallocate request data structures */ 3135 void 3136 uhci_device_bulk_done(struct usbd_xfer *xfer) 3137 { 3138 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3139 uhci_softc_t *sc = ii->sc; 3140 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3141 3142 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3143 DPRINTFN(5, "xfer=%p ii=%p sc=%p upipe=%p", xfer, ii, sc, 3144 upipe); 3145 3146 KASSERT(mutex_owned(&sc->sc_lock)); 3147 3148 if (!uhci_active_intr_info(ii)) 3149 return; 3150 3151 uhci_del_intr_info(ii); /* remove from active list */ 3152 3153 uhci_remove_bulk(sc, upipe->bulk.sqh); 3154 3155 uhci_free_std_chain(sc, ii->stdstart, NULL); 3156 3157 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3158 } 3159 3160 /* Add interrupt QH, called with vflock. */ 3161 void 3162 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3163 { 3164 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3165 uhci_soft_qh_t *eqh; 3166 3167 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3168 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3169 3170 eqh = vf->eqh; 3171 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3172 sizeof(eqh->qh.qh_hlink), 3173 BUS_DMASYNC_POSTWRITE); 3174 sqh->hlink = eqh->hlink; 3175 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3176 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3177 sizeof(sqh->qh.qh_hlink), 3178 BUS_DMASYNC_PREWRITE); 3179 eqh->hlink = sqh; 3180 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3181 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3182 sizeof(eqh->qh.qh_hlink), 3183 BUS_DMASYNC_PREWRITE); 3184 vf->eqh = sqh; 3185 vf->bandwidth++; 3186 } 3187 3188 /* Remove interrupt QH. */ 3189 void 3190 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3191 { 3192 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3193 uhci_soft_qh_t *pqh; 3194 3195 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3196 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3197 3198 /* See comment in uhci_remove_ctrl() */ 3199 3200 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3201 sizeof(sqh->qh.qh_elink), 3202 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3203 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3204 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3205 usb_syncmem(&sqh->dma, 3206 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3207 sizeof(sqh->qh.qh_elink), 3208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3209 delay(UHCI_QH_REMOVE_DELAY); 3210 } 3211 3212 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3213 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3214 sizeof(sqh->qh.qh_hlink), 3215 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3216 pqh->hlink = sqh->hlink; 3217 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3218 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3219 sizeof(pqh->qh.qh_hlink), 3220 BUS_DMASYNC_PREWRITE); 3221 delay(UHCI_QH_REMOVE_DELAY); 3222 if (vf->eqh == sqh) 3223 vf->eqh = pqh; 3224 vf->bandwidth--; 3225 } 3226 3227 usbd_status 3228 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3229 { 3230 uhci_soft_qh_t *sqh; 3231 int i, npoll; 3232 u_int bestbw, bw, bestoffs, offs; 3233 3234 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3235 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3236 if (ival == 0) { 3237 printf("uhci_device_setintr: 0 interval\n"); 3238 return USBD_INVAL; 3239 } 3240 3241 if (ival > UHCI_VFRAMELIST_COUNT) 3242 ival = UHCI_VFRAMELIST_COUNT; 3243 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3244 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3245 3246 upipe->intr.npoll = npoll; 3247 upipe->intr.qhs = 3248 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3249 if (upipe->intr.qhs == NULL) 3250 return USBD_NOMEM; 3251 3252 /* 3253 * Figure out which offset in the schedule that has most 3254 * bandwidth left over. 3255 */ 3256 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3257 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3258 for (bw = i = 0; i < npoll; i++) 3259 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3260 if (bw < bestbw) { 3261 bestbw = bw; 3262 bestoffs = offs; 3263 } 3264 } 3265 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3266 mutex_enter(&sc->sc_lock); 3267 for(i = 0; i < npoll; i++) { 3268 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3269 sqh->elink = NULL; 3270 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3271 usb_syncmem(&sqh->dma, 3272 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3273 sizeof(sqh->qh.qh_elink), 3274 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3275 sqh->pos = MOD(i * ival + bestoffs); 3276 } 3277 #undef MOD 3278 3279 /* Enter QHs into the controller data structures. */ 3280 for(i = 0; i < npoll; i++) 3281 uhci_add_intr(sc, upipe->intr.qhs[i]); 3282 mutex_exit(&sc->sc_lock); 3283 3284 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3285 3286 return USBD_NORMAL_COMPLETION; 3287 } 3288 3289 /* Open a new pipe. */ 3290 usbd_status 3291 uhci_open(struct usbd_pipe *pipe) 3292 { 3293 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3294 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3295 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3296 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3297 usbd_status err = USBD_NOMEM; 3298 int ival; 3299 3300 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3301 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3302 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3303 3304 if (sc->sc_dying) 3305 return USBD_IOERROR; 3306 3307 upipe->aborting = 0; 3308 /* toggle state needed for bulk endpoints */ 3309 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3310 3311 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3312 switch (ed->bEndpointAddress) { 3313 case USB_CONTROL_ENDPOINT: 3314 pipe->up_methods = &roothub_ctrl_methods; 3315 break; 3316 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3317 pipe->up_methods = &uhci_root_intr_methods; 3318 break; 3319 default: 3320 return USBD_INVAL; 3321 } 3322 } else { 3323 switch (ed->bmAttributes & UE_XFERTYPE) { 3324 case UE_CONTROL: 3325 pipe->up_methods = &uhci_device_ctrl_methods; 3326 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3327 if (upipe->ctrl.sqh == NULL) 3328 goto bad; 3329 upipe->ctrl.setup = uhci_alloc_std(sc); 3330 if (upipe->ctrl.setup == NULL) { 3331 uhci_free_sqh(sc, upipe->ctrl.sqh); 3332 goto bad; 3333 } 3334 upipe->ctrl.stat = uhci_alloc_std(sc); 3335 if (upipe->ctrl.stat == NULL) { 3336 uhci_free_sqh(sc, upipe->ctrl.sqh); 3337 uhci_free_std(sc, upipe->ctrl.setup); 3338 goto bad; 3339 } 3340 err = usb_allocmem(&sc->sc_bus, 3341 sizeof(usb_device_request_t), 3342 0, &upipe->ctrl.reqdma); 3343 if (err) { 3344 uhci_free_sqh(sc, upipe->ctrl.sqh); 3345 uhci_free_std(sc, upipe->ctrl.setup); 3346 uhci_free_std(sc, upipe->ctrl.stat); 3347 goto bad; 3348 } 3349 break; 3350 case UE_INTERRUPT: 3351 pipe->up_methods = &uhci_device_intr_methods; 3352 ival = pipe->up_interval; 3353 if (ival == USBD_DEFAULT_INTERVAL) 3354 ival = ed->bInterval; 3355 return uhci_device_setintr(sc, upipe, ival); 3356 case UE_ISOCHRONOUS: 3357 pipe->up_methods = &uhci_device_isoc_methods; 3358 return uhci_setup_isoc(pipe); 3359 case UE_BULK: 3360 pipe->up_methods = &uhci_device_bulk_methods; 3361 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3362 if (upipe->bulk.sqh == NULL) 3363 goto bad; 3364 break; 3365 } 3366 } 3367 return USBD_NORMAL_COMPLETION; 3368 3369 bad: 3370 return USBD_NOMEM; 3371 } 3372 3373 /* 3374 * Data structures and routines to emulate the root hub. 3375 */ 3376 /* 3377 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3378 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3379 * should not be used by the USB subsystem. As we cannot issue a 3380 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3381 * will be enabled as part of the reset. 3382 * 3383 * On the VT83C572, the port cannot be successfully enabled until the 3384 * outstanding "port enable change" and "connection status change" 3385 * events have been reset. 3386 */ 3387 Static usbd_status 3388 uhci_portreset(uhci_softc_t *sc, int index) 3389 { 3390 int lim, port, x; 3391 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3392 3393 if (index == 1) 3394 port = UHCI_PORTSC1; 3395 else if (index == 2) 3396 port = UHCI_PORTSC2; 3397 else 3398 return USBD_IOERROR; 3399 3400 x = URWMASK(UREAD2(sc, port)); 3401 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3402 3403 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3404 3405 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3406 UREAD2(sc, port), 0, 0); 3407 3408 x = URWMASK(UREAD2(sc, port)); 3409 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3410 3411 delay(100); 3412 3413 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3414 UREAD2(sc, port), 0, 0); 3415 3416 x = URWMASK(UREAD2(sc, port)); 3417 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3418 3419 for (lim = 10; --lim > 0;) { 3420 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3421 3422 x = UREAD2(sc, port); 3423 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3424 lim, x, 0); 3425 3426 if (!(x & UHCI_PORTSC_CCS)) { 3427 /* 3428 * No device is connected (or was disconnected 3429 * during reset). Consider the port reset. 3430 * The delay must be long enough to ensure on 3431 * the initial iteration that the device 3432 * connection will have been registered. 50ms 3433 * appears to be sufficient, but 20ms is not. 3434 */ 3435 DPRINTFN(3, "uhci port %d loop %u, device detached", 3436 index, lim, 0, 0); 3437 break; 3438 } 3439 3440 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3441 /* 3442 * Port enabled changed and/or connection 3443 * status changed were set. Reset either or 3444 * both raised flags (by writing a 1 to that 3445 * bit), and wait again for state to settle. 3446 */ 3447 UWRITE2(sc, port, URWMASK(x) | 3448 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3449 continue; 3450 } 3451 3452 if (x & UHCI_PORTSC_PE) 3453 /* Port is enabled */ 3454 break; 3455 3456 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3457 } 3458 3459 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3460 UREAD2(sc, port), 0, 0); 3461 3462 if (lim <= 0) { 3463 DPRINTF("uhci port %d reset timed out", index, 3464 0, 0, 0); 3465 return USBD_TIMEOUT; 3466 } 3467 3468 sc->sc_isreset = 1; 3469 return USBD_NORMAL_COMPLETION; 3470 } 3471 3472 Static int 3473 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3474 void *buf, int buflen) 3475 { 3476 uhci_softc_t *sc = bus->ub_hcpriv; 3477 int port, x; 3478 int status, change, totlen = 0; 3479 uint16_t len, value, index; 3480 usb_port_status_t ps; 3481 usbd_status err; 3482 3483 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3484 3485 if (sc->sc_dying) 3486 return -1; 3487 3488 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3489 req->bRequest, 0, 0); 3490 3491 len = UGETW(req->wLength); 3492 value = UGETW(req->wValue); 3493 index = UGETW(req->wIndex); 3494 3495 #define C(x,y) ((x) | ((y) << 8)) 3496 switch (C(req->bRequest, req->bmRequestType)) { 3497 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3498 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3499 if (len == 0) 3500 break; 3501 switch (value) { 3502 case C(0, UDESC_DEVICE): { 3503 usb_device_descriptor_t devd; 3504 3505 totlen = min(buflen, sizeof(devd)); 3506 memcpy(&devd, buf, totlen); 3507 USETW(devd.idVendor, sc->sc_id_vendor); 3508 memcpy(buf, &devd, totlen); 3509 break; 3510 } 3511 case C(1, UDESC_STRING): 3512 #define sd ((usb_string_descriptor_t *)buf) 3513 /* Vendor */ 3514 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3515 break; 3516 case C(2, UDESC_STRING): 3517 /* Product */ 3518 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3519 break; 3520 #undef sd 3521 default: 3522 /* default from usbroothub */ 3523 return buflen; 3524 } 3525 break; 3526 3527 /* Hub requests */ 3528 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3529 break; 3530 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3531 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3532 value, 0, 0); 3533 if (index == 1) 3534 port = UHCI_PORTSC1; 3535 else if (index == 2) 3536 port = UHCI_PORTSC2; 3537 else { 3538 return -1; 3539 } 3540 switch(value) { 3541 case UHF_PORT_ENABLE: 3542 x = URWMASK(UREAD2(sc, port)); 3543 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3544 break; 3545 case UHF_PORT_SUSPEND: 3546 x = URWMASK(UREAD2(sc, port)); 3547 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3548 break; 3549 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3550 /* see USB2 spec ch. 7.1.7.7 */ 3551 usb_delay_ms(&sc->sc_bus, 20); 3552 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3553 /* 10ms resume delay must be provided by caller */ 3554 break; 3555 case UHF_PORT_RESET: 3556 x = URWMASK(UREAD2(sc, port)); 3557 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3558 break; 3559 case UHF_C_PORT_CONNECTION: 3560 x = URWMASK(UREAD2(sc, port)); 3561 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3562 break; 3563 case UHF_C_PORT_ENABLE: 3564 x = URWMASK(UREAD2(sc, port)); 3565 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3566 break; 3567 case UHF_C_PORT_OVER_CURRENT: 3568 x = URWMASK(UREAD2(sc, port)); 3569 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3570 break; 3571 case UHF_C_PORT_RESET: 3572 sc->sc_isreset = 0; 3573 break; 3574 case UHF_PORT_CONNECTION: 3575 case UHF_PORT_OVER_CURRENT: 3576 case UHF_PORT_POWER: 3577 case UHF_PORT_LOW_SPEED: 3578 case UHF_C_PORT_SUSPEND: 3579 default: 3580 return -1; 3581 } 3582 break; 3583 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3584 if (index == 1) 3585 port = UHCI_PORTSC1; 3586 else if (index == 2) 3587 port = UHCI_PORTSC2; 3588 else { 3589 return -1; 3590 } 3591 if (len > 0) { 3592 *(uint8_t *)buf = 3593 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3594 UHCI_PORTSC_LS_SHIFT; 3595 totlen = 1; 3596 } 3597 break; 3598 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3599 if (len == 0) 3600 break; 3601 if ((value & 0xff) != 0) { 3602 return -1; 3603 } 3604 usb_hub_descriptor_t hubd; 3605 3606 totlen = min(buflen, sizeof(hubd)); 3607 memcpy(&hubd, buf, totlen); 3608 hubd.bNbrPorts = 2; 3609 memcpy(buf, &hubd, totlen); 3610 break; 3611 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3612 if (len != 4) { 3613 return -1; 3614 } 3615 memset(buf, 0, len); 3616 totlen = len; 3617 break; 3618 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3619 if (index == 1) 3620 port = UHCI_PORTSC1; 3621 else if (index == 2) 3622 port = UHCI_PORTSC2; 3623 else { 3624 return -1; 3625 } 3626 if (len != 4) { 3627 return -1; 3628 } 3629 x = UREAD2(sc, port); 3630 status = change = 0; 3631 if (x & UHCI_PORTSC_CCS) 3632 status |= UPS_CURRENT_CONNECT_STATUS; 3633 if (x & UHCI_PORTSC_CSC) 3634 change |= UPS_C_CONNECT_STATUS; 3635 if (x & UHCI_PORTSC_PE) 3636 status |= UPS_PORT_ENABLED; 3637 if (x & UHCI_PORTSC_POEDC) 3638 change |= UPS_C_PORT_ENABLED; 3639 if (x & UHCI_PORTSC_OCI) 3640 status |= UPS_OVERCURRENT_INDICATOR; 3641 if (x & UHCI_PORTSC_OCIC) 3642 change |= UPS_C_OVERCURRENT_INDICATOR; 3643 if (x & UHCI_PORTSC_SUSP) 3644 status |= UPS_SUSPEND; 3645 if (x & UHCI_PORTSC_LSDA) 3646 status |= UPS_LOW_SPEED; 3647 status |= UPS_PORT_POWER; 3648 if (sc->sc_isreset) 3649 change |= UPS_C_PORT_RESET; 3650 USETW(ps.wPortStatus, status); 3651 USETW(ps.wPortChange, change); 3652 totlen = min(len, sizeof(ps)); 3653 memcpy(buf, &ps, totlen); 3654 break; 3655 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3656 return -1; 3657 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3658 break; 3659 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3660 if (index == 1) 3661 port = UHCI_PORTSC1; 3662 else if (index == 2) 3663 port = UHCI_PORTSC2; 3664 else { 3665 return -1; 3666 } 3667 switch(value) { 3668 case UHF_PORT_ENABLE: 3669 x = URWMASK(UREAD2(sc, port)); 3670 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3671 break; 3672 case UHF_PORT_SUSPEND: 3673 x = URWMASK(UREAD2(sc, port)); 3674 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3675 break; 3676 case UHF_PORT_RESET: 3677 err = uhci_portreset(sc, index); 3678 if (err != USBD_NORMAL_COMPLETION) 3679 return -1; 3680 return 0; 3681 case UHF_PORT_POWER: 3682 /* Pretend we turned on power */ 3683 return 0; 3684 case UHF_C_PORT_CONNECTION: 3685 case UHF_C_PORT_ENABLE: 3686 case UHF_C_PORT_OVER_CURRENT: 3687 case UHF_PORT_CONNECTION: 3688 case UHF_PORT_OVER_CURRENT: 3689 case UHF_PORT_LOW_SPEED: 3690 case UHF_C_PORT_SUSPEND: 3691 case UHF_C_PORT_RESET: 3692 default: 3693 return -1; 3694 } 3695 break; 3696 default: 3697 /* default from usbroothub */ 3698 DPRINTF("returning %d (usbroothub default)", 3699 buflen, 0, 0, 0); 3700 return buflen; 3701 } 3702 3703 DPRINTF("returning %d", totlen, 0, 0, 0); 3704 3705 return totlen; 3706 } 3707 3708 /* Abort a root interrupt request. */ 3709 void 3710 uhci_root_intr_abort(struct usbd_xfer *xfer) 3711 { 3712 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3713 3714 KASSERT(mutex_owned(&sc->sc_lock)); 3715 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3716 3717 callout_stop(&sc->sc_poll_handle); 3718 sc->sc_intr_xfer = NULL; 3719 3720 xfer->ux_status = USBD_CANCELLED; 3721 #ifdef DIAGNOSTIC 3722 UXFER(xfer)->iinfo.isdone = 1; 3723 #endif 3724 usb_transfer_complete(xfer); 3725 } 3726 3727 usbd_status 3728 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3729 { 3730 uhci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3731 usbd_status err; 3732 3733 /* Insert last in queue. */ 3734 mutex_enter(&sc->sc_lock); 3735 err = usb_insert_transfer(xfer); 3736 mutex_exit(&sc->sc_lock); 3737 if (err) 3738 return err; 3739 3740 /* 3741 * Pipe isn't running (otherwise err would be USBD_INPROG), 3742 * start first 3743 */ 3744 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3745 } 3746 3747 /* Start a transfer on the root interrupt pipe */ 3748 usbd_status 3749 uhci_root_intr_start(struct usbd_xfer *xfer) 3750 { 3751 struct usbd_pipe *pipe = xfer->ux_pipe; 3752 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3753 unsigned int ival; 3754 3755 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3756 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3757 xfer->ux_flags, 0); 3758 3759 if (sc->sc_dying) 3760 return USBD_IOERROR; 3761 3762 /* XXX temporary variable needed to avoid gcc3 warning */ 3763 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3764 sc->sc_ival = mstohz(ival); 3765 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3766 sc->sc_intr_xfer = xfer; 3767 return USBD_IN_PROGRESS; 3768 } 3769 3770 /* Close the root interrupt pipe. */ 3771 void 3772 uhci_root_intr_close(struct usbd_pipe *pipe) 3773 { 3774 uhci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3775 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3776 3777 KASSERT(mutex_owned(&sc->sc_lock)); 3778 3779 callout_stop(&sc->sc_poll_handle); 3780 sc->sc_intr_xfer = NULL; 3781 } 3782
Indexes created Tue Sep 30 20:09:53 GMT 2025