uhci.c revision 1.264.4.38
1 /* $NetBSD: uhci.c,v 1.264.4.38 2015/10/27 08:02:31 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.38 2015/10/27 08:02:31 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Isochronous pipe */ 158 struct isoc { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } isoc; 162 }; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static usbd_status uhci_run(uhci_softc_t *, int, int); 169 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 170 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, 180 uhci_soft_td_t *, uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 182 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 183 uhci_soft_td_t **, uhci_soft_td_t **); 184 Static void uhci_poll_hub(void *); 185 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 186 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 187 Static void uhci_idone(uhci_intr_info_t *); 188 189 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 190 191 Static void uhci_timeout(void *); 192 Static void uhci_timeout_task(void *); 193 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 194 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 195 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 197 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 198 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_add_loop(uhci_softc_t *); 200 Static void uhci_rem_loop(uhci_softc_t *); 201 202 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 203 Static void uhci_device_isoc_enter(struct usbd_xfer *); 204 205 Static struct usbd_xfer * 206 uhci_allocx(struct usbd_bus *, unsigned int); 207 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 208 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 209 Static int uhci_roothub_ctrl(struct usbd_bus *, 210 usb_device_request_t *, void *, int); 211 212 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 213 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 214 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 215 Static void uhci_device_ctrl_close(struct usbd_pipe *); 216 Static void uhci_device_ctrl_done(struct usbd_xfer *); 217 218 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 220 Static void uhci_device_intr_abort(struct usbd_xfer *); 221 Static void uhci_device_intr_close(struct usbd_pipe *); 222 Static void uhci_device_intr_done(struct usbd_xfer *); 223 224 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 225 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 226 Static void uhci_device_bulk_abort(struct usbd_xfer *); 227 Static void uhci_device_bulk_close(struct usbd_pipe *); 228 Static void uhci_device_bulk_done(struct usbd_xfer *); 229 230 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 231 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 232 Static void uhci_device_isoc_abort(struct usbd_xfer *); 233 Static void uhci_device_isoc_close(struct usbd_pipe *); 234 Static void uhci_device_isoc_done(struct usbd_xfer *); 235 236 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 238 Static void uhci_root_intr_abort(struct usbd_xfer *); 239 Static void uhci_root_intr_close(struct usbd_pipe *); 240 Static void uhci_root_intr_done(struct usbd_xfer *); 241 242 Static usbd_status uhci_open(struct usbd_pipe *); 243 Static void uhci_poll(struct usbd_bus *); 244 Static void uhci_softintr(void *); 245 246 Static usbd_status uhci_device_request(struct usbd_xfer *); 247 248 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 250 Static usbd_status uhci_device_setintr(uhci_softc_t *, 251 struct uhci_pipe *, int); 252 253 Static void uhci_device_clear_toggle(struct usbd_pipe *); 254 Static void uhci_noop(struct usbd_pipe *); 255 256 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 257 uhci_soft_qh_t *); 258 259 #ifdef UHCI_DEBUG 260 Static void uhci_dump_all(uhci_softc_t *); 261 Static void uhci_dumpregs(uhci_softc_t *); 262 Static void uhci_dump_qhs(uhci_soft_qh_t *); 263 Static void uhci_dump_qh(uhci_soft_qh_t *); 264 Static void uhci_dump_tds(uhci_soft_td_t *); 265 Static void uhci_dump_td(uhci_soft_td_t *); 266 Static void uhci_dump_ii(uhci_intr_info_t *); 267 void uhci_dump(void); 268 #endif 269 270 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 271 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 272 #define UWRITE1(sc, r, x) \ 273 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 274 } while (/*CONSTCOND*/0) 275 #define UWRITE2(sc, r, x) \ 276 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 277 } while (/*CONSTCOND*/0) 278 #define UWRITE4(sc, r, x) \ 279 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 280 } while (/*CONSTCOND*/0) 281 static __inline uint8_t 282 UREAD1(uhci_softc_t *sc, bus_size_t r) 283 { 284 285 UBARR(sc); 286 return bus_space_read_1(sc->iot, sc->ioh, r); 287 } 288 289 static __inline uint16_t 290 UREAD2(uhci_softc_t *sc, bus_size_t r) 291 { 292 293 UBARR(sc); 294 return bus_space_read_2(sc->iot, sc->ioh, r); 295 } 296 297 #ifdef UHCI_DEBUG 298 static __inline uint32_t 299 UREAD4(uhci_softc_t *sc, bus_size_t r) 300 { 301 302 UBARR(sc); 303 return bus_space_read_4(sc->iot, sc->ioh, r); 304 } 305 #endif 306 307 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 308 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 309 310 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 311 312 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 313 314 const struct usbd_bus_methods uhci_bus_methods = { 315 .ubm_open = uhci_open, 316 .ubm_softint = uhci_softintr, 317 .ubm_dopoll = uhci_poll, 318 .ubm_allocx = uhci_allocx, 319 .ubm_freex = uhci_freex, 320 .ubm_getlock = uhci_get_lock, 321 .ubm_rhctrl = uhci_roothub_ctrl, 322 }; 323 324 const struct usbd_pipe_methods uhci_root_intr_methods = { 325 .upm_transfer = uhci_root_intr_transfer, 326 .upm_start = uhci_root_intr_start, 327 .upm_abort = uhci_root_intr_abort, 328 .upm_close = uhci_root_intr_close, 329 .upm_cleartoggle = uhci_noop, 330 .upm_done = uhci_root_intr_done, 331 }; 332 333 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 334 .upm_transfer = uhci_device_ctrl_transfer, 335 .upm_start = uhci_device_ctrl_start, 336 .upm_abort = uhci_device_ctrl_abort, 337 .upm_close = uhci_device_ctrl_close, 338 .upm_cleartoggle = uhci_noop, 339 .upm_done = uhci_device_ctrl_done, 340 }; 341 342 const struct usbd_pipe_methods uhci_device_intr_methods = { 343 .upm_transfer = uhci_device_intr_transfer, 344 .upm_start = uhci_device_intr_start, 345 .upm_abort = uhci_device_intr_abort, 346 .upm_close = uhci_device_intr_close, 347 .upm_cleartoggle = uhci_device_clear_toggle, 348 .upm_done = uhci_device_intr_done, 349 }; 350 351 const struct usbd_pipe_methods uhci_device_bulk_methods = { 352 .upm_transfer = uhci_device_bulk_transfer, 353 .upm_start = uhci_device_bulk_start, 354 .upm_abort = uhci_device_bulk_abort, 355 .upm_close = uhci_device_bulk_close, 356 .upm_cleartoggle = uhci_device_clear_toggle, 357 .upm_done = uhci_device_bulk_done, 358 }; 359 360 const struct usbd_pipe_methods uhci_device_isoc_methods = { 361 .upm_transfer = uhci_device_isoc_transfer, 362 .upm_start = uhci_device_isoc_start, 363 .upm_abort = uhci_device_isoc_abort, 364 .upm_close = uhci_device_isoc_close, 365 .upm_cleartoggle = uhci_noop, 366 .upm_done = uhci_device_isoc_done, 367 }; 368 369 #define uhci_add_intr_info(sc, ii) \ 370 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 371 #define uhci_del_intr_info(ii) \ 372 do { \ 373 LIST_REMOVE((ii), list); \ 374 (ii)->list.le_prev = NULL; \ 375 } while (0) 376 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 377 378 static inline uhci_soft_qh_t * 379 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 380 { 381 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 382 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 383 384 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 385 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 386 usb_syncmem(&pqh->dma, 387 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 388 sizeof(pqh->qh.qh_hlink), 389 BUS_DMASYNC_POSTWRITE); 390 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 391 printf("uhci_find_prev_qh: QH not found\n"); 392 return NULL; 393 } 394 #endif 395 } 396 return pqh; 397 } 398 399 void 400 uhci_globalreset(uhci_softc_t *sc) 401 { 402 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 403 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 404 UHCICMD(sc, 0); /* do nothing */ 405 } 406 407 int 408 uhci_init(uhci_softc_t *sc) 409 { 410 usbd_status err; 411 int i, j; 412 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 413 uhci_soft_td_t *std; 414 415 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 416 417 #ifdef UHCI_DEBUG 418 thesc = sc; 419 420 if (uhcidebug > 2) 421 uhci_dumpregs(sc); 422 #endif 423 424 sc->sc_suspend = PWR_RESUME; 425 426 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 427 uhci_globalreset(sc); /* reset the controller */ 428 uhci_reset(sc); 429 430 /* Allocate and initialize real frame array. */ 431 err = usb_allocmem(&sc->sc_bus, 432 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 433 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 434 if (err) 435 return err; 436 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 437 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 438 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 439 440 /* 441 * Allocate a TD, inactive, that hangs from the last QH. 442 * This is to avoid a bug in the PIIX that makes it run berserk 443 * otherwise. 444 */ 445 std = uhci_alloc_std(sc); 446 if (std == NULL) 447 return ENOMEM; 448 std->link.std = NULL; 449 std->td.td_link = htole32(UHCI_PTR_T); 450 std->td.td_status = htole32(0); /* inactive */ 451 std->td.td_token = htole32(0); 452 std->td.td_buffer = htole32(0); 453 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 455 456 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 457 lsqh = uhci_alloc_sqh(sc); 458 if (lsqh == NULL) 459 return ENOMEM; 460 lsqh->hlink = NULL; 461 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 462 lsqh->elink = std; 463 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 464 sc->sc_last_qh = lsqh; 465 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 467 468 /* Allocate the dummy QH where bulk traffic will be queued. */ 469 bsqh = uhci_alloc_sqh(sc); 470 if (bsqh == NULL) 471 return ENOMEM; 472 bsqh->hlink = lsqh; 473 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 474 bsqh->elink = NULL; 475 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 476 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 477 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 479 480 /* Allocate dummy QH where high speed control traffic will be queued. */ 481 chsqh = uhci_alloc_sqh(sc); 482 if (chsqh == NULL) 483 return ENOMEM; 484 chsqh->hlink = bsqh; 485 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 486 chsqh->elink = NULL; 487 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 488 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 489 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 490 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 491 492 /* Allocate dummy QH where control traffic will be queued. */ 493 clsqh = uhci_alloc_sqh(sc); 494 if (clsqh == NULL) 495 return ENOMEM; 496 clsqh->hlink = chsqh; 497 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 498 clsqh->elink = NULL; 499 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 500 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 501 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 504 /* 505 * Make all (virtual) frame list pointers point to the interrupt 506 * queue heads and the interrupt queue heads at the control 507 * queue head and point the physical frame list to the virtual. 508 */ 509 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 510 std = uhci_alloc_std(sc); 511 sqh = uhci_alloc_sqh(sc); 512 if (std == NULL || sqh == NULL) 513 return USBD_NOMEM; 514 std->link.sqh = sqh; 515 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 516 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 517 std->td.td_token = htole32(0); 518 std->td.td_buffer = htole32(0); 519 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 520 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 521 sqh->hlink = clsqh; 522 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 523 sqh->elink = NULL; 524 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 525 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 526 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 527 sc->sc_vframes[i].htd = std; 528 sc->sc_vframes[i].etd = std; 529 sc->sc_vframes[i].hqh = sqh; 530 sc->sc_vframes[i].eqh = sqh; 531 for (j = i; 532 j < UHCI_FRAMELIST_COUNT; 533 j += UHCI_VFRAMELIST_COUNT) 534 sc->sc_pframes[j] = htole32(std->physaddr); 535 } 536 usb_syncmem(&sc->sc_dma, 0, 537 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 538 BUS_DMASYNC_PREWRITE); 539 540 541 LIST_INIT(&sc->sc_intrhead); 542 543 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 544 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 545 546 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 547 548 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 549 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 550 cv_init(&sc->sc_softwake_cv, "uhciab"); 551 552 /* Set up the bus struct. */ 553 sc->sc_bus.ub_methods = &uhci_bus_methods; 554 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 555 sc->sc_bus.ub_usedma = true; 556 557 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 558 559 DPRINTF("Enabling...", 0, 0, 0, 0); 560 561 err = uhci_run(sc, 1, 0); /* and here we go... */ 562 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 563 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 564 return err; 565 } 566 567 int 568 uhci_activate(device_t self, enum devact act) 569 { 570 struct uhci_softc *sc = device_private(self); 571 572 switch (act) { 573 case DVACT_DEACTIVATE: 574 sc->sc_dying = 1; 575 return 0; 576 default: 577 return EOPNOTSUPP; 578 } 579 } 580 581 void 582 uhci_childdet(device_t self, device_t child) 583 { 584 struct uhci_softc *sc = device_private(self); 585 586 KASSERT(sc->sc_child == child); 587 sc->sc_child = NULL; 588 } 589 590 int 591 uhci_detach(struct uhci_softc *sc, int flags) 592 { 593 int rv = 0; 594 595 if (sc->sc_child != NULL) 596 rv = config_detach(sc->sc_child, flags); 597 598 if (rv != 0) 599 return rv; 600 601 callout_halt(&sc->sc_poll_handle, NULL); 602 callout_destroy(&sc->sc_poll_handle); 603 604 cv_destroy(&sc->sc_softwake_cv); 605 606 mutex_destroy(&sc->sc_lock); 607 mutex_destroy(&sc->sc_intr_lock); 608 609 pool_cache_destroy(sc->sc_xferpool); 610 611 /* XXX free other data structures XXX */ 612 613 return rv; 614 } 615 616 struct usbd_xfer * 617 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 618 { 619 struct uhci_softc *sc = UHCI_BUS2SC(bus); 620 struct usbd_xfer *xfer; 621 622 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 623 if (xfer != NULL) { 624 memset(xfer, 0, sizeof(struct uhci_xfer)); 625 626 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 627 #ifdef DIAGNOSTIC 628 uxfer->iinfo.isdone = true; 629 xfer->ux_state = XFER_BUSY; 630 #endif 631 } 632 return xfer; 633 } 634 635 void 636 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 637 { 638 struct uhci_softc *sc = UHCI_BUS2SC(bus); 639 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 640 641 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 642 xfer->ux_state); 643 KASSERTMSG(uxfer->iinfo.isdone, "xfer %p not done\n", xfer); 644 #ifdef DIAGNOSTIC 645 xfer->ux_state = XFER_FREE; 646 #endif 647 pool_cache_put(sc->sc_xferpool, xfer); 648 } 649 650 Static void 651 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 652 { 653 struct uhci_softc *sc = UHCI_BUS2SC(bus); 654 655 *lock = &sc->sc_lock; 656 } 657 658 659 /* 660 * Handle suspend/resume. 661 * 662 * We need to switch to polling mode here, because this routine is 663 * called from an interrupt context. This is all right since we 664 * are almost suspended anyway. 665 */ 666 bool 667 uhci_resume(device_t dv, const pmf_qual_t *qual) 668 { 669 uhci_softc_t *sc = device_private(dv); 670 int cmd; 671 672 mutex_spin_enter(&sc->sc_intr_lock); 673 674 cmd = UREAD2(sc, UHCI_CMD); 675 sc->sc_bus.ub_usepolling++; 676 UWRITE2(sc, UHCI_INTR, 0); 677 uhci_globalreset(sc); 678 uhci_reset(sc); 679 if (cmd & UHCI_CMD_RS) 680 uhci_run(sc, 0, 1); 681 682 /* restore saved state */ 683 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 684 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 685 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 686 687 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 688 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 689 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 690 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 691 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 692 UHCICMD(sc, UHCI_CMD_MAXP); 693 uhci_run(sc, 1, 1); /* and start traffic again */ 694 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 695 sc->sc_bus.ub_usepolling--; 696 if (sc->sc_intr_xfer != NULL) 697 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 698 sc->sc_intr_xfer); 699 #ifdef UHCI_DEBUG 700 if (uhcidebug > 2) 701 uhci_dumpregs(sc); 702 #endif 703 704 sc->sc_suspend = PWR_RESUME; 705 mutex_spin_exit(&sc->sc_intr_lock); 706 707 return true; 708 } 709 710 bool 711 uhci_suspend(device_t dv, const pmf_qual_t *qual) 712 { 713 uhci_softc_t *sc = device_private(dv); 714 int cmd; 715 716 mutex_spin_enter(&sc->sc_intr_lock); 717 718 cmd = UREAD2(sc, UHCI_CMD); 719 720 #ifdef UHCI_DEBUG 721 if (uhcidebug > 2) 722 uhci_dumpregs(sc); 723 #endif 724 if (sc->sc_intr_xfer != NULL) 725 callout_stop(&sc->sc_poll_handle); 726 sc->sc_suspend = PWR_SUSPEND; 727 sc->sc_bus.ub_usepolling++; 728 729 uhci_run(sc, 0, 1); /* stop the controller */ 730 cmd &= ~UHCI_CMD_RS; 731 732 /* save some state if BIOS doesn't */ 733 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 734 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 735 736 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 737 738 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 739 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 740 sc->sc_bus.ub_usepolling--; 741 742 mutex_spin_exit(&sc->sc_intr_lock); 743 744 return true; 745 } 746 747 #ifdef UHCI_DEBUG 748 Static void 749 uhci_dumpregs(uhci_softc_t *sc) 750 { 751 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 752 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 753 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 754 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 755 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 756 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 757 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 758 } 759 760 void 761 uhci_dump_td(uhci_soft_td_t *p) 762 { 763 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 764 765 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 766 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 767 768 DPRINTF("TD(%p) at %08x", p, p->physaddr, 0, 0); 769 DPRINTF(" link=0x%08x status=0x%08x " 770 "token=0x%08x buffer=0x%08x", 771 le32toh(p->td.td_link), 772 le32toh(p->td.td_status), 773 le32toh(p->td.td_token), 774 le32toh(p->td.td_buffer)); 775 776 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 777 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 778 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 779 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 780 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 781 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 782 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 783 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 784 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 785 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 786 DPRINTF("ios =%d ls =%d spd =%d", 787 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 788 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 789 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 790 DPRINTF("errcnt =%d actlen =%d pid=%02x", 791 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 792 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 793 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 794 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 795 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 796 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 797 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 798 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 799 } 800 801 void 802 uhci_dump_qh(uhci_soft_qh_t *sqh) 803 { 804 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 805 806 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 807 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 808 809 DPRINTF("QH(%p) at %08x: hlink=%08x elink=%08x", sqh, 810 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 811 le32toh(sqh->qh.qh_elink)); 812 813 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 814 } 815 816 817 #if 1 818 void 819 uhci_dump(void) 820 { 821 uhci_dump_all(thesc); 822 } 823 #endif 824 825 void 826 uhci_dump_all(uhci_softc_t *sc) 827 { 828 uhci_dumpregs(sc); 829 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 830 uhci_dump_qhs(sc->sc_lctl_start); 831 } 832 833 834 void 835 uhci_dump_qhs(uhci_soft_qh_t *sqh) 836 { 837 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 838 839 uhci_dump_qh(sqh); 840 841 /* 842 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 843 * Traverses sideways first, then down. 844 * 845 * QH1 846 * QH2 847 * No QH 848 * TD2.1 849 * TD2.2 850 * TD1.1 851 * etc. 852 * 853 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 854 */ 855 856 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 857 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 858 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 859 uhci_dump_qhs(sqh->hlink); 860 else 861 DPRINTF("No QH", 0, 0, 0, 0); 862 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 863 864 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 865 uhci_dump_tds(sqh->elink); 866 else 867 DPRINTF("No QH", 0, 0, 0, 0); 868 } 869 870 void 871 uhci_dump_tds(uhci_soft_td_t *std) 872 { 873 uhci_soft_td_t *td; 874 int stop; 875 876 for (td = std; td != NULL; td = td->link.std) { 877 uhci_dump_td(td); 878 879 /* 880 * Check whether the link pointer in this TD marks 881 * the link pointer as end of queue. This avoids 882 * printing the free list in case the queue/TD has 883 * already been moved there (seatbelt). 884 */ 885 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 886 sizeof(td->td.td_link), 887 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 888 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 889 le32toh(td->td.td_link) == 0); 890 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 891 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 892 if (stop) 893 break; 894 } 895 } 896 897 Static void 898 uhci_dump_ii(uhci_intr_info_t *ii) 899 { 900 struct usbd_pipe *pipe; 901 usb_endpoint_descriptor_t *ed; 902 struct usbd_device *dev; 903 904 #ifdef DIAGNOSTIC 905 #define DONE ii->isdone 906 #else 907 #define DONE 0 908 #endif 909 if (ii == NULL) { 910 printf("ii NULL\n"); 911 return; 912 } 913 if (ii->xfer == NULL) { 914 printf("ii %p: done=%d xfer=NULL\n", 915 ii, DONE); 916 return; 917 } 918 pipe = ii->xfer->ux_pipe; 919 if (pipe == NULL) { 920 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 921 ii, DONE, ii->xfer); 922 return; 923 } 924 if (pipe->up_endpoint == NULL) { 925 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 926 ii, DONE, ii->xfer, pipe); 927 return; 928 } 929 if (pipe->up_dev == NULL) { 930 printf("ii %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 931 ii, DONE, ii->xfer, pipe); 932 return; 933 } 934 ed = pipe->up_endpoint->ue_edesc; 935 dev = pipe->up_dev; 936 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 937 ii, DONE, ii->xfer, dev, 938 UGETW(dev->ud_ddesc.idVendor), 939 UGETW(dev->ud_ddesc.idProduct), 940 dev->ud_addr, pipe, 941 ed->bEndpointAddress, ed->bmAttributes); 942 #undef DONE 943 } 944 945 void uhci_dump_iis(struct uhci_softc *sc); 946 void 947 uhci_dump_iis(struct uhci_softc *sc) 948 { 949 uhci_intr_info_t *ii; 950 951 printf("intr_info list:\n"); 952 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 953 uhci_dump_ii(ii); 954 } 955 956 void iidump(void); 957 void iidump(void) { uhci_dump_iis(thesc); } 958 959 #endif 960 961 /* 962 * This routine is executed periodically and simulates interrupts 963 * from the root controller interrupt pipe for port status change. 964 */ 965 void 966 uhci_poll_hub(void *addr) 967 { 968 struct usbd_xfer *xfer = addr; 969 struct usbd_pipe *pipe = xfer->ux_pipe; 970 uhci_softc_t *sc; 971 u_char *p; 972 973 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 974 975 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 976 return; /* device has detached */ 977 sc = UHCI_PIPE2SC(pipe); 978 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 979 980 p = xfer->ux_buf; 981 p[0] = 0; 982 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 983 p[0] |= 1<<1; 984 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 985 p[0] |= 1<<2; 986 if (p[0] == 0) 987 /* No change, try again in a while */ 988 return; 989 990 xfer->ux_actlen = 1; 991 xfer->ux_status = USBD_NORMAL_COMPLETION; 992 mutex_enter(&sc->sc_lock); 993 usb_transfer_complete(xfer); 994 mutex_exit(&sc->sc_lock); 995 } 996 997 void 998 uhci_root_intr_done(struct usbd_xfer *xfer) 999 { 1000 } 1001 1002 /* 1003 * Let the last QH loop back to the high speed control transfer QH. 1004 * This is what intel calls "bandwidth reclamation" and improves 1005 * USB performance a lot for some devices. 1006 * If we are already looping, just count it. 1007 */ 1008 void 1009 uhci_add_loop(uhci_softc_t *sc) 1010 { 1011 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1012 1013 #ifdef UHCI_DEBUG 1014 if (uhcinoloop) 1015 return; 1016 #endif 1017 if (++sc->sc_loops == 1) { 1018 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1019 /* Note, we don't loop back the soft pointer. */ 1020 sc->sc_last_qh->qh.qh_hlink = 1021 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1022 usb_syncmem(&sc->sc_last_qh->dma, 1023 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1024 sizeof(sc->sc_last_qh->qh.qh_hlink), 1025 BUS_DMASYNC_PREWRITE); 1026 } 1027 } 1028 1029 void 1030 uhci_rem_loop(uhci_softc_t *sc) 1031 { 1032 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1033 1034 #ifdef UHCI_DEBUG 1035 if (uhcinoloop) 1036 return; 1037 #endif 1038 if (--sc->sc_loops == 0) { 1039 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1040 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1041 usb_syncmem(&sc->sc_last_qh->dma, 1042 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1043 sizeof(sc->sc_last_qh->qh.qh_hlink), 1044 BUS_DMASYNC_PREWRITE); 1045 } 1046 } 1047 1048 /* Add high speed control QH, called with lock held. */ 1049 void 1050 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1051 { 1052 uhci_soft_qh_t *eqh; 1053 1054 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1055 1056 KASSERT(mutex_owned(&sc->sc_lock)); 1057 1058 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1059 eqh = sc->sc_hctl_end; 1060 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1061 sizeof(eqh->qh.qh_hlink), 1062 BUS_DMASYNC_POSTWRITE); 1063 sqh->hlink = eqh->hlink; 1064 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1065 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1066 BUS_DMASYNC_PREWRITE); 1067 eqh->hlink = sqh; 1068 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1069 sc->sc_hctl_end = sqh; 1070 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1071 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1072 #ifdef UHCI_CTL_LOOP 1073 uhci_add_loop(sc); 1074 #endif 1075 } 1076 1077 /* Remove high speed control QH, called with lock held. */ 1078 void 1079 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1080 { 1081 uhci_soft_qh_t *pqh; 1082 uint32_t elink; 1083 1084 KASSERT(mutex_owned(&sc->sc_lock)); 1085 1086 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1087 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1088 #ifdef UHCI_CTL_LOOP 1089 uhci_rem_loop(sc); 1090 #endif 1091 /* 1092 * The T bit should be set in the elink of the QH so that the HC 1093 * doesn't follow the pointer. This condition may fail if the 1094 * the transferred packet was short so that the QH still points 1095 * at the last used TD. 1096 * In this case we set the T bit and wait a little for the HC 1097 * to stop looking at the TD. 1098 * Note that if the TD chain is large enough, the controller 1099 * may still be looking at the chain at the end of this function. 1100 * uhci_free_std_chain() will make sure the controller stops 1101 * looking at it quickly, but until then we should not change 1102 * sqh->hlink. 1103 */ 1104 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1105 sizeof(sqh->qh.qh_elink), 1106 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1107 elink = le32toh(sqh->qh.qh_elink); 1108 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1109 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1110 if (!(elink & UHCI_PTR_T)) { 1111 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1112 usb_syncmem(&sqh->dma, 1113 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1114 sizeof(sqh->qh.qh_elink), 1115 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1116 delay(UHCI_QH_REMOVE_DELAY); 1117 } 1118 1119 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1120 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1121 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1122 pqh->hlink = sqh->hlink; 1123 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1124 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1125 sizeof(pqh->qh.qh_hlink), 1126 BUS_DMASYNC_PREWRITE); 1127 delay(UHCI_QH_REMOVE_DELAY); 1128 if (sc->sc_hctl_end == sqh) 1129 sc->sc_hctl_end = pqh; 1130 } 1131 1132 /* Add low speed control QH, called with lock held. */ 1133 void 1134 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1135 { 1136 uhci_soft_qh_t *eqh; 1137 1138 KASSERT(mutex_owned(&sc->sc_lock)); 1139 1140 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1141 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1142 1143 eqh = sc->sc_lctl_end; 1144 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1145 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1146 sqh->hlink = eqh->hlink; 1147 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1148 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1149 BUS_DMASYNC_PREWRITE); 1150 eqh->hlink = sqh; 1151 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1152 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1153 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1154 sc->sc_lctl_end = sqh; 1155 } 1156 1157 /* Remove low speed control QH, called with lock held. */ 1158 void 1159 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1160 { 1161 uhci_soft_qh_t *pqh; 1162 uint32_t elink; 1163 1164 KASSERT(mutex_owned(&sc->sc_lock)); 1165 1166 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1167 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1168 1169 /* See comment in uhci_remove_hs_ctrl() */ 1170 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1171 sizeof(sqh->qh.qh_elink), 1172 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1173 elink = le32toh(sqh->qh.qh_elink); 1174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1175 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1176 if (!(elink & UHCI_PTR_T)) { 1177 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1178 usb_syncmem(&sqh->dma, 1179 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1180 sizeof(sqh->qh.qh_elink), 1181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1182 delay(UHCI_QH_REMOVE_DELAY); 1183 } 1184 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1185 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1186 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1187 pqh->hlink = sqh->hlink; 1188 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1189 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1190 sizeof(pqh->qh.qh_hlink), 1191 BUS_DMASYNC_PREWRITE); 1192 delay(UHCI_QH_REMOVE_DELAY); 1193 if (sc->sc_lctl_end == sqh) 1194 sc->sc_lctl_end = pqh; 1195 } 1196 1197 /* Add bulk QH, called with lock held. */ 1198 void 1199 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1200 { 1201 uhci_soft_qh_t *eqh; 1202 1203 KASSERT(mutex_owned(&sc->sc_lock)); 1204 1205 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1206 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1207 1208 eqh = sc->sc_bulk_end; 1209 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1210 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1211 sqh->hlink = eqh->hlink; 1212 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1213 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1214 BUS_DMASYNC_PREWRITE); 1215 eqh->hlink = sqh; 1216 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1217 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1218 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1219 sc->sc_bulk_end = sqh; 1220 uhci_add_loop(sc); 1221 } 1222 1223 /* Remove bulk QH, called with lock held. */ 1224 void 1225 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1226 { 1227 uhci_soft_qh_t *pqh; 1228 1229 KASSERT(mutex_owned(&sc->sc_lock)); 1230 1231 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1232 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1233 1234 uhci_rem_loop(sc); 1235 /* See comment in uhci_remove_hs_ctrl() */ 1236 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1237 sizeof(sqh->qh.qh_elink), 1238 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1239 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1240 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1241 usb_syncmem(&sqh->dma, 1242 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1243 sizeof(sqh->qh.qh_elink), 1244 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1245 delay(UHCI_QH_REMOVE_DELAY); 1246 } 1247 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1248 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1249 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1250 pqh->hlink = sqh->hlink; 1251 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1252 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1253 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1254 delay(UHCI_QH_REMOVE_DELAY); 1255 if (sc->sc_bulk_end == sqh) 1256 sc->sc_bulk_end = pqh; 1257 } 1258 1259 Static int uhci_intr1(uhci_softc_t *); 1260 1261 int 1262 uhci_intr(void *arg) 1263 { 1264 uhci_softc_t *sc = arg; 1265 int ret = 0; 1266 1267 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1268 1269 mutex_spin_enter(&sc->sc_intr_lock); 1270 1271 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1272 goto done; 1273 1274 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1275 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1276 goto done; 1277 } 1278 1279 ret = uhci_intr1(sc); 1280 1281 done: 1282 mutex_spin_exit(&sc->sc_intr_lock); 1283 return ret; 1284 } 1285 1286 int 1287 uhci_intr1(uhci_softc_t *sc) 1288 { 1289 int status; 1290 int ack; 1291 1292 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1293 1294 #ifdef UHCI_DEBUG 1295 if (uhcidebug > 15) { 1296 DPRINTF("sc %p", sc, 0, 0, 0); 1297 uhci_dumpregs(sc); 1298 } 1299 #endif 1300 1301 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1302 1303 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1304 if (status == 0) /* The interrupt was not for us. */ 1305 return 0; 1306 1307 if (sc->sc_suspend != PWR_RESUME) { 1308 #ifdef DIAGNOSTIC 1309 printf("%s: interrupt while not operating ignored\n", 1310 device_xname(sc->sc_dev)); 1311 #endif 1312 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1313 return 0; 1314 } 1315 1316 ack = 0; 1317 if (status & UHCI_STS_USBINT) 1318 ack |= UHCI_STS_USBINT; 1319 if (status & UHCI_STS_USBEI) 1320 ack |= UHCI_STS_USBEI; 1321 if (status & UHCI_STS_RD) { 1322 ack |= UHCI_STS_RD; 1323 #ifdef UHCI_DEBUG 1324 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1325 #endif 1326 } 1327 if (status & UHCI_STS_HSE) { 1328 ack |= UHCI_STS_HSE; 1329 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1330 } 1331 if (status & UHCI_STS_HCPE) { 1332 ack |= UHCI_STS_HCPE; 1333 printf("%s: host controller process error\n", 1334 device_xname(sc->sc_dev)); 1335 } 1336 1337 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1338 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1339 /* no acknowledge needed */ 1340 if (!sc->sc_dying) { 1341 printf("%s: host controller halted\n", 1342 device_xname(sc->sc_dev)); 1343 #ifdef UHCI_DEBUG 1344 uhci_dump_all(sc); 1345 #endif 1346 } 1347 sc->sc_dying = 1; 1348 } 1349 1350 if (!ack) 1351 return 0; /* nothing to acknowledge */ 1352 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1353 1354 usb_schedsoftintr(&sc->sc_bus); 1355 1356 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1357 1358 return 1; 1359 } 1360 1361 void 1362 uhci_softintr(void *v) 1363 { 1364 struct usbd_bus *bus = v; 1365 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1366 uhci_intr_info_t *ii, *nextii; 1367 1368 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1369 DPRINTF("sc %p", sc, 0, 0, 0); 1370 1371 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1372 1373 /* 1374 * Interrupts on UHCI really suck. When the host controller 1375 * interrupts because a transfer is completed there is no 1376 * way of knowing which transfer it was. You can scan down 1377 * the TDs and QHs of the previous frame to limit the search, 1378 * but that assumes that the interrupt was not delayed by more 1379 * than 1 ms, which may not always be true (e.g. after debug 1380 * output on a slow console). 1381 * We scan all interrupt descriptors to see if any have 1382 * completed. 1383 */ 1384 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1385 nextii = LIST_NEXT(ii, list); 1386 uhci_check_intr(sc, ii); 1387 } 1388 1389 if (sc->sc_softwake) { 1390 sc->sc_softwake = 0; 1391 cv_broadcast(&sc->sc_softwake_cv); 1392 } 1393 } 1394 1395 /* Check for an interrupt. */ 1396 void 1397 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1398 { 1399 uhci_soft_td_t *std, *lstd; 1400 uint32_t status; 1401 1402 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1403 DPRINTFN(15, "ii %p", ii, 0, 0, 0); 1404 1405 KASSERT(ii != NULL); 1406 1407 if (ii->xfer->ux_status == USBD_CANCELLED || 1408 ii->xfer->ux_status == USBD_TIMEOUT) { 1409 DPRINTF("aborted xfer %p", ii->xfer, 0, 0, 0); 1410 return; 1411 } 1412 1413 if (ii->stdstart == NULL) 1414 return; 1415 lstd = ii->stdend; 1416 1417 KASSERT(lstd != NULL); 1418 1419 usb_syncmem(&lstd->dma, 1420 lstd->offs + offsetof(uhci_td_t, td_status), 1421 sizeof(lstd->td.td_status), 1422 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1423 status = le32toh(lstd->td.td_status); 1424 usb_syncmem(&lstd->dma, 1425 lstd->offs + offsetof(uhci_td_t, td_status), 1426 sizeof(lstd->td.td_status), 1427 BUS_DMASYNC_PREREAD); 1428 1429 /* If the last TD is not marked active we can complete */ 1430 if (!(status & UHCI_TD_ACTIVE)) { 1431 done: 1432 DPRINTFN(12, "ii=%p done", ii, 0, 0, 0); 1433 1434 callout_stop(&ii->xfer->ux_callout); 1435 uhci_idone(ii); 1436 return; 1437 } 1438 1439 /* 1440 * If the last TD is still active we need to check whether there 1441 * is an error somewhere in the middle, or whether there was a 1442 * short packet (SPD and not ACTIVE). 1443 */ 1444 DPRINTFN(12, "active ii=%p", ii, 0, 0, 0); 1445 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1446 usb_syncmem(&std->dma, 1447 std->offs + offsetof(uhci_td_t, td_status), 1448 sizeof(std->td.td_status), 1449 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1450 status = le32toh(std->td.td_status); 1451 usb_syncmem(&std->dma, 1452 std->offs + offsetof(uhci_td_t, td_status), 1453 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1454 1455 /* If there's an active TD the xfer isn't done. */ 1456 if (status & UHCI_TD_ACTIVE) { 1457 DPRINTFN(12, "ii=%p std=%p still active", 1458 ii, std, 0, 0); 1459 return; 1460 } 1461 1462 /* Any kind of error makes the xfer done. */ 1463 if (status & UHCI_TD_STALLED) 1464 goto done; 1465 1466 /* 1467 * If the data phase of a control transfer is short, we need 1468 * to complete the status stage 1469 */ 1470 struct usbd_xfer *xfer = ii->xfer; 1471 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1472 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1473 1474 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1475 struct uhci_pipe *upipe = 1476 (struct uhci_pipe *)xfer->ux_pipe; 1477 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1478 uhci_soft_td_t *stat = upipe->ctrl.stat; 1479 1480 DPRINTFN(12, "ii=%p std=%p control status" 1481 "phase needs completion", ii, ii->stdstart, 0, 0); 1482 1483 sqh->qh.qh_elink = 1484 htole32(stat->physaddr | UHCI_PTR_TD); 1485 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1486 BUS_DMASYNC_PREWRITE); 1487 break; 1488 } 1489 1490 /* We want short packets, and it is short: it's done */ 1491 usb_syncmem(&std->dma, 1492 std->offs + offsetof(uhci_td_t, td_token), 1493 sizeof(std->td.td_token), 1494 BUS_DMASYNC_POSTWRITE); 1495 1496 if ((status & UHCI_TD_SPD) && 1497 UHCI_TD_GET_ACTLEN(status) < 1498 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1499 goto done; 1500 } 1501 } 1502 } 1503 1504 /* Called with USB lock held. */ 1505 void 1506 uhci_idone(uhci_intr_info_t *ii) 1507 { 1508 struct usbd_xfer *xfer = ii->xfer; 1509 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1510 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1511 uhci_soft_td_t *std; 1512 uint32_t status = 0, nstatus; 1513 int actlen; 1514 1515 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1516 1517 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1518 DPRINTFN(12, "ii=%p", ii, 0, 0, 0); 1519 1520 #ifdef DIAGNOSTIC 1521 #ifdef UHCI_DEBUG 1522 if (ii->isdone) { 1523 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1524 uhci_dump_ii(ii); 1525 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1526 } 1527 #endif 1528 KASSERT(!ii->isdone); 1529 ii->isdone = true; 1530 #endif 1531 1532 if (xfer->ux_nframes != 0) { 1533 /* Isoc transfer, do things differently. */ 1534 uhci_soft_td_t **stds = upipe->isoc.stds; 1535 int i, n, nframes, len; 1536 1537 DPRINTFN(5, "ii=%p isoc ready", ii, 0, 0, 0); 1538 1539 nframes = xfer->ux_nframes; 1540 actlen = 0; 1541 n = UHCI_XFER2UXFER(xfer)->curframe; 1542 for (i = 0; i < nframes; i++) { 1543 std = stds[n]; 1544 #ifdef UHCI_DEBUG 1545 if (uhcidebug > 5) { 1546 DPRINTF("isoc TD %d", i, 0, 0, 0); 1547 uhci_dump_td(std); 1548 } 1549 #endif 1550 if (++n >= UHCI_VFRAMELIST_COUNT) 1551 n = 0; 1552 usb_syncmem(&std->dma, 1553 std->offs + offsetof(uhci_td_t, td_status), 1554 sizeof(std->td.td_status), 1555 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1556 status = le32toh(std->td.td_status); 1557 len = UHCI_TD_GET_ACTLEN(status); 1558 xfer->ux_frlengths[i] = len; 1559 actlen += len; 1560 } 1561 upipe->isoc.inuse -= nframes; 1562 xfer->ux_actlen = actlen; 1563 xfer->ux_status = USBD_NORMAL_COMPLETION; 1564 goto end; 1565 } 1566 1567 #ifdef UHCI_DEBUG 1568 DPRINTFN(10, "ii=%p, xfer=%p, pipe=%p ready", 1569 ii, xfer, upipe, 0); 1570 if (uhcidebug > 10) 1571 uhci_dump_tds(ii->stdstart); 1572 #endif 1573 1574 /* The transfer is done, compute actual length and status. */ 1575 actlen = 0; 1576 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1577 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1578 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1579 nstatus = le32toh(std->td.td_status); 1580 if (nstatus & UHCI_TD_ACTIVE) 1581 break; 1582 1583 status = nstatus; 1584 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1585 UHCI_TD_PID_SETUP) 1586 actlen += UHCI_TD_GET_ACTLEN(status); 1587 else { 1588 /* 1589 * UHCI will report CRCTO in addition to a STALL or NAK 1590 * for a SETUP transaction. See section 3.2.2, "TD 1591 * CONTROL AND STATUS". 1592 */ 1593 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1594 status &= ~UHCI_TD_CRCTO; 1595 } 1596 } 1597 /* If there are left over TDs we need to update the toggle. */ 1598 if (std != NULL) 1599 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1600 1601 status &= UHCI_TD_ERROR; 1602 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1603 xfer->ux_actlen = actlen; 1604 if (status != 0) { 1605 1606 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1607 "error, addr=%d, endpt=0x%02x", 1608 xfer->ux_pipe->up_dev->ud_addr, 1609 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1610 0, 0); 1611 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1612 "bitstuff=%d crcto =%d nak =%d babble =%d", 1613 status & UHCI_TD_BITSTUFF, 1614 status & UHCI_TD_CRCTO, 1615 status & UHCI_TD_NAK, 1616 status & UHCI_TD_BABBLE); 1617 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1618 "dbuffer =%d stalled =%d active =%d", 1619 status & UHCI_TD_DBUFFER, 1620 status & UHCI_TD_STALLED, 1621 status & UHCI_TD_ACTIVE, 1622 0); 1623 1624 if (status == UHCI_TD_STALLED) 1625 xfer->ux_status = USBD_STALLED; 1626 else 1627 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1628 } else { 1629 xfer->ux_status = USBD_NORMAL_COMPLETION; 1630 } 1631 1632 end: 1633 usb_transfer_complete(xfer); 1634 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1635 DPRINTFN(12, "ii=%p done", ii, 0, 0, 0); 1636 } 1637 1638 /* 1639 * Called when a request does not complete. 1640 */ 1641 void 1642 uhci_timeout(void *addr) 1643 { 1644 uhci_intr_info_t *ii = addr; 1645 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(ii->xfer); 1646 uhci_softc_t *sc = UHCI_XFER2SC(ii->xfer); 1647 1648 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1649 1650 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1651 1652 if (sc->sc_dying) { 1653 mutex_enter(&sc->sc_lock); 1654 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1655 mutex_exit(&sc->sc_lock); 1656 return; 1657 } 1658 1659 /* Execute the abort in a process context. */ 1660 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1661 USB_TASKQ_MPSAFE); 1662 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1663 USB_TASKQ_HC); 1664 } 1665 1666 void 1667 uhci_timeout_task(void *addr) 1668 { 1669 struct usbd_xfer *xfer = addr; 1670 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1671 1672 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1673 1674 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1675 1676 mutex_enter(&sc->sc_lock); 1677 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1678 mutex_exit(&sc->sc_lock); 1679 } 1680 1681 /* 1682 * Wait here until controller claims to have an interrupt. 1683 * Then call uhci_intr and return. Use timeout to avoid waiting 1684 * too long. 1685 * Only used during boot when interrupts are not enabled yet. 1686 */ 1687 void 1688 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1689 { 1690 int timo = xfer->ux_timeout; 1691 uhci_intr_info_t *ii; 1692 1693 mutex_enter(&sc->sc_lock); 1694 1695 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1696 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1697 1698 xfer->ux_status = USBD_IN_PROGRESS; 1699 for (; timo >= 0; timo--) { 1700 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1701 DPRINTFN(20, "0x%04x", 1702 UREAD2(sc, UHCI_STS), 0, 0, 0); 1703 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1704 mutex_spin_enter(&sc->sc_intr_lock); 1705 uhci_intr1(sc); 1706 mutex_spin_exit(&sc->sc_intr_lock); 1707 if (xfer->ux_status != USBD_IN_PROGRESS) 1708 goto done; 1709 } 1710 } 1711 1712 /* Timeout */ 1713 DPRINTF("timeout", 0, 0, 0, 0); 1714 for (ii = LIST_FIRST(&sc->sc_intrhead); 1715 ii != NULL && ii->xfer != xfer; 1716 ii = LIST_NEXT(ii, list)) 1717 ; 1718 1719 KASSERT(ii != NULL); 1720 1721 uhci_idone(ii); 1722 1723 done: 1724 mutex_exit(&sc->sc_lock); 1725 } 1726 1727 void 1728 uhci_poll(struct usbd_bus *bus) 1729 { 1730 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1731 1732 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1733 mutex_spin_enter(&sc->sc_intr_lock); 1734 uhci_intr1(sc); 1735 mutex_spin_exit(&sc->sc_intr_lock); 1736 } 1737 } 1738 1739 void 1740 uhci_reset(uhci_softc_t *sc) 1741 { 1742 int n; 1743 1744 UHCICMD(sc, UHCI_CMD_HCRESET); 1745 /* The reset bit goes low when the controller is done. */ 1746 for (n = 0; n < UHCI_RESET_TIMEOUT && 1747 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1748 usb_delay_ms(&sc->sc_bus, 1); 1749 if (n >= UHCI_RESET_TIMEOUT) 1750 printf("%s: controller did not reset\n", 1751 device_xname(sc->sc_dev)); 1752 } 1753 1754 usbd_status 1755 uhci_run(uhci_softc_t *sc, int run, int locked) 1756 { 1757 int n, running; 1758 uint16_t cmd; 1759 1760 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1761 1762 run = run != 0; 1763 if (!locked) 1764 mutex_spin_enter(&sc->sc_intr_lock); 1765 1766 DPRINTF("setting run=%d", run, 0, 0, 0); 1767 cmd = UREAD2(sc, UHCI_CMD); 1768 if (run) 1769 cmd |= UHCI_CMD_RS; 1770 else 1771 cmd &= ~UHCI_CMD_RS; 1772 UHCICMD(sc, cmd); 1773 for(n = 0; n < 10; n++) { 1774 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1775 /* return when we've entered the state we want */ 1776 if (run == running) { 1777 if (!locked) 1778 mutex_spin_exit(&sc->sc_intr_lock); 1779 DPRINTF("done cmd=0x%x sts=0x%x", 1780 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1781 return USBD_NORMAL_COMPLETION; 1782 } 1783 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1784 } 1785 if (!locked) 1786 mutex_spin_exit(&sc->sc_intr_lock); 1787 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1788 run ? "start" : "stop"); 1789 return USBD_IOERROR; 1790 } 1791 1792 /* 1793 * Memory management routines. 1794 * uhci_alloc_std allocates TDs 1795 * uhci_alloc_sqh allocates QHs 1796 * These two routines do their own free list management, 1797 * partly for speed, partly because allocating DMAable memory 1798 * has page size granularity so much memory would be wasted if 1799 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1800 */ 1801 1802 uhci_soft_td_t * 1803 uhci_alloc_std(uhci_softc_t *sc) 1804 { 1805 uhci_soft_td_t *std; 1806 usbd_status err; 1807 int i, offs; 1808 usb_dma_t dma; 1809 1810 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1811 1812 if (sc->sc_freetds == NULL) { 1813 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1814 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1815 UHCI_TD_ALIGN, &dma); 1816 if (err) 1817 return 0; 1818 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1819 offs = i * UHCI_STD_SIZE; 1820 std = KERNADDR(&dma, offs); 1821 std->physaddr = DMAADDR(&dma, offs); 1822 std->dma = dma; 1823 std->offs = offs; 1824 std->link.std = sc->sc_freetds; 1825 sc->sc_freetds = std; 1826 } 1827 } 1828 std = sc->sc_freetds; 1829 sc->sc_freetds = std->link.std; 1830 memset(&std->td, 0, sizeof(uhci_td_t)); 1831 return std; 1832 } 1833 1834 void 1835 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1836 { 1837 #ifdef DIAGNOSTIC 1838 #define TD_IS_FREE 0x12345678 1839 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1840 printf("uhci_free_std: freeing free TD %p\n", std); 1841 return; 1842 } 1843 std->td.td_token = htole32(TD_IS_FREE); 1844 #endif 1845 std->link.std = sc->sc_freetds; 1846 sc->sc_freetds = std; 1847 } 1848 1849 uhci_soft_qh_t * 1850 uhci_alloc_sqh(uhci_softc_t *sc) 1851 { 1852 uhci_soft_qh_t *sqh; 1853 usbd_status err; 1854 int i, offs; 1855 usb_dma_t dma; 1856 1857 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1858 1859 if (sc->sc_freeqhs == NULL) { 1860 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1861 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1862 UHCI_QH_ALIGN, &dma); 1863 if (err) 1864 return 0; 1865 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1866 offs = i * UHCI_SQH_SIZE; 1867 sqh = KERNADDR(&dma, offs); 1868 sqh->physaddr = DMAADDR(&dma, offs); 1869 sqh->dma = dma; 1870 sqh->offs = offs; 1871 sqh->hlink = sc->sc_freeqhs; 1872 sc->sc_freeqhs = sqh; 1873 } 1874 } 1875 sqh = sc->sc_freeqhs; 1876 sc->sc_freeqhs = sqh->hlink; 1877 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1878 return sqh; 1879 } 1880 1881 void 1882 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1883 { 1884 sqh->hlink = sc->sc_freeqhs; 1885 sc->sc_freeqhs = sqh; 1886 } 1887 1888 void 1889 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1890 uhci_soft_td_t *stdend) 1891 { 1892 uhci_soft_td_t *p; 1893 uint32_t td_link; 1894 1895 /* 1896 * to avoid race condition with the controller which may be looking 1897 * at this chain, we need to first invalidate all links, and 1898 * then wait for the controller to move to another queue 1899 */ 1900 for (p = std; p != stdend; p = p->link.std) { 1901 usb_syncmem(&p->dma, 1902 p->offs + offsetof(uhci_td_t, td_link), 1903 sizeof(p->td.td_link), 1904 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1905 td_link = le32toh(p->td.td_link); 1906 usb_syncmem(&p->dma, 1907 p->offs + offsetof(uhci_td_t, td_link), 1908 sizeof(p->td.td_link), 1909 BUS_DMASYNC_PREREAD); 1910 if ((td_link & UHCI_PTR_T) == 0) { 1911 p->td.td_link = htole32(UHCI_PTR_T); 1912 usb_syncmem(&p->dma, 1913 p->offs + offsetof(uhci_td_t, td_link), 1914 sizeof(p->td.td_link), 1915 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1916 } 1917 } 1918 delay(UHCI_QH_REMOVE_DELAY); 1919 1920 for (; std != stdend; std = p) { 1921 p = std->link.std; 1922 uhci_free_std(sc, std); 1923 } 1924 } 1925 1926 usbd_status 1927 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1928 int rd, uint16_t flags, usb_dma_t *dma, 1929 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1930 { 1931 uhci_soft_td_t *p, *lastp; 1932 uhci_physaddr_t lastlink; 1933 int i, ntd, l, tog, maxp; 1934 uint32_t status; 1935 int addr = upipe->pipe.up_dev->ud_addr; 1936 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1937 1938 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1939 1940 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 1941 addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed); 1942 1943 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1944 1945 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1946 if (maxp == 0) { 1947 printf("uhci_alloc_std_chain: maxp=0\n"); 1948 return USBD_INVAL; 1949 } 1950 ntd = (len + maxp - 1) / maxp; 1951 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1952 ntd++; 1953 DPRINTFN(10, "maxp=%d ntd=%d", 1954 maxp, ntd, 0, 0); 1955 1956 if (ntd == 0) { 1957 *sp = *ep = NULL; 1958 DPRINTF("ntd=0", 0, 0, 0, 0); 1959 return USBD_NORMAL_COMPLETION; 1960 } 1961 tog = upipe->nexttoggle; 1962 if (ntd % 2 == 0) 1963 tog ^= 1; 1964 upipe->nexttoggle = tog ^ 1; 1965 lastp = NULL; 1966 lastlink = UHCI_PTR_T; 1967 ntd--; 1968 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1969 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1970 status |= UHCI_TD_LS; 1971 if (flags & USBD_SHORT_XFER_OK) 1972 status |= UHCI_TD_SPD; 1973 usb_syncmem(dma, 0, len, 1974 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1975 for (i = ntd; i >= 0; i--) { 1976 p = uhci_alloc_std(sc); 1977 if (p == NULL) { 1978 KASSERT(lastp != NULL); 1979 uhci_free_std_chain(sc, lastp, NULL); 1980 return USBD_NOMEM; 1981 } 1982 p->link.std = lastp; 1983 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1984 lastp = p; 1985 lastlink = p->physaddr; 1986 p->td.td_status = htole32(status); 1987 if (i == ntd) { 1988 /* last TD */ 1989 l = len % maxp; 1990 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1991 l = maxp; 1992 *ep = p; 1993 } else 1994 l = maxp; 1995 p->td.td_token = 1996 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1997 UHCI_TD_OUT(l, endpt, addr, tog)); 1998 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1999 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 2000 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2001 tog ^= 1; 2002 } 2003 *sp = lastp; 2004 DPRINTFN(10, "nexttog=%d", upipe->nexttoggle, 2005 0, 0, 0); 2006 2007 return USBD_NORMAL_COMPLETION; 2008 } 2009 2010 void 2011 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2012 { 2013 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2014 upipe->nexttoggle = 0; 2015 } 2016 2017 void 2018 uhci_noop(struct usbd_pipe *pipe) 2019 { 2020 } 2021 2022 usbd_status 2023 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2024 { 2025 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2026 usbd_status err; 2027 2028 /* Insert last in queue. */ 2029 mutex_enter(&sc->sc_lock); 2030 err = usb_insert_transfer(xfer); 2031 mutex_exit(&sc->sc_lock); 2032 if (err) 2033 return err; 2034 2035 /* 2036 * Pipe isn't running (otherwise err would be USBD_INPROG), 2037 * so start it first. 2038 */ 2039 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2040 } 2041 2042 usbd_status 2043 uhci_device_bulk_start(struct usbd_xfer *xfer) 2044 { 2045 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2046 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2047 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 2048 uhci_soft_td_t *data, *dataend; 2049 uhci_soft_qh_t *sqh; 2050 usbd_status err; 2051 int len, isread, endpt; 2052 2053 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2054 DPRINTFN(3, "xfer=%p len=%d flags=%d ii=%p", 2055 xfer, xfer->ux_length, xfer->ux_flags, ii); 2056 2057 if (sc->sc_dying) 2058 return USBD_IOERROR; 2059 2060 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2061 2062 mutex_enter(&sc->sc_lock); 2063 2064 len = xfer->ux_length; 2065 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2066 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2067 sqh = upipe->bulk.sqh; 2068 2069 upipe->bulk.isread = isread; 2070 upipe->bulk.length = len; 2071 2072 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2073 &xfer->ux_dmabuf, &data, &dataend); 2074 if (err) { 2075 mutex_exit(&sc->sc_lock); 2076 return err; 2077 } 2078 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2079 usb_syncmem(&dataend->dma, 2080 dataend->offs + offsetof(uhci_td_t, td_status), 2081 sizeof(dataend->td.td_status), 2082 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2083 2084 2085 #ifdef UHCI_DEBUG 2086 if (uhcidebug > 8) { 2087 DPRINTFN(8, "data(1)", 0, 0, 0, 0); 2088 uhci_dump_tds(data); 2089 } 2090 #endif 2091 2092 /* Set up interrupt info. */ 2093 ii->xfer = xfer; 2094 ii->stdstart = data; 2095 ii->stdend = dataend; 2096 2097 KASSERT(ii->isdone); 2098 #ifdef DIAGNOSTIC 2099 ii->isdone = false; 2100 #endif 2101 2102 sqh->elink = data; 2103 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2104 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2105 2106 uhci_add_bulk(sc, sqh); 2107 uhci_add_intr_info(sc, ii); 2108 2109 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2110 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2111 uhci_timeout, ii); 2112 } 2113 xfer->ux_status = USBD_IN_PROGRESS; 2114 2115 #ifdef UHCI_DEBUG 2116 if (uhcidebug > 10) { 2117 DPRINTFN(10, "data(2)", 0, 0, 0, 0); 2118 uhci_dump_tds(data); 2119 } 2120 #endif 2121 2122 if (sc->sc_bus.ub_usepolling) 2123 uhci_waitintr(sc, xfer); 2124 2125 mutex_exit(&sc->sc_lock); 2126 return USBD_IN_PROGRESS; 2127 } 2128 2129 /* Abort a device bulk request. */ 2130 void 2131 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2132 { 2133 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2134 2135 KASSERT(mutex_owned(&sc->sc_lock)); 2136 2137 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2138 2139 uhci_abort_xfer(xfer, USBD_CANCELLED); 2140 } 2141 2142 /* 2143 * Abort a device request. 2144 * If this routine is called at splusb() it guarantees that the request 2145 * will be removed from the hardware scheduling and that the callback 2146 * for it will be called with USBD_CANCELLED status. 2147 * It's impossible to guarantee that the requested transfer will not 2148 * have happened since the hardware runs concurrently. 2149 * If the transaction has already happened we rely on the ordinary 2150 * interrupt processing to process it. 2151 * XXX This is most probably wrong. 2152 * XXXMRG this doesn't make sense anymore. 2153 */ 2154 void 2155 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2156 { 2157 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 2158 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2159 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2160 uhci_soft_td_t *std; 2161 int wake; 2162 2163 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2164 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2165 2166 KASSERT(mutex_owned(&sc->sc_lock)); 2167 ASSERT_SLEEPABLE(); 2168 2169 if (sc->sc_dying) { 2170 /* If we're dying, just do the software part. */ 2171 xfer->ux_status = status; /* make software ignore it */ 2172 callout_stop(&xfer->ux_callout); 2173 usb_transfer_complete(xfer); 2174 return; 2175 } 2176 2177 /* 2178 * If an abort is already in progress then just wait for it to 2179 * complete and return. 2180 */ 2181 if (xfer->ux_hcflags & UXFER_ABORTING) { 2182 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2183 #ifdef DIAGNOSTIC 2184 if (status == USBD_TIMEOUT) 2185 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2186 #endif 2187 /* Override the status which might be USBD_TIMEOUT. */ 2188 xfer->ux_status = status; 2189 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2190 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2191 while (xfer->ux_hcflags & UXFER_ABORTING) 2192 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2193 goto done; 2194 } 2195 xfer->ux_hcflags |= UXFER_ABORTING; 2196 2197 /* 2198 * Step 1: Make interrupt routine and hardware ignore xfer. 2199 */ 2200 xfer->ux_status = status; /* make software ignore it */ 2201 callout_stop(&xfer->ux_callout); 2202 DPRINTF("stop ii=%p", ii, 0, 0, 0); 2203 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2204 usb_syncmem(&std->dma, 2205 std->offs + offsetof(uhci_td_t, td_status), 2206 sizeof(std->td.td_status), 2207 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2208 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2209 usb_syncmem(&std->dma, 2210 std->offs + offsetof(uhci_td_t, td_status), 2211 sizeof(std->td.td_status), 2212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2213 } 2214 2215 /* 2216 * Step 2: Wait until we know hardware has finished any possible 2217 * use of the xfer. Also make sure the soft interrupt routine 2218 * has run. 2219 */ 2220 /* Hardware finishes in 1ms */ 2221 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2222 sc->sc_softwake = 1; 2223 usb_schedsoftintr(&sc->sc_bus); 2224 DPRINTF("cv_wait", 0, 0, 0, 0); 2225 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2226 2227 /* 2228 * Step 3: Execute callback. 2229 */ 2230 DPRINTF("callback", 0, 0, 0, 0); 2231 #ifdef DIAGNOSTIC 2232 ii->isdone = true; 2233 #endif 2234 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2235 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2236 usb_transfer_complete(xfer); 2237 if (wake) 2238 cv_broadcast(&xfer->ux_hccv); 2239 done: 2240 KASSERT(mutex_owned(&sc->sc_lock)); 2241 } 2242 2243 /* Close a device bulk pipe. */ 2244 void 2245 uhci_device_bulk_close(struct usbd_pipe *pipe) 2246 { 2247 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2248 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2249 2250 KASSERT(mutex_owned(&sc->sc_lock)); 2251 2252 uhci_free_sqh(sc, upipe->bulk.sqh); 2253 2254 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2255 } 2256 2257 usbd_status 2258 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2259 { 2260 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2261 usbd_status err; 2262 2263 /* Insert last in queue. */ 2264 mutex_enter(&sc->sc_lock); 2265 err = usb_insert_transfer(xfer); 2266 mutex_exit(&sc->sc_lock); 2267 if (err) 2268 return err; 2269 2270 /* 2271 * Pipe isn't running (otherwise err would be USBD_INPROG), 2272 * so start it first. 2273 */ 2274 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2275 } 2276 2277 usbd_status 2278 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2279 { 2280 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2281 usbd_status err; 2282 2283 if (sc->sc_dying) 2284 return USBD_IOERROR; 2285 2286 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2287 2288 mutex_enter(&sc->sc_lock); 2289 err = uhci_device_request(xfer); 2290 mutex_exit(&sc->sc_lock); 2291 if (err) 2292 return err; 2293 2294 if (sc->sc_bus.ub_usepolling) 2295 uhci_waitintr(sc, xfer); 2296 return USBD_IN_PROGRESS; 2297 } 2298 2299 usbd_status 2300 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2301 { 2302 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2303 usbd_status err; 2304 2305 /* Insert last in queue. */ 2306 mutex_enter(&sc->sc_lock); 2307 err = usb_insert_transfer(xfer); 2308 mutex_exit(&sc->sc_lock); 2309 if (err) 2310 return err; 2311 2312 /* 2313 * Pipe isn't running (otherwise err would be USBD_INPROG), 2314 * so start it first. 2315 */ 2316 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2317 } 2318 2319 usbd_status 2320 uhci_device_intr_start(struct usbd_xfer *xfer) 2321 { 2322 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2323 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2324 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 2325 uhci_soft_td_t *data, *dataend; 2326 uhci_soft_qh_t *sqh; 2327 usbd_status err; 2328 int isread, endpt; 2329 int i; 2330 2331 if (sc->sc_dying) 2332 return USBD_IOERROR; 2333 2334 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2335 2336 DPRINTFN(3, "xfer=%p len=%d flags=%d", 2337 xfer, xfer->ux_length, xfer->ux_flags, 0); 2338 2339 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2340 2341 mutex_enter(&sc->sc_lock); 2342 2343 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2344 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2345 2346 upipe->intr.isread = isread; 2347 2348 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2349 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2350 &dataend); 2351 if (err) { 2352 mutex_exit(&sc->sc_lock); 2353 return err; 2354 } 2355 2356 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2357 usb_syncmem(&dataend->dma, 2358 dataend->offs + offsetof(uhci_td_t, td_status), 2359 sizeof(dataend->td.td_status), 2360 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2361 2362 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2363 #ifdef UHCI_DEBUG 2364 if (uhcidebug > 10) { 2365 uhci_dump_tds(data); 2366 uhci_dump_qh(upipe->intr.qhs[0]); 2367 } 2368 #endif 2369 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2370 2371 /* Set up interrupt info. */ 2372 ii->xfer = xfer; 2373 ii->stdstart = data; 2374 ii->stdend = dataend; 2375 KASSERT(ii->isdone); 2376 #ifdef DIAGNOSTIC 2377 ii->isdone = false; 2378 #endif 2379 2380 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2381 for (i = 0; i < upipe->intr.npoll; i++) { 2382 sqh = upipe->intr.qhs[i]; 2383 sqh->elink = data; 2384 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2385 usb_syncmem(&sqh->dma, 2386 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2387 sizeof(sqh->qh.qh_elink), 2388 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2389 } 2390 uhci_add_intr_info(sc, ii); 2391 xfer->ux_status = USBD_IN_PROGRESS; 2392 mutex_exit(&sc->sc_lock); 2393 2394 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2395 #ifdef UHCI_DEBUG 2396 if (uhcidebug > 10) { 2397 uhci_dump_tds(data); 2398 uhci_dump_qh(upipe->intr.qhs[0]); 2399 } 2400 #endif 2401 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2402 2403 return USBD_IN_PROGRESS; 2404 } 2405 2406 /* Abort a device control request. */ 2407 void 2408 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2409 { 2410 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2411 2412 KASSERT(mutex_owned(&sc->sc_lock)); 2413 2414 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2415 uhci_abort_xfer(xfer, USBD_CANCELLED); 2416 } 2417 2418 /* Close a device control pipe. */ 2419 void 2420 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2421 { 2422 } 2423 2424 /* Abort a device interrupt request. */ 2425 void 2426 uhci_device_intr_abort(struct usbd_xfer *xfer) 2427 { 2428 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2429 2430 KASSERT(mutex_owned(&sc->sc_lock)); 2431 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2432 2433 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2434 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2435 2436 uhci_abort_xfer(xfer, USBD_CANCELLED); 2437 } 2438 2439 /* Close a device interrupt pipe. */ 2440 void 2441 uhci_device_intr_close(struct usbd_pipe *pipe) 2442 { 2443 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2444 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2445 int i, npoll; 2446 2447 KASSERT(mutex_owned(&sc->sc_lock)); 2448 2449 /* Unlink descriptors from controller data structures. */ 2450 npoll = upipe->intr.npoll; 2451 for (i = 0; i < npoll; i++) 2452 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2453 2454 /* 2455 * We now have to wait for any activity on the physical 2456 * descriptors to stop. 2457 */ 2458 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2459 2460 for(i = 0; i < npoll; i++) 2461 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2462 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2463 2464 /* XXX free other resources */ 2465 } 2466 2467 usbd_status 2468 uhci_device_request(struct usbd_xfer *xfer) 2469 { 2470 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2471 usb_device_request_t *req = &xfer->ux_request; 2472 struct usbd_device *dev = upipe->pipe.up_dev; 2473 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2474 int addr = dev->ud_addr; 2475 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2476 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 2477 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2478 uhci_soft_qh_t *sqh; 2479 int len; 2480 uint32_t ls; 2481 usbd_status err; 2482 int isread; 2483 2484 KASSERT(mutex_owned(&sc->sc_lock)); 2485 2486 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2487 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2488 "wValue=0x%04x, wIndex=0x%04x", 2489 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2490 UGETW(req->wIndex)); 2491 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2492 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2493 2494 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2495 isread = req->bmRequestType & UT_READ; 2496 len = UGETW(req->wLength); 2497 2498 setup = upipe->ctrl.setup; 2499 stat = upipe->ctrl.stat; 2500 sqh = upipe->ctrl.sqh; 2501 2502 /* Set up data transaction */ 2503 if (len != 0) { 2504 upipe->nexttoggle = 1; 2505 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2506 &xfer->ux_dmabuf, &data, &dataend); 2507 if (err) 2508 return err; 2509 next = data; 2510 dataend->link.std = stat; 2511 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2512 usb_syncmem(&dataend->dma, 2513 dataend->offs + offsetof(uhci_td_t, td_link), 2514 sizeof(dataend->td.td_link), 2515 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2516 } else { 2517 next = stat; 2518 } 2519 upipe->ctrl.length = len; 2520 2521 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2522 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2523 2524 setup->link.std = next; 2525 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2526 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2527 UHCI_TD_ACTIVE); 2528 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2529 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2530 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2532 2533 stat->link.std = NULL; 2534 stat->td.td_link = htole32(UHCI_PTR_T); 2535 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2536 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2537 stat->td.td_token = 2538 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2539 UHCI_TD_IN (0, endpt, addr, 1)); 2540 stat->td.td_buffer = htole32(0); 2541 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2542 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2543 2544 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2545 #ifdef UHCI_DEBUG 2546 if (uhcidebug > 10) { 2547 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2548 uhci_dump_tds(setup); 2549 } 2550 #endif 2551 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2552 2553 /* Set up interrupt info. */ 2554 ii->xfer = xfer; 2555 ii->stdstart = setup; 2556 ii->stdend = stat; 2557 KASSERT(ii->isdone); 2558 #ifdef DIAGNOSTIC 2559 ii->isdone = false; 2560 #endif 2561 2562 sqh->elink = setup; 2563 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2564 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2565 2566 if (dev->ud_speed == USB_SPEED_LOW) 2567 uhci_add_ls_ctrl(sc, sqh); 2568 else 2569 uhci_add_hs_ctrl(sc, sqh); 2570 uhci_add_intr_info(sc, ii); 2571 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2572 #ifdef UHCI_DEBUG 2573 if (uhcidebug > 12) { 2574 uhci_soft_td_t *std; 2575 uhci_soft_qh_t *xqh; 2576 uhci_soft_qh_t *sxqh; 2577 int maxqh = 0; 2578 uhci_physaddr_t link; 2579 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2580 for (std = sc->sc_vframes[0].htd, link = 0; 2581 (link & UHCI_PTR_QH) == 0; 2582 std = std->link.std) { 2583 link = le32toh(std->td.td_link); 2584 uhci_dump_td(std); 2585 } 2586 sxqh = (uhci_soft_qh_t *)std; 2587 uhci_dump_qh(sxqh); 2588 for (xqh = sxqh; 2589 xqh != NULL; 2590 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2591 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2592 uhci_dump_qh(xqh); 2593 } 2594 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2595 uhci_dump_qh(sqh); 2596 uhci_dump_tds(sqh->elink); 2597 } 2598 #endif 2599 DPRINTFN(12, "--- dump end ---", 0, 0, 0, 0); 2600 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2601 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2602 uhci_timeout, ii); 2603 } 2604 xfer->ux_status = USBD_IN_PROGRESS; 2605 2606 return USBD_NORMAL_COMPLETION; 2607 } 2608 2609 usbd_status 2610 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2611 { 2612 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2613 usbd_status err; 2614 2615 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2616 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2617 2618 /* Put it on our queue, */ 2619 mutex_enter(&sc->sc_lock); 2620 err = usb_insert_transfer(xfer); 2621 mutex_exit(&sc->sc_lock); 2622 2623 /* bail out on error, */ 2624 if (err && err != USBD_IN_PROGRESS) 2625 return err; 2626 2627 /* XXX should check inuse here */ 2628 2629 /* insert into schedule, */ 2630 uhci_device_isoc_enter(xfer); 2631 2632 /* and start if the pipe wasn't running */ 2633 if (!err) 2634 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2635 2636 return err; 2637 } 2638 2639 void 2640 uhci_device_isoc_enter(struct usbd_xfer *xfer) 2641 { 2642 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2643 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2644 struct isoc *isoc = &upipe->isoc; 2645 uhci_soft_td_t *std; 2646 uint32_t buf, len, status, offs; 2647 int i, next, nframes; 2648 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2649 2650 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2651 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2652 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2653 2654 if (sc->sc_dying) 2655 return; 2656 2657 if (xfer->ux_status == USBD_IN_PROGRESS) { 2658 /* This request has already been entered into the frame list */ 2659 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2660 /* XXX */ 2661 } 2662 2663 #ifdef DIAGNOSTIC 2664 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2665 printf("uhci_device_isoc_enter: overflow!\n"); 2666 #endif 2667 2668 next = isoc->next; 2669 if (next == -1) { 2670 /* Not in use yet, schedule it a few frames ahead. */ 2671 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2672 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2673 } 2674 2675 xfer->ux_status = USBD_IN_PROGRESS; 2676 UHCI_XFER2UXFER(xfer)->curframe = next; 2677 2678 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2679 offs = 0; 2680 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2681 UHCI_TD_ACTIVE | 2682 UHCI_TD_IOS); 2683 nframes = xfer->ux_nframes; 2684 mutex_enter(&sc->sc_lock); 2685 for (i = 0; i < nframes; i++) { 2686 std = isoc->stds[next]; 2687 if (++next >= UHCI_VFRAMELIST_COUNT) 2688 next = 0; 2689 len = xfer->ux_frlengths[i]; 2690 std->td.td_buffer = htole32(buf); 2691 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2692 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2693 if (i == nframes - 1) 2694 status |= UHCI_TD_IOC; 2695 std->td.td_status = htole32(status); 2696 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2697 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2698 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2699 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2700 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2701 #ifdef UHCI_DEBUG 2702 if (uhcidebug > 5) { 2703 DPRINTF("TD %d", i, 0, 0, 0); 2704 uhci_dump_td(std); 2705 } 2706 #endif 2707 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2708 buf += len; 2709 offs += len; 2710 } 2711 isoc->next = next; 2712 isoc->inuse += xfer->ux_nframes; 2713 2714 mutex_exit(&sc->sc_lock); 2715 } 2716 2717 usbd_status 2718 uhci_device_isoc_start(struct usbd_xfer *xfer) 2719 { 2720 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2721 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2722 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 2723 uhci_soft_td_t *end; 2724 int i; 2725 2726 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2727 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2728 2729 mutex_enter(&sc->sc_lock); 2730 2731 if (sc->sc_dying) { 2732 mutex_exit(&sc->sc_lock); 2733 return USBD_IOERROR; 2734 } 2735 2736 #ifdef DIAGNOSTIC 2737 if (xfer->ux_status != USBD_IN_PROGRESS) 2738 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2739 #endif 2740 2741 /* Find the last TD */ 2742 i = UHCI_XFER2UXFER(xfer)->curframe + xfer->ux_nframes; 2743 if (i >= UHCI_VFRAMELIST_COUNT) 2744 i -= UHCI_VFRAMELIST_COUNT; 2745 end = upipe->isoc.stds[i]; 2746 2747 KASSERT(end != NULL); 2748 2749 /* Set up interrupt info. */ 2750 ii->xfer = xfer; 2751 ii->stdstart = end; 2752 ii->stdend = end; 2753 2754 KASSERT(ii->isdone); 2755 #ifdef DIAGNOSTIC 2756 ii->isdone = false; 2757 #endif 2758 uhci_add_intr_info(sc, ii); 2759 2760 mutex_exit(&sc->sc_lock); 2761 2762 return USBD_IN_PROGRESS; 2763 } 2764 2765 void 2766 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2767 { 2768 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2769 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2770 uhci_soft_td_t **stds = upipe->isoc.stds; 2771 uhci_soft_td_t *std; 2772 int i, n, nframes, maxlen, len; 2773 2774 KASSERT(mutex_owned(&sc->sc_lock)); 2775 2776 /* Transfer is already done. */ 2777 if (xfer->ux_status != USBD_NOT_STARTED && 2778 xfer->ux_status != USBD_IN_PROGRESS) { 2779 return; 2780 } 2781 2782 /* Give xfer the requested abort code. */ 2783 xfer->ux_status = USBD_CANCELLED; 2784 2785 /* make hardware ignore it, */ 2786 nframes = xfer->ux_nframes; 2787 n = UHCI_XFER2UXFER(xfer)->curframe; 2788 maxlen = 0; 2789 for (i = 0; i < nframes; i++) { 2790 std = stds[n]; 2791 usb_syncmem(&std->dma, 2792 std->offs + offsetof(uhci_td_t, td_status), 2793 sizeof(std->td.td_status), 2794 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2795 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2796 usb_syncmem(&std->dma, 2797 std->offs + offsetof(uhci_td_t, td_status), 2798 sizeof(std->td.td_status), 2799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2800 usb_syncmem(&std->dma, 2801 std->offs + offsetof(uhci_td_t, td_token), 2802 sizeof(std->td.td_token), 2803 BUS_DMASYNC_POSTWRITE); 2804 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2805 if (len > maxlen) 2806 maxlen = len; 2807 if (++n >= UHCI_VFRAMELIST_COUNT) 2808 n = 0; 2809 } 2810 2811 /* and wait until we are sure the hardware has finished. */ 2812 delay(maxlen); 2813 2814 #ifdef DIAGNOSTIC 2815 UHCI_XFER2UXFER(xfer)->iinfo.isdone = true; 2816 #endif 2817 /* Run callback and remove from interrupt list. */ 2818 usb_transfer_complete(xfer); 2819 2820 KASSERT(mutex_owned(&sc->sc_lock)); 2821 } 2822 2823 void 2824 uhci_device_isoc_close(struct usbd_pipe *pipe) 2825 { 2826 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2827 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2828 uhci_soft_td_t *std, *vstd; 2829 struct isoc *isoc; 2830 int i; 2831 2832 KASSERT(mutex_owned(&sc->sc_lock)); 2833 2834 /* 2835 * Make sure all TDs are marked as inactive. 2836 * Wait for completion. 2837 * Unschedule. 2838 * Deallocate. 2839 */ 2840 isoc = &upipe->isoc; 2841 2842 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2843 std = isoc->stds[i]; 2844 usb_syncmem(&std->dma, 2845 std->offs + offsetof(uhci_td_t, td_status), 2846 sizeof(std->td.td_status), 2847 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2848 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2849 usb_syncmem(&std->dma, 2850 std->offs + offsetof(uhci_td_t, td_status), 2851 sizeof(std->td.td_status), 2852 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2853 } 2854 /* wait for completion */ 2855 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2856 2857 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2858 std = isoc->stds[i]; 2859 for (vstd = sc->sc_vframes[i].htd; 2860 vstd != NULL && vstd->link.std != std; 2861 vstd = vstd->link.std) 2862 ; 2863 if (vstd == NULL) { 2864 /*panic*/ 2865 printf("uhci_device_isoc_close: %p not found\n", std); 2866 mutex_exit(&sc->sc_lock); 2867 return; 2868 } 2869 vstd->link = std->link; 2870 usb_syncmem(&std->dma, 2871 std->offs + offsetof(uhci_td_t, td_link), 2872 sizeof(std->td.td_link), 2873 BUS_DMASYNC_POSTWRITE); 2874 vstd->td.td_link = std->td.td_link; 2875 usb_syncmem(&vstd->dma, 2876 vstd->offs + offsetof(uhci_td_t, td_link), 2877 sizeof(vstd->td.td_link), 2878 BUS_DMASYNC_PREWRITE); 2879 uhci_free_std(sc, std); 2880 } 2881 2882 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2883 } 2884 2885 usbd_status 2886 uhci_setup_isoc(struct usbd_pipe *pipe) 2887 { 2888 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2889 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2890 int addr = upipe->pipe.up_dev->ud_addr; 2891 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2892 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2893 uhci_soft_td_t *std, *vstd; 2894 uint32_t token; 2895 struct isoc *isoc; 2896 int i; 2897 2898 isoc = &upipe->isoc; 2899 isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2900 sizeof(uhci_soft_td_t *), 2901 KM_SLEEP); 2902 if (isoc->stds == NULL) 2903 return USBD_NOMEM; 2904 2905 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2906 UHCI_TD_OUT(0, endpt, addr, 0); 2907 2908 mutex_enter(&sc->sc_lock); 2909 2910 /* Allocate the TDs and mark as inactive; */ 2911 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2912 std = uhci_alloc_std(sc); 2913 if (std == 0) 2914 goto bad; 2915 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2916 std->td.td_token = htole32(token); 2917 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2918 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2919 isoc->stds[i] = std; 2920 } 2921 2922 /* Insert TDs into schedule. */ 2923 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2924 std = isoc->stds[i]; 2925 vstd = sc->sc_vframes[i].htd; 2926 usb_syncmem(&vstd->dma, 2927 vstd->offs + offsetof(uhci_td_t, td_link), 2928 sizeof(vstd->td.td_link), 2929 BUS_DMASYNC_POSTWRITE); 2930 std->link = vstd->link; 2931 std->td.td_link = vstd->td.td_link; 2932 usb_syncmem(&std->dma, 2933 std->offs + offsetof(uhci_td_t, td_link), 2934 sizeof(std->td.td_link), 2935 BUS_DMASYNC_PREWRITE); 2936 vstd->link.std = std; 2937 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2938 usb_syncmem(&vstd->dma, 2939 vstd->offs + offsetof(uhci_td_t, td_link), 2940 sizeof(vstd->td.td_link), 2941 BUS_DMASYNC_PREWRITE); 2942 } 2943 mutex_exit(&sc->sc_lock); 2944 2945 isoc->next = -1; 2946 isoc->inuse = 0; 2947 2948 return USBD_NORMAL_COMPLETION; 2949 2950 bad: 2951 while (--i >= 0) 2952 uhci_free_std(sc, isoc->stds[i]); 2953 mutex_exit(&sc->sc_lock); 2954 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2955 return USBD_NOMEM; 2956 } 2957 2958 void 2959 uhci_device_isoc_done(struct usbd_xfer *xfer) 2960 { 2961 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 2962 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2963 int i, offs; 2964 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2965 2966 2967 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2968 DPRINTFN(4, "length=%d, ux_state=0x%08x", 2969 xfer->ux_actlen, xfer->ux_state, 0, 0); 2970 2971 if (ii->xfer != xfer) 2972 /* Not on interrupt list, ignore it. */ 2973 return; 2974 2975 if (!uhci_active_intr_info(ii)) 2976 return; 2977 2978 #ifdef DIAGNOSTIC 2979 if (ii->stdend == NULL) { 2980 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2981 #ifdef UHCI_DEBUG 2982 uhci_dump_ii(ii); 2983 #endif 2984 return; 2985 } 2986 #endif 2987 2988 /* Turn off the interrupt since it is active even if the TD is not. */ 2989 usb_syncmem(&ii->stdend->dma, 2990 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2991 sizeof(ii->stdend->td.td_status), 2992 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2993 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2994 usb_syncmem(&ii->stdend->dma, 2995 ii->stdend->offs + offsetof(uhci_td_t, td_status), 2996 sizeof(ii->stdend->td.td_status), 2997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2998 2999 uhci_del_intr_info(ii); /* remove from active list */ 3000 3001 offs = 0; 3002 for (i = 0; i < xfer->ux_nframes; i++) { 3003 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3004 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3005 offs += xfer->ux_frlengths[i]; 3006 } 3007 } 3008 3009 void 3010 uhci_device_intr_done(struct usbd_xfer *xfer) 3011 { 3012 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 3013 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3014 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3015 uhci_soft_qh_t *sqh; 3016 int i, npoll, isread; 3017 3018 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3019 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3020 3021 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3022 3023 npoll = upipe->intr.npoll; 3024 for(i = 0; i < npoll; i++) { 3025 sqh = upipe->intr.qhs[i]; 3026 sqh->elink = NULL; 3027 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3028 usb_syncmem(&sqh->dma, 3029 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3030 sizeof(sqh->qh.qh_elink), 3031 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3032 } 3033 uhci_free_std_chain(sc, ii->stdstart, NULL); 3034 3035 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3036 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3037 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3038 3039 /* XXX Wasteful. */ 3040 if (xfer->ux_pipe->up_repeat) { 3041 uhci_soft_td_t *data, *dataend; 3042 3043 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3044 3045 /* This alloc cannot fail since we freed the chain above. */ 3046 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3047 upipe->intr.isread, xfer->ux_flags, 3048 &xfer->ux_dmabuf, &data, &dataend); 3049 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3050 usb_syncmem(&dataend->dma, 3051 dataend->offs + offsetof(uhci_td_t, td_status), 3052 sizeof(dataend->td.td_status), 3053 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3054 3055 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 3056 #ifdef UHCI_DEBUG 3057 if (uhcidebug > 10) { 3058 uhci_dump_tds(data); 3059 uhci_dump_qh(upipe->intr.qhs[0]); 3060 } 3061 #endif 3062 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 3063 3064 ii->stdstart = data; 3065 ii->stdend = dataend; 3066 KASSERT(ii->isdone); 3067 #ifdef DIAGNOSTIC 3068 ii->isdone = false; 3069 #endif 3070 for (i = 0; i < npoll; i++) { 3071 sqh = upipe->intr.qhs[i]; 3072 sqh->elink = data; 3073 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3074 usb_syncmem(&sqh->dma, 3075 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3076 sizeof(sqh->qh.qh_elink), 3077 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3078 } 3079 xfer->ux_status = USBD_IN_PROGRESS; 3080 /* The ii is already on the examined list, just leave it. */ 3081 } else { 3082 DPRINTFN(5, "removing", 0, 0, 0, 0); 3083 if (uhci_active_intr_info(ii)) 3084 uhci_del_intr_info(ii); 3085 } 3086 } 3087 3088 /* Deallocate request data structures */ 3089 void 3090 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3091 { 3092 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 3093 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3094 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3095 int len = UGETW(xfer->ux_request.wLength); 3096 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3097 3098 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3099 3100 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3101 3102 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3103 3104 if (!uhci_active_intr_info(ii)) 3105 return; 3106 3107 uhci_del_intr_info(ii); /* remove from active list */ 3108 3109 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3110 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3111 else 3112 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3113 3114 if (upipe->ctrl.length != 0) 3115 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3116 3117 if (len) { 3118 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3119 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3120 } 3121 usb_syncmem(&upipe->ctrl.reqdma, 0, 3122 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3123 3124 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3125 } 3126 3127 /* Deallocate request data structures */ 3128 void 3129 uhci_device_bulk_done(struct usbd_xfer *xfer) 3130 { 3131 uhci_intr_info_t *ii = &UHCI_XFER2UXFER(xfer)->iinfo; 3132 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3133 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3134 3135 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3136 DPRINTFN(5, "xfer=%p ii=%p sc=%p upipe=%p", xfer, ii, sc, 3137 upipe); 3138 3139 KASSERT(mutex_owned(&sc->sc_lock)); 3140 3141 if (!uhci_active_intr_info(ii)) 3142 return; 3143 3144 uhci_del_intr_info(ii); /* remove from active list */ 3145 3146 uhci_remove_bulk(sc, upipe->bulk.sqh); 3147 3148 uhci_free_std_chain(sc, ii->stdstart, NULL); 3149 3150 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3151 } 3152 3153 /* Add interrupt QH, called with vflock. */ 3154 void 3155 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3156 { 3157 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3158 uhci_soft_qh_t *eqh; 3159 3160 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3161 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3162 3163 eqh = vf->eqh; 3164 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3165 sizeof(eqh->qh.qh_hlink), 3166 BUS_DMASYNC_POSTWRITE); 3167 sqh->hlink = eqh->hlink; 3168 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3169 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3170 sizeof(sqh->qh.qh_hlink), 3171 BUS_DMASYNC_PREWRITE); 3172 eqh->hlink = sqh; 3173 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3174 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3175 sizeof(eqh->qh.qh_hlink), 3176 BUS_DMASYNC_PREWRITE); 3177 vf->eqh = sqh; 3178 vf->bandwidth++; 3179 } 3180 3181 /* Remove interrupt QH. */ 3182 void 3183 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3184 { 3185 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3186 uhci_soft_qh_t *pqh; 3187 3188 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3189 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3190 3191 /* See comment in uhci_remove_ctrl() */ 3192 3193 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3194 sizeof(sqh->qh.qh_elink), 3195 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3196 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3197 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3198 usb_syncmem(&sqh->dma, 3199 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3200 sizeof(sqh->qh.qh_elink), 3201 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3202 delay(UHCI_QH_REMOVE_DELAY); 3203 } 3204 3205 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3206 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3207 sizeof(sqh->qh.qh_hlink), 3208 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3209 pqh->hlink = sqh->hlink; 3210 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3211 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3212 sizeof(pqh->qh.qh_hlink), 3213 BUS_DMASYNC_PREWRITE); 3214 delay(UHCI_QH_REMOVE_DELAY); 3215 if (vf->eqh == sqh) 3216 vf->eqh = pqh; 3217 vf->bandwidth--; 3218 } 3219 3220 usbd_status 3221 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3222 { 3223 uhci_soft_qh_t *sqh; 3224 int i, npoll; 3225 u_int bestbw, bw, bestoffs, offs; 3226 3227 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3228 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3229 if (ival == 0) { 3230 printf("uhci_device_setintr: 0 interval\n"); 3231 return USBD_INVAL; 3232 } 3233 3234 if (ival > UHCI_VFRAMELIST_COUNT) 3235 ival = UHCI_VFRAMELIST_COUNT; 3236 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3237 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3238 3239 upipe->intr.npoll = npoll; 3240 upipe->intr.qhs = 3241 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3242 if (upipe->intr.qhs == NULL) 3243 return USBD_NOMEM; 3244 3245 /* 3246 * Figure out which offset in the schedule that has most 3247 * bandwidth left over. 3248 */ 3249 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3250 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3251 for (bw = i = 0; i < npoll; i++) 3252 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3253 if (bw < bestbw) { 3254 bestbw = bw; 3255 bestoffs = offs; 3256 } 3257 } 3258 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3259 mutex_enter(&sc->sc_lock); 3260 for(i = 0; i < npoll; i++) { 3261 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3262 sqh->elink = NULL; 3263 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3264 usb_syncmem(&sqh->dma, 3265 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3266 sizeof(sqh->qh.qh_elink), 3267 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3268 sqh->pos = MOD(i * ival + bestoffs); 3269 } 3270 #undef MOD 3271 3272 /* Enter QHs into the controller data structures. */ 3273 for(i = 0; i < npoll; i++) 3274 uhci_add_intr(sc, upipe->intr.qhs[i]); 3275 mutex_exit(&sc->sc_lock); 3276 3277 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3278 3279 return USBD_NORMAL_COMPLETION; 3280 } 3281 3282 /* Open a new pipe. */ 3283 usbd_status 3284 uhci_open(struct usbd_pipe *pipe) 3285 { 3286 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3287 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3288 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3289 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3290 usbd_status err = USBD_NOMEM; 3291 int ival; 3292 3293 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3294 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3295 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3296 3297 if (sc->sc_dying) 3298 return USBD_IOERROR; 3299 3300 upipe->aborting = 0; 3301 /* toggle state needed for bulk endpoints */ 3302 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3303 3304 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3305 switch (ed->bEndpointAddress) { 3306 case USB_CONTROL_ENDPOINT: 3307 pipe->up_methods = &roothub_ctrl_methods; 3308 break; 3309 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3310 pipe->up_methods = &uhci_root_intr_methods; 3311 break; 3312 default: 3313 return USBD_INVAL; 3314 } 3315 } else { 3316 switch (ed->bmAttributes & UE_XFERTYPE) { 3317 case UE_CONTROL: 3318 pipe->up_methods = &uhci_device_ctrl_methods; 3319 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3320 if (upipe->ctrl.sqh == NULL) 3321 goto bad; 3322 upipe->ctrl.setup = uhci_alloc_std(sc); 3323 if (upipe->ctrl.setup == NULL) { 3324 uhci_free_sqh(sc, upipe->ctrl.sqh); 3325 goto bad; 3326 } 3327 upipe->ctrl.stat = uhci_alloc_std(sc); 3328 if (upipe->ctrl.stat == NULL) { 3329 uhci_free_sqh(sc, upipe->ctrl.sqh); 3330 uhci_free_std(sc, upipe->ctrl.setup); 3331 goto bad; 3332 } 3333 err = usb_allocmem(&sc->sc_bus, 3334 sizeof(usb_device_request_t), 3335 0, &upipe->ctrl.reqdma); 3336 if (err) { 3337 uhci_free_sqh(sc, upipe->ctrl.sqh); 3338 uhci_free_std(sc, upipe->ctrl.setup); 3339 uhci_free_std(sc, upipe->ctrl.stat); 3340 goto bad; 3341 } 3342 break; 3343 case UE_INTERRUPT: 3344 pipe->up_methods = &uhci_device_intr_methods; 3345 ival = pipe->up_interval; 3346 if (ival == USBD_DEFAULT_INTERVAL) 3347 ival = ed->bInterval; 3348 return uhci_device_setintr(sc, upipe, ival); 3349 case UE_ISOCHRONOUS: 3350 pipe->up_methods = &uhci_device_isoc_methods; 3351 return uhci_setup_isoc(pipe); 3352 case UE_BULK: 3353 pipe->up_methods = &uhci_device_bulk_methods; 3354 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3355 if (upipe->bulk.sqh == NULL) 3356 goto bad; 3357 break; 3358 } 3359 } 3360 return USBD_NORMAL_COMPLETION; 3361 3362 bad: 3363 return USBD_NOMEM; 3364 } 3365 3366 /* 3367 * Data structures and routines to emulate the root hub. 3368 */ 3369 /* 3370 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3371 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3372 * should not be used by the USB subsystem. As we cannot issue a 3373 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3374 * will be enabled as part of the reset. 3375 * 3376 * On the VT83C572, the port cannot be successfully enabled until the 3377 * outstanding "port enable change" and "connection status change" 3378 * events have been reset. 3379 */ 3380 Static usbd_status 3381 uhci_portreset(uhci_softc_t *sc, int index) 3382 { 3383 int lim, port, x; 3384 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3385 3386 if (index == 1) 3387 port = UHCI_PORTSC1; 3388 else if (index == 2) 3389 port = UHCI_PORTSC2; 3390 else 3391 return USBD_IOERROR; 3392 3393 x = URWMASK(UREAD2(sc, port)); 3394 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3395 3396 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3397 3398 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3399 UREAD2(sc, port), 0, 0); 3400 3401 x = URWMASK(UREAD2(sc, port)); 3402 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3403 3404 delay(100); 3405 3406 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3407 UREAD2(sc, port), 0, 0); 3408 3409 x = URWMASK(UREAD2(sc, port)); 3410 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3411 3412 for (lim = 10; --lim > 0;) { 3413 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3414 3415 x = UREAD2(sc, port); 3416 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3417 lim, x, 0); 3418 3419 if (!(x & UHCI_PORTSC_CCS)) { 3420 /* 3421 * No device is connected (or was disconnected 3422 * during reset). Consider the port reset. 3423 * The delay must be long enough to ensure on 3424 * the initial iteration that the device 3425 * connection will have been registered. 50ms 3426 * appears to be sufficient, but 20ms is not. 3427 */ 3428 DPRINTFN(3, "uhci port %d loop %u, device detached", 3429 index, lim, 0, 0); 3430 break; 3431 } 3432 3433 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3434 /* 3435 * Port enabled changed and/or connection 3436 * status changed were set. Reset either or 3437 * both raised flags (by writing a 1 to that 3438 * bit), and wait again for state to settle. 3439 */ 3440 UWRITE2(sc, port, URWMASK(x) | 3441 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3442 continue; 3443 } 3444 3445 if (x & UHCI_PORTSC_PE) 3446 /* Port is enabled */ 3447 break; 3448 3449 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3450 } 3451 3452 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3453 UREAD2(sc, port), 0, 0); 3454 3455 if (lim <= 0) { 3456 DPRINTF("uhci port %d reset timed out", index, 3457 0, 0, 0); 3458 return USBD_TIMEOUT; 3459 } 3460 3461 sc->sc_isreset = 1; 3462 return USBD_NORMAL_COMPLETION; 3463 } 3464 3465 Static int 3466 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3467 void *buf, int buflen) 3468 { 3469 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3470 int port, x; 3471 int status, change, totlen = 0; 3472 uint16_t len, value, index; 3473 usb_port_status_t ps; 3474 usbd_status err; 3475 3476 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3477 3478 if (sc->sc_dying) 3479 return -1; 3480 3481 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3482 req->bRequest, 0, 0); 3483 3484 len = UGETW(req->wLength); 3485 value = UGETW(req->wValue); 3486 index = UGETW(req->wIndex); 3487 3488 #define C(x,y) ((x) | ((y) << 8)) 3489 switch (C(req->bRequest, req->bmRequestType)) { 3490 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3491 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3492 if (len == 0) 3493 break; 3494 switch (value) { 3495 case C(0, UDESC_DEVICE): { 3496 usb_device_descriptor_t devd; 3497 3498 totlen = min(buflen, sizeof(devd)); 3499 memcpy(&devd, buf, totlen); 3500 USETW(devd.idVendor, sc->sc_id_vendor); 3501 memcpy(buf, &devd, totlen); 3502 break; 3503 } 3504 case C(1, UDESC_STRING): 3505 #define sd ((usb_string_descriptor_t *)buf) 3506 /* Vendor */ 3507 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3508 break; 3509 case C(2, UDESC_STRING): 3510 /* Product */ 3511 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3512 break; 3513 #undef sd 3514 default: 3515 /* default from usbroothub */ 3516 return buflen; 3517 } 3518 break; 3519 3520 /* Hub requests */ 3521 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3522 break; 3523 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3524 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3525 value, 0, 0); 3526 if (index == 1) 3527 port = UHCI_PORTSC1; 3528 else if (index == 2) 3529 port = UHCI_PORTSC2; 3530 else { 3531 return -1; 3532 } 3533 switch(value) { 3534 case UHF_PORT_ENABLE: 3535 x = URWMASK(UREAD2(sc, port)); 3536 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3537 break; 3538 case UHF_PORT_SUSPEND: 3539 x = URWMASK(UREAD2(sc, port)); 3540 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3541 break; 3542 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3543 /* see USB2 spec ch. 7.1.7.7 */ 3544 usb_delay_ms(&sc->sc_bus, 20); 3545 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3546 /* 10ms resume delay must be provided by caller */ 3547 break; 3548 case UHF_PORT_RESET: 3549 x = URWMASK(UREAD2(sc, port)); 3550 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3551 break; 3552 case UHF_C_PORT_CONNECTION: 3553 x = URWMASK(UREAD2(sc, port)); 3554 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3555 break; 3556 case UHF_C_PORT_ENABLE: 3557 x = URWMASK(UREAD2(sc, port)); 3558 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3559 break; 3560 case UHF_C_PORT_OVER_CURRENT: 3561 x = URWMASK(UREAD2(sc, port)); 3562 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3563 break; 3564 case UHF_C_PORT_RESET: 3565 sc->sc_isreset = 0; 3566 break; 3567 case UHF_PORT_CONNECTION: 3568 case UHF_PORT_OVER_CURRENT: 3569 case UHF_PORT_POWER: 3570 case UHF_PORT_LOW_SPEED: 3571 case UHF_C_PORT_SUSPEND: 3572 default: 3573 return -1; 3574 } 3575 break; 3576 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3577 if (index == 1) 3578 port = UHCI_PORTSC1; 3579 else if (index == 2) 3580 port = UHCI_PORTSC2; 3581 else { 3582 return -1; 3583 } 3584 if (len > 0) { 3585 *(uint8_t *)buf = 3586 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3587 UHCI_PORTSC_LS_SHIFT; 3588 totlen = 1; 3589 } 3590 break; 3591 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3592 if (len == 0) 3593 break; 3594 if ((value & 0xff) != 0) { 3595 return -1; 3596 } 3597 usb_hub_descriptor_t hubd; 3598 3599 totlen = min(buflen, sizeof(hubd)); 3600 memcpy(&hubd, buf, totlen); 3601 hubd.bNbrPorts = 2; 3602 memcpy(buf, &hubd, totlen); 3603 break; 3604 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3605 if (len != 4) { 3606 return -1; 3607 } 3608 memset(buf, 0, len); 3609 totlen = len; 3610 break; 3611 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3612 if (index == 1) 3613 port = UHCI_PORTSC1; 3614 else if (index == 2) 3615 port = UHCI_PORTSC2; 3616 else { 3617 return -1; 3618 } 3619 if (len != 4) { 3620 return -1; 3621 } 3622 x = UREAD2(sc, port); 3623 status = change = 0; 3624 if (x & UHCI_PORTSC_CCS) 3625 status |= UPS_CURRENT_CONNECT_STATUS; 3626 if (x & UHCI_PORTSC_CSC) 3627 change |= UPS_C_CONNECT_STATUS; 3628 if (x & UHCI_PORTSC_PE) 3629 status |= UPS_PORT_ENABLED; 3630 if (x & UHCI_PORTSC_POEDC) 3631 change |= UPS_C_PORT_ENABLED; 3632 if (x & UHCI_PORTSC_OCI) 3633 status |= UPS_OVERCURRENT_INDICATOR; 3634 if (x & UHCI_PORTSC_OCIC) 3635 change |= UPS_C_OVERCURRENT_INDICATOR; 3636 if (x & UHCI_PORTSC_SUSP) 3637 status |= UPS_SUSPEND; 3638 if (x & UHCI_PORTSC_LSDA) 3639 status |= UPS_LOW_SPEED; 3640 status |= UPS_PORT_POWER; 3641 if (sc->sc_isreset) 3642 change |= UPS_C_PORT_RESET; 3643 USETW(ps.wPortStatus, status); 3644 USETW(ps.wPortChange, change); 3645 totlen = min(len, sizeof(ps)); 3646 memcpy(buf, &ps, totlen); 3647 break; 3648 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3649 return -1; 3650 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3651 break; 3652 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3653 if (index == 1) 3654 port = UHCI_PORTSC1; 3655 else if (index == 2) 3656 port = UHCI_PORTSC2; 3657 else { 3658 return -1; 3659 } 3660 switch(value) { 3661 case UHF_PORT_ENABLE: 3662 x = URWMASK(UREAD2(sc, port)); 3663 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3664 break; 3665 case UHF_PORT_SUSPEND: 3666 x = URWMASK(UREAD2(sc, port)); 3667 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3668 break; 3669 case UHF_PORT_RESET: 3670 err = uhci_portreset(sc, index); 3671 if (err != USBD_NORMAL_COMPLETION) 3672 return -1; 3673 return 0; 3674 case UHF_PORT_POWER: 3675 /* Pretend we turned on power */ 3676 return 0; 3677 case UHF_C_PORT_CONNECTION: 3678 case UHF_C_PORT_ENABLE: 3679 case UHF_C_PORT_OVER_CURRENT: 3680 case UHF_PORT_CONNECTION: 3681 case UHF_PORT_OVER_CURRENT: 3682 case UHF_PORT_LOW_SPEED: 3683 case UHF_C_PORT_SUSPEND: 3684 case UHF_C_PORT_RESET: 3685 default: 3686 return -1; 3687 } 3688 break; 3689 default: 3690 /* default from usbroothub */ 3691 DPRINTF("returning %d (usbroothub default)", 3692 buflen, 0, 0, 0); 3693 return buflen; 3694 } 3695 3696 DPRINTF("returning %d", totlen, 0, 0, 0); 3697 3698 return totlen; 3699 } 3700 3701 /* Abort a root interrupt request. */ 3702 void 3703 uhci_root_intr_abort(struct usbd_xfer *xfer) 3704 { 3705 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3706 3707 KASSERT(mutex_owned(&sc->sc_lock)); 3708 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3709 3710 callout_stop(&sc->sc_poll_handle); 3711 sc->sc_intr_xfer = NULL; 3712 3713 xfer->ux_status = USBD_CANCELLED; 3714 #ifdef DIAGNOSTIC 3715 UHCI_XFER2UXFER(xfer)->iinfo.isdone = 1; 3716 #endif 3717 usb_transfer_complete(xfer); 3718 } 3719 3720 usbd_status 3721 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3722 { 3723 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3724 usbd_status err; 3725 3726 /* Insert last in queue. */ 3727 mutex_enter(&sc->sc_lock); 3728 err = usb_insert_transfer(xfer); 3729 mutex_exit(&sc->sc_lock); 3730 if (err) 3731 return err; 3732 3733 /* 3734 * Pipe isn't running (otherwise err would be USBD_INPROG), 3735 * start first 3736 */ 3737 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3738 } 3739 3740 /* Start a transfer on the root interrupt pipe */ 3741 usbd_status 3742 uhci_root_intr_start(struct usbd_xfer *xfer) 3743 { 3744 struct usbd_pipe *pipe = xfer->ux_pipe; 3745 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3746 unsigned int ival; 3747 3748 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3749 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3750 xfer->ux_flags, 0); 3751 3752 if (sc->sc_dying) 3753 return USBD_IOERROR; 3754 3755 /* XXX temporary variable needed to avoid gcc3 warning */ 3756 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3757 sc->sc_ival = mstohz(ival); 3758 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3759 sc->sc_intr_xfer = xfer; 3760 return USBD_IN_PROGRESS; 3761 } 3762 3763 /* Close the root interrupt pipe. */ 3764 void 3765 uhci_root_intr_close(struct usbd_pipe *pipe) 3766 { 3767 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3768 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3769 3770 KASSERT(mutex_owned(&sc->sc_lock)); 3771 3772 callout_stop(&sc->sc_poll_handle); 3773 sc->sc_intr_xfer = NULL; 3774 } 3775
Indexes created Tue Sep 30 20:09:53 GMT 2025