uhci.c revision 1.264.4.39
1 /* $NetBSD: uhci.c,v 1.264.4.39 2015/10/27 14:05:29 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.39 2015/10/27 14:05:29 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Isochronous pipe */ 158 struct isoc { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } isoc; 162 }; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static usbd_status uhci_run(uhci_softc_t *, int, int); 169 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 170 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, 180 uhci_soft_td_t *, uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 182 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 183 uhci_soft_td_t **, uhci_soft_td_t **); 184 Static void uhci_poll_hub(void *); 185 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 186 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *); 187 Static void uhci_idone(struct uhci_xfer *); 188 189 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 190 191 Static void uhci_timeout(void *); 192 Static void uhci_timeout_task(void *); 193 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 194 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 195 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 197 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 198 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_add_loop(uhci_softc_t *); 200 Static void uhci_rem_loop(uhci_softc_t *); 201 202 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 203 Static void uhci_device_isoc_enter(struct usbd_xfer *); 204 205 Static struct usbd_xfer * 206 uhci_allocx(struct usbd_bus *, unsigned int); 207 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 208 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 209 Static int uhci_roothub_ctrl(struct usbd_bus *, 210 usb_device_request_t *, void *, int); 211 212 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 213 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 214 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 215 Static void uhci_device_ctrl_close(struct usbd_pipe *); 216 Static void uhci_device_ctrl_done(struct usbd_xfer *); 217 218 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 220 Static void uhci_device_intr_abort(struct usbd_xfer *); 221 Static void uhci_device_intr_close(struct usbd_pipe *); 222 Static void uhci_device_intr_done(struct usbd_xfer *); 223 224 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 225 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 226 Static void uhci_device_bulk_abort(struct usbd_xfer *); 227 Static void uhci_device_bulk_close(struct usbd_pipe *); 228 Static void uhci_device_bulk_done(struct usbd_xfer *); 229 230 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 231 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 232 Static void uhci_device_isoc_abort(struct usbd_xfer *); 233 Static void uhci_device_isoc_close(struct usbd_pipe *); 234 Static void uhci_device_isoc_done(struct usbd_xfer *); 235 236 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 238 Static void uhci_root_intr_abort(struct usbd_xfer *); 239 Static void uhci_root_intr_close(struct usbd_pipe *); 240 Static void uhci_root_intr_done(struct usbd_xfer *); 241 242 Static usbd_status uhci_open(struct usbd_pipe *); 243 Static void uhci_poll(struct usbd_bus *); 244 Static void uhci_softintr(void *); 245 246 Static usbd_status uhci_device_request(struct usbd_xfer *); 247 248 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 250 Static usbd_status uhci_device_setintr(uhci_softc_t *, 251 struct uhci_pipe *, int); 252 253 Static void uhci_device_clear_toggle(struct usbd_pipe *); 254 Static void uhci_noop(struct usbd_pipe *); 255 256 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 257 uhci_soft_qh_t *); 258 259 #ifdef UHCI_DEBUG 260 Static void uhci_dump_all(uhci_softc_t *); 261 Static void uhci_dumpregs(uhci_softc_t *); 262 Static void uhci_dump_qhs(uhci_soft_qh_t *); 263 Static void uhci_dump_qh(uhci_soft_qh_t *); 264 Static void uhci_dump_tds(uhci_soft_td_t *); 265 Static void uhci_dump_td(uhci_soft_td_t *); 266 Static void uhci_dump_ii(uhci_intr_info_t *); 267 void uhci_dump(void); 268 #endif 269 270 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 271 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 272 #define UWRITE1(sc, r, x) \ 273 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 274 } while (/*CONSTCOND*/0) 275 #define UWRITE2(sc, r, x) \ 276 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 277 } while (/*CONSTCOND*/0) 278 #define UWRITE4(sc, r, x) \ 279 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 280 } while (/*CONSTCOND*/0) 281 static __inline uint8_t 282 UREAD1(uhci_softc_t *sc, bus_size_t r) 283 { 284 285 UBARR(sc); 286 return bus_space_read_1(sc->iot, sc->ioh, r); 287 } 288 289 static __inline uint16_t 290 UREAD2(uhci_softc_t *sc, bus_size_t r) 291 { 292 293 UBARR(sc); 294 return bus_space_read_2(sc->iot, sc->ioh, r); 295 } 296 297 #ifdef UHCI_DEBUG 298 static __inline uint32_t 299 UREAD4(uhci_softc_t *sc, bus_size_t r) 300 { 301 302 UBARR(sc); 303 return bus_space_read_4(sc->iot, sc->ioh, r); 304 } 305 #endif 306 307 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 308 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 309 310 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 311 312 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 313 314 const struct usbd_bus_methods uhci_bus_methods = { 315 .ubm_open = uhci_open, 316 .ubm_softint = uhci_softintr, 317 .ubm_dopoll = uhci_poll, 318 .ubm_allocx = uhci_allocx, 319 .ubm_freex = uhci_freex, 320 .ubm_getlock = uhci_get_lock, 321 .ubm_rhctrl = uhci_roothub_ctrl, 322 }; 323 324 const struct usbd_pipe_methods uhci_root_intr_methods = { 325 .upm_transfer = uhci_root_intr_transfer, 326 .upm_start = uhci_root_intr_start, 327 .upm_abort = uhci_root_intr_abort, 328 .upm_close = uhci_root_intr_close, 329 .upm_cleartoggle = uhci_noop, 330 .upm_done = uhci_root_intr_done, 331 }; 332 333 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 334 .upm_transfer = uhci_device_ctrl_transfer, 335 .upm_start = uhci_device_ctrl_start, 336 .upm_abort = uhci_device_ctrl_abort, 337 .upm_close = uhci_device_ctrl_close, 338 .upm_cleartoggle = uhci_noop, 339 .upm_done = uhci_device_ctrl_done, 340 }; 341 342 const struct usbd_pipe_methods uhci_device_intr_methods = { 343 .upm_transfer = uhci_device_intr_transfer, 344 .upm_start = uhci_device_intr_start, 345 .upm_abort = uhci_device_intr_abort, 346 .upm_close = uhci_device_intr_close, 347 .upm_cleartoggle = uhci_device_clear_toggle, 348 .upm_done = uhci_device_intr_done, 349 }; 350 351 const struct usbd_pipe_methods uhci_device_bulk_methods = { 352 .upm_transfer = uhci_device_bulk_transfer, 353 .upm_start = uhci_device_bulk_start, 354 .upm_abort = uhci_device_bulk_abort, 355 .upm_close = uhci_device_bulk_close, 356 .upm_cleartoggle = uhci_device_clear_toggle, 357 .upm_done = uhci_device_bulk_done, 358 }; 359 360 const struct usbd_pipe_methods uhci_device_isoc_methods = { 361 .upm_transfer = uhci_device_isoc_transfer, 362 .upm_start = uhci_device_isoc_start, 363 .upm_abort = uhci_device_isoc_abort, 364 .upm_close = uhci_device_isoc_close, 365 .upm_cleartoggle = uhci_noop, 366 .upm_done = uhci_device_isoc_done, 367 }; 368 369 #define uhci_add_intr_info(sc, ux) \ 370 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), list) 371 #define uhci_del_intr_info(sc, ux) \ 372 do { \ 373 TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), list); \ 374 (ux)->list.tqe_prev = NULL; \ 375 } while (0) 376 #define uhci_active_intr_info(ux) ((ux)->list.tqe_prev != NULL) 377 378 static inline uhci_soft_qh_t * 379 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 380 { 381 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 382 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 383 384 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 385 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 386 usb_syncmem(&pqh->dma, 387 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 388 sizeof(pqh->qh.qh_hlink), 389 BUS_DMASYNC_POSTWRITE); 390 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 391 printf("uhci_find_prev_qh: QH not found\n"); 392 return NULL; 393 } 394 #endif 395 } 396 return pqh; 397 } 398 399 void 400 uhci_globalreset(uhci_softc_t *sc) 401 { 402 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 403 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 404 UHCICMD(sc, 0); /* do nothing */ 405 } 406 407 int 408 uhci_init(uhci_softc_t *sc) 409 { 410 usbd_status err; 411 int i, j; 412 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 413 uhci_soft_td_t *std; 414 415 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 416 417 #ifdef UHCI_DEBUG 418 thesc = sc; 419 420 if (uhcidebug > 2) 421 uhci_dumpregs(sc); 422 #endif 423 424 sc->sc_suspend = PWR_RESUME; 425 426 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 427 uhci_globalreset(sc); /* reset the controller */ 428 uhci_reset(sc); 429 430 /* Allocate and initialize real frame array. */ 431 err = usb_allocmem(&sc->sc_bus, 432 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 433 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 434 if (err) 435 return err; 436 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 437 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 438 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 439 440 /* 441 * Allocate a TD, inactive, that hangs from the last QH. 442 * This is to avoid a bug in the PIIX that makes it run berserk 443 * otherwise. 444 */ 445 std = uhci_alloc_std(sc); 446 if (std == NULL) 447 return ENOMEM; 448 std->link.std = NULL; 449 std->td.td_link = htole32(UHCI_PTR_T); 450 std->td.td_status = htole32(0); /* inactive */ 451 std->td.td_token = htole32(0); 452 std->td.td_buffer = htole32(0); 453 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 455 456 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 457 lsqh = uhci_alloc_sqh(sc); 458 if (lsqh == NULL) 459 return ENOMEM; 460 lsqh->hlink = NULL; 461 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 462 lsqh->elink = std; 463 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 464 sc->sc_last_qh = lsqh; 465 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 467 468 /* Allocate the dummy QH where bulk traffic will be queued. */ 469 bsqh = uhci_alloc_sqh(sc); 470 if (bsqh == NULL) 471 return ENOMEM; 472 bsqh->hlink = lsqh; 473 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 474 bsqh->elink = NULL; 475 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 476 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 477 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 479 480 /* Allocate dummy QH where high speed control traffic will be queued. */ 481 chsqh = uhci_alloc_sqh(sc); 482 if (chsqh == NULL) 483 return ENOMEM; 484 chsqh->hlink = bsqh; 485 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 486 chsqh->elink = NULL; 487 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 488 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 489 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 490 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 491 492 /* Allocate dummy QH where control traffic will be queued. */ 493 clsqh = uhci_alloc_sqh(sc); 494 if (clsqh == NULL) 495 return ENOMEM; 496 clsqh->hlink = chsqh; 497 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 498 clsqh->elink = NULL; 499 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 500 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 501 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 504 /* 505 * Make all (virtual) frame list pointers point to the interrupt 506 * queue heads and the interrupt queue heads at the control 507 * queue head and point the physical frame list to the virtual. 508 */ 509 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 510 std = uhci_alloc_std(sc); 511 sqh = uhci_alloc_sqh(sc); 512 if (std == NULL || sqh == NULL) 513 return USBD_NOMEM; 514 std->link.sqh = sqh; 515 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 516 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 517 std->td.td_token = htole32(0); 518 std->td.td_buffer = htole32(0); 519 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 520 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 521 sqh->hlink = clsqh; 522 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 523 sqh->elink = NULL; 524 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 525 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 526 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 527 sc->sc_vframes[i].htd = std; 528 sc->sc_vframes[i].etd = std; 529 sc->sc_vframes[i].hqh = sqh; 530 sc->sc_vframes[i].eqh = sqh; 531 for (j = i; 532 j < UHCI_FRAMELIST_COUNT; 533 j += UHCI_VFRAMELIST_COUNT) 534 sc->sc_pframes[j] = htole32(std->physaddr); 535 } 536 usb_syncmem(&sc->sc_dma, 0, 537 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 538 BUS_DMASYNC_PREWRITE); 539 540 541 TAILQ_INIT(&sc->sc_intrhead); 542 543 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 544 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 545 546 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 547 548 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 549 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 550 cv_init(&sc->sc_softwake_cv, "uhciab"); 551 552 /* Set up the bus struct. */ 553 sc->sc_bus.ub_methods = &uhci_bus_methods; 554 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 555 sc->sc_bus.ub_usedma = true; 556 557 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 558 559 DPRINTF("Enabling...", 0, 0, 0, 0); 560 561 err = uhci_run(sc, 1, 0); /* and here we go... */ 562 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 563 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 564 return err; 565 } 566 567 int 568 uhci_activate(device_t self, enum devact act) 569 { 570 struct uhci_softc *sc = device_private(self); 571 572 switch (act) { 573 case DVACT_DEACTIVATE: 574 sc->sc_dying = 1; 575 return 0; 576 default: 577 return EOPNOTSUPP; 578 } 579 } 580 581 void 582 uhci_childdet(device_t self, device_t child) 583 { 584 struct uhci_softc *sc = device_private(self); 585 586 KASSERT(sc->sc_child == child); 587 sc->sc_child = NULL; 588 } 589 590 int 591 uhci_detach(struct uhci_softc *sc, int flags) 592 { 593 int rv = 0; 594 595 if (sc->sc_child != NULL) 596 rv = config_detach(sc->sc_child, flags); 597 598 if (rv != 0) 599 return rv; 600 601 callout_halt(&sc->sc_poll_handle, NULL); 602 callout_destroy(&sc->sc_poll_handle); 603 604 cv_destroy(&sc->sc_softwake_cv); 605 606 mutex_destroy(&sc->sc_lock); 607 mutex_destroy(&sc->sc_intr_lock); 608 609 pool_cache_destroy(sc->sc_xferpool); 610 611 /* XXX free other data structures XXX */ 612 613 return rv; 614 } 615 616 struct usbd_xfer * 617 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 618 { 619 struct uhci_softc *sc = UHCI_BUS2SC(bus); 620 struct usbd_xfer *xfer; 621 622 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 623 if (xfer != NULL) { 624 memset(xfer, 0, sizeof(struct uhci_xfer)); 625 626 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 627 #ifdef DIAGNOSTIC 628 uxfer->isdone = true; 629 xfer->ux_state = XFER_BUSY; 630 #endif 631 } 632 return xfer; 633 } 634 635 void 636 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 637 { 638 struct uhci_softc *sc = UHCI_BUS2SC(bus); 639 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 640 641 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 642 xfer->ux_state); 643 KASSERTMSG(uxfer->isdone, "xfer %p not done\n", xfer); 644 #ifdef DIAGNOSTIC 645 xfer->ux_state = XFER_FREE; 646 #endif 647 pool_cache_put(sc->sc_xferpool, xfer); 648 } 649 650 Static void 651 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 652 { 653 struct uhci_softc *sc = UHCI_BUS2SC(bus); 654 655 *lock = &sc->sc_lock; 656 } 657 658 659 /* 660 * Handle suspend/resume. 661 * 662 * We need to switch to polling mode here, because this routine is 663 * called from an interrupt context. This is all right since we 664 * are almost suspended anyway. 665 */ 666 bool 667 uhci_resume(device_t dv, const pmf_qual_t *qual) 668 { 669 uhci_softc_t *sc = device_private(dv); 670 int cmd; 671 672 mutex_spin_enter(&sc->sc_intr_lock); 673 674 cmd = UREAD2(sc, UHCI_CMD); 675 sc->sc_bus.ub_usepolling++; 676 UWRITE2(sc, UHCI_INTR, 0); 677 uhci_globalreset(sc); 678 uhci_reset(sc); 679 if (cmd & UHCI_CMD_RS) 680 uhci_run(sc, 0, 1); 681 682 /* restore saved state */ 683 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 684 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 685 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 686 687 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 688 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 689 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 690 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 691 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 692 UHCICMD(sc, UHCI_CMD_MAXP); 693 uhci_run(sc, 1, 1); /* and start traffic again */ 694 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 695 sc->sc_bus.ub_usepolling--; 696 if (sc->sc_intr_xfer != NULL) 697 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 698 sc->sc_intr_xfer); 699 #ifdef UHCI_DEBUG 700 if (uhcidebug > 2) 701 uhci_dumpregs(sc); 702 #endif 703 704 sc->sc_suspend = PWR_RESUME; 705 mutex_spin_exit(&sc->sc_intr_lock); 706 707 return true; 708 } 709 710 bool 711 uhci_suspend(device_t dv, const pmf_qual_t *qual) 712 { 713 uhci_softc_t *sc = device_private(dv); 714 int cmd; 715 716 mutex_spin_enter(&sc->sc_intr_lock); 717 718 cmd = UREAD2(sc, UHCI_CMD); 719 720 #ifdef UHCI_DEBUG 721 if (uhcidebug > 2) 722 uhci_dumpregs(sc); 723 #endif 724 if (sc->sc_intr_xfer != NULL) 725 callout_stop(&sc->sc_poll_handle); 726 sc->sc_suspend = PWR_SUSPEND; 727 sc->sc_bus.ub_usepolling++; 728 729 uhci_run(sc, 0, 1); /* stop the controller */ 730 cmd &= ~UHCI_CMD_RS; 731 732 /* save some state if BIOS doesn't */ 733 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 734 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 735 736 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 737 738 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 739 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 740 sc->sc_bus.ub_usepolling--; 741 742 mutex_spin_exit(&sc->sc_intr_lock); 743 744 return true; 745 } 746 747 #ifdef UHCI_DEBUG 748 Static void 749 uhci_dumpregs(uhci_softc_t *sc) 750 { 751 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 752 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 753 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 754 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 755 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 756 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 757 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 758 } 759 760 void 761 uhci_dump_td(uhci_soft_td_t *p) 762 { 763 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 764 765 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 766 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 767 768 DPRINTF("TD(%p) at %08x", p, p->physaddr, 0, 0); 769 DPRINTF(" link=0x%08x status=0x%08x " 770 "token=0x%08x buffer=0x%08x", 771 le32toh(p->td.td_link), 772 le32toh(p->td.td_status), 773 le32toh(p->td.td_token), 774 le32toh(p->td.td_buffer)); 775 776 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 777 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 778 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 779 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 780 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 781 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 782 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 783 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 784 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 785 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 786 DPRINTF("ios =%d ls =%d spd =%d", 787 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 788 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 789 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 790 DPRINTF("errcnt =%d actlen =%d pid=%02x", 791 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 792 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 793 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 794 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 795 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 796 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 797 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 798 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 799 } 800 801 void 802 uhci_dump_qh(uhci_soft_qh_t *sqh) 803 { 804 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 805 806 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 807 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 808 809 DPRINTF("QH(%p) at %08x: hlink=%08x elink=%08x", sqh, 810 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 811 le32toh(sqh->qh.qh_elink)); 812 813 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 814 } 815 816 817 #if 1 818 void 819 uhci_dump(void) 820 { 821 uhci_dump_all(thesc); 822 } 823 #endif 824 825 void 826 uhci_dump_all(uhci_softc_t *sc) 827 { 828 uhci_dumpregs(sc); 829 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 830 uhci_dump_qhs(sc->sc_lctl_start); 831 } 832 833 834 void 835 uhci_dump_qhs(uhci_soft_qh_t *sqh) 836 { 837 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 838 839 uhci_dump_qh(sqh); 840 841 /* 842 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 843 * Traverses sideways first, then down. 844 * 845 * QH1 846 * QH2 847 * No QH 848 * TD2.1 849 * TD2.2 850 * TD1.1 851 * etc. 852 * 853 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 854 */ 855 856 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 857 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 858 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 859 uhci_dump_qhs(sqh->hlink); 860 else 861 DPRINTF("No QH", 0, 0, 0, 0); 862 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 863 864 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 865 uhci_dump_tds(sqh->elink); 866 else 867 DPRINTF("No QH", 0, 0, 0, 0); 868 } 869 870 void 871 uhci_dump_tds(uhci_soft_td_t *std) 872 { 873 uhci_soft_td_t *td; 874 int stop; 875 876 for (td = std; td != NULL; td = td->link.std) { 877 uhci_dump_td(td); 878 879 /* 880 * Check whether the link pointer in this TD marks 881 * the link pointer as end of queue. This avoids 882 * printing the free list in case the queue/TD has 883 * already been moved there (seatbelt). 884 */ 885 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 886 sizeof(td->td.td_link), 887 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 888 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 889 le32toh(td->td.td_link) == 0); 890 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 891 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 892 if (stop) 893 break; 894 } 895 } 896 897 Static void 898 uhci_dump_ii(uhci_intr_info_t *ux) 899 { 900 struct usbd_pipe *pipe; 901 usb_endpoint_descriptor_t *ed; 902 struct usbd_device *dev; 903 904 if (ux == NULL) { 905 printf("ux NULL\n"); 906 return; 907 } 908 if (ux->xfer == NULL) { 909 printf("ux %p: done=%d xfer=NULL\n", 910 ux, ux->isdone); 911 return; 912 } 913 pipe = ux->xfer->ux_pipe; 914 if (pipe == NULL) { 915 printf("ux %p: done=%d xfer=%p pipe=NULL\n", 916 ux, ux->isdone, ux->xfer); 917 return; 918 } 919 if (pipe->up_endpoint == NULL) { 920 printf("ux %p: done=%d xfer=%p pipe=%p pipe->up_endpoint=NULL\n", 921 ux, ux->isdone, ux->xfer, pipe); 922 return; 923 } 924 if (pipe->up_dev == NULL) { 925 printf("ux %p: done=%d xfer=%p pipe=%p pipe->up_dev=NULL\n", 926 ux, ux->isdone, ux->xfer, pipe); 927 return; 928 } 929 ed = pipe->up_endpoint->ue_edesc; 930 dev = pipe->up_dev; 931 printf("ux %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 932 ux, ux->isdone, ux->xfer, dev, 933 UGETW(dev->ud_ddesc.idVendor), 934 UGETW(dev->ud_ddesc.idProduct), 935 dev->ud_addr, pipe, 936 ed->bEndpointAddress, ed->bmAttributes); 937 } 938 939 void uhci_dump_iis(struct uhci_softc *sc); 940 void 941 uhci_dump_iis(struct uhci_softc *sc) 942 { 943 uhci_intr_info_t *ii; 944 945 printf("interrupt list:\n"); 946 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = TAILQ_NEXT(ux, list)) 947 uhci_dump_ii(ux); 948 } 949 950 void iidump(void); 951 void iidump(void) { uhci_dump_iis(thesc); } 952 953 #endif 954 955 /* 956 * This routine is executed periodically and simulates interrupts 957 * from the root controller interrupt pipe for port status change. 958 */ 959 void 960 uhci_poll_hub(void *addr) 961 { 962 struct usbd_xfer *xfer = addr; 963 struct usbd_pipe *pipe = xfer->ux_pipe; 964 uhci_softc_t *sc; 965 u_char *p; 966 967 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 968 969 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 970 return; /* device has detached */ 971 sc = UHCI_PIPE2SC(pipe); 972 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 973 974 p = xfer->ux_buf; 975 p[0] = 0; 976 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 977 p[0] |= 1<<1; 978 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 979 p[0] |= 1<<2; 980 if (p[0] == 0) 981 /* No change, try again in a while */ 982 return; 983 984 xfer->ux_actlen = 1; 985 xfer->ux_status = USBD_NORMAL_COMPLETION; 986 mutex_enter(&sc->sc_lock); 987 usb_transfer_complete(xfer); 988 mutex_exit(&sc->sc_lock); 989 } 990 991 void 992 uhci_root_intr_done(struct usbd_xfer *xfer) 993 { 994 } 995 996 /* 997 * Let the last QH loop back to the high speed control transfer QH. 998 * This is what intel calls "bandwidth reclamation" and improves 999 * USB performance a lot for some devices. 1000 * If we are already looping, just count it. 1001 */ 1002 void 1003 uhci_add_loop(uhci_softc_t *sc) 1004 { 1005 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1006 1007 #ifdef UHCI_DEBUG 1008 if (uhcinoloop) 1009 return; 1010 #endif 1011 if (++sc->sc_loops == 1) { 1012 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1013 /* Note, we don't loop back the soft pointer. */ 1014 sc->sc_last_qh->qh.qh_hlink = 1015 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1016 usb_syncmem(&sc->sc_last_qh->dma, 1017 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1018 sizeof(sc->sc_last_qh->qh.qh_hlink), 1019 BUS_DMASYNC_PREWRITE); 1020 } 1021 } 1022 1023 void 1024 uhci_rem_loop(uhci_softc_t *sc) 1025 { 1026 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1027 1028 #ifdef UHCI_DEBUG 1029 if (uhcinoloop) 1030 return; 1031 #endif 1032 if (--sc->sc_loops == 0) { 1033 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1034 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1035 usb_syncmem(&sc->sc_last_qh->dma, 1036 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1037 sizeof(sc->sc_last_qh->qh.qh_hlink), 1038 BUS_DMASYNC_PREWRITE); 1039 } 1040 } 1041 1042 /* Add high speed control QH, called with lock held. */ 1043 void 1044 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1045 { 1046 uhci_soft_qh_t *eqh; 1047 1048 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1049 1050 KASSERT(mutex_owned(&sc->sc_lock)); 1051 1052 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1053 eqh = sc->sc_hctl_end; 1054 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1055 sizeof(eqh->qh.qh_hlink), 1056 BUS_DMASYNC_POSTWRITE); 1057 sqh->hlink = eqh->hlink; 1058 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1059 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1060 BUS_DMASYNC_PREWRITE); 1061 eqh->hlink = sqh; 1062 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1063 sc->sc_hctl_end = sqh; 1064 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1065 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1066 #ifdef UHCI_CTL_LOOP 1067 uhci_add_loop(sc); 1068 #endif 1069 } 1070 1071 /* Remove high speed control QH, called with lock held. */ 1072 void 1073 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1074 { 1075 uhci_soft_qh_t *pqh; 1076 uint32_t elink; 1077 1078 KASSERT(mutex_owned(&sc->sc_lock)); 1079 1080 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1081 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1082 #ifdef UHCI_CTL_LOOP 1083 uhci_rem_loop(sc); 1084 #endif 1085 /* 1086 * The T bit should be set in the elink of the QH so that the HC 1087 * doesn't follow the pointer. This condition may fail if the 1088 * the transferred packet was short so that the QH still points 1089 * at the last used TD. 1090 * In this case we set the T bit and wait a little for the HC 1091 * to stop looking at the TD. 1092 * Note that if the TD chain is large enough, the controller 1093 * may still be looking at the chain at the end of this function. 1094 * uhci_free_std_chain() will make sure the controller stops 1095 * looking at it quickly, but until then we should not change 1096 * sqh->hlink. 1097 */ 1098 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1099 sizeof(sqh->qh.qh_elink), 1100 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1101 elink = le32toh(sqh->qh.qh_elink); 1102 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1103 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1104 if (!(elink & UHCI_PTR_T)) { 1105 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1106 usb_syncmem(&sqh->dma, 1107 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1108 sizeof(sqh->qh.qh_elink), 1109 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1110 delay(UHCI_QH_REMOVE_DELAY); 1111 } 1112 1113 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1114 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1115 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1116 pqh->hlink = sqh->hlink; 1117 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1118 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1119 sizeof(pqh->qh.qh_hlink), 1120 BUS_DMASYNC_PREWRITE); 1121 delay(UHCI_QH_REMOVE_DELAY); 1122 if (sc->sc_hctl_end == sqh) 1123 sc->sc_hctl_end = pqh; 1124 } 1125 1126 /* Add low speed control QH, called with lock held. */ 1127 void 1128 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1129 { 1130 uhci_soft_qh_t *eqh; 1131 1132 KASSERT(mutex_owned(&sc->sc_lock)); 1133 1134 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1135 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1136 1137 eqh = sc->sc_lctl_end; 1138 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1139 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1140 sqh->hlink = eqh->hlink; 1141 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1142 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1143 BUS_DMASYNC_PREWRITE); 1144 eqh->hlink = sqh; 1145 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1146 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1147 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1148 sc->sc_lctl_end = sqh; 1149 } 1150 1151 /* Remove low speed control QH, called with lock held. */ 1152 void 1153 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1154 { 1155 uhci_soft_qh_t *pqh; 1156 uint32_t elink; 1157 1158 KASSERT(mutex_owned(&sc->sc_lock)); 1159 1160 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1161 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1162 1163 /* See comment in uhci_remove_hs_ctrl() */ 1164 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1165 sizeof(sqh->qh.qh_elink), 1166 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1167 elink = le32toh(sqh->qh.qh_elink); 1168 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1169 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1170 if (!(elink & UHCI_PTR_T)) { 1171 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1172 usb_syncmem(&sqh->dma, 1173 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1174 sizeof(sqh->qh.qh_elink), 1175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1176 delay(UHCI_QH_REMOVE_DELAY); 1177 } 1178 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1179 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1180 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1181 pqh->hlink = sqh->hlink; 1182 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1183 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1184 sizeof(pqh->qh.qh_hlink), 1185 BUS_DMASYNC_PREWRITE); 1186 delay(UHCI_QH_REMOVE_DELAY); 1187 if (sc->sc_lctl_end == sqh) 1188 sc->sc_lctl_end = pqh; 1189 } 1190 1191 /* Add bulk QH, called with lock held. */ 1192 void 1193 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1194 { 1195 uhci_soft_qh_t *eqh; 1196 1197 KASSERT(mutex_owned(&sc->sc_lock)); 1198 1199 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1200 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1201 1202 eqh = sc->sc_bulk_end; 1203 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1204 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1205 sqh->hlink = eqh->hlink; 1206 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1207 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1208 BUS_DMASYNC_PREWRITE); 1209 eqh->hlink = sqh; 1210 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1211 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1212 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1213 sc->sc_bulk_end = sqh; 1214 uhci_add_loop(sc); 1215 } 1216 1217 /* Remove bulk QH, called with lock held. */ 1218 void 1219 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1220 { 1221 uhci_soft_qh_t *pqh; 1222 1223 KASSERT(mutex_owned(&sc->sc_lock)); 1224 1225 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1226 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1227 1228 uhci_rem_loop(sc); 1229 /* See comment in uhci_remove_hs_ctrl() */ 1230 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1231 sizeof(sqh->qh.qh_elink), 1232 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1233 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1234 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1235 usb_syncmem(&sqh->dma, 1236 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1237 sizeof(sqh->qh.qh_elink), 1238 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1239 delay(UHCI_QH_REMOVE_DELAY); 1240 } 1241 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1242 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1243 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1244 pqh->hlink = sqh->hlink; 1245 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1246 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1247 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1248 delay(UHCI_QH_REMOVE_DELAY); 1249 if (sc->sc_bulk_end == sqh) 1250 sc->sc_bulk_end = pqh; 1251 } 1252 1253 Static int uhci_intr1(uhci_softc_t *); 1254 1255 int 1256 uhci_intr(void *arg) 1257 { 1258 uhci_softc_t *sc = arg; 1259 int ret = 0; 1260 1261 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1262 1263 mutex_spin_enter(&sc->sc_intr_lock); 1264 1265 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1266 goto done; 1267 1268 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1269 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1270 goto done; 1271 } 1272 1273 ret = uhci_intr1(sc); 1274 1275 done: 1276 mutex_spin_exit(&sc->sc_intr_lock); 1277 return ret; 1278 } 1279 1280 int 1281 uhci_intr1(uhci_softc_t *sc) 1282 { 1283 int status; 1284 int ack; 1285 1286 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1287 1288 #ifdef UHCI_DEBUG 1289 if (uhcidebug > 15) { 1290 DPRINTF("sc %p", sc, 0, 0, 0); 1291 uhci_dumpregs(sc); 1292 } 1293 #endif 1294 1295 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1296 1297 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1298 if (status == 0) /* The interrupt was not for us. */ 1299 return 0; 1300 1301 if (sc->sc_suspend != PWR_RESUME) { 1302 #ifdef DIAGNOSTIC 1303 printf("%s: interrupt while not operating ignored\n", 1304 device_xname(sc->sc_dev)); 1305 #endif 1306 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1307 return 0; 1308 } 1309 1310 ack = 0; 1311 if (status & UHCI_STS_USBINT) 1312 ack |= UHCI_STS_USBINT; 1313 if (status & UHCI_STS_USBEI) 1314 ack |= UHCI_STS_USBEI; 1315 if (status & UHCI_STS_RD) { 1316 ack |= UHCI_STS_RD; 1317 #ifdef UHCI_DEBUG 1318 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1319 #endif 1320 } 1321 if (status & UHCI_STS_HSE) { 1322 ack |= UHCI_STS_HSE; 1323 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1324 } 1325 if (status & UHCI_STS_HCPE) { 1326 ack |= UHCI_STS_HCPE; 1327 printf("%s: host controller process error\n", 1328 device_xname(sc->sc_dev)); 1329 } 1330 1331 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1332 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1333 /* no acknowledge needed */ 1334 if (!sc->sc_dying) { 1335 printf("%s: host controller halted\n", 1336 device_xname(sc->sc_dev)); 1337 #ifdef UHCI_DEBUG 1338 uhci_dump_all(sc); 1339 #endif 1340 } 1341 sc->sc_dying = 1; 1342 } 1343 1344 if (!ack) 1345 return 0; /* nothing to acknowledge */ 1346 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1347 1348 usb_schedsoftintr(&sc->sc_bus); 1349 1350 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1351 1352 return 1; 1353 } 1354 1355 void 1356 uhci_softintr(void *v) 1357 { 1358 struct usbd_bus *bus = v; 1359 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1360 struct uhci_xfer *ux, *nextux; 1361 1362 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1363 DPRINTF("sc %p", sc, 0, 0, 0); 1364 1365 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1366 1367 /* 1368 * Interrupts on UHCI really suck. When the host controller 1369 * interrupts because a transfer is completed there is no 1370 * way of knowing which transfer it was. You can scan down 1371 * the TDs and QHs of the previous frame to limit the search, 1372 * but that assumes that the interrupt was not delayed by more 1373 * than 1 ms, which may not always be true (e.g. after debug 1374 * output on a slow console). 1375 * We scan all interrupt descriptors to see if any have 1376 * completed. 1377 */ 1378 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) { 1379 nextux = TAILQ_NEXT(ux, list); 1380 uhci_check_intr(sc, ux); 1381 } 1382 1383 if (sc->sc_softwake) { 1384 sc->sc_softwake = 0; 1385 cv_broadcast(&sc->sc_softwake_cv); 1386 } 1387 } 1388 1389 /* Check for an interrupt. */ 1390 void 1391 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux) 1392 { 1393 uhci_soft_td_t *std, *lstd; 1394 uint32_t status; 1395 1396 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1397 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1398 1399 KASSERT(ux != NULL); 1400 1401 struct usbd_xfer *xfer = &ux->xfer; 1402 if (xfer->ux_status == USBD_CANCELLED || 1403 xfer->ux_status == USBD_TIMEOUT) { 1404 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1405 return; 1406 } 1407 1408 if (ux->stdstart == NULL) 1409 return; 1410 lstd = ux->stdend; 1411 1412 KASSERT(lstd != NULL); 1413 1414 usb_syncmem(&lstd->dma, 1415 lstd->offs + offsetof(uhci_td_t, td_status), 1416 sizeof(lstd->td.td_status), 1417 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1418 status = le32toh(lstd->td.td_status); 1419 usb_syncmem(&lstd->dma, 1420 lstd->offs + offsetof(uhci_td_t, td_status), 1421 sizeof(lstd->td.td_status), 1422 BUS_DMASYNC_PREREAD); 1423 1424 /* If the last TD is not marked active we can complete */ 1425 if (!(status & UHCI_TD_ACTIVE)) { 1426 done: 1427 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1428 1429 callout_stop(&xfer->ux_callout); 1430 uhci_idone(ux); 1431 return; 1432 } 1433 1434 /* 1435 * If the last TD is still active we need to check whether there 1436 * is an error somewhere in the middle, or whether there was a 1437 * short packet (SPD and not ACTIVE). 1438 */ 1439 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1440 for (std = ux->stdstart; std != lstd; std = std->link.std) { 1441 usb_syncmem(&std->dma, 1442 std->offs + offsetof(uhci_td_t, td_status), 1443 sizeof(std->td.td_status), 1444 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1445 status = le32toh(std->td.td_status); 1446 usb_syncmem(&std->dma, 1447 std->offs + offsetof(uhci_td_t, td_status), 1448 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1449 1450 /* If there's an active TD the xfer isn't done. */ 1451 if (status & UHCI_TD_ACTIVE) { 1452 DPRINTFN(12, "ux=%p std=%p still active", 1453 ux, std, 0, 0); 1454 return; 1455 } 1456 1457 /* Any kind of error makes the xfer done. */ 1458 if (status & UHCI_TD_STALLED) 1459 goto done; 1460 1461 /* 1462 * If the data phase of a control transfer is short, we need 1463 * to complete the status stage 1464 */ 1465 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1466 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1467 1468 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1469 struct uhci_pipe *upipe = 1470 (struct uhci_pipe *)xfer->ux_pipe; 1471 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1472 uhci_soft_td_t *stat = upipe->ctrl.stat; 1473 1474 DPRINTFN(12, "ux=%p std=%p control status" 1475 "phase needs completion", ux, ux->stdstart, 0, 0); 1476 1477 sqh->qh.qh_elink = 1478 htole32(stat->physaddr | UHCI_PTR_TD); 1479 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1480 BUS_DMASYNC_PREWRITE); 1481 break; 1482 } 1483 1484 /* We want short packets, and it is short: it's done */ 1485 usb_syncmem(&std->dma, 1486 std->offs + offsetof(uhci_td_t, td_token), 1487 sizeof(std->td.td_token), 1488 BUS_DMASYNC_POSTWRITE); 1489 1490 if ((status & UHCI_TD_SPD) && 1491 UHCI_TD_GET_ACTLEN(status) < 1492 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1493 goto done; 1494 } 1495 } 1496 } 1497 1498 /* Called with USB lock held. */ 1499 void 1500 uhci_idone(struct uhci_xfer *ux) 1501 { 1502 struct usbd_xfer *xfer = &ux->xfer; 1503 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1504 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1505 uhci_soft_td_t *std; 1506 uint32_t status = 0, nstatus; 1507 int actlen; 1508 1509 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1510 1511 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1512 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1513 1514 #ifdef DIAGNOSTIC 1515 #ifdef UHCI_DEBUG 1516 if (ux->isdone) { 1517 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1518 uhci_dump_ii(ux); 1519 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1520 } 1521 #endif 1522 KASSERT(!ux->isdone); 1523 ux->isdone = true; 1524 #endif 1525 1526 if (xfer->ux_nframes != 0) { 1527 /* Isoc transfer, do things differently. */ 1528 uhci_soft_td_t **stds = upipe->isoc.stds; 1529 int i, n, nframes, len; 1530 1531 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1532 1533 nframes = xfer->ux_nframes; 1534 actlen = 0; 1535 n = UHCI_XFER2UXFER(xfer)->curframe; 1536 for (i = 0; i < nframes; i++) { 1537 std = stds[n]; 1538 #ifdef UHCI_DEBUG 1539 if (uhcidebug > 5) { 1540 DPRINTF("isoc TD %d", i, 0, 0, 0); 1541 uhci_dump_td(std); 1542 } 1543 #endif 1544 if (++n >= UHCI_VFRAMELIST_COUNT) 1545 n = 0; 1546 usb_syncmem(&std->dma, 1547 std->offs + offsetof(uhci_td_t, td_status), 1548 sizeof(std->td.td_status), 1549 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1550 status = le32toh(std->td.td_status); 1551 len = UHCI_TD_GET_ACTLEN(status); 1552 xfer->ux_frlengths[i] = len; 1553 actlen += len; 1554 } 1555 upipe->isoc.inuse -= nframes; 1556 xfer->ux_actlen = actlen; 1557 xfer->ux_status = USBD_NORMAL_COMPLETION; 1558 goto end; 1559 } 1560 1561 #ifdef UHCI_DEBUG 1562 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", 1563 ux, xfer, upipe, 0); 1564 if (uhcidebug > 10) 1565 uhci_dump_tds(ux->stdstart); 1566 #endif 1567 1568 /* The transfer is done, compute actual length and status. */ 1569 actlen = 0; 1570 for (std = ux->stdstart; std != NULL; std = std->link.std) { 1571 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1572 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1573 nstatus = le32toh(std->td.td_status); 1574 if (nstatus & UHCI_TD_ACTIVE) 1575 break; 1576 1577 status = nstatus; 1578 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1579 UHCI_TD_PID_SETUP) 1580 actlen += UHCI_TD_GET_ACTLEN(status); 1581 else { 1582 /* 1583 * UHCI will report CRCTO in addition to a STALL or NAK 1584 * for a SETUP transaction. See section 3.2.2, "TD 1585 * CONTROL AND STATUS". 1586 */ 1587 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1588 status &= ~UHCI_TD_CRCTO; 1589 } 1590 } 1591 /* If there are left over TDs we need to update the toggle. */ 1592 if (std != NULL) 1593 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1594 1595 status &= UHCI_TD_ERROR; 1596 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1597 xfer->ux_actlen = actlen; 1598 if (status != 0) { 1599 1600 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1601 "error, addr=%d, endpt=0x%02x", 1602 xfer->ux_pipe->up_dev->ud_addr, 1603 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1604 0, 0); 1605 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1606 "bitstuff=%d crcto =%d nak =%d babble =%d", 1607 status & UHCI_TD_BITSTUFF, 1608 status & UHCI_TD_CRCTO, 1609 status & UHCI_TD_NAK, 1610 status & UHCI_TD_BABBLE); 1611 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1612 "dbuffer =%d stalled =%d active =%d", 1613 status & UHCI_TD_DBUFFER, 1614 status & UHCI_TD_STALLED, 1615 status & UHCI_TD_ACTIVE, 1616 0); 1617 1618 if (status == UHCI_TD_STALLED) 1619 xfer->ux_status = USBD_STALLED; 1620 else 1621 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1622 } else { 1623 xfer->ux_status = USBD_NORMAL_COMPLETION; 1624 } 1625 1626 end: 1627 usb_transfer_complete(xfer); 1628 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1629 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1630 } 1631 1632 /* 1633 * Called when a request does not complete. 1634 */ 1635 void 1636 uhci_timeout(void *addr) 1637 { 1638 struct usbd_xfer *xfer = addr; 1639 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1640 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1641 1642 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1643 1644 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1645 1646 if (sc->sc_dying) { 1647 mutex_enter(&sc->sc_lock); 1648 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1649 mutex_exit(&sc->sc_lock); 1650 return; 1651 } 1652 1653 /* Execute the abort in a process context. */ 1654 usb_init_task(&uxfer->abort_task, uhci_timeout_task, xfer, 1655 USB_TASKQ_MPSAFE); 1656 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1657 USB_TASKQ_HC); 1658 } 1659 1660 void 1661 uhci_timeout_task(void *addr) 1662 { 1663 struct usbd_xfer *xfer = addr; 1664 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1665 1666 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1667 1668 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1669 1670 mutex_enter(&sc->sc_lock); 1671 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1672 mutex_exit(&sc->sc_lock); 1673 } 1674 1675 /* 1676 * Wait here until controller claims to have an interrupt. 1677 * Then call uhci_intr and return. Use timeout to avoid waiting 1678 * too long. 1679 * Only used during boot when interrupts are not enabled yet. 1680 */ 1681 void 1682 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1683 { 1684 int timo = xfer->ux_timeout; 1685 struct uhci_xfer *ux; 1686 1687 mutex_enter(&sc->sc_lock); 1688 1689 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1690 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1691 1692 xfer->ux_status = USBD_IN_PROGRESS; 1693 for (; timo >= 0; timo--) { 1694 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1695 DPRINTFN(20, "0x%04x", 1696 UREAD2(sc, UHCI_STS), 0, 0, 0); 1697 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1698 mutex_spin_enter(&sc->sc_intr_lock); 1699 uhci_intr1(sc); 1700 mutex_spin_exit(&sc->sc_intr_lock); 1701 if (xfer->ux_status != USBD_IN_PROGRESS) 1702 goto done; 1703 } 1704 } 1705 1706 /* Timeout */ 1707 DPRINTF("timeout", 0, 0, 0, 0); 1708 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux != NULL; 1709 ux = TAILQ_NEXT(ux, list)) 1710 if (&ux->xfer == xfer) 1711 break; 1712 1713 KASSERT(ux != NULL); 1714 1715 uhci_idone(ux); 1716 1717 done: 1718 mutex_exit(&sc->sc_lock); 1719 } 1720 1721 void 1722 uhci_poll(struct usbd_bus *bus) 1723 { 1724 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1725 1726 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1727 mutex_spin_enter(&sc->sc_intr_lock); 1728 uhci_intr1(sc); 1729 mutex_spin_exit(&sc->sc_intr_lock); 1730 } 1731 } 1732 1733 void 1734 uhci_reset(uhci_softc_t *sc) 1735 { 1736 int n; 1737 1738 UHCICMD(sc, UHCI_CMD_HCRESET); 1739 /* The reset bit goes low when the controller is done. */ 1740 for (n = 0; n < UHCI_RESET_TIMEOUT && 1741 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1742 usb_delay_ms(&sc->sc_bus, 1); 1743 if (n >= UHCI_RESET_TIMEOUT) 1744 printf("%s: controller did not reset\n", 1745 device_xname(sc->sc_dev)); 1746 } 1747 1748 usbd_status 1749 uhci_run(uhci_softc_t *sc, int run, int locked) 1750 { 1751 int n, running; 1752 uint16_t cmd; 1753 1754 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1755 1756 run = run != 0; 1757 if (!locked) 1758 mutex_spin_enter(&sc->sc_intr_lock); 1759 1760 DPRINTF("setting run=%d", run, 0, 0, 0); 1761 cmd = UREAD2(sc, UHCI_CMD); 1762 if (run) 1763 cmd |= UHCI_CMD_RS; 1764 else 1765 cmd &= ~UHCI_CMD_RS; 1766 UHCICMD(sc, cmd); 1767 for(n = 0; n < 10; n++) { 1768 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1769 /* return when we've entered the state we want */ 1770 if (run == running) { 1771 if (!locked) 1772 mutex_spin_exit(&sc->sc_intr_lock); 1773 DPRINTF("done cmd=0x%x sts=0x%x", 1774 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1775 return USBD_NORMAL_COMPLETION; 1776 } 1777 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1778 } 1779 if (!locked) 1780 mutex_spin_exit(&sc->sc_intr_lock); 1781 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1782 run ? "start" : "stop"); 1783 return USBD_IOERROR; 1784 } 1785 1786 /* 1787 * Memory management routines. 1788 * uhci_alloc_std allocates TDs 1789 * uhci_alloc_sqh allocates QHs 1790 * These two routines do their own free list management, 1791 * partly for speed, partly because allocating DMAable memory 1792 * has page size granularity so much memory would be wasted if 1793 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1794 */ 1795 1796 uhci_soft_td_t * 1797 uhci_alloc_std(uhci_softc_t *sc) 1798 { 1799 uhci_soft_td_t *std; 1800 usbd_status err; 1801 int i, offs; 1802 usb_dma_t dma; 1803 1804 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1805 1806 if (sc->sc_freetds == NULL) { 1807 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1808 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1809 UHCI_TD_ALIGN, &dma); 1810 if (err) 1811 return 0; 1812 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1813 offs = i * UHCI_STD_SIZE; 1814 std = KERNADDR(&dma, offs); 1815 std->physaddr = DMAADDR(&dma, offs); 1816 std->dma = dma; 1817 std->offs = offs; 1818 std->link.std = sc->sc_freetds; 1819 sc->sc_freetds = std; 1820 } 1821 } 1822 std = sc->sc_freetds; 1823 sc->sc_freetds = std->link.std; 1824 memset(&std->td, 0, sizeof(uhci_td_t)); 1825 return std; 1826 } 1827 1828 void 1829 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1830 { 1831 #ifdef DIAGNOSTIC 1832 #define TD_IS_FREE 0x12345678 1833 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1834 printf("uhci_free_std: freeing free TD %p\n", std); 1835 return; 1836 } 1837 std->td.td_token = htole32(TD_IS_FREE); 1838 #endif 1839 std->link.std = sc->sc_freetds; 1840 sc->sc_freetds = std; 1841 } 1842 1843 uhci_soft_qh_t * 1844 uhci_alloc_sqh(uhci_softc_t *sc) 1845 { 1846 uhci_soft_qh_t *sqh; 1847 usbd_status err; 1848 int i, offs; 1849 usb_dma_t dma; 1850 1851 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1852 1853 if (sc->sc_freeqhs == NULL) { 1854 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1855 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1856 UHCI_QH_ALIGN, &dma); 1857 if (err) 1858 return 0; 1859 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1860 offs = i * UHCI_SQH_SIZE; 1861 sqh = KERNADDR(&dma, offs); 1862 sqh->physaddr = DMAADDR(&dma, offs); 1863 sqh->dma = dma; 1864 sqh->offs = offs; 1865 sqh->hlink = sc->sc_freeqhs; 1866 sc->sc_freeqhs = sqh; 1867 } 1868 } 1869 sqh = sc->sc_freeqhs; 1870 sc->sc_freeqhs = sqh->hlink; 1871 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1872 return sqh; 1873 } 1874 1875 void 1876 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1877 { 1878 sqh->hlink = sc->sc_freeqhs; 1879 sc->sc_freeqhs = sqh; 1880 } 1881 1882 void 1883 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1884 uhci_soft_td_t *stdend) 1885 { 1886 uhci_soft_td_t *p; 1887 uint32_t td_link; 1888 1889 /* 1890 * to avoid race condition with the controller which may be looking 1891 * at this chain, we need to first invalidate all links, and 1892 * then wait for the controller to move to another queue 1893 */ 1894 for (p = std; p != stdend; p = p->link.std) { 1895 usb_syncmem(&p->dma, 1896 p->offs + offsetof(uhci_td_t, td_link), 1897 sizeof(p->td.td_link), 1898 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1899 td_link = le32toh(p->td.td_link); 1900 usb_syncmem(&p->dma, 1901 p->offs + offsetof(uhci_td_t, td_link), 1902 sizeof(p->td.td_link), 1903 BUS_DMASYNC_PREREAD); 1904 if ((td_link & UHCI_PTR_T) == 0) { 1905 p->td.td_link = htole32(UHCI_PTR_T); 1906 usb_syncmem(&p->dma, 1907 p->offs + offsetof(uhci_td_t, td_link), 1908 sizeof(p->td.td_link), 1909 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1910 } 1911 } 1912 delay(UHCI_QH_REMOVE_DELAY); 1913 1914 for (; std != stdend; std = p) { 1915 p = std->link.std; 1916 uhci_free_std(sc, std); 1917 } 1918 } 1919 1920 usbd_status 1921 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1922 int rd, uint16_t flags, usb_dma_t *dma, 1923 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1924 { 1925 uhci_soft_td_t *p, *lastp; 1926 uhci_physaddr_t lastlink; 1927 int i, ntd, l, tog, maxp; 1928 uint32_t status; 1929 int addr = upipe->pipe.up_dev->ud_addr; 1930 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1931 1932 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1933 1934 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 1935 addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed); 1936 1937 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1938 1939 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1940 if (maxp == 0) { 1941 printf("uhci_alloc_std_chain: maxp=0\n"); 1942 return USBD_INVAL; 1943 } 1944 ntd = (len + maxp - 1) / maxp; 1945 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1946 ntd++; 1947 DPRINTFN(10, "maxp=%d ntd=%d", 1948 maxp, ntd, 0, 0); 1949 1950 if (ntd == 0) { 1951 *sp = *ep = NULL; 1952 DPRINTF("ntd=0", 0, 0, 0, 0); 1953 return USBD_NORMAL_COMPLETION; 1954 } 1955 tog = upipe->nexttoggle; 1956 if (ntd % 2 == 0) 1957 tog ^= 1; 1958 upipe->nexttoggle = tog ^ 1; 1959 lastp = NULL; 1960 lastlink = UHCI_PTR_T; 1961 ntd--; 1962 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1963 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1964 status |= UHCI_TD_LS; 1965 if (flags & USBD_SHORT_XFER_OK) 1966 status |= UHCI_TD_SPD; 1967 usb_syncmem(dma, 0, len, 1968 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1969 for (i = ntd; i >= 0; i--) { 1970 p = uhci_alloc_std(sc); 1971 if (p == NULL) { 1972 KASSERT(lastp != NULL); 1973 uhci_free_std_chain(sc, lastp, NULL); 1974 return USBD_NOMEM; 1975 } 1976 p->link.std = lastp; 1977 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1978 lastp = p; 1979 lastlink = p->physaddr; 1980 p->td.td_status = htole32(status); 1981 if (i == ntd) { 1982 /* last TD */ 1983 l = len % maxp; 1984 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1985 l = maxp; 1986 *ep = p; 1987 } else 1988 l = maxp; 1989 p->td.td_token = 1990 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1991 UHCI_TD_OUT(l, endpt, addr, tog)); 1992 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1993 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1994 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1995 tog ^= 1; 1996 } 1997 *sp = lastp; 1998 DPRINTFN(10, "nexttog=%d", upipe->nexttoggle, 1999 0, 0, 0); 2000 2001 return USBD_NORMAL_COMPLETION; 2002 } 2003 2004 void 2005 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2006 { 2007 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2008 upipe->nexttoggle = 0; 2009 } 2010 2011 void 2012 uhci_noop(struct usbd_pipe *pipe) 2013 { 2014 } 2015 2016 usbd_status 2017 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2018 { 2019 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2020 usbd_status err; 2021 2022 /* Insert last in queue. */ 2023 mutex_enter(&sc->sc_lock); 2024 err = usb_insert_transfer(xfer); 2025 mutex_exit(&sc->sc_lock); 2026 if (err) 2027 return err; 2028 2029 /* 2030 * Pipe isn't running (otherwise err would be USBD_INPROG), 2031 * so start it first. 2032 */ 2033 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2034 } 2035 2036 usbd_status 2037 uhci_device_bulk_start(struct usbd_xfer *xfer) 2038 { 2039 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2040 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2041 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2042 uhci_soft_td_t *data, *dataend; 2043 uhci_soft_qh_t *sqh; 2044 usbd_status err; 2045 int len, isread, endpt; 2046 2047 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2048 DPRINTFN(3, "xfer=%p len=%d flags=%d ux=%p", 2049 xfer, xfer->ux_length, xfer->ux_flags, ux); 2050 2051 if (sc->sc_dying) 2052 return USBD_IOERROR; 2053 2054 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2055 2056 mutex_enter(&sc->sc_lock); 2057 2058 len = xfer->ux_length; 2059 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2060 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2061 sqh = upipe->bulk.sqh; 2062 2063 upipe->bulk.isread = isread; 2064 upipe->bulk.length = len; 2065 2066 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2067 &xfer->ux_dmabuf, &data, &dataend); 2068 if (err) { 2069 mutex_exit(&sc->sc_lock); 2070 return err; 2071 } 2072 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2073 usb_syncmem(&dataend->dma, 2074 dataend->offs + offsetof(uhci_td_t, td_status), 2075 sizeof(dataend->td.td_status), 2076 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2077 2078 2079 #ifdef UHCI_DEBUG 2080 if (uhcidebug > 8) { 2081 DPRINTFN(8, "data(1)", 0, 0, 0, 0); 2082 uhci_dump_tds(data); 2083 } 2084 #endif 2085 2086 /* Set up interrupt info. */ 2087 ux->stdstart = data; 2088 ux->stdend = dataend; 2089 2090 KASSERT(ux->isdone); 2091 #ifdef DIAGNOSTIC 2092 ux->isdone = false; 2093 #endif 2094 2095 sqh->elink = data; 2096 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2097 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2098 2099 uhci_add_bulk(sc, sqh); 2100 uhci_add_intr_info(sc, ux); 2101 2102 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2103 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2104 uhci_timeout, xfer); 2105 } 2106 xfer->ux_status = USBD_IN_PROGRESS; 2107 2108 #ifdef UHCI_DEBUG 2109 if (uhcidebug > 10) { 2110 DPRINTFN(10, "data(2)", 0, 0, 0, 0); 2111 uhci_dump_tds(data); 2112 } 2113 #endif 2114 2115 if (sc->sc_bus.ub_usepolling) 2116 uhci_waitintr(sc, xfer); 2117 2118 mutex_exit(&sc->sc_lock); 2119 return USBD_IN_PROGRESS; 2120 } 2121 2122 /* Abort a device bulk request. */ 2123 void 2124 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2125 { 2126 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2127 2128 KASSERT(mutex_owned(&sc->sc_lock)); 2129 2130 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2131 2132 uhci_abort_xfer(xfer, USBD_CANCELLED); 2133 } 2134 2135 /* 2136 * Abort a device request. 2137 * If this routine is called at splusb() it guarantees that the request 2138 * will be removed from the hardware scheduling and that the callback 2139 * for it will be called with USBD_CANCELLED status. 2140 * It's impossible to guarantee that the requested transfer will not 2141 * have happened since the hardware runs concurrently. 2142 * If the transaction has already happened we rely on the ordinary 2143 * interrupt processing to process it. 2144 * XXX This is most probably wrong. 2145 * XXXMRG this doesn't make sense anymore. 2146 */ 2147 void 2148 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2149 { 2150 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2151 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2152 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2153 uhci_soft_td_t *std; 2154 int wake; 2155 2156 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2157 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2158 2159 KASSERT(mutex_owned(&sc->sc_lock)); 2160 ASSERT_SLEEPABLE(); 2161 2162 if (sc->sc_dying) { 2163 /* If we're dying, just do the software part. */ 2164 xfer->ux_status = status; /* make software ignore it */ 2165 callout_stop(&xfer->ux_callout); 2166 usb_transfer_complete(xfer); 2167 return; 2168 } 2169 2170 /* 2171 * If an abort is already in progress then just wait for it to 2172 * complete and return. 2173 */ 2174 if (xfer->ux_hcflags & UXFER_ABORTING) { 2175 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2176 #ifdef DIAGNOSTIC 2177 if (status == USBD_TIMEOUT) 2178 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2179 #endif 2180 /* Override the status which might be USBD_TIMEOUT. */ 2181 xfer->ux_status = status; 2182 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2183 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2184 while (xfer->ux_hcflags & UXFER_ABORTING) 2185 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2186 goto done; 2187 } 2188 xfer->ux_hcflags |= UXFER_ABORTING; 2189 2190 /* 2191 * Step 1: Make interrupt routine and hardware ignore xfer. 2192 */ 2193 xfer->ux_status = status; /* make software ignore it */ 2194 callout_stop(&xfer->ux_callout); 2195 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2196 for (std = ux->stdstart; std != NULL; std = std->link.std) { 2197 usb_syncmem(&std->dma, 2198 std->offs + offsetof(uhci_td_t, td_status), 2199 sizeof(std->td.td_status), 2200 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2201 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2202 usb_syncmem(&std->dma, 2203 std->offs + offsetof(uhci_td_t, td_status), 2204 sizeof(std->td.td_status), 2205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2206 } 2207 2208 /* 2209 * Step 2: Wait until we know hardware has finished any possible 2210 * use of the xfer. Also make sure the soft interrupt routine 2211 * has run. 2212 */ 2213 /* Hardware finishes in 1ms */ 2214 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2215 sc->sc_softwake = 1; 2216 usb_schedsoftintr(&sc->sc_bus); 2217 DPRINTF("cv_wait", 0, 0, 0, 0); 2218 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2219 2220 /* 2221 * Step 3: Execute callback. 2222 */ 2223 DPRINTF("callback", 0, 0, 0, 0); 2224 #ifdef DIAGNOSTIC 2225 ux->isdone = true; 2226 #endif 2227 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2228 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2229 usb_transfer_complete(xfer); 2230 if (wake) 2231 cv_broadcast(&xfer->ux_hccv); 2232 done: 2233 KASSERT(mutex_owned(&sc->sc_lock)); 2234 } 2235 2236 /* Close a device bulk pipe. */ 2237 void 2238 uhci_device_bulk_close(struct usbd_pipe *pipe) 2239 { 2240 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2241 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2242 2243 KASSERT(mutex_owned(&sc->sc_lock)); 2244 2245 uhci_free_sqh(sc, upipe->bulk.sqh); 2246 2247 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2248 } 2249 2250 usbd_status 2251 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2252 { 2253 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2254 usbd_status err; 2255 2256 /* Insert last in queue. */ 2257 mutex_enter(&sc->sc_lock); 2258 err = usb_insert_transfer(xfer); 2259 mutex_exit(&sc->sc_lock); 2260 if (err) 2261 return err; 2262 2263 /* 2264 * Pipe isn't running (otherwise err would be USBD_INPROG), 2265 * so start it first. 2266 */ 2267 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2268 } 2269 2270 usbd_status 2271 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2272 { 2273 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2274 usbd_status err; 2275 2276 if (sc->sc_dying) 2277 return USBD_IOERROR; 2278 2279 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2280 2281 mutex_enter(&sc->sc_lock); 2282 err = uhci_device_request(xfer); 2283 mutex_exit(&sc->sc_lock); 2284 if (err) 2285 return err; 2286 2287 if (sc->sc_bus.ub_usepolling) 2288 uhci_waitintr(sc, xfer); 2289 return USBD_IN_PROGRESS; 2290 } 2291 2292 usbd_status 2293 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2294 { 2295 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2296 usbd_status err; 2297 2298 /* Insert last in queue. */ 2299 mutex_enter(&sc->sc_lock); 2300 err = usb_insert_transfer(xfer); 2301 mutex_exit(&sc->sc_lock); 2302 if (err) 2303 return err; 2304 2305 /* 2306 * Pipe isn't running (otherwise err would be USBD_INPROG), 2307 * so start it first. 2308 */ 2309 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2310 } 2311 2312 usbd_status 2313 uhci_device_intr_start(struct usbd_xfer *xfer) 2314 { 2315 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2316 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2317 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2318 uhci_soft_td_t *data, *dataend; 2319 uhci_soft_qh_t *sqh; 2320 usbd_status err; 2321 int isread, endpt; 2322 int i; 2323 2324 if (sc->sc_dying) 2325 return USBD_IOERROR; 2326 2327 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2328 2329 DPRINTFN(3, "xfer=%p len=%d flags=%d", 2330 xfer, xfer->ux_length, xfer->ux_flags, 0); 2331 2332 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2333 2334 mutex_enter(&sc->sc_lock); 2335 2336 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2337 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2338 2339 upipe->intr.isread = isread; 2340 2341 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2342 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2343 &dataend); 2344 if (err) { 2345 mutex_exit(&sc->sc_lock); 2346 return err; 2347 } 2348 2349 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2350 usb_syncmem(&dataend->dma, 2351 dataend->offs + offsetof(uhci_td_t, td_status), 2352 sizeof(dataend->td.td_status), 2353 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2354 2355 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2356 #ifdef UHCI_DEBUG 2357 if (uhcidebug > 10) { 2358 uhci_dump_tds(data); 2359 uhci_dump_qh(upipe->intr.qhs[0]); 2360 } 2361 #endif 2362 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2363 2364 /* Set up interrupt info. */ 2365 ux->stdstart = data; 2366 ux->stdend = dataend; 2367 KASSERT(ux->isdone); 2368 #ifdef DIAGNOSTIC 2369 ux->isdone = false; 2370 #endif 2371 2372 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2373 for (i = 0; i < upipe->intr.npoll; i++) { 2374 sqh = upipe->intr.qhs[i]; 2375 sqh->elink = data; 2376 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2377 usb_syncmem(&sqh->dma, 2378 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2379 sizeof(sqh->qh.qh_elink), 2380 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2381 } 2382 uhci_add_intr_info(sc, ux); 2383 xfer->ux_status = USBD_IN_PROGRESS; 2384 mutex_exit(&sc->sc_lock); 2385 2386 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2387 #ifdef UHCI_DEBUG 2388 if (uhcidebug > 10) { 2389 uhci_dump_tds(data); 2390 uhci_dump_qh(upipe->intr.qhs[0]); 2391 } 2392 #endif 2393 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2394 2395 return USBD_IN_PROGRESS; 2396 } 2397 2398 /* Abort a device control request. */ 2399 void 2400 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2401 { 2402 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2403 2404 KASSERT(mutex_owned(&sc->sc_lock)); 2405 2406 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2407 uhci_abort_xfer(xfer, USBD_CANCELLED); 2408 } 2409 2410 /* Close a device control pipe. */ 2411 void 2412 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2413 { 2414 } 2415 2416 /* Abort a device interrupt request. */ 2417 void 2418 uhci_device_intr_abort(struct usbd_xfer *xfer) 2419 { 2420 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2421 2422 KASSERT(mutex_owned(&sc->sc_lock)); 2423 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2424 2425 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2426 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2427 2428 uhci_abort_xfer(xfer, USBD_CANCELLED); 2429 } 2430 2431 /* Close a device interrupt pipe. */ 2432 void 2433 uhci_device_intr_close(struct usbd_pipe *pipe) 2434 { 2435 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2436 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2437 int i, npoll; 2438 2439 KASSERT(mutex_owned(&sc->sc_lock)); 2440 2441 /* Unlink descriptors from controller data structures. */ 2442 npoll = upipe->intr.npoll; 2443 for (i = 0; i < npoll; i++) 2444 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2445 2446 /* 2447 * We now have to wait for any activity on the physical 2448 * descriptors to stop. 2449 */ 2450 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2451 2452 for(i = 0; i < npoll; i++) 2453 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2454 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2455 2456 /* XXX free other resources */ 2457 } 2458 2459 usbd_status 2460 uhci_device_request(struct usbd_xfer *xfer) 2461 { 2462 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2463 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2464 usb_device_request_t *req = &xfer->ux_request; 2465 struct usbd_device *dev = upipe->pipe.up_dev; 2466 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2467 int addr = dev->ud_addr; 2468 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2469 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2470 uhci_soft_qh_t *sqh; 2471 int len; 2472 uint32_t ls; 2473 usbd_status err; 2474 int isread; 2475 2476 KASSERT(mutex_owned(&sc->sc_lock)); 2477 2478 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2479 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2480 "wValue=0x%04x, wIndex=0x%04x", 2481 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2482 UGETW(req->wIndex)); 2483 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2484 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2485 2486 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2487 isread = req->bmRequestType & UT_READ; 2488 len = UGETW(req->wLength); 2489 2490 setup = upipe->ctrl.setup; 2491 stat = upipe->ctrl.stat; 2492 sqh = upipe->ctrl.sqh; 2493 2494 /* Set up data transaction */ 2495 if (len != 0) { 2496 upipe->nexttoggle = 1; 2497 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2498 &xfer->ux_dmabuf, &data, &dataend); 2499 if (err) 2500 return err; 2501 next = data; 2502 dataend->link.std = stat; 2503 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2504 usb_syncmem(&dataend->dma, 2505 dataend->offs + offsetof(uhci_td_t, td_link), 2506 sizeof(dataend->td.td_link), 2507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2508 } else { 2509 next = stat; 2510 } 2511 upipe->ctrl.length = len; 2512 2513 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2514 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2515 2516 setup->link.std = next; 2517 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2518 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2519 UHCI_TD_ACTIVE); 2520 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2521 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2522 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2523 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2524 2525 stat->link.std = NULL; 2526 stat->td.td_link = htole32(UHCI_PTR_T); 2527 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2528 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2529 stat->td.td_token = 2530 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2531 UHCI_TD_IN (0, endpt, addr, 1)); 2532 stat->td.td_buffer = htole32(0); 2533 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2535 2536 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2537 #ifdef UHCI_DEBUG 2538 if (uhcidebug > 10) { 2539 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2540 uhci_dump_tds(setup); 2541 } 2542 #endif 2543 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2544 2545 /* Set up interrupt info. */ 2546 uxfer->stdstart = setup; 2547 uxfer->stdend = stat; 2548 KASSERT(uxfer->isdone); 2549 #ifdef DIAGNOSTIC 2550 uxfer->isdone = false; 2551 #endif 2552 2553 sqh->elink = setup; 2554 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2555 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2556 2557 if (dev->ud_speed == USB_SPEED_LOW) 2558 uhci_add_ls_ctrl(sc, sqh); 2559 else 2560 uhci_add_hs_ctrl(sc, sqh); 2561 uhci_add_intr_info(sc, uxfer); 2562 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2563 #ifdef UHCI_DEBUG 2564 if (uhcidebug > 12) { 2565 uhci_soft_td_t *std; 2566 uhci_soft_qh_t *xqh; 2567 uhci_soft_qh_t *sxqh; 2568 int maxqh = 0; 2569 uhci_physaddr_t link; 2570 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2571 for (std = sc->sc_vframes[0].htd, link = 0; 2572 (link & UHCI_PTR_QH) == 0; 2573 std = std->link.std) { 2574 link = le32toh(std->td.td_link); 2575 uhci_dump_td(std); 2576 } 2577 sxqh = (uhci_soft_qh_t *)std; 2578 uhci_dump_qh(sxqh); 2579 for (xqh = sxqh; 2580 xqh != NULL; 2581 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2582 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2583 uhci_dump_qh(xqh); 2584 } 2585 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2586 uhci_dump_qh(sqh); 2587 uhci_dump_tds(sqh->elink); 2588 } 2589 #endif 2590 DPRINTFN(12, "--- dump end ---", 0, 0, 0, 0); 2591 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2592 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2593 uhci_timeout, xfer); 2594 } 2595 xfer->ux_status = USBD_IN_PROGRESS; 2596 2597 return USBD_NORMAL_COMPLETION; 2598 } 2599 2600 usbd_status 2601 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2602 { 2603 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2604 usbd_status err; 2605 2606 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2607 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2608 2609 /* Put it on our queue, */ 2610 mutex_enter(&sc->sc_lock); 2611 err = usb_insert_transfer(xfer); 2612 mutex_exit(&sc->sc_lock); 2613 2614 /* bail out on error, */ 2615 if (err && err != USBD_IN_PROGRESS) 2616 return err; 2617 2618 /* XXX should check inuse here */ 2619 2620 /* insert into schedule, */ 2621 uhci_device_isoc_enter(xfer); 2622 2623 /* and start if the pipe wasn't running */ 2624 if (!err) 2625 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2626 2627 return err; 2628 } 2629 2630 void 2631 uhci_device_isoc_enter(struct usbd_xfer *xfer) 2632 { 2633 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2634 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2635 struct isoc *isoc = &upipe->isoc; 2636 uhci_soft_td_t *std; 2637 uint32_t buf, len, status, offs; 2638 int i, next, nframes; 2639 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2640 2641 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2642 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2643 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2644 2645 if (sc->sc_dying) 2646 return; 2647 2648 if (xfer->ux_status == USBD_IN_PROGRESS) { 2649 /* This request has already been entered into the frame list */ 2650 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2651 /* XXX */ 2652 } 2653 2654 #ifdef DIAGNOSTIC 2655 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2656 printf("uhci_device_isoc_enter: overflow!\n"); 2657 #endif 2658 2659 next = isoc->next; 2660 if (next == -1) { 2661 /* Not in use yet, schedule it a few frames ahead. */ 2662 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2663 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2664 } 2665 2666 xfer->ux_status = USBD_IN_PROGRESS; 2667 UHCI_XFER2UXFER(xfer)->curframe = next; 2668 2669 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2670 offs = 0; 2671 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2672 UHCI_TD_ACTIVE | 2673 UHCI_TD_IOS); 2674 nframes = xfer->ux_nframes; 2675 mutex_enter(&sc->sc_lock); 2676 for (i = 0; i < nframes; i++) { 2677 std = isoc->stds[next]; 2678 if (++next >= UHCI_VFRAMELIST_COUNT) 2679 next = 0; 2680 len = xfer->ux_frlengths[i]; 2681 std->td.td_buffer = htole32(buf); 2682 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2683 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2684 if (i == nframes - 1) 2685 status |= UHCI_TD_IOC; 2686 std->td.td_status = htole32(status); 2687 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2688 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2689 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2690 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2691 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2692 #ifdef UHCI_DEBUG 2693 if (uhcidebug > 5) { 2694 DPRINTF("TD %d", i, 0, 0, 0); 2695 uhci_dump_td(std); 2696 } 2697 #endif 2698 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2699 buf += len; 2700 offs += len; 2701 } 2702 isoc->next = next; 2703 isoc->inuse += xfer->ux_nframes; 2704 2705 mutex_exit(&sc->sc_lock); 2706 } 2707 2708 usbd_status 2709 uhci_device_isoc_start(struct usbd_xfer *xfer) 2710 { 2711 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2712 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2713 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2714 uhci_soft_td_t *end; 2715 int i; 2716 2717 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2718 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2719 2720 mutex_enter(&sc->sc_lock); 2721 2722 if (sc->sc_dying) { 2723 mutex_exit(&sc->sc_lock); 2724 return USBD_IOERROR; 2725 } 2726 2727 #ifdef DIAGNOSTIC 2728 if (xfer->ux_status != USBD_IN_PROGRESS) 2729 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2730 #endif 2731 2732 /* Find the last TD */ 2733 i = UHCI_XFER2UXFER(xfer)->curframe + xfer->ux_nframes; 2734 if (i >= UHCI_VFRAMELIST_COUNT) 2735 i -= UHCI_VFRAMELIST_COUNT; 2736 end = upipe->isoc.stds[i]; 2737 2738 KASSERT(end != NULL); 2739 2740 /* Set up interrupt info. */ 2741 ux->stdstart = end; 2742 ux->stdend = end; 2743 2744 KASSERT(ux->isdone); 2745 #ifdef DIAGNOSTIC 2746 ux->isdone = false; 2747 #endif 2748 uhci_add_intr_info(sc, ux); 2749 2750 mutex_exit(&sc->sc_lock); 2751 2752 return USBD_IN_PROGRESS; 2753 } 2754 2755 void 2756 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2757 { 2758 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2759 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2760 uhci_soft_td_t **stds = upipe->isoc.stds; 2761 uhci_soft_td_t *std; 2762 int i, n, nframes, maxlen, len; 2763 2764 KASSERT(mutex_owned(&sc->sc_lock)); 2765 2766 /* Transfer is already done. */ 2767 if (xfer->ux_status != USBD_NOT_STARTED && 2768 xfer->ux_status != USBD_IN_PROGRESS) { 2769 return; 2770 } 2771 2772 /* Give xfer the requested abort code. */ 2773 xfer->ux_status = USBD_CANCELLED; 2774 2775 /* make hardware ignore it, */ 2776 nframes = xfer->ux_nframes; 2777 n = UHCI_XFER2UXFER(xfer)->curframe; 2778 maxlen = 0; 2779 for (i = 0; i < nframes; i++) { 2780 std = stds[n]; 2781 usb_syncmem(&std->dma, 2782 std->offs + offsetof(uhci_td_t, td_status), 2783 sizeof(std->td.td_status), 2784 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2785 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2786 usb_syncmem(&std->dma, 2787 std->offs + offsetof(uhci_td_t, td_status), 2788 sizeof(std->td.td_status), 2789 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2790 usb_syncmem(&std->dma, 2791 std->offs + offsetof(uhci_td_t, td_token), 2792 sizeof(std->td.td_token), 2793 BUS_DMASYNC_POSTWRITE); 2794 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2795 if (len > maxlen) 2796 maxlen = len; 2797 if (++n >= UHCI_VFRAMELIST_COUNT) 2798 n = 0; 2799 } 2800 2801 /* and wait until we are sure the hardware has finished. */ 2802 delay(maxlen); 2803 2804 #ifdef DIAGNOSTIC 2805 UHCI_XFER2UXFER(xfer)->isdone = true; 2806 #endif 2807 /* Run callback and remove from interrupt list. */ 2808 usb_transfer_complete(xfer); 2809 2810 KASSERT(mutex_owned(&sc->sc_lock)); 2811 } 2812 2813 void 2814 uhci_device_isoc_close(struct usbd_pipe *pipe) 2815 { 2816 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2817 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2818 uhci_soft_td_t *std, *vstd; 2819 struct isoc *isoc; 2820 int i; 2821 2822 KASSERT(mutex_owned(&sc->sc_lock)); 2823 2824 /* 2825 * Make sure all TDs are marked as inactive. 2826 * Wait for completion. 2827 * Unschedule. 2828 * Deallocate. 2829 */ 2830 isoc = &upipe->isoc; 2831 2832 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2833 std = isoc->stds[i]; 2834 usb_syncmem(&std->dma, 2835 std->offs + offsetof(uhci_td_t, td_status), 2836 sizeof(std->td.td_status), 2837 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2838 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2839 usb_syncmem(&std->dma, 2840 std->offs + offsetof(uhci_td_t, td_status), 2841 sizeof(std->td.td_status), 2842 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2843 } 2844 /* wait for completion */ 2845 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2846 2847 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2848 std = isoc->stds[i]; 2849 for (vstd = sc->sc_vframes[i].htd; 2850 vstd != NULL && vstd->link.std != std; 2851 vstd = vstd->link.std) 2852 ; 2853 if (vstd == NULL) { 2854 /*panic*/ 2855 printf("uhci_device_isoc_close: %p not found\n", std); 2856 mutex_exit(&sc->sc_lock); 2857 return; 2858 } 2859 vstd->link = std->link; 2860 usb_syncmem(&std->dma, 2861 std->offs + offsetof(uhci_td_t, td_link), 2862 sizeof(std->td.td_link), 2863 BUS_DMASYNC_POSTWRITE); 2864 vstd->td.td_link = std->td.td_link; 2865 usb_syncmem(&vstd->dma, 2866 vstd->offs + offsetof(uhci_td_t, td_link), 2867 sizeof(vstd->td.td_link), 2868 BUS_DMASYNC_PREWRITE); 2869 uhci_free_std(sc, std); 2870 } 2871 2872 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2873 } 2874 2875 usbd_status 2876 uhci_setup_isoc(struct usbd_pipe *pipe) 2877 { 2878 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2879 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2880 int addr = upipe->pipe.up_dev->ud_addr; 2881 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2882 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2883 uhci_soft_td_t *std, *vstd; 2884 uint32_t token; 2885 struct isoc *isoc; 2886 int i; 2887 2888 isoc = &upipe->isoc; 2889 isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2890 sizeof(uhci_soft_td_t *), 2891 KM_SLEEP); 2892 if (isoc->stds == NULL) 2893 return USBD_NOMEM; 2894 2895 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2896 UHCI_TD_OUT(0, endpt, addr, 0); 2897 2898 mutex_enter(&sc->sc_lock); 2899 2900 /* Allocate the TDs and mark as inactive; */ 2901 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2902 std = uhci_alloc_std(sc); 2903 if (std == 0) 2904 goto bad; 2905 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2906 std->td.td_token = htole32(token); 2907 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2908 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2909 isoc->stds[i] = std; 2910 } 2911 2912 /* Insert TDs into schedule. */ 2913 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2914 std = isoc->stds[i]; 2915 vstd = sc->sc_vframes[i].htd; 2916 usb_syncmem(&vstd->dma, 2917 vstd->offs + offsetof(uhci_td_t, td_link), 2918 sizeof(vstd->td.td_link), 2919 BUS_DMASYNC_POSTWRITE); 2920 std->link = vstd->link; 2921 std->td.td_link = vstd->td.td_link; 2922 usb_syncmem(&std->dma, 2923 std->offs + offsetof(uhci_td_t, td_link), 2924 sizeof(std->td.td_link), 2925 BUS_DMASYNC_PREWRITE); 2926 vstd->link.std = std; 2927 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2928 usb_syncmem(&vstd->dma, 2929 vstd->offs + offsetof(uhci_td_t, td_link), 2930 sizeof(vstd->td.td_link), 2931 BUS_DMASYNC_PREWRITE); 2932 } 2933 mutex_exit(&sc->sc_lock); 2934 2935 isoc->next = -1; 2936 isoc->inuse = 0; 2937 2938 return USBD_NORMAL_COMPLETION; 2939 2940 bad: 2941 while (--i >= 0) 2942 uhci_free_std(sc, isoc->stds[i]); 2943 mutex_exit(&sc->sc_lock); 2944 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2945 return USBD_NOMEM; 2946 } 2947 2948 void 2949 uhci_device_isoc_done(struct usbd_xfer *xfer) 2950 { 2951 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2952 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2953 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2954 int i, offs; 2955 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2956 2957 2958 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2959 DPRINTFN(4, "length=%d, ux_state=0x%08x", 2960 xfer->ux_actlen, xfer->ux_state, 0, 0); 2961 2962 if (!uhci_active_intr_info(ux)) 2963 return; 2964 2965 #ifdef DIAGNOSTIC 2966 if (ux->stdend == NULL) { 2967 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2968 #ifdef UHCI_DEBUG 2969 uhci_dump_ii(ux); 2970 #endif 2971 return; 2972 } 2973 #endif 2974 2975 /* Turn off the interrupt since it is active even if the TD is not. */ 2976 usb_syncmem(&ux->stdend->dma, 2977 ux->stdend->offs + offsetof(uhci_td_t, td_status), 2978 sizeof(ux->stdend->td.td_status), 2979 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2980 ux->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2981 usb_syncmem(&ux->stdend->dma, 2982 ux->stdend->offs + offsetof(uhci_td_t, td_status), 2983 sizeof(ux->stdend->td.td_status), 2984 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2985 2986 uhci_del_intr_info(sc, ux); /* remove from active list */ 2987 2988 offs = 0; 2989 for (i = 0; i < xfer->ux_nframes; i++) { 2990 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2991 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2992 offs += xfer->ux_frlengths[i]; 2993 } 2994 } 2995 2996 void 2997 uhci_device_intr_done(struct usbd_xfer *xfer) 2998 { 2999 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3000 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3001 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3002 uhci_soft_qh_t *sqh; 3003 int i, npoll, isread; 3004 3005 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3006 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3007 3008 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3009 3010 npoll = upipe->intr.npoll; 3011 for(i = 0; i < npoll; i++) { 3012 sqh = upipe->intr.qhs[i]; 3013 sqh->elink = NULL; 3014 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3015 usb_syncmem(&sqh->dma, 3016 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3017 sizeof(sqh->qh.qh_elink), 3018 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3019 } 3020 uhci_free_std_chain(sc, ux->stdstart, NULL); 3021 3022 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3023 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3024 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3025 3026 /* XXX Wasteful. */ 3027 if (xfer->ux_pipe->up_repeat) { 3028 uhci_soft_td_t *data, *dataend; 3029 3030 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3031 3032 /* This alloc cannot fail since we freed the chain above. */ 3033 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3034 upipe->intr.isread, xfer->ux_flags, 3035 &xfer->ux_dmabuf, &data, &dataend); 3036 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3037 usb_syncmem(&dataend->dma, 3038 dataend->offs + offsetof(uhci_td_t, td_status), 3039 sizeof(dataend->td.td_status), 3040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3041 3042 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 3043 #ifdef UHCI_DEBUG 3044 if (uhcidebug > 10) { 3045 uhci_dump_tds(data); 3046 uhci_dump_qh(upipe->intr.qhs[0]); 3047 } 3048 #endif 3049 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 3050 3051 ux->stdstart = data; 3052 ux->stdend = dataend; 3053 KASSERT(ux->isdone); 3054 #ifdef DIAGNOSTIC 3055 ux->isdone = false; 3056 #endif 3057 for (i = 0; i < npoll; i++) { 3058 sqh = upipe->intr.qhs[i]; 3059 sqh->elink = data; 3060 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3061 usb_syncmem(&sqh->dma, 3062 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3063 sizeof(sqh->qh.qh_elink), 3064 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3065 } 3066 xfer->ux_status = USBD_IN_PROGRESS; 3067 /* The ux is already on the examined list, just leave it. */ 3068 } else { 3069 DPRINTFN(5, "removing", 0, 0, 0, 0); 3070 if (uhci_active_intr_info(ux)) 3071 uhci_del_intr_info(sc, ux); 3072 } 3073 } 3074 3075 /* Deallocate request data structures */ 3076 void 3077 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3078 { 3079 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3080 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3081 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3082 int len = UGETW(xfer->ux_request.wLength); 3083 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3084 3085 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3086 3087 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3088 3089 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3090 3091 if (!uhci_active_intr_info(ux)) 3092 return; 3093 3094 uhci_del_intr_info(sc, ux); /* remove from active list */ 3095 3096 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3097 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3098 else 3099 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3100 3101 if (upipe->ctrl.length != 0) 3102 uhci_free_std_chain(sc, ux->stdstart->link.std, ux->stdend); 3103 3104 if (len) { 3105 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3106 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3107 } 3108 usb_syncmem(&upipe->ctrl.reqdma, 0, 3109 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3110 3111 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3112 } 3113 3114 /* Deallocate request data structures */ 3115 void 3116 uhci_device_bulk_done(struct usbd_xfer *xfer) 3117 { 3118 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3119 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3120 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3121 3122 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3123 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3124 upipe); 3125 3126 KASSERT(mutex_owned(&sc->sc_lock)); 3127 3128 if (!uhci_active_intr_info(ux)) 3129 return; 3130 3131 uhci_del_intr_info(sc, ux); /* remove from active list */ 3132 3133 uhci_remove_bulk(sc, upipe->bulk.sqh); 3134 3135 uhci_free_std_chain(sc, ux->stdstart, NULL); 3136 3137 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3138 } 3139 3140 /* Add interrupt QH, called with vflock. */ 3141 void 3142 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3143 { 3144 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3145 uhci_soft_qh_t *eqh; 3146 3147 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3148 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3149 3150 eqh = vf->eqh; 3151 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3152 sizeof(eqh->qh.qh_hlink), 3153 BUS_DMASYNC_POSTWRITE); 3154 sqh->hlink = eqh->hlink; 3155 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3156 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3157 sizeof(sqh->qh.qh_hlink), 3158 BUS_DMASYNC_PREWRITE); 3159 eqh->hlink = sqh; 3160 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3161 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3162 sizeof(eqh->qh.qh_hlink), 3163 BUS_DMASYNC_PREWRITE); 3164 vf->eqh = sqh; 3165 vf->bandwidth++; 3166 } 3167 3168 /* Remove interrupt QH. */ 3169 void 3170 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3171 { 3172 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3173 uhci_soft_qh_t *pqh; 3174 3175 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3176 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3177 3178 /* See comment in uhci_remove_ctrl() */ 3179 3180 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3181 sizeof(sqh->qh.qh_elink), 3182 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3183 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3184 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3185 usb_syncmem(&sqh->dma, 3186 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3187 sizeof(sqh->qh.qh_elink), 3188 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3189 delay(UHCI_QH_REMOVE_DELAY); 3190 } 3191 3192 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3193 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3194 sizeof(sqh->qh.qh_hlink), 3195 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3196 pqh->hlink = sqh->hlink; 3197 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3198 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3199 sizeof(pqh->qh.qh_hlink), 3200 BUS_DMASYNC_PREWRITE); 3201 delay(UHCI_QH_REMOVE_DELAY); 3202 if (vf->eqh == sqh) 3203 vf->eqh = pqh; 3204 vf->bandwidth--; 3205 } 3206 3207 usbd_status 3208 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3209 { 3210 uhci_soft_qh_t *sqh; 3211 int i, npoll; 3212 u_int bestbw, bw, bestoffs, offs; 3213 3214 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3215 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3216 if (ival == 0) { 3217 printf("uhci_device_setintr: 0 interval\n"); 3218 return USBD_INVAL; 3219 } 3220 3221 if (ival > UHCI_VFRAMELIST_COUNT) 3222 ival = UHCI_VFRAMELIST_COUNT; 3223 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3224 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3225 3226 upipe->intr.npoll = npoll; 3227 upipe->intr.qhs = 3228 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3229 if (upipe->intr.qhs == NULL) 3230 return USBD_NOMEM; 3231 3232 /* 3233 * Figure out which offset in the schedule that has most 3234 * bandwidth left over. 3235 */ 3236 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3237 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3238 for (bw = i = 0; i < npoll; i++) 3239 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3240 if (bw < bestbw) { 3241 bestbw = bw; 3242 bestoffs = offs; 3243 } 3244 } 3245 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3246 mutex_enter(&sc->sc_lock); 3247 for(i = 0; i < npoll; i++) { 3248 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3249 sqh->elink = NULL; 3250 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3251 usb_syncmem(&sqh->dma, 3252 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3253 sizeof(sqh->qh.qh_elink), 3254 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3255 sqh->pos = MOD(i * ival + bestoffs); 3256 } 3257 #undef MOD 3258 3259 /* Enter QHs into the controller data structures. */ 3260 for(i = 0; i < npoll; i++) 3261 uhci_add_intr(sc, upipe->intr.qhs[i]); 3262 mutex_exit(&sc->sc_lock); 3263 3264 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3265 3266 return USBD_NORMAL_COMPLETION; 3267 } 3268 3269 /* Open a new pipe. */ 3270 usbd_status 3271 uhci_open(struct usbd_pipe *pipe) 3272 { 3273 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3274 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3275 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3276 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3277 usbd_status err = USBD_NOMEM; 3278 int ival; 3279 3280 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3281 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3282 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3283 3284 if (sc->sc_dying) 3285 return USBD_IOERROR; 3286 3287 upipe->aborting = 0; 3288 /* toggle state needed for bulk endpoints */ 3289 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3290 3291 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3292 switch (ed->bEndpointAddress) { 3293 case USB_CONTROL_ENDPOINT: 3294 pipe->up_methods = &roothub_ctrl_methods; 3295 break; 3296 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3297 pipe->up_methods = &uhci_root_intr_methods; 3298 break; 3299 default: 3300 return USBD_INVAL; 3301 } 3302 } else { 3303 switch (ed->bmAttributes & UE_XFERTYPE) { 3304 case UE_CONTROL: 3305 pipe->up_methods = &uhci_device_ctrl_methods; 3306 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3307 if (upipe->ctrl.sqh == NULL) 3308 goto bad; 3309 upipe->ctrl.setup = uhci_alloc_std(sc); 3310 if (upipe->ctrl.setup == NULL) { 3311 uhci_free_sqh(sc, upipe->ctrl.sqh); 3312 goto bad; 3313 } 3314 upipe->ctrl.stat = uhci_alloc_std(sc); 3315 if (upipe->ctrl.stat == NULL) { 3316 uhci_free_sqh(sc, upipe->ctrl.sqh); 3317 uhci_free_std(sc, upipe->ctrl.setup); 3318 goto bad; 3319 } 3320 err = usb_allocmem(&sc->sc_bus, 3321 sizeof(usb_device_request_t), 3322 0, &upipe->ctrl.reqdma); 3323 if (err) { 3324 uhci_free_sqh(sc, upipe->ctrl.sqh); 3325 uhci_free_std(sc, upipe->ctrl.setup); 3326 uhci_free_std(sc, upipe->ctrl.stat); 3327 goto bad; 3328 } 3329 break; 3330 case UE_INTERRUPT: 3331 pipe->up_methods = &uhci_device_intr_methods; 3332 ival = pipe->up_interval; 3333 if (ival == USBD_DEFAULT_INTERVAL) 3334 ival = ed->bInterval; 3335 return uhci_device_setintr(sc, upipe, ival); 3336 case UE_ISOCHRONOUS: 3337 pipe->up_methods = &uhci_device_isoc_methods; 3338 return uhci_setup_isoc(pipe); 3339 case UE_BULK: 3340 pipe->up_methods = &uhci_device_bulk_methods; 3341 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3342 if (upipe->bulk.sqh == NULL) 3343 goto bad; 3344 break; 3345 } 3346 } 3347 return USBD_NORMAL_COMPLETION; 3348 3349 bad: 3350 return USBD_NOMEM; 3351 } 3352 3353 /* 3354 * Data structures and routines to emulate the root hub. 3355 */ 3356 /* 3357 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3358 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3359 * should not be used by the USB subsystem. As we cannot issue a 3360 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3361 * will be enabled as part of the reset. 3362 * 3363 * On the VT83C572, the port cannot be successfully enabled until the 3364 * outstanding "port enable change" and "connection status change" 3365 * events have been reset. 3366 */ 3367 Static usbd_status 3368 uhci_portreset(uhci_softc_t *sc, int index) 3369 { 3370 int lim, port, x; 3371 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3372 3373 if (index == 1) 3374 port = UHCI_PORTSC1; 3375 else if (index == 2) 3376 port = UHCI_PORTSC2; 3377 else 3378 return USBD_IOERROR; 3379 3380 x = URWMASK(UREAD2(sc, port)); 3381 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3382 3383 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3384 3385 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3386 UREAD2(sc, port), 0, 0); 3387 3388 x = URWMASK(UREAD2(sc, port)); 3389 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3390 3391 delay(100); 3392 3393 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3394 UREAD2(sc, port), 0, 0); 3395 3396 x = URWMASK(UREAD2(sc, port)); 3397 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3398 3399 for (lim = 10; --lim > 0;) { 3400 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3401 3402 x = UREAD2(sc, port); 3403 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3404 lim, x, 0); 3405 3406 if (!(x & UHCI_PORTSC_CCS)) { 3407 /* 3408 * No device is connected (or was disconnected 3409 * during reset). Consider the port reset. 3410 * The delay must be long enough to ensure on 3411 * the initial iteration that the device 3412 * connection will have been registered. 50ms 3413 * appears to be sufficient, but 20ms is not. 3414 */ 3415 DPRINTFN(3, "uhci port %d loop %u, device detached", 3416 index, lim, 0, 0); 3417 break; 3418 } 3419 3420 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3421 /* 3422 * Port enabled changed and/or connection 3423 * status changed were set. Reset either or 3424 * both raised flags (by writing a 1 to that 3425 * bit), and wait again for state to settle. 3426 */ 3427 UWRITE2(sc, port, URWMASK(x) | 3428 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3429 continue; 3430 } 3431 3432 if (x & UHCI_PORTSC_PE) 3433 /* Port is enabled */ 3434 break; 3435 3436 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3437 } 3438 3439 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3440 UREAD2(sc, port), 0, 0); 3441 3442 if (lim <= 0) { 3443 DPRINTF("uhci port %d reset timed out", index, 3444 0, 0, 0); 3445 return USBD_TIMEOUT; 3446 } 3447 3448 sc->sc_isreset = 1; 3449 return USBD_NORMAL_COMPLETION; 3450 } 3451 3452 Static int 3453 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3454 void *buf, int buflen) 3455 { 3456 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3457 int port, x; 3458 int status, change, totlen = 0; 3459 uint16_t len, value, index; 3460 usb_port_status_t ps; 3461 usbd_status err; 3462 3463 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3464 3465 if (sc->sc_dying) 3466 return -1; 3467 3468 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3469 req->bRequest, 0, 0); 3470 3471 len = UGETW(req->wLength); 3472 value = UGETW(req->wValue); 3473 index = UGETW(req->wIndex); 3474 3475 #define C(x,y) ((x) | ((y) << 8)) 3476 switch (C(req->bRequest, req->bmRequestType)) { 3477 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3478 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3479 if (len == 0) 3480 break; 3481 switch (value) { 3482 case C(0, UDESC_DEVICE): { 3483 usb_device_descriptor_t devd; 3484 3485 totlen = min(buflen, sizeof(devd)); 3486 memcpy(&devd, buf, totlen); 3487 USETW(devd.idVendor, sc->sc_id_vendor); 3488 memcpy(buf, &devd, totlen); 3489 break; 3490 } 3491 case C(1, UDESC_STRING): 3492 #define sd ((usb_string_descriptor_t *)buf) 3493 /* Vendor */ 3494 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3495 break; 3496 case C(2, UDESC_STRING): 3497 /* Product */ 3498 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3499 break; 3500 #undef sd 3501 default: 3502 /* default from usbroothub */ 3503 return buflen; 3504 } 3505 break; 3506 3507 /* Hub requests */ 3508 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3509 break; 3510 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3511 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3512 value, 0, 0); 3513 if (index == 1) 3514 port = UHCI_PORTSC1; 3515 else if (index == 2) 3516 port = UHCI_PORTSC2; 3517 else { 3518 return -1; 3519 } 3520 switch(value) { 3521 case UHF_PORT_ENABLE: 3522 x = URWMASK(UREAD2(sc, port)); 3523 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3524 break; 3525 case UHF_PORT_SUSPEND: 3526 x = URWMASK(UREAD2(sc, port)); 3527 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3528 break; 3529 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3530 /* see USB2 spec ch. 7.1.7.7 */ 3531 usb_delay_ms(&sc->sc_bus, 20); 3532 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3533 /* 10ms resume delay must be provided by caller */ 3534 break; 3535 case UHF_PORT_RESET: 3536 x = URWMASK(UREAD2(sc, port)); 3537 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3538 break; 3539 case UHF_C_PORT_CONNECTION: 3540 x = URWMASK(UREAD2(sc, port)); 3541 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3542 break; 3543 case UHF_C_PORT_ENABLE: 3544 x = URWMASK(UREAD2(sc, port)); 3545 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3546 break; 3547 case UHF_C_PORT_OVER_CURRENT: 3548 x = URWMASK(UREAD2(sc, port)); 3549 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3550 break; 3551 case UHF_C_PORT_RESET: 3552 sc->sc_isreset = 0; 3553 break; 3554 case UHF_PORT_CONNECTION: 3555 case UHF_PORT_OVER_CURRENT: 3556 case UHF_PORT_POWER: 3557 case UHF_PORT_LOW_SPEED: 3558 case UHF_C_PORT_SUSPEND: 3559 default: 3560 return -1; 3561 } 3562 break; 3563 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3564 if (index == 1) 3565 port = UHCI_PORTSC1; 3566 else if (index == 2) 3567 port = UHCI_PORTSC2; 3568 else { 3569 return -1; 3570 } 3571 if (len > 0) { 3572 *(uint8_t *)buf = 3573 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3574 UHCI_PORTSC_LS_SHIFT; 3575 totlen = 1; 3576 } 3577 break; 3578 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3579 if (len == 0) 3580 break; 3581 if ((value & 0xff) != 0) { 3582 return -1; 3583 } 3584 usb_hub_descriptor_t hubd; 3585 3586 totlen = min(buflen, sizeof(hubd)); 3587 memcpy(&hubd, buf, totlen); 3588 hubd.bNbrPorts = 2; 3589 memcpy(buf, &hubd, totlen); 3590 break; 3591 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3592 if (len != 4) { 3593 return -1; 3594 } 3595 memset(buf, 0, len); 3596 totlen = len; 3597 break; 3598 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3599 if (index == 1) 3600 port = UHCI_PORTSC1; 3601 else if (index == 2) 3602 port = UHCI_PORTSC2; 3603 else { 3604 return -1; 3605 } 3606 if (len != 4) { 3607 return -1; 3608 } 3609 x = UREAD2(sc, port); 3610 status = change = 0; 3611 if (x & UHCI_PORTSC_CCS) 3612 status |= UPS_CURRENT_CONNECT_STATUS; 3613 if (x & UHCI_PORTSC_CSC) 3614 change |= UPS_C_CONNECT_STATUS; 3615 if (x & UHCI_PORTSC_PE) 3616 status |= UPS_PORT_ENABLED; 3617 if (x & UHCI_PORTSC_POEDC) 3618 change |= UPS_C_PORT_ENABLED; 3619 if (x & UHCI_PORTSC_OCI) 3620 status |= UPS_OVERCURRENT_INDICATOR; 3621 if (x & UHCI_PORTSC_OCIC) 3622 change |= UPS_C_OVERCURRENT_INDICATOR; 3623 if (x & UHCI_PORTSC_SUSP) 3624 status |= UPS_SUSPEND; 3625 if (x & UHCI_PORTSC_LSDA) 3626 status |= UPS_LOW_SPEED; 3627 status |= UPS_PORT_POWER; 3628 if (sc->sc_isreset) 3629 change |= UPS_C_PORT_RESET; 3630 USETW(ps.wPortStatus, status); 3631 USETW(ps.wPortChange, change); 3632 totlen = min(len, sizeof(ps)); 3633 memcpy(buf, &ps, totlen); 3634 break; 3635 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3636 return -1; 3637 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3638 break; 3639 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3640 if (index == 1) 3641 port = UHCI_PORTSC1; 3642 else if (index == 2) 3643 port = UHCI_PORTSC2; 3644 else { 3645 return -1; 3646 } 3647 switch(value) { 3648 case UHF_PORT_ENABLE: 3649 x = URWMASK(UREAD2(sc, port)); 3650 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3651 break; 3652 case UHF_PORT_SUSPEND: 3653 x = URWMASK(UREAD2(sc, port)); 3654 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3655 break; 3656 case UHF_PORT_RESET: 3657 err = uhci_portreset(sc, index); 3658 if (err != USBD_NORMAL_COMPLETION) 3659 return -1; 3660 return 0; 3661 case UHF_PORT_POWER: 3662 /* Pretend we turned on power */ 3663 return 0; 3664 case UHF_C_PORT_CONNECTION: 3665 case UHF_C_PORT_ENABLE: 3666 case UHF_C_PORT_OVER_CURRENT: 3667 case UHF_PORT_CONNECTION: 3668 case UHF_PORT_OVER_CURRENT: 3669 case UHF_PORT_LOW_SPEED: 3670 case UHF_C_PORT_SUSPEND: 3671 case UHF_C_PORT_RESET: 3672 default: 3673 return -1; 3674 } 3675 break; 3676 default: 3677 /* default from usbroothub */ 3678 DPRINTF("returning %d (usbroothub default)", 3679 buflen, 0, 0, 0); 3680 return buflen; 3681 } 3682 3683 DPRINTF("returning %d", totlen, 0, 0, 0); 3684 3685 return totlen; 3686 } 3687 3688 /* Abort a root interrupt request. */ 3689 void 3690 uhci_root_intr_abort(struct usbd_xfer *xfer) 3691 { 3692 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3693 3694 KASSERT(mutex_owned(&sc->sc_lock)); 3695 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3696 3697 callout_stop(&sc->sc_poll_handle); 3698 sc->sc_intr_xfer = NULL; 3699 3700 xfer->ux_status = USBD_CANCELLED; 3701 #ifdef DIAGNOSTIC 3702 UHCI_XFER2UXFER(xfer)->isdone = 1; 3703 #endif 3704 usb_transfer_complete(xfer); 3705 } 3706 3707 usbd_status 3708 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3709 { 3710 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3711 usbd_status err; 3712 3713 /* Insert last in queue. */ 3714 mutex_enter(&sc->sc_lock); 3715 err = usb_insert_transfer(xfer); 3716 mutex_exit(&sc->sc_lock); 3717 if (err) 3718 return err; 3719 3720 /* 3721 * Pipe isn't running (otherwise err would be USBD_INPROG), 3722 * start first 3723 */ 3724 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3725 } 3726 3727 /* Start a transfer on the root interrupt pipe */ 3728 usbd_status 3729 uhci_root_intr_start(struct usbd_xfer *xfer) 3730 { 3731 struct usbd_pipe *pipe = xfer->ux_pipe; 3732 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3733 unsigned int ival; 3734 3735 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3736 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3737 xfer->ux_flags, 0); 3738 3739 if (sc->sc_dying) 3740 return USBD_IOERROR; 3741 3742 /* XXX temporary variable needed to avoid gcc3 warning */ 3743 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3744 sc->sc_ival = mstohz(ival); 3745 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3746 sc->sc_intr_xfer = xfer; 3747 return USBD_IN_PROGRESS; 3748 } 3749 3750 /* Close the root interrupt pipe. */ 3751 void 3752 uhci_root_intr_close(struct usbd_pipe *pipe) 3753 { 3754 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3755 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3756 3757 KASSERT(mutex_owned(&sc->sc_lock)); 3758 3759 callout_stop(&sc->sc_poll_handle); 3760 sc->sc_intr_xfer = NULL; 3761 } 3762
Indexes created Tue Sep 30 20:09:53 GMT 2025