uhci.c revision 1.264.4.40
1 /* $NetBSD: uhci.c,v 1.264.4.40 2015/10/27 14:22:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.40 2015/10/27 14:22:38 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Isochronous pipe */ 158 struct isoc { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } isoc; 162 }; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static usbd_status uhci_run(uhci_softc_t *, int, int); 169 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 170 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, 180 uhci_soft_td_t *, uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 182 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 183 uhci_soft_td_t **, uhci_soft_td_t **); 184 Static void uhci_poll_hub(void *); 185 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 186 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *); 187 Static void uhci_idone(struct uhci_xfer *); 188 189 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 190 191 Static void uhci_timeout(void *); 192 Static void uhci_timeout_task(void *); 193 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 194 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 195 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 197 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 198 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_add_loop(uhci_softc_t *); 200 Static void uhci_rem_loop(uhci_softc_t *); 201 202 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 203 Static void uhci_device_isoc_enter(struct usbd_xfer *); 204 205 Static struct usbd_xfer * 206 uhci_allocx(struct usbd_bus *, unsigned int); 207 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 208 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 209 Static int uhci_roothub_ctrl(struct usbd_bus *, 210 usb_device_request_t *, void *, int); 211 212 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 213 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 214 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 215 Static void uhci_device_ctrl_close(struct usbd_pipe *); 216 Static void uhci_device_ctrl_done(struct usbd_xfer *); 217 218 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 220 Static void uhci_device_intr_abort(struct usbd_xfer *); 221 Static void uhci_device_intr_close(struct usbd_pipe *); 222 Static void uhci_device_intr_done(struct usbd_xfer *); 223 224 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 225 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 226 Static void uhci_device_bulk_abort(struct usbd_xfer *); 227 Static void uhci_device_bulk_close(struct usbd_pipe *); 228 Static void uhci_device_bulk_done(struct usbd_xfer *); 229 230 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 231 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 232 Static void uhci_device_isoc_abort(struct usbd_xfer *); 233 Static void uhci_device_isoc_close(struct usbd_pipe *); 234 Static void uhci_device_isoc_done(struct usbd_xfer *); 235 236 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 238 Static void uhci_root_intr_abort(struct usbd_xfer *); 239 Static void uhci_root_intr_close(struct usbd_pipe *); 240 Static void uhci_root_intr_done(struct usbd_xfer *); 241 242 Static usbd_status uhci_open(struct usbd_pipe *); 243 Static void uhci_poll(struct usbd_bus *); 244 Static void uhci_softintr(void *); 245 246 Static usbd_status uhci_device_request(struct usbd_xfer *); 247 248 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 250 Static usbd_status uhci_device_setintr(uhci_softc_t *, 251 struct uhci_pipe *, int); 252 253 Static void uhci_device_clear_toggle(struct usbd_pipe *); 254 Static void uhci_noop(struct usbd_pipe *); 255 256 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 257 uhci_soft_qh_t *); 258 259 #ifdef UHCI_DEBUG 260 Static void uhci_dump_all(uhci_softc_t *); 261 Static void uhci_dumpregs(uhci_softc_t *); 262 Static void uhci_dump_qhs(uhci_soft_qh_t *); 263 Static void uhci_dump_qh(uhci_soft_qh_t *); 264 Static void uhci_dump_tds(uhci_soft_td_t *); 265 Static void uhci_dump_td(uhci_soft_td_t *); 266 Static void uhci_dump_ii(struct uhci_xfer *); 267 void uhci_dump(void); 268 #endif 269 270 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 271 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 272 #define UWRITE1(sc, r, x) \ 273 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 274 } while (/*CONSTCOND*/0) 275 #define UWRITE2(sc, r, x) \ 276 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 277 } while (/*CONSTCOND*/0) 278 #define UWRITE4(sc, r, x) \ 279 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 280 } while (/*CONSTCOND*/0) 281 static __inline uint8_t 282 UREAD1(uhci_softc_t *sc, bus_size_t r) 283 { 284 285 UBARR(sc); 286 return bus_space_read_1(sc->iot, sc->ioh, r); 287 } 288 289 static __inline uint16_t 290 UREAD2(uhci_softc_t *sc, bus_size_t r) 291 { 292 293 UBARR(sc); 294 return bus_space_read_2(sc->iot, sc->ioh, r); 295 } 296 297 #ifdef UHCI_DEBUG 298 static __inline uint32_t 299 UREAD4(uhci_softc_t *sc, bus_size_t r) 300 { 301 302 UBARR(sc); 303 return bus_space_read_4(sc->iot, sc->ioh, r); 304 } 305 #endif 306 307 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 308 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 309 310 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 311 312 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 313 314 const struct usbd_bus_methods uhci_bus_methods = { 315 .ubm_open = uhci_open, 316 .ubm_softint = uhci_softintr, 317 .ubm_dopoll = uhci_poll, 318 .ubm_allocx = uhci_allocx, 319 .ubm_freex = uhci_freex, 320 .ubm_getlock = uhci_get_lock, 321 .ubm_rhctrl = uhci_roothub_ctrl, 322 }; 323 324 const struct usbd_pipe_methods uhci_root_intr_methods = { 325 .upm_transfer = uhci_root_intr_transfer, 326 .upm_start = uhci_root_intr_start, 327 .upm_abort = uhci_root_intr_abort, 328 .upm_close = uhci_root_intr_close, 329 .upm_cleartoggle = uhci_noop, 330 .upm_done = uhci_root_intr_done, 331 }; 332 333 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 334 .upm_transfer = uhci_device_ctrl_transfer, 335 .upm_start = uhci_device_ctrl_start, 336 .upm_abort = uhci_device_ctrl_abort, 337 .upm_close = uhci_device_ctrl_close, 338 .upm_cleartoggle = uhci_noop, 339 .upm_done = uhci_device_ctrl_done, 340 }; 341 342 const struct usbd_pipe_methods uhci_device_intr_methods = { 343 .upm_transfer = uhci_device_intr_transfer, 344 .upm_start = uhci_device_intr_start, 345 .upm_abort = uhci_device_intr_abort, 346 .upm_close = uhci_device_intr_close, 347 .upm_cleartoggle = uhci_device_clear_toggle, 348 .upm_done = uhci_device_intr_done, 349 }; 350 351 const struct usbd_pipe_methods uhci_device_bulk_methods = { 352 .upm_transfer = uhci_device_bulk_transfer, 353 .upm_start = uhci_device_bulk_start, 354 .upm_abort = uhci_device_bulk_abort, 355 .upm_close = uhci_device_bulk_close, 356 .upm_cleartoggle = uhci_device_clear_toggle, 357 .upm_done = uhci_device_bulk_done, 358 }; 359 360 const struct usbd_pipe_methods uhci_device_isoc_methods = { 361 .upm_transfer = uhci_device_isoc_transfer, 362 .upm_start = uhci_device_isoc_start, 363 .upm_abort = uhci_device_isoc_abort, 364 .upm_close = uhci_device_isoc_close, 365 .upm_cleartoggle = uhci_noop, 366 .upm_done = uhci_device_isoc_done, 367 }; 368 369 #define uhci_add_intr_info(sc, ux) \ 370 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), list) 371 #define uhci_del_intr_info(sc, ux) \ 372 do { \ 373 TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), list); \ 374 (ux)->list.tqe_prev = NULL; \ 375 } while (0) 376 #define uhci_active_intr_info(ux) ((ux)->list.tqe_prev != NULL) 377 378 static inline uhci_soft_qh_t * 379 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 380 { 381 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 382 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 383 384 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 385 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 386 usb_syncmem(&pqh->dma, 387 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 388 sizeof(pqh->qh.qh_hlink), 389 BUS_DMASYNC_POSTWRITE); 390 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 391 printf("uhci_find_prev_qh: QH not found\n"); 392 return NULL; 393 } 394 #endif 395 } 396 return pqh; 397 } 398 399 void 400 uhci_globalreset(uhci_softc_t *sc) 401 { 402 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 403 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 404 UHCICMD(sc, 0); /* do nothing */ 405 } 406 407 int 408 uhci_init(uhci_softc_t *sc) 409 { 410 usbd_status err; 411 int i, j; 412 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 413 uhci_soft_td_t *std; 414 415 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 416 417 #ifdef UHCI_DEBUG 418 thesc = sc; 419 420 if (uhcidebug > 2) 421 uhci_dumpregs(sc); 422 #endif 423 424 sc->sc_suspend = PWR_RESUME; 425 426 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 427 uhci_globalreset(sc); /* reset the controller */ 428 uhci_reset(sc); 429 430 /* Allocate and initialize real frame array. */ 431 err = usb_allocmem(&sc->sc_bus, 432 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 433 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 434 if (err) 435 return err; 436 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 437 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 438 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 439 440 /* 441 * Allocate a TD, inactive, that hangs from the last QH. 442 * This is to avoid a bug in the PIIX that makes it run berserk 443 * otherwise. 444 */ 445 std = uhci_alloc_std(sc); 446 if (std == NULL) 447 return ENOMEM; 448 std->link.std = NULL; 449 std->td.td_link = htole32(UHCI_PTR_T); 450 std->td.td_status = htole32(0); /* inactive */ 451 std->td.td_token = htole32(0); 452 std->td.td_buffer = htole32(0); 453 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 454 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 455 456 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 457 lsqh = uhci_alloc_sqh(sc); 458 if (lsqh == NULL) 459 return ENOMEM; 460 lsqh->hlink = NULL; 461 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 462 lsqh->elink = std; 463 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 464 sc->sc_last_qh = lsqh; 465 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 467 468 /* Allocate the dummy QH where bulk traffic will be queued. */ 469 bsqh = uhci_alloc_sqh(sc); 470 if (bsqh == NULL) 471 return ENOMEM; 472 bsqh->hlink = lsqh; 473 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 474 bsqh->elink = NULL; 475 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 476 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 477 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 478 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 479 480 /* Allocate dummy QH where high speed control traffic will be queued. */ 481 chsqh = uhci_alloc_sqh(sc); 482 if (chsqh == NULL) 483 return ENOMEM; 484 chsqh->hlink = bsqh; 485 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 486 chsqh->elink = NULL; 487 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 488 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 489 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 490 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 491 492 /* Allocate dummy QH where control traffic will be queued. */ 493 clsqh = uhci_alloc_sqh(sc); 494 if (clsqh == NULL) 495 return ENOMEM; 496 clsqh->hlink = chsqh; 497 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 498 clsqh->elink = NULL; 499 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 500 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 501 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 504 /* 505 * Make all (virtual) frame list pointers point to the interrupt 506 * queue heads and the interrupt queue heads at the control 507 * queue head and point the physical frame list to the virtual. 508 */ 509 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 510 std = uhci_alloc_std(sc); 511 sqh = uhci_alloc_sqh(sc); 512 if (std == NULL || sqh == NULL) 513 return USBD_NOMEM; 514 std->link.sqh = sqh; 515 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 516 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 517 std->td.td_token = htole32(0); 518 std->td.td_buffer = htole32(0); 519 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 520 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 521 sqh->hlink = clsqh; 522 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 523 sqh->elink = NULL; 524 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 525 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 526 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 527 sc->sc_vframes[i].htd = std; 528 sc->sc_vframes[i].etd = std; 529 sc->sc_vframes[i].hqh = sqh; 530 sc->sc_vframes[i].eqh = sqh; 531 for (j = i; 532 j < UHCI_FRAMELIST_COUNT; 533 j += UHCI_VFRAMELIST_COUNT) 534 sc->sc_pframes[j] = htole32(std->physaddr); 535 } 536 usb_syncmem(&sc->sc_dma, 0, 537 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 538 BUS_DMASYNC_PREWRITE); 539 540 541 TAILQ_INIT(&sc->sc_intrhead); 542 543 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 544 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 545 546 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 547 548 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 549 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 550 cv_init(&sc->sc_softwake_cv, "uhciab"); 551 552 /* Set up the bus struct. */ 553 sc->sc_bus.ub_methods = &uhci_bus_methods; 554 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 555 sc->sc_bus.ub_usedma = true; 556 557 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 558 559 DPRINTF("Enabling...", 0, 0, 0, 0); 560 561 err = uhci_run(sc, 1, 0); /* and here we go... */ 562 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 563 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 564 return err; 565 } 566 567 int 568 uhci_activate(device_t self, enum devact act) 569 { 570 struct uhci_softc *sc = device_private(self); 571 572 switch (act) { 573 case DVACT_DEACTIVATE: 574 sc->sc_dying = 1; 575 return 0; 576 default: 577 return EOPNOTSUPP; 578 } 579 } 580 581 void 582 uhci_childdet(device_t self, device_t child) 583 { 584 struct uhci_softc *sc = device_private(self); 585 586 KASSERT(sc->sc_child == child); 587 sc->sc_child = NULL; 588 } 589 590 int 591 uhci_detach(struct uhci_softc *sc, int flags) 592 { 593 int rv = 0; 594 595 if (sc->sc_child != NULL) 596 rv = config_detach(sc->sc_child, flags); 597 598 if (rv != 0) 599 return rv; 600 601 callout_halt(&sc->sc_poll_handle, NULL); 602 callout_destroy(&sc->sc_poll_handle); 603 604 cv_destroy(&sc->sc_softwake_cv); 605 606 mutex_destroy(&sc->sc_lock); 607 mutex_destroy(&sc->sc_intr_lock); 608 609 pool_cache_destroy(sc->sc_xferpool); 610 611 /* XXX free other data structures XXX */ 612 613 return rv; 614 } 615 616 struct usbd_xfer * 617 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 618 { 619 struct uhci_softc *sc = UHCI_BUS2SC(bus); 620 struct usbd_xfer *xfer; 621 622 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 623 if (xfer != NULL) { 624 memset(xfer, 0, sizeof(struct uhci_xfer)); 625 626 #ifdef DIAGNOSTIC 627 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 628 uxfer->isdone = true; 629 xfer->ux_state = XFER_BUSY; 630 #endif 631 } 632 return xfer; 633 } 634 635 void 636 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 637 { 638 struct uhci_softc *sc = UHCI_BUS2SC(bus); 639 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 640 641 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 642 xfer->ux_state); 643 KASSERTMSG(uxfer->isdone, "xfer %p not done\n", xfer); 644 #ifdef DIAGNOSTIC 645 xfer->ux_state = XFER_FREE; 646 #endif 647 pool_cache_put(sc->sc_xferpool, xfer); 648 } 649 650 Static void 651 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 652 { 653 struct uhci_softc *sc = UHCI_BUS2SC(bus); 654 655 *lock = &sc->sc_lock; 656 } 657 658 659 /* 660 * Handle suspend/resume. 661 * 662 * We need to switch to polling mode here, because this routine is 663 * called from an interrupt context. This is all right since we 664 * are almost suspended anyway. 665 */ 666 bool 667 uhci_resume(device_t dv, const pmf_qual_t *qual) 668 { 669 uhci_softc_t *sc = device_private(dv); 670 int cmd; 671 672 mutex_spin_enter(&sc->sc_intr_lock); 673 674 cmd = UREAD2(sc, UHCI_CMD); 675 sc->sc_bus.ub_usepolling++; 676 UWRITE2(sc, UHCI_INTR, 0); 677 uhci_globalreset(sc); 678 uhci_reset(sc); 679 if (cmd & UHCI_CMD_RS) 680 uhci_run(sc, 0, 1); 681 682 /* restore saved state */ 683 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 684 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 685 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 686 687 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 688 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 689 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 690 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 691 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 692 UHCICMD(sc, UHCI_CMD_MAXP); 693 uhci_run(sc, 1, 1); /* and start traffic again */ 694 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 695 sc->sc_bus.ub_usepolling--; 696 if (sc->sc_intr_xfer != NULL) 697 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 698 sc->sc_intr_xfer); 699 #ifdef UHCI_DEBUG 700 if (uhcidebug > 2) 701 uhci_dumpregs(sc); 702 #endif 703 704 sc->sc_suspend = PWR_RESUME; 705 mutex_spin_exit(&sc->sc_intr_lock); 706 707 return true; 708 } 709 710 bool 711 uhci_suspend(device_t dv, const pmf_qual_t *qual) 712 { 713 uhci_softc_t *sc = device_private(dv); 714 int cmd; 715 716 mutex_spin_enter(&sc->sc_intr_lock); 717 718 cmd = UREAD2(sc, UHCI_CMD); 719 720 #ifdef UHCI_DEBUG 721 if (uhcidebug > 2) 722 uhci_dumpregs(sc); 723 #endif 724 if (sc->sc_intr_xfer != NULL) 725 callout_stop(&sc->sc_poll_handle); 726 sc->sc_suspend = PWR_SUSPEND; 727 sc->sc_bus.ub_usepolling++; 728 729 uhci_run(sc, 0, 1); /* stop the controller */ 730 cmd &= ~UHCI_CMD_RS; 731 732 /* save some state if BIOS doesn't */ 733 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 734 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 735 736 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 737 738 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 739 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 740 sc->sc_bus.ub_usepolling--; 741 742 mutex_spin_exit(&sc->sc_intr_lock); 743 744 return true; 745 } 746 747 #ifdef UHCI_DEBUG 748 Static void 749 uhci_dumpregs(uhci_softc_t *sc) 750 { 751 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 752 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 753 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 754 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 755 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 756 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 757 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 758 } 759 760 void 761 uhci_dump_td(uhci_soft_td_t *p) 762 { 763 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 764 765 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 766 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 767 768 DPRINTF("TD(%p) at %08x", p, p->physaddr, 0, 0); 769 DPRINTF(" link=0x%08x status=0x%08x " 770 "token=0x%08x buffer=0x%08x", 771 le32toh(p->td.td_link), 772 le32toh(p->td.td_status), 773 le32toh(p->td.td_token), 774 le32toh(p->td.td_buffer)); 775 776 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 777 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 778 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 779 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 780 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 781 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 782 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 783 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 784 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 785 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 786 DPRINTF("ios =%d ls =%d spd =%d", 787 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 788 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 789 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 790 DPRINTF("errcnt =%d actlen =%d pid=%02x", 791 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 792 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 793 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 794 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 795 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 796 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 797 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 798 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 799 } 800 801 void 802 uhci_dump_qh(uhci_soft_qh_t *sqh) 803 { 804 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 805 806 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 807 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 808 809 DPRINTF("QH(%p) at %08x: hlink=%08x elink=%08x", sqh, 810 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 811 le32toh(sqh->qh.qh_elink)); 812 813 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 814 } 815 816 817 #if 1 818 void 819 uhci_dump(void) 820 { 821 uhci_dump_all(thesc); 822 } 823 #endif 824 825 void 826 uhci_dump_all(uhci_softc_t *sc) 827 { 828 uhci_dumpregs(sc); 829 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 830 uhci_dump_qhs(sc->sc_lctl_start); 831 } 832 833 834 void 835 uhci_dump_qhs(uhci_soft_qh_t *sqh) 836 { 837 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 838 839 uhci_dump_qh(sqh); 840 841 /* 842 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 843 * Traverses sideways first, then down. 844 * 845 * QH1 846 * QH2 847 * No QH 848 * TD2.1 849 * TD2.2 850 * TD1.1 851 * etc. 852 * 853 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 854 */ 855 856 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 857 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 858 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 859 uhci_dump_qhs(sqh->hlink); 860 else 861 DPRINTF("No QH", 0, 0, 0, 0); 862 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 863 864 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 865 uhci_dump_tds(sqh->elink); 866 else 867 DPRINTF("No QH", 0, 0, 0, 0); 868 } 869 870 void 871 uhci_dump_tds(uhci_soft_td_t *std) 872 { 873 uhci_soft_td_t *td; 874 int stop; 875 876 for (td = std; td != NULL; td = td->link.std) { 877 uhci_dump_td(td); 878 879 /* 880 * Check whether the link pointer in this TD marks 881 * the link pointer as end of queue. This avoids 882 * printing the free list in case the queue/TD has 883 * already been moved there (seatbelt). 884 */ 885 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 886 sizeof(td->td.td_link), 887 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 888 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 889 le32toh(td->td.td_link) == 0); 890 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 891 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 892 if (stop) 893 break; 894 } 895 } 896 897 Static void 898 uhci_dump_ii(struct uhci_xfer *ux) 899 { 900 struct usbd_pipe *pipe; 901 usb_endpoint_descriptor_t *ed; 902 struct usbd_device *dev; 903 904 if (ux == NULL) { 905 printf("ux NULL\n"); 906 return; 907 } 908 pipe = ux->xfer.ux_pipe; 909 if (pipe == NULL) { 910 printf("ux %p: done=%d pipe=NULL\n", ux, ux->isdone); 911 return; 912 } 913 if (pipe->up_endpoint == NULL) { 914 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 915 ux, ux->isdone, pipe); 916 return; 917 } 918 if (pipe->up_dev == NULL) { 919 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 920 ux, ux->isdone, pipe); 921 return; 922 } 923 ed = pipe->up_endpoint->ue_edesc; 924 dev = pipe->up_dev; 925 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 926 ux, ux->isdone, dev, 927 UGETW(dev->ud_ddesc.idVendor), 928 UGETW(dev->ud_ddesc.idProduct), 929 dev->ud_addr, pipe, 930 ed->bEndpointAddress, ed->bmAttributes); 931 } 932 933 void uhci_dump_iis(struct uhci_softc *sc); 934 void 935 uhci_dump_iis(struct uhci_softc *sc) 936 { 937 struct uhci_xfer *ux; 938 939 printf("interrupt list:\n"); 940 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = TAILQ_NEXT(ux, list)) 941 uhci_dump_ii(ux); 942 } 943 944 void iidump(void); 945 void iidump(void) { uhci_dump_iis(thesc); } 946 947 #endif 948 949 /* 950 * This routine is executed periodically and simulates interrupts 951 * from the root controller interrupt pipe for port status change. 952 */ 953 void 954 uhci_poll_hub(void *addr) 955 { 956 struct usbd_xfer *xfer = addr; 957 struct usbd_pipe *pipe = xfer->ux_pipe; 958 uhci_softc_t *sc; 959 u_char *p; 960 961 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 962 963 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 964 return; /* device has detached */ 965 sc = UHCI_PIPE2SC(pipe); 966 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 967 968 p = xfer->ux_buf; 969 p[0] = 0; 970 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 971 p[0] |= 1<<1; 972 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 973 p[0] |= 1<<2; 974 if (p[0] == 0) 975 /* No change, try again in a while */ 976 return; 977 978 xfer->ux_actlen = 1; 979 xfer->ux_status = USBD_NORMAL_COMPLETION; 980 mutex_enter(&sc->sc_lock); 981 usb_transfer_complete(xfer); 982 mutex_exit(&sc->sc_lock); 983 } 984 985 void 986 uhci_root_intr_done(struct usbd_xfer *xfer) 987 { 988 } 989 990 /* 991 * Let the last QH loop back to the high speed control transfer QH. 992 * This is what intel calls "bandwidth reclamation" and improves 993 * USB performance a lot for some devices. 994 * If we are already looping, just count it. 995 */ 996 void 997 uhci_add_loop(uhci_softc_t *sc) 998 { 999 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1000 1001 #ifdef UHCI_DEBUG 1002 if (uhcinoloop) 1003 return; 1004 #endif 1005 if (++sc->sc_loops == 1) { 1006 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1007 /* Note, we don't loop back the soft pointer. */ 1008 sc->sc_last_qh->qh.qh_hlink = 1009 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1010 usb_syncmem(&sc->sc_last_qh->dma, 1011 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1012 sizeof(sc->sc_last_qh->qh.qh_hlink), 1013 BUS_DMASYNC_PREWRITE); 1014 } 1015 } 1016 1017 void 1018 uhci_rem_loop(uhci_softc_t *sc) 1019 { 1020 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1021 1022 #ifdef UHCI_DEBUG 1023 if (uhcinoloop) 1024 return; 1025 #endif 1026 if (--sc->sc_loops == 0) { 1027 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1028 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1029 usb_syncmem(&sc->sc_last_qh->dma, 1030 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1031 sizeof(sc->sc_last_qh->qh.qh_hlink), 1032 BUS_DMASYNC_PREWRITE); 1033 } 1034 } 1035 1036 /* Add high speed control QH, called with lock held. */ 1037 void 1038 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1039 { 1040 uhci_soft_qh_t *eqh; 1041 1042 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1043 1044 KASSERT(mutex_owned(&sc->sc_lock)); 1045 1046 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1047 eqh = sc->sc_hctl_end; 1048 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1049 sizeof(eqh->qh.qh_hlink), 1050 BUS_DMASYNC_POSTWRITE); 1051 sqh->hlink = eqh->hlink; 1052 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1053 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1054 BUS_DMASYNC_PREWRITE); 1055 eqh->hlink = sqh; 1056 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1057 sc->sc_hctl_end = sqh; 1058 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1059 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1060 #ifdef UHCI_CTL_LOOP 1061 uhci_add_loop(sc); 1062 #endif 1063 } 1064 1065 /* Remove high speed control QH, called with lock held. */ 1066 void 1067 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1068 { 1069 uhci_soft_qh_t *pqh; 1070 uint32_t elink; 1071 1072 KASSERT(mutex_owned(&sc->sc_lock)); 1073 1074 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1075 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1076 #ifdef UHCI_CTL_LOOP 1077 uhci_rem_loop(sc); 1078 #endif 1079 /* 1080 * The T bit should be set in the elink of the QH so that the HC 1081 * doesn't follow the pointer. This condition may fail if the 1082 * the transferred packet was short so that the QH still points 1083 * at the last used TD. 1084 * In this case we set the T bit and wait a little for the HC 1085 * to stop looking at the TD. 1086 * Note that if the TD chain is large enough, the controller 1087 * may still be looking at the chain at the end of this function. 1088 * uhci_free_std_chain() will make sure the controller stops 1089 * looking at it quickly, but until then we should not change 1090 * sqh->hlink. 1091 */ 1092 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1093 sizeof(sqh->qh.qh_elink), 1094 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1095 elink = le32toh(sqh->qh.qh_elink); 1096 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1097 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1098 if (!(elink & UHCI_PTR_T)) { 1099 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1100 usb_syncmem(&sqh->dma, 1101 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1102 sizeof(sqh->qh.qh_elink), 1103 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1104 delay(UHCI_QH_REMOVE_DELAY); 1105 } 1106 1107 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1108 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1109 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1110 pqh->hlink = sqh->hlink; 1111 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1112 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1113 sizeof(pqh->qh.qh_hlink), 1114 BUS_DMASYNC_PREWRITE); 1115 delay(UHCI_QH_REMOVE_DELAY); 1116 if (sc->sc_hctl_end == sqh) 1117 sc->sc_hctl_end = pqh; 1118 } 1119 1120 /* Add low speed control QH, called with lock held. */ 1121 void 1122 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1123 { 1124 uhci_soft_qh_t *eqh; 1125 1126 KASSERT(mutex_owned(&sc->sc_lock)); 1127 1128 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1129 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1130 1131 eqh = sc->sc_lctl_end; 1132 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1133 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1134 sqh->hlink = eqh->hlink; 1135 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1136 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1137 BUS_DMASYNC_PREWRITE); 1138 eqh->hlink = sqh; 1139 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1140 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1141 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1142 sc->sc_lctl_end = sqh; 1143 } 1144 1145 /* Remove low speed control QH, called with lock held. */ 1146 void 1147 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1148 { 1149 uhci_soft_qh_t *pqh; 1150 uint32_t elink; 1151 1152 KASSERT(mutex_owned(&sc->sc_lock)); 1153 1154 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1155 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1156 1157 /* See comment in uhci_remove_hs_ctrl() */ 1158 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1159 sizeof(sqh->qh.qh_elink), 1160 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1161 elink = le32toh(sqh->qh.qh_elink); 1162 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1163 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1164 if (!(elink & UHCI_PTR_T)) { 1165 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1166 usb_syncmem(&sqh->dma, 1167 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1168 sizeof(sqh->qh.qh_elink), 1169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1170 delay(UHCI_QH_REMOVE_DELAY); 1171 } 1172 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1173 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1174 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1175 pqh->hlink = sqh->hlink; 1176 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1177 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1178 sizeof(pqh->qh.qh_hlink), 1179 BUS_DMASYNC_PREWRITE); 1180 delay(UHCI_QH_REMOVE_DELAY); 1181 if (sc->sc_lctl_end == sqh) 1182 sc->sc_lctl_end = pqh; 1183 } 1184 1185 /* Add bulk QH, called with lock held. */ 1186 void 1187 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1188 { 1189 uhci_soft_qh_t *eqh; 1190 1191 KASSERT(mutex_owned(&sc->sc_lock)); 1192 1193 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1194 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1195 1196 eqh = sc->sc_bulk_end; 1197 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1198 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1199 sqh->hlink = eqh->hlink; 1200 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1201 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1202 BUS_DMASYNC_PREWRITE); 1203 eqh->hlink = sqh; 1204 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1205 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1206 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1207 sc->sc_bulk_end = sqh; 1208 uhci_add_loop(sc); 1209 } 1210 1211 /* Remove bulk QH, called with lock held. */ 1212 void 1213 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1214 { 1215 uhci_soft_qh_t *pqh; 1216 1217 KASSERT(mutex_owned(&sc->sc_lock)); 1218 1219 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1220 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1221 1222 uhci_rem_loop(sc); 1223 /* See comment in uhci_remove_hs_ctrl() */ 1224 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1225 sizeof(sqh->qh.qh_elink), 1226 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1227 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1228 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1229 usb_syncmem(&sqh->dma, 1230 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1231 sizeof(sqh->qh.qh_elink), 1232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1233 delay(UHCI_QH_REMOVE_DELAY); 1234 } 1235 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1236 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1237 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1238 pqh->hlink = sqh->hlink; 1239 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1240 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1241 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1242 delay(UHCI_QH_REMOVE_DELAY); 1243 if (sc->sc_bulk_end == sqh) 1244 sc->sc_bulk_end = pqh; 1245 } 1246 1247 Static int uhci_intr1(uhci_softc_t *); 1248 1249 int 1250 uhci_intr(void *arg) 1251 { 1252 uhci_softc_t *sc = arg; 1253 int ret = 0; 1254 1255 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1256 1257 mutex_spin_enter(&sc->sc_intr_lock); 1258 1259 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1260 goto done; 1261 1262 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1263 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1264 goto done; 1265 } 1266 1267 ret = uhci_intr1(sc); 1268 1269 done: 1270 mutex_spin_exit(&sc->sc_intr_lock); 1271 return ret; 1272 } 1273 1274 int 1275 uhci_intr1(uhci_softc_t *sc) 1276 { 1277 int status; 1278 int ack; 1279 1280 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1281 1282 #ifdef UHCI_DEBUG 1283 if (uhcidebug > 15) { 1284 DPRINTF("sc %p", sc, 0, 0, 0); 1285 uhci_dumpregs(sc); 1286 } 1287 #endif 1288 1289 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1290 1291 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1292 if (status == 0) /* The interrupt was not for us. */ 1293 return 0; 1294 1295 if (sc->sc_suspend != PWR_RESUME) { 1296 #ifdef DIAGNOSTIC 1297 printf("%s: interrupt while not operating ignored\n", 1298 device_xname(sc->sc_dev)); 1299 #endif 1300 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1301 return 0; 1302 } 1303 1304 ack = 0; 1305 if (status & UHCI_STS_USBINT) 1306 ack |= UHCI_STS_USBINT; 1307 if (status & UHCI_STS_USBEI) 1308 ack |= UHCI_STS_USBEI; 1309 if (status & UHCI_STS_RD) { 1310 ack |= UHCI_STS_RD; 1311 #ifdef UHCI_DEBUG 1312 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1313 #endif 1314 } 1315 if (status & UHCI_STS_HSE) { 1316 ack |= UHCI_STS_HSE; 1317 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1318 } 1319 if (status & UHCI_STS_HCPE) { 1320 ack |= UHCI_STS_HCPE; 1321 printf("%s: host controller process error\n", 1322 device_xname(sc->sc_dev)); 1323 } 1324 1325 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1326 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1327 /* no acknowledge needed */ 1328 if (!sc->sc_dying) { 1329 printf("%s: host controller halted\n", 1330 device_xname(sc->sc_dev)); 1331 #ifdef UHCI_DEBUG 1332 uhci_dump_all(sc); 1333 #endif 1334 } 1335 sc->sc_dying = 1; 1336 } 1337 1338 if (!ack) 1339 return 0; /* nothing to acknowledge */ 1340 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1341 1342 usb_schedsoftintr(&sc->sc_bus); 1343 1344 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1345 1346 return 1; 1347 } 1348 1349 void 1350 uhci_softintr(void *v) 1351 { 1352 struct usbd_bus *bus = v; 1353 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1354 struct uhci_xfer *ux, *nextux; 1355 1356 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1357 DPRINTF("sc %p", sc, 0, 0, 0); 1358 1359 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1360 1361 /* 1362 * Interrupts on UHCI really suck. When the host controller 1363 * interrupts because a transfer is completed there is no 1364 * way of knowing which transfer it was. You can scan down 1365 * the TDs and QHs of the previous frame to limit the search, 1366 * but that assumes that the interrupt was not delayed by more 1367 * than 1 ms, which may not always be true (e.g. after debug 1368 * output on a slow console). 1369 * We scan all interrupt descriptors to see if any have 1370 * completed. 1371 */ 1372 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) { 1373 nextux = TAILQ_NEXT(ux, list); 1374 uhci_check_intr(sc, ux); 1375 } 1376 1377 if (sc->sc_softwake) { 1378 sc->sc_softwake = 0; 1379 cv_broadcast(&sc->sc_softwake_cv); 1380 } 1381 } 1382 1383 /* Check for an interrupt. */ 1384 void 1385 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux) 1386 { 1387 uhci_soft_td_t *std, *lstd; 1388 uint32_t status; 1389 1390 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1391 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1392 1393 KASSERT(ux != NULL); 1394 1395 struct usbd_xfer *xfer = &ux->xfer; 1396 if (xfer->ux_status == USBD_CANCELLED || 1397 xfer->ux_status == USBD_TIMEOUT) { 1398 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1399 return; 1400 } 1401 1402 if (ux->stdstart == NULL) 1403 return; 1404 lstd = ux->stdend; 1405 1406 KASSERT(lstd != NULL); 1407 1408 usb_syncmem(&lstd->dma, 1409 lstd->offs + offsetof(uhci_td_t, td_status), 1410 sizeof(lstd->td.td_status), 1411 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1412 status = le32toh(lstd->td.td_status); 1413 usb_syncmem(&lstd->dma, 1414 lstd->offs + offsetof(uhci_td_t, td_status), 1415 sizeof(lstd->td.td_status), 1416 BUS_DMASYNC_PREREAD); 1417 1418 /* If the last TD is not marked active we can complete */ 1419 if (!(status & UHCI_TD_ACTIVE)) { 1420 done: 1421 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1422 1423 callout_stop(&xfer->ux_callout); 1424 uhci_idone(ux); 1425 return; 1426 } 1427 1428 /* 1429 * If the last TD is still active we need to check whether there 1430 * is an error somewhere in the middle, or whether there was a 1431 * short packet (SPD and not ACTIVE). 1432 */ 1433 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1434 for (std = ux->stdstart; std != lstd; std = std->link.std) { 1435 usb_syncmem(&std->dma, 1436 std->offs + offsetof(uhci_td_t, td_status), 1437 sizeof(std->td.td_status), 1438 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1439 status = le32toh(std->td.td_status); 1440 usb_syncmem(&std->dma, 1441 std->offs + offsetof(uhci_td_t, td_status), 1442 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1443 1444 /* If there's an active TD the xfer isn't done. */ 1445 if (status & UHCI_TD_ACTIVE) { 1446 DPRINTFN(12, "ux=%p std=%p still active", 1447 ux, std, 0, 0); 1448 return; 1449 } 1450 1451 /* Any kind of error makes the xfer done. */ 1452 if (status & UHCI_TD_STALLED) 1453 goto done; 1454 1455 /* 1456 * If the data phase of a control transfer is short, we need 1457 * to complete the status stage 1458 */ 1459 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1460 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1461 1462 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1463 struct uhci_pipe *upipe = 1464 (struct uhci_pipe *)xfer->ux_pipe; 1465 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1466 uhci_soft_td_t *stat = upipe->ctrl.stat; 1467 1468 DPRINTFN(12, "ux=%p std=%p control status" 1469 "phase needs completion", ux, ux->stdstart, 0, 0); 1470 1471 sqh->qh.qh_elink = 1472 htole32(stat->physaddr | UHCI_PTR_TD); 1473 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1474 BUS_DMASYNC_PREWRITE); 1475 break; 1476 } 1477 1478 /* We want short packets, and it is short: it's done */ 1479 usb_syncmem(&std->dma, 1480 std->offs + offsetof(uhci_td_t, td_token), 1481 sizeof(std->td.td_token), 1482 BUS_DMASYNC_POSTWRITE); 1483 1484 if ((status & UHCI_TD_SPD) && 1485 UHCI_TD_GET_ACTLEN(status) < 1486 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1487 goto done; 1488 } 1489 } 1490 } 1491 1492 /* Called with USB lock held. */ 1493 void 1494 uhci_idone(struct uhci_xfer *ux) 1495 { 1496 struct usbd_xfer *xfer = &ux->xfer; 1497 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1498 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1499 uhci_soft_td_t *std; 1500 uint32_t status = 0, nstatus; 1501 int actlen; 1502 1503 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1504 1505 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1506 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1507 1508 #ifdef DIAGNOSTIC 1509 #ifdef UHCI_DEBUG 1510 if (ux->isdone) { 1511 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1512 uhci_dump_ii(ux); 1513 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1514 } 1515 #endif 1516 KASSERT(!ux->isdone); 1517 ux->isdone = true; 1518 #endif 1519 1520 if (xfer->ux_nframes != 0) { 1521 /* Isoc transfer, do things differently. */ 1522 uhci_soft_td_t **stds = upipe->isoc.stds; 1523 int i, n, nframes, len; 1524 1525 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1526 1527 nframes = xfer->ux_nframes; 1528 actlen = 0; 1529 n = UHCI_XFER2UXFER(xfer)->curframe; 1530 for (i = 0; i < nframes; i++) { 1531 std = stds[n]; 1532 #ifdef UHCI_DEBUG 1533 if (uhcidebug > 5) { 1534 DPRINTF("isoc TD %d", i, 0, 0, 0); 1535 uhci_dump_td(std); 1536 } 1537 #endif 1538 if (++n >= UHCI_VFRAMELIST_COUNT) 1539 n = 0; 1540 usb_syncmem(&std->dma, 1541 std->offs + offsetof(uhci_td_t, td_status), 1542 sizeof(std->td.td_status), 1543 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1544 status = le32toh(std->td.td_status); 1545 len = UHCI_TD_GET_ACTLEN(status); 1546 xfer->ux_frlengths[i] = len; 1547 actlen += len; 1548 } 1549 upipe->isoc.inuse -= nframes; 1550 xfer->ux_actlen = actlen; 1551 xfer->ux_status = USBD_NORMAL_COMPLETION; 1552 goto end; 1553 } 1554 1555 #ifdef UHCI_DEBUG 1556 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", 1557 ux, xfer, upipe, 0); 1558 if (uhcidebug > 10) 1559 uhci_dump_tds(ux->stdstart); 1560 #endif 1561 1562 /* The transfer is done, compute actual length and status. */ 1563 actlen = 0; 1564 for (std = ux->stdstart; std != NULL; std = std->link.std) { 1565 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1566 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1567 nstatus = le32toh(std->td.td_status); 1568 if (nstatus & UHCI_TD_ACTIVE) 1569 break; 1570 1571 status = nstatus; 1572 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1573 UHCI_TD_PID_SETUP) 1574 actlen += UHCI_TD_GET_ACTLEN(status); 1575 else { 1576 /* 1577 * UHCI will report CRCTO in addition to a STALL or NAK 1578 * for a SETUP transaction. See section 3.2.2, "TD 1579 * CONTROL AND STATUS". 1580 */ 1581 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1582 status &= ~UHCI_TD_CRCTO; 1583 } 1584 } 1585 /* If there are left over TDs we need to update the toggle. */ 1586 if (std != NULL) 1587 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1588 1589 status &= UHCI_TD_ERROR; 1590 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1591 xfer->ux_actlen = actlen; 1592 if (status != 0) { 1593 1594 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1595 "error, addr=%d, endpt=0x%02x", 1596 xfer->ux_pipe->up_dev->ud_addr, 1597 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1598 0, 0); 1599 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1600 "bitstuff=%d crcto =%d nak =%d babble =%d", 1601 status & UHCI_TD_BITSTUFF, 1602 status & UHCI_TD_CRCTO, 1603 status & UHCI_TD_NAK, 1604 status & UHCI_TD_BABBLE); 1605 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1606 "dbuffer =%d stalled =%d active =%d", 1607 status & UHCI_TD_DBUFFER, 1608 status & UHCI_TD_STALLED, 1609 status & UHCI_TD_ACTIVE, 1610 0); 1611 1612 if (status == UHCI_TD_STALLED) 1613 xfer->ux_status = USBD_STALLED; 1614 else 1615 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1616 } else { 1617 xfer->ux_status = USBD_NORMAL_COMPLETION; 1618 } 1619 1620 end: 1621 usb_transfer_complete(xfer); 1622 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1623 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1624 } 1625 1626 /* 1627 * Called when a request does not complete. 1628 */ 1629 void 1630 uhci_timeout(void *addr) 1631 { 1632 struct usbd_xfer *xfer = addr; 1633 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1634 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1635 1636 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1637 1638 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1639 1640 if (sc->sc_dying) { 1641 mutex_enter(&sc->sc_lock); 1642 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1643 mutex_exit(&sc->sc_lock); 1644 return; 1645 } 1646 1647 /* Execute the abort in a process context. */ 1648 usb_init_task(&uxfer->abort_task, uhci_timeout_task, xfer, 1649 USB_TASKQ_MPSAFE); 1650 usb_add_task(uxfer->xfer.ux_pipe->up_dev, &uxfer->abort_task, 1651 USB_TASKQ_HC); 1652 } 1653 1654 void 1655 uhci_timeout_task(void *addr) 1656 { 1657 struct usbd_xfer *xfer = addr; 1658 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1659 1660 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1661 1662 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1663 1664 mutex_enter(&sc->sc_lock); 1665 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1666 mutex_exit(&sc->sc_lock); 1667 } 1668 1669 /* 1670 * Wait here until controller claims to have an interrupt. 1671 * Then call uhci_intr and return. Use timeout to avoid waiting 1672 * too long. 1673 * Only used during boot when interrupts are not enabled yet. 1674 */ 1675 void 1676 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1677 { 1678 int timo = xfer->ux_timeout; 1679 struct uhci_xfer *ux; 1680 1681 mutex_enter(&sc->sc_lock); 1682 1683 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1684 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1685 1686 xfer->ux_status = USBD_IN_PROGRESS; 1687 for (; timo >= 0; timo--) { 1688 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1689 DPRINTFN(20, "0x%04x", 1690 UREAD2(sc, UHCI_STS), 0, 0, 0); 1691 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1692 mutex_spin_enter(&sc->sc_intr_lock); 1693 uhci_intr1(sc); 1694 mutex_spin_exit(&sc->sc_intr_lock); 1695 if (xfer->ux_status != USBD_IN_PROGRESS) 1696 goto done; 1697 } 1698 } 1699 1700 /* Timeout */ 1701 DPRINTF("timeout", 0, 0, 0, 0); 1702 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux != NULL; 1703 ux = TAILQ_NEXT(ux, list)) 1704 if (&ux->xfer == xfer) 1705 break; 1706 1707 KASSERT(ux != NULL); 1708 1709 uhci_idone(ux); 1710 1711 done: 1712 mutex_exit(&sc->sc_lock); 1713 } 1714 1715 void 1716 uhci_poll(struct usbd_bus *bus) 1717 { 1718 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1719 1720 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1721 mutex_spin_enter(&sc->sc_intr_lock); 1722 uhci_intr1(sc); 1723 mutex_spin_exit(&sc->sc_intr_lock); 1724 } 1725 } 1726 1727 void 1728 uhci_reset(uhci_softc_t *sc) 1729 { 1730 int n; 1731 1732 UHCICMD(sc, UHCI_CMD_HCRESET); 1733 /* The reset bit goes low when the controller is done. */ 1734 for (n = 0; n < UHCI_RESET_TIMEOUT && 1735 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1736 usb_delay_ms(&sc->sc_bus, 1); 1737 if (n >= UHCI_RESET_TIMEOUT) 1738 printf("%s: controller did not reset\n", 1739 device_xname(sc->sc_dev)); 1740 } 1741 1742 usbd_status 1743 uhci_run(uhci_softc_t *sc, int run, int locked) 1744 { 1745 int n, running; 1746 uint16_t cmd; 1747 1748 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1749 1750 run = run != 0; 1751 if (!locked) 1752 mutex_spin_enter(&sc->sc_intr_lock); 1753 1754 DPRINTF("setting run=%d", run, 0, 0, 0); 1755 cmd = UREAD2(sc, UHCI_CMD); 1756 if (run) 1757 cmd |= UHCI_CMD_RS; 1758 else 1759 cmd &= ~UHCI_CMD_RS; 1760 UHCICMD(sc, cmd); 1761 for(n = 0; n < 10; n++) { 1762 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1763 /* return when we've entered the state we want */ 1764 if (run == running) { 1765 if (!locked) 1766 mutex_spin_exit(&sc->sc_intr_lock); 1767 DPRINTF("done cmd=0x%x sts=0x%x", 1768 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1769 return USBD_NORMAL_COMPLETION; 1770 } 1771 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1772 } 1773 if (!locked) 1774 mutex_spin_exit(&sc->sc_intr_lock); 1775 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1776 run ? "start" : "stop"); 1777 return USBD_IOERROR; 1778 } 1779 1780 /* 1781 * Memory management routines. 1782 * uhci_alloc_std allocates TDs 1783 * uhci_alloc_sqh allocates QHs 1784 * These two routines do their own free list management, 1785 * partly for speed, partly because allocating DMAable memory 1786 * has page size granularity so much memory would be wasted if 1787 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1788 */ 1789 1790 uhci_soft_td_t * 1791 uhci_alloc_std(uhci_softc_t *sc) 1792 { 1793 uhci_soft_td_t *std; 1794 usbd_status err; 1795 int i, offs; 1796 usb_dma_t dma; 1797 1798 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1799 1800 if (sc->sc_freetds == NULL) { 1801 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1802 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1803 UHCI_TD_ALIGN, &dma); 1804 if (err) 1805 return 0; 1806 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1807 offs = i * UHCI_STD_SIZE; 1808 std = KERNADDR(&dma, offs); 1809 std->physaddr = DMAADDR(&dma, offs); 1810 std->dma = dma; 1811 std->offs = offs; 1812 std->link.std = sc->sc_freetds; 1813 sc->sc_freetds = std; 1814 } 1815 } 1816 std = sc->sc_freetds; 1817 sc->sc_freetds = std->link.std; 1818 memset(&std->td, 0, sizeof(uhci_td_t)); 1819 return std; 1820 } 1821 1822 void 1823 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1824 { 1825 #ifdef DIAGNOSTIC 1826 #define TD_IS_FREE 0x12345678 1827 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1828 printf("uhci_free_std: freeing free TD %p\n", std); 1829 return; 1830 } 1831 std->td.td_token = htole32(TD_IS_FREE); 1832 #endif 1833 std->link.std = sc->sc_freetds; 1834 sc->sc_freetds = std; 1835 } 1836 1837 uhci_soft_qh_t * 1838 uhci_alloc_sqh(uhci_softc_t *sc) 1839 { 1840 uhci_soft_qh_t *sqh; 1841 usbd_status err; 1842 int i, offs; 1843 usb_dma_t dma; 1844 1845 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1846 1847 if (sc->sc_freeqhs == NULL) { 1848 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1849 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1850 UHCI_QH_ALIGN, &dma); 1851 if (err) 1852 return 0; 1853 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1854 offs = i * UHCI_SQH_SIZE; 1855 sqh = KERNADDR(&dma, offs); 1856 sqh->physaddr = DMAADDR(&dma, offs); 1857 sqh->dma = dma; 1858 sqh->offs = offs; 1859 sqh->hlink = sc->sc_freeqhs; 1860 sc->sc_freeqhs = sqh; 1861 } 1862 } 1863 sqh = sc->sc_freeqhs; 1864 sc->sc_freeqhs = sqh->hlink; 1865 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1866 return sqh; 1867 } 1868 1869 void 1870 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1871 { 1872 sqh->hlink = sc->sc_freeqhs; 1873 sc->sc_freeqhs = sqh; 1874 } 1875 1876 void 1877 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1878 uhci_soft_td_t *stdend) 1879 { 1880 uhci_soft_td_t *p; 1881 uint32_t td_link; 1882 1883 /* 1884 * to avoid race condition with the controller which may be looking 1885 * at this chain, we need to first invalidate all links, and 1886 * then wait for the controller to move to another queue 1887 */ 1888 for (p = std; p != stdend; p = p->link.std) { 1889 usb_syncmem(&p->dma, 1890 p->offs + offsetof(uhci_td_t, td_link), 1891 sizeof(p->td.td_link), 1892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1893 td_link = le32toh(p->td.td_link); 1894 usb_syncmem(&p->dma, 1895 p->offs + offsetof(uhci_td_t, td_link), 1896 sizeof(p->td.td_link), 1897 BUS_DMASYNC_PREREAD); 1898 if ((td_link & UHCI_PTR_T) == 0) { 1899 p->td.td_link = htole32(UHCI_PTR_T); 1900 usb_syncmem(&p->dma, 1901 p->offs + offsetof(uhci_td_t, td_link), 1902 sizeof(p->td.td_link), 1903 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1904 } 1905 } 1906 delay(UHCI_QH_REMOVE_DELAY); 1907 1908 for (; std != stdend; std = p) { 1909 p = std->link.std; 1910 uhci_free_std(sc, std); 1911 } 1912 } 1913 1914 usbd_status 1915 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1916 int rd, uint16_t flags, usb_dma_t *dma, 1917 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1918 { 1919 uhci_soft_td_t *p, *lastp; 1920 uhci_physaddr_t lastlink; 1921 int i, ntd, l, tog, maxp; 1922 uint32_t status; 1923 int addr = upipe->pipe.up_dev->ud_addr; 1924 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1925 1926 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1927 1928 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 1929 addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed); 1930 1931 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1932 1933 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1934 if (maxp == 0) { 1935 printf("uhci_alloc_std_chain: maxp=0\n"); 1936 return USBD_INVAL; 1937 } 1938 ntd = (len + maxp - 1) / maxp; 1939 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1940 ntd++; 1941 DPRINTFN(10, "maxp=%d ntd=%d", 1942 maxp, ntd, 0, 0); 1943 1944 if (ntd == 0) { 1945 *sp = *ep = NULL; 1946 DPRINTF("ntd=0", 0, 0, 0, 0); 1947 return USBD_NORMAL_COMPLETION; 1948 } 1949 tog = upipe->nexttoggle; 1950 if (ntd % 2 == 0) 1951 tog ^= 1; 1952 upipe->nexttoggle = tog ^ 1; 1953 lastp = NULL; 1954 lastlink = UHCI_PTR_T; 1955 ntd--; 1956 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1957 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1958 status |= UHCI_TD_LS; 1959 if (flags & USBD_SHORT_XFER_OK) 1960 status |= UHCI_TD_SPD; 1961 usb_syncmem(dma, 0, len, 1962 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1963 for (i = ntd; i >= 0; i--) { 1964 p = uhci_alloc_std(sc); 1965 if (p == NULL) { 1966 KASSERT(lastp != NULL); 1967 uhci_free_std_chain(sc, lastp, NULL); 1968 return USBD_NOMEM; 1969 } 1970 p->link.std = lastp; 1971 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1972 lastp = p; 1973 lastlink = p->physaddr; 1974 p->td.td_status = htole32(status); 1975 if (i == ntd) { 1976 /* last TD */ 1977 l = len % maxp; 1978 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1979 l = maxp; 1980 *ep = p; 1981 } else 1982 l = maxp; 1983 p->td.td_token = 1984 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1985 UHCI_TD_OUT(l, endpt, addr, tog)); 1986 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1987 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1989 tog ^= 1; 1990 } 1991 *sp = lastp; 1992 DPRINTFN(10, "nexttog=%d", upipe->nexttoggle, 1993 0, 0, 0); 1994 1995 return USBD_NORMAL_COMPLETION; 1996 } 1997 1998 void 1999 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2000 { 2001 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2002 upipe->nexttoggle = 0; 2003 } 2004 2005 void 2006 uhci_noop(struct usbd_pipe *pipe) 2007 { 2008 } 2009 2010 usbd_status 2011 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2012 { 2013 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2014 usbd_status err; 2015 2016 /* Insert last in queue. */ 2017 mutex_enter(&sc->sc_lock); 2018 err = usb_insert_transfer(xfer); 2019 mutex_exit(&sc->sc_lock); 2020 if (err) 2021 return err; 2022 2023 /* 2024 * Pipe isn't running (otherwise err would be USBD_INPROG), 2025 * so start it first. 2026 */ 2027 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2028 } 2029 2030 usbd_status 2031 uhci_device_bulk_start(struct usbd_xfer *xfer) 2032 { 2033 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2034 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2035 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2036 uhci_soft_td_t *data, *dataend; 2037 uhci_soft_qh_t *sqh; 2038 usbd_status err; 2039 int len, isread, endpt; 2040 2041 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2042 DPRINTFN(3, "xfer=%p len=%d flags=%d ux=%p", 2043 xfer, xfer->ux_length, xfer->ux_flags, ux); 2044 2045 if (sc->sc_dying) 2046 return USBD_IOERROR; 2047 2048 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2049 2050 mutex_enter(&sc->sc_lock); 2051 2052 len = xfer->ux_length; 2053 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2054 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2055 sqh = upipe->bulk.sqh; 2056 2057 upipe->bulk.isread = isread; 2058 upipe->bulk.length = len; 2059 2060 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2061 &xfer->ux_dmabuf, &data, &dataend); 2062 if (err) { 2063 mutex_exit(&sc->sc_lock); 2064 return err; 2065 } 2066 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2067 usb_syncmem(&dataend->dma, 2068 dataend->offs + offsetof(uhci_td_t, td_status), 2069 sizeof(dataend->td.td_status), 2070 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2071 2072 2073 #ifdef UHCI_DEBUG 2074 if (uhcidebug > 8) { 2075 DPRINTFN(8, "data(1)", 0, 0, 0, 0); 2076 uhci_dump_tds(data); 2077 } 2078 #endif 2079 2080 /* Set up interrupt info. */ 2081 ux->stdstart = data; 2082 ux->stdend = dataend; 2083 2084 KASSERT(ux->isdone); 2085 #ifdef DIAGNOSTIC 2086 ux->isdone = false; 2087 #endif 2088 2089 sqh->elink = data; 2090 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2091 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2092 2093 uhci_add_bulk(sc, sqh); 2094 uhci_add_intr_info(sc, ux); 2095 2096 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2097 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2098 uhci_timeout, xfer); 2099 } 2100 xfer->ux_status = USBD_IN_PROGRESS; 2101 2102 #ifdef UHCI_DEBUG 2103 if (uhcidebug > 10) { 2104 DPRINTFN(10, "data(2)", 0, 0, 0, 0); 2105 uhci_dump_tds(data); 2106 } 2107 #endif 2108 2109 if (sc->sc_bus.ub_usepolling) 2110 uhci_waitintr(sc, xfer); 2111 2112 mutex_exit(&sc->sc_lock); 2113 return USBD_IN_PROGRESS; 2114 } 2115 2116 /* Abort a device bulk request. */ 2117 void 2118 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2119 { 2120 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2121 2122 KASSERT(mutex_owned(&sc->sc_lock)); 2123 2124 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2125 2126 uhci_abort_xfer(xfer, USBD_CANCELLED); 2127 } 2128 2129 /* 2130 * Abort a device request. 2131 * If this routine is called at splusb() it guarantees that the request 2132 * will be removed from the hardware scheduling and that the callback 2133 * for it will be called with USBD_CANCELLED status. 2134 * It's impossible to guarantee that the requested transfer will not 2135 * have happened since the hardware runs concurrently. 2136 * If the transaction has already happened we rely on the ordinary 2137 * interrupt processing to process it. 2138 * XXX This is most probably wrong. 2139 * XXXMRG this doesn't make sense anymore. 2140 */ 2141 void 2142 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2143 { 2144 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2145 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2146 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2147 uhci_soft_td_t *std; 2148 int wake; 2149 2150 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2151 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2152 2153 KASSERT(mutex_owned(&sc->sc_lock)); 2154 ASSERT_SLEEPABLE(); 2155 2156 if (sc->sc_dying) { 2157 /* If we're dying, just do the software part. */ 2158 xfer->ux_status = status; /* make software ignore it */ 2159 callout_stop(&xfer->ux_callout); 2160 usb_transfer_complete(xfer); 2161 return; 2162 } 2163 2164 /* 2165 * If an abort is already in progress then just wait for it to 2166 * complete and return. 2167 */ 2168 if (xfer->ux_hcflags & UXFER_ABORTING) { 2169 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2170 #ifdef DIAGNOSTIC 2171 if (status == USBD_TIMEOUT) 2172 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2173 #endif 2174 /* Override the status which might be USBD_TIMEOUT. */ 2175 xfer->ux_status = status; 2176 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2177 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2178 while (xfer->ux_hcflags & UXFER_ABORTING) 2179 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2180 goto done; 2181 } 2182 xfer->ux_hcflags |= UXFER_ABORTING; 2183 2184 /* 2185 * Step 1: Make interrupt routine and hardware ignore xfer. 2186 */ 2187 xfer->ux_status = status; /* make software ignore it */ 2188 callout_stop(&xfer->ux_callout); 2189 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2190 for (std = ux->stdstart; std != NULL; std = std->link.std) { 2191 usb_syncmem(&std->dma, 2192 std->offs + offsetof(uhci_td_t, td_status), 2193 sizeof(std->td.td_status), 2194 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2195 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2196 usb_syncmem(&std->dma, 2197 std->offs + offsetof(uhci_td_t, td_status), 2198 sizeof(std->td.td_status), 2199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2200 } 2201 2202 /* 2203 * Step 2: Wait until we know hardware has finished any possible 2204 * use of the xfer. Also make sure the soft interrupt routine 2205 * has run. 2206 */ 2207 /* Hardware finishes in 1ms */ 2208 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2209 sc->sc_softwake = 1; 2210 usb_schedsoftintr(&sc->sc_bus); 2211 DPRINTF("cv_wait", 0, 0, 0, 0); 2212 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2213 2214 /* 2215 * Step 3: Execute callback. 2216 */ 2217 DPRINTF("callback", 0, 0, 0, 0); 2218 #ifdef DIAGNOSTIC 2219 ux->isdone = true; 2220 #endif 2221 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2222 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2223 usb_transfer_complete(xfer); 2224 if (wake) 2225 cv_broadcast(&xfer->ux_hccv); 2226 done: 2227 KASSERT(mutex_owned(&sc->sc_lock)); 2228 } 2229 2230 /* Close a device bulk pipe. */ 2231 void 2232 uhci_device_bulk_close(struct usbd_pipe *pipe) 2233 { 2234 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2235 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2236 2237 KASSERT(mutex_owned(&sc->sc_lock)); 2238 2239 uhci_free_sqh(sc, upipe->bulk.sqh); 2240 2241 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2242 } 2243 2244 usbd_status 2245 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2246 { 2247 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2248 usbd_status err; 2249 2250 /* Insert last in queue. */ 2251 mutex_enter(&sc->sc_lock); 2252 err = usb_insert_transfer(xfer); 2253 mutex_exit(&sc->sc_lock); 2254 if (err) 2255 return err; 2256 2257 /* 2258 * Pipe isn't running (otherwise err would be USBD_INPROG), 2259 * so start it first. 2260 */ 2261 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2262 } 2263 2264 usbd_status 2265 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2266 { 2267 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2268 usbd_status err; 2269 2270 if (sc->sc_dying) 2271 return USBD_IOERROR; 2272 2273 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2274 2275 mutex_enter(&sc->sc_lock); 2276 err = uhci_device_request(xfer); 2277 mutex_exit(&sc->sc_lock); 2278 if (err) 2279 return err; 2280 2281 if (sc->sc_bus.ub_usepolling) 2282 uhci_waitintr(sc, xfer); 2283 return USBD_IN_PROGRESS; 2284 } 2285 2286 usbd_status 2287 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2288 { 2289 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2290 usbd_status err; 2291 2292 /* Insert last in queue. */ 2293 mutex_enter(&sc->sc_lock); 2294 err = usb_insert_transfer(xfer); 2295 mutex_exit(&sc->sc_lock); 2296 if (err) 2297 return err; 2298 2299 /* 2300 * Pipe isn't running (otherwise err would be USBD_INPROG), 2301 * so start it first. 2302 */ 2303 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2304 } 2305 2306 usbd_status 2307 uhci_device_intr_start(struct usbd_xfer *xfer) 2308 { 2309 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2310 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2311 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2312 uhci_soft_td_t *data, *dataend; 2313 uhci_soft_qh_t *sqh; 2314 usbd_status err; 2315 int isread, endpt; 2316 int i; 2317 2318 if (sc->sc_dying) 2319 return USBD_IOERROR; 2320 2321 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2322 2323 DPRINTFN(3, "xfer=%p len=%d flags=%d", 2324 xfer, xfer->ux_length, xfer->ux_flags, 0); 2325 2326 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2327 2328 mutex_enter(&sc->sc_lock); 2329 2330 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2331 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2332 2333 upipe->intr.isread = isread; 2334 2335 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2336 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2337 &dataend); 2338 if (err) { 2339 mutex_exit(&sc->sc_lock); 2340 return err; 2341 } 2342 2343 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2344 usb_syncmem(&dataend->dma, 2345 dataend->offs + offsetof(uhci_td_t, td_status), 2346 sizeof(dataend->td.td_status), 2347 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2348 2349 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2350 #ifdef UHCI_DEBUG 2351 if (uhcidebug > 10) { 2352 uhci_dump_tds(data); 2353 uhci_dump_qh(upipe->intr.qhs[0]); 2354 } 2355 #endif 2356 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2357 2358 /* Set up interrupt info. */ 2359 ux->stdstart = data; 2360 ux->stdend = dataend; 2361 KASSERT(ux->isdone); 2362 #ifdef DIAGNOSTIC 2363 ux->isdone = false; 2364 #endif 2365 2366 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2367 for (i = 0; i < upipe->intr.npoll; i++) { 2368 sqh = upipe->intr.qhs[i]; 2369 sqh->elink = data; 2370 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2371 usb_syncmem(&sqh->dma, 2372 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2373 sizeof(sqh->qh.qh_elink), 2374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2375 } 2376 uhci_add_intr_info(sc, ux); 2377 xfer->ux_status = USBD_IN_PROGRESS; 2378 mutex_exit(&sc->sc_lock); 2379 2380 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2381 #ifdef UHCI_DEBUG 2382 if (uhcidebug > 10) { 2383 uhci_dump_tds(data); 2384 uhci_dump_qh(upipe->intr.qhs[0]); 2385 } 2386 #endif 2387 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2388 2389 return USBD_IN_PROGRESS; 2390 } 2391 2392 /* Abort a device control request. */ 2393 void 2394 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2395 { 2396 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2397 2398 KASSERT(mutex_owned(&sc->sc_lock)); 2399 2400 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2401 uhci_abort_xfer(xfer, USBD_CANCELLED); 2402 } 2403 2404 /* Close a device control pipe. */ 2405 void 2406 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2407 { 2408 } 2409 2410 /* Abort a device interrupt request. */ 2411 void 2412 uhci_device_intr_abort(struct usbd_xfer *xfer) 2413 { 2414 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2415 2416 KASSERT(mutex_owned(&sc->sc_lock)); 2417 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2418 2419 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2420 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2421 2422 uhci_abort_xfer(xfer, USBD_CANCELLED); 2423 } 2424 2425 /* Close a device interrupt pipe. */ 2426 void 2427 uhci_device_intr_close(struct usbd_pipe *pipe) 2428 { 2429 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2430 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2431 int i, npoll; 2432 2433 KASSERT(mutex_owned(&sc->sc_lock)); 2434 2435 /* Unlink descriptors from controller data structures. */ 2436 npoll = upipe->intr.npoll; 2437 for (i = 0; i < npoll; i++) 2438 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2439 2440 /* 2441 * We now have to wait for any activity on the physical 2442 * descriptors to stop. 2443 */ 2444 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2445 2446 for(i = 0; i < npoll; i++) 2447 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2448 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2449 2450 /* XXX free other resources */ 2451 } 2452 2453 usbd_status 2454 uhci_device_request(struct usbd_xfer *xfer) 2455 { 2456 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2457 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2458 usb_device_request_t *req = &xfer->ux_request; 2459 struct usbd_device *dev = upipe->pipe.up_dev; 2460 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2461 int addr = dev->ud_addr; 2462 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2463 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2464 uhci_soft_qh_t *sqh; 2465 int len; 2466 uint32_t ls; 2467 usbd_status err; 2468 int isread; 2469 2470 KASSERT(mutex_owned(&sc->sc_lock)); 2471 2472 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2473 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2474 "wValue=0x%04x, wIndex=0x%04x", 2475 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2476 UGETW(req->wIndex)); 2477 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2478 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2479 2480 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2481 isread = req->bmRequestType & UT_READ; 2482 len = UGETW(req->wLength); 2483 2484 setup = upipe->ctrl.setup; 2485 stat = upipe->ctrl.stat; 2486 sqh = upipe->ctrl.sqh; 2487 2488 /* Set up data transaction */ 2489 if (len != 0) { 2490 upipe->nexttoggle = 1; 2491 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2492 &xfer->ux_dmabuf, &data, &dataend); 2493 if (err) 2494 return err; 2495 next = data; 2496 dataend->link.std = stat; 2497 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2498 usb_syncmem(&dataend->dma, 2499 dataend->offs + offsetof(uhci_td_t, td_link), 2500 sizeof(dataend->td.td_link), 2501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2502 } else { 2503 next = stat; 2504 } 2505 upipe->ctrl.length = len; 2506 2507 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2508 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2509 2510 setup->link.std = next; 2511 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2512 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2513 UHCI_TD_ACTIVE); 2514 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2515 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2516 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2517 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2518 2519 stat->link.std = NULL; 2520 stat->td.td_link = htole32(UHCI_PTR_T); 2521 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2522 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2523 stat->td.td_token = 2524 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2525 UHCI_TD_IN (0, endpt, addr, 1)); 2526 stat->td.td_buffer = htole32(0); 2527 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2529 2530 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2531 #ifdef UHCI_DEBUG 2532 if (uhcidebug > 10) { 2533 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2534 uhci_dump_tds(setup); 2535 } 2536 #endif 2537 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2538 2539 /* Set up interrupt info. */ 2540 uxfer->stdstart = setup; 2541 uxfer->stdend = stat; 2542 KASSERT(uxfer->isdone); 2543 #ifdef DIAGNOSTIC 2544 uxfer->isdone = false; 2545 #endif 2546 2547 sqh->elink = setup; 2548 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2549 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2550 2551 if (dev->ud_speed == USB_SPEED_LOW) 2552 uhci_add_ls_ctrl(sc, sqh); 2553 else 2554 uhci_add_hs_ctrl(sc, sqh); 2555 uhci_add_intr_info(sc, uxfer); 2556 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2557 #ifdef UHCI_DEBUG 2558 if (uhcidebug > 12) { 2559 uhci_soft_td_t *std; 2560 uhci_soft_qh_t *xqh; 2561 uhci_soft_qh_t *sxqh; 2562 int maxqh = 0; 2563 uhci_physaddr_t link; 2564 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2565 for (std = sc->sc_vframes[0].htd, link = 0; 2566 (link & UHCI_PTR_QH) == 0; 2567 std = std->link.std) { 2568 link = le32toh(std->td.td_link); 2569 uhci_dump_td(std); 2570 } 2571 sxqh = (uhci_soft_qh_t *)std; 2572 uhci_dump_qh(sxqh); 2573 for (xqh = sxqh; 2574 xqh != NULL; 2575 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2576 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2577 uhci_dump_qh(xqh); 2578 } 2579 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2580 uhci_dump_qh(sqh); 2581 uhci_dump_tds(sqh->elink); 2582 } 2583 #endif 2584 DPRINTFN(12, "--- dump end ---", 0, 0, 0, 0); 2585 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2586 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2587 uhci_timeout, xfer); 2588 } 2589 xfer->ux_status = USBD_IN_PROGRESS; 2590 2591 return USBD_NORMAL_COMPLETION; 2592 } 2593 2594 usbd_status 2595 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2596 { 2597 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2598 usbd_status err; 2599 2600 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2601 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2602 2603 /* Put it on our queue, */ 2604 mutex_enter(&sc->sc_lock); 2605 err = usb_insert_transfer(xfer); 2606 mutex_exit(&sc->sc_lock); 2607 2608 /* bail out on error, */ 2609 if (err && err != USBD_IN_PROGRESS) 2610 return err; 2611 2612 /* XXX should check inuse here */ 2613 2614 /* insert into schedule, */ 2615 uhci_device_isoc_enter(xfer); 2616 2617 /* and start if the pipe wasn't running */ 2618 if (!err) 2619 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2620 2621 return err; 2622 } 2623 2624 void 2625 uhci_device_isoc_enter(struct usbd_xfer *xfer) 2626 { 2627 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2628 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2629 struct isoc *isoc = &upipe->isoc; 2630 uhci_soft_td_t *std; 2631 uint32_t buf, len, status, offs; 2632 int i, next, nframes; 2633 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2634 2635 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2636 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2637 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2638 2639 if (sc->sc_dying) 2640 return; 2641 2642 if (xfer->ux_status == USBD_IN_PROGRESS) { 2643 /* This request has already been entered into the frame list */ 2644 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2645 /* XXX */ 2646 } 2647 2648 #ifdef DIAGNOSTIC 2649 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2650 printf("uhci_device_isoc_enter: overflow!\n"); 2651 #endif 2652 2653 next = isoc->next; 2654 if (next == -1) { 2655 /* Not in use yet, schedule it a few frames ahead. */ 2656 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2657 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2658 } 2659 2660 xfer->ux_status = USBD_IN_PROGRESS; 2661 UHCI_XFER2UXFER(xfer)->curframe = next; 2662 2663 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2664 offs = 0; 2665 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2666 UHCI_TD_ACTIVE | 2667 UHCI_TD_IOS); 2668 nframes = xfer->ux_nframes; 2669 mutex_enter(&sc->sc_lock); 2670 for (i = 0; i < nframes; i++) { 2671 std = isoc->stds[next]; 2672 if (++next >= UHCI_VFRAMELIST_COUNT) 2673 next = 0; 2674 len = xfer->ux_frlengths[i]; 2675 std->td.td_buffer = htole32(buf); 2676 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2677 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2678 if (i == nframes - 1) 2679 status |= UHCI_TD_IOC; 2680 std->td.td_status = htole32(status); 2681 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2682 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2683 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2684 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2685 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2686 #ifdef UHCI_DEBUG 2687 if (uhcidebug > 5) { 2688 DPRINTF("TD %d", i, 0, 0, 0); 2689 uhci_dump_td(std); 2690 } 2691 #endif 2692 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2693 buf += len; 2694 offs += len; 2695 } 2696 isoc->next = next; 2697 isoc->inuse += xfer->ux_nframes; 2698 2699 mutex_exit(&sc->sc_lock); 2700 } 2701 2702 usbd_status 2703 uhci_device_isoc_start(struct usbd_xfer *xfer) 2704 { 2705 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2706 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2707 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2708 uhci_soft_td_t *end; 2709 int i; 2710 2711 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2712 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2713 2714 mutex_enter(&sc->sc_lock); 2715 2716 if (sc->sc_dying) { 2717 mutex_exit(&sc->sc_lock); 2718 return USBD_IOERROR; 2719 } 2720 2721 #ifdef DIAGNOSTIC 2722 if (xfer->ux_status != USBD_IN_PROGRESS) 2723 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2724 #endif 2725 2726 /* Find the last TD */ 2727 i = UHCI_XFER2UXFER(xfer)->curframe + xfer->ux_nframes; 2728 if (i >= UHCI_VFRAMELIST_COUNT) 2729 i -= UHCI_VFRAMELIST_COUNT; 2730 end = upipe->isoc.stds[i]; 2731 2732 KASSERT(end != NULL); 2733 2734 /* Set up interrupt info. */ 2735 ux->stdstart = end; 2736 ux->stdend = end; 2737 2738 KASSERT(ux->isdone); 2739 #ifdef DIAGNOSTIC 2740 ux->isdone = false; 2741 #endif 2742 uhci_add_intr_info(sc, ux); 2743 2744 mutex_exit(&sc->sc_lock); 2745 2746 return USBD_IN_PROGRESS; 2747 } 2748 2749 void 2750 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2751 { 2752 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2753 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2754 uhci_soft_td_t **stds = upipe->isoc.stds; 2755 uhci_soft_td_t *std; 2756 int i, n, nframes, maxlen, len; 2757 2758 KASSERT(mutex_owned(&sc->sc_lock)); 2759 2760 /* Transfer is already done. */ 2761 if (xfer->ux_status != USBD_NOT_STARTED && 2762 xfer->ux_status != USBD_IN_PROGRESS) { 2763 return; 2764 } 2765 2766 /* Give xfer the requested abort code. */ 2767 xfer->ux_status = USBD_CANCELLED; 2768 2769 /* make hardware ignore it, */ 2770 nframes = xfer->ux_nframes; 2771 n = UHCI_XFER2UXFER(xfer)->curframe; 2772 maxlen = 0; 2773 for (i = 0; i < nframes; i++) { 2774 std = stds[n]; 2775 usb_syncmem(&std->dma, 2776 std->offs + offsetof(uhci_td_t, td_status), 2777 sizeof(std->td.td_status), 2778 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2779 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2780 usb_syncmem(&std->dma, 2781 std->offs + offsetof(uhci_td_t, td_status), 2782 sizeof(std->td.td_status), 2783 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2784 usb_syncmem(&std->dma, 2785 std->offs + offsetof(uhci_td_t, td_token), 2786 sizeof(std->td.td_token), 2787 BUS_DMASYNC_POSTWRITE); 2788 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2789 if (len > maxlen) 2790 maxlen = len; 2791 if (++n >= UHCI_VFRAMELIST_COUNT) 2792 n = 0; 2793 } 2794 2795 /* and wait until we are sure the hardware has finished. */ 2796 delay(maxlen); 2797 2798 #ifdef DIAGNOSTIC 2799 UHCI_XFER2UXFER(xfer)->isdone = true; 2800 #endif 2801 /* Run callback and remove from interrupt list. */ 2802 usb_transfer_complete(xfer); 2803 2804 KASSERT(mutex_owned(&sc->sc_lock)); 2805 } 2806 2807 void 2808 uhci_device_isoc_close(struct usbd_pipe *pipe) 2809 { 2810 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2811 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2812 uhci_soft_td_t *std, *vstd; 2813 struct isoc *isoc; 2814 int i; 2815 2816 KASSERT(mutex_owned(&sc->sc_lock)); 2817 2818 /* 2819 * Make sure all TDs are marked as inactive. 2820 * Wait for completion. 2821 * Unschedule. 2822 * Deallocate. 2823 */ 2824 isoc = &upipe->isoc; 2825 2826 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2827 std = isoc->stds[i]; 2828 usb_syncmem(&std->dma, 2829 std->offs + offsetof(uhci_td_t, td_status), 2830 sizeof(std->td.td_status), 2831 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2832 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2833 usb_syncmem(&std->dma, 2834 std->offs + offsetof(uhci_td_t, td_status), 2835 sizeof(std->td.td_status), 2836 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2837 } 2838 /* wait for completion */ 2839 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2840 2841 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2842 std = isoc->stds[i]; 2843 for (vstd = sc->sc_vframes[i].htd; 2844 vstd != NULL && vstd->link.std != std; 2845 vstd = vstd->link.std) 2846 ; 2847 if (vstd == NULL) { 2848 /*panic*/ 2849 printf("uhci_device_isoc_close: %p not found\n", std); 2850 mutex_exit(&sc->sc_lock); 2851 return; 2852 } 2853 vstd->link = std->link; 2854 usb_syncmem(&std->dma, 2855 std->offs + offsetof(uhci_td_t, td_link), 2856 sizeof(std->td.td_link), 2857 BUS_DMASYNC_POSTWRITE); 2858 vstd->td.td_link = std->td.td_link; 2859 usb_syncmem(&vstd->dma, 2860 vstd->offs + offsetof(uhci_td_t, td_link), 2861 sizeof(vstd->td.td_link), 2862 BUS_DMASYNC_PREWRITE); 2863 uhci_free_std(sc, std); 2864 } 2865 2866 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2867 } 2868 2869 usbd_status 2870 uhci_setup_isoc(struct usbd_pipe *pipe) 2871 { 2872 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2873 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2874 int addr = upipe->pipe.up_dev->ud_addr; 2875 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2876 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2877 uhci_soft_td_t *std, *vstd; 2878 uint32_t token; 2879 struct isoc *isoc; 2880 int i; 2881 2882 isoc = &upipe->isoc; 2883 isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2884 sizeof(uhci_soft_td_t *), 2885 KM_SLEEP); 2886 if (isoc->stds == NULL) 2887 return USBD_NOMEM; 2888 2889 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2890 UHCI_TD_OUT(0, endpt, addr, 0); 2891 2892 mutex_enter(&sc->sc_lock); 2893 2894 /* Allocate the TDs and mark as inactive; */ 2895 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2896 std = uhci_alloc_std(sc); 2897 if (std == 0) 2898 goto bad; 2899 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2900 std->td.td_token = htole32(token); 2901 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2902 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2903 isoc->stds[i] = std; 2904 } 2905 2906 /* Insert TDs into schedule. */ 2907 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2908 std = isoc->stds[i]; 2909 vstd = sc->sc_vframes[i].htd; 2910 usb_syncmem(&vstd->dma, 2911 vstd->offs + offsetof(uhci_td_t, td_link), 2912 sizeof(vstd->td.td_link), 2913 BUS_DMASYNC_POSTWRITE); 2914 std->link = vstd->link; 2915 std->td.td_link = vstd->td.td_link; 2916 usb_syncmem(&std->dma, 2917 std->offs + offsetof(uhci_td_t, td_link), 2918 sizeof(std->td.td_link), 2919 BUS_DMASYNC_PREWRITE); 2920 vstd->link.std = std; 2921 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2922 usb_syncmem(&vstd->dma, 2923 vstd->offs + offsetof(uhci_td_t, td_link), 2924 sizeof(vstd->td.td_link), 2925 BUS_DMASYNC_PREWRITE); 2926 } 2927 mutex_exit(&sc->sc_lock); 2928 2929 isoc->next = -1; 2930 isoc->inuse = 0; 2931 2932 return USBD_NORMAL_COMPLETION; 2933 2934 bad: 2935 while (--i >= 0) 2936 uhci_free_std(sc, isoc->stds[i]); 2937 mutex_exit(&sc->sc_lock); 2938 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2939 return USBD_NOMEM; 2940 } 2941 2942 void 2943 uhci_device_isoc_done(struct usbd_xfer *xfer) 2944 { 2945 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2946 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2947 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2948 int i, offs; 2949 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2950 2951 2952 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2953 DPRINTFN(4, "length=%d, ux_state=0x%08x", 2954 xfer->ux_actlen, xfer->ux_state, 0, 0); 2955 2956 if (!uhci_active_intr_info(ux)) 2957 return; 2958 2959 #ifdef DIAGNOSTIC 2960 if (ux->stdend == NULL) { 2961 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2962 #ifdef UHCI_DEBUG 2963 uhci_dump_ii(ux); 2964 #endif 2965 return; 2966 } 2967 #endif 2968 2969 /* Turn off the interrupt since it is active even if the TD is not. */ 2970 usb_syncmem(&ux->stdend->dma, 2971 ux->stdend->offs + offsetof(uhci_td_t, td_status), 2972 sizeof(ux->stdend->td.td_status), 2973 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2974 ux->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2975 usb_syncmem(&ux->stdend->dma, 2976 ux->stdend->offs + offsetof(uhci_td_t, td_status), 2977 sizeof(ux->stdend->td.td_status), 2978 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2979 2980 uhci_del_intr_info(sc, ux); /* remove from active list */ 2981 2982 offs = 0; 2983 for (i = 0; i < xfer->ux_nframes; i++) { 2984 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2985 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2986 offs += xfer->ux_frlengths[i]; 2987 } 2988 } 2989 2990 void 2991 uhci_device_intr_done(struct usbd_xfer *xfer) 2992 { 2993 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2994 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2995 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2996 uhci_soft_qh_t *sqh; 2997 int i, npoll, isread; 2998 2999 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3000 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3001 3002 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3003 3004 npoll = upipe->intr.npoll; 3005 for(i = 0; i < npoll; i++) { 3006 sqh = upipe->intr.qhs[i]; 3007 sqh->elink = NULL; 3008 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3009 usb_syncmem(&sqh->dma, 3010 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3011 sizeof(sqh->qh.qh_elink), 3012 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3013 } 3014 uhci_free_std_chain(sc, ux->stdstart, NULL); 3015 3016 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3017 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3018 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3019 3020 /* XXX Wasteful. */ 3021 if (xfer->ux_pipe->up_repeat) { 3022 uhci_soft_td_t *data, *dataend; 3023 3024 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3025 3026 /* This alloc cannot fail since we freed the chain above. */ 3027 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3028 upipe->intr.isread, xfer->ux_flags, 3029 &xfer->ux_dmabuf, &data, &dataend); 3030 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3031 usb_syncmem(&dataend->dma, 3032 dataend->offs + offsetof(uhci_td_t, td_status), 3033 sizeof(dataend->td.td_status), 3034 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3035 3036 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 3037 #ifdef UHCI_DEBUG 3038 if (uhcidebug > 10) { 3039 uhci_dump_tds(data); 3040 uhci_dump_qh(upipe->intr.qhs[0]); 3041 } 3042 #endif 3043 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 3044 3045 ux->stdstart = data; 3046 ux->stdend = dataend; 3047 KASSERT(ux->isdone); 3048 #ifdef DIAGNOSTIC 3049 ux->isdone = false; 3050 #endif 3051 for (i = 0; i < npoll; i++) { 3052 sqh = upipe->intr.qhs[i]; 3053 sqh->elink = data; 3054 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3055 usb_syncmem(&sqh->dma, 3056 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3057 sizeof(sqh->qh.qh_elink), 3058 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3059 } 3060 xfer->ux_status = USBD_IN_PROGRESS; 3061 /* The ux is already on the examined list, just leave it. */ 3062 } else { 3063 DPRINTFN(5, "removing", 0, 0, 0, 0); 3064 if (uhci_active_intr_info(ux)) 3065 uhci_del_intr_info(sc, ux); 3066 } 3067 } 3068 3069 /* Deallocate request data structures */ 3070 void 3071 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3072 { 3073 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3074 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3075 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3076 int len = UGETW(xfer->ux_request.wLength); 3077 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3078 3079 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3080 3081 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3082 3083 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3084 3085 if (!uhci_active_intr_info(ux)) 3086 return; 3087 3088 uhci_del_intr_info(sc, ux); /* remove from active list */ 3089 3090 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3091 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3092 else 3093 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3094 3095 if (upipe->ctrl.length != 0) 3096 uhci_free_std_chain(sc, ux->stdstart->link.std, ux->stdend); 3097 3098 if (len) { 3099 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3100 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3101 } 3102 usb_syncmem(&upipe->ctrl.reqdma, 0, 3103 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3104 3105 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3106 } 3107 3108 /* Deallocate request data structures */ 3109 void 3110 uhci_device_bulk_done(struct usbd_xfer *xfer) 3111 { 3112 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3113 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3114 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3115 3116 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3117 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3118 upipe); 3119 3120 KASSERT(mutex_owned(&sc->sc_lock)); 3121 3122 if (!uhci_active_intr_info(ux)) 3123 return; 3124 3125 uhci_del_intr_info(sc, ux); /* remove from active list */ 3126 3127 uhci_remove_bulk(sc, upipe->bulk.sqh); 3128 3129 uhci_free_std_chain(sc, ux->stdstart, NULL); 3130 3131 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3132 } 3133 3134 /* Add interrupt QH, called with vflock. */ 3135 void 3136 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3137 { 3138 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3139 uhci_soft_qh_t *eqh; 3140 3141 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3142 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3143 3144 eqh = vf->eqh; 3145 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3146 sizeof(eqh->qh.qh_hlink), 3147 BUS_DMASYNC_POSTWRITE); 3148 sqh->hlink = eqh->hlink; 3149 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3150 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3151 sizeof(sqh->qh.qh_hlink), 3152 BUS_DMASYNC_PREWRITE); 3153 eqh->hlink = sqh; 3154 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3155 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3156 sizeof(eqh->qh.qh_hlink), 3157 BUS_DMASYNC_PREWRITE); 3158 vf->eqh = sqh; 3159 vf->bandwidth++; 3160 } 3161 3162 /* Remove interrupt QH. */ 3163 void 3164 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3165 { 3166 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3167 uhci_soft_qh_t *pqh; 3168 3169 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3170 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3171 3172 /* See comment in uhci_remove_ctrl() */ 3173 3174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3175 sizeof(sqh->qh.qh_elink), 3176 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3177 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3178 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3179 usb_syncmem(&sqh->dma, 3180 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3181 sizeof(sqh->qh.qh_elink), 3182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3183 delay(UHCI_QH_REMOVE_DELAY); 3184 } 3185 3186 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3187 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3188 sizeof(sqh->qh.qh_hlink), 3189 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3190 pqh->hlink = sqh->hlink; 3191 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3192 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3193 sizeof(pqh->qh.qh_hlink), 3194 BUS_DMASYNC_PREWRITE); 3195 delay(UHCI_QH_REMOVE_DELAY); 3196 if (vf->eqh == sqh) 3197 vf->eqh = pqh; 3198 vf->bandwidth--; 3199 } 3200 3201 usbd_status 3202 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3203 { 3204 uhci_soft_qh_t *sqh; 3205 int i, npoll; 3206 u_int bestbw, bw, bestoffs, offs; 3207 3208 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3209 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3210 if (ival == 0) { 3211 printf("uhci_device_setintr: 0 interval\n"); 3212 return USBD_INVAL; 3213 } 3214 3215 if (ival > UHCI_VFRAMELIST_COUNT) 3216 ival = UHCI_VFRAMELIST_COUNT; 3217 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3218 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3219 3220 upipe->intr.npoll = npoll; 3221 upipe->intr.qhs = 3222 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3223 if (upipe->intr.qhs == NULL) 3224 return USBD_NOMEM; 3225 3226 /* 3227 * Figure out which offset in the schedule that has most 3228 * bandwidth left over. 3229 */ 3230 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3231 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3232 for (bw = i = 0; i < npoll; i++) 3233 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3234 if (bw < bestbw) { 3235 bestbw = bw; 3236 bestoffs = offs; 3237 } 3238 } 3239 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3240 mutex_enter(&sc->sc_lock); 3241 for(i = 0; i < npoll; i++) { 3242 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3243 sqh->elink = NULL; 3244 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3245 usb_syncmem(&sqh->dma, 3246 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3247 sizeof(sqh->qh.qh_elink), 3248 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3249 sqh->pos = MOD(i * ival + bestoffs); 3250 } 3251 #undef MOD 3252 3253 /* Enter QHs into the controller data structures. */ 3254 for(i = 0; i < npoll; i++) 3255 uhci_add_intr(sc, upipe->intr.qhs[i]); 3256 mutex_exit(&sc->sc_lock); 3257 3258 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3259 3260 return USBD_NORMAL_COMPLETION; 3261 } 3262 3263 /* Open a new pipe. */ 3264 usbd_status 3265 uhci_open(struct usbd_pipe *pipe) 3266 { 3267 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3268 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3269 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3270 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3271 usbd_status err = USBD_NOMEM; 3272 int ival; 3273 3274 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3275 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3276 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3277 3278 if (sc->sc_dying) 3279 return USBD_IOERROR; 3280 3281 upipe->aborting = 0; 3282 /* toggle state needed for bulk endpoints */ 3283 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3284 3285 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3286 switch (ed->bEndpointAddress) { 3287 case USB_CONTROL_ENDPOINT: 3288 pipe->up_methods = &roothub_ctrl_methods; 3289 break; 3290 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3291 pipe->up_methods = &uhci_root_intr_methods; 3292 break; 3293 default: 3294 return USBD_INVAL; 3295 } 3296 } else { 3297 switch (ed->bmAttributes & UE_XFERTYPE) { 3298 case UE_CONTROL: 3299 pipe->up_methods = &uhci_device_ctrl_methods; 3300 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3301 if (upipe->ctrl.sqh == NULL) 3302 goto bad; 3303 upipe->ctrl.setup = uhci_alloc_std(sc); 3304 if (upipe->ctrl.setup == NULL) { 3305 uhci_free_sqh(sc, upipe->ctrl.sqh); 3306 goto bad; 3307 } 3308 upipe->ctrl.stat = uhci_alloc_std(sc); 3309 if (upipe->ctrl.stat == NULL) { 3310 uhci_free_sqh(sc, upipe->ctrl.sqh); 3311 uhci_free_std(sc, upipe->ctrl.setup); 3312 goto bad; 3313 } 3314 err = usb_allocmem(&sc->sc_bus, 3315 sizeof(usb_device_request_t), 3316 0, &upipe->ctrl.reqdma); 3317 if (err) { 3318 uhci_free_sqh(sc, upipe->ctrl.sqh); 3319 uhci_free_std(sc, upipe->ctrl.setup); 3320 uhci_free_std(sc, upipe->ctrl.stat); 3321 goto bad; 3322 } 3323 break; 3324 case UE_INTERRUPT: 3325 pipe->up_methods = &uhci_device_intr_methods; 3326 ival = pipe->up_interval; 3327 if (ival == USBD_DEFAULT_INTERVAL) 3328 ival = ed->bInterval; 3329 return uhci_device_setintr(sc, upipe, ival); 3330 case UE_ISOCHRONOUS: 3331 pipe->up_methods = &uhci_device_isoc_methods; 3332 return uhci_setup_isoc(pipe); 3333 case UE_BULK: 3334 pipe->up_methods = &uhci_device_bulk_methods; 3335 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3336 if (upipe->bulk.sqh == NULL) 3337 goto bad; 3338 break; 3339 } 3340 } 3341 return USBD_NORMAL_COMPLETION; 3342 3343 bad: 3344 return USBD_NOMEM; 3345 } 3346 3347 /* 3348 * Data structures and routines to emulate the root hub. 3349 */ 3350 /* 3351 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3352 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3353 * should not be used by the USB subsystem. As we cannot issue a 3354 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3355 * will be enabled as part of the reset. 3356 * 3357 * On the VT83C572, the port cannot be successfully enabled until the 3358 * outstanding "port enable change" and "connection status change" 3359 * events have been reset. 3360 */ 3361 Static usbd_status 3362 uhci_portreset(uhci_softc_t *sc, int index) 3363 { 3364 int lim, port, x; 3365 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3366 3367 if (index == 1) 3368 port = UHCI_PORTSC1; 3369 else if (index == 2) 3370 port = UHCI_PORTSC2; 3371 else 3372 return USBD_IOERROR; 3373 3374 x = URWMASK(UREAD2(sc, port)); 3375 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3376 3377 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3378 3379 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3380 UREAD2(sc, port), 0, 0); 3381 3382 x = URWMASK(UREAD2(sc, port)); 3383 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3384 3385 delay(100); 3386 3387 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3388 UREAD2(sc, port), 0, 0); 3389 3390 x = URWMASK(UREAD2(sc, port)); 3391 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3392 3393 for (lim = 10; --lim > 0;) { 3394 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3395 3396 x = UREAD2(sc, port); 3397 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3398 lim, x, 0); 3399 3400 if (!(x & UHCI_PORTSC_CCS)) { 3401 /* 3402 * No device is connected (or was disconnected 3403 * during reset). Consider the port reset. 3404 * The delay must be long enough to ensure on 3405 * the initial iteration that the device 3406 * connection will have been registered. 50ms 3407 * appears to be sufficient, but 20ms is not. 3408 */ 3409 DPRINTFN(3, "uhci port %d loop %u, device detached", 3410 index, lim, 0, 0); 3411 break; 3412 } 3413 3414 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3415 /* 3416 * Port enabled changed and/or connection 3417 * status changed were set. Reset either or 3418 * both raised flags (by writing a 1 to that 3419 * bit), and wait again for state to settle. 3420 */ 3421 UWRITE2(sc, port, URWMASK(x) | 3422 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3423 continue; 3424 } 3425 3426 if (x & UHCI_PORTSC_PE) 3427 /* Port is enabled */ 3428 break; 3429 3430 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3431 } 3432 3433 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3434 UREAD2(sc, port), 0, 0); 3435 3436 if (lim <= 0) { 3437 DPRINTF("uhci port %d reset timed out", index, 3438 0, 0, 0); 3439 return USBD_TIMEOUT; 3440 } 3441 3442 sc->sc_isreset = 1; 3443 return USBD_NORMAL_COMPLETION; 3444 } 3445 3446 Static int 3447 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3448 void *buf, int buflen) 3449 { 3450 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3451 int port, x; 3452 int status, change, totlen = 0; 3453 uint16_t len, value, index; 3454 usb_port_status_t ps; 3455 usbd_status err; 3456 3457 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3458 3459 if (sc->sc_dying) 3460 return -1; 3461 3462 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3463 req->bRequest, 0, 0); 3464 3465 len = UGETW(req->wLength); 3466 value = UGETW(req->wValue); 3467 index = UGETW(req->wIndex); 3468 3469 #define C(x,y) ((x) | ((y) << 8)) 3470 switch (C(req->bRequest, req->bmRequestType)) { 3471 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3472 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3473 if (len == 0) 3474 break; 3475 switch (value) { 3476 case C(0, UDESC_DEVICE): { 3477 usb_device_descriptor_t devd; 3478 3479 totlen = min(buflen, sizeof(devd)); 3480 memcpy(&devd, buf, totlen); 3481 USETW(devd.idVendor, sc->sc_id_vendor); 3482 memcpy(buf, &devd, totlen); 3483 break; 3484 } 3485 case C(1, UDESC_STRING): 3486 #define sd ((usb_string_descriptor_t *)buf) 3487 /* Vendor */ 3488 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3489 break; 3490 case C(2, UDESC_STRING): 3491 /* Product */ 3492 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3493 break; 3494 #undef sd 3495 default: 3496 /* default from usbroothub */ 3497 return buflen; 3498 } 3499 break; 3500 3501 /* Hub requests */ 3502 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3503 break; 3504 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3505 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3506 value, 0, 0); 3507 if (index == 1) 3508 port = UHCI_PORTSC1; 3509 else if (index == 2) 3510 port = UHCI_PORTSC2; 3511 else { 3512 return -1; 3513 } 3514 switch(value) { 3515 case UHF_PORT_ENABLE: 3516 x = URWMASK(UREAD2(sc, port)); 3517 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3518 break; 3519 case UHF_PORT_SUSPEND: 3520 x = URWMASK(UREAD2(sc, port)); 3521 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3522 break; 3523 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3524 /* see USB2 spec ch. 7.1.7.7 */ 3525 usb_delay_ms(&sc->sc_bus, 20); 3526 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3527 /* 10ms resume delay must be provided by caller */ 3528 break; 3529 case UHF_PORT_RESET: 3530 x = URWMASK(UREAD2(sc, port)); 3531 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3532 break; 3533 case UHF_C_PORT_CONNECTION: 3534 x = URWMASK(UREAD2(sc, port)); 3535 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3536 break; 3537 case UHF_C_PORT_ENABLE: 3538 x = URWMASK(UREAD2(sc, port)); 3539 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3540 break; 3541 case UHF_C_PORT_OVER_CURRENT: 3542 x = URWMASK(UREAD2(sc, port)); 3543 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3544 break; 3545 case UHF_C_PORT_RESET: 3546 sc->sc_isreset = 0; 3547 break; 3548 case UHF_PORT_CONNECTION: 3549 case UHF_PORT_OVER_CURRENT: 3550 case UHF_PORT_POWER: 3551 case UHF_PORT_LOW_SPEED: 3552 case UHF_C_PORT_SUSPEND: 3553 default: 3554 return -1; 3555 } 3556 break; 3557 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3558 if (index == 1) 3559 port = UHCI_PORTSC1; 3560 else if (index == 2) 3561 port = UHCI_PORTSC2; 3562 else { 3563 return -1; 3564 } 3565 if (len > 0) { 3566 *(uint8_t *)buf = 3567 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3568 UHCI_PORTSC_LS_SHIFT; 3569 totlen = 1; 3570 } 3571 break; 3572 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3573 if (len == 0) 3574 break; 3575 if ((value & 0xff) != 0) { 3576 return -1; 3577 } 3578 usb_hub_descriptor_t hubd; 3579 3580 totlen = min(buflen, sizeof(hubd)); 3581 memcpy(&hubd, buf, totlen); 3582 hubd.bNbrPorts = 2; 3583 memcpy(buf, &hubd, totlen); 3584 break; 3585 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3586 if (len != 4) { 3587 return -1; 3588 } 3589 memset(buf, 0, len); 3590 totlen = len; 3591 break; 3592 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3593 if (index == 1) 3594 port = UHCI_PORTSC1; 3595 else if (index == 2) 3596 port = UHCI_PORTSC2; 3597 else { 3598 return -1; 3599 } 3600 if (len != 4) { 3601 return -1; 3602 } 3603 x = UREAD2(sc, port); 3604 status = change = 0; 3605 if (x & UHCI_PORTSC_CCS) 3606 status |= UPS_CURRENT_CONNECT_STATUS; 3607 if (x & UHCI_PORTSC_CSC) 3608 change |= UPS_C_CONNECT_STATUS; 3609 if (x & UHCI_PORTSC_PE) 3610 status |= UPS_PORT_ENABLED; 3611 if (x & UHCI_PORTSC_POEDC) 3612 change |= UPS_C_PORT_ENABLED; 3613 if (x & UHCI_PORTSC_OCI) 3614 status |= UPS_OVERCURRENT_INDICATOR; 3615 if (x & UHCI_PORTSC_OCIC) 3616 change |= UPS_C_OVERCURRENT_INDICATOR; 3617 if (x & UHCI_PORTSC_SUSP) 3618 status |= UPS_SUSPEND; 3619 if (x & UHCI_PORTSC_LSDA) 3620 status |= UPS_LOW_SPEED; 3621 status |= UPS_PORT_POWER; 3622 if (sc->sc_isreset) 3623 change |= UPS_C_PORT_RESET; 3624 USETW(ps.wPortStatus, status); 3625 USETW(ps.wPortChange, change); 3626 totlen = min(len, sizeof(ps)); 3627 memcpy(buf, &ps, totlen); 3628 break; 3629 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3630 return -1; 3631 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3632 break; 3633 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3634 if (index == 1) 3635 port = UHCI_PORTSC1; 3636 else if (index == 2) 3637 port = UHCI_PORTSC2; 3638 else { 3639 return -1; 3640 } 3641 switch(value) { 3642 case UHF_PORT_ENABLE: 3643 x = URWMASK(UREAD2(sc, port)); 3644 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3645 break; 3646 case UHF_PORT_SUSPEND: 3647 x = URWMASK(UREAD2(sc, port)); 3648 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3649 break; 3650 case UHF_PORT_RESET: 3651 err = uhci_portreset(sc, index); 3652 if (err != USBD_NORMAL_COMPLETION) 3653 return -1; 3654 return 0; 3655 case UHF_PORT_POWER: 3656 /* Pretend we turned on power */ 3657 return 0; 3658 case UHF_C_PORT_CONNECTION: 3659 case UHF_C_PORT_ENABLE: 3660 case UHF_C_PORT_OVER_CURRENT: 3661 case UHF_PORT_CONNECTION: 3662 case UHF_PORT_OVER_CURRENT: 3663 case UHF_PORT_LOW_SPEED: 3664 case UHF_C_PORT_SUSPEND: 3665 case UHF_C_PORT_RESET: 3666 default: 3667 return -1; 3668 } 3669 break; 3670 default: 3671 /* default from usbroothub */ 3672 DPRINTF("returning %d (usbroothub default)", 3673 buflen, 0, 0, 0); 3674 return buflen; 3675 } 3676 3677 DPRINTF("returning %d", totlen, 0, 0, 0); 3678 3679 return totlen; 3680 } 3681 3682 /* Abort a root interrupt request. */ 3683 void 3684 uhci_root_intr_abort(struct usbd_xfer *xfer) 3685 { 3686 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3687 3688 KASSERT(mutex_owned(&sc->sc_lock)); 3689 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3690 3691 callout_stop(&sc->sc_poll_handle); 3692 sc->sc_intr_xfer = NULL; 3693 3694 xfer->ux_status = USBD_CANCELLED; 3695 #ifdef DIAGNOSTIC 3696 UHCI_XFER2UXFER(xfer)->isdone = 1; 3697 #endif 3698 usb_transfer_complete(xfer); 3699 } 3700 3701 usbd_status 3702 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3703 { 3704 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3705 usbd_status err; 3706 3707 /* Insert last in queue. */ 3708 mutex_enter(&sc->sc_lock); 3709 err = usb_insert_transfer(xfer); 3710 mutex_exit(&sc->sc_lock); 3711 if (err) 3712 return err; 3713 3714 /* 3715 * Pipe isn't running (otherwise err would be USBD_INPROG), 3716 * start first 3717 */ 3718 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3719 } 3720 3721 /* Start a transfer on the root interrupt pipe */ 3722 usbd_status 3723 uhci_root_intr_start(struct usbd_xfer *xfer) 3724 { 3725 struct usbd_pipe *pipe = xfer->ux_pipe; 3726 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3727 unsigned int ival; 3728 3729 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3730 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3731 xfer->ux_flags, 0); 3732 3733 if (sc->sc_dying) 3734 return USBD_IOERROR; 3735 3736 /* XXX temporary variable needed to avoid gcc3 warning */ 3737 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3738 sc->sc_ival = mstohz(ival); 3739 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3740 sc->sc_intr_xfer = xfer; 3741 return USBD_IN_PROGRESS; 3742 } 3743 3744 /* Close the root interrupt pipe. */ 3745 void 3746 uhci_root_intr_close(struct usbd_pipe *pipe) 3747 { 3748 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3749 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3750 3751 KASSERT(mutex_owned(&sc->sc_lock)); 3752 3753 callout_stop(&sc->sc_poll_handle); 3754 sc->sc_intr_xfer = NULL; 3755 } 3756
Indexes created Tue Sep 30 20:09:53 GMT 2025