uhci.c revision 1.264.4.45
1 /* $NetBSD: uhci.c,v 1.264.4.45 2015/11/01 10:45:42 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.45 2015/11/01 10:45:42 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Isochronous pipe */ 158 struct isoc { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } isoc; 162 }; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static usbd_status uhci_run(uhci_softc_t *, int, int); 169 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 170 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, 180 uhci_soft_td_t *, uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 182 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 183 uhci_soft_td_t **, uhci_soft_td_t **); 184 Static void uhci_poll_hub(void *); 185 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 186 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *); 187 Static void uhci_idone(struct uhci_xfer *); 188 189 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 190 191 Static void uhci_timeout(void *); 192 Static void uhci_timeout_task(void *); 193 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 194 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 195 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 197 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 198 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_add_loop(uhci_softc_t *); 200 Static void uhci_rem_loop(uhci_softc_t *); 201 202 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 203 Static void uhci_device_isoc_enter(struct usbd_xfer *); 204 205 Static struct usbd_xfer * 206 uhci_allocx(struct usbd_bus *, unsigned int); 207 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 208 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 209 Static int uhci_roothub_ctrl(struct usbd_bus *, 210 usb_device_request_t *, void *, int); 211 212 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 213 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 214 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 215 Static void uhci_device_ctrl_close(struct usbd_pipe *); 216 Static void uhci_device_ctrl_done(struct usbd_xfer *); 217 218 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 220 Static void uhci_device_intr_abort(struct usbd_xfer *); 221 Static void uhci_device_intr_close(struct usbd_pipe *); 222 Static void uhci_device_intr_done(struct usbd_xfer *); 223 224 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 225 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 226 Static void uhci_device_bulk_abort(struct usbd_xfer *); 227 Static void uhci_device_bulk_close(struct usbd_pipe *); 228 Static void uhci_device_bulk_done(struct usbd_xfer *); 229 230 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 231 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 232 Static void uhci_device_isoc_abort(struct usbd_xfer *); 233 Static void uhci_device_isoc_close(struct usbd_pipe *); 234 Static void uhci_device_isoc_done(struct usbd_xfer *); 235 236 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 238 Static void uhci_root_intr_abort(struct usbd_xfer *); 239 Static void uhci_root_intr_close(struct usbd_pipe *); 240 Static void uhci_root_intr_done(struct usbd_xfer *); 241 242 Static usbd_status uhci_open(struct usbd_pipe *); 243 Static void uhci_poll(struct usbd_bus *); 244 Static void uhci_softintr(void *); 245 246 Static usbd_status uhci_device_request(struct usbd_xfer *); 247 248 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 250 Static usbd_status uhci_device_setintr(uhci_softc_t *, 251 struct uhci_pipe *, int); 252 253 Static void uhci_device_clear_toggle(struct usbd_pipe *); 254 Static void uhci_noop(struct usbd_pipe *); 255 256 static inline uhci_soft_qh_t * 257 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 258 259 #ifdef UHCI_DEBUG 260 Static void uhci_dump_all(uhci_softc_t *); 261 Static void uhci_dumpregs(uhci_softc_t *); 262 Static void uhci_dump_qhs(uhci_soft_qh_t *); 263 Static void uhci_dump_qh(uhci_soft_qh_t *); 264 Static void uhci_dump_tds(uhci_soft_td_t *); 265 Static void uhci_dump_td(uhci_soft_td_t *); 266 Static void uhci_dump_ii(struct uhci_xfer *); 267 void uhci_dump(void); 268 #endif 269 270 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 271 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 272 #define UWRITE1(sc, r, x) \ 273 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 274 } while (/*CONSTCOND*/0) 275 #define UWRITE2(sc, r, x) \ 276 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 277 } while (/*CONSTCOND*/0) 278 #define UWRITE4(sc, r, x) \ 279 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 280 } while (/*CONSTCOND*/0) 281 282 static __inline uint8_t 283 UREAD1(uhci_softc_t *sc, bus_size_t r) 284 { 285 286 UBARR(sc); 287 return bus_space_read_1(sc->iot, sc->ioh, r); 288 } 289 290 static __inline uint16_t 291 UREAD2(uhci_softc_t *sc, bus_size_t r) 292 { 293 294 UBARR(sc); 295 return bus_space_read_2(sc->iot, sc->ioh, r); 296 } 297 298 #ifdef UHCI_DEBUG 299 static __inline uint32_t 300 UREAD4(uhci_softc_t *sc, bus_size_t r) 301 { 302 303 UBARR(sc); 304 return bus_space_read_4(sc->iot, sc->ioh, r); 305 } 306 #endif 307 308 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 309 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 310 311 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 312 313 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 314 315 const struct usbd_bus_methods uhci_bus_methods = { 316 .ubm_open = uhci_open, 317 .ubm_softint = uhci_softintr, 318 .ubm_dopoll = uhci_poll, 319 .ubm_allocx = uhci_allocx, 320 .ubm_freex = uhci_freex, 321 .ubm_getlock = uhci_get_lock, 322 .ubm_rhctrl = uhci_roothub_ctrl, 323 }; 324 325 const struct usbd_pipe_methods uhci_root_intr_methods = { 326 .upm_transfer = uhci_root_intr_transfer, 327 .upm_start = uhci_root_intr_start, 328 .upm_abort = uhci_root_intr_abort, 329 .upm_close = uhci_root_intr_close, 330 .upm_cleartoggle = uhci_noop, 331 .upm_done = uhci_root_intr_done, 332 }; 333 334 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 335 .upm_transfer = uhci_device_ctrl_transfer, 336 .upm_start = uhci_device_ctrl_start, 337 .upm_abort = uhci_device_ctrl_abort, 338 .upm_close = uhci_device_ctrl_close, 339 .upm_cleartoggle = uhci_noop, 340 .upm_done = uhci_device_ctrl_done, 341 }; 342 343 const struct usbd_pipe_methods uhci_device_intr_methods = { 344 .upm_transfer = uhci_device_intr_transfer, 345 .upm_start = uhci_device_intr_start, 346 .upm_abort = uhci_device_intr_abort, 347 .upm_close = uhci_device_intr_close, 348 .upm_cleartoggle = uhci_device_clear_toggle, 349 .upm_done = uhci_device_intr_done, 350 }; 351 352 const struct usbd_pipe_methods uhci_device_bulk_methods = { 353 .upm_transfer = uhci_device_bulk_transfer, 354 .upm_start = uhci_device_bulk_start, 355 .upm_abort = uhci_device_bulk_abort, 356 .upm_close = uhci_device_bulk_close, 357 .upm_cleartoggle = uhci_device_clear_toggle, 358 .upm_done = uhci_device_bulk_done, 359 }; 360 361 const struct usbd_pipe_methods uhci_device_isoc_methods = { 362 .upm_transfer = uhci_device_isoc_transfer, 363 .upm_start = uhci_device_isoc_start, 364 .upm_abort = uhci_device_isoc_abort, 365 .upm_close = uhci_device_isoc_close, 366 .upm_cleartoggle = uhci_noop, 367 .upm_done = uhci_device_isoc_done, 368 }; 369 370 #define uhci_add_intr_info(sc, ux) \ 371 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), ux_list) 372 #define uhci_del_intr_info(sc, ux) \ 373 do { \ 374 TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), ux_list); \ 375 (ux)->ux_list.tqe_prev = NULL; \ 376 } while (0) 377 #define uhci_active_intr_info(ux) ((ux)->ux_list.tqe_prev != NULL) 378 379 static inline uhci_soft_qh_t * 380 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 381 { 382 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 383 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 384 385 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 386 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 387 usb_syncmem(&pqh->dma, 388 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 389 sizeof(pqh->qh.qh_hlink), 390 BUS_DMASYNC_POSTWRITE); 391 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 392 printf("uhci_find_prev_qh: QH not found\n"); 393 return NULL; 394 } 395 #endif 396 } 397 return pqh; 398 } 399 400 void 401 uhci_globalreset(uhci_softc_t *sc) 402 { 403 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 404 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 405 UHCICMD(sc, 0); /* do nothing */ 406 } 407 408 int 409 uhci_init(uhci_softc_t *sc) 410 { 411 usbd_status err; 412 int i, j; 413 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 414 uhci_soft_td_t *std; 415 416 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 417 418 #ifdef UHCI_DEBUG 419 thesc = sc; 420 421 if (uhcidebug >= 2) 422 uhci_dumpregs(sc); 423 #endif 424 425 sc->sc_suspend = PWR_RESUME; 426 427 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 428 uhci_globalreset(sc); /* reset the controller */ 429 uhci_reset(sc); 430 431 /* Allocate and initialize real frame array. */ 432 err = usb_allocmem(&sc->sc_bus, 433 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 434 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 435 if (err) 436 return err; 437 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 438 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 439 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 440 441 /* 442 * Allocate a TD, inactive, that hangs from the last QH. 443 * This is to avoid a bug in the PIIX that makes it run berserk 444 * otherwise. 445 */ 446 std = uhci_alloc_std(sc); 447 if (std == NULL) 448 return ENOMEM; 449 std->link.std = NULL; 450 std->td.td_link = htole32(UHCI_PTR_T); 451 std->td.td_status = htole32(0); /* inactive */ 452 std->td.td_token = htole32(0); 453 std->td.td_buffer = htole32(0); 454 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 456 457 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 458 lsqh = uhci_alloc_sqh(sc); 459 if (lsqh == NULL) 460 return ENOMEM; 461 lsqh->hlink = NULL; 462 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 463 lsqh->elink = std; 464 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 465 sc->sc_last_qh = lsqh; 466 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 468 469 /* Allocate the dummy QH where bulk traffic will be queued. */ 470 bsqh = uhci_alloc_sqh(sc); 471 if (bsqh == NULL) 472 return ENOMEM; 473 bsqh->hlink = lsqh; 474 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 475 bsqh->elink = NULL; 476 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 477 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 478 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 480 481 /* Allocate dummy QH where high speed control traffic will be queued. */ 482 chsqh = uhci_alloc_sqh(sc); 483 if (chsqh == NULL) 484 return ENOMEM; 485 chsqh->hlink = bsqh; 486 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 487 chsqh->elink = NULL; 488 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 489 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 490 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 492 493 /* Allocate dummy QH where control traffic will be queued. */ 494 clsqh = uhci_alloc_sqh(sc); 495 if (clsqh == NULL) 496 return ENOMEM; 497 clsqh->hlink = chsqh; 498 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 499 clsqh->elink = NULL; 500 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 501 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 502 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 504 505 /* 506 * Make all (virtual) frame list pointers point to the interrupt 507 * queue heads and the interrupt queue heads at the control 508 * queue head and point the physical frame list to the virtual. 509 */ 510 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 511 std = uhci_alloc_std(sc); 512 sqh = uhci_alloc_sqh(sc); 513 if (std == NULL || sqh == NULL) 514 return USBD_NOMEM; 515 std->link.sqh = sqh; 516 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 517 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 518 std->td.td_token = htole32(0); 519 std->td.td_buffer = htole32(0); 520 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 521 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 522 sqh->hlink = clsqh; 523 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 524 sqh->elink = NULL; 525 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 526 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 528 sc->sc_vframes[i].htd = std; 529 sc->sc_vframes[i].etd = std; 530 sc->sc_vframes[i].hqh = sqh; 531 sc->sc_vframes[i].eqh = sqh; 532 for (j = i; 533 j < UHCI_FRAMELIST_COUNT; 534 j += UHCI_VFRAMELIST_COUNT) 535 sc->sc_pframes[j] = htole32(std->physaddr); 536 } 537 usb_syncmem(&sc->sc_dma, 0, 538 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 539 BUS_DMASYNC_PREWRITE); 540 541 542 TAILQ_INIT(&sc->sc_intrhead); 543 544 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 545 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 546 547 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 548 549 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 550 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 551 cv_init(&sc->sc_softwake_cv, "uhciab"); 552 553 /* Set up the bus struct. */ 554 sc->sc_bus.ub_methods = &uhci_bus_methods; 555 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 556 sc->sc_bus.ub_usedma = true; 557 558 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 559 560 DPRINTF("Enabling...", 0, 0, 0, 0); 561 562 err = uhci_run(sc, 1, 0); /* and here we go... */ 563 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 564 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 565 return err; 566 } 567 568 int 569 uhci_activate(device_t self, enum devact act) 570 { 571 struct uhci_softc *sc = device_private(self); 572 573 switch (act) { 574 case DVACT_DEACTIVATE: 575 sc->sc_dying = 1; 576 return 0; 577 default: 578 return EOPNOTSUPP; 579 } 580 } 581 582 void 583 uhci_childdet(device_t self, device_t child) 584 { 585 struct uhci_softc *sc = device_private(self); 586 587 KASSERT(sc->sc_child == child); 588 sc->sc_child = NULL; 589 } 590 591 int 592 uhci_detach(struct uhci_softc *sc, int flags) 593 { 594 int rv = 0; 595 596 if (sc->sc_child != NULL) 597 rv = config_detach(sc->sc_child, flags); 598 599 if (rv != 0) 600 return rv; 601 602 callout_halt(&sc->sc_poll_handle, NULL); 603 callout_destroy(&sc->sc_poll_handle); 604 605 cv_destroy(&sc->sc_softwake_cv); 606 607 mutex_destroy(&sc->sc_lock); 608 mutex_destroy(&sc->sc_intr_lock); 609 610 pool_cache_destroy(sc->sc_xferpool); 611 612 /* XXX free other data structures XXX */ 613 614 return rv; 615 } 616 617 struct usbd_xfer * 618 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 619 { 620 struct uhci_softc *sc = UHCI_BUS2SC(bus); 621 struct usbd_xfer *xfer; 622 623 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 624 if (xfer != NULL) { 625 memset(xfer, 0, sizeof(struct uhci_xfer)); 626 627 #ifdef DIAGNOSTIC 628 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 629 uxfer->ux_isdone = true; 630 xfer->ux_state = XFER_BUSY; 631 #endif 632 } 633 return xfer; 634 } 635 636 void 637 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 638 { 639 struct uhci_softc *sc = UHCI_BUS2SC(bus); 640 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 641 642 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 643 xfer->ux_state); 644 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 645 #ifdef DIAGNOSTIC 646 xfer->ux_state = XFER_FREE; 647 #endif 648 pool_cache_put(sc->sc_xferpool, xfer); 649 } 650 651 Static void 652 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 653 { 654 struct uhci_softc *sc = UHCI_BUS2SC(bus); 655 656 *lock = &sc->sc_lock; 657 } 658 659 660 /* 661 * Handle suspend/resume. 662 * 663 * We need to switch to polling mode here, because this routine is 664 * called from an interrupt context. This is all right since we 665 * are almost suspended anyway. 666 */ 667 bool 668 uhci_resume(device_t dv, const pmf_qual_t *qual) 669 { 670 uhci_softc_t *sc = device_private(dv); 671 int cmd; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 cmd = UREAD2(sc, UHCI_CMD); 676 sc->sc_bus.ub_usepolling++; 677 UWRITE2(sc, UHCI_INTR, 0); 678 uhci_globalreset(sc); 679 uhci_reset(sc); 680 if (cmd & UHCI_CMD_RS) 681 uhci_run(sc, 0, 1); 682 683 /* restore saved state */ 684 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 685 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 686 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 687 688 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 689 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 690 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 691 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 692 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 693 UHCICMD(sc, UHCI_CMD_MAXP); 694 uhci_run(sc, 1, 1); /* and start traffic again */ 695 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 696 sc->sc_bus.ub_usepolling--; 697 if (sc->sc_intr_xfer != NULL) 698 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 699 sc->sc_intr_xfer); 700 #ifdef UHCI_DEBUG 701 if (uhcidebug >= 2) 702 uhci_dumpregs(sc); 703 #endif 704 705 sc->sc_suspend = PWR_RESUME; 706 mutex_spin_exit(&sc->sc_intr_lock); 707 708 return true; 709 } 710 711 bool 712 uhci_suspend(device_t dv, const pmf_qual_t *qual) 713 { 714 uhci_softc_t *sc = device_private(dv); 715 int cmd; 716 717 mutex_spin_enter(&sc->sc_intr_lock); 718 719 cmd = UREAD2(sc, UHCI_CMD); 720 721 #ifdef UHCI_DEBUG 722 if (uhcidebug >= 2) 723 uhci_dumpregs(sc); 724 #endif 725 if (sc->sc_intr_xfer != NULL) 726 callout_stop(&sc->sc_poll_handle); 727 sc->sc_suspend = PWR_SUSPEND; 728 sc->sc_bus.ub_usepolling++; 729 730 uhci_run(sc, 0, 1); /* stop the controller */ 731 cmd &= ~UHCI_CMD_RS; 732 733 /* save some state if BIOS doesn't */ 734 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 735 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 736 737 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 738 739 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 740 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 741 sc->sc_bus.ub_usepolling--; 742 743 mutex_spin_exit(&sc->sc_intr_lock); 744 745 return true; 746 } 747 748 #ifdef UHCI_DEBUG 749 Static void 750 uhci_dumpregs(uhci_softc_t *sc) 751 { 752 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 753 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 754 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 755 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 756 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 757 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 758 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 759 } 760 761 void 762 uhci_dump_td(uhci_soft_td_t *p) 763 { 764 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 765 766 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 768 769 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 770 DPRINTF(" link=0x%08x status=0x%08x " 771 "token=0x%08x buffer=0x%08x", 772 le32toh(p->td.td_link), 773 le32toh(p->td.td_status), 774 le32toh(p->td.td_token), 775 le32toh(p->td.td_buffer)); 776 777 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 778 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 779 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 780 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 781 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 782 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 783 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 784 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 785 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 786 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 787 DPRINTF("ios =%d ls =%d spd =%d", 788 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 789 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 790 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 791 DPRINTF("errcnt =%d actlen =%d pid=%02x", 792 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 793 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 794 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 795 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 796 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 797 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 798 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 799 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 800 } 801 802 void 803 uhci_dump_qh(uhci_soft_qh_t *sqh) 804 { 805 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 806 807 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 808 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 809 810 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 811 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 812 le32toh(sqh->qh.qh_elink)); 813 814 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 815 } 816 817 818 #if 1 819 void 820 uhci_dump(void) 821 { 822 uhci_dump_all(thesc); 823 } 824 #endif 825 826 void 827 uhci_dump_all(uhci_softc_t *sc) 828 { 829 uhci_dumpregs(sc); 830 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 831 uhci_dump_qhs(sc->sc_lctl_start); 832 } 833 834 835 void 836 uhci_dump_qhs(uhci_soft_qh_t *sqh) 837 { 838 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 839 840 uhci_dump_qh(sqh); 841 842 /* 843 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 844 * Traverses sideways first, then down. 845 * 846 * QH1 847 * QH2 848 * No QH 849 * TD2.1 850 * TD2.2 851 * TD1.1 852 * etc. 853 * 854 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 855 */ 856 857 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 858 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 859 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 860 uhci_dump_qhs(sqh->hlink); 861 else 862 DPRINTF("No QH", 0, 0, 0, 0); 863 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 864 865 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 866 uhci_dump_tds(sqh->elink); 867 else 868 DPRINTF("No QH", 0, 0, 0, 0); 869 } 870 871 void 872 uhci_dump_tds(uhci_soft_td_t *std) 873 { 874 uhci_soft_td_t *td; 875 int stop; 876 877 for (td = std; td != NULL; td = td->link.std) { 878 uhci_dump_td(td); 879 880 /* 881 * Check whether the link pointer in this TD marks 882 * the link pointer as end of queue. This avoids 883 * printing the free list in case the queue/TD has 884 * already been moved there (seatbelt). 885 */ 886 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 887 sizeof(td->td.td_link), 888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 889 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 890 le32toh(td->td.td_link) == 0); 891 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 892 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 893 if (stop) 894 break; 895 } 896 } 897 898 Static void 899 uhci_dump_ii(struct uhci_xfer *ux) 900 { 901 struct usbd_pipe *pipe; 902 usb_endpoint_descriptor_t *ed; 903 struct usbd_device *dev; 904 905 if (ux == NULL) { 906 printf("ux NULL\n"); 907 return; 908 } 909 pipe = ux->ux_xfer.ux_pipe; 910 if (pipe == NULL) { 911 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 912 return; 913 } 914 if (pipe->up_endpoint == NULL) { 915 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 916 ux, ux->ux_isdone, pipe); 917 return; 918 } 919 if (pipe->up_dev == NULL) { 920 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 921 ux, ux->ux_isdone, pipe); 922 return; 923 } 924 ed = pipe->up_endpoint->ue_edesc; 925 dev = pipe->up_dev; 926 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 927 ux, ux->ux_isdone, dev, 928 UGETW(dev->ud_ddesc.idVendor), 929 UGETW(dev->ud_ddesc.idProduct), 930 dev->ud_addr, pipe, 931 ed->bEndpointAddress, ed->bmAttributes); 932 } 933 934 void uhci_dump_iis(struct uhci_softc *sc); 935 void 936 uhci_dump_iis(struct uhci_softc *sc) 937 { 938 struct uhci_xfer *ux; 939 940 printf("interrupt list:\n"); 941 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = TAILQ_NEXT(ux, ux_list)) 942 uhci_dump_ii(ux); 943 } 944 945 void iidump(void); 946 void iidump(void) { uhci_dump_iis(thesc); } 947 948 #endif 949 950 /* 951 * This routine is executed periodically and simulates interrupts 952 * from the root controller interrupt pipe for port status change. 953 */ 954 void 955 uhci_poll_hub(void *addr) 956 { 957 struct usbd_xfer *xfer = addr; 958 struct usbd_pipe *pipe = xfer->ux_pipe; 959 uhci_softc_t *sc; 960 u_char *p; 961 962 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 963 964 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 965 return; /* device has detached */ 966 sc = UHCI_PIPE2SC(pipe); 967 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 968 969 p = xfer->ux_buf; 970 p[0] = 0; 971 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 972 p[0] |= 1<<1; 973 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 974 p[0] |= 1<<2; 975 if (p[0] == 0) 976 /* No change, try again in a while */ 977 return; 978 979 xfer->ux_actlen = 1; 980 xfer->ux_status = USBD_NORMAL_COMPLETION; 981 mutex_enter(&sc->sc_lock); 982 usb_transfer_complete(xfer); 983 mutex_exit(&sc->sc_lock); 984 } 985 986 void 987 uhci_root_intr_done(struct usbd_xfer *xfer) 988 { 989 } 990 991 /* 992 * Let the last QH loop back to the high speed control transfer QH. 993 * This is what intel calls "bandwidth reclamation" and improves 994 * USB performance a lot for some devices. 995 * If we are already looping, just count it. 996 */ 997 void 998 uhci_add_loop(uhci_softc_t *sc) 999 { 1000 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1001 1002 #ifdef UHCI_DEBUG 1003 if (uhcinoloop) 1004 return; 1005 #endif 1006 if (++sc->sc_loops == 1) { 1007 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1008 /* Note, we don't loop back the soft pointer. */ 1009 sc->sc_last_qh->qh.qh_hlink = 1010 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1011 usb_syncmem(&sc->sc_last_qh->dma, 1012 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1013 sizeof(sc->sc_last_qh->qh.qh_hlink), 1014 BUS_DMASYNC_PREWRITE); 1015 } 1016 } 1017 1018 void 1019 uhci_rem_loop(uhci_softc_t *sc) 1020 { 1021 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1022 1023 #ifdef UHCI_DEBUG 1024 if (uhcinoloop) 1025 return; 1026 #endif 1027 if (--sc->sc_loops == 0) { 1028 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1029 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1030 usb_syncmem(&sc->sc_last_qh->dma, 1031 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1032 sizeof(sc->sc_last_qh->qh.qh_hlink), 1033 BUS_DMASYNC_PREWRITE); 1034 } 1035 } 1036 1037 /* Add high speed control QH, called with lock held. */ 1038 void 1039 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1040 { 1041 uhci_soft_qh_t *eqh; 1042 1043 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1044 1045 KASSERT(mutex_owned(&sc->sc_lock)); 1046 1047 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1048 eqh = sc->sc_hctl_end; 1049 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1050 sizeof(eqh->qh.qh_hlink), 1051 BUS_DMASYNC_POSTWRITE); 1052 sqh->hlink = eqh->hlink; 1053 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1054 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1055 BUS_DMASYNC_PREWRITE); 1056 eqh->hlink = sqh; 1057 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1058 sc->sc_hctl_end = sqh; 1059 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1060 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1061 #ifdef UHCI_CTL_LOOP 1062 uhci_add_loop(sc); 1063 #endif 1064 } 1065 1066 /* Remove high speed control QH, called with lock held. */ 1067 void 1068 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1069 { 1070 uhci_soft_qh_t *pqh; 1071 uint32_t elink; 1072 1073 KASSERT(mutex_owned(&sc->sc_lock)); 1074 1075 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1076 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1077 #ifdef UHCI_CTL_LOOP 1078 uhci_rem_loop(sc); 1079 #endif 1080 /* 1081 * The T bit should be set in the elink of the QH so that the HC 1082 * doesn't follow the pointer. This condition may fail if the 1083 * the transferred packet was short so that the QH still points 1084 * at the last used TD. 1085 * In this case we set the T bit and wait a little for the HC 1086 * to stop looking at the TD. 1087 * Note that if the TD chain is large enough, the controller 1088 * may still be looking at the chain at the end of this function. 1089 * uhci_free_std_chain() will make sure the controller stops 1090 * looking at it quickly, but until then we should not change 1091 * sqh->hlink. 1092 */ 1093 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1094 sizeof(sqh->qh.qh_elink), 1095 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1096 elink = le32toh(sqh->qh.qh_elink); 1097 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1098 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1099 if (!(elink & UHCI_PTR_T)) { 1100 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1101 usb_syncmem(&sqh->dma, 1102 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1103 sizeof(sqh->qh.qh_elink), 1104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1105 delay(UHCI_QH_REMOVE_DELAY); 1106 } 1107 1108 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1109 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1110 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1111 pqh->hlink = sqh->hlink; 1112 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1113 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1114 sizeof(pqh->qh.qh_hlink), 1115 BUS_DMASYNC_PREWRITE); 1116 delay(UHCI_QH_REMOVE_DELAY); 1117 if (sc->sc_hctl_end == sqh) 1118 sc->sc_hctl_end = pqh; 1119 } 1120 1121 /* Add low speed control QH, called with lock held. */ 1122 void 1123 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1124 { 1125 uhci_soft_qh_t *eqh; 1126 1127 KASSERT(mutex_owned(&sc->sc_lock)); 1128 1129 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1130 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1131 1132 eqh = sc->sc_lctl_end; 1133 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1134 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1135 sqh->hlink = eqh->hlink; 1136 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1137 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1138 BUS_DMASYNC_PREWRITE); 1139 eqh->hlink = sqh; 1140 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1141 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1142 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1143 sc->sc_lctl_end = sqh; 1144 } 1145 1146 /* Remove low speed control QH, called with lock held. */ 1147 void 1148 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1149 { 1150 uhci_soft_qh_t *pqh; 1151 uint32_t elink; 1152 1153 KASSERT(mutex_owned(&sc->sc_lock)); 1154 1155 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1156 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1157 1158 /* See comment in uhci_remove_hs_ctrl() */ 1159 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1160 sizeof(sqh->qh.qh_elink), 1161 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1162 elink = le32toh(sqh->qh.qh_elink); 1163 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1164 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1165 if (!(elink & UHCI_PTR_T)) { 1166 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1167 usb_syncmem(&sqh->dma, 1168 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1169 sizeof(sqh->qh.qh_elink), 1170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1171 delay(UHCI_QH_REMOVE_DELAY); 1172 } 1173 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1175 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1176 pqh->hlink = sqh->hlink; 1177 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1178 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1179 sizeof(pqh->qh.qh_hlink), 1180 BUS_DMASYNC_PREWRITE); 1181 delay(UHCI_QH_REMOVE_DELAY); 1182 if (sc->sc_lctl_end == sqh) 1183 sc->sc_lctl_end = pqh; 1184 } 1185 1186 /* Add bulk QH, called with lock held. */ 1187 void 1188 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1189 { 1190 uhci_soft_qh_t *eqh; 1191 1192 KASSERT(mutex_owned(&sc->sc_lock)); 1193 1194 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1195 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1196 1197 eqh = sc->sc_bulk_end; 1198 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1199 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1200 sqh->hlink = eqh->hlink; 1201 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1202 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1203 BUS_DMASYNC_PREWRITE); 1204 eqh->hlink = sqh; 1205 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1206 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1207 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1208 sc->sc_bulk_end = sqh; 1209 uhci_add_loop(sc); 1210 } 1211 1212 /* Remove bulk QH, called with lock held. */ 1213 void 1214 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1215 { 1216 uhci_soft_qh_t *pqh; 1217 1218 KASSERT(mutex_owned(&sc->sc_lock)); 1219 1220 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1221 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1222 1223 uhci_rem_loop(sc); 1224 /* See comment in uhci_remove_hs_ctrl() */ 1225 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1226 sizeof(sqh->qh.qh_elink), 1227 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1228 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1229 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1230 usb_syncmem(&sqh->dma, 1231 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1232 sizeof(sqh->qh.qh_elink), 1233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1234 delay(UHCI_QH_REMOVE_DELAY); 1235 } 1236 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1237 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1238 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1239 pqh->hlink = sqh->hlink; 1240 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1241 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1242 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1243 delay(UHCI_QH_REMOVE_DELAY); 1244 if (sc->sc_bulk_end == sqh) 1245 sc->sc_bulk_end = pqh; 1246 } 1247 1248 Static int uhci_intr1(uhci_softc_t *); 1249 1250 int 1251 uhci_intr(void *arg) 1252 { 1253 uhci_softc_t *sc = arg; 1254 int ret = 0; 1255 1256 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 1260 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1261 goto done; 1262 1263 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1264 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1265 goto done; 1266 } 1267 1268 ret = uhci_intr1(sc); 1269 1270 done: 1271 mutex_spin_exit(&sc->sc_intr_lock); 1272 return ret; 1273 } 1274 1275 int 1276 uhci_intr1(uhci_softc_t *sc) 1277 { 1278 int status; 1279 int ack; 1280 1281 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1282 1283 #ifdef UHCI_DEBUG 1284 if (uhcidebug > 15) { 1285 DPRINTF("sc %p", sc, 0, 0, 0); 1286 uhci_dumpregs(sc); 1287 } 1288 #endif 1289 1290 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1291 1292 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1293 if (status == 0) /* The interrupt was not for us. */ 1294 return 0; 1295 1296 if (sc->sc_suspend != PWR_RESUME) { 1297 #ifdef DIAGNOSTIC 1298 printf("%s: interrupt while not operating ignored\n", 1299 device_xname(sc->sc_dev)); 1300 #endif 1301 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1302 return 0; 1303 } 1304 1305 ack = 0; 1306 if (status & UHCI_STS_USBINT) 1307 ack |= UHCI_STS_USBINT; 1308 if (status & UHCI_STS_USBEI) 1309 ack |= UHCI_STS_USBEI; 1310 if (status & UHCI_STS_RD) { 1311 ack |= UHCI_STS_RD; 1312 #ifdef UHCI_DEBUG 1313 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1314 #endif 1315 } 1316 if (status & UHCI_STS_HSE) { 1317 ack |= UHCI_STS_HSE; 1318 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1319 } 1320 if (status & UHCI_STS_HCPE) { 1321 ack |= UHCI_STS_HCPE; 1322 printf("%s: host controller process error\n", 1323 device_xname(sc->sc_dev)); 1324 } 1325 1326 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1327 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1328 /* no acknowledge needed */ 1329 if (!sc->sc_dying) { 1330 printf("%s: host controller halted\n", 1331 device_xname(sc->sc_dev)); 1332 #ifdef UHCI_DEBUG 1333 uhci_dump_all(sc); 1334 #endif 1335 } 1336 sc->sc_dying = 1; 1337 } 1338 1339 if (!ack) 1340 return 0; /* nothing to acknowledge */ 1341 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1342 1343 usb_schedsoftintr(&sc->sc_bus); 1344 1345 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1346 1347 return 1; 1348 } 1349 1350 void 1351 uhci_softintr(void *v) 1352 { 1353 struct usbd_bus *bus = v; 1354 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1355 struct uhci_xfer *ux, *nextux; 1356 1357 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1358 DPRINTF("sc %p", sc, 0, 0, 0); 1359 1360 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1361 1362 /* 1363 * Interrupts on UHCI really suck. When the host controller 1364 * interrupts because a transfer is completed there is no 1365 * way of knowing which transfer it was. You can scan down 1366 * the TDs and QHs of the previous frame to limit the search, 1367 * but that assumes that the interrupt was not delayed by more 1368 * than 1 ms, which may not always be true (e.g. after debug 1369 * output on a slow console). 1370 * We scan all interrupt descriptors to see if any have 1371 * completed. 1372 */ 1373 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) { 1374 nextux = TAILQ_NEXT(ux, ux_list); 1375 uhci_check_intr(sc, ux); 1376 } 1377 1378 if (sc->sc_softwake) { 1379 sc->sc_softwake = 0; 1380 cv_broadcast(&sc->sc_softwake_cv); 1381 } 1382 } 1383 1384 /* Check for an interrupt. */ 1385 void 1386 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux) 1387 { 1388 uhci_soft_td_t *std, *lstd; 1389 uint32_t status; 1390 1391 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1392 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1393 1394 KASSERT(ux != NULL); 1395 1396 struct usbd_xfer *xfer = &ux->ux_xfer; 1397 if (xfer->ux_status == USBD_CANCELLED || 1398 xfer->ux_status == USBD_TIMEOUT) { 1399 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1400 return; 1401 } 1402 1403 if (ux->ux_stdstart == NULL) 1404 return; 1405 lstd = ux->ux_stdend; 1406 1407 KASSERT(lstd != NULL); 1408 1409 usb_syncmem(&lstd->dma, 1410 lstd->offs + offsetof(uhci_td_t, td_status), 1411 sizeof(lstd->td.td_status), 1412 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1413 status = le32toh(lstd->td.td_status); 1414 usb_syncmem(&lstd->dma, 1415 lstd->offs + offsetof(uhci_td_t, td_status), 1416 sizeof(lstd->td.td_status), 1417 BUS_DMASYNC_PREREAD); 1418 1419 /* If the last TD is not marked active we can complete */ 1420 if (!(status & UHCI_TD_ACTIVE)) { 1421 done: 1422 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1423 1424 callout_stop(&xfer->ux_callout); 1425 uhci_idone(ux); 1426 return; 1427 } 1428 1429 /* 1430 * If the last TD is still active we need to check whether there 1431 * is an error somewhere in the middle, or whether there was a 1432 * short packet (SPD and not ACTIVE). 1433 */ 1434 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1435 for (std = ux->ux_stdstart; std != lstd; std = std->link.std) { 1436 usb_syncmem(&std->dma, 1437 std->offs + offsetof(uhci_td_t, td_status), 1438 sizeof(std->td.td_status), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 status = le32toh(std->td.td_status); 1441 usb_syncmem(&std->dma, 1442 std->offs + offsetof(uhci_td_t, td_status), 1443 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1444 1445 /* If there's an active TD the xfer isn't done. */ 1446 if (status & UHCI_TD_ACTIVE) { 1447 DPRINTFN(12, "ux=%p std=%p still active", 1448 ux, std, 0, 0); 1449 return; 1450 } 1451 1452 /* Any kind of error makes the xfer done. */ 1453 if (status & UHCI_TD_STALLED) 1454 goto done; 1455 1456 /* 1457 * If the data phase of a control transfer is short, we need 1458 * to complete the status stage 1459 */ 1460 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1461 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1462 1463 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1464 struct uhci_pipe *upipe = 1465 (struct uhci_pipe *)xfer->ux_pipe; 1466 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1467 uhci_soft_td_t *stat = upipe->ctrl.stat; 1468 1469 DPRINTFN(12, "ux=%p std=%p control status" 1470 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1471 1472 sqh->qh.qh_elink = 1473 htole32(stat->physaddr | UHCI_PTR_TD); 1474 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1475 BUS_DMASYNC_PREWRITE); 1476 break; 1477 } 1478 1479 /* We want short packets, and it is short: it's done */ 1480 usb_syncmem(&std->dma, 1481 std->offs + offsetof(uhci_td_t, td_token), 1482 sizeof(std->td.td_token), 1483 BUS_DMASYNC_POSTWRITE); 1484 1485 if ((status & UHCI_TD_SPD) && 1486 UHCI_TD_GET_ACTLEN(status) < 1487 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1488 goto done; 1489 } 1490 } 1491 } 1492 1493 /* Called with USB lock held. */ 1494 void 1495 uhci_idone(struct uhci_xfer *ux) 1496 { 1497 struct usbd_xfer *xfer = &ux->ux_xfer; 1498 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1499 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 1500 uhci_soft_td_t *std; 1501 uint32_t status = 0, nstatus; 1502 int actlen; 1503 1504 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1505 1506 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1507 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1508 1509 #ifdef DIAGNOSTIC 1510 #ifdef UHCI_DEBUG 1511 if (ux->ux_isdone) { 1512 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1513 uhci_dump_ii(ux); 1514 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1515 } 1516 #endif 1517 KASSERT(!ux->ux_isdone); 1518 ux->ux_isdone = true; 1519 #endif 1520 1521 if (xfer->ux_nframes != 0) { 1522 /* Isoc transfer, do things differently. */ 1523 uhci_soft_td_t **stds = upipe->isoc.stds; 1524 int i, n, nframes, len; 1525 1526 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1527 1528 nframes = xfer->ux_nframes; 1529 actlen = 0; 1530 n = UHCI_XFER2UXFER(xfer)->ux_curframe; 1531 for (i = 0; i < nframes; i++) { 1532 std = stds[n]; 1533 #ifdef UHCI_DEBUG 1534 if (uhcidebug >= 5) { 1535 DPRINTF("isoc TD %d", i, 0, 0, 0); 1536 uhci_dump_td(std); 1537 } 1538 #endif 1539 if (++n >= UHCI_VFRAMELIST_COUNT) 1540 n = 0; 1541 usb_syncmem(&std->dma, 1542 std->offs + offsetof(uhci_td_t, td_status), 1543 sizeof(std->td.td_status), 1544 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1545 status = le32toh(std->td.td_status); 1546 len = UHCI_TD_GET_ACTLEN(status); 1547 xfer->ux_frlengths[i] = len; 1548 actlen += len; 1549 } 1550 upipe->isoc.inuse -= nframes; 1551 xfer->ux_actlen = actlen; 1552 xfer->ux_status = USBD_NORMAL_COMPLETION; 1553 goto end; 1554 } 1555 1556 #ifdef UHCI_DEBUG 1557 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", 1558 ux, xfer, upipe, 0); 1559 if (uhcidebug >= 10) 1560 uhci_dump_tds(ux->ux_stdstart); 1561 #endif 1562 1563 /* The transfer is done, compute actual length and status. */ 1564 actlen = 0; 1565 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1566 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1567 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1568 nstatus = le32toh(std->td.td_status); 1569 if (nstatus & UHCI_TD_ACTIVE) 1570 break; 1571 1572 status = nstatus; 1573 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1574 UHCI_TD_PID_SETUP) 1575 actlen += UHCI_TD_GET_ACTLEN(status); 1576 else { 1577 /* 1578 * UHCI will report CRCTO in addition to a STALL or NAK 1579 * for a SETUP transaction. See section 3.2.2, "TD 1580 * CONTROL AND STATUS". 1581 */ 1582 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1583 status &= ~UHCI_TD_CRCTO; 1584 } 1585 } 1586 /* If there are left over TDs we need to update the toggle. */ 1587 if (std != NULL) 1588 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1589 1590 status &= UHCI_TD_ERROR; 1591 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1592 xfer->ux_actlen = actlen; 1593 if (status != 0) { 1594 1595 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1596 "error, addr=%d, endpt=0x%02x", 1597 xfer->ux_pipe->up_dev->ud_addr, 1598 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1599 0, 0); 1600 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1601 "bitstuff=%d crcto =%d nak =%d babble =%d", 1602 !!(status & UHCI_TD_BITSTUFF), 1603 !!(status & UHCI_TD_CRCTO), 1604 !!(status & UHCI_TD_NAK), 1605 !!(status & UHCI_TD_BABBLE)); 1606 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1607 "dbuffer =%d stalled =%d active =%d", 1608 !!(status & UHCI_TD_DBUFFER), 1609 !!(status & UHCI_TD_STALLED), 1610 !!(status & UHCI_TD_ACTIVE), 1611 0); 1612 1613 if (status == UHCI_TD_STALLED) 1614 xfer->ux_status = USBD_STALLED; 1615 else 1616 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1617 } else { 1618 xfer->ux_status = USBD_NORMAL_COMPLETION; 1619 } 1620 1621 end: 1622 usb_transfer_complete(xfer); 1623 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1624 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1625 } 1626 1627 /* 1628 * Called when a request does not complete. 1629 */ 1630 void 1631 uhci_timeout(void *addr) 1632 { 1633 struct usbd_xfer *xfer = addr; 1634 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1635 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1636 1637 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1638 1639 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1640 1641 if (sc->sc_dying) { 1642 mutex_enter(&sc->sc_lock); 1643 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1644 mutex_exit(&sc->sc_lock); 1645 return; 1646 } 1647 1648 /* Execute the abort in a process context. */ 1649 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1650 USB_TASKQ_MPSAFE); 1651 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1652 USB_TASKQ_HC); 1653 } 1654 1655 void 1656 uhci_timeout_task(void *addr) 1657 { 1658 struct usbd_xfer *xfer = addr; 1659 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1660 1661 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1662 1663 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1664 1665 mutex_enter(&sc->sc_lock); 1666 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1667 mutex_exit(&sc->sc_lock); 1668 } 1669 1670 /* 1671 * Wait here until controller claims to have an interrupt. 1672 * Then call uhci_intr and return. Use timeout to avoid waiting 1673 * too long. 1674 * Only used during boot when interrupts are not enabled yet. 1675 */ 1676 void 1677 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1678 { 1679 int timo = xfer->ux_timeout; 1680 struct uhci_xfer *ux; 1681 1682 mutex_enter(&sc->sc_lock); 1683 1684 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1685 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1686 1687 xfer->ux_status = USBD_IN_PROGRESS; 1688 for (; timo >= 0; timo--) { 1689 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1690 DPRINTFN(20, "0x%04x", 1691 UREAD2(sc, UHCI_STS), 0, 0, 0); 1692 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1693 mutex_spin_enter(&sc->sc_intr_lock); 1694 uhci_intr1(sc); 1695 mutex_spin_exit(&sc->sc_intr_lock); 1696 if (xfer->ux_status != USBD_IN_PROGRESS) 1697 goto done; 1698 } 1699 } 1700 1701 /* Timeout */ 1702 DPRINTF("timeout", 0, 0, 0, 0); 1703 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux != NULL; 1704 ux = TAILQ_NEXT(ux, ux_list)) 1705 if (&ux->ux_xfer == xfer) 1706 break; 1707 1708 KASSERT(ux != NULL); 1709 1710 uhci_idone(ux); 1711 1712 done: 1713 mutex_exit(&sc->sc_lock); 1714 } 1715 1716 void 1717 uhci_poll(struct usbd_bus *bus) 1718 { 1719 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1720 1721 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1722 mutex_spin_enter(&sc->sc_intr_lock); 1723 uhci_intr1(sc); 1724 mutex_spin_exit(&sc->sc_intr_lock); 1725 } 1726 } 1727 1728 void 1729 uhci_reset(uhci_softc_t *sc) 1730 { 1731 int n; 1732 1733 UHCICMD(sc, UHCI_CMD_HCRESET); 1734 /* The reset bit goes low when the controller is done. */ 1735 for (n = 0; n < UHCI_RESET_TIMEOUT && 1736 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1737 usb_delay_ms(&sc->sc_bus, 1); 1738 if (n >= UHCI_RESET_TIMEOUT) 1739 printf("%s: controller did not reset\n", 1740 device_xname(sc->sc_dev)); 1741 } 1742 1743 usbd_status 1744 uhci_run(uhci_softc_t *sc, int run, int locked) 1745 { 1746 int n, running; 1747 uint16_t cmd; 1748 1749 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1750 1751 run = run != 0; 1752 if (!locked) 1753 mutex_spin_enter(&sc->sc_intr_lock); 1754 1755 DPRINTF("setting run=%d", run, 0, 0, 0); 1756 cmd = UREAD2(sc, UHCI_CMD); 1757 if (run) 1758 cmd |= UHCI_CMD_RS; 1759 else 1760 cmd &= ~UHCI_CMD_RS; 1761 UHCICMD(sc, cmd); 1762 for(n = 0; n < 10; n++) { 1763 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1764 /* return when we've entered the state we want */ 1765 if (run == running) { 1766 if (!locked) 1767 mutex_spin_exit(&sc->sc_intr_lock); 1768 DPRINTF("done cmd=0x%x sts=0x%x", 1769 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1770 return USBD_NORMAL_COMPLETION; 1771 } 1772 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1773 } 1774 if (!locked) 1775 mutex_spin_exit(&sc->sc_intr_lock); 1776 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1777 run ? "start" : "stop"); 1778 return USBD_IOERROR; 1779 } 1780 1781 /* 1782 * Memory management routines. 1783 * uhci_alloc_std allocates TDs 1784 * uhci_alloc_sqh allocates QHs 1785 * These two routines do their own free list management, 1786 * partly for speed, partly because allocating DMAable memory 1787 * has page size granularity so much memory would be wasted if 1788 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1789 */ 1790 1791 uhci_soft_td_t * 1792 uhci_alloc_std(uhci_softc_t *sc) 1793 { 1794 uhci_soft_td_t *std; 1795 usbd_status err; 1796 int i, offs; 1797 usb_dma_t dma; 1798 1799 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1800 1801 if (sc->sc_freetds == NULL) { 1802 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1803 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1804 UHCI_TD_ALIGN, &dma); 1805 if (err) 1806 return 0; 1807 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1808 offs = i * UHCI_STD_SIZE; 1809 std = KERNADDR(&dma, offs); 1810 std->physaddr = DMAADDR(&dma, offs); 1811 std->dma = dma; 1812 std->offs = offs; 1813 std->link.std = sc->sc_freetds; 1814 sc->sc_freetds = std; 1815 } 1816 } 1817 std = sc->sc_freetds; 1818 sc->sc_freetds = std->link.std; 1819 memset(&std->td, 0, sizeof(uhci_td_t)); 1820 return std; 1821 } 1822 1823 void 1824 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1825 { 1826 #ifdef DIAGNOSTIC 1827 #define TD_IS_FREE 0x12345678 1828 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1829 printf("uhci_free_std: freeing free TD %p\n", std); 1830 return; 1831 } 1832 std->td.td_token = htole32(TD_IS_FREE); 1833 #endif 1834 std->link.std = sc->sc_freetds; 1835 sc->sc_freetds = std; 1836 } 1837 1838 uhci_soft_qh_t * 1839 uhci_alloc_sqh(uhci_softc_t *sc) 1840 { 1841 uhci_soft_qh_t *sqh; 1842 usbd_status err; 1843 int i, offs; 1844 usb_dma_t dma; 1845 1846 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1847 1848 if (sc->sc_freeqhs == NULL) { 1849 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1850 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1851 UHCI_QH_ALIGN, &dma); 1852 if (err) 1853 return 0; 1854 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1855 offs = i * UHCI_SQH_SIZE; 1856 sqh = KERNADDR(&dma, offs); 1857 sqh->physaddr = DMAADDR(&dma, offs); 1858 sqh->dma = dma; 1859 sqh->offs = offs; 1860 sqh->hlink = sc->sc_freeqhs; 1861 sc->sc_freeqhs = sqh; 1862 } 1863 } 1864 sqh = sc->sc_freeqhs; 1865 sc->sc_freeqhs = sqh->hlink; 1866 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1867 return sqh; 1868 } 1869 1870 void 1871 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1872 { 1873 sqh->hlink = sc->sc_freeqhs; 1874 sc->sc_freeqhs = sqh; 1875 } 1876 1877 void 1878 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1879 uhci_soft_td_t *stdend) 1880 { 1881 uhci_soft_td_t *p; 1882 uint32_t td_link; 1883 1884 /* 1885 * to avoid race condition with the controller which may be looking 1886 * at this chain, we need to first invalidate all links, and 1887 * then wait for the controller to move to another queue 1888 */ 1889 for (p = std; p != stdend; p = p->link.std) { 1890 usb_syncmem(&p->dma, 1891 p->offs + offsetof(uhci_td_t, td_link), 1892 sizeof(p->td.td_link), 1893 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1894 td_link = le32toh(p->td.td_link); 1895 usb_syncmem(&p->dma, 1896 p->offs + offsetof(uhci_td_t, td_link), 1897 sizeof(p->td.td_link), 1898 BUS_DMASYNC_PREREAD); 1899 if ((td_link & UHCI_PTR_T) == 0) { 1900 p->td.td_link = htole32(UHCI_PTR_T); 1901 usb_syncmem(&p->dma, 1902 p->offs + offsetof(uhci_td_t, td_link), 1903 sizeof(p->td.td_link), 1904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1905 } 1906 } 1907 delay(UHCI_QH_REMOVE_DELAY); 1908 1909 for (; std != stdend; std = p) { 1910 p = std->link.std; 1911 uhci_free_std(sc, std); 1912 } 1913 } 1914 1915 usbd_status 1916 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1917 int rd, uint16_t flags, usb_dma_t *dma, 1918 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1919 { 1920 uhci_soft_td_t *p, *lastp; 1921 uhci_physaddr_t lastlink; 1922 int i, ntd, l, tog, maxp; 1923 uint32_t status; 1924 int addr = upipe->pipe.up_dev->ud_addr; 1925 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1926 1927 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1928 1929 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 1930 addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed); 1931 1932 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1933 1934 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1935 if (maxp == 0) { 1936 printf("uhci_alloc_std_chain: maxp=0\n"); 1937 return USBD_INVAL; 1938 } 1939 ntd = (len + maxp - 1) / maxp; 1940 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1941 ntd++; 1942 DPRINTFN(10, "maxp=%d ntd=%d", 1943 maxp, ntd, 0, 0); 1944 1945 if (ntd == 0) { 1946 *sp = *ep = NULL; 1947 DPRINTF("ntd=0", 0, 0, 0, 0); 1948 return USBD_NORMAL_COMPLETION; 1949 } 1950 tog = upipe->nexttoggle; 1951 if (ntd % 2 == 0) 1952 tog ^= 1; 1953 upipe->nexttoggle = tog ^ 1; 1954 lastp = NULL; 1955 lastlink = UHCI_PTR_T; 1956 ntd--; 1957 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1958 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1959 status |= UHCI_TD_LS; 1960 if (flags & USBD_SHORT_XFER_OK) 1961 status |= UHCI_TD_SPD; 1962 usb_syncmem(dma, 0, len, 1963 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1964 for (i = ntd; i >= 0; i--) { 1965 p = uhci_alloc_std(sc); 1966 if (p == NULL) { 1967 KASSERT(lastp != NULL); 1968 uhci_free_std_chain(sc, lastp, NULL); 1969 return USBD_NOMEM; 1970 } 1971 p->link.std = lastp; 1972 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1973 lastp = p; 1974 lastlink = p->physaddr; 1975 p->td.td_status = htole32(status); 1976 if (i == ntd) { 1977 /* last TD */ 1978 l = len % maxp; 1979 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1980 l = maxp; 1981 *ep = p; 1982 } else 1983 l = maxp; 1984 p->td.td_token = 1985 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1986 UHCI_TD_OUT(l, endpt, addr, tog)); 1987 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1988 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1989 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1990 tog ^= 1; 1991 } 1992 *sp = lastp; 1993 DPRINTFN(10, "nexttog=%d", upipe->nexttoggle, 1994 0, 0, 0); 1995 1996 return USBD_NORMAL_COMPLETION; 1997 } 1998 1999 void 2000 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2001 { 2002 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2003 upipe->nexttoggle = 0; 2004 } 2005 2006 void 2007 uhci_noop(struct usbd_pipe *pipe) 2008 { 2009 } 2010 2011 usbd_status 2012 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2013 { 2014 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2015 usbd_status err; 2016 2017 /* Insert last in queue. */ 2018 mutex_enter(&sc->sc_lock); 2019 err = usb_insert_transfer(xfer); 2020 mutex_exit(&sc->sc_lock); 2021 if (err) 2022 return err; 2023 2024 /* 2025 * Pipe isn't running (otherwise err would be USBD_INPROG), 2026 * so start it first. 2027 */ 2028 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2029 } 2030 2031 usbd_status 2032 uhci_device_bulk_start(struct usbd_xfer *xfer) 2033 { 2034 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2035 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2036 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2037 uhci_soft_td_t *data, *dataend; 2038 uhci_soft_qh_t *sqh; 2039 usbd_status err; 2040 int len, isread, endpt; 2041 2042 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2043 DPRINTFN(3, "xfer=%p len=%d flags=%d ux=%p", 2044 xfer, xfer->ux_length, xfer->ux_flags, ux); 2045 2046 if (sc->sc_dying) 2047 return USBD_IOERROR; 2048 2049 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2050 2051 mutex_enter(&sc->sc_lock); 2052 2053 len = xfer->ux_length; 2054 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2055 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2056 sqh = upipe->bulk.sqh; 2057 2058 upipe->bulk.isread = isread; 2059 upipe->bulk.length = len; 2060 2061 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2062 &xfer->ux_dmabuf, &data, &dataend); 2063 if (err) { 2064 mutex_exit(&sc->sc_lock); 2065 return err; 2066 } 2067 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2068 usb_syncmem(&dataend->dma, 2069 dataend->offs + offsetof(uhci_td_t, td_status), 2070 sizeof(dataend->td.td_status), 2071 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2072 2073 2074 #ifdef UHCI_DEBUG 2075 if (uhcidebug >= 8) { 2076 DPRINTFN(8, "data(1)", 0, 0, 0, 0); 2077 uhci_dump_tds(data); 2078 } 2079 #endif 2080 2081 /* Set up interrupt info. */ 2082 ux->ux_stdstart = data; 2083 ux->ux_stdend = dataend; 2084 2085 KASSERT(ux->ux_isdone); 2086 #ifdef DIAGNOSTIC 2087 ux->ux_isdone = false; 2088 #endif 2089 2090 sqh->elink = data; 2091 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2092 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2093 2094 uhci_add_bulk(sc, sqh); 2095 uhci_add_intr_info(sc, ux); 2096 2097 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2098 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2099 uhci_timeout, xfer); 2100 } 2101 xfer->ux_status = USBD_IN_PROGRESS; 2102 2103 #ifdef UHCI_DEBUG 2104 if (uhcidebug >= 10) { 2105 DPRINTFN(10, "data(2)", 0, 0, 0, 0); 2106 uhci_dump_tds(data); 2107 } 2108 #endif 2109 2110 if (sc->sc_bus.ub_usepolling) 2111 uhci_waitintr(sc, xfer); 2112 2113 mutex_exit(&sc->sc_lock); 2114 return USBD_IN_PROGRESS; 2115 } 2116 2117 /* Abort a device bulk request. */ 2118 void 2119 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2120 { 2121 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2122 2123 KASSERT(mutex_owned(&sc->sc_lock)); 2124 2125 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2126 2127 uhci_abort_xfer(xfer, USBD_CANCELLED); 2128 } 2129 2130 /* 2131 * Abort a device request. 2132 * If this routine is called at splusb() it guarantees that the request 2133 * will be removed from the hardware scheduling and that the callback 2134 * for it will be called with USBD_CANCELLED status. 2135 * It's impossible to guarantee that the requested transfer will not 2136 * have happened since the hardware runs concurrently. 2137 * If the transaction has already happened we rely on the ordinary 2138 * interrupt processing to process it. 2139 * XXX This is most probably wrong. 2140 * XXXMRG this doesn't make sense anymore. 2141 */ 2142 void 2143 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2144 { 2145 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2146 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2147 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2148 uhci_soft_td_t *std; 2149 int wake; 2150 2151 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2152 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2153 2154 KASSERT(mutex_owned(&sc->sc_lock)); 2155 ASSERT_SLEEPABLE(); 2156 2157 if (sc->sc_dying) { 2158 /* If we're dying, just do the software part. */ 2159 xfer->ux_status = status; /* make software ignore it */ 2160 callout_stop(&xfer->ux_callout); 2161 usb_transfer_complete(xfer); 2162 return; 2163 } 2164 2165 /* 2166 * If an abort is already in progress then just wait for it to 2167 * complete and return. 2168 */ 2169 if (xfer->ux_hcflags & UXFER_ABORTING) { 2170 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2171 #ifdef DIAGNOSTIC 2172 if (status == USBD_TIMEOUT) 2173 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2174 #endif 2175 /* Override the status which might be USBD_TIMEOUT. */ 2176 xfer->ux_status = status; 2177 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2178 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2179 while (xfer->ux_hcflags & UXFER_ABORTING) 2180 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2181 goto done; 2182 } 2183 xfer->ux_hcflags |= UXFER_ABORTING; 2184 2185 /* 2186 * Step 1: Make interrupt routine and hardware ignore xfer. 2187 */ 2188 xfer->ux_status = status; /* make software ignore it */ 2189 callout_stop(&xfer->ux_callout); 2190 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2191 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2192 usb_syncmem(&std->dma, 2193 std->offs + offsetof(uhci_td_t, td_status), 2194 sizeof(std->td.td_status), 2195 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2196 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2197 usb_syncmem(&std->dma, 2198 std->offs + offsetof(uhci_td_t, td_status), 2199 sizeof(std->td.td_status), 2200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2201 } 2202 2203 /* 2204 * Step 2: Wait until we know hardware has finished any possible 2205 * use of the xfer. Also make sure the soft interrupt routine 2206 * has run. 2207 */ 2208 /* Hardware finishes in 1ms */ 2209 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2210 sc->sc_softwake = 1; 2211 usb_schedsoftintr(&sc->sc_bus); 2212 DPRINTF("cv_wait", 0, 0, 0, 0); 2213 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2214 2215 /* 2216 * Step 3: Execute callback. 2217 */ 2218 DPRINTF("callback", 0, 0, 0, 0); 2219 #ifdef DIAGNOSTIC 2220 ux->ux_isdone = true; 2221 #endif 2222 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2223 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2224 usb_transfer_complete(xfer); 2225 if (wake) 2226 cv_broadcast(&xfer->ux_hccv); 2227 done: 2228 KASSERT(mutex_owned(&sc->sc_lock)); 2229 } 2230 2231 /* Close a device bulk pipe. */ 2232 void 2233 uhci_device_bulk_close(struct usbd_pipe *pipe) 2234 { 2235 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2236 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2237 2238 KASSERT(mutex_owned(&sc->sc_lock)); 2239 2240 uhci_free_sqh(sc, upipe->bulk.sqh); 2241 2242 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2243 } 2244 2245 usbd_status 2246 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2247 { 2248 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2249 usbd_status err; 2250 2251 /* Insert last in queue. */ 2252 mutex_enter(&sc->sc_lock); 2253 err = usb_insert_transfer(xfer); 2254 mutex_exit(&sc->sc_lock); 2255 if (err) 2256 return err; 2257 2258 /* 2259 * Pipe isn't running (otherwise err would be USBD_INPROG), 2260 * so start it first. 2261 */ 2262 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2263 } 2264 2265 usbd_status 2266 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2267 { 2268 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2269 usbd_status err; 2270 2271 if (sc->sc_dying) 2272 return USBD_IOERROR; 2273 2274 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2275 2276 mutex_enter(&sc->sc_lock); 2277 err = uhci_device_request(xfer); 2278 mutex_exit(&sc->sc_lock); 2279 if (err) 2280 return err; 2281 2282 if (sc->sc_bus.ub_usepolling) 2283 uhci_waitintr(sc, xfer); 2284 return USBD_IN_PROGRESS; 2285 } 2286 2287 usbd_status 2288 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2289 { 2290 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2291 usbd_status err; 2292 2293 /* Insert last in queue. */ 2294 mutex_enter(&sc->sc_lock); 2295 err = usb_insert_transfer(xfer); 2296 mutex_exit(&sc->sc_lock); 2297 if (err) 2298 return err; 2299 2300 /* 2301 * Pipe isn't running (otherwise err would be USBD_INPROG), 2302 * so start it first. 2303 */ 2304 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2305 } 2306 2307 usbd_status 2308 uhci_device_intr_start(struct usbd_xfer *xfer) 2309 { 2310 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2311 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2312 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2313 uhci_soft_td_t *data, *dataend; 2314 uhci_soft_qh_t *sqh; 2315 usbd_status err; 2316 int isread, endpt; 2317 int i; 2318 2319 if (sc->sc_dying) 2320 return USBD_IOERROR; 2321 2322 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2323 2324 DPRINTFN(3, "xfer=%p len=%d flags=%d", 2325 xfer, xfer->ux_length, xfer->ux_flags, 0); 2326 2327 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2328 2329 mutex_enter(&sc->sc_lock); 2330 2331 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2332 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2333 2334 upipe->intr.isread = isread; 2335 2336 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2337 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2338 &dataend); 2339 if (err) { 2340 mutex_exit(&sc->sc_lock); 2341 return err; 2342 } 2343 2344 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2345 usb_syncmem(&dataend->dma, 2346 dataend->offs + offsetof(uhci_td_t, td_status), 2347 sizeof(dataend->td.td_status), 2348 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2349 2350 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2351 #ifdef UHCI_DEBUG 2352 if (uhcidebug >= 10) { 2353 uhci_dump_tds(data); 2354 uhci_dump_qh(upipe->intr.qhs[0]); 2355 } 2356 #endif 2357 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2358 2359 /* Set up interrupt info. */ 2360 ux->ux_stdstart = data; 2361 ux->ux_stdend = dataend; 2362 KASSERT(ux->ux_isdone); 2363 #ifdef DIAGNOSTIC 2364 ux->ux_isdone = false; 2365 #endif 2366 2367 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2368 for (i = 0; i < upipe->intr.npoll; i++) { 2369 sqh = upipe->intr.qhs[i]; 2370 sqh->elink = data; 2371 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2372 usb_syncmem(&sqh->dma, 2373 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2374 sizeof(sqh->qh.qh_elink), 2375 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2376 } 2377 uhci_add_intr_info(sc, ux); 2378 xfer->ux_status = USBD_IN_PROGRESS; 2379 mutex_exit(&sc->sc_lock); 2380 2381 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2382 #ifdef UHCI_DEBUG 2383 if (uhcidebug >= 10) { 2384 uhci_dump_tds(data); 2385 uhci_dump_qh(upipe->intr.qhs[0]); 2386 } 2387 #endif 2388 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2389 2390 return USBD_IN_PROGRESS; 2391 } 2392 2393 /* Abort a device control request. */ 2394 void 2395 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2396 { 2397 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2398 2399 KASSERT(mutex_owned(&sc->sc_lock)); 2400 2401 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2402 uhci_abort_xfer(xfer, USBD_CANCELLED); 2403 } 2404 2405 /* Close a device control pipe. */ 2406 void 2407 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2408 { 2409 } 2410 2411 /* Abort a device interrupt request. */ 2412 void 2413 uhci_device_intr_abort(struct usbd_xfer *xfer) 2414 { 2415 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2416 2417 KASSERT(mutex_owned(&sc->sc_lock)); 2418 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2419 2420 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2421 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2422 2423 uhci_abort_xfer(xfer, USBD_CANCELLED); 2424 } 2425 2426 /* Close a device interrupt pipe. */ 2427 void 2428 uhci_device_intr_close(struct usbd_pipe *pipe) 2429 { 2430 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2431 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2432 int i, npoll; 2433 2434 KASSERT(mutex_owned(&sc->sc_lock)); 2435 2436 /* Unlink descriptors from controller data structures. */ 2437 npoll = upipe->intr.npoll; 2438 for (i = 0; i < npoll; i++) 2439 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2440 2441 /* 2442 * We now have to wait for any activity on the physical 2443 * descriptors to stop. 2444 */ 2445 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2446 2447 for(i = 0; i < npoll; i++) 2448 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2449 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2450 2451 /* XXX free other resources */ 2452 } 2453 2454 usbd_status 2455 uhci_device_request(struct usbd_xfer *xfer) 2456 { 2457 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2458 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2459 usb_device_request_t *req = &xfer->ux_request; 2460 struct usbd_device *dev = upipe->pipe.up_dev; 2461 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2462 int addr = dev->ud_addr; 2463 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2464 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2465 uhci_soft_qh_t *sqh; 2466 int len; 2467 uint32_t ls; 2468 usbd_status err; 2469 int isread; 2470 2471 KASSERT(mutex_owned(&sc->sc_lock)); 2472 2473 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2474 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2475 "wValue=0x%04x, wIndex=0x%04x", 2476 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2477 UGETW(req->wIndex)); 2478 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2479 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2480 2481 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2482 isread = req->bmRequestType & UT_READ; 2483 len = UGETW(req->wLength); 2484 2485 setup = upipe->ctrl.setup; 2486 stat = upipe->ctrl.stat; 2487 sqh = upipe->ctrl.sqh; 2488 2489 /* Set up data transaction */ 2490 if (len != 0) { 2491 upipe->nexttoggle = 1; 2492 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2493 &xfer->ux_dmabuf, &data, &dataend); 2494 if (err) 2495 return err; 2496 next = data; 2497 dataend->link.std = stat; 2498 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2499 usb_syncmem(&dataend->dma, 2500 dataend->offs + offsetof(uhci_td_t, td_link), 2501 sizeof(dataend->td.td_link), 2502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2503 } else { 2504 next = stat; 2505 } 2506 upipe->ctrl.length = len; 2507 2508 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2509 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2510 2511 setup->link.std = next; 2512 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2513 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2514 UHCI_TD_ACTIVE); 2515 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2516 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2517 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2518 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2519 2520 stat->link.std = NULL; 2521 stat->td.td_link = htole32(UHCI_PTR_T); 2522 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2523 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2524 stat->td.td_token = 2525 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2526 UHCI_TD_IN (0, endpt, addr, 1)); 2527 stat->td.td_buffer = htole32(0); 2528 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2530 2531 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2532 #ifdef UHCI_DEBUG 2533 if (uhcidebug >= 10) { 2534 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2535 uhci_dump_tds(setup); 2536 } 2537 #endif 2538 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2539 2540 /* Set up interrupt info. */ 2541 uxfer->ux_stdstart = setup; 2542 uxfer->ux_stdend = stat; 2543 KASSERT(uxfer->ux_isdone); 2544 #ifdef DIAGNOSTIC 2545 uxfer->ux_isdone = false; 2546 #endif 2547 2548 sqh->elink = setup; 2549 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2550 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2551 2552 if (dev->ud_speed == USB_SPEED_LOW) 2553 uhci_add_ls_ctrl(sc, sqh); 2554 else 2555 uhci_add_hs_ctrl(sc, sqh); 2556 uhci_add_intr_info(sc, uxfer); 2557 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2558 #ifdef UHCI_DEBUG 2559 if (uhcidebug >= 12) { 2560 uhci_soft_td_t *std; 2561 uhci_soft_qh_t *xqh; 2562 uhci_soft_qh_t *sxqh; 2563 int maxqh = 0; 2564 uhci_physaddr_t link; 2565 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2566 for (std = sc->sc_vframes[0].htd, link = 0; 2567 (link & UHCI_PTR_QH) == 0; 2568 std = std->link.std) { 2569 link = le32toh(std->td.td_link); 2570 uhci_dump_td(std); 2571 } 2572 sxqh = (uhci_soft_qh_t *)std; 2573 uhci_dump_qh(sxqh); 2574 for (xqh = sxqh; 2575 xqh != NULL; 2576 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2577 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2578 uhci_dump_qh(xqh); 2579 } 2580 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2581 uhci_dump_qh(sqh); 2582 uhci_dump_tds(sqh->elink); 2583 } 2584 #endif 2585 DPRINTFN(12, "--- dump end ---", 0, 0, 0, 0); 2586 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2587 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2588 uhci_timeout, xfer); 2589 } 2590 xfer->ux_status = USBD_IN_PROGRESS; 2591 2592 return USBD_NORMAL_COMPLETION; 2593 } 2594 2595 usbd_status 2596 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2597 { 2598 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2599 usbd_status err; 2600 2601 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2602 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2603 2604 /* Put it on our queue, */ 2605 mutex_enter(&sc->sc_lock); 2606 err = usb_insert_transfer(xfer); 2607 mutex_exit(&sc->sc_lock); 2608 2609 /* bail out on error, */ 2610 if (err && err != USBD_IN_PROGRESS) 2611 return err; 2612 2613 /* XXX should check inuse here */ 2614 2615 /* insert into schedule, */ 2616 uhci_device_isoc_enter(xfer); 2617 2618 /* and start if the pipe wasn't running */ 2619 if (!err) 2620 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2621 2622 return err; 2623 } 2624 2625 void 2626 uhci_device_isoc_enter(struct usbd_xfer *xfer) 2627 { 2628 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2629 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2630 struct isoc *isoc = &upipe->isoc; 2631 uhci_soft_td_t *std; 2632 uint32_t buf, len, status, offs; 2633 int i, next, nframes; 2634 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2635 2636 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2637 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2638 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2639 2640 if (sc->sc_dying) 2641 return; 2642 2643 if (xfer->ux_status == USBD_IN_PROGRESS) { 2644 /* This request has already been entered into the frame list */ 2645 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2646 /* XXX */ 2647 } 2648 2649 #ifdef DIAGNOSTIC 2650 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2651 printf("uhci_device_isoc_enter: overflow!\n"); 2652 #endif 2653 2654 next = isoc->next; 2655 if (next == -1) { 2656 /* Not in use yet, schedule it a few frames ahead. */ 2657 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2658 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2659 } 2660 2661 xfer->ux_status = USBD_IN_PROGRESS; 2662 UHCI_XFER2UXFER(xfer)->ux_curframe = next; 2663 2664 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2665 offs = 0; 2666 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2667 UHCI_TD_ACTIVE | 2668 UHCI_TD_IOS); 2669 nframes = xfer->ux_nframes; 2670 mutex_enter(&sc->sc_lock); 2671 for (i = 0; i < nframes; i++) { 2672 std = isoc->stds[next]; 2673 if (++next >= UHCI_VFRAMELIST_COUNT) 2674 next = 0; 2675 len = xfer->ux_frlengths[i]; 2676 std->td.td_buffer = htole32(buf); 2677 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2678 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2679 if (i == nframes - 1) 2680 status |= UHCI_TD_IOC; 2681 std->td.td_status = htole32(status); 2682 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2683 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2684 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2685 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2686 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2687 #ifdef UHCI_DEBUG 2688 if (uhcidebug >= 5) { 2689 DPRINTF("TD %d", i, 0, 0, 0); 2690 uhci_dump_td(std); 2691 } 2692 #endif 2693 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2694 buf += len; 2695 offs += len; 2696 } 2697 isoc->next = next; 2698 isoc->inuse += xfer->ux_nframes; 2699 2700 mutex_exit(&sc->sc_lock); 2701 } 2702 2703 usbd_status 2704 uhci_device_isoc_start(struct usbd_xfer *xfer) 2705 { 2706 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2707 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2708 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2709 uhci_soft_td_t *end; 2710 int i; 2711 2712 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2713 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2714 2715 mutex_enter(&sc->sc_lock); 2716 2717 if (sc->sc_dying) { 2718 mutex_exit(&sc->sc_lock); 2719 return USBD_IOERROR; 2720 } 2721 2722 #ifdef DIAGNOSTIC 2723 if (xfer->ux_status != USBD_IN_PROGRESS) 2724 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2725 #endif 2726 2727 /* Find the last TD */ 2728 i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes; 2729 if (i >= UHCI_VFRAMELIST_COUNT) 2730 i -= UHCI_VFRAMELIST_COUNT; 2731 end = upipe->isoc.stds[i]; 2732 2733 KASSERT(end != NULL); 2734 2735 /* Set up interrupt info. */ 2736 ux->ux_stdstart = end; 2737 ux->ux_stdend = end; 2738 2739 KASSERT(ux->ux_isdone); 2740 #ifdef DIAGNOSTIC 2741 ux->ux_isdone = false; 2742 #endif 2743 uhci_add_intr_info(sc, ux); 2744 2745 mutex_exit(&sc->sc_lock); 2746 2747 return USBD_IN_PROGRESS; 2748 } 2749 2750 void 2751 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2752 { 2753 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2754 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2755 uhci_soft_td_t **stds = upipe->isoc.stds; 2756 uhci_soft_td_t *std; 2757 int i, n, nframes, maxlen, len; 2758 2759 KASSERT(mutex_owned(&sc->sc_lock)); 2760 2761 /* Transfer is already done. */ 2762 if (xfer->ux_status != USBD_NOT_STARTED && 2763 xfer->ux_status != USBD_IN_PROGRESS) { 2764 return; 2765 } 2766 2767 /* Give xfer the requested abort code. */ 2768 xfer->ux_status = USBD_CANCELLED; 2769 2770 /* make hardware ignore it, */ 2771 nframes = xfer->ux_nframes; 2772 n = UHCI_XFER2UXFER(xfer)->ux_curframe; 2773 maxlen = 0; 2774 for (i = 0; i < nframes; i++) { 2775 std = stds[n]; 2776 usb_syncmem(&std->dma, 2777 std->offs + offsetof(uhci_td_t, td_status), 2778 sizeof(std->td.td_status), 2779 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2780 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2781 usb_syncmem(&std->dma, 2782 std->offs + offsetof(uhci_td_t, td_status), 2783 sizeof(std->td.td_status), 2784 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2785 usb_syncmem(&std->dma, 2786 std->offs + offsetof(uhci_td_t, td_token), 2787 sizeof(std->td.td_token), 2788 BUS_DMASYNC_POSTWRITE); 2789 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2790 if (len > maxlen) 2791 maxlen = len; 2792 if (++n >= UHCI_VFRAMELIST_COUNT) 2793 n = 0; 2794 } 2795 2796 /* and wait until we are sure the hardware has finished. */ 2797 delay(maxlen); 2798 2799 #ifdef DIAGNOSTIC 2800 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 2801 #endif 2802 /* Run callback and remove from interrupt list. */ 2803 usb_transfer_complete(xfer); 2804 2805 KASSERT(mutex_owned(&sc->sc_lock)); 2806 } 2807 2808 void 2809 uhci_device_isoc_close(struct usbd_pipe *pipe) 2810 { 2811 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2812 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2813 uhci_soft_td_t *std, *vstd; 2814 struct isoc *isoc; 2815 int i; 2816 2817 KASSERT(mutex_owned(&sc->sc_lock)); 2818 2819 /* 2820 * Make sure all TDs are marked as inactive. 2821 * Wait for completion. 2822 * Unschedule. 2823 * Deallocate. 2824 */ 2825 isoc = &upipe->isoc; 2826 2827 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2828 std = isoc->stds[i]; 2829 usb_syncmem(&std->dma, 2830 std->offs + offsetof(uhci_td_t, td_status), 2831 sizeof(std->td.td_status), 2832 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2833 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2834 usb_syncmem(&std->dma, 2835 std->offs + offsetof(uhci_td_t, td_status), 2836 sizeof(std->td.td_status), 2837 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2838 } 2839 /* wait for completion */ 2840 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2841 2842 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2843 std = isoc->stds[i]; 2844 for (vstd = sc->sc_vframes[i].htd; 2845 vstd != NULL && vstd->link.std != std; 2846 vstd = vstd->link.std) 2847 ; 2848 if (vstd == NULL) { 2849 /*panic*/ 2850 printf("uhci_device_isoc_close: %p not found\n", std); 2851 mutex_exit(&sc->sc_lock); 2852 return; 2853 } 2854 vstd->link = std->link; 2855 usb_syncmem(&std->dma, 2856 std->offs + offsetof(uhci_td_t, td_link), 2857 sizeof(std->td.td_link), 2858 BUS_DMASYNC_POSTWRITE); 2859 vstd->td.td_link = std->td.td_link; 2860 usb_syncmem(&vstd->dma, 2861 vstd->offs + offsetof(uhci_td_t, td_link), 2862 sizeof(vstd->td.td_link), 2863 BUS_DMASYNC_PREWRITE); 2864 uhci_free_std(sc, std); 2865 } 2866 2867 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2868 } 2869 2870 usbd_status 2871 uhci_setup_isoc(struct usbd_pipe *pipe) 2872 { 2873 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2874 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2875 int addr = upipe->pipe.up_dev->ud_addr; 2876 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2877 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2878 uhci_soft_td_t *std, *vstd; 2879 uint32_t token; 2880 struct isoc *isoc; 2881 int i; 2882 2883 isoc = &upipe->isoc; 2884 isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2885 sizeof(uhci_soft_td_t *), 2886 KM_SLEEP); 2887 if (isoc->stds == NULL) 2888 return USBD_NOMEM; 2889 2890 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2891 UHCI_TD_OUT(0, endpt, addr, 0); 2892 2893 mutex_enter(&sc->sc_lock); 2894 2895 /* Allocate the TDs and mark as inactive; */ 2896 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2897 std = uhci_alloc_std(sc); 2898 if (std == 0) 2899 goto bad; 2900 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2901 std->td.td_token = htole32(token); 2902 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2903 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2904 isoc->stds[i] = std; 2905 } 2906 2907 /* Insert TDs into schedule. */ 2908 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2909 std = isoc->stds[i]; 2910 vstd = sc->sc_vframes[i].htd; 2911 usb_syncmem(&vstd->dma, 2912 vstd->offs + offsetof(uhci_td_t, td_link), 2913 sizeof(vstd->td.td_link), 2914 BUS_DMASYNC_POSTWRITE); 2915 std->link = vstd->link; 2916 std->td.td_link = vstd->td.td_link; 2917 usb_syncmem(&std->dma, 2918 std->offs + offsetof(uhci_td_t, td_link), 2919 sizeof(std->td.td_link), 2920 BUS_DMASYNC_PREWRITE); 2921 vstd->link.std = std; 2922 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2923 usb_syncmem(&vstd->dma, 2924 vstd->offs + offsetof(uhci_td_t, td_link), 2925 sizeof(vstd->td.td_link), 2926 BUS_DMASYNC_PREWRITE); 2927 } 2928 mutex_exit(&sc->sc_lock); 2929 2930 isoc->next = -1; 2931 isoc->inuse = 0; 2932 2933 return USBD_NORMAL_COMPLETION; 2934 2935 bad: 2936 while (--i >= 0) 2937 uhci_free_std(sc, isoc->stds[i]); 2938 mutex_exit(&sc->sc_lock); 2939 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2940 return USBD_NOMEM; 2941 } 2942 2943 void 2944 uhci_device_isoc_done(struct usbd_xfer *xfer) 2945 { 2946 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2947 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2948 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2949 int i, offs; 2950 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2951 2952 2953 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2954 DPRINTFN(4, "length=%d, ux_state=0x%08x", 2955 xfer->ux_actlen, xfer->ux_state, 0, 0); 2956 2957 if (!uhci_active_intr_info(ux)) 2958 return; 2959 2960 #ifdef DIAGNOSTIC 2961 if (ux->ux_stdend == NULL) { 2962 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2963 #ifdef UHCI_DEBUG 2964 uhci_dump_ii(ux); 2965 #endif 2966 return; 2967 } 2968 #endif 2969 2970 /* Turn off the interrupt since it is active even if the TD is not. */ 2971 usb_syncmem(&ux->ux_stdend->dma, 2972 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 2973 sizeof(ux->ux_stdend->td.td_status), 2974 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2975 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2976 usb_syncmem(&ux->ux_stdend->dma, 2977 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 2978 sizeof(ux->ux_stdend->td.td_status), 2979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2980 2981 uhci_del_intr_info(sc, ux); /* remove from active list */ 2982 2983 offs = 0; 2984 for (i = 0; i < xfer->ux_nframes; i++) { 2985 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2986 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2987 offs += xfer->ux_frlengths[i]; 2988 } 2989 } 2990 2991 void 2992 uhci_device_intr_done(struct usbd_xfer *xfer) 2993 { 2994 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2995 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2996 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 2997 uhci_soft_qh_t *sqh; 2998 int i, npoll, isread; 2999 3000 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3001 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3002 3003 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3004 3005 npoll = upipe->intr.npoll; 3006 for(i = 0; i < npoll; i++) { 3007 sqh = upipe->intr.qhs[i]; 3008 sqh->elink = NULL; 3009 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3010 usb_syncmem(&sqh->dma, 3011 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3012 sizeof(sqh->qh.qh_elink), 3013 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3014 } 3015 uhci_free_std_chain(sc, ux->ux_stdstart, NULL); 3016 3017 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3018 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3019 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3020 3021 /* XXX Wasteful. */ 3022 if (xfer->ux_pipe->up_repeat) { 3023 uhci_soft_td_t *data, *dataend; 3024 3025 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3026 3027 /* This alloc cannot fail since we freed the chain above. */ 3028 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3029 upipe->intr.isread, xfer->ux_flags, 3030 &xfer->ux_dmabuf, &data, &dataend); 3031 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3032 usb_syncmem(&dataend->dma, 3033 dataend->offs + offsetof(uhci_td_t, td_status), 3034 sizeof(dataend->td.td_status), 3035 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3036 3037 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 3038 #ifdef UHCI_DEBUG 3039 if (uhcidebug >= 10) { 3040 uhci_dump_tds(data); 3041 uhci_dump_qh(upipe->intr.qhs[0]); 3042 } 3043 #endif 3044 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 3045 3046 ux->ux_stdstart = data; 3047 ux->ux_stdend = dataend; 3048 KASSERT(ux->ux_isdone); 3049 #ifdef DIAGNOSTIC 3050 ux->ux_isdone = false; 3051 #endif 3052 for (i = 0; i < npoll; i++) { 3053 sqh = upipe->intr.qhs[i]; 3054 sqh->elink = data; 3055 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3056 usb_syncmem(&sqh->dma, 3057 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3058 sizeof(sqh->qh.qh_elink), 3059 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3060 } 3061 xfer->ux_status = USBD_IN_PROGRESS; 3062 /* The ux is already on the examined list, just leave it. */ 3063 } else { 3064 DPRINTFN(5, "removing", 0, 0, 0, 0); 3065 if (uhci_active_intr_info(ux)) 3066 uhci_del_intr_info(sc, ux); 3067 } 3068 } 3069 3070 /* Deallocate request data structures */ 3071 void 3072 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3073 { 3074 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3075 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3076 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3077 int len = UGETW(xfer->ux_request.wLength); 3078 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3079 3080 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3081 3082 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3083 3084 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3085 3086 if (!uhci_active_intr_info(ux)) 3087 return; 3088 3089 uhci_del_intr_info(sc, ux); /* remove from active list */ 3090 3091 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3092 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3093 else 3094 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3095 3096 if (upipe->ctrl.length != 0) 3097 uhci_free_std_chain(sc, ux->ux_stdstart->link.std, ux->ux_stdend); 3098 3099 if (len) { 3100 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3101 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3102 } 3103 usb_syncmem(&upipe->ctrl.reqdma, 0, 3104 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3105 3106 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3107 } 3108 3109 /* Deallocate request data structures */ 3110 void 3111 uhci_device_bulk_done(struct usbd_xfer *xfer) 3112 { 3113 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3114 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3115 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->ux_pipe; 3116 3117 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3118 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3119 upipe); 3120 3121 KASSERT(mutex_owned(&sc->sc_lock)); 3122 3123 if (!uhci_active_intr_info(ux)) 3124 return; 3125 3126 uhci_del_intr_info(sc, ux); /* remove from active list */ 3127 3128 uhci_remove_bulk(sc, upipe->bulk.sqh); 3129 3130 uhci_free_std_chain(sc, ux->ux_stdstart, NULL); 3131 3132 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3133 } 3134 3135 /* Add interrupt QH, called with vflock. */ 3136 void 3137 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3138 { 3139 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3140 uhci_soft_qh_t *eqh; 3141 3142 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3143 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3144 3145 eqh = vf->eqh; 3146 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3147 sizeof(eqh->qh.qh_hlink), 3148 BUS_DMASYNC_POSTWRITE); 3149 sqh->hlink = eqh->hlink; 3150 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3151 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3152 sizeof(sqh->qh.qh_hlink), 3153 BUS_DMASYNC_PREWRITE); 3154 eqh->hlink = sqh; 3155 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3156 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3157 sizeof(eqh->qh.qh_hlink), 3158 BUS_DMASYNC_PREWRITE); 3159 vf->eqh = sqh; 3160 vf->bandwidth++; 3161 } 3162 3163 /* Remove interrupt QH. */ 3164 void 3165 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3166 { 3167 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3168 uhci_soft_qh_t *pqh; 3169 3170 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3171 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3172 3173 /* See comment in uhci_remove_ctrl() */ 3174 3175 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3176 sizeof(sqh->qh.qh_elink), 3177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3178 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3179 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3180 usb_syncmem(&sqh->dma, 3181 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3182 sizeof(sqh->qh.qh_elink), 3183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3184 delay(UHCI_QH_REMOVE_DELAY); 3185 } 3186 3187 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3188 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3189 sizeof(sqh->qh.qh_hlink), 3190 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3191 pqh->hlink = sqh->hlink; 3192 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3193 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3194 sizeof(pqh->qh.qh_hlink), 3195 BUS_DMASYNC_PREWRITE); 3196 delay(UHCI_QH_REMOVE_DELAY); 3197 if (vf->eqh == sqh) 3198 vf->eqh = pqh; 3199 vf->bandwidth--; 3200 } 3201 3202 usbd_status 3203 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3204 { 3205 uhci_soft_qh_t *sqh; 3206 int i, npoll; 3207 u_int bestbw, bw, bestoffs, offs; 3208 3209 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3210 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3211 if (ival == 0) { 3212 printf("uhci_device_setintr: 0 interval\n"); 3213 return USBD_INVAL; 3214 } 3215 3216 if (ival > UHCI_VFRAMELIST_COUNT) 3217 ival = UHCI_VFRAMELIST_COUNT; 3218 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3219 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3220 3221 upipe->intr.npoll = npoll; 3222 upipe->intr.qhs = 3223 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3224 if (upipe->intr.qhs == NULL) 3225 return USBD_NOMEM; 3226 3227 /* 3228 * Figure out which offset in the schedule that has most 3229 * bandwidth left over. 3230 */ 3231 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3232 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3233 for (bw = i = 0; i < npoll; i++) 3234 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3235 if (bw < bestbw) { 3236 bestbw = bw; 3237 bestoffs = offs; 3238 } 3239 } 3240 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3241 mutex_enter(&sc->sc_lock); 3242 for(i = 0; i < npoll; i++) { 3243 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3244 sqh->elink = NULL; 3245 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3246 usb_syncmem(&sqh->dma, 3247 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3248 sizeof(sqh->qh.qh_elink), 3249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3250 sqh->pos = MOD(i * ival + bestoffs); 3251 } 3252 #undef MOD 3253 3254 /* Enter QHs into the controller data structures. */ 3255 for(i = 0; i < npoll; i++) 3256 uhci_add_intr(sc, upipe->intr.qhs[i]); 3257 mutex_exit(&sc->sc_lock); 3258 3259 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3260 3261 return USBD_NORMAL_COMPLETION; 3262 } 3263 3264 /* Open a new pipe. */ 3265 usbd_status 3266 uhci_open(struct usbd_pipe *pipe) 3267 { 3268 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3269 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3270 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3271 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3272 usbd_status err = USBD_NOMEM; 3273 int ival; 3274 3275 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3276 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3277 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3278 3279 if (sc->sc_dying) 3280 return USBD_IOERROR; 3281 3282 upipe->aborting = 0; 3283 /* toggle state needed for bulk endpoints */ 3284 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3285 3286 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3287 switch (ed->bEndpointAddress) { 3288 case USB_CONTROL_ENDPOINT: 3289 pipe->up_methods = &roothub_ctrl_methods; 3290 break; 3291 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3292 pipe->up_methods = &uhci_root_intr_methods; 3293 break; 3294 default: 3295 return USBD_INVAL; 3296 } 3297 } else { 3298 switch (ed->bmAttributes & UE_XFERTYPE) { 3299 case UE_CONTROL: 3300 pipe->up_methods = &uhci_device_ctrl_methods; 3301 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3302 if (upipe->ctrl.sqh == NULL) 3303 goto bad; 3304 upipe->ctrl.setup = uhci_alloc_std(sc); 3305 if (upipe->ctrl.setup == NULL) { 3306 uhci_free_sqh(sc, upipe->ctrl.sqh); 3307 goto bad; 3308 } 3309 upipe->ctrl.stat = uhci_alloc_std(sc); 3310 if (upipe->ctrl.stat == NULL) { 3311 uhci_free_sqh(sc, upipe->ctrl.sqh); 3312 uhci_free_std(sc, upipe->ctrl.setup); 3313 goto bad; 3314 } 3315 err = usb_allocmem(&sc->sc_bus, 3316 sizeof(usb_device_request_t), 3317 0, &upipe->ctrl.reqdma); 3318 if (err) { 3319 uhci_free_sqh(sc, upipe->ctrl.sqh); 3320 uhci_free_std(sc, upipe->ctrl.setup); 3321 uhci_free_std(sc, upipe->ctrl.stat); 3322 goto bad; 3323 } 3324 break; 3325 case UE_INTERRUPT: 3326 pipe->up_methods = &uhci_device_intr_methods; 3327 ival = pipe->up_interval; 3328 if (ival == USBD_DEFAULT_INTERVAL) 3329 ival = ed->bInterval; 3330 return uhci_device_setintr(sc, upipe, ival); 3331 case UE_ISOCHRONOUS: 3332 pipe->up_methods = &uhci_device_isoc_methods; 3333 return uhci_setup_isoc(pipe); 3334 case UE_BULK: 3335 pipe->up_methods = &uhci_device_bulk_methods; 3336 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3337 if (upipe->bulk.sqh == NULL) 3338 goto bad; 3339 break; 3340 } 3341 } 3342 return USBD_NORMAL_COMPLETION; 3343 3344 bad: 3345 return USBD_NOMEM; 3346 } 3347 3348 /* 3349 * Data structures and routines to emulate the root hub. 3350 */ 3351 /* 3352 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3353 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3354 * should not be used by the USB subsystem. As we cannot issue a 3355 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3356 * will be enabled as part of the reset. 3357 * 3358 * On the VT83C572, the port cannot be successfully enabled until the 3359 * outstanding "port enable change" and "connection status change" 3360 * events have been reset. 3361 */ 3362 Static usbd_status 3363 uhci_portreset(uhci_softc_t *sc, int index) 3364 { 3365 int lim, port, x; 3366 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3367 3368 if (index == 1) 3369 port = UHCI_PORTSC1; 3370 else if (index == 2) 3371 port = UHCI_PORTSC2; 3372 else 3373 return USBD_IOERROR; 3374 3375 x = URWMASK(UREAD2(sc, port)); 3376 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3377 3378 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3379 3380 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3381 UREAD2(sc, port), 0, 0); 3382 3383 x = URWMASK(UREAD2(sc, port)); 3384 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3385 3386 delay(100); 3387 3388 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3389 UREAD2(sc, port), 0, 0); 3390 3391 x = URWMASK(UREAD2(sc, port)); 3392 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3393 3394 for (lim = 10; --lim > 0;) { 3395 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3396 3397 x = UREAD2(sc, port); 3398 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3399 lim, x, 0); 3400 3401 if (!(x & UHCI_PORTSC_CCS)) { 3402 /* 3403 * No device is connected (or was disconnected 3404 * during reset). Consider the port reset. 3405 * The delay must be long enough to ensure on 3406 * the initial iteration that the device 3407 * connection will have been registered. 50ms 3408 * appears to be sufficient, but 20ms is not. 3409 */ 3410 DPRINTFN(3, "uhci port %d loop %u, device detached", 3411 index, lim, 0, 0); 3412 break; 3413 } 3414 3415 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3416 /* 3417 * Port enabled changed and/or connection 3418 * status changed were set. Reset either or 3419 * both raised flags (by writing a 1 to that 3420 * bit), and wait again for state to settle. 3421 */ 3422 UWRITE2(sc, port, URWMASK(x) | 3423 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3424 continue; 3425 } 3426 3427 if (x & UHCI_PORTSC_PE) 3428 /* Port is enabled */ 3429 break; 3430 3431 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3432 } 3433 3434 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3435 UREAD2(sc, port), 0, 0); 3436 3437 if (lim <= 0) { 3438 DPRINTF("uhci port %d reset timed out", index, 3439 0, 0, 0); 3440 return USBD_TIMEOUT; 3441 } 3442 3443 sc->sc_isreset = 1; 3444 return USBD_NORMAL_COMPLETION; 3445 } 3446 3447 Static int 3448 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3449 void *buf, int buflen) 3450 { 3451 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3452 int port, x; 3453 int status, change, totlen = 0; 3454 uint16_t len, value, index; 3455 usb_port_status_t ps; 3456 usbd_status err; 3457 3458 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3459 3460 if (sc->sc_dying) 3461 return -1; 3462 3463 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3464 req->bRequest, 0, 0); 3465 3466 len = UGETW(req->wLength); 3467 value = UGETW(req->wValue); 3468 index = UGETW(req->wIndex); 3469 3470 #define C(x,y) ((x) | ((y) << 8)) 3471 switch (C(req->bRequest, req->bmRequestType)) { 3472 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3473 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3474 if (len == 0) 3475 break; 3476 switch (value) { 3477 case C(0, UDESC_DEVICE): { 3478 usb_device_descriptor_t devd; 3479 3480 totlen = min(buflen, sizeof(devd)); 3481 memcpy(&devd, buf, totlen); 3482 USETW(devd.idVendor, sc->sc_id_vendor); 3483 memcpy(buf, &devd, totlen); 3484 break; 3485 } 3486 case C(1, UDESC_STRING): 3487 #define sd ((usb_string_descriptor_t *)buf) 3488 /* Vendor */ 3489 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3490 break; 3491 case C(2, UDESC_STRING): 3492 /* Product */ 3493 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3494 break; 3495 #undef sd 3496 default: 3497 /* default from usbroothub */ 3498 return buflen; 3499 } 3500 break; 3501 3502 /* Hub requests */ 3503 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3504 break; 3505 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3506 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3507 value, 0, 0); 3508 if (index == 1) 3509 port = UHCI_PORTSC1; 3510 else if (index == 2) 3511 port = UHCI_PORTSC2; 3512 else { 3513 return -1; 3514 } 3515 switch(value) { 3516 case UHF_PORT_ENABLE: 3517 x = URWMASK(UREAD2(sc, port)); 3518 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3519 break; 3520 case UHF_PORT_SUSPEND: 3521 x = URWMASK(UREAD2(sc, port)); 3522 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3523 break; 3524 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3525 /* see USB2 spec ch. 7.1.7.7 */ 3526 usb_delay_ms(&sc->sc_bus, 20); 3527 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3528 /* 10ms resume delay must be provided by caller */ 3529 break; 3530 case UHF_PORT_RESET: 3531 x = URWMASK(UREAD2(sc, port)); 3532 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3533 break; 3534 case UHF_C_PORT_CONNECTION: 3535 x = URWMASK(UREAD2(sc, port)); 3536 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3537 break; 3538 case UHF_C_PORT_ENABLE: 3539 x = URWMASK(UREAD2(sc, port)); 3540 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3541 break; 3542 case UHF_C_PORT_OVER_CURRENT: 3543 x = URWMASK(UREAD2(sc, port)); 3544 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3545 break; 3546 case UHF_C_PORT_RESET: 3547 sc->sc_isreset = 0; 3548 break; 3549 case UHF_PORT_CONNECTION: 3550 case UHF_PORT_OVER_CURRENT: 3551 case UHF_PORT_POWER: 3552 case UHF_PORT_LOW_SPEED: 3553 case UHF_C_PORT_SUSPEND: 3554 default: 3555 return -1; 3556 } 3557 break; 3558 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3559 if (index == 1) 3560 port = UHCI_PORTSC1; 3561 else if (index == 2) 3562 port = UHCI_PORTSC2; 3563 else { 3564 return -1; 3565 } 3566 if (len > 0) { 3567 *(uint8_t *)buf = 3568 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3569 UHCI_PORTSC_LS_SHIFT; 3570 totlen = 1; 3571 } 3572 break; 3573 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3574 if (len == 0) 3575 break; 3576 if ((value & 0xff) != 0) { 3577 return -1; 3578 } 3579 usb_hub_descriptor_t hubd; 3580 3581 totlen = min(buflen, sizeof(hubd)); 3582 memcpy(&hubd, buf, totlen); 3583 hubd.bNbrPorts = 2; 3584 memcpy(buf, &hubd, totlen); 3585 break; 3586 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3587 if (len != 4) { 3588 return -1; 3589 } 3590 memset(buf, 0, len); 3591 totlen = len; 3592 break; 3593 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3594 if (index == 1) 3595 port = UHCI_PORTSC1; 3596 else if (index == 2) 3597 port = UHCI_PORTSC2; 3598 else { 3599 return -1; 3600 } 3601 if (len != 4) { 3602 return -1; 3603 } 3604 x = UREAD2(sc, port); 3605 status = change = 0; 3606 if (x & UHCI_PORTSC_CCS) 3607 status |= UPS_CURRENT_CONNECT_STATUS; 3608 if (x & UHCI_PORTSC_CSC) 3609 change |= UPS_C_CONNECT_STATUS; 3610 if (x & UHCI_PORTSC_PE) 3611 status |= UPS_PORT_ENABLED; 3612 if (x & UHCI_PORTSC_POEDC) 3613 change |= UPS_C_PORT_ENABLED; 3614 if (x & UHCI_PORTSC_OCI) 3615 status |= UPS_OVERCURRENT_INDICATOR; 3616 if (x & UHCI_PORTSC_OCIC) 3617 change |= UPS_C_OVERCURRENT_INDICATOR; 3618 if (x & UHCI_PORTSC_SUSP) 3619 status |= UPS_SUSPEND; 3620 if (x & UHCI_PORTSC_LSDA) 3621 status |= UPS_LOW_SPEED; 3622 status |= UPS_PORT_POWER; 3623 if (sc->sc_isreset) 3624 change |= UPS_C_PORT_RESET; 3625 USETW(ps.wPortStatus, status); 3626 USETW(ps.wPortChange, change); 3627 totlen = min(len, sizeof(ps)); 3628 memcpy(buf, &ps, totlen); 3629 break; 3630 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3631 return -1; 3632 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3633 break; 3634 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3635 if (index == 1) 3636 port = UHCI_PORTSC1; 3637 else if (index == 2) 3638 port = UHCI_PORTSC2; 3639 else { 3640 return -1; 3641 } 3642 switch(value) { 3643 case UHF_PORT_ENABLE: 3644 x = URWMASK(UREAD2(sc, port)); 3645 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3646 break; 3647 case UHF_PORT_SUSPEND: 3648 x = URWMASK(UREAD2(sc, port)); 3649 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3650 break; 3651 case UHF_PORT_RESET: 3652 err = uhci_portreset(sc, index); 3653 if (err != USBD_NORMAL_COMPLETION) 3654 return -1; 3655 return 0; 3656 case UHF_PORT_POWER: 3657 /* Pretend we turned on power */ 3658 return 0; 3659 case UHF_C_PORT_CONNECTION: 3660 case UHF_C_PORT_ENABLE: 3661 case UHF_C_PORT_OVER_CURRENT: 3662 case UHF_PORT_CONNECTION: 3663 case UHF_PORT_OVER_CURRENT: 3664 case UHF_PORT_LOW_SPEED: 3665 case UHF_C_PORT_SUSPEND: 3666 case UHF_C_PORT_RESET: 3667 default: 3668 return -1; 3669 } 3670 break; 3671 default: 3672 /* default from usbroothub */ 3673 DPRINTF("returning %d (usbroothub default)", 3674 buflen, 0, 0, 0); 3675 return buflen; 3676 } 3677 3678 DPRINTF("returning %d", totlen, 0, 0, 0); 3679 3680 return totlen; 3681 } 3682 3683 /* Abort a root interrupt request. */ 3684 void 3685 uhci_root_intr_abort(struct usbd_xfer *xfer) 3686 { 3687 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3688 3689 KASSERT(mutex_owned(&sc->sc_lock)); 3690 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3691 3692 callout_stop(&sc->sc_poll_handle); 3693 sc->sc_intr_xfer = NULL; 3694 3695 xfer->ux_status = USBD_CANCELLED; 3696 #ifdef DIAGNOSTIC 3697 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3698 #endif 3699 usb_transfer_complete(xfer); 3700 } 3701 3702 usbd_status 3703 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3704 { 3705 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3706 usbd_status err; 3707 3708 /* Insert last in queue. */ 3709 mutex_enter(&sc->sc_lock); 3710 err = usb_insert_transfer(xfer); 3711 mutex_exit(&sc->sc_lock); 3712 if (err) 3713 return err; 3714 3715 /* 3716 * Pipe isn't running (otherwise err would be USBD_INPROG), 3717 * start first 3718 */ 3719 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3720 } 3721 3722 /* Start a transfer on the root interrupt pipe */ 3723 usbd_status 3724 uhci_root_intr_start(struct usbd_xfer *xfer) 3725 { 3726 struct usbd_pipe *pipe = xfer->ux_pipe; 3727 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3728 unsigned int ival; 3729 3730 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3731 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3732 xfer->ux_flags, 0); 3733 3734 if (sc->sc_dying) 3735 return USBD_IOERROR; 3736 3737 /* XXX temporary variable needed to avoid gcc3 warning */ 3738 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3739 sc->sc_ival = mstohz(ival); 3740 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3741 sc->sc_intr_xfer = xfer; 3742 return USBD_IN_PROGRESS; 3743 } 3744 3745 /* Close the root interrupt pipe. */ 3746 void 3747 uhci_root_intr_close(struct usbd_pipe *pipe) 3748 { 3749 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3750 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3751 3752 KASSERT(mutex_owned(&sc->sc_lock)); 3753 3754 callout_stop(&sc->sc_poll_handle); 3755 sc->sc_intr_xfer = NULL; 3756 } 3757
Indexes created Tue Sep 30 17:09:57 GMT 2025