uhci.c revision 1.264.4.5
1 /* $NetBSD: uhci.c,v 1.264.4.5 2014/12/01 12:38:39 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.5 2014/12/01 12:38:39 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 72 /*#define UHCI_CTL_LOOP */ 73 74 75 76 #ifdef UHCI_DEBUG 77 uhci_softc_t *thesc; 78 #define DPRINTF(x) if (uhcidebug) printf x 79 #define DPRINTFN(n,x) if (uhcidebug>(n)) printf x 80 int uhcidebug = 0; 81 int uhcinoloop = 0; 82 #else 83 #define DPRINTF(x) 84 #define DPRINTFN(n,x) 85 #endif 86 87 /* 88 * The UHCI controller is little endian, so on big endian machines 89 * the data stored in memory needs to be swapped. 90 */ 91 92 struct uhci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 u_char aborting; 97 usbd_xfer_handle abortstart, abortend; 98 99 /* Info needed for different pipe kinds. */ 100 union { 101 /* Control pipe */ 102 struct { 103 uhci_soft_qh_t *sqh; 104 usb_dma_t reqdma; 105 uhci_soft_td_t *setup, *stat; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 int npoll; 111 int isread; 112 uhci_soft_qh_t **qhs; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 uhci_soft_qh_t *sqh; 117 u_int length; 118 int isread; 119 } bulk; 120 /* Iso pipe */ 121 struct iso { 122 uhci_soft_td_t **stds; 123 int next, inuse; 124 } iso; 125 } u; 126 }; 127 128 Static void uhci_globalreset(uhci_softc_t *); 129 Static usbd_status uhci_portreset(uhci_softc_t*, int); 130 Static void uhci_reset(uhci_softc_t *); 131 Static usbd_status uhci_run(uhci_softc_t *, int run, int locked); 132 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 133 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 134 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 135 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 136 #if 0 137 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 138 uhci_intr_info_t *); 139 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 140 #endif 141 142 Static void uhci_free_std_chain(uhci_softc_t *, 143 uhci_soft_td_t *, uhci_soft_td_t *); 144 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 145 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 146 uhci_soft_td_t **, uhci_soft_td_t **); 147 Static void uhci_poll_hub(void *); 148 Static void uhci_waitintr(uhci_softc_t *, usbd_xfer_handle); 149 Static void uhci_check_intr(uhci_softc_t *, uhci_intr_info_t *); 150 Static void uhci_idone(uhci_intr_info_t *); 151 152 Static void uhci_abort_xfer(usbd_xfer_handle, usbd_status status); 153 154 Static void uhci_timeout(void *); 155 Static void uhci_timeout_task(void *); 156 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 157 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 158 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 159 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 160 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 161 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 162 Static void uhci_add_loop(uhci_softc_t *sc); 163 Static void uhci_rem_loop(uhci_softc_t *sc); 164 165 Static usbd_status uhci_setup_isoc(usbd_pipe_handle pipe); 166 Static void uhci_device_isoc_enter(usbd_xfer_handle); 167 168 Static usbd_status uhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 169 Static void uhci_freem(struct usbd_bus *, usb_dma_t *); 170 171 Static usbd_xfer_handle uhci_allocx(struct usbd_bus *); 172 Static void uhci_freex(struct usbd_bus *, usbd_xfer_handle); 173 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 174 175 Static usbd_status uhci_device_ctrl_transfer(usbd_xfer_handle); 176 Static usbd_status uhci_device_ctrl_start(usbd_xfer_handle); 177 Static void uhci_device_ctrl_abort(usbd_xfer_handle); 178 Static void uhci_device_ctrl_close(usbd_pipe_handle); 179 Static void uhci_device_ctrl_done(usbd_xfer_handle); 180 181 Static usbd_status uhci_device_intr_transfer(usbd_xfer_handle); 182 Static usbd_status uhci_device_intr_start(usbd_xfer_handle); 183 Static void uhci_device_intr_abort(usbd_xfer_handle); 184 Static void uhci_device_intr_close(usbd_pipe_handle); 185 Static void uhci_device_intr_done(usbd_xfer_handle); 186 187 Static usbd_status uhci_device_bulk_transfer(usbd_xfer_handle); 188 Static usbd_status uhci_device_bulk_start(usbd_xfer_handle); 189 Static void uhci_device_bulk_abort(usbd_xfer_handle); 190 Static void uhci_device_bulk_close(usbd_pipe_handle); 191 Static void uhci_device_bulk_done(usbd_xfer_handle); 192 193 Static usbd_status uhci_device_isoc_transfer(usbd_xfer_handle); 194 Static usbd_status uhci_device_isoc_start(usbd_xfer_handle); 195 Static void uhci_device_isoc_abort(usbd_xfer_handle); 196 Static void uhci_device_isoc_close(usbd_pipe_handle); 197 Static void uhci_device_isoc_done(usbd_xfer_handle); 198 199 Static usbd_status uhci_root_ctrl_transfer(usbd_xfer_handle); 200 Static usbd_status uhci_root_ctrl_start(usbd_xfer_handle); 201 Static void uhci_root_ctrl_abort(usbd_xfer_handle); 202 Static void uhci_root_ctrl_close(usbd_pipe_handle); 203 Static void uhci_root_ctrl_done(usbd_xfer_handle); 204 205 Static usbd_status uhci_root_intr_transfer(usbd_xfer_handle); 206 Static usbd_status uhci_root_intr_start(usbd_xfer_handle); 207 Static void uhci_root_intr_abort(usbd_xfer_handle); 208 Static void uhci_root_intr_close(usbd_pipe_handle); 209 Static void uhci_root_intr_done(usbd_xfer_handle); 210 211 Static usbd_status uhci_open(usbd_pipe_handle); 212 Static void uhci_poll(struct usbd_bus *); 213 Static void uhci_softintr(void *); 214 215 Static usbd_status uhci_device_request(usbd_xfer_handle xfer); 216 217 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 218 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 219 Static usbd_status uhci_device_setintr(uhci_softc_t *sc, 220 struct uhci_pipe *pipe, int ival); 221 222 Static void uhci_device_clear_toggle(usbd_pipe_handle pipe); 223 Static void uhci_noop(usbd_pipe_handle pipe); 224 225 static inline uhci_soft_qh_t *uhci_find_prev_qh(uhci_soft_qh_t *, 226 uhci_soft_qh_t *); 227 228 #ifdef UHCI_DEBUG 229 Static void uhci_dump_all(uhci_softc_t *); 230 Static void uhci_dumpregs(uhci_softc_t *); 231 Static void uhci_dump_qhs(uhci_soft_qh_t *); 232 Static void uhci_dump_qh(uhci_soft_qh_t *); 233 Static void uhci_dump_tds(uhci_soft_td_t *); 234 Static void uhci_dump_td(uhci_soft_td_t *); 235 Static void uhci_dump_ii(uhci_intr_info_t *ii); 236 void uhci_dump(void); 237 #endif 238 239 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 240 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 241 #define UWRITE1(sc, r, x) \ 242 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 243 } while (/*CONSTCOND*/0) 244 #define UWRITE2(sc, r, x) \ 245 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 246 } while (/*CONSTCOND*/0) 247 #define UWRITE4(sc, r, x) \ 248 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 249 } while (/*CONSTCOND*/0) 250 static __inline uint8_t 251 UREAD1(uhci_softc_t *sc, bus_size_t r) 252 { 253 254 UBARR(sc); 255 return bus_space_read_1(sc->iot, sc->ioh, r); 256 } 257 258 static __inline uint16_t 259 UREAD2(uhci_softc_t *sc, bus_size_t r) 260 { 261 262 UBARR(sc); 263 return bus_space_read_2(sc->iot, sc->ioh, r); 264 } 265 266 #ifdef UHCI_DEBUG 267 static __inline uint32_t 268 UREAD4(uhci_softc_t *sc, bus_size_t r) 269 { 270 271 UBARR(sc); 272 return bus_space_read_4(sc->iot, sc->ioh, r); 273 } 274 #endif 275 276 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 277 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 278 279 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 280 281 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 282 283 #define UHCI_INTR_ENDPT 1 284 285 const struct usbd_bus_methods uhci_bus_methods = { 286 .ubm_open = uhci_open, 287 .ubm_softint = uhci_softintr, 288 .ubm_dopoll = uhci_poll, 289 .ubm_allocm = uhci_allocm, 290 .ubm_freem = uhci_freem, 291 .ubm_allocx = uhci_allocx, 292 .ubm_freex = uhci_freex, 293 .ubm_getlock = uhci_get_lock, 294 .ubm_newdev = NULL, 295 }; 296 297 const struct usbd_pipe_methods uhci_root_ctrl_methods = { 298 .upm_transfer = uhci_root_ctrl_transfer, 299 .upm_start = uhci_root_ctrl_start, 300 .upm_abort = uhci_root_ctrl_abort, 301 .upm_close = uhci_root_ctrl_close, 302 .upm_cleartoggle = uhci_noop, 303 .upm_done = uhci_root_ctrl_done, 304 }; 305 306 const struct usbd_pipe_methods uhci_root_intr_methods = { 307 .upm_transfer = uhci_root_intr_transfer, 308 .upm_start = uhci_root_intr_start, 309 .upm_abort = uhci_root_intr_abort, 310 .upm_close = uhci_root_intr_close, 311 .upm_cleartoggle = uhci_noop, 312 .upm_done = uhci_root_intr_done, 313 }; 314 315 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 316 .upm_transfer = uhci_device_ctrl_transfer, 317 .upm_start = uhci_device_ctrl_start, 318 .upm_abort = uhci_device_ctrl_abort, 319 .upm_close = uhci_device_ctrl_close, 320 .upm_cleartoggle = uhci_noop, 321 .upm_done = uhci_device_ctrl_done, 322 }; 323 324 const struct usbd_pipe_methods uhci_device_intr_methods = { 325 .upm_transfer = uhci_device_intr_transfer, 326 .upm_start = uhci_device_intr_start, 327 .upm_abort = uhci_device_intr_abort, 328 .upm_close = uhci_device_intr_close, 329 .upm_cleartoggle = uhci_device_clear_toggle, 330 .upm_done = uhci_device_intr_done, 331 }; 332 333 const struct usbd_pipe_methods uhci_device_bulk_methods = { 334 .upm_transfer = uhci_device_bulk_transfer, 335 .upm_start = uhci_device_bulk_start, 336 .upm_abort = uhci_device_bulk_abort, 337 .upm_close = uhci_device_bulk_close, 338 .upm_cleartoggle = uhci_device_clear_toggle, 339 .upm_done = uhci_device_bulk_done, 340 }; 341 342 const struct usbd_pipe_methods uhci_device_isoc_methods = { 343 .upm_transfer = uhci_device_isoc_transfer, 344 .upm_start = uhci_device_isoc_start, 345 .upm_abort = uhci_device_isoc_abort, 346 .upm_close = uhci_device_isoc_close, 347 .upm_cleartoggle = uhci_noop, 348 .upm_done = uhci_device_isoc_done, 349 }; 350 351 #define uhci_add_intr_info(sc, ii) \ 352 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ii), list) 353 #define uhci_del_intr_info(ii) \ 354 do { \ 355 LIST_REMOVE((ii), list); \ 356 (ii)->list.le_prev = NULL; \ 357 } while (0) 358 #define uhci_active_intr_info(ii) ((ii)->list.le_prev != NULL) 359 360 static inline uhci_soft_qh_t * 361 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 362 { 363 DPRINTFN(15,("uhci_find_prev_qh: pqh=%p sqh=%p\n", pqh, sqh)); 364 365 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 366 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 367 usb_syncmem(&pqh->dma, 368 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 369 sizeof(pqh->qh.qh_hlink), 370 BUS_DMASYNC_POSTWRITE); 371 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 372 printf("uhci_find_prev_qh: QH not found\n"); 373 return (NULL); 374 } 375 #endif 376 } 377 return (pqh); 378 } 379 380 void 381 uhci_globalreset(uhci_softc_t *sc) 382 { 383 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 384 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 385 UHCICMD(sc, 0); /* do nothing */ 386 } 387 388 usbd_status 389 uhci_init(uhci_softc_t *sc) 390 { 391 usbd_status err; 392 int i, j; 393 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 394 uhci_soft_td_t *std; 395 396 DPRINTFN(1,("uhci_init: start\n")); 397 398 #ifdef UHCI_DEBUG 399 thesc = sc; 400 401 if (uhcidebug > 2) 402 uhci_dumpregs(sc); 403 #endif 404 405 sc->sc_suspend = PWR_RESUME; 406 407 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 408 uhci_globalreset(sc); /* reset the controller */ 409 uhci_reset(sc); 410 411 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 412 USB_MEM_RESERVE); 413 414 /* Allocate and initialize real frame array. */ 415 err = usb_allocmem(&sc->sc_bus, 416 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 417 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 418 if (err) 419 return (err); 420 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 421 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 422 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 423 424 /* 425 * Allocate a TD, inactive, that hangs from the last QH. 426 * This is to avoid a bug in the PIIX that makes it run berserk 427 * otherwise. 428 */ 429 std = uhci_alloc_std(sc); 430 if (std == NULL) 431 return (USBD_NOMEM); 432 std->link.std = NULL; 433 std->td.td_link = htole32(UHCI_PTR_T); 434 std->td.td_status = htole32(0); /* inactive */ 435 std->td.td_token = htole32(0); 436 std->td.td_buffer = htole32(0); 437 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 438 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 439 440 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 441 lsqh = uhci_alloc_sqh(sc); 442 if (lsqh == NULL) 443 return (USBD_NOMEM); 444 lsqh->hlink = NULL; 445 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 446 lsqh->elink = std; 447 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 448 sc->sc_last_qh = lsqh; 449 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 450 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 451 452 /* Allocate the dummy QH where bulk traffic will be queued. */ 453 bsqh = uhci_alloc_sqh(sc); 454 if (bsqh == NULL) 455 return (USBD_NOMEM); 456 bsqh->hlink = lsqh; 457 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 458 bsqh->elink = NULL; 459 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 460 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 461 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 462 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 463 464 /* Allocate dummy QH where high speed control traffic will be queued. */ 465 chsqh = uhci_alloc_sqh(sc); 466 if (chsqh == NULL) 467 return (USBD_NOMEM); 468 chsqh->hlink = bsqh; 469 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 470 chsqh->elink = NULL; 471 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 472 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 473 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 475 476 /* Allocate dummy QH where control traffic will be queued. */ 477 clsqh = uhci_alloc_sqh(sc); 478 if (clsqh == NULL) 479 return (USBD_NOMEM); 480 clsqh->hlink = chsqh; 481 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 482 clsqh->elink = NULL; 483 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 484 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 485 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 487 488 /* 489 * Make all (virtual) frame list pointers point to the interrupt 490 * queue heads and the interrupt queue heads at the control 491 * queue head and point the physical frame list to the virtual. 492 */ 493 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 494 std = uhci_alloc_std(sc); 495 sqh = uhci_alloc_sqh(sc); 496 if (std == NULL || sqh == NULL) 497 return (USBD_NOMEM); 498 std->link.sqh = sqh; 499 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 500 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 501 std->td.td_token = htole32(0); 502 std->td.td_buffer = htole32(0); 503 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 504 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 505 sqh->hlink = clsqh; 506 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 507 sqh->elink = NULL; 508 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 509 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 511 sc->sc_vframes[i].htd = std; 512 sc->sc_vframes[i].etd = std; 513 sc->sc_vframes[i].hqh = sqh; 514 sc->sc_vframes[i].eqh = sqh; 515 for (j = i; 516 j < UHCI_FRAMELIST_COUNT; 517 j += UHCI_VFRAMELIST_COUNT) 518 sc->sc_pframes[j] = htole32(std->physaddr); 519 } 520 usb_syncmem(&sc->sc_dma, 0, 521 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 522 BUS_DMASYNC_PREWRITE); 523 524 525 LIST_INIT(&sc->sc_intrhead); 526 527 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 528 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 529 530 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 531 532 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 533 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 534 cv_init(&sc->sc_softwake_cv, "uhciab"); 535 536 /* Set up the bus struct. */ 537 sc->sc_bus.methods = &uhci_bus_methods; 538 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 539 540 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 541 542 DPRINTFN(1,("uhci_init: enabling\n")); 543 544 err = uhci_run(sc, 1, 0); /* and here we go... */ 545 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 546 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 547 return err; 548 } 549 550 int 551 uhci_activate(device_t self, enum devact act) 552 { 553 struct uhci_softc *sc = device_private(self); 554 555 switch (act) { 556 case DVACT_DEACTIVATE: 557 sc->sc_dying = 1; 558 return 0; 559 default: 560 return EOPNOTSUPP; 561 } 562 } 563 564 void 565 uhci_childdet(device_t self, device_t child) 566 { 567 struct uhci_softc *sc = device_private(self); 568 569 KASSERT(sc->sc_child == child); 570 sc->sc_child = NULL; 571 } 572 573 int 574 uhci_detach(struct uhci_softc *sc, int flags) 575 { 576 int rv = 0; 577 578 if (sc->sc_child != NULL) 579 rv = config_detach(sc->sc_child, flags); 580 581 if (rv != 0) 582 return (rv); 583 584 callout_halt(&sc->sc_poll_handle, NULL); 585 callout_destroy(&sc->sc_poll_handle); 586 587 cv_destroy(&sc->sc_softwake_cv); 588 589 mutex_destroy(&sc->sc_lock); 590 mutex_destroy(&sc->sc_intr_lock); 591 592 pool_cache_destroy(sc->sc_xferpool); 593 594 /* XXX free other data structures XXX */ 595 596 return (rv); 597 } 598 599 usbd_status 600 uhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 601 { 602 struct uhci_softc *sc = bus->hci_private; 603 usbd_status status; 604 uint32_t n; 605 606 /* 607 * XXX 608 * Since we are allocating a buffer we can assume that we will 609 * need TDs for it. Since we don't want to allocate those from 610 * an interrupt context, we allocate them here and free them again. 611 * This is no guarantee that we'll get the TDs next time... 612 */ 613 n = size / 8; 614 if (n > 16) { 615 uint32_t i; 616 uhci_soft_td_t **stds; 617 618 DPRINTF(("uhci_allocm: get %d TDs\n", n)); 619 stds = kmem_alloc(sizeof(uhci_soft_td_t *) * n, KM_SLEEP); 620 if (!stds) 621 return USBD_NOMEM; 622 for(i = 0; i < n; i++) 623 stds[i] = uhci_alloc_std(sc); 624 for(i = 0; i < n; i++) 625 if (stds[i] != NULL) 626 uhci_free_std(sc, stds[i]); 627 kmem_free(stds, sizeof(uhci_soft_td_t *) * n); 628 } 629 630 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 631 if (status == USBD_NOMEM) 632 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 633 return status; 634 } 635 636 void 637 uhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 638 { 639 if (dma->block->flags & USB_DMA_RESERVE) { 640 usb_reserve_freem(&((struct uhci_softc *)bus)->sc_dma_reserve, 641 dma); 642 return; 643 } 644 usb_freemem(&((struct uhci_softc *)bus)->sc_bus, dma); 645 } 646 647 usbd_xfer_handle 648 uhci_allocx(struct usbd_bus *bus) 649 { 650 struct uhci_softc *sc = bus->hci_private; 651 usbd_xfer_handle xfer; 652 653 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 654 if (xfer != NULL) { 655 memset(xfer, 0, sizeof(struct uhci_xfer)); 656 UXFER(xfer)->iinfo.sc = sc; 657 #ifdef DIAGNOSTIC 658 UXFER(xfer)->iinfo.isdone = 1; 659 xfer->busy_free = XFER_BUSY; 660 #endif 661 } 662 return (xfer); 663 } 664 665 void 666 uhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 667 { 668 struct uhci_softc *sc = bus->hci_private; 669 670 #ifdef DIAGNOSTIC 671 if (xfer->busy_free != XFER_BUSY) { 672 printf("uhci_freex: xfer=%p not busy, 0x%08x\n", xfer, 673 xfer->busy_free); 674 } 675 xfer->busy_free = XFER_FREE; 676 if (!UXFER(xfer)->iinfo.isdone) { 677 printf("uhci_freex: !isdone\n"); 678 } 679 #endif 680 pool_cache_put(sc->sc_xferpool, xfer); 681 } 682 683 Static void 684 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 685 { 686 struct uhci_softc *sc = bus->hci_private; 687 688 *lock = &sc->sc_lock; 689 } 690 691 692 /* 693 * Handle suspend/resume. 694 * 695 * We need to switch to polling mode here, because this routine is 696 * called from an interrupt context. This is all right since we 697 * are almost suspended anyway. 698 */ 699 bool 700 uhci_resume(device_t dv, const pmf_qual_t *qual) 701 { 702 uhci_softc_t *sc = device_private(dv); 703 int cmd; 704 705 mutex_spin_enter(&sc->sc_intr_lock); 706 707 cmd = UREAD2(sc, UHCI_CMD); 708 sc->sc_bus.use_polling++; 709 UWRITE2(sc, UHCI_INTR, 0); 710 uhci_globalreset(sc); 711 uhci_reset(sc); 712 if (cmd & UHCI_CMD_RS) 713 uhci_run(sc, 0, 1); 714 715 /* restore saved state */ 716 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 717 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 718 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 719 720 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 721 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 722 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 723 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 724 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 725 UHCICMD(sc, UHCI_CMD_MAXP); 726 uhci_run(sc, 1, 1); /* and start traffic again */ 727 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 728 sc->sc_bus.use_polling--; 729 if (sc->sc_intr_xfer != NULL) 730 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 731 sc->sc_intr_xfer); 732 #ifdef UHCI_DEBUG 733 if (uhcidebug > 2) 734 uhci_dumpregs(sc); 735 #endif 736 737 sc->sc_suspend = PWR_RESUME; 738 mutex_spin_exit(&sc->sc_intr_lock); 739 740 return true; 741 } 742 743 bool 744 uhci_suspend(device_t dv, const pmf_qual_t *qual) 745 { 746 uhci_softc_t *sc = device_private(dv); 747 int cmd; 748 749 mutex_spin_enter(&sc->sc_intr_lock); 750 751 cmd = UREAD2(sc, UHCI_CMD); 752 753 #ifdef UHCI_DEBUG 754 if (uhcidebug > 2) 755 uhci_dumpregs(sc); 756 #endif 757 if (sc->sc_intr_xfer != NULL) 758 callout_stop(&sc->sc_poll_handle); 759 sc->sc_suspend = PWR_SUSPEND; 760 sc->sc_bus.use_polling++; 761 762 uhci_run(sc, 0, 1); /* stop the controller */ 763 cmd &= ~UHCI_CMD_RS; 764 765 /* save some state if BIOS doesn't */ 766 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 767 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 768 769 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 770 771 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 772 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 773 sc->sc_bus.use_polling--; 774 775 mutex_spin_exit(&sc->sc_intr_lock); 776 777 return true; 778 } 779 780 #ifdef UHCI_DEBUG 781 Static void 782 uhci_dumpregs(uhci_softc_t *sc) 783 { 784 DPRINTFN(-1,("%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 785 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 786 device_xname(sc->sc_dev), 787 UREAD2(sc, UHCI_CMD), 788 UREAD2(sc, UHCI_STS), 789 UREAD2(sc, UHCI_INTR), 790 UREAD2(sc, UHCI_FRNUM), 791 UREAD4(sc, UHCI_FLBASEADDR), 792 UREAD1(sc, UHCI_SOF), 793 UREAD2(sc, UHCI_PORTSC1), 794 UREAD2(sc, UHCI_PORTSC2))); 795 } 796 797 void 798 uhci_dump_td(uhci_soft_td_t *p) 799 { 800 char sbuf[128], sbuf2[128]; 801 802 803 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 805 DPRINTFN(-1,("TD(%p) at %08lx = link=0x%08lx status=0x%08lx " 806 "token=0x%08lx buffer=0x%08lx\n", 807 p, (long)p->physaddr, 808 (long)le32toh(p->td.td_link), 809 (long)le32toh(p->td.td_status), 810 (long)le32toh(p->td.td_token), 811 (long)le32toh(p->td.td_buffer))); 812 813 snprintb(sbuf, sizeof(sbuf), "\20\1T\2Q\3VF", 814 (uint32_t)le32toh(p->td.td_link)); 815 snprintb(sbuf2, sizeof(sbuf2), 816 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27" 817 "STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 818 (uint32_t)le32toh(p->td.td_status)); 819 820 DPRINTFN(-1,(" %s %s,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d," 821 "D=%d,maxlen=%d\n", sbuf, sbuf2, 822 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 823 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 824 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 825 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 826 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 827 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 828 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token)))); 829 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 830 BUS_DMASYNC_PREREAD); 831 } 832 833 void 834 uhci_dump_qh(uhci_soft_qh_t *sqh) 835 { 836 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 837 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 838 DPRINTFN(-1,("QH(%p) at %08x: hlink=%08x elink=%08x\n", sqh, 839 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 840 le32toh(sqh->qh.qh_elink))); 841 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 842 } 843 844 845 #if 1 846 void 847 uhci_dump(void) 848 { 849 uhci_dump_all(thesc); 850 } 851 #endif 852 853 void 854 uhci_dump_all(uhci_softc_t *sc) 855 { 856 uhci_dumpregs(sc); 857 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 858 uhci_dump_qhs(sc->sc_lctl_start); 859 } 860 861 862 void 863 uhci_dump_qhs(uhci_soft_qh_t *sqh) 864 { 865 uhci_dump_qh(sqh); 866 867 /* uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 868 * Traverses sideways first, then down. 869 * 870 * QH1 871 * QH2 872 * No QH 873 * TD2.1 874 * TD2.2 875 * TD1.1 876 * etc. 877 * 878 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 879 */ 880 881 882 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 883 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 884 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 885 uhci_dump_qhs(sqh->hlink); 886 else 887 DPRINTF(("No QH\n")); 888 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 889 890 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 891 uhci_dump_tds(sqh->elink); 892 else 893 DPRINTF(("No TD\n")); 894 } 895 896 void 897 uhci_dump_tds(uhci_soft_td_t *std) 898 { 899 uhci_soft_td_t *td; 900 int stop; 901 902 for(td = std; td != NULL; td = td->link.std) { 903 uhci_dump_td(td); 904 905 /* Check whether the link pointer in this TD marks 906 * the link pointer as end of queue. This avoids 907 * printing the free list in case the queue/TD has 908 * already been moved there (seatbelt). 909 */ 910 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 911 sizeof(td->td.td_link), 912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 913 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 914 le32toh(td->td.td_link) == 0); 915 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 916 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 917 if (stop) 918 break; 919 } 920 } 921 922 Static void 923 uhci_dump_ii(uhci_intr_info_t *ii) 924 { 925 usbd_pipe_handle pipe; 926 usb_endpoint_descriptor_t *ed; 927 usbd_device_handle dev; 928 929 #ifdef DIAGNOSTIC 930 #define DONE ii->isdone 931 #else 932 #define DONE 0 933 #endif 934 if (ii == NULL) { 935 printf("ii NULL\n"); 936 return; 937 } 938 if (ii->xfer == NULL) { 939 printf("ii %p: done=%d xfer=NULL\n", 940 ii, DONE); 941 return; 942 } 943 pipe = ii->xfer->pipe; 944 if (pipe == NULL) { 945 printf("ii %p: done=%d xfer=%p pipe=NULL\n", 946 ii, DONE, ii->xfer); 947 return; 948 } 949 if (pipe->endpoint == NULL) { 950 printf("ii %p: done=%d xfer=%p pipe=%p pipe->endpoint=NULL\n", 951 ii, DONE, ii->xfer, pipe); 952 return; 953 } 954 if (pipe->device == NULL) { 955 printf("ii %p: done=%d xfer=%p pipe=%p pipe->device=NULL\n", 956 ii, DONE, ii->xfer, pipe); 957 return; 958 } 959 ed = pipe->endpoint->edesc; 960 dev = pipe->device; 961 printf("ii %p: done=%d xfer=%p dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 962 ii, DONE, ii->xfer, dev, 963 UGETW(dev->ddesc.idVendor), 964 UGETW(dev->ddesc.idProduct), 965 dev->address, pipe, 966 ed->bEndpointAddress, ed->bmAttributes); 967 #undef DONE 968 } 969 970 void uhci_dump_iis(struct uhci_softc *sc); 971 void 972 uhci_dump_iis(struct uhci_softc *sc) 973 { 974 uhci_intr_info_t *ii; 975 976 printf("intr_info list:\n"); 977 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 978 uhci_dump_ii(ii); 979 } 980 981 void iidump(void); 982 void iidump(void) { uhci_dump_iis(thesc); } 983 984 #endif 985 986 /* 987 * This routine is executed periodically and simulates interrupts 988 * from the root controller interrupt pipe for port status change. 989 */ 990 void 991 uhci_poll_hub(void *addr) 992 { 993 usbd_xfer_handle xfer = addr; 994 usbd_pipe_handle pipe = xfer->pipe; 995 uhci_softc_t *sc; 996 u_char *p; 997 998 DPRINTFN(20, ("uhci_poll_hub\n")); 999 1000 if (__predict_false(pipe->device == NULL || pipe->device->bus == NULL)) 1001 return; /* device has detached */ 1002 sc = pipe->device->bus->hci_private; 1003 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1004 1005 p = KERNADDR(&xfer->dmabuf, 0); 1006 p[0] = 0; 1007 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1008 p[0] |= 1<<1; 1009 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1010 p[0] |= 1<<2; 1011 if (p[0] == 0) 1012 /* No change, try again in a while */ 1013 return; 1014 1015 xfer->actlen = 1; 1016 xfer->status = USBD_NORMAL_COMPLETION; 1017 mutex_enter(&sc->sc_lock); 1018 usb_transfer_complete(xfer); 1019 mutex_exit(&sc->sc_lock); 1020 } 1021 1022 void 1023 uhci_root_intr_done(usbd_xfer_handle xfer) 1024 { 1025 } 1026 1027 void 1028 uhci_root_ctrl_done(usbd_xfer_handle xfer) 1029 { 1030 } 1031 1032 /* 1033 * Let the last QH loop back to the high speed control transfer QH. 1034 * This is what intel calls "bandwidth reclamation" and improves 1035 * USB performance a lot for some devices. 1036 * If we are already looping, just count it. 1037 */ 1038 void 1039 uhci_add_loop(uhci_softc_t *sc) { 1040 #ifdef UHCI_DEBUG 1041 if (uhcinoloop) 1042 return; 1043 #endif 1044 if (++sc->sc_loops == 1) { 1045 DPRINTFN(5,("uhci_start_loop: add\n")); 1046 /* Note, we don't loop back the soft pointer. */ 1047 sc->sc_last_qh->qh.qh_hlink = 1048 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1049 usb_syncmem(&sc->sc_last_qh->dma, 1050 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1051 sizeof(sc->sc_last_qh->qh.qh_hlink), 1052 BUS_DMASYNC_PREWRITE); 1053 } 1054 } 1055 1056 void 1057 uhci_rem_loop(uhci_softc_t *sc) { 1058 #ifdef UHCI_DEBUG 1059 if (uhcinoloop) 1060 return; 1061 #endif 1062 if (--sc->sc_loops == 0) { 1063 DPRINTFN(5,("uhci_end_loop: remove\n")); 1064 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1065 usb_syncmem(&sc->sc_last_qh->dma, 1066 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1067 sizeof(sc->sc_last_qh->qh.qh_hlink), 1068 BUS_DMASYNC_PREWRITE); 1069 } 1070 } 1071 1072 /* Add high speed control QH, called with lock held. */ 1073 void 1074 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1075 { 1076 uhci_soft_qh_t *eqh; 1077 1078 KASSERT(mutex_owned(&sc->sc_lock)); 1079 1080 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 1081 eqh = sc->sc_hctl_end; 1082 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1083 sizeof(eqh->qh.qh_hlink), 1084 BUS_DMASYNC_POSTWRITE); 1085 sqh->hlink = eqh->hlink; 1086 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1087 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1088 BUS_DMASYNC_PREWRITE); 1089 eqh->hlink = sqh; 1090 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1091 sc->sc_hctl_end = sqh; 1092 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1093 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1094 #ifdef UHCI_CTL_LOOP 1095 uhci_add_loop(sc); 1096 #endif 1097 } 1098 1099 /* Remove high speed control QH, called with lock held. */ 1100 void 1101 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1102 { 1103 uhci_soft_qh_t *pqh; 1104 uint32_t elink; 1105 1106 KASSERT(mutex_owned(&sc->sc_lock)); 1107 1108 DPRINTFN(10, ("uhci_remove_hs_ctrl: sqh=%p\n", sqh)); 1109 #ifdef UHCI_CTL_LOOP 1110 uhci_rem_loop(sc); 1111 #endif 1112 /* 1113 * The T bit should be set in the elink of the QH so that the HC 1114 * doesn't follow the pointer. This condition may fail if the 1115 * the transferred packet was short so that the QH still points 1116 * at the last used TD. 1117 * In this case we set the T bit and wait a little for the HC 1118 * to stop looking at the TD. 1119 * Note that if the TD chain is large enough, the controller 1120 * may still be looking at the chain at the end of this function. 1121 * uhci_free_std_chain() will make sure the controller stops 1122 * looking at it quickly, but until then we should not change 1123 * sqh->hlink. 1124 */ 1125 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1126 sizeof(sqh->qh.qh_elink), 1127 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1128 elink = le32toh(sqh->qh.qh_elink); 1129 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1130 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1131 if (!(elink & UHCI_PTR_T)) { 1132 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1133 usb_syncmem(&sqh->dma, 1134 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1135 sizeof(sqh->qh.qh_elink), 1136 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1137 delay(UHCI_QH_REMOVE_DELAY); 1138 } 1139 1140 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1141 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1142 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1143 pqh->hlink = sqh->hlink; 1144 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1145 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1146 sizeof(pqh->qh.qh_hlink), 1147 BUS_DMASYNC_PREWRITE); 1148 delay(UHCI_QH_REMOVE_DELAY); 1149 if (sc->sc_hctl_end == sqh) 1150 sc->sc_hctl_end = pqh; 1151 } 1152 1153 /* Add low speed control QH, called with lock held. */ 1154 void 1155 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1156 { 1157 uhci_soft_qh_t *eqh; 1158 1159 KASSERT(mutex_owned(&sc->sc_lock)); 1160 1161 DPRINTFN(10, ("uhci_add_ls_ctrl: sqh=%p\n", sqh)); 1162 eqh = sc->sc_lctl_end; 1163 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1164 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1165 sqh->hlink = eqh->hlink; 1166 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1167 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1168 BUS_DMASYNC_PREWRITE); 1169 eqh->hlink = sqh; 1170 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1171 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1172 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1173 sc->sc_lctl_end = sqh; 1174 } 1175 1176 /* Remove low speed control QH, called with lock held. */ 1177 void 1178 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1179 { 1180 uhci_soft_qh_t *pqh; 1181 uint32_t elink; 1182 1183 KASSERT(mutex_owned(&sc->sc_lock)); 1184 1185 DPRINTFN(10, ("uhci_remove_ls_ctrl: sqh=%p\n", sqh)); 1186 /* See comment in uhci_remove_hs_ctrl() */ 1187 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1188 sizeof(sqh->qh.qh_elink), 1189 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1190 elink = le32toh(sqh->qh.qh_elink); 1191 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1192 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1193 if (!(elink & UHCI_PTR_T)) { 1194 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1195 usb_syncmem(&sqh->dma, 1196 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1197 sizeof(sqh->qh.qh_elink), 1198 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1199 delay(UHCI_QH_REMOVE_DELAY); 1200 } 1201 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1202 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1203 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1204 pqh->hlink = sqh->hlink; 1205 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1206 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1207 sizeof(pqh->qh.qh_hlink), 1208 BUS_DMASYNC_PREWRITE); 1209 delay(UHCI_QH_REMOVE_DELAY); 1210 if (sc->sc_lctl_end == sqh) 1211 sc->sc_lctl_end = pqh; 1212 } 1213 1214 /* Add bulk QH, called with lock held. */ 1215 void 1216 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1217 { 1218 uhci_soft_qh_t *eqh; 1219 1220 KASSERT(mutex_owned(&sc->sc_lock)); 1221 1222 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 1223 eqh = sc->sc_bulk_end; 1224 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1225 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1226 sqh->hlink = eqh->hlink; 1227 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1228 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1229 BUS_DMASYNC_PREWRITE); 1230 eqh->hlink = sqh; 1231 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1232 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1233 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1234 sc->sc_bulk_end = sqh; 1235 uhci_add_loop(sc); 1236 } 1237 1238 /* Remove bulk QH, called with lock held. */ 1239 void 1240 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1241 { 1242 uhci_soft_qh_t *pqh; 1243 1244 KASSERT(mutex_owned(&sc->sc_lock)); 1245 1246 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 1247 uhci_rem_loop(sc); 1248 /* See comment in uhci_remove_hs_ctrl() */ 1249 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1250 sizeof(sqh->qh.qh_elink), 1251 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1252 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1253 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1254 usb_syncmem(&sqh->dma, 1255 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1256 sizeof(sqh->qh.qh_elink), 1257 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1258 delay(UHCI_QH_REMOVE_DELAY); 1259 } 1260 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1261 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1262 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1263 pqh->hlink = sqh->hlink; 1264 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1265 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1266 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1267 delay(UHCI_QH_REMOVE_DELAY); 1268 if (sc->sc_bulk_end == sqh) 1269 sc->sc_bulk_end = pqh; 1270 } 1271 1272 Static int uhci_intr1(uhci_softc_t *); 1273 1274 int 1275 uhci_intr(void *arg) 1276 { 1277 uhci_softc_t *sc = arg; 1278 int ret = 0; 1279 1280 mutex_spin_enter(&sc->sc_intr_lock); 1281 1282 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1283 goto done; 1284 1285 if (sc->sc_bus.use_polling || UREAD2(sc, UHCI_INTR) == 0) { 1286 #ifdef DIAGNOSTIC 1287 DPRINTFN(16, ("uhci_intr: ignored interrupt while polling\n")); 1288 #endif 1289 goto done; 1290 } 1291 1292 ret = uhci_intr1(sc); 1293 1294 done: 1295 mutex_spin_exit(&sc->sc_intr_lock); 1296 return ret; 1297 } 1298 1299 int 1300 uhci_intr1(uhci_softc_t *sc) 1301 { 1302 int status; 1303 int ack; 1304 1305 #ifdef UHCI_DEBUG 1306 if (uhcidebug > 15) { 1307 DPRINTF(("%s: uhci_intr1\n", device_xname(sc->sc_dev))); 1308 uhci_dumpregs(sc); 1309 } 1310 #endif 1311 1312 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1313 1314 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1315 if (status == 0) /* The interrupt was not for us. */ 1316 return (0); 1317 1318 if (sc->sc_suspend != PWR_RESUME) { 1319 #ifdef DIAGNOSTIC 1320 printf("%s: interrupt while not operating ignored\n", 1321 device_xname(sc->sc_dev)); 1322 #endif 1323 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1324 return (0); 1325 } 1326 1327 ack = 0; 1328 if (status & UHCI_STS_USBINT) 1329 ack |= UHCI_STS_USBINT; 1330 if (status & UHCI_STS_USBEI) 1331 ack |= UHCI_STS_USBEI; 1332 if (status & UHCI_STS_RD) { 1333 ack |= UHCI_STS_RD; 1334 #ifdef UHCI_DEBUG 1335 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1336 #endif 1337 } 1338 if (status & UHCI_STS_HSE) { 1339 ack |= UHCI_STS_HSE; 1340 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1341 } 1342 if (status & UHCI_STS_HCPE) { 1343 ack |= UHCI_STS_HCPE; 1344 printf("%s: host controller process error\n", 1345 device_xname(sc->sc_dev)); 1346 } 1347 1348 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1349 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1350 /* no acknowledge needed */ 1351 if (!sc->sc_dying) { 1352 printf("%s: host controller halted\n", 1353 device_xname(sc->sc_dev)); 1354 #ifdef UHCI_DEBUG 1355 uhci_dump_all(sc); 1356 #endif 1357 } 1358 sc->sc_dying = 1; 1359 } 1360 1361 if (!ack) 1362 return (0); /* nothing to acknowledge */ 1363 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1364 1365 usb_schedsoftintr(&sc->sc_bus); 1366 1367 DPRINTFN(15, ("%s: uhci_intr: exit\n", device_xname(sc->sc_dev))); 1368 1369 return (1); 1370 } 1371 1372 void 1373 uhci_softintr(void *v) 1374 { 1375 struct usbd_bus *bus = v; 1376 uhci_softc_t *sc = bus->hci_private; 1377 uhci_intr_info_t *ii, *nextii; 1378 1379 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1380 1381 DPRINTFN(10,("%s: uhci_softintr\n", device_xname(sc->sc_dev))); 1382 1383 /* 1384 * Interrupts on UHCI really suck. When the host controller 1385 * interrupts because a transfer is completed there is no 1386 * way of knowing which transfer it was. You can scan down 1387 * the TDs and QHs of the previous frame to limit the search, 1388 * but that assumes that the interrupt was not delayed by more 1389 * than 1 ms, which may not always be true (e.g. after debug 1390 * output on a slow console). 1391 * We scan all interrupt descriptors to see if any have 1392 * completed. 1393 */ 1394 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = nextii) { 1395 nextii = LIST_NEXT(ii, list); 1396 uhci_check_intr(sc, ii); 1397 } 1398 1399 if (sc->sc_softwake) { 1400 sc->sc_softwake = 0; 1401 cv_broadcast(&sc->sc_softwake_cv); 1402 } 1403 } 1404 1405 /* Check for an interrupt. */ 1406 void 1407 uhci_check_intr(uhci_softc_t *sc, uhci_intr_info_t *ii) 1408 { 1409 uhci_soft_td_t *std, *lstd; 1410 uint32_t status; 1411 1412 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 1413 #ifdef DIAGNOSTIC 1414 if (ii == NULL) { 1415 printf("uhci_check_intr: no ii? %p\n", ii); 1416 return; 1417 } 1418 #endif 1419 if (ii->xfer->status == USBD_CANCELLED || 1420 ii->xfer->status == USBD_TIMEOUT) { 1421 DPRINTF(("uhci_check_intr: aborted xfer=%p\n", ii->xfer)); 1422 return; 1423 } 1424 1425 if (ii->stdstart == NULL) 1426 return; 1427 lstd = ii->stdend; 1428 #ifdef DIAGNOSTIC 1429 if (lstd == NULL) { 1430 printf("uhci_check_intr: std==0\n"); 1431 return; 1432 } 1433 #endif 1434 usb_syncmem(&lstd->dma, 1435 lstd->offs + offsetof(uhci_td_t, td_status), 1436 sizeof(lstd->td.td_status), 1437 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1438 status = le32toh(lstd->td.td_status); 1439 usb_syncmem(&lstd->dma, 1440 lstd->offs + offsetof(uhci_td_t, td_status), 1441 sizeof(lstd->td.td_status), 1442 BUS_DMASYNC_PREREAD); 1443 1444 /* If the last TD is not marked active we can complete */ 1445 if (!(status & UHCI_TD_ACTIVE)) { 1446 done: 1447 DPRINTFN(12, ("uhci_check_intr: ii=%p done\n", ii)); 1448 callout_stop(&ii->xfer->timeout_handle); 1449 uhci_idone(ii); 1450 return; 1451 } 1452 1453 /* 1454 * If the last TD is still active we need to check whether there 1455 * is an error somewhere in the middle, or whether there was a 1456 * short packet (SPD and not ACTIVE). 1457 */ 1458 DPRINTFN(12, ("uhci_check_intr: active ii=%p\n", ii)); 1459 for (std = ii->stdstart; std != lstd; std = std->link.std) { 1460 usb_syncmem(&std->dma, 1461 std->offs + offsetof(uhci_td_t, td_status), 1462 sizeof(std->td.td_status), 1463 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1464 status = le32toh(std->td.td_status); 1465 usb_syncmem(&std->dma, 1466 std->offs + offsetof(uhci_td_t, td_status), 1467 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1468 1469 /* If there's an active TD the xfer isn't done. */ 1470 if (status & UHCI_TD_ACTIVE) { 1471 DPRINTFN(12, ("%s: ii=%p std=%p still active\n", 1472 __func__, ii, std)); 1473 return; 1474 } 1475 1476 /* Any kind of error makes the xfer done. */ 1477 if (status & UHCI_TD_STALLED) 1478 goto done; 1479 1480 /* 1481 * If the data phase of a control transfer is short, we need 1482 * to complete the status stage 1483 */ 1484 usbd_xfer_handle xfer = ii->xfer; 1485 usb_endpoint_descriptor_t *ed = xfer->pipe->endpoint->edesc; 1486 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1487 1488 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1489 struct uhci_pipe *upipe = 1490 (struct uhci_pipe *)xfer->pipe; 1491 uhci_soft_qh_t *sqh = upipe->u.ctl.sqh; 1492 uhci_soft_td_t *stat = upipe->u.ctl.stat; 1493 1494 DPRINTFN(12, ("%s: ii=%p std=%p control status" 1495 "phase needs completion\n", __func__, ii, 1496 ii->stdstart)); 1497 1498 sqh->qh.qh_elink = 1499 htole32(stat->physaddr | UHCI_PTR_TD); 1500 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1501 BUS_DMASYNC_PREWRITE); 1502 break; 1503 } 1504 1505 /* We want short packets, and it is short: it's done */ 1506 usb_syncmem(&std->dma, 1507 std->offs + offsetof(uhci_td_t, td_token), 1508 sizeof(std->td.td_token), 1509 BUS_DMASYNC_POSTWRITE); 1510 1511 if ((status & UHCI_TD_SPD) && 1512 UHCI_TD_GET_ACTLEN(status) < 1513 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1514 goto done; 1515 } 1516 } 1517 } 1518 1519 /* Called with USB lock held. */ 1520 void 1521 uhci_idone(uhci_intr_info_t *ii) 1522 { 1523 usbd_xfer_handle xfer = ii->xfer; 1524 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 1525 #ifdef DIAGNOSTIC 1526 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1527 #endif 1528 uhci_soft_td_t *std; 1529 uint32_t status = 0, nstatus; 1530 int actlen; 1531 1532 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1533 1534 DPRINTFN(12, ("uhci_idone: ii=%p\n", ii)); 1535 #ifdef DIAGNOSTIC 1536 { 1537 /* XXX SMP? */ 1538 int s = splhigh(); 1539 if (ii->isdone) { 1540 splx(s); 1541 #ifdef UHCI_DEBUG 1542 printf("uhci_idone: ii is done!\n "); 1543 uhci_dump_ii(ii); 1544 #else 1545 printf("uhci_idone: ii=%p is done!\n", ii); 1546 #endif 1547 return; 1548 } 1549 ii->isdone = 1; 1550 splx(s); 1551 } 1552 #endif 1553 1554 if (xfer->nframes != 0) { 1555 /* Isoc transfer, do things differently. */ 1556 uhci_soft_td_t **stds = upipe->u.iso.stds; 1557 int i, n, nframes, len; 1558 1559 DPRINTFN(5,("uhci_idone: ii=%p isoc ready\n", ii)); 1560 1561 nframes = xfer->nframes; 1562 actlen = 0; 1563 n = UXFER(xfer)->curframe; 1564 for (i = 0; i < nframes; i++) { 1565 std = stds[n]; 1566 #ifdef UHCI_DEBUG 1567 if (uhcidebug > 5) { 1568 DPRINTFN(-1,("uhci_idone: isoc TD %d\n", i)); 1569 uhci_dump_td(std); 1570 } 1571 #endif 1572 if (++n >= UHCI_VFRAMELIST_COUNT) 1573 n = 0; 1574 usb_syncmem(&std->dma, 1575 std->offs + offsetof(uhci_td_t, td_status), 1576 sizeof(std->td.td_status), 1577 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1578 status = le32toh(std->td.td_status); 1579 len = UHCI_TD_GET_ACTLEN(status); 1580 xfer->frlengths[i] = len; 1581 actlen += len; 1582 } 1583 upipe->u.iso.inuse -= nframes; 1584 xfer->actlen = actlen; 1585 xfer->status = USBD_NORMAL_COMPLETION; 1586 goto end; 1587 } 1588 1589 #ifdef UHCI_DEBUG 1590 DPRINTFN(10, ("uhci_idone: ii=%p, xfer=%p, pipe=%p ready\n", 1591 ii, xfer, upipe)); 1592 if (uhcidebug > 10) 1593 uhci_dump_tds(ii->stdstart); 1594 #endif 1595 1596 /* The transfer is done, compute actual length and status. */ 1597 actlen = 0; 1598 for (std = ii->stdstart; std != NULL; std = std->link.std) { 1599 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1600 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1601 nstatus = le32toh(std->td.td_status); 1602 if (nstatus & UHCI_TD_ACTIVE) 1603 break; 1604 1605 status = nstatus; 1606 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1607 UHCI_TD_PID_SETUP) 1608 actlen += UHCI_TD_GET_ACTLEN(status); 1609 else { 1610 /* 1611 * UHCI will report CRCTO in addition to a STALL or NAK 1612 * for a SETUP transaction. See section 3.2.2, "TD 1613 * CONTROL AND STATUS". 1614 */ 1615 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1616 status &= ~UHCI_TD_CRCTO; 1617 } 1618 } 1619 /* If there are left over TDs we need to update the toggle. */ 1620 if (std != NULL) 1621 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1622 1623 status &= UHCI_TD_ERROR; 1624 DPRINTFN(10, ("uhci_idone: actlen=%d, status=0x%x\n", 1625 actlen, status)); 1626 xfer->actlen = actlen; 1627 if (status != 0) { 1628 #ifdef UHCI_DEBUG 1629 char sbuf[128]; 1630 1631 snprintb(sbuf, sizeof(sbuf), 1632 "\20\22BITSTUFF\23CRCTO\24NAK\25" 1633 "BABBLE\26DBUFFER\27STALLED\30ACTIVE",(uint32_t)status); 1634 1635 DPRINTFN((status == UHCI_TD_STALLED)*10, 1636 ("uhci_idone: error, addr=%d, endpt=0x%02x, " 1637 "status 0x%s\n", 1638 xfer->pipe->device->address, 1639 xfer->pipe->endpoint->edesc->bEndpointAddress, 1640 sbuf)); 1641 #endif 1642 1643 if (status == UHCI_TD_STALLED) 1644 xfer->status = USBD_STALLED; 1645 else 1646 xfer->status = USBD_IOERROR; /* more info XXX */ 1647 } else { 1648 xfer->status = USBD_NORMAL_COMPLETION; 1649 } 1650 1651 end: 1652 usb_transfer_complete(xfer); 1653 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1654 DPRINTFN(12, ("uhci_idone: ii=%p done\n", ii)); 1655 } 1656 1657 /* 1658 * Called when a request does not complete. 1659 */ 1660 void 1661 uhci_timeout(void *addr) 1662 { 1663 uhci_intr_info_t *ii = addr; 1664 struct uhci_xfer *uxfer = UXFER(ii->xfer); 1665 struct uhci_pipe *upipe = (struct uhci_pipe *)uxfer->xfer.pipe; 1666 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 1667 1668 DPRINTF(("uhci_timeout: uxfer=%p\n", uxfer)); 1669 1670 if (sc->sc_dying) { 1671 mutex_enter(&sc->sc_lock); 1672 uhci_abort_xfer(&uxfer->xfer, USBD_TIMEOUT); 1673 mutex_exit(&sc->sc_lock); 1674 return; 1675 } 1676 1677 /* Execute the abort in a process context. */ 1678 usb_init_task(&uxfer->abort_task, uhci_timeout_task, ii->xfer, 1679 USB_TASKQ_MPSAFE); 1680 usb_add_task(uxfer->xfer.pipe->device, &uxfer->abort_task, 1681 USB_TASKQ_HC); 1682 } 1683 1684 void 1685 uhci_timeout_task(void *addr) 1686 { 1687 usbd_xfer_handle xfer = addr; 1688 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1689 1690 DPRINTF(("uhci_timeout_task: xfer=%p\n", xfer)); 1691 1692 mutex_enter(&sc->sc_lock); 1693 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1694 mutex_exit(&sc->sc_lock); 1695 } 1696 1697 /* 1698 * Wait here until controller claims to have an interrupt. 1699 * Then call uhci_intr and return. Use timeout to avoid waiting 1700 * too long. 1701 * Only used during boot when interrupts are not enabled yet. 1702 */ 1703 void 1704 uhci_waitintr(uhci_softc_t *sc, usbd_xfer_handle xfer) 1705 { 1706 int timo = xfer->timeout; 1707 uhci_intr_info_t *ii; 1708 1709 mutex_enter(&sc->sc_lock); 1710 1711 DPRINTFN(10,("uhci_waitintr: timeout = %dms\n", timo)); 1712 1713 xfer->status = USBD_IN_PROGRESS; 1714 for (; timo >= 0; timo--) { 1715 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1716 DPRINTFN(20,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 1717 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1718 mutex_spin_enter(&sc->sc_intr_lock); 1719 uhci_intr1(sc); 1720 mutex_spin_exit(&sc->sc_intr_lock); 1721 if (xfer->status != USBD_IN_PROGRESS) 1722 goto done; 1723 } 1724 } 1725 1726 /* Timeout */ 1727 DPRINTF(("uhci_waitintr: timeout\n")); 1728 for (ii = LIST_FIRST(&sc->sc_intrhead); 1729 ii != NULL && ii->xfer != xfer; 1730 ii = LIST_NEXT(ii, list)) 1731 ; 1732 #ifdef DIAGNOSTIC 1733 if (ii == NULL) 1734 panic("uhci_waitintr: lost intr_info"); 1735 #endif 1736 uhci_idone(ii); 1737 1738 done: 1739 mutex_exit(&sc->sc_lock); 1740 } 1741 1742 void 1743 uhci_poll(struct usbd_bus *bus) 1744 { 1745 uhci_softc_t *sc = bus->hci_private; 1746 1747 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1748 mutex_spin_enter(&sc->sc_intr_lock); 1749 uhci_intr1(sc); 1750 mutex_spin_exit(&sc->sc_intr_lock); 1751 } 1752 } 1753 1754 void 1755 uhci_reset(uhci_softc_t *sc) 1756 { 1757 int n; 1758 1759 UHCICMD(sc, UHCI_CMD_HCRESET); 1760 /* The reset bit goes low when the controller is done. */ 1761 for (n = 0; n < UHCI_RESET_TIMEOUT && 1762 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1763 usb_delay_ms(&sc->sc_bus, 1); 1764 if (n >= UHCI_RESET_TIMEOUT) 1765 printf("%s: controller did not reset\n", 1766 device_xname(sc->sc_dev)); 1767 } 1768 1769 usbd_status 1770 uhci_run(uhci_softc_t *sc, int run, int locked) 1771 { 1772 int n, running; 1773 uint16_t cmd; 1774 1775 run = run != 0; 1776 if (!locked) 1777 mutex_spin_enter(&sc->sc_intr_lock); 1778 DPRINTF(("uhci_run: setting run=%d\n", run)); 1779 cmd = UREAD2(sc, UHCI_CMD); 1780 if (run) 1781 cmd |= UHCI_CMD_RS; 1782 else 1783 cmd &= ~UHCI_CMD_RS; 1784 UHCICMD(sc, cmd); 1785 for(n = 0; n < 10; n++) { 1786 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1787 /* return when we've entered the state we want */ 1788 if (run == running) { 1789 if (!locked) 1790 mutex_spin_exit(&sc->sc_intr_lock); 1791 DPRINTF(("uhci_run: done cmd=0x%x sts=0x%x\n", 1792 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS))); 1793 return (USBD_NORMAL_COMPLETION); 1794 } 1795 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1796 } 1797 if (!locked) 1798 mutex_spin_exit(&sc->sc_intr_lock); 1799 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1800 run ? "start" : "stop"); 1801 return (USBD_IOERROR); 1802 } 1803 1804 /* 1805 * Memory management routines. 1806 * uhci_alloc_std allocates TDs 1807 * uhci_alloc_sqh allocates QHs 1808 * These two routines do their own free list management, 1809 * partly for speed, partly because allocating DMAable memory 1810 * has page size granularaity so much memory would be wasted if 1811 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1812 */ 1813 1814 uhci_soft_td_t * 1815 uhci_alloc_std(uhci_softc_t *sc) 1816 { 1817 uhci_soft_td_t *std; 1818 usbd_status err; 1819 int i, offs; 1820 usb_dma_t dma; 1821 1822 if (sc->sc_freetds == NULL) { 1823 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 1824 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1825 UHCI_TD_ALIGN, &dma); 1826 if (err) 1827 return (0); 1828 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1829 offs = i * UHCI_STD_SIZE; 1830 std = KERNADDR(&dma, offs); 1831 std->physaddr = DMAADDR(&dma, offs); 1832 std->dma = dma; 1833 std->offs = offs; 1834 std->link.std = sc->sc_freetds; 1835 sc->sc_freetds = std; 1836 } 1837 } 1838 std = sc->sc_freetds; 1839 sc->sc_freetds = std->link.std; 1840 memset(&std->td, 0, sizeof(uhci_td_t)); 1841 return std; 1842 } 1843 1844 void 1845 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1846 { 1847 #ifdef DIAGNOSTIC 1848 #define TD_IS_FREE 0x12345678 1849 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1850 printf("uhci_free_std: freeing free TD %p\n", std); 1851 return; 1852 } 1853 std->td.td_token = htole32(TD_IS_FREE); 1854 #endif 1855 std->link.std = sc->sc_freetds; 1856 sc->sc_freetds = std; 1857 } 1858 1859 uhci_soft_qh_t * 1860 uhci_alloc_sqh(uhci_softc_t *sc) 1861 { 1862 uhci_soft_qh_t *sqh; 1863 usbd_status err; 1864 int i, offs; 1865 usb_dma_t dma; 1866 1867 if (sc->sc_freeqhs == NULL) { 1868 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 1869 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1870 UHCI_QH_ALIGN, &dma); 1871 if (err) 1872 return (0); 1873 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1874 offs = i * UHCI_SQH_SIZE; 1875 sqh = KERNADDR(&dma, offs); 1876 sqh->physaddr = DMAADDR(&dma, offs); 1877 sqh->dma = dma; 1878 sqh->offs = offs; 1879 sqh->hlink = sc->sc_freeqhs; 1880 sc->sc_freeqhs = sqh; 1881 } 1882 } 1883 sqh = sc->sc_freeqhs; 1884 sc->sc_freeqhs = sqh->hlink; 1885 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1886 return (sqh); 1887 } 1888 1889 void 1890 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1891 { 1892 sqh->hlink = sc->sc_freeqhs; 1893 sc->sc_freeqhs = sqh; 1894 } 1895 1896 void 1897 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1898 uhci_soft_td_t *stdend) 1899 { 1900 uhci_soft_td_t *p; 1901 uint32_t td_link; 1902 1903 /* 1904 * to avoid race condition with the controller which may be looking 1905 * at this chain, we need to first invalidate all links, and 1906 * then wait for the controller to move to another queue 1907 */ 1908 for (p = std; p != stdend; p = p->link.std) { 1909 usb_syncmem(&p->dma, 1910 p->offs + offsetof(uhci_td_t, td_link), 1911 sizeof(p->td.td_link), 1912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1913 td_link = le32toh(p->td.td_link); 1914 usb_syncmem(&p->dma, 1915 p->offs + offsetof(uhci_td_t, td_link), 1916 sizeof(p->td.td_link), 1917 BUS_DMASYNC_PREREAD); 1918 if ((td_link & UHCI_PTR_T) == 0) { 1919 p->td.td_link = htole32(UHCI_PTR_T); 1920 usb_syncmem(&p->dma, 1921 p->offs + offsetof(uhci_td_t, td_link), 1922 sizeof(p->td.td_link), 1923 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1924 } 1925 } 1926 delay(UHCI_QH_REMOVE_DELAY); 1927 1928 for (; std != stdend; std = p) { 1929 p = std->link.std; 1930 uhci_free_std(sc, std); 1931 } 1932 } 1933 1934 usbd_status 1935 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1936 int rd, uint16_t flags, usb_dma_t *dma, 1937 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1938 { 1939 uhci_soft_td_t *p, *lastp; 1940 uhci_physaddr_t lastlink; 1941 int i, ntd, l, tog, maxp; 1942 uint32_t status; 1943 int addr = upipe->pipe.device->address; 1944 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1945 1946 DPRINTFN(8, ("uhci_alloc_std_chain: addr=%d endpt=%d len=%d speed=%d " 1947 "flags=0x%x\n", addr, UE_GET_ADDR(endpt), len, 1948 upipe->pipe.device->speed, flags)); 1949 1950 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1951 1952 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1953 if (maxp == 0) { 1954 printf("uhci_alloc_std_chain: maxp=0\n"); 1955 return (USBD_INVAL); 1956 } 1957 ntd = (len + maxp - 1) / maxp; 1958 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1959 ntd++; 1960 DPRINTFN(10, ("uhci_alloc_std_chain: maxp=%d ntd=%d\n", maxp, ntd)); 1961 if (ntd == 0) { 1962 *sp = *ep = 0; 1963 DPRINTFN(-1,("uhci_alloc_std_chain: ntd=0\n")); 1964 return (USBD_NORMAL_COMPLETION); 1965 } 1966 tog = upipe->nexttoggle; 1967 if (ntd % 2 == 0) 1968 tog ^= 1; 1969 upipe->nexttoggle = tog ^ 1; 1970 lastp = NULL; 1971 lastlink = UHCI_PTR_T; 1972 ntd--; 1973 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1974 if (upipe->pipe.device->speed == USB_SPEED_LOW) 1975 status |= UHCI_TD_LS; 1976 if (flags & USBD_SHORT_XFER_OK) 1977 status |= UHCI_TD_SPD; 1978 usb_syncmem(dma, 0, len, 1979 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1980 for (i = ntd; i >= 0; i--) { 1981 p = uhci_alloc_std(sc); 1982 if (p == NULL) { 1983 KASSERT(lastp != NULL); 1984 uhci_free_std_chain(sc, lastp, NULL); 1985 return (USBD_NOMEM); 1986 } 1987 p->link.std = lastp; 1988 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1989 lastp = p; 1990 lastlink = p->physaddr; 1991 p->td.td_status = htole32(status); 1992 if (i == ntd) { 1993 /* last TD */ 1994 l = len % maxp; 1995 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1996 l = maxp; 1997 *ep = p; 1998 } else 1999 l = maxp; 2000 p->td.td_token = 2001 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 2002 UHCI_TD_OUT(l, endpt, addr, tog)); 2003 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2004 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 2005 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2006 tog ^= 1; 2007 } 2008 *sp = lastp; 2009 DPRINTFN(10, ("uhci_alloc_std_chain: nexttog=%d\n", 2010 upipe->nexttoggle)); 2011 return (USBD_NORMAL_COMPLETION); 2012 } 2013 2014 void 2015 uhci_device_clear_toggle(usbd_pipe_handle pipe) 2016 { 2017 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2018 upipe->nexttoggle = 0; 2019 } 2020 2021 void 2022 uhci_noop(usbd_pipe_handle pipe) 2023 { 2024 } 2025 2026 usbd_status 2027 uhci_device_bulk_transfer(usbd_xfer_handle xfer) 2028 { 2029 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2030 usbd_status err; 2031 2032 /* Insert last in queue. */ 2033 mutex_enter(&sc->sc_lock); 2034 err = usb_insert_transfer(xfer); 2035 mutex_exit(&sc->sc_lock); 2036 if (err) 2037 return (err); 2038 2039 /* 2040 * Pipe isn't running (otherwise err would be USBD_INPROG), 2041 * so start it first. 2042 */ 2043 return (uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2044 } 2045 2046 usbd_status 2047 uhci_device_bulk_start(usbd_xfer_handle xfer) 2048 { 2049 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2050 usbd_device_handle dev = upipe->pipe.device; 2051 uhci_softc_t *sc = dev->bus->hci_private; 2052 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2053 uhci_soft_td_t *data, *dataend; 2054 uhci_soft_qh_t *sqh; 2055 usbd_status err; 2056 int len, isread, endpt; 2057 2058 DPRINTFN(3, ("uhci_device_bulk_start: xfer=%p len=%d flags=%d ii=%p\n", 2059 xfer, xfer->length, xfer->flags, ii)); 2060 2061 if (sc->sc_dying) 2062 return (USBD_IOERROR); 2063 2064 #ifdef DIAGNOSTIC 2065 if (xfer->rqflags & URQ_REQUEST) 2066 panic("uhci_device_bulk_transfer: a request"); 2067 #endif 2068 2069 mutex_enter(&sc->sc_lock); 2070 2071 len = xfer->length; 2072 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2073 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2074 sqh = upipe->u.bulk.sqh; 2075 2076 upipe->u.bulk.isread = isread; 2077 upipe->u.bulk.length = len; 2078 2079 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2080 &xfer->dmabuf, &data, &dataend); 2081 if (err) { 2082 mutex_exit(&sc->sc_lock); 2083 return (err); 2084 } 2085 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2086 usb_syncmem(&dataend->dma, 2087 dataend->offs + offsetof(uhci_td_t, td_status), 2088 sizeof(dataend->td.td_status), 2089 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2090 2091 2092 #ifdef UHCI_DEBUG 2093 if (uhcidebug > 8) { 2094 DPRINTF(("uhci_device_bulk_transfer: data(1)\n")); 2095 uhci_dump_tds(data); 2096 } 2097 #endif 2098 2099 /* Set up interrupt info. */ 2100 ii->xfer = xfer; 2101 ii->stdstart = data; 2102 ii->stdend = dataend; 2103 #ifdef DIAGNOSTIC 2104 if (!ii->isdone) { 2105 printf("uhci_device_bulk_transfer: not done, ii=%p\n", ii); 2106 } 2107 ii->isdone = 0; 2108 #endif 2109 2110 sqh->elink = data; 2111 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2112 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2113 2114 uhci_add_bulk(sc, sqh); 2115 uhci_add_intr_info(sc, ii); 2116 2117 if (xfer->timeout && !sc->sc_bus.use_polling) { 2118 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2119 uhci_timeout, ii); 2120 } 2121 xfer->status = USBD_IN_PROGRESS; 2122 2123 #ifdef UHCI_DEBUG 2124 if (uhcidebug > 10) { 2125 DPRINTF(("uhci_device_bulk_transfer: data(2)\n")); 2126 uhci_dump_tds(data); 2127 } 2128 #endif 2129 2130 if (sc->sc_bus.use_polling) 2131 uhci_waitintr(sc, xfer); 2132 2133 mutex_exit(&sc->sc_lock); 2134 return (USBD_IN_PROGRESS); 2135 } 2136 2137 /* Abort a device bulk request. */ 2138 void 2139 uhci_device_bulk_abort(usbd_xfer_handle xfer) 2140 { 2141 #ifdef DIAGNOSTIC 2142 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2143 #endif 2144 2145 KASSERT(mutex_owned(&sc->sc_lock)); 2146 2147 DPRINTF(("uhci_device_bulk_abort:\n")); 2148 uhci_abort_xfer(xfer, USBD_CANCELLED); 2149 } 2150 2151 /* 2152 * Abort a device request. 2153 * If this routine is called at splusb() it guarantees that the request 2154 * will be removed from the hardware scheduling and that the callback 2155 * for it will be called with USBD_CANCELLED status. 2156 * It's impossible to guarantee that the requested transfer will not 2157 * have happened since the hardware runs concurrently. 2158 * If the transaction has already happened we rely on the ordinary 2159 * interrupt processing to process it. 2160 * XXX This is most probably wrong. 2161 * XXXMRG this doesn't make sense anymore. 2162 */ 2163 void 2164 uhci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2165 { 2166 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2167 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2168 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2169 uhci_soft_td_t *std; 2170 int wake; 2171 2172 DPRINTFN(1,("uhci_abort_xfer: xfer=%p, status=%d\n", xfer, status)); 2173 2174 KASSERT(mutex_owned(&sc->sc_lock)); 2175 ASSERT_SLEEPABLE(); 2176 2177 if (sc->sc_dying) { 2178 /* If we're dying, just do the software part. */ 2179 xfer->status = status; /* make software ignore it */ 2180 callout_stop(&xfer->timeout_handle); 2181 usb_transfer_complete(xfer); 2182 return; 2183 } 2184 2185 /* 2186 * If an abort is already in progress then just wait for it to 2187 * complete and return. 2188 */ 2189 if (xfer->hcflags & UXFER_ABORTING) { 2190 DPRINTFN(2, ("uhci_abort_xfer: already aborting\n")); 2191 #ifdef DIAGNOSTIC 2192 if (status == USBD_TIMEOUT) 2193 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2194 #endif 2195 /* Override the status which might be USBD_TIMEOUT. */ 2196 xfer->status = status; 2197 DPRINTFN(2, ("uhci_abort_xfer: waiting for abort to finish\n")); 2198 xfer->hcflags |= UXFER_ABORTWAIT; 2199 while (xfer->hcflags & UXFER_ABORTING) 2200 cv_wait(&xfer->hccv, &sc->sc_lock); 2201 goto done; 2202 } 2203 xfer->hcflags |= UXFER_ABORTING; 2204 2205 /* 2206 * Step 1: Make interrupt routine and hardware ignore xfer. 2207 */ 2208 xfer->status = status; /* make software ignore it */ 2209 callout_stop(&xfer->timeout_handle); 2210 DPRINTFN(1,("uhci_abort_xfer: stop ii=%p\n", ii)); 2211 for (std = ii->stdstart; std != NULL; std = std->link.std) { 2212 usb_syncmem(&std->dma, 2213 std->offs + offsetof(uhci_td_t, td_status), 2214 sizeof(std->td.td_status), 2215 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2216 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2217 usb_syncmem(&std->dma, 2218 std->offs + offsetof(uhci_td_t, td_status), 2219 sizeof(std->td.td_status), 2220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2221 } 2222 2223 /* 2224 * Step 2: Wait until we know hardware has finished any possible 2225 * use of the xfer. Also make sure the soft interrupt routine 2226 * has run. 2227 */ 2228 /* Hardware finishes in 1ms */ 2229 usb_delay_ms_locked(upipe->pipe.device->bus, 2, &sc->sc_lock); 2230 sc->sc_softwake = 1; 2231 usb_schedsoftintr(&sc->sc_bus); 2232 DPRINTFN(1,("uhci_abort_xfer: cv_wait\n")); 2233 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2234 2235 /* 2236 * Step 3: Execute callback. 2237 */ 2238 DPRINTFN(1,("uhci_abort_xfer: callback\n")); 2239 #ifdef DIAGNOSTIC 2240 ii->isdone = 1; 2241 #endif 2242 wake = xfer->hcflags & UXFER_ABORTWAIT; 2243 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2244 usb_transfer_complete(xfer); 2245 if (wake) 2246 cv_broadcast(&xfer->hccv); 2247 done: 2248 KASSERT(mutex_owned(&sc->sc_lock)); 2249 } 2250 2251 /* Close a device bulk pipe. */ 2252 void 2253 uhci_device_bulk_close(usbd_pipe_handle pipe) 2254 { 2255 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2256 usbd_device_handle dev = upipe->pipe.device; 2257 uhci_softc_t *sc = dev->bus->hci_private; 2258 2259 KASSERT(mutex_owned(&sc->sc_lock)); 2260 2261 uhci_free_sqh(sc, upipe->u.bulk.sqh); 2262 2263 pipe->endpoint->datatoggle = upipe->nexttoggle; 2264 } 2265 2266 usbd_status 2267 uhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2268 { 2269 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2270 usbd_status err; 2271 2272 /* Insert last in queue. */ 2273 mutex_enter(&sc->sc_lock); 2274 err = usb_insert_transfer(xfer); 2275 mutex_exit(&sc->sc_lock); 2276 if (err) 2277 return (err); 2278 2279 /* 2280 * Pipe isn't running (otherwise err would be USBD_INPROG), 2281 * so start it first. 2282 */ 2283 return (uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2284 } 2285 2286 usbd_status 2287 uhci_device_ctrl_start(usbd_xfer_handle xfer) 2288 { 2289 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2290 usbd_status err; 2291 2292 if (sc->sc_dying) 2293 return (USBD_IOERROR); 2294 2295 #ifdef DIAGNOSTIC 2296 if (!(xfer->rqflags & URQ_REQUEST)) 2297 panic("uhci_device_ctrl_transfer: not a request"); 2298 #endif 2299 2300 mutex_enter(&sc->sc_lock); 2301 err = uhci_device_request(xfer); 2302 mutex_exit(&sc->sc_lock); 2303 if (err) 2304 return (err); 2305 2306 if (sc->sc_bus.use_polling) 2307 uhci_waitintr(sc, xfer); 2308 return (USBD_IN_PROGRESS); 2309 } 2310 2311 usbd_status 2312 uhci_device_intr_transfer(usbd_xfer_handle xfer) 2313 { 2314 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2315 usbd_status err; 2316 2317 /* Insert last in queue. */ 2318 mutex_enter(&sc->sc_lock); 2319 err = usb_insert_transfer(xfer); 2320 mutex_exit(&sc->sc_lock); 2321 if (err) 2322 return (err); 2323 2324 /* 2325 * Pipe isn't running (otherwise err would be USBD_INPROG), 2326 * so start it first. 2327 */ 2328 return (uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2329 } 2330 2331 usbd_status 2332 uhci_device_intr_start(usbd_xfer_handle xfer) 2333 { 2334 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2335 usbd_device_handle dev = upipe->pipe.device; 2336 uhci_softc_t *sc = dev->bus->hci_private; 2337 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2338 uhci_soft_td_t *data, *dataend; 2339 uhci_soft_qh_t *sqh; 2340 usbd_status err; 2341 int isread, endpt; 2342 int i; 2343 2344 if (sc->sc_dying) 2345 return (USBD_IOERROR); 2346 2347 DPRINTFN(3,("uhci_device_intr_transfer: xfer=%p len=%d flags=%d\n", 2348 xfer, xfer->length, xfer->flags)); 2349 2350 #ifdef DIAGNOSTIC 2351 if (xfer->rqflags & URQ_REQUEST) 2352 panic("uhci_device_intr_transfer: a request"); 2353 #endif 2354 2355 mutex_enter(&sc->sc_lock); 2356 2357 endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2358 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2359 2360 upipe->u.intr.isread = isread; 2361 2362 err = uhci_alloc_std_chain(upipe, sc, xfer->length, isread, 2363 xfer->flags, &xfer->dmabuf, &data, 2364 &dataend); 2365 if (err) { 2366 mutex_exit(&sc->sc_lock); 2367 return (err); 2368 } 2369 2370 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2371 usb_syncmem(&dataend->dma, 2372 dataend->offs + offsetof(uhci_td_t, td_status), 2373 sizeof(dataend->td.td_status), 2374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2375 2376 #ifdef UHCI_DEBUG 2377 if (uhcidebug > 10) { 2378 DPRINTF(("uhci_device_intr_transfer: data(1)\n")); 2379 uhci_dump_tds(data); 2380 uhci_dump_qh(upipe->u.intr.qhs[0]); 2381 } 2382 #endif 2383 2384 /* Set up interrupt info. */ 2385 ii->xfer = xfer; 2386 ii->stdstart = data; 2387 ii->stdend = dataend; 2388 #ifdef DIAGNOSTIC 2389 if (!ii->isdone) { 2390 printf("uhci_device_intr_transfer: not done, ii=%p\n", ii); 2391 } 2392 ii->isdone = 0; 2393 #endif 2394 2395 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", 2396 upipe->u.intr.qhs[0])); 2397 for (i = 0; i < upipe->u.intr.npoll; i++) { 2398 sqh = upipe->u.intr.qhs[i]; 2399 sqh->elink = data; 2400 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2401 usb_syncmem(&sqh->dma, 2402 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2403 sizeof(sqh->qh.qh_elink), 2404 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2405 } 2406 uhci_add_intr_info(sc, ii); 2407 xfer->status = USBD_IN_PROGRESS; 2408 mutex_exit(&sc->sc_lock); 2409 2410 #ifdef UHCI_DEBUG 2411 if (uhcidebug > 10) { 2412 DPRINTF(("uhci_device_intr_transfer: data(2)\n")); 2413 uhci_dump_tds(data); 2414 uhci_dump_qh(upipe->u.intr.qhs[0]); 2415 } 2416 #endif 2417 2418 return (USBD_IN_PROGRESS); 2419 } 2420 2421 /* Abort a device control request. */ 2422 void 2423 uhci_device_ctrl_abort(usbd_xfer_handle xfer) 2424 { 2425 #ifdef DIAGNOSTIC 2426 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2427 #endif 2428 2429 KASSERT(mutex_owned(&sc->sc_lock)); 2430 2431 DPRINTF(("uhci_device_ctrl_abort:\n")); 2432 uhci_abort_xfer(xfer, USBD_CANCELLED); 2433 } 2434 2435 /* Close a device control pipe. */ 2436 void 2437 uhci_device_ctrl_close(usbd_pipe_handle pipe) 2438 { 2439 } 2440 2441 /* Abort a device interrupt request. */ 2442 void 2443 uhci_device_intr_abort(usbd_xfer_handle xfer) 2444 { 2445 #ifdef DIAGNOSTIC 2446 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2447 #endif 2448 2449 KASSERT(mutex_owned(&sc->sc_lock)); 2450 KASSERT(xfer->pipe->intrxfer == xfer); 2451 2452 DPRINTFN(1,("uhci_device_intr_abort: xfer=%p\n", xfer)); 2453 2454 uhci_abort_xfer(xfer, USBD_CANCELLED); 2455 } 2456 2457 /* Close a device interrupt pipe. */ 2458 void 2459 uhci_device_intr_close(usbd_pipe_handle pipe) 2460 { 2461 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2462 uhci_softc_t *sc = pipe->device->bus->hci_private; 2463 int i, npoll; 2464 2465 KASSERT(mutex_owned(&sc->sc_lock)); 2466 2467 /* Unlink descriptors from controller data structures. */ 2468 npoll = upipe->u.intr.npoll; 2469 for (i = 0; i < npoll; i++) 2470 uhci_remove_intr(sc, upipe->u.intr.qhs[i]); 2471 2472 /* 2473 * We now have to wait for any activity on the physical 2474 * descriptors to stop. 2475 */ 2476 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2477 2478 for(i = 0; i < npoll; i++) 2479 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 2480 kmem_free(upipe->u.intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2481 2482 /* XXX free other resources */ 2483 } 2484 2485 usbd_status 2486 uhci_device_request(usbd_xfer_handle xfer) 2487 { 2488 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2489 usb_device_request_t *req = &xfer->request; 2490 usbd_device_handle dev = upipe->pipe.device; 2491 uhci_softc_t *sc = dev->bus->hci_private; 2492 int addr = dev->address; 2493 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2494 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2495 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2496 uhci_soft_qh_t *sqh; 2497 int len; 2498 uint32_t ls; 2499 usbd_status err; 2500 int isread; 2501 2502 KASSERT(mutex_owned(&sc->sc_lock)); 2503 2504 DPRINTFN(3,("uhci_device_control type=0x%02x, request=0x%02x, " 2505 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2506 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2507 UGETW(req->wIndex), UGETW(req->wLength), 2508 addr, endpt)); 2509 2510 ls = dev->speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2511 isread = req->bmRequestType & UT_READ; 2512 len = UGETW(req->wLength); 2513 2514 setup = upipe->u.ctl.setup; 2515 stat = upipe->u.ctl.stat; 2516 sqh = upipe->u.ctl.sqh; 2517 2518 /* Set up data transaction */ 2519 if (len != 0) { 2520 upipe->nexttoggle = 1; 2521 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->flags, 2522 &xfer->dmabuf, &data, &dataend); 2523 if (err) 2524 return (err); 2525 next = data; 2526 dataend->link.std = stat; 2527 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2528 usb_syncmem(&dataend->dma, 2529 dataend->offs + offsetof(uhci_td_t, td_link), 2530 sizeof(dataend->td.td_link), 2531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2532 } else { 2533 next = stat; 2534 } 2535 upipe->u.ctl.length = len; 2536 2537 memcpy(KERNADDR(&upipe->u.ctl.reqdma, 0), req, sizeof *req); 2538 usb_syncmem(&upipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2539 2540 setup->link.std = next; 2541 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2542 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2543 UHCI_TD_ACTIVE); 2544 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof *req, endpt, addr)); 2545 setup->td.td_buffer = htole32(DMAADDR(&upipe->u.ctl.reqdma, 0)); 2546 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2548 2549 stat->link.std = NULL; 2550 stat->td.td_link = htole32(UHCI_PTR_T); 2551 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2552 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2553 stat->td.td_token = 2554 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2555 UHCI_TD_IN (0, endpt, addr, 1)); 2556 stat->td.td_buffer = htole32(0); 2557 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2559 2560 #ifdef UHCI_DEBUG 2561 if (uhcidebug > 10) { 2562 DPRINTF(("uhci_device_request: before transfer\n")); 2563 uhci_dump_tds(setup); 2564 } 2565 #endif 2566 2567 /* Set up interrupt info. */ 2568 ii->xfer = xfer; 2569 ii->stdstart = setup; 2570 ii->stdend = stat; 2571 #ifdef DIAGNOSTIC 2572 if (!ii->isdone) { 2573 printf("uhci_device_request: not done, ii=%p\n", ii); 2574 } 2575 ii->isdone = 0; 2576 #endif 2577 2578 sqh->elink = setup; 2579 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2580 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2581 2582 if (dev->speed == USB_SPEED_LOW) 2583 uhci_add_ls_ctrl(sc, sqh); 2584 else 2585 uhci_add_hs_ctrl(sc, sqh); 2586 uhci_add_intr_info(sc, ii); 2587 #ifdef UHCI_DEBUG 2588 if (uhcidebug > 12) { 2589 uhci_soft_td_t *std; 2590 uhci_soft_qh_t *xqh; 2591 uhci_soft_qh_t *sxqh; 2592 int maxqh = 0; 2593 uhci_physaddr_t link; 2594 DPRINTF(("uhci_enter_ctl_q: follow from [0]\n")); 2595 for (std = sc->sc_vframes[0].htd, link = 0; 2596 (link & UHCI_PTR_QH) == 0; 2597 std = std->link.std) { 2598 link = le32toh(std->td.td_link); 2599 uhci_dump_td(std); 2600 } 2601 sxqh = (uhci_soft_qh_t *)std; 2602 uhci_dump_qh(sxqh); 2603 for (xqh = sxqh; 2604 xqh != NULL; 2605 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2606 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2607 uhci_dump_qh(xqh); 2608 } 2609 DPRINTF(("Enqueued QH:\n")); 2610 uhci_dump_qh(sqh); 2611 uhci_dump_tds(sqh->elink); 2612 } 2613 #endif 2614 if (xfer->timeout && !sc->sc_bus.use_polling) { 2615 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2616 uhci_timeout, ii); 2617 } 2618 xfer->status = USBD_IN_PROGRESS; 2619 2620 return (USBD_NORMAL_COMPLETION); 2621 } 2622 2623 usbd_status 2624 uhci_device_isoc_transfer(usbd_xfer_handle xfer) 2625 { 2626 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2627 usbd_status err; 2628 2629 DPRINTFN(5,("uhci_device_isoc_transfer: xfer=%p\n", xfer)); 2630 2631 /* Put it on our queue, */ 2632 mutex_enter(&sc->sc_lock); 2633 err = usb_insert_transfer(xfer); 2634 mutex_exit(&sc->sc_lock); 2635 2636 /* bail out on error, */ 2637 if (err && err != USBD_IN_PROGRESS) 2638 return (err); 2639 2640 /* XXX should check inuse here */ 2641 2642 /* insert into schedule, */ 2643 uhci_device_isoc_enter(xfer); 2644 2645 /* and start if the pipe wasn't running */ 2646 if (!err) 2647 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 2648 2649 return (err); 2650 } 2651 2652 void 2653 uhci_device_isoc_enter(usbd_xfer_handle xfer) 2654 { 2655 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2656 usbd_device_handle dev = upipe->pipe.device; 2657 uhci_softc_t *sc = dev->bus->hci_private; 2658 struct iso *iso = &upipe->u.iso; 2659 uhci_soft_td_t *std; 2660 uint32_t buf, len, status, offs; 2661 int i, next, nframes; 2662 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2663 2664 DPRINTFN(5,("uhci_device_isoc_enter: used=%d next=%d xfer=%p " 2665 "nframes=%d\n", 2666 iso->inuse, iso->next, xfer, xfer->nframes)); 2667 2668 if (sc->sc_dying) 2669 return; 2670 2671 if (xfer->status == USBD_IN_PROGRESS) { 2672 /* This request has already been entered into the frame list */ 2673 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2674 /* XXX */ 2675 } 2676 2677 #ifdef DIAGNOSTIC 2678 if (iso->inuse >= UHCI_VFRAMELIST_COUNT) 2679 printf("uhci_device_isoc_enter: overflow!\n"); 2680 #endif 2681 2682 next = iso->next; 2683 if (next == -1) { 2684 /* Not in use yet, schedule it a few frames ahead. */ 2685 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2686 DPRINTFN(2,("uhci_device_isoc_enter: start next=%d\n", next)); 2687 } 2688 2689 xfer->status = USBD_IN_PROGRESS; 2690 UXFER(xfer)->curframe = next; 2691 2692 buf = DMAADDR(&xfer->dmabuf, 0); 2693 offs = 0; 2694 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2695 UHCI_TD_ACTIVE | 2696 UHCI_TD_IOS); 2697 nframes = xfer->nframes; 2698 mutex_enter(&sc->sc_lock); 2699 for (i = 0; i < nframes; i++) { 2700 std = iso->stds[next]; 2701 if (++next >= UHCI_VFRAMELIST_COUNT) 2702 next = 0; 2703 len = xfer->frlengths[i]; 2704 std->td.td_buffer = htole32(buf); 2705 usb_syncmem(&xfer->dmabuf, offs, len, 2706 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2707 if (i == nframes - 1) 2708 status |= UHCI_TD_IOC; 2709 std->td.td_status = htole32(status); 2710 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2711 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2712 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2713 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2714 #ifdef UHCI_DEBUG 2715 if (uhcidebug > 5) { 2716 DPRINTFN(5,("uhci_device_isoc_enter: TD %d\n", i)); 2717 uhci_dump_td(std); 2718 } 2719 #endif 2720 buf += len; 2721 offs += len; 2722 } 2723 iso->next = next; 2724 iso->inuse += xfer->nframes; 2725 2726 mutex_exit(&sc->sc_lock); 2727 } 2728 2729 usbd_status 2730 uhci_device_isoc_start(usbd_xfer_handle xfer) 2731 { 2732 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2733 uhci_softc_t *sc = upipe->pipe.device->bus->hci_private; 2734 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2735 uhci_soft_td_t *end; 2736 int i; 2737 2738 DPRINTFN(5,("uhci_device_isoc_start: xfer=%p\n", xfer)); 2739 2740 mutex_enter(&sc->sc_lock); 2741 2742 if (sc->sc_dying) { 2743 mutex_exit(&sc->sc_lock); 2744 return (USBD_IOERROR); 2745 } 2746 2747 #ifdef DIAGNOSTIC 2748 if (xfer->status != USBD_IN_PROGRESS) 2749 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2750 #endif 2751 2752 /* Find the last TD */ 2753 i = UXFER(xfer)->curframe + xfer->nframes; 2754 if (i >= UHCI_VFRAMELIST_COUNT) 2755 i -= UHCI_VFRAMELIST_COUNT; 2756 end = upipe->u.iso.stds[i]; 2757 2758 #ifdef DIAGNOSTIC 2759 if (end == NULL) { 2760 printf("uhci_device_isoc_start: end == NULL\n"); 2761 return (USBD_INVAL); 2762 } 2763 #endif 2764 2765 /* Set up interrupt info. */ 2766 ii->xfer = xfer; 2767 ii->stdstart = end; 2768 ii->stdend = end; 2769 #ifdef DIAGNOSTIC 2770 if (!ii->isdone) 2771 printf("uhci_device_isoc_start: not done, ii=%p\n", ii); 2772 ii->isdone = 0; 2773 #endif 2774 uhci_add_intr_info(sc, ii); 2775 2776 mutex_exit(&sc->sc_lock); 2777 2778 return (USBD_IN_PROGRESS); 2779 } 2780 2781 void 2782 uhci_device_isoc_abort(usbd_xfer_handle xfer) 2783 { 2784 #ifdef DIAGNOSTIC 2785 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2786 #endif 2787 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2788 uhci_soft_td_t **stds = upipe->u.iso.stds; 2789 uhci_soft_td_t *std; 2790 int i, n, nframes, maxlen, len; 2791 2792 KASSERT(mutex_owned(&sc->sc_lock)); 2793 2794 /* Transfer is already done. */ 2795 if (xfer->status != USBD_NOT_STARTED && 2796 xfer->status != USBD_IN_PROGRESS) { 2797 return; 2798 } 2799 2800 /* Give xfer the requested abort code. */ 2801 xfer->status = USBD_CANCELLED; 2802 2803 /* make hardware ignore it, */ 2804 nframes = xfer->nframes; 2805 n = UXFER(xfer)->curframe; 2806 maxlen = 0; 2807 for (i = 0; i < nframes; i++) { 2808 std = stds[n]; 2809 usb_syncmem(&std->dma, 2810 std->offs + offsetof(uhci_td_t, td_status), 2811 sizeof(std->td.td_status), 2812 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2813 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2814 usb_syncmem(&std->dma, 2815 std->offs + offsetof(uhci_td_t, td_status), 2816 sizeof(std->td.td_status), 2817 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2818 usb_syncmem(&std->dma, 2819 std->offs + offsetof(uhci_td_t, td_token), 2820 sizeof(std->td.td_token), 2821 BUS_DMASYNC_POSTWRITE); 2822 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2823 if (len > maxlen) 2824 maxlen = len; 2825 if (++n >= UHCI_VFRAMELIST_COUNT) 2826 n = 0; 2827 } 2828 2829 /* and wait until we are sure the hardware has finished. */ 2830 delay(maxlen); 2831 2832 #ifdef DIAGNOSTIC 2833 UXFER(xfer)->iinfo.isdone = 1; 2834 #endif 2835 /* Run callback and remove from interrupt list. */ 2836 usb_transfer_complete(xfer); 2837 2838 KASSERT(mutex_owned(&sc->sc_lock)); 2839 } 2840 2841 void 2842 uhci_device_isoc_close(usbd_pipe_handle pipe) 2843 { 2844 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2845 usbd_device_handle dev = upipe->pipe.device; 2846 uhci_softc_t *sc = dev->bus->hci_private; 2847 uhci_soft_td_t *std, *vstd; 2848 struct iso *iso; 2849 int i; 2850 2851 KASSERT(mutex_owned(&sc->sc_lock)); 2852 2853 /* 2854 * Make sure all TDs are marked as inactive. 2855 * Wait for completion. 2856 * Unschedule. 2857 * Deallocate. 2858 */ 2859 iso = &upipe->u.iso; 2860 2861 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2862 std = iso->stds[i]; 2863 usb_syncmem(&std->dma, 2864 std->offs + offsetof(uhci_td_t, td_status), 2865 sizeof(std->td.td_status), 2866 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2867 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2868 usb_syncmem(&std->dma, 2869 std->offs + offsetof(uhci_td_t, td_status), 2870 sizeof(std->td.td_status), 2871 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2872 } 2873 /* wait for completion */ 2874 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2875 2876 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2877 std = iso->stds[i]; 2878 for (vstd = sc->sc_vframes[i].htd; 2879 vstd != NULL && vstd->link.std != std; 2880 vstd = vstd->link.std) 2881 ; 2882 if (vstd == NULL) { 2883 /*panic*/ 2884 printf("uhci_device_isoc_close: %p not found\n", std); 2885 mutex_exit(&sc->sc_lock); 2886 return; 2887 } 2888 vstd->link = std->link; 2889 usb_syncmem(&std->dma, 2890 std->offs + offsetof(uhci_td_t, td_link), 2891 sizeof(std->td.td_link), 2892 BUS_DMASYNC_POSTWRITE); 2893 vstd->td.td_link = std->td.td_link; 2894 usb_syncmem(&vstd->dma, 2895 vstd->offs + offsetof(uhci_td_t, td_link), 2896 sizeof(vstd->td.td_link), 2897 BUS_DMASYNC_PREWRITE); 2898 uhci_free_std(sc, std); 2899 } 2900 2901 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2902 } 2903 2904 usbd_status 2905 uhci_setup_isoc(usbd_pipe_handle pipe) 2906 { 2907 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2908 usbd_device_handle dev = upipe->pipe.device; 2909 uhci_softc_t *sc = dev->bus->hci_private; 2910 int addr = upipe->pipe.device->address; 2911 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 2912 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2913 uhci_soft_td_t *std, *vstd; 2914 uint32_t token; 2915 struct iso *iso; 2916 int i; 2917 2918 iso = &upipe->u.iso; 2919 iso->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2920 sizeof (uhci_soft_td_t *), 2921 KM_SLEEP); 2922 if (iso->stds == NULL) 2923 return USBD_NOMEM; 2924 2925 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2926 UHCI_TD_OUT(0, endpt, addr, 0); 2927 2928 mutex_enter(&sc->sc_lock); 2929 2930 /* Allocate the TDs and mark as inactive; */ 2931 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2932 std = uhci_alloc_std(sc); 2933 if (std == 0) 2934 goto bad; 2935 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2936 std->td.td_token = htole32(token); 2937 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2938 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2939 iso->stds[i] = std; 2940 } 2941 2942 /* Insert TDs into schedule. */ 2943 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2944 std = iso->stds[i]; 2945 vstd = sc->sc_vframes[i].htd; 2946 usb_syncmem(&vstd->dma, 2947 vstd->offs + offsetof(uhci_td_t, td_link), 2948 sizeof(vstd->td.td_link), 2949 BUS_DMASYNC_POSTWRITE); 2950 std->link = vstd->link; 2951 std->td.td_link = vstd->td.td_link; 2952 usb_syncmem(&std->dma, 2953 std->offs + offsetof(uhci_td_t, td_link), 2954 sizeof(std->td.td_link), 2955 BUS_DMASYNC_PREWRITE); 2956 vstd->link.std = std; 2957 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2958 usb_syncmem(&vstd->dma, 2959 vstd->offs + offsetof(uhci_td_t, td_link), 2960 sizeof(vstd->td.td_link), 2961 BUS_DMASYNC_PREWRITE); 2962 } 2963 mutex_exit(&sc->sc_lock); 2964 2965 iso->next = -1; 2966 iso->inuse = 0; 2967 2968 return (USBD_NORMAL_COMPLETION); 2969 2970 bad: 2971 while (--i >= 0) 2972 uhci_free_std(sc, iso->stds[i]); 2973 mutex_exit(&sc->sc_lock); 2974 kmem_free(iso->stds, UHCI_VFRAMELIST_COUNT * sizeof (uhci_soft_td_t *)); 2975 return (USBD_NOMEM); 2976 } 2977 2978 void 2979 uhci_device_isoc_done(usbd_xfer_handle xfer) 2980 { 2981 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 2982 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 2983 int i, offs; 2984 int rd = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 2985 2986 2987 DPRINTFN(4, ("uhci_isoc_done: length=%d, busy_free=0x%08x\n", 2988 xfer->actlen, xfer->busy_free)); 2989 2990 if (ii->xfer != xfer) 2991 /* Not on interrupt list, ignore it. */ 2992 return; 2993 2994 if (!uhci_active_intr_info(ii)) 2995 return; 2996 2997 #ifdef DIAGNOSTIC 2998 if (ii->stdend == NULL) { 2999 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 3000 #ifdef UHCI_DEBUG 3001 uhci_dump_ii(ii); 3002 #endif 3003 return; 3004 } 3005 #endif 3006 3007 /* Turn off the interrupt since it is active even if the TD is not. */ 3008 usb_syncmem(&ii->stdend->dma, 3009 ii->stdend->offs + offsetof(uhci_td_t, td_status), 3010 sizeof(ii->stdend->td.td_status), 3011 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3012 ii->stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3013 usb_syncmem(&ii->stdend->dma, 3014 ii->stdend->offs + offsetof(uhci_td_t, td_status), 3015 sizeof(ii->stdend->td.td_status), 3016 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3017 3018 uhci_del_intr_info(ii); /* remove from active list */ 3019 3020 offs = 0; 3021 for (i = 0; i < xfer->nframes; i++) { 3022 usb_syncmem(&xfer->dmabuf, offs, xfer->frlengths[i], 3023 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3024 offs += xfer->frlengths[i]; 3025 } 3026 } 3027 3028 void 3029 uhci_device_intr_done(usbd_xfer_handle xfer) 3030 { 3031 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3032 uhci_softc_t *sc = ii->sc; 3033 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3034 uhci_soft_qh_t *sqh; 3035 int i, npoll, isread; 3036 3037 DPRINTFN(5, ("uhci_device_intr_done: length=%d\n", xfer->actlen)); 3038 3039 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3040 3041 npoll = upipe->u.intr.npoll; 3042 for(i = 0; i < npoll; i++) { 3043 sqh = upipe->u.intr.qhs[i]; 3044 sqh->elink = NULL; 3045 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3046 usb_syncmem(&sqh->dma, 3047 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3048 sizeof(sqh->qh.qh_elink), 3049 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3050 } 3051 uhci_free_std_chain(sc, ii->stdstart, NULL); 3052 3053 isread = UE_GET_DIR(upipe->pipe.endpoint->edesc->bEndpointAddress) == UE_DIR_IN; 3054 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3055 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3056 3057 /* XXX Wasteful. */ 3058 if (xfer->pipe->repeat) { 3059 uhci_soft_td_t *data, *dataend; 3060 3061 DPRINTFN(5,("uhci_device_intr_done: requeing\n")); 3062 3063 /* This alloc cannot fail since we freed the chain above. */ 3064 uhci_alloc_std_chain(upipe, sc, xfer->length, 3065 upipe->u.intr.isread, xfer->flags, 3066 &xfer->dmabuf, &data, &dataend); 3067 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3068 usb_syncmem(&dataend->dma, 3069 dataend->offs + offsetof(uhci_td_t, td_status), 3070 sizeof(dataend->td.td_status), 3071 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3072 3073 #ifdef UHCI_DEBUG 3074 if (uhcidebug > 10) { 3075 DPRINTF(("uhci_device_intr_done: data(1)\n")); 3076 uhci_dump_tds(data); 3077 uhci_dump_qh(upipe->u.intr.qhs[0]); 3078 } 3079 #endif 3080 3081 ii->stdstart = data; 3082 ii->stdend = dataend; 3083 #ifdef DIAGNOSTIC 3084 if (!ii->isdone) { 3085 printf("uhci_device_intr_done: not done, ii=%p\n", ii); 3086 } 3087 ii->isdone = 0; 3088 #endif 3089 for (i = 0; i < npoll; i++) { 3090 sqh = upipe->u.intr.qhs[i]; 3091 sqh->elink = data; 3092 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3093 usb_syncmem(&sqh->dma, 3094 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3095 sizeof(sqh->qh.qh_elink), 3096 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3097 } 3098 xfer->status = USBD_IN_PROGRESS; 3099 /* The ii is already on the examined list, just leave it. */ 3100 } else { 3101 DPRINTFN(5,("uhci_device_intr_done: removing\n")); 3102 if (uhci_active_intr_info(ii)) 3103 uhci_del_intr_info(ii); 3104 } 3105 } 3106 3107 /* Deallocate request data structures */ 3108 void 3109 uhci_device_ctrl_done(usbd_xfer_handle xfer) 3110 { 3111 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3112 uhci_softc_t *sc = ii->sc; 3113 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3114 int len = UGETW(xfer->request.wLength); 3115 int isread = (xfer->request.bmRequestType & UT_READ); 3116 3117 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3118 3119 #ifdef DIAGNOSTIC 3120 if (!(xfer->rqflags & URQ_REQUEST)) 3121 panic("uhci_device_ctrl_done: not a request"); 3122 #endif 3123 3124 if (!uhci_active_intr_info(ii)) 3125 return; 3126 3127 uhci_del_intr_info(ii); /* remove from active list */ 3128 3129 if (upipe->pipe.device->speed == USB_SPEED_LOW) 3130 uhci_remove_ls_ctrl(sc, upipe->u.ctl.sqh); 3131 else 3132 uhci_remove_hs_ctrl(sc, upipe->u.ctl.sqh); 3133 3134 if (upipe->u.ctl.length != 0) 3135 uhci_free_std_chain(sc, ii->stdstart->link.std, ii->stdend); 3136 3137 if (len) { 3138 usb_syncmem(&xfer->dmabuf, 0, len, 3139 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3140 } 3141 usb_syncmem(&upipe->u.ctl.reqdma, 0, 3142 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3143 3144 DPRINTFN(5, ("uhci_device_ctrl_done: length=%d\n", xfer->actlen)); 3145 } 3146 3147 /* Deallocate request data structures */ 3148 void 3149 uhci_device_bulk_done(usbd_xfer_handle xfer) 3150 { 3151 uhci_intr_info_t *ii = &UXFER(xfer)->iinfo; 3152 uhci_softc_t *sc = ii->sc; 3153 struct uhci_pipe *upipe = (struct uhci_pipe *)xfer->pipe; 3154 3155 DPRINTFN(5,("uhci_device_bulk_done: xfer=%p ii=%p sc=%p upipe=%p\n", 3156 xfer, ii, sc, upipe)); 3157 3158 KASSERT(mutex_owned(&sc->sc_lock)); 3159 3160 if (!uhci_active_intr_info(ii)) 3161 return; 3162 3163 uhci_del_intr_info(ii); /* remove from active list */ 3164 3165 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 3166 3167 uhci_free_std_chain(sc, ii->stdstart, NULL); 3168 3169 DPRINTFN(5, ("uhci_device_bulk_done: length=%d\n", xfer->actlen)); 3170 } 3171 3172 /* Add interrupt QH, called with vflock. */ 3173 void 3174 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3175 { 3176 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3177 uhci_soft_qh_t *eqh; 3178 3179 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3180 3181 eqh = vf->eqh; 3182 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3183 sizeof(eqh->qh.qh_hlink), 3184 BUS_DMASYNC_POSTWRITE); 3185 sqh->hlink = eqh->hlink; 3186 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3187 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3188 sizeof(sqh->qh.qh_hlink), 3189 BUS_DMASYNC_PREWRITE); 3190 eqh->hlink = sqh; 3191 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3192 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3193 sizeof(eqh->qh.qh_hlink), 3194 BUS_DMASYNC_PREWRITE); 3195 vf->eqh = sqh; 3196 vf->bandwidth++; 3197 } 3198 3199 /* Remove interrupt QH. */ 3200 void 3201 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3202 { 3203 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3204 uhci_soft_qh_t *pqh; 3205 3206 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", sqh->pos, sqh)); 3207 3208 /* See comment in uhci_remove_ctrl() */ 3209 3210 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3211 sizeof(sqh->qh.qh_elink), 3212 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3213 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3214 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3215 usb_syncmem(&sqh->dma, 3216 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3217 sizeof(sqh->qh.qh_elink), 3218 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3219 delay(UHCI_QH_REMOVE_DELAY); 3220 } 3221 3222 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3223 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3224 sizeof(sqh->qh.qh_hlink), 3225 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3226 pqh->hlink = sqh->hlink; 3227 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3228 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3229 sizeof(pqh->qh.qh_hlink), 3230 BUS_DMASYNC_PREWRITE); 3231 delay(UHCI_QH_REMOVE_DELAY); 3232 if (vf->eqh == sqh) 3233 vf->eqh = pqh; 3234 vf->bandwidth--; 3235 } 3236 3237 usbd_status 3238 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3239 { 3240 uhci_soft_qh_t *sqh; 3241 int i, npoll; 3242 u_int bestbw, bw, bestoffs, offs; 3243 3244 DPRINTFN(2, ("uhci_device_setintr: pipe=%p\n", upipe)); 3245 if (ival == 0) { 3246 printf("uhci_device_setintr: 0 interval\n"); 3247 return (USBD_INVAL); 3248 } 3249 3250 if (ival > UHCI_VFRAMELIST_COUNT) 3251 ival = UHCI_VFRAMELIST_COUNT; 3252 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3253 DPRINTFN(2, ("uhci_device_setintr: ival=%d npoll=%d\n", ival, npoll)); 3254 3255 upipe->u.intr.npoll = npoll; 3256 upipe->u.intr.qhs = 3257 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3258 if (upipe->u.intr.qhs == NULL) 3259 return USBD_NOMEM; 3260 3261 /* 3262 * Figure out which offset in the schedule that has most 3263 * bandwidth left over. 3264 */ 3265 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3266 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3267 for (bw = i = 0; i < npoll; i++) 3268 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3269 if (bw < bestbw) { 3270 bestbw = bw; 3271 bestoffs = offs; 3272 } 3273 } 3274 DPRINTFN(1, ("uhci_device_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 3275 3276 mutex_enter(&sc->sc_lock); 3277 for(i = 0; i < npoll; i++) { 3278 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3279 sqh->elink = NULL; 3280 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3281 usb_syncmem(&sqh->dma, 3282 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3283 sizeof(sqh->qh.qh_elink), 3284 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3285 sqh->pos = MOD(i * ival + bestoffs); 3286 } 3287 #undef MOD 3288 3289 /* Enter QHs into the controller data structures. */ 3290 for(i = 0; i < npoll; i++) 3291 uhci_add_intr(sc, upipe->u.intr.qhs[i]); 3292 mutex_exit(&sc->sc_lock); 3293 3294 DPRINTFN(5, ("uhci_device_setintr: returns %p\n", upipe)); 3295 return (USBD_NORMAL_COMPLETION); 3296 } 3297 3298 /* Open a new pipe. */ 3299 usbd_status 3300 uhci_open(usbd_pipe_handle pipe) 3301 { 3302 uhci_softc_t *sc = pipe->device->bus->hci_private; 3303 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 3304 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 3305 usbd_status err = USBD_NOMEM; 3306 int ival; 3307 3308 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 3309 pipe, pipe->device->address, 3310 ed->bEndpointAddress, sc->sc_addr)); 3311 3312 if (sc->sc_dying) 3313 return USBD_IOERROR; 3314 3315 upipe->aborting = 0; 3316 /* toggle state needed for bulk endpoints */ 3317 upipe->nexttoggle = pipe->endpoint->datatoggle; 3318 3319 if (pipe->device->address == sc->sc_addr) { 3320 switch (ed->bEndpointAddress) { 3321 case USB_CONTROL_ENDPOINT: 3322 pipe->methods = &uhci_root_ctrl_methods; 3323 break; 3324 case UE_DIR_IN | UHCI_INTR_ENDPT: 3325 pipe->methods = &uhci_root_intr_methods; 3326 break; 3327 default: 3328 return (USBD_INVAL); 3329 } 3330 } else { 3331 switch (ed->bmAttributes & UE_XFERTYPE) { 3332 case UE_CONTROL: 3333 pipe->methods = &uhci_device_ctrl_methods; 3334 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 3335 if (upipe->u.ctl.sqh == NULL) 3336 goto bad; 3337 upipe->u.ctl.setup = uhci_alloc_std(sc); 3338 if (upipe->u.ctl.setup == NULL) { 3339 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3340 goto bad; 3341 } 3342 upipe->u.ctl.stat = uhci_alloc_std(sc); 3343 if (upipe->u.ctl.stat == NULL) { 3344 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3345 uhci_free_std(sc, upipe->u.ctl.setup); 3346 goto bad; 3347 } 3348 err = usb_allocmem(&sc->sc_bus, 3349 sizeof(usb_device_request_t), 3350 0, &upipe->u.ctl.reqdma); 3351 if (err) { 3352 uhci_free_sqh(sc, upipe->u.ctl.sqh); 3353 uhci_free_std(sc, upipe->u.ctl.setup); 3354 uhci_free_std(sc, upipe->u.ctl.stat); 3355 goto bad; 3356 } 3357 break; 3358 case UE_INTERRUPT: 3359 pipe->methods = &uhci_device_intr_methods; 3360 ival = pipe->interval; 3361 if (ival == USBD_DEFAULT_INTERVAL) 3362 ival = ed->bInterval; 3363 return (uhci_device_setintr(sc, upipe, ival)); 3364 case UE_ISOCHRONOUS: 3365 pipe->methods = &uhci_device_isoc_methods; 3366 return (uhci_setup_isoc(pipe)); 3367 case UE_BULK: 3368 pipe->methods = &uhci_device_bulk_methods; 3369 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 3370 if (upipe->u.bulk.sqh == NULL) 3371 goto bad; 3372 break; 3373 } 3374 } 3375 return (USBD_NORMAL_COMPLETION); 3376 3377 bad: 3378 return USBD_NOMEM; 3379 } 3380 3381 /* 3382 * Data structures and routines to emulate the root hub. 3383 */ 3384 usb_device_descriptor_t uhci_devd = { 3385 USB_DEVICE_DESCRIPTOR_SIZE, 3386 UDESC_DEVICE, /* type */ 3387 {0x00, 0x01}, /* USB version */ 3388 UDCLASS_HUB, /* class */ 3389 UDSUBCLASS_HUB, /* subclass */ 3390 UDPROTO_FSHUB, /* protocol */ 3391 64, /* max packet */ 3392 {0},{0},{0x00,0x01}, /* device id */ 3393 1,2,0, /* string indicies */ 3394 1 /* # of configurations */ 3395 }; 3396 3397 const usb_config_descriptor_t uhci_confd = { 3398 USB_CONFIG_DESCRIPTOR_SIZE, 3399 UDESC_CONFIG, 3400 {USB_CONFIG_DESCRIPTOR_SIZE + 3401 USB_INTERFACE_DESCRIPTOR_SIZE + 3402 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3403 1, 3404 1, 3405 0, 3406 UC_ATTR_MBO | UC_SELF_POWERED, 3407 0 /* max power */ 3408 }; 3409 3410 const usb_interface_descriptor_t uhci_ifcd = { 3411 USB_INTERFACE_DESCRIPTOR_SIZE, 3412 UDESC_INTERFACE, 3413 0, 3414 0, 3415 1, 3416 UICLASS_HUB, 3417 UISUBCLASS_HUB, 3418 UIPROTO_FSHUB, 3419 0 3420 }; 3421 3422 const usb_endpoint_descriptor_t uhci_endpd = { 3423 USB_ENDPOINT_DESCRIPTOR_SIZE, 3424 UDESC_ENDPOINT, 3425 UE_DIR_IN | UHCI_INTR_ENDPT, 3426 UE_INTERRUPT, 3427 {8}, 3428 255 3429 }; 3430 3431 const usb_hub_descriptor_t uhci_hubd_piix = { 3432 USB_HUB_DESCRIPTOR_SIZE, 3433 UDESC_HUB, 3434 2, 3435 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 3436 50, /* power on to power good */ 3437 0, 3438 { 0x00 }, /* both ports are removable */ 3439 { 0 }, 3440 }; 3441 3442 /* 3443 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3444 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3445 * should not be used by the USB subsystem. As we cannot issue a 3446 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3447 * will be enabled as part of the reset. 3448 * 3449 * On the VT83C572, the port cannot be successfully enabled until the 3450 * outstanding "port enable change" and "connection status change" 3451 * events have been reset. 3452 */ 3453 Static usbd_status 3454 uhci_portreset(uhci_softc_t *sc, int index) 3455 { 3456 int lim, port, x; 3457 3458 if (index == 1) 3459 port = UHCI_PORTSC1; 3460 else if (index == 2) 3461 port = UHCI_PORTSC2; 3462 else 3463 return (USBD_IOERROR); 3464 3465 x = URWMASK(UREAD2(sc, port)); 3466 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3467 3468 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3469 3470 DPRINTFN(3,("uhci port %d reset, status0 = 0x%04x\n", 3471 index, UREAD2(sc, port))); 3472 3473 x = URWMASK(UREAD2(sc, port)); 3474 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3475 3476 delay(100); 3477 3478 DPRINTFN(3,("uhci port %d reset, status1 = 0x%04x\n", 3479 index, UREAD2(sc, port))); 3480 3481 x = URWMASK(UREAD2(sc, port)); 3482 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3483 3484 for (lim = 10; --lim > 0;) { 3485 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3486 3487 x = UREAD2(sc, port); 3488 3489 DPRINTFN(3,("uhci port %d iteration %u, status = 0x%04x\n", 3490 index, lim, x)); 3491 3492 if (!(x & UHCI_PORTSC_CCS)) { 3493 /* 3494 * No device is connected (or was disconnected 3495 * during reset). Consider the port reset. 3496 * The delay must be long enough to ensure on 3497 * the initial iteration that the device 3498 * connection will have been registered. 50ms 3499 * appears to be sufficient, but 20ms is not. 3500 */ 3501 DPRINTFN(3,("uhci port %d loop %u, device detached\n", 3502 index, lim)); 3503 break; 3504 } 3505 3506 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3507 /* 3508 * Port enabled changed and/or connection 3509 * status changed were set. Reset either or 3510 * both raised flags (by writing a 1 to that 3511 * bit), and wait again for state to settle. 3512 */ 3513 UWRITE2(sc, port, URWMASK(x) | 3514 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3515 continue; 3516 } 3517 3518 if (x & UHCI_PORTSC_PE) 3519 /* Port is enabled */ 3520 break; 3521 3522 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3523 } 3524 3525 DPRINTFN(3,("uhci port %d reset, status2 = 0x%04x\n", 3526 index, UREAD2(sc, port))); 3527 3528 if (lim <= 0) { 3529 DPRINTFN(1,("uhci port %d reset timed out\n", index)); 3530 return (USBD_TIMEOUT); 3531 } 3532 3533 sc->sc_isreset = 1; 3534 return (USBD_NORMAL_COMPLETION); 3535 } 3536 3537 /* 3538 * Simulate a hardware hub by handling all the necessary requests. 3539 */ 3540 usbd_status 3541 uhci_root_ctrl_transfer(usbd_xfer_handle xfer) 3542 { 3543 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3544 usbd_status err; 3545 3546 /* Insert last in queue. */ 3547 mutex_enter(&sc->sc_lock); 3548 err = usb_insert_transfer(xfer); 3549 mutex_exit(&sc->sc_lock); 3550 if (err) 3551 return (err); 3552 3553 /* 3554 * Pipe isn't running (otherwise err would be USBD_INPROG), 3555 * so start it first. 3556 */ 3557 return (uhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3558 } 3559 3560 usbd_status 3561 uhci_root_ctrl_start(usbd_xfer_handle xfer) 3562 { 3563 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3564 usb_device_request_t *req; 3565 void *buf = NULL; 3566 int port, x; 3567 int len, value, index, status, change, l, totlen = 0; 3568 usb_port_status_t ps; 3569 usbd_status err; 3570 3571 if (sc->sc_dying) 3572 return (USBD_IOERROR); 3573 3574 #ifdef DIAGNOSTIC 3575 if (!(xfer->rqflags & URQ_REQUEST)) 3576 panic("uhci_root_ctrl_start: not a request"); 3577 #endif 3578 req = &xfer->request; 3579 3580 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 3581 req->bmRequestType, req->bRequest)); 3582 3583 len = UGETW(req->wLength); 3584 value = UGETW(req->wValue); 3585 index = UGETW(req->wIndex); 3586 3587 if (len != 0) 3588 buf = KERNADDR(&xfer->dmabuf, 0); 3589 3590 #define C(x,y) ((x) | ((y) << 8)) 3591 switch(C(req->bRequest, req->bmRequestType)) { 3592 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3593 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3594 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3595 /* 3596 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3597 * for the integrated root hub. 3598 */ 3599 break; 3600 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3601 if (len > 0) { 3602 *(uint8_t *)buf = sc->sc_conf; 3603 totlen = 1; 3604 } 3605 break; 3606 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3607 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 3608 if (len == 0) 3609 break; 3610 switch(value >> 8) { 3611 case UDESC_DEVICE: 3612 if ((value & 0xff) != 0) { 3613 err = USBD_IOERROR; 3614 goto ret; 3615 } 3616 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3617 USETW(uhci_devd.idVendor, sc->sc_id_vendor); 3618 memcpy(buf, &uhci_devd, l); 3619 break; 3620 case UDESC_CONFIG: 3621 if ((value & 0xff) != 0) { 3622 err = USBD_IOERROR; 3623 goto ret; 3624 } 3625 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3626 memcpy(buf, &uhci_confd, l); 3627 buf = (char *)buf + l; 3628 len -= l; 3629 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3630 totlen += l; 3631 memcpy(buf, &uhci_ifcd, l); 3632 buf = (char *)buf + l; 3633 len -= l; 3634 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3635 totlen += l; 3636 memcpy(buf, &uhci_endpd, l); 3637 break; 3638 case UDESC_STRING: 3639 #define sd ((usb_string_descriptor_t *)buf) 3640 switch (value & 0xff) { 3641 case 0: /* Language table */ 3642 totlen = usb_makelangtbl(sd, len); 3643 break; 3644 case 1: /* Vendor */ 3645 totlen = usb_makestrdesc(sd, len, 3646 sc->sc_vendor); 3647 break; 3648 case 2: /* Product */ 3649 totlen = usb_makestrdesc(sd, len, 3650 "UHCI root hub"); 3651 break; 3652 } 3653 #undef sd 3654 break; 3655 default: 3656 err = USBD_IOERROR; 3657 goto ret; 3658 } 3659 break; 3660 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3661 if (len > 0) { 3662 *(uint8_t *)buf = 0; 3663 totlen = 1; 3664 } 3665 break; 3666 case C(UR_GET_STATUS, UT_READ_DEVICE): 3667 if (len > 1) { 3668 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3669 totlen = 2; 3670 } 3671 break; 3672 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3673 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3674 if (len > 1) { 3675 USETW(((usb_status_t *)buf)->wStatus, 0); 3676 totlen = 2; 3677 } 3678 break; 3679 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3680 if (value >= USB_MAX_DEVICES) { 3681 err = USBD_IOERROR; 3682 goto ret; 3683 } 3684 sc->sc_addr = value; 3685 break; 3686 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3687 if (value != 0 && value != 1) { 3688 err = USBD_IOERROR; 3689 goto ret; 3690 } 3691 sc->sc_conf = value; 3692 break; 3693 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3694 break; 3695 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3696 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3697 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3698 err = USBD_IOERROR; 3699 goto ret; 3700 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3701 break; 3702 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3703 break; 3704 /* Hub requests */ 3705 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3706 break; 3707 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3708 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 3709 "port=%d feature=%d\n", 3710 index, value)); 3711 if (index == 1) 3712 port = UHCI_PORTSC1; 3713 else if (index == 2) 3714 port = UHCI_PORTSC2; 3715 else { 3716 err = USBD_IOERROR; 3717 goto ret; 3718 } 3719 switch(value) { 3720 case UHF_PORT_ENABLE: 3721 x = URWMASK(UREAD2(sc, port)); 3722 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3723 break; 3724 case UHF_PORT_SUSPEND: 3725 x = URWMASK(UREAD2(sc, port)); 3726 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3727 break; 3728 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3729 /* see USB2 spec ch. 7.1.7.7 */ 3730 usb_delay_ms(&sc->sc_bus, 20); 3731 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3732 /* 10ms resume delay must be provided by caller */ 3733 break; 3734 case UHF_PORT_RESET: 3735 x = URWMASK(UREAD2(sc, port)); 3736 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3737 break; 3738 case UHF_C_PORT_CONNECTION: 3739 x = URWMASK(UREAD2(sc, port)); 3740 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3741 break; 3742 case UHF_C_PORT_ENABLE: 3743 x = URWMASK(UREAD2(sc, port)); 3744 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3745 break; 3746 case UHF_C_PORT_OVER_CURRENT: 3747 x = URWMASK(UREAD2(sc, port)); 3748 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3749 break; 3750 case UHF_C_PORT_RESET: 3751 sc->sc_isreset = 0; 3752 err = USBD_NORMAL_COMPLETION; 3753 goto ret; 3754 case UHF_PORT_CONNECTION: 3755 case UHF_PORT_OVER_CURRENT: 3756 case UHF_PORT_POWER: 3757 case UHF_PORT_LOW_SPEED: 3758 case UHF_C_PORT_SUSPEND: 3759 default: 3760 err = USBD_IOERROR; 3761 goto ret; 3762 } 3763 break; 3764 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3765 if (index == 1) 3766 port = UHCI_PORTSC1; 3767 else if (index == 2) 3768 port = UHCI_PORTSC2; 3769 else { 3770 err = USBD_IOERROR; 3771 goto ret; 3772 } 3773 if (len > 0) { 3774 *(uint8_t *)buf = 3775 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3776 UHCI_PORTSC_LS_SHIFT; 3777 totlen = 1; 3778 } 3779 break; 3780 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3781 if (len == 0) 3782 break; 3783 if ((value & 0xff) != 0) { 3784 err = USBD_IOERROR; 3785 goto ret; 3786 } 3787 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 3788 totlen = l; 3789 memcpy(buf, &uhci_hubd_piix, l); 3790 break; 3791 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3792 if (len != 4) { 3793 err = USBD_IOERROR; 3794 goto ret; 3795 } 3796 memset(buf, 0, len); 3797 totlen = len; 3798 break; 3799 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3800 if (index == 1) 3801 port = UHCI_PORTSC1; 3802 else if (index == 2) 3803 port = UHCI_PORTSC2; 3804 else { 3805 err = USBD_IOERROR; 3806 goto ret; 3807 } 3808 if (len != 4) { 3809 err = USBD_IOERROR; 3810 goto ret; 3811 } 3812 x = UREAD2(sc, port); 3813 status = change = 0; 3814 if (x & UHCI_PORTSC_CCS) 3815 status |= UPS_CURRENT_CONNECT_STATUS; 3816 if (x & UHCI_PORTSC_CSC) 3817 change |= UPS_C_CONNECT_STATUS; 3818 if (x & UHCI_PORTSC_PE) 3819 status |= UPS_PORT_ENABLED; 3820 if (x & UHCI_PORTSC_POEDC) 3821 change |= UPS_C_PORT_ENABLED; 3822 if (x & UHCI_PORTSC_OCI) 3823 status |= UPS_OVERCURRENT_INDICATOR; 3824 if (x & UHCI_PORTSC_OCIC) 3825 change |= UPS_C_OVERCURRENT_INDICATOR; 3826 if (x & UHCI_PORTSC_SUSP) 3827 status |= UPS_SUSPEND; 3828 if (x & UHCI_PORTSC_LSDA) 3829 status |= UPS_LOW_SPEED; 3830 status |= UPS_PORT_POWER; 3831 if (sc->sc_isreset) 3832 change |= UPS_C_PORT_RESET; 3833 USETW(ps.wPortStatus, status); 3834 USETW(ps.wPortChange, change); 3835 l = min(len, sizeof ps); 3836 memcpy(buf, &ps, l); 3837 totlen = l; 3838 break; 3839 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3840 err = USBD_IOERROR; 3841 goto ret; 3842 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3843 break; 3844 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3845 if (index == 1) 3846 port = UHCI_PORTSC1; 3847 else if (index == 2) 3848 port = UHCI_PORTSC2; 3849 else { 3850 err = USBD_IOERROR; 3851 goto ret; 3852 } 3853 switch(value) { 3854 case UHF_PORT_ENABLE: 3855 x = URWMASK(UREAD2(sc, port)); 3856 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3857 break; 3858 case UHF_PORT_SUSPEND: 3859 x = URWMASK(UREAD2(sc, port)); 3860 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3861 break; 3862 case UHF_PORT_RESET: 3863 err = uhci_portreset(sc, index); 3864 goto ret; 3865 case UHF_PORT_POWER: 3866 /* Pretend we turned on power */ 3867 err = USBD_NORMAL_COMPLETION; 3868 goto ret; 3869 case UHF_C_PORT_CONNECTION: 3870 case UHF_C_PORT_ENABLE: 3871 case UHF_C_PORT_OVER_CURRENT: 3872 case UHF_PORT_CONNECTION: 3873 case UHF_PORT_OVER_CURRENT: 3874 case UHF_PORT_LOW_SPEED: 3875 case UHF_C_PORT_SUSPEND: 3876 case UHF_C_PORT_RESET: 3877 default: 3878 err = USBD_IOERROR; 3879 goto ret; 3880 } 3881 break; 3882 default: 3883 err = USBD_IOERROR; 3884 goto ret; 3885 } 3886 xfer->actlen = totlen; 3887 err = USBD_NORMAL_COMPLETION; 3888 ret: 3889 xfer->status = err; 3890 mutex_enter(&sc->sc_lock); 3891 usb_transfer_complete(xfer); 3892 mutex_exit(&sc->sc_lock); 3893 return (USBD_IN_PROGRESS); 3894 } 3895 3896 /* Abort a root control request. */ 3897 void 3898 uhci_root_ctrl_abort(usbd_xfer_handle xfer) 3899 { 3900 /* Nothing to do, all transfers are synchronous. */ 3901 } 3902 3903 /* Close the root pipe. */ 3904 void 3905 uhci_root_ctrl_close(usbd_pipe_handle pipe) 3906 { 3907 DPRINTF(("uhci_root_ctrl_close\n")); 3908 } 3909 3910 /* Abort a root interrupt request. */ 3911 void 3912 uhci_root_intr_abort(usbd_xfer_handle xfer) 3913 { 3914 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3915 3916 KASSERT(mutex_owned(&sc->sc_lock)); 3917 KASSERT(xfer->pipe->intrxfer == xfer); 3918 3919 callout_stop(&sc->sc_poll_handle); 3920 sc->sc_intr_xfer = NULL; 3921 3922 xfer->status = USBD_CANCELLED; 3923 #ifdef DIAGNOSTIC 3924 UXFER(xfer)->iinfo.isdone = 1; 3925 #endif 3926 usb_transfer_complete(xfer); 3927 } 3928 3929 usbd_status 3930 uhci_root_intr_transfer(usbd_xfer_handle xfer) 3931 { 3932 uhci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3933 usbd_status err; 3934 3935 /* Insert last in queue. */ 3936 mutex_enter(&sc->sc_lock); 3937 err = usb_insert_transfer(xfer); 3938 mutex_exit(&sc->sc_lock); 3939 if (err) 3940 return (err); 3941 3942 /* 3943 * Pipe isn't running (otherwise err would be USBD_INPROG), 3944 * start first 3945 */ 3946 return (uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3947 } 3948 3949 /* Start a transfer on the root interrupt pipe */ 3950 usbd_status 3951 uhci_root_intr_start(usbd_xfer_handle xfer) 3952 { 3953 usbd_pipe_handle pipe = xfer->pipe; 3954 uhci_softc_t *sc = pipe->device->bus->hci_private; 3955 unsigned int ival; 3956 3957 DPRINTFN(3, ("uhci_root_intr_start: xfer=%p len=%d flags=%d\n", 3958 xfer, xfer->length, xfer->flags)); 3959 3960 if (sc->sc_dying) 3961 return (USBD_IOERROR); 3962 3963 /* XXX temporary variable needed to avoid gcc3 warning */ 3964 ival = xfer->pipe->endpoint->edesc->bInterval; 3965 sc->sc_ival = mstohz(ival); 3966 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3967 sc->sc_intr_xfer = xfer; 3968 return (USBD_IN_PROGRESS); 3969 } 3970 3971 /* Close the root interrupt pipe. */ 3972 void 3973 uhci_root_intr_close(usbd_pipe_handle pipe) 3974 { 3975 uhci_softc_t *sc = pipe->device->bus->hci_private; 3976 3977 KASSERT(mutex_owned(&sc->sc_lock)); 3978 3979 callout_stop(&sc->sc_poll_handle); 3980 sc->sc_intr_xfer = NULL; 3981 DPRINTF(("uhci_root_intr_close\n")); 3982 } 3983
Indexes created Tue Sep 30 17:09:57 GMT 2025