uhci.c revision 1.264.4.50
1 /* $NetBSD: uhci.c,v 1.264.4.50 2015/11/08 14:56:21 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.50 2015/11/08 14:56:21 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Isochronous pipe */ 158 struct isoc { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } isoc; 162 }; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static usbd_status uhci_run(uhci_softc_t *, int, int); 169 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 170 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, 180 uhci_soft_td_t *, uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 182 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 183 uhci_soft_td_t **, uhci_soft_td_t **); 184 Static void uhci_poll_hub(void *); 185 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 186 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *); 187 Static void uhci_idone(struct uhci_xfer *); 188 189 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 190 191 Static void uhci_timeout(void *); 192 Static void uhci_timeout_task(void *); 193 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 194 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 195 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 197 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 198 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_add_loop(uhci_softc_t *); 200 Static void uhci_rem_loop(uhci_softc_t *); 201 202 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 203 Static void uhci_device_isoc_enter(struct usbd_xfer *); 204 205 Static struct usbd_xfer * 206 uhci_allocx(struct usbd_bus *, unsigned int); 207 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 208 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 209 Static int uhci_roothub_ctrl(struct usbd_bus *, 210 usb_device_request_t *, void *, int); 211 212 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 213 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 214 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 215 Static void uhci_device_ctrl_close(struct usbd_pipe *); 216 Static void uhci_device_ctrl_done(struct usbd_xfer *); 217 218 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 220 Static void uhci_device_intr_abort(struct usbd_xfer *); 221 Static void uhci_device_intr_close(struct usbd_pipe *); 222 Static void uhci_device_intr_done(struct usbd_xfer *); 223 224 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 225 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 226 Static void uhci_device_bulk_abort(struct usbd_xfer *); 227 Static void uhci_device_bulk_close(struct usbd_pipe *); 228 Static void uhci_device_bulk_done(struct usbd_xfer *); 229 230 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 231 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 232 Static void uhci_device_isoc_abort(struct usbd_xfer *); 233 Static void uhci_device_isoc_close(struct usbd_pipe *); 234 Static void uhci_device_isoc_done(struct usbd_xfer *); 235 236 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 238 Static void uhci_root_intr_abort(struct usbd_xfer *); 239 Static void uhci_root_intr_close(struct usbd_pipe *); 240 Static void uhci_root_intr_done(struct usbd_xfer *); 241 242 Static usbd_status uhci_open(struct usbd_pipe *); 243 Static void uhci_poll(struct usbd_bus *); 244 Static void uhci_softintr(void *); 245 246 Static usbd_status uhci_device_request(struct usbd_xfer *); 247 248 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 250 Static usbd_status uhci_device_setintr(uhci_softc_t *, 251 struct uhci_pipe *, int); 252 253 Static void uhci_device_clear_toggle(struct usbd_pipe *); 254 Static void uhci_noop(struct usbd_pipe *); 255 256 static inline uhci_soft_qh_t * 257 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 258 259 #ifdef UHCI_DEBUG 260 Static void uhci_dump_all(uhci_softc_t *); 261 Static void uhci_dumpregs(uhci_softc_t *); 262 Static void uhci_dump_qhs(uhci_soft_qh_t *); 263 Static void uhci_dump_qh(uhci_soft_qh_t *); 264 Static void uhci_dump_tds(uhci_soft_td_t *); 265 Static void uhci_dump_td(uhci_soft_td_t *); 266 Static void uhci_dump_ii(struct uhci_xfer *); 267 void uhci_dump(void); 268 #endif 269 270 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 271 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 272 #define UWRITE1(sc, r, x) \ 273 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 274 } while (/*CONSTCOND*/0) 275 #define UWRITE2(sc, r, x) \ 276 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 277 } while (/*CONSTCOND*/0) 278 #define UWRITE4(sc, r, x) \ 279 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 280 } while (/*CONSTCOND*/0) 281 282 static __inline uint8_t 283 UREAD1(uhci_softc_t *sc, bus_size_t r) 284 { 285 286 UBARR(sc); 287 return bus_space_read_1(sc->iot, sc->ioh, r); 288 } 289 290 static __inline uint16_t 291 UREAD2(uhci_softc_t *sc, bus_size_t r) 292 { 293 294 UBARR(sc); 295 return bus_space_read_2(sc->iot, sc->ioh, r); 296 } 297 298 #ifdef UHCI_DEBUG 299 static __inline uint32_t 300 UREAD4(uhci_softc_t *sc, bus_size_t r) 301 { 302 303 UBARR(sc); 304 return bus_space_read_4(sc->iot, sc->ioh, r); 305 } 306 #endif 307 308 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 309 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 310 311 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 312 313 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 314 315 const struct usbd_bus_methods uhci_bus_methods = { 316 .ubm_open = uhci_open, 317 .ubm_softint = uhci_softintr, 318 .ubm_dopoll = uhci_poll, 319 .ubm_allocx = uhci_allocx, 320 .ubm_freex = uhci_freex, 321 .ubm_getlock = uhci_get_lock, 322 .ubm_rhctrl = uhci_roothub_ctrl, 323 }; 324 325 const struct usbd_pipe_methods uhci_root_intr_methods = { 326 .upm_transfer = uhci_root_intr_transfer, 327 .upm_start = uhci_root_intr_start, 328 .upm_abort = uhci_root_intr_abort, 329 .upm_close = uhci_root_intr_close, 330 .upm_cleartoggle = uhci_noop, 331 .upm_done = uhci_root_intr_done, 332 }; 333 334 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 335 .upm_transfer = uhci_device_ctrl_transfer, 336 .upm_start = uhci_device_ctrl_start, 337 .upm_abort = uhci_device_ctrl_abort, 338 .upm_close = uhci_device_ctrl_close, 339 .upm_cleartoggle = uhci_noop, 340 .upm_done = uhci_device_ctrl_done, 341 }; 342 343 const struct usbd_pipe_methods uhci_device_intr_methods = { 344 .upm_transfer = uhci_device_intr_transfer, 345 .upm_start = uhci_device_intr_start, 346 .upm_abort = uhci_device_intr_abort, 347 .upm_close = uhci_device_intr_close, 348 .upm_cleartoggle = uhci_device_clear_toggle, 349 .upm_done = uhci_device_intr_done, 350 }; 351 352 const struct usbd_pipe_methods uhci_device_bulk_methods = { 353 .upm_transfer = uhci_device_bulk_transfer, 354 .upm_start = uhci_device_bulk_start, 355 .upm_abort = uhci_device_bulk_abort, 356 .upm_close = uhci_device_bulk_close, 357 .upm_cleartoggle = uhci_device_clear_toggle, 358 .upm_done = uhci_device_bulk_done, 359 }; 360 361 const struct usbd_pipe_methods uhci_device_isoc_methods = { 362 .upm_transfer = uhci_device_isoc_transfer, 363 .upm_start = uhci_device_isoc_start, 364 .upm_abort = uhci_device_isoc_abort, 365 .upm_close = uhci_device_isoc_close, 366 .upm_cleartoggle = uhci_noop, 367 .upm_done = uhci_device_isoc_done, 368 }; 369 370 #define uhci_add_intr_info(sc, ux) \ 371 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), ux_list) 372 #define uhci_del_intr_info(sc, ux) \ 373 do { \ 374 TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), ux_list); \ 375 (ux)->ux_list.tqe_prev = NULL; \ 376 } while (0) 377 #define uhci_active_intr_info(ux) ((ux)->ux_list.tqe_prev != NULL) 378 379 static inline uhci_soft_qh_t * 380 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 381 { 382 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 383 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 384 385 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 386 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 387 usb_syncmem(&pqh->dma, 388 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 389 sizeof(pqh->qh.qh_hlink), 390 BUS_DMASYNC_POSTWRITE); 391 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 392 printf("uhci_find_prev_qh: QH not found\n"); 393 return NULL; 394 } 395 #endif 396 } 397 return pqh; 398 } 399 400 void 401 uhci_globalreset(uhci_softc_t *sc) 402 { 403 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 404 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 405 UHCICMD(sc, 0); /* do nothing */ 406 } 407 408 int 409 uhci_init(uhci_softc_t *sc) 410 { 411 usbd_status err; 412 int i, j; 413 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 414 uhci_soft_td_t *std; 415 416 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 417 418 #ifdef UHCI_DEBUG 419 thesc = sc; 420 421 if (uhcidebug >= 2) 422 uhci_dumpregs(sc); 423 #endif 424 425 sc->sc_suspend = PWR_RESUME; 426 427 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 428 uhci_globalreset(sc); /* reset the controller */ 429 uhci_reset(sc); 430 431 /* Allocate and initialize real frame array. */ 432 err = usb_allocmem(&sc->sc_bus, 433 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 434 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 435 if (err) 436 return err; 437 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 438 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 439 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 440 441 /* 442 * Allocate a TD, inactive, that hangs from the last QH. 443 * This is to avoid a bug in the PIIX that makes it run berserk 444 * otherwise. 445 */ 446 std = uhci_alloc_std(sc); 447 if (std == NULL) 448 return ENOMEM; 449 std->link.std = NULL; 450 std->td.td_link = htole32(UHCI_PTR_T); 451 std->td.td_status = htole32(0); /* inactive */ 452 std->td.td_token = htole32(0); 453 std->td.td_buffer = htole32(0); 454 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 456 457 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 458 lsqh = uhci_alloc_sqh(sc); 459 if (lsqh == NULL) 460 return ENOMEM; 461 lsqh->hlink = NULL; 462 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 463 lsqh->elink = std; 464 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 465 sc->sc_last_qh = lsqh; 466 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 468 469 /* Allocate the dummy QH where bulk traffic will be queued. */ 470 bsqh = uhci_alloc_sqh(sc); 471 if (bsqh == NULL) 472 return ENOMEM; 473 bsqh->hlink = lsqh; 474 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 475 bsqh->elink = NULL; 476 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 477 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 478 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 480 481 /* Allocate dummy QH where high speed control traffic will be queued. */ 482 chsqh = uhci_alloc_sqh(sc); 483 if (chsqh == NULL) 484 return ENOMEM; 485 chsqh->hlink = bsqh; 486 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 487 chsqh->elink = NULL; 488 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 489 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 490 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 492 493 /* Allocate dummy QH where control traffic will be queued. */ 494 clsqh = uhci_alloc_sqh(sc); 495 if (clsqh == NULL) 496 return ENOMEM; 497 clsqh->hlink = chsqh; 498 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 499 clsqh->elink = NULL; 500 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 501 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 502 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 504 505 /* 506 * Make all (virtual) frame list pointers point to the interrupt 507 * queue heads and the interrupt queue heads at the control 508 * queue head and point the physical frame list to the virtual. 509 */ 510 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 511 std = uhci_alloc_std(sc); 512 sqh = uhci_alloc_sqh(sc); 513 if (std == NULL || sqh == NULL) 514 return USBD_NOMEM; 515 std->link.sqh = sqh; 516 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 517 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 518 std->td.td_token = htole32(0); 519 std->td.td_buffer = htole32(0); 520 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 521 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 522 sqh->hlink = clsqh; 523 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 524 sqh->elink = NULL; 525 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 526 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 528 sc->sc_vframes[i].htd = std; 529 sc->sc_vframes[i].etd = std; 530 sc->sc_vframes[i].hqh = sqh; 531 sc->sc_vframes[i].eqh = sqh; 532 for (j = i; 533 j < UHCI_FRAMELIST_COUNT; 534 j += UHCI_VFRAMELIST_COUNT) 535 sc->sc_pframes[j] = htole32(std->physaddr); 536 } 537 usb_syncmem(&sc->sc_dma, 0, 538 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 539 BUS_DMASYNC_PREWRITE); 540 541 542 TAILQ_INIT(&sc->sc_intrhead); 543 544 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 545 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 546 547 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 548 549 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 550 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 551 cv_init(&sc->sc_softwake_cv, "uhciab"); 552 553 /* Set up the bus struct. */ 554 sc->sc_bus.ub_methods = &uhci_bus_methods; 555 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 556 sc->sc_bus.ub_usedma = true; 557 558 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 559 560 DPRINTF("Enabling...", 0, 0, 0, 0); 561 562 err = uhci_run(sc, 1, 0); /* and here we go... */ 563 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 564 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 565 return err; 566 } 567 568 int 569 uhci_activate(device_t self, enum devact act) 570 { 571 struct uhci_softc *sc = device_private(self); 572 573 switch (act) { 574 case DVACT_DEACTIVATE: 575 sc->sc_dying = 1; 576 return 0; 577 default: 578 return EOPNOTSUPP; 579 } 580 } 581 582 void 583 uhci_childdet(device_t self, device_t child) 584 { 585 struct uhci_softc *sc = device_private(self); 586 587 KASSERT(sc->sc_child == child); 588 sc->sc_child = NULL; 589 } 590 591 int 592 uhci_detach(struct uhci_softc *sc, int flags) 593 { 594 int rv = 0; 595 596 if (sc->sc_child != NULL) 597 rv = config_detach(sc->sc_child, flags); 598 599 if (rv != 0) 600 return rv; 601 602 callout_halt(&sc->sc_poll_handle, NULL); 603 callout_destroy(&sc->sc_poll_handle); 604 605 cv_destroy(&sc->sc_softwake_cv); 606 607 mutex_destroy(&sc->sc_lock); 608 mutex_destroy(&sc->sc_intr_lock); 609 610 pool_cache_destroy(sc->sc_xferpool); 611 612 /* XXX free other data structures XXX */ 613 614 return rv; 615 } 616 617 struct usbd_xfer * 618 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 619 { 620 struct uhci_softc *sc = UHCI_BUS2SC(bus); 621 struct usbd_xfer *xfer; 622 623 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 624 if (xfer != NULL) { 625 memset(xfer, 0, sizeof(struct uhci_xfer)); 626 627 #ifdef DIAGNOSTIC 628 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 629 uxfer->ux_isdone = true; 630 xfer->ux_state = XFER_BUSY; 631 #endif 632 } 633 return xfer; 634 } 635 636 void 637 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 638 { 639 struct uhci_softc *sc = UHCI_BUS2SC(bus); 640 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 641 642 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 643 xfer->ux_state); 644 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 645 #ifdef DIAGNOSTIC 646 xfer->ux_state = XFER_FREE; 647 #endif 648 pool_cache_put(sc->sc_xferpool, xfer); 649 } 650 651 Static void 652 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 653 { 654 struct uhci_softc *sc = UHCI_BUS2SC(bus); 655 656 *lock = &sc->sc_lock; 657 } 658 659 660 /* 661 * Handle suspend/resume. 662 * 663 * We need to switch to polling mode here, because this routine is 664 * called from an interrupt context. This is all right since we 665 * are almost suspended anyway. 666 */ 667 bool 668 uhci_resume(device_t dv, const pmf_qual_t *qual) 669 { 670 uhci_softc_t *sc = device_private(dv); 671 int cmd; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 cmd = UREAD2(sc, UHCI_CMD); 676 sc->sc_bus.ub_usepolling++; 677 UWRITE2(sc, UHCI_INTR, 0); 678 uhci_globalreset(sc); 679 uhci_reset(sc); 680 if (cmd & UHCI_CMD_RS) 681 uhci_run(sc, 0, 1); 682 683 /* restore saved state */ 684 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 685 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 686 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 687 688 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 689 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 690 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 691 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 692 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 693 UHCICMD(sc, UHCI_CMD_MAXP); 694 uhci_run(sc, 1, 1); /* and start traffic again */ 695 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 696 sc->sc_bus.ub_usepolling--; 697 if (sc->sc_intr_xfer != NULL) 698 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 699 sc->sc_intr_xfer); 700 #ifdef UHCI_DEBUG 701 if (uhcidebug >= 2) 702 uhci_dumpregs(sc); 703 #endif 704 705 sc->sc_suspend = PWR_RESUME; 706 mutex_spin_exit(&sc->sc_intr_lock); 707 708 return true; 709 } 710 711 bool 712 uhci_suspend(device_t dv, const pmf_qual_t *qual) 713 { 714 uhci_softc_t *sc = device_private(dv); 715 int cmd; 716 717 mutex_spin_enter(&sc->sc_intr_lock); 718 719 cmd = UREAD2(sc, UHCI_CMD); 720 721 #ifdef UHCI_DEBUG 722 if (uhcidebug >= 2) 723 uhci_dumpregs(sc); 724 #endif 725 if (sc->sc_intr_xfer != NULL) 726 callout_stop(&sc->sc_poll_handle); 727 sc->sc_suspend = PWR_SUSPEND; 728 sc->sc_bus.ub_usepolling++; 729 730 uhci_run(sc, 0, 1); /* stop the controller */ 731 cmd &= ~UHCI_CMD_RS; 732 733 /* save some state if BIOS doesn't */ 734 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 735 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 736 737 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 738 739 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 740 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 741 sc->sc_bus.ub_usepolling--; 742 743 mutex_spin_exit(&sc->sc_intr_lock); 744 745 return true; 746 } 747 748 #ifdef UHCI_DEBUG 749 Static void 750 uhci_dumpregs(uhci_softc_t *sc) 751 { 752 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 753 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 754 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 755 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 756 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 757 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 758 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 759 } 760 761 void 762 uhci_dump_td(uhci_soft_td_t *p) 763 { 764 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 765 766 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 768 769 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 770 DPRINTF(" link=0x%08x status=0x%08x " 771 "token=0x%08x buffer=0x%08x", 772 le32toh(p->td.td_link), 773 le32toh(p->td.td_status), 774 le32toh(p->td.td_token), 775 le32toh(p->td.td_buffer)); 776 777 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 778 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 779 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 780 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 781 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 782 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 783 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 784 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 785 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 786 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 787 DPRINTF("ios =%d ls =%d spd =%d", 788 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 789 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 790 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 791 DPRINTF("errcnt =%d actlen =%d pid=%02x", 792 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 793 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 794 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 795 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 796 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 797 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 798 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 799 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 800 } 801 802 void 803 uhci_dump_qh(uhci_soft_qh_t *sqh) 804 { 805 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 806 807 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 808 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 809 810 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 811 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 812 le32toh(sqh->qh.qh_elink)); 813 814 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 815 } 816 817 818 #if 1 819 void 820 uhci_dump(void) 821 { 822 uhci_dump_all(thesc); 823 } 824 #endif 825 826 void 827 uhci_dump_all(uhci_softc_t *sc) 828 { 829 uhci_dumpregs(sc); 830 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 831 uhci_dump_qhs(sc->sc_lctl_start); 832 } 833 834 835 void 836 uhci_dump_qhs(uhci_soft_qh_t *sqh) 837 { 838 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 839 840 uhci_dump_qh(sqh); 841 842 /* 843 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 844 * Traverses sideways first, then down. 845 * 846 * QH1 847 * QH2 848 * No QH 849 * TD2.1 850 * TD2.2 851 * TD1.1 852 * etc. 853 * 854 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 855 */ 856 857 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 858 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 859 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 860 uhci_dump_qhs(sqh->hlink); 861 else 862 DPRINTF("No QH", 0, 0, 0, 0); 863 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 864 865 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 866 uhci_dump_tds(sqh->elink); 867 else 868 DPRINTF("No QH", 0, 0, 0, 0); 869 } 870 871 void 872 uhci_dump_tds(uhci_soft_td_t *std) 873 { 874 uhci_soft_td_t *td; 875 int stop; 876 877 for (td = std; td != NULL; td = td->link.std) { 878 uhci_dump_td(td); 879 880 /* 881 * Check whether the link pointer in this TD marks 882 * the link pointer as end of queue. This avoids 883 * printing the free list in case the queue/TD has 884 * already been moved there (seatbelt). 885 */ 886 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 887 sizeof(td->td.td_link), 888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 889 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 890 le32toh(td->td.td_link) == 0); 891 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 892 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 893 if (stop) 894 break; 895 } 896 } 897 898 Static void 899 uhci_dump_ii(struct uhci_xfer *ux) 900 { 901 struct usbd_pipe *pipe; 902 usb_endpoint_descriptor_t *ed; 903 struct usbd_device *dev; 904 905 if (ux == NULL) { 906 printf("ux NULL\n"); 907 return; 908 } 909 pipe = ux->ux_xfer.ux_pipe; 910 if (pipe == NULL) { 911 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 912 return; 913 } 914 if (pipe->up_endpoint == NULL) { 915 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 916 ux, ux->ux_isdone, pipe); 917 return; 918 } 919 if (pipe->up_dev == NULL) { 920 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 921 ux, ux->ux_isdone, pipe); 922 return; 923 } 924 ed = pipe->up_endpoint->ue_edesc; 925 dev = pipe->up_dev; 926 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 927 ux, ux->ux_isdone, dev, 928 UGETW(dev->ud_ddesc.idVendor), 929 UGETW(dev->ud_ddesc.idProduct), 930 dev->ud_addr, pipe, 931 ed->bEndpointAddress, ed->bmAttributes); 932 } 933 934 void uhci_dump_iis(struct uhci_softc *sc); 935 void 936 uhci_dump_iis(struct uhci_softc *sc) 937 { 938 struct uhci_xfer *ux; 939 940 printf("interrupt list:\n"); 941 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = TAILQ_NEXT(ux, ux_list)) 942 uhci_dump_ii(ux); 943 } 944 945 void iidump(void); 946 void iidump(void) { uhci_dump_iis(thesc); } 947 948 #endif 949 950 /* 951 * This routine is executed periodically and simulates interrupts 952 * from the root controller interrupt pipe for port status change. 953 */ 954 void 955 uhci_poll_hub(void *addr) 956 { 957 struct usbd_xfer *xfer = addr; 958 struct usbd_pipe *pipe = xfer->ux_pipe; 959 uhci_softc_t *sc; 960 u_char *p; 961 962 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 963 964 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 965 return; /* device has detached */ 966 sc = UHCI_PIPE2SC(pipe); 967 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 968 969 p = xfer->ux_buf; 970 p[0] = 0; 971 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 972 p[0] |= 1<<1; 973 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 974 p[0] |= 1<<2; 975 if (p[0] == 0) 976 /* No change, try again in a while */ 977 return; 978 979 xfer->ux_actlen = 1; 980 xfer->ux_status = USBD_NORMAL_COMPLETION; 981 mutex_enter(&sc->sc_lock); 982 usb_transfer_complete(xfer); 983 mutex_exit(&sc->sc_lock); 984 } 985 986 void 987 uhci_root_intr_done(struct usbd_xfer *xfer) 988 { 989 } 990 991 /* 992 * Let the last QH loop back to the high speed control transfer QH. 993 * This is what intel calls "bandwidth reclamation" and improves 994 * USB performance a lot for some devices. 995 * If we are already looping, just count it. 996 */ 997 void 998 uhci_add_loop(uhci_softc_t *sc) 999 { 1000 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1001 1002 #ifdef UHCI_DEBUG 1003 if (uhcinoloop) 1004 return; 1005 #endif 1006 if (++sc->sc_loops == 1) { 1007 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1008 /* Note, we don't loop back the soft pointer. */ 1009 sc->sc_last_qh->qh.qh_hlink = 1010 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1011 usb_syncmem(&sc->sc_last_qh->dma, 1012 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1013 sizeof(sc->sc_last_qh->qh.qh_hlink), 1014 BUS_DMASYNC_PREWRITE); 1015 } 1016 } 1017 1018 void 1019 uhci_rem_loop(uhci_softc_t *sc) 1020 { 1021 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1022 1023 #ifdef UHCI_DEBUG 1024 if (uhcinoloop) 1025 return; 1026 #endif 1027 if (--sc->sc_loops == 0) { 1028 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1029 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1030 usb_syncmem(&sc->sc_last_qh->dma, 1031 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1032 sizeof(sc->sc_last_qh->qh.qh_hlink), 1033 BUS_DMASYNC_PREWRITE); 1034 } 1035 } 1036 1037 /* Add high speed control QH, called with lock held. */ 1038 void 1039 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1040 { 1041 uhci_soft_qh_t *eqh; 1042 1043 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1044 1045 KASSERT(mutex_owned(&sc->sc_lock)); 1046 1047 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1048 eqh = sc->sc_hctl_end; 1049 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1050 sizeof(eqh->qh.qh_hlink), 1051 BUS_DMASYNC_POSTWRITE); 1052 sqh->hlink = eqh->hlink; 1053 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1054 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1055 BUS_DMASYNC_PREWRITE); 1056 eqh->hlink = sqh; 1057 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1058 sc->sc_hctl_end = sqh; 1059 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1060 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1061 #ifdef UHCI_CTL_LOOP 1062 uhci_add_loop(sc); 1063 #endif 1064 } 1065 1066 /* Remove high speed control QH, called with lock held. */ 1067 void 1068 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1069 { 1070 uhci_soft_qh_t *pqh; 1071 uint32_t elink; 1072 1073 KASSERT(mutex_owned(&sc->sc_lock)); 1074 1075 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1076 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1077 #ifdef UHCI_CTL_LOOP 1078 uhci_rem_loop(sc); 1079 #endif 1080 /* 1081 * The T bit should be set in the elink of the QH so that the HC 1082 * doesn't follow the pointer. This condition may fail if the 1083 * the transferred packet was short so that the QH still points 1084 * at the last used TD. 1085 * In this case we set the T bit and wait a little for the HC 1086 * to stop looking at the TD. 1087 * Note that if the TD chain is large enough, the controller 1088 * may still be looking at the chain at the end of this function. 1089 * uhci_free_std_chain() will make sure the controller stops 1090 * looking at it quickly, but until then we should not change 1091 * sqh->hlink. 1092 */ 1093 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1094 sizeof(sqh->qh.qh_elink), 1095 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1096 elink = le32toh(sqh->qh.qh_elink); 1097 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1098 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1099 if (!(elink & UHCI_PTR_T)) { 1100 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1101 usb_syncmem(&sqh->dma, 1102 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1103 sizeof(sqh->qh.qh_elink), 1104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1105 delay(UHCI_QH_REMOVE_DELAY); 1106 } 1107 1108 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1109 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1110 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1111 pqh->hlink = sqh->hlink; 1112 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1113 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1114 sizeof(pqh->qh.qh_hlink), 1115 BUS_DMASYNC_PREWRITE); 1116 delay(UHCI_QH_REMOVE_DELAY); 1117 if (sc->sc_hctl_end == sqh) 1118 sc->sc_hctl_end = pqh; 1119 } 1120 1121 /* Add low speed control QH, called with lock held. */ 1122 void 1123 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1124 { 1125 uhci_soft_qh_t *eqh; 1126 1127 KASSERT(mutex_owned(&sc->sc_lock)); 1128 1129 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1130 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1131 1132 eqh = sc->sc_lctl_end; 1133 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1134 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1135 sqh->hlink = eqh->hlink; 1136 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1137 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1138 BUS_DMASYNC_PREWRITE); 1139 eqh->hlink = sqh; 1140 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1141 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1142 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1143 sc->sc_lctl_end = sqh; 1144 } 1145 1146 /* Remove low speed control QH, called with lock held. */ 1147 void 1148 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1149 { 1150 uhci_soft_qh_t *pqh; 1151 uint32_t elink; 1152 1153 KASSERT(mutex_owned(&sc->sc_lock)); 1154 1155 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1156 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1157 1158 /* See comment in uhci_remove_hs_ctrl() */ 1159 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1160 sizeof(sqh->qh.qh_elink), 1161 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1162 elink = le32toh(sqh->qh.qh_elink); 1163 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1164 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1165 if (!(elink & UHCI_PTR_T)) { 1166 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1167 usb_syncmem(&sqh->dma, 1168 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1169 sizeof(sqh->qh.qh_elink), 1170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1171 delay(UHCI_QH_REMOVE_DELAY); 1172 } 1173 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1175 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1176 pqh->hlink = sqh->hlink; 1177 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1178 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1179 sizeof(pqh->qh.qh_hlink), 1180 BUS_DMASYNC_PREWRITE); 1181 delay(UHCI_QH_REMOVE_DELAY); 1182 if (sc->sc_lctl_end == sqh) 1183 sc->sc_lctl_end = pqh; 1184 } 1185 1186 /* Add bulk QH, called with lock held. */ 1187 void 1188 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1189 { 1190 uhci_soft_qh_t *eqh; 1191 1192 KASSERT(mutex_owned(&sc->sc_lock)); 1193 1194 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1195 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1196 1197 eqh = sc->sc_bulk_end; 1198 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1199 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1200 sqh->hlink = eqh->hlink; 1201 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1202 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1203 BUS_DMASYNC_PREWRITE); 1204 eqh->hlink = sqh; 1205 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1206 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1207 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1208 sc->sc_bulk_end = sqh; 1209 uhci_add_loop(sc); 1210 } 1211 1212 /* Remove bulk QH, called with lock held. */ 1213 void 1214 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1215 { 1216 uhci_soft_qh_t *pqh; 1217 1218 KASSERT(mutex_owned(&sc->sc_lock)); 1219 1220 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1221 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1222 1223 uhci_rem_loop(sc); 1224 /* See comment in uhci_remove_hs_ctrl() */ 1225 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1226 sizeof(sqh->qh.qh_elink), 1227 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1228 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1229 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1230 usb_syncmem(&sqh->dma, 1231 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1232 sizeof(sqh->qh.qh_elink), 1233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1234 delay(UHCI_QH_REMOVE_DELAY); 1235 } 1236 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1237 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1238 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1239 pqh->hlink = sqh->hlink; 1240 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1241 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1242 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1243 delay(UHCI_QH_REMOVE_DELAY); 1244 if (sc->sc_bulk_end == sqh) 1245 sc->sc_bulk_end = pqh; 1246 } 1247 1248 Static int uhci_intr1(uhci_softc_t *); 1249 1250 int 1251 uhci_intr(void *arg) 1252 { 1253 uhci_softc_t *sc = arg; 1254 int ret = 0; 1255 1256 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 1260 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1261 goto done; 1262 1263 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1264 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1265 goto done; 1266 } 1267 1268 ret = uhci_intr1(sc); 1269 1270 done: 1271 mutex_spin_exit(&sc->sc_intr_lock); 1272 return ret; 1273 } 1274 1275 int 1276 uhci_intr1(uhci_softc_t *sc) 1277 { 1278 int status; 1279 int ack; 1280 1281 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1282 1283 #ifdef UHCI_DEBUG 1284 if (uhcidebug >= 15) { 1285 DPRINTF("sc %p", sc, 0, 0, 0); 1286 uhci_dumpregs(sc); 1287 } 1288 #endif 1289 1290 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1291 1292 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1293 if (status == 0) /* The interrupt was not for us. */ 1294 return 0; 1295 1296 if (sc->sc_suspend != PWR_RESUME) { 1297 #ifdef DIAGNOSTIC 1298 printf("%s: interrupt while not operating ignored\n", 1299 device_xname(sc->sc_dev)); 1300 #endif 1301 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1302 return 0; 1303 } 1304 1305 ack = 0; 1306 if (status & UHCI_STS_USBINT) 1307 ack |= UHCI_STS_USBINT; 1308 if (status & UHCI_STS_USBEI) 1309 ack |= UHCI_STS_USBEI; 1310 if (status & UHCI_STS_RD) { 1311 ack |= UHCI_STS_RD; 1312 #ifdef UHCI_DEBUG 1313 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1314 #endif 1315 } 1316 if (status & UHCI_STS_HSE) { 1317 ack |= UHCI_STS_HSE; 1318 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1319 } 1320 if (status & UHCI_STS_HCPE) { 1321 ack |= UHCI_STS_HCPE; 1322 printf("%s: host controller process error\n", 1323 device_xname(sc->sc_dev)); 1324 } 1325 1326 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1327 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1328 /* no acknowledge needed */ 1329 if (!sc->sc_dying) { 1330 printf("%s: host controller halted\n", 1331 device_xname(sc->sc_dev)); 1332 #ifdef UHCI_DEBUG 1333 uhci_dump_all(sc); 1334 #endif 1335 } 1336 sc->sc_dying = 1; 1337 } 1338 1339 if (!ack) 1340 return 0; /* nothing to acknowledge */ 1341 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1342 1343 usb_schedsoftintr(&sc->sc_bus); 1344 1345 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1346 1347 return 1; 1348 } 1349 1350 void 1351 uhci_softintr(void *v) 1352 { 1353 struct usbd_bus *bus = v; 1354 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1355 struct uhci_xfer *ux, *nextux; 1356 1357 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1358 DPRINTF("sc %p", sc, 0, 0, 0); 1359 1360 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1361 1362 /* 1363 * Interrupts on UHCI really suck. When the host controller 1364 * interrupts because a transfer is completed there is no 1365 * way of knowing which transfer it was. You can scan down 1366 * the TDs and QHs of the previous frame to limit the search, 1367 * but that assumes that the interrupt was not delayed by more 1368 * than 1 ms, which may not always be true (e.g. after debug 1369 * output on a slow console). 1370 * We scan all interrupt descriptors to see if any have 1371 * completed. 1372 */ 1373 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) { 1374 nextux = TAILQ_NEXT(ux, ux_list); 1375 uhci_check_intr(sc, ux); 1376 } 1377 1378 if (sc->sc_softwake) { 1379 sc->sc_softwake = 0; 1380 cv_broadcast(&sc->sc_softwake_cv); 1381 } 1382 } 1383 1384 /* Check for an interrupt. */ 1385 void 1386 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux) 1387 { 1388 uhci_soft_td_t *std, *lstd; 1389 uint32_t status; 1390 1391 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1392 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1393 1394 KASSERT(ux != NULL); 1395 1396 struct usbd_xfer *xfer = &ux->ux_xfer; 1397 if (xfer->ux_status == USBD_CANCELLED || 1398 xfer->ux_status == USBD_TIMEOUT) { 1399 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1400 return; 1401 } 1402 1403 if (ux->ux_stdstart == NULL) 1404 return; 1405 lstd = ux->ux_stdend; 1406 1407 KASSERT(lstd != NULL); 1408 1409 usb_syncmem(&lstd->dma, 1410 lstd->offs + offsetof(uhci_td_t, td_status), 1411 sizeof(lstd->td.td_status), 1412 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1413 status = le32toh(lstd->td.td_status); 1414 usb_syncmem(&lstd->dma, 1415 lstd->offs + offsetof(uhci_td_t, td_status), 1416 sizeof(lstd->td.td_status), 1417 BUS_DMASYNC_PREREAD); 1418 1419 /* If the last TD is not marked active we can complete */ 1420 if (!(status & UHCI_TD_ACTIVE)) { 1421 done: 1422 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1423 1424 callout_stop(&xfer->ux_callout); 1425 uhci_idone(ux); 1426 return; 1427 } 1428 1429 /* 1430 * If the last TD is still active we need to check whether there 1431 * is an error somewhere in the middle, or whether there was a 1432 * short packet (SPD and not ACTIVE). 1433 */ 1434 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1435 for (std = ux->ux_stdstart; std != lstd; std = std->link.std) { 1436 usb_syncmem(&std->dma, 1437 std->offs + offsetof(uhci_td_t, td_status), 1438 sizeof(std->td.td_status), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 status = le32toh(std->td.td_status); 1441 usb_syncmem(&std->dma, 1442 std->offs + offsetof(uhci_td_t, td_status), 1443 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1444 1445 /* If there's an active TD the xfer isn't done. */ 1446 if (status & UHCI_TD_ACTIVE) { 1447 DPRINTFN(12, "ux=%p std=%p still active", 1448 ux, std, 0, 0); 1449 return; 1450 } 1451 1452 /* Any kind of error makes the xfer done. */ 1453 if (status & UHCI_TD_STALLED) 1454 goto done; 1455 1456 /* 1457 * If the data phase of a control transfer is short, we need 1458 * to complete the status stage 1459 */ 1460 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1461 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1462 1463 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1464 struct uhci_pipe *upipe = 1465 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1466 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1467 uhci_soft_td_t *stat = upipe->ctrl.stat; 1468 1469 DPRINTFN(12, "ux=%p std=%p control status" 1470 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1471 1472 sqh->qh.qh_elink = 1473 htole32(stat->physaddr | UHCI_PTR_TD); 1474 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1475 BUS_DMASYNC_PREWRITE); 1476 break; 1477 } 1478 1479 /* We want short packets, and it is short: it's done */ 1480 usb_syncmem(&std->dma, 1481 std->offs + offsetof(uhci_td_t, td_token), 1482 sizeof(std->td.td_token), 1483 BUS_DMASYNC_POSTWRITE); 1484 1485 if ((status & UHCI_TD_SPD) && 1486 UHCI_TD_GET_ACTLEN(status) < 1487 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1488 goto done; 1489 } 1490 } 1491 } 1492 1493 /* Called with USB lock held. */ 1494 void 1495 uhci_idone(struct uhci_xfer *ux) 1496 { 1497 struct usbd_xfer *xfer = &ux->ux_xfer; 1498 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1499 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1500 uhci_soft_td_t *std; 1501 uint32_t status = 0, nstatus; 1502 int actlen; 1503 1504 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1505 1506 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1507 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1508 1509 #ifdef DIAGNOSTIC 1510 #ifdef UHCI_DEBUG 1511 if (ux->ux_isdone) { 1512 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1513 uhci_dump_ii(ux); 1514 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1515 } 1516 #endif 1517 KASSERT(!ux->ux_isdone); 1518 ux->ux_isdone = true; 1519 #endif 1520 1521 if (xfer->ux_nframes != 0) { 1522 /* Isoc transfer, do things differently. */ 1523 uhci_soft_td_t **stds = upipe->isoc.stds; 1524 int i, n, nframes, len; 1525 1526 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1527 1528 nframes = xfer->ux_nframes; 1529 actlen = 0; 1530 n = UHCI_XFER2UXFER(xfer)->ux_curframe; 1531 for (i = 0; i < nframes; i++) { 1532 std = stds[n]; 1533 #ifdef UHCI_DEBUG 1534 if (uhcidebug >= 5) { 1535 DPRINTF("isoc TD %d", i, 0, 0, 0); 1536 uhci_dump_td(std); 1537 } 1538 #endif 1539 if (++n >= UHCI_VFRAMELIST_COUNT) 1540 n = 0; 1541 usb_syncmem(&std->dma, 1542 std->offs + offsetof(uhci_td_t, td_status), 1543 sizeof(std->td.td_status), 1544 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1545 status = le32toh(std->td.td_status); 1546 len = UHCI_TD_GET_ACTLEN(status); 1547 xfer->ux_frlengths[i] = len; 1548 actlen += len; 1549 } 1550 upipe->isoc.inuse -= nframes; 1551 xfer->ux_actlen = actlen; 1552 xfer->ux_status = USBD_NORMAL_COMPLETION; 1553 goto end; 1554 } 1555 1556 #ifdef UHCI_DEBUG 1557 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1558 if (uhcidebug >= 10) { 1559 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1560 uhci_dump_tds(ux->ux_stdstart); 1561 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1562 } 1563 #endif 1564 1565 /* The transfer is done, compute actual length and status. */ 1566 actlen = 0; 1567 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1568 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1569 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1570 nstatus = le32toh(std->td.td_status); 1571 if (nstatus & UHCI_TD_ACTIVE) 1572 break; 1573 1574 status = nstatus; 1575 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1576 UHCI_TD_PID_SETUP) 1577 actlen += UHCI_TD_GET_ACTLEN(status); 1578 else { 1579 /* 1580 * UHCI will report CRCTO in addition to a STALL or NAK 1581 * for a SETUP transaction. See section 3.2.2, "TD 1582 * CONTROL AND STATUS". 1583 */ 1584 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1585 status &= ~UHCI_TD_CRCTO; 1586 } 1587 } 1588 /* If there are left over TDs we need to update the toggle. */ 1589 if (std != NULL) 1590 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1591 1592 status &= UHCI_TD_ERROR; 1593 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1594 xfer->ux_actlen = actlen; 1595 if (status != 0) { 1596 1597 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1598 "error, addr=%d, endpt=0x%02x", 1599 xfer->ux_pipe->up_dev->ud_addr, 1600 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1601 0, 0); 1602 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1603 "bitstuff=%d crcto =%d nak =%d babble =%d", 1604 !!(status & UHCI_TD_BITSTUFF), 1605 !!(status & UHCI_TD_CRCTO), 1606 !!(status & UHCI_TD_NAK), 1607 !!(status & UHCI_TD_BABBLE)); 1608 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1609 "dbuffer =%d stalled =%d active =%d", 1610 !!(status & UHCI_TD_DBUFFER), 1611 !!(status & UHCI_TD_STALLED), 1612 !!(status & UHCI_TD_ACTIVE), 1613 0); 1614 1615 if (status == UHCI_TD_STALLED) 1616 xfer->ux_status = USBD_STALLED; 1617 else 1618 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1619 } else { 1620 xfer->ux_status = USBD_NORMAL_COMPLETION; 1621 } 1622 1623 end: 1624 usb_transfer_complete(xfer); 1625 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1626 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1627 } 1628 1629 /* 1630 * Called when a request does not complete. 1631 */ 1632 void 1633 uhci_timeout(void *addr) 1634 { 1635 struct usbd_xfer *xfer = addr; 1636 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1637 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1638 1639 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1640 1641 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1642 1643 if (sc->sc_dying) { 1644 mutex_enter(&sc->sc_lock); 1645 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1646 mutex_exit(&sc->sc_lock); 1647 return; 1648 } 1649 1650 /* Execute the abort in a process context. */ 1651 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1652 USB_TASKQ_MPSAFE); 1653 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1654 USB_TASKQ_HC); 1655 } 1656 1657 void 1658 uhci_timeout_task(void *addr) 1659 { 1660 struct usbd_xfer *xfer = addr; 1661 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1662 1663 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1664 1665 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1666 1667 mutex_enter(&sc->sc_lock); 1668 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1669 mutex_exit(&sc->sc_lock); 1670 } 1671 1672 /* 1673 * Wait here until controller claims to have an interrupt. 1674 * Then call uhci_intr and return. Use timeout to avoid waiting 1675 * too long. 1676 * Only used during boot when interrupts are not enabled yet. 1677 */ 1678 void 1679 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1680 { 1681 int timo = xfer->ux_timeout; 1682 struct uhci_xfer *ux; 1683 1684 mutex_enter(&sc->sc_lock); 1685 1686 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1687 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1688 1689 xfer->ux_status = USBD_IN_PROGRESS; 1690 for (; timo >= 0; timo--) { 1691 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1692 DPRINTFN(20, "0x%04x", 1693 UREAD2(sc, UHCI_STS), 0, 0, 0); 1694 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1695 mutex_spin_enter(&sc->sc_intr_lock); 1696 uhci_intr1(sc); 1697 mutex_spin_exit(&sc->sc_intr_lock); 1698 if (xfer->ux_status != USBD_IN_PROGRESS) 1699 goto done; 1700 } 1701 } 1702 1703 /* Timeout */ 1704 DPRINTF("timeout", 0, 0, 0, 0); 1705 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux != NULL; 1706 ux = TAILQ_NEXT(ux, ux_list)) 1707 if (&ux->ux_xfer == xfer) 1708 break; 1709 1710 KASSERT(ux != NULL); 1711 1712 uhci_idone(ux); 1713 1714 done: 1715 mutex_exit(&sc->sc_lock); 1716 } 1717 1718 void 1719 uhci_poll(struct usbd_bus *bus) 1720 { 1721 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1722 1723 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1724 mutex_spin_enter(&sc->sc_intr_lock); 1725 uhci_intr1(sc); 1726 mutex_spin_exit(&sc->sc_intr_lock); 1727 } 1728 } 1729 1730 void 1731 uhci_reset(uhci_softc_t *sc) 1732 { 1733 int n; 1734 1735 UHCICMD(sc, UHCI_CMD_HCRESET); 1736 /* The reset bit goes low when the controller is done. */ 1737 for (n = 0; n < UHCI_RESET_TIMEOUT && 1738 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1739 usb_delay_ms(&sc->sc_bus, 1); 1740 if (n >= UHCI_RESET_TIMEOUT) 1741 printf("%s: controller did not reset\n", 1742 device_xname(sc->sc_dev)); 1743 } 1744 1745 usbd_status 1746 uhci_run(uhci_softc_t *sc, int run, int locked) 1747 { 1748 int n, running; 1749 uint16_t cmd; 1750 1751 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1752 1753 run = run != 0; 1754 if (!locked) 1755 mutex_spin_enter(&sc->sc_intr_lock); 1756 1757 DPRINTF("setting run=%d", run, 0, 0, 0); 1758 cmd = UREAD2(sc, UHCI_CMD); 1759 if (run) 1760 cmd |= UHCI_CMD_RS; 1761 else 1762 cmd &= ~UHCI_CMD_RS; 1763 UHCICMD(sc, cmd); 1764 for(n = 0; n < 10; n++) { 1765 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1766 /* return when we've entered the state we want */ 1767 if (run == running) { 1768 if (!locked) 1769 mutex_spin_exit(&sc->sc_intr_lock); 1770 DPRINTF("done cmd=0x%x sts=0x%x", 1771 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1772 return USBD_NORMAL_COMPLETION; 1773 } 1774 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1775 } 1776 if (!locked) 1777 mutex_spin_exit(&sc->sc_intr_lock); 1778 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1779 run ? "start" : "stop"); 1780 return USBD_IOERROR; 1781 } 1782 1783 /* 1784 * Memory management routines. 1785 * uhci_alloc_std allocates TDs 1786 * uhci_alloc_sqh allocates QHs 1787 * These two routines do their own free list management, 1788 * partly for speed, partly because allocating DMAable memory 1789 * has page size granularity so much memory would be wasted if 1790 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1791 */ 1792 1793 uhci_soft_td_t * 1794 uhci_alloc_std(uhci_softc_t *sc) 1795 { 1796 uhci_soft_td_t *std; 1797 usbd_status err; 1798 int i, offs; 1799 usb_dma_t dma; 1800 1801 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1802 1803 if (sc->sc_freetds == NULL) { 1804 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1805 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1806 UHCI_TD_ALIGN, &dma); 1807 if (err) 1808 return 0; 1809 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1810 offs = i * UHCI_STD_SIZE; 1811 std = KERNADDR(&dma, offs); 1812 std->physaddr = DMAADDR(&dma, offs); 1813 std->dma = dma; 1814 std->offs = offs; 1815 std->link.std = sc->sc_freetds; 1816 sc->sc_freetds = std; 1817 } 1818 } 1819 std = sc->sc_freetds; 1820 sc->sc_freetds = std->link.std; 1821 memset(&std->td, 0, sizeof(uhci_td_t)); 1822 return std; 1823 } 1824 1825 void 1826 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1827 { 1828 #ifdef DIAGNOSTIC 1829 #define TD_IS_FREE 0x12345678 1830 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1831 printf("uhci_free_std: freeing free TD %p\n", std); 1832 return; 1833 } 1834 std->td.td_token = htole32(TD_IS_FREE); 1835 #endif 1836 std->link.std = sc->sc_freetds; 1837 sc->sc_freetds = std; 1838 } 1839 1840 uhci_soft_qh_t * 1841 uhci_alloc_sqh(uhci_softc_t *sc) 1842 { 1843 uhci_soft_qh_t *sqh; 1844 usbd_status err; 1845 int i, offs; 1846 usb_dma_t dma; 1847 1848 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1849 1850 if (sc->sc_freeqhs == NULL) { 1851 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1852 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1853 UHCI_QH_ALIGN, &dma); 1854 if (err) 1855 return 0; 1856 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1857 offs = i * UHCI_SQH_SIZE; 1858 sqh = KERNADDR(&dma, offs); 1859 sqh->physaddr = DMAADDR(&dma, offs); 1860 sqh->dma = dma; 1861 sqh->offs = offs; 1862 sqh->hlink = sc->sc_freeqhs; 1863 sc->sc_freeqhs = sqh; 1864 } 1865 } 1866 sqh = sc->sc_freeqhs; 1867 sc->sc_freeqhs = sqh->hlink; 1868 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1869 return sqh; 1870 } 1871 1872 void 1873 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1874 { 1875 sqh->hlink = sc->sc_freeqhs; 1876 sc->sc_freeqhs = sqh; 1877 } 1878 1879 void 1880 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1881 uhci_soft_td_t *stdend) 1882 { 1883 uhci_soft_td_t *p; 1884 uint32_t td_link; 1885 1886 /* 1887 * to avoid race condition with the controller which may be looking 1888 * at this chain, we need to first invalidate all links, and 1889 * then wait for the controller to move to another queue 1890 */ 1891 for (p = std; p != stdend; p = p->link.std) { 1892 usb_syncmem(&p->dma, 1893 p->offs + offsetof(uhci_td_t, td_link), 1894 sizeof(p->td.td_link), 1895 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1896 td_link = le32toh(p->td.td_link); 1897 usb_syncmem(&p->dma, 1898 p->offs + offsetof(uhci_td_t, td_link), 1899 sizeof(p->td.td_link), 1900 BUS_DMASYNC_PREREAD); 1901 if ((td_link & UHCI_PTR_T) == 0) { 1902 p->td.td_link = htole32(UHCI_PTR_T); 1903 usb_syncmem(&p->dma, 1904 p->offs + offsetof(uhci_td_t, td_link), 1905 sizeof(p->td.td_link), 1906 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1907 } 1908 } 1909 delay(UHCI_QH_REMOVE_DELAY); 1910 1911 for (; std != stdend; std = p) { 1912 p = std->link.std; 1913 uhci_free_std(sc, std); 1914 } 1915 } 1916 1917 usbd_status 1918 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1919 int rd, uint16_t flags, usb_dma_t *dma, 1920 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1921 { 1922 uhci_soft_td_t *p, *lastp; 1923 uhci_physaddr_t lastlink; 1924 int i, ntd, l, tog, maxp; 1925 uint32_t status; 1926 int addr = upipe->pipe.up_dev->ud_addr; 1927 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1928 1929 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1930 1931 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 1932 addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed); 1933 1934 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1935 1936 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1937 if (maxp == 0) { 1938 printf("uhci_alloc_std_chain: maxp=0\n"); 1939 return USBD_INVAL; 1940 } 1941 ntd = (len + maxp - 1) / maxp; 1942 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1943 ntd++; 1944 DPRINTFN(10, "maxp=%d ntd=%d", 1945 maxp, ntd, 0, 0); 1946 1947 if (ntd == 0) { 1948 *sp = *ep = NULL; 1949 DPRINTF("ntd=0", 0, 0, 0, 0); 1950 return USBD_NORMAL_COMPLETION; 1951 } 1952 tog = upipe->nexttoggle; 1953 if (ntd % 2 == 0) 1954 tog ^= 1; 1955 upipe->nexttoggle = tog ^ 1; 1956 lastp = NULL; 1957 lastlink = UHCI_PTR_T; 1958 ntd--; 1959 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1960 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1961 status |= UHCI_TD_LS; 1962 if (flags & USBD_SHORT_XFER_OK) 1963 status |= UHCI_TD_SPD; 1964 usb_syncmem(dma, 0, len, 1965 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1966 for (i = ntd; i >= 0; i--) { 1967 p = uhci_alloc_std(sc); 1968 if (p == NULL) { 1969 KASSERT(lastp != NULL); 1970 uhci_free_std_chain(sc, lastp, NULL); 1971 return USBD_NOMEM; 1972 } 1973 p->link.std = lastp; 1974 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1975 lastp = p; 1976 lastlink = p->physaddr; 1977 p->td.td_status = htole32(status); 1978 if (i == ntd) { 1979 /* last TD */ 1980 l = len % maxp; 1981 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1982 l = maxp; 1983 *ep = p; 1984 } else 1985 l = maxp; 1986 p->td.td_token = 1987 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1988 UHCI_TD_OUT(l, endpt, addr, tog)); 1989 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1990 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1991 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1992 tog ^= 1; 1993 } 1994 *sp = lastp; 1995 DPRINTFN(10, "nexttog=%d", upipe->nexttoggle, 1996 0, 0, 0); 1997 1998 return USBD_NORMAL_COMPLETION; 1999 } 2000 2001 void 2002 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2003 { 2004 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2005 upipe->nexttoggle = 0; 2006 } 2007 2008 void 2009 uhci_noop(struct usbd_pipe *pipe) 2010 { 2011 } 2012 2013 usbd_status 2014 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2015 { 2016 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2017 usbd_status err; 2018 2019 /* Insert last in queue. */ 2020 mutex_enter(&sc->sc_lock); 2021 err = usb_insert_transfer(xfer); 2022 mutex_exit(&sc->sc_lock); 2023 if (err) 2024 return err; 2025 2026 /* 2027 * Pipe isn't running (otherwise err would be USBD_INPROG), 2028 * so start it first. 2029 */ 2030 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2031 } 2032 2033 usbd_status 2034 uhci_device_bulk_start(struct usbd_xfer *xfer) 2035 { 2036 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2037 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2038 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2039 uhci_soft_td_t *data, *dataend; 2040 uhci_soft_qh_t *sqh; 2041 usbd_status err; 2042 int len, isread, endpt; 2043 2044 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2045 DPRINTFN(3, "xfer=%p len=%d flags=%d ux=%p", 2046 xfer, xfer->ux_length, xfer->ux_flags, ux); 2047 2048 if (sc->sc_dying) 2049 return USBD_IOERROR; 2050 2051 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2052 2053 mutex_enter(&sc->sc_lock); 2054 2055 len = xfer->ux_length; 2056 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2057 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2058 sqh = upipe->bulk.sqh; 2059 2060 upipe->bulk.isread = isread; 2061 upipe->bulk.length = len; 2062 2063 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2064 &xfer->ux_dmabuf, &data, &dataend); 2065 if (err) { 2066 mutex_exit(&sc->sc_lock); 2067 return err; 2068 } 2069 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2070 usb_syncmem(&dataend->dma, 2071 dataend->offs + offsetof(uhci_td_t, td_status), 2072 sizeof(dataend->td.td_status), 2073 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2074 2075 2076 #ifdef UHCI_DEBUG 2077 if (uhcidebug >= 8) { 2078 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2079 DPRINTFN(8, "data(1)", 0, 0, 0, 0); 2080 uhci_dump_tds(data); 2081 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2082 } 2083 #endif 2084 2085 /* Set up interrupt info. */ 2086 ux->ux_stdstart = data; 2087 ux->ux_stdend = dataend; 2088 2089 KASSERT(ux->ux_isdone); 2090 #ifdef DIAGNOSTIC 2091 ux->ux_isdone = false; 2092 #endif 2093 2094 sqh->elink = data; 2095 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2096 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2097 2098 uhci_add_bulk(sc, sqh); 2099 uhci_add_intr_info(sc, ux); 2100 2101 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2102 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2103 uhci_timeout, xfer); 2104 } 2105 xfer->ux_status = USBD_IN_PROGRESS; 2106 2107 #ifdef UHCI_DEBUG 2108 if (uhcidebug >= 10) { 2109 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2110 DPRINTFN(10, "data(2)", 0, 0, 0, 0); 2111 uhci_dump_tds(data); 2112 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2113 } 2114 #endif 2115 2116 if (sc->sc_bus.ub_usepolling) 2117 uhci_waitintr(sc, xfer); 2118 2119 mutex_exit(&sc->sc_lock); 2120 return USBD_IN_PROGRESS; 2121 } 2122 2123 /* Abort a device bulk request. */ 2124 void 2125 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2126 { 2127 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2128 2129 KASSERT(mutex_owned(&sc->sc_lock)); 2130 2131 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2132 2133 uhci_abort_xfer(xfer, USBD_CANCELLED); 2134 } 2135 2136 /* 2137 * Abort a device request. 2138 * If this routine is called at splusb() it guarantees that the request 2139 * will be removed from the hardware scheduling and that the callback 2140 * for it will be called with USBD_CANCELLED status. 2141 * It's impossible to guarantee that the requested transfer will not 2142 * have happened since the hardware runs concurrently. 2143 * If the transaction has already happened we rely on the ordinary 2144 * interrupt processing to process it. 2145 * XXX This is most probably wrong. 2146 * XXXMRG this doesn't make sense anymore. 2147 */ 2148 void 2149 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2150 { 2151 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2152 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2153 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2154 uhci_soft_td_t *std; 2155 int wake; 2156 2157 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2158 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2159 2160 KASSERT(mutex_owned(&sc->sc_lock)); 2161 ASSERT_SLEEPABLE(); 2162 2163 if (sc->sc_dying) { 2164 /* If we're dying, just do the software part. */ 2165 xfer->ux_status = status; /* make software ignore it */ 2166 callout_stop(&xfer->ux_callout); 2167 usb_transfer_complete(xfer); 2168 return; 2169 } 2170 2171 /* 2172 * If an abort is already in progress then just wait for it to 2173 * complete and return. 2174 */ 2175 if (xfer->ux_hcflags & UXFER_ABORTING) { 2176 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2177 #ifdef DIAGNOSTIC 2178 if (status == USBD_TIMEOUT) 2179 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2180 #endif 2181 /* Override the status which might be USBD_TIMEOUT. */ 2182 xfer->ux_status = status; 2183 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2184 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2185 while (xfer->ux_hcflags & UXFER_ABORTING) 2186 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2187 goto done; 2188 } 2189 xfer->ux_hcflags |= UXFER_ABORTING; 2190 2191 /* 2192 * Step 1: Make interrupt routine and hardware ignore xfer. 2193 */ 2194 xfer->ux_status = status; /* make software ignore it */ 2195 callout_stop(&xfer->ux_callout); 2196 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2197 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2198 usb_syncmem(&std->dma, 2199 std->offs + offsetof(uhci_td_t, td_status), 2200 sizeof(std->td.td_status), 2201 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2202 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2203 usb_syncmem(&std->dma, 2204 std->offs + offsetof(uhci_td_t, td_status), 2205 sizeof(std->td.td_status), 2206 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2207 } 2208 2209 /* 2210 * Step 2: Wait until we know hardware has finished any possible 2211 * use of the xfer. Also make sure the soft interrupt routine 2212 * has run. 2213 */ 2214 /* Hardware finishes in 1ms */ 2215 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2216 sc->sc_softwake = 1; 2217 usb_schedsoftintr(&sc->sc_bus); 2218 DPRINTF("cv_wait", 0, 0, 0, 0); 2219 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2220 2221 /* 2222 * Step 3: Execute callback. 2223 */ 2224 DPRINTF("callback", 0, 0, 0, 0); 2225 #ifdef DIAGNOSTIC 2226 ux->ux_isdone = true; 2227 #endif 2228 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2229 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2230 usb_transfer_complete(xfer); 2231 if (wake) 2232 cv_broadcast(&xfer->ux_hccv); 2233 done: 2234 KASSERT(mutex_owned(&sc->sc_lock)); 2235 } 2236 2237 /* Close a device bulk pipe. */ 2238 void 2239 uhci_device_bulk_close(struct usbd_pipe *pipe) 2240 { 2241 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2242 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2243 2244 KASSERT(mutex_owned(&sc->sc_lock)); 2245 2246 uhci_free_sqh(sc, upipe->bulk.sqh); 2247 2248 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2249 } 2250 2251 usbd_status 2252 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2253 { 2254 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2255 usbd_status err; 2256 2257 /* Insert last in queue. */ 2258 mutex_enter(&sc->sc_lock); 2259 err = usb_insert_transfer(xfer); 2260 mutex_exit(&sc->sc_lock); 2261 if (err) 2262 return err; 2263 2264 /* 2265 * Pipe isn't running (otherwise err would be USBD_INPROG), 2266 * so start it first. 2267 */ 2268 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2269 } 2270 2271 usbd_status 2272 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2273 { 2274 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2275 usbd_status err; 2276 2277 if (sc->sc_dying) 2278 return USBD_IOERROR; 2279 2280 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2281 2282 mutex_enter(&sc->sc_lock); 2283 err = uhci_device_request(xfer); 2284 mutex_exit(&sc->sc_lock); 2285 if (err) 2286 return err; 2287 2288 if (sc->sc_bus.ub_usepolling) 2289 uhci_waitintr(sc, xfer); 2290 return USBD_IN_PROGRESS; 2291 } 2292 2293 usbd_status 2294 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2295 { 2296 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2297 usbd_status err; 2298 2299 /* Insert last in queue. */ 2300 mutex_enter(&sc->sc_lock); 2301 err = usb_insert_transfer(xfer); 2302 mutex_exit(&sc->sc_lock); 2303 if (err) 2304 return err; 2305 2306 /* 2307 * Pipe isn't running (otherwise err would be USBD_INPROG), 2308 * so start it first. 2309 */ 2310 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2311 } 2312 2313 usbd_status 2314 uhci_device_intr_start(struct usbd_xfer *xfer) 2315 { 2316 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2317 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2318 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2319 uhci_soft_td_t *data, *dataend; 2320 uhci_soft_qh_t *sqh; 2321 usbd_status err; 2322 int isread, endpt; 2323 int i; 2324 2325 if (sc->sc_dying) 2326 return USBD_IOERROR; 2327 2328 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2329 2330 DPRINTFN(3, "xfer=%p len=%d flags=%d", 2331 xfer, xfer->ux_length, xfer->ux_flags, 0); 2332 2333 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2334 2335 mutex_enter(&sc->sc_lock); 2336 2337 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2338 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2339 2340 upipe->intr.isread = isread; 2341 2342 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2343 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2344 &dataend); 2345 if (err) { 2346 mutex_exit(&sc->sc_lock); 2347 return err; 2348 } 2349 2350 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2351 usb_syncmem(&dataend->dma, 2352 dataend->offs + offsetof(uhci_td_t, td_status), 2353 sizeof(dataend->td.td_status), 2354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2355 2356 #ifdef UHCI_DEBUG 2357 if (uhcidebug >= 10) { 2358 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2359 uhci_dump_tds(data); 2360 uhci_dump_qh(upipe->intr.qhs[0]); 2361 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2362 } 2363 #endif 2364 2365 /* Set up interrupt info. */ 2366 ux->ux_stdstart = data; 2367 ux->ux_stdend = dataend; 2368 KASSERT(ux->ux_isdone); 2369 #ifdef DIAGNOSTIC 2370 ux->ux_isdone = false; 2371 #endif 2372 2373 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2374 for (i = 0; i < upipe->intr.npoll; i++) { 2375 sqh = upipe->intr.qhs[i]; 2376 sqh->elink = data; 2377 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2378 usb_syncmem(&sqh->dma, 2379 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2380 sizeof(sqh->qh.qh_elink), 2381 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2382 } 2383 uhci_add_intr_info(sc, ux); 2384 xfer->ux_status = USBD_IN_PROGRESS; 2385 mutex_exit(&sc->sc_lock); 2386 2387 #ifdef UHCI_DEBUG 2388 if (uhcidebug >= 10) { 2389 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2390 uhci_dump_tds(data); 2391 uhci_dump_qh(upipe->intr.qhs[0]); 2392 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2393 } 2394 #endif 2395 2396 return USBD_IN_PROGRESS; 2397 } 2398 2399 /* Abort a device control request. */ 2400 void 2401 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2402 { 2403 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2404 2405 KASSERT(mutex_owned(&sc->sc_lock)); 2406 2407 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2408 uhci_abort_xfer(xfer, USBD_CANCELLED); 2409 } 2410 2411 /* Close a device control pipe. */ 2412 void 2413 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2414 { 2415 } 2416 2417 /* Abort a device interrupt request. */ 2418 void 2419 uhci_device_intr_abort(struct usbd_xfer *xfer) 2420 { 2421 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2422 2423 KASSERT(mutex_owned(&sc->sc_lock)); 2424 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2425 2426 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2427 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2428 2429 uhci_abort_xfer(xfer, USBD_CANCELLED); 2430 } 2431 2432 /* Close a device interrupt pipe. */ 2433 void 2434 uhci_device_intr_close(struct usbd_pipe *pipe) 2435 { 2436 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2437 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2438 int i, npoll; 2439 2440 KASSERT(mutex_owned(&sc->sc_lock)); 2441 2442 /* Unlink descriptors from controller data structures. */ 2443 npoll = upipe->intr.npoll; 2444 for (i = 0; i < npoll; i++) 2445 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2446 2447 /* 2448 * We now have to wait for any activity on the physical 2449 * descriptors to stop. 2450 */ 2451 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2452 2453 for(i = 0; i < npoll; i++) 2454 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2455 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2456 2457 /* XXX free other resources */ 2458 } 2459 2460 usbd_status 2461 uhci_device_request(struct usbd_xfer *xfer) 2462 { 2463 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2464 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2465 usb_device_request_t *req = &xfer->ux_request; 2466 struct usbd_device *dev = upipe->pipe.up_dev; 2467 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2468 int addr = dev->ud_addr; 2469 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2470 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2471 uhci_soft_qh_t *sqh; 2472 int len; 2473 uint32_t ls; 2474 usbd_status err; 2475 int isread; 2476 2477 KASSERT(mutex_owned(&sc->sc_lock)); 2478 2479 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2480 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2481 "wValue=0x%04x, wIndex=0x%04x", 2482 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2483 UGETW(req->wIndex)); 2484 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2485 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2486 2487 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2488 isread = req->bmRequestType & UT_READ; 2489 len = UGETW(req->wLength); 2490 2491 setup = upipe->ctrl.setup; 2492 stat = upipe->ctrl.stat; 2493 sqh = upipe->ctrl.sqh; 2494 2495 /* Set up data transaction */ 2496 if (len != 0) { 2497 upipe->nexttoggle = 1; 2498 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2499 &xfer->ux_dmabuf, &data, &dataend); 2500 if (err) 2501 return err; 2502 next = data; 2503 dataend->link.std = stat; 2504 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2505 usb_syncmem(&dataend->dma, 2506 dataend->offs + offsetof(uhci_td_t, td_link), 2507 sizeof(dataend->td.td_link), 2508 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2509 } else { 2510 next = stat; 2511 } 2512 upipe->ctrl.length = len; 2513 2514 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2515 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2516 2517 setup->link.std = next; 2518 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2519 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2520 UHCI_TD_ACTIVE); 2521 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2522 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2523 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2524 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2525 2526 stat->link.std = NULL; 2527 stat->td.td_link = htole32(UHCI_PTR_T); 2528 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2529 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2530 stat->td.td_token = 2531 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2532 UHCI_TD_IN (0, endpt, addr, 1)); 2533 stat->td.td_buffer = htole32(0); 2534 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2536 2537 #ifdef UHCI_DEBUG 2538 if (uhcidebug >= 10) { 2539 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2540 DPRINTF("before transfer", 0, 0, 0, 0); 2541 uhci_dump_tds(setup); 2542 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2543 } 2544 #endif 2545 2546 /* Set up interrupt info. */ 2547 uxfer->ux_stdstart = setup; 2548 uxfer->ux_stdend = stat; 2549 KASSERT(uxfer->ux_isdone); 2550 #ifdef DIAGNOSTIC 2551 uxfer->ux_isdone = false; 2552 #endif 2553 2554 sqh->elink = setup; 2555 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2556 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2557 2558 if (dev->ud_speed == USB_SPEED_LOW) 2559 uhci_add_ls_ctrl(sc, sqh); 2560 else 2561 uhci_add_hs_ctrl(sc, sqh); 2562 uhci_add_intr_info(sc, uxfer); 2563 #ifdef UHCI_DEBUG 2564 if (uhcidebug >= 12) { 2565 uhci_soft_td_t *std; 2566 uhci_soft_qh_t *xqh; 2567 uhci_soft_qh_t *sxqh; 2568 int maxqh = 0; 2569 uhci_physaddr_t link; 2570 2571 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2572 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2573 for (std = sc->sc_vframes[0].htd, link = 0; 2574 (link & UHCI_PTR_QH) == 0; 2575 std = std->link.std) { 2576 link = le32toh(std->td.td_link); 2577 uhci_dump_td(std); 2578 } 2579 sxqh = (uhci_soft_qh_t *)std; 2580 uhci_dump_qh(sxqh); 2581 for (xqh = sxqh; 2582 xqh != NULL; 2583 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2584 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2585 uhci_dump_qh(xqh); 2586 } 2587 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2588 uhci_dump_qh(sqh); 2589 uhci_dump_tds(sqh->elink); 2590 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2591 } 2592 #endif 2593 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2594 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2595 uhci_timeout, xfer); 2596 } 2597 xfer->ux_status = USBD_IN_PROGRESS; 2598 2599 return USBD_NORMAL_COMPLETION; 2600 } 2601 2602 usbd_status 2603 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2604 { 2605 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2606 usbd_status err; 2607 2608 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2609 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2610 2611 /* Put it on our queue, */ 2612 mutex_enter(&sc->sc_lock); 2613 err = usb_insert_transfer(xfer); 2614 mutex_exit(&sc->sc_lock); 2615 2616 /* bail out on error, */ 2617 if (err && err != USBD_IN_PROGRESS) 2618 return err; 2619 2620 /* XXX should check inuse here */ 2621 2622 /* insert into schedule, */ 2623 uhci_device_isoc_enter(xfer); 2624 2625 /* and start if the pipe wasn't running */ 2626 if (!err) 2627 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2628 2629 return err; 2630 } 2631 2632 void 2633 uhci_device_isoc_enter(struct usbd_xfer *xfer) 2634 { 2635 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2636 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2637 struct isoc *isoc = &upipe->isoc; 2638 uhci_soft_td_t *std; 2639 uint32_t buf, len, status, offs; 2640 int i, next, nframes; 2641 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2642 2643 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2644 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2645 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2646 2647 if (sc->sc_dying) 2648 return; 2649 2650 if (xfer->ux_status == USBD_IN_PROGRESS) { 2651 /* This request has already been entered into the frame list */ 2652 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2653 /* XXX */ 2654 } 2655 2656 #ifdef DIAGNOSTIC 2657 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2658 printf("uhci_device_isoc_enter: overflow!\n"); 2659 #endif 2660 2661 next = isoc->next; 2662 if (next == -1) { 2663 /* Not in use yet, schedule it a few frames ahead. */ 2664 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2665 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2666 } 2667 2668 xfer->ux_status = USBD_IN_PROGRESS; 2669 UHCI_XFER2UXFER(xfer)->ux_curframe = next; 2670 2671 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2672 offs = 0; 2673 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2674 UHCI_TD_ACTIVE | 2675 UHCI_TD_IOS); 2676 nframes = xfer->ux_nframes; 2677 mutex_enter(&sc->sc_lock); 2678 for (i = 0; i < nframes; i++) { 2679 std = isoc->stds[next]; 2680 if (++next >= UHCI_VFRAMELIST_COUNT) 2681 next = 0; 2682 len = xfer->ux_frlengths[i]; 2683 std->td.td_buffer = htole32(buf); 2684 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2685 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2686 if (i == nframes - 1) 2687 status |= UHCI_TD_IOC; 2688 std->td.td_status = htole32(status); 2689 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2690 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2691 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2692 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2693 #ifdef UHCI_DEBUG 2694 if (uhcidebug >= 5) { 2695 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2696 DPRINTF("TD %d", i, 0, 0, 0); 2697 uhci_dump_td(std); 2698 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2699 } 2700 #endif 2701 buf += len; 2702 offs += len; 2703 } 2704 isoc->next = next; 2705 isoc->inuse += xfer->ux_nframes; 2706 2707 mutex_exit(&sc->sc_lock); 2708 } 2709 2710 usbd_status 2711 uhci_device_isoc_start(struct usbd_xfer *xfer) 2712 { 2713 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2714 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2715 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2716 uhci_soft_td_t *end; 2717 int i; 2718 2719 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2720 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2721 2722 mutex_enter(&sc->sc_lock); 2723 2724 if (sc->sc_dying) { 2725 mutex_exit(&sc->sc_lock); 2726 return USBD_IOERROR; 2727 } 2728 2729 #ifdef DIAGNOSTIC 2730 if (xfer->ux_status != USBD_IN_PROGRESS) 2731 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2732 #endif 2733 2734 /* Find the last TD */ 2735 i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes; 2736 if (i >= UHCI_VFRAMELIST_COUNT) 2737 i -= UHCI_VFRAMELIST_COUNT; 2738 end = upipe->isoc.stds[i]; 2739 2740 KASSERT(end != NULL); 2741 2742 /* Set up interrupt info. */ 2743 ux->ux_stdstart = end; 2744 ux->ux_stdend = end; 2745 2746 KASSERT(ux->ux_isdone); 2747 #ifdef DIAGNOSTIC 2748 ux->ux_isdone = false; 2749 #endif 2750 uhci_add_intr_info(sc, ux); 2751 2752 mutex_exit(&sc->sc_lock); 2753 2754 return USBD_IN_PROGRESS; 2755 } 2756 2757 void 2758 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2759 { 2760 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2761 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2762 uhci_soft_td_t **stds = upipe->isoc.stds; 2763 uhci_soft_td_t *std; 2764 int i, n, nframes, maxlen, len; 2765 2766 KASSERT(mutex_owned(&sc->sc_lock)); 2767 2768 /* Transfer is already done. */ 2769 if (xfer->ux_status != USBD_NOT_STARTED && 2770 xfer->ux_status != USBD_IN_PROGRESS) { 2771 return; 2772 } 2773 2774 /* Give xfer the requested abort code. */ 2775 xfer->ux_status = USBD_CANCELLED; 2776 2777 /* make hardware ignore it, */ 2778 nframes = xfer->ux_nframes; 2779 n = UHCI_XFER2UXFER(xfer)->ux_curframe; 2780 maxlen = 0; 2781 for (i = 0; i < nframes; i++) { 2782 std = stds[n]; 2783 usb_syncmem(&std->dma, 2784 std->offs + offsetof(uhci_td_t, td_status), 2785 sizeof(std->td.td_status), 2786 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2787 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2788 usb_syncmem(&std->dma, 2789 std->offs + offsetof(uhci_td_t, td_status), 2790 sizeof(std->td.td_status), 2791 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2792 usb_syncmem(&std->dma, 2793 std->offs + offsetof(uhci_td_t, td_token), 2794 sizeof(std->td.td_token), 2795 BUS_DMASYNC_POSTWRITE); 2796 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2797 if (len > maxlen) 2798 maxlen = len; 2799 if (++n >= UHCI_VFRAMELIST_COUNT) 2800 n = 0; 2801 } 2802 2803 /* and wait until we are sure the hardware has finished. */ 2804 delay(maxlen); 2805 2806 #ifdef DIAGNOSTIC 2807 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 2808 #endif 2809 /* Run callback and remove from interrupt list. */ 2810 usb_transfer_complete(xfer); 2811 2812 KASSERT(mutex_owned(&sc->sc_lock)); 2813 } 2814 2815 void 2816 uhci_device_isoc_close(struct usbd_pipe *pipe) 2817 { 2818 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2819 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2820 uhci_soft_td_t *std, *vstd; 2821 struct isoc *isoc; 2822 int i; 2823 2824 KASSERT(mutex_owned(&sc->sc_lock)); 2825 2826 /* 2827 * Make sure all TDs are marked as inactive. 2828 * Wait for completion. 2829 * Unschedule. 2830 * Deallocate. 2831 */ 2832 isoc = &upipe->isoc; 2833 2834 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2835 std = isoc->stds[i]; 2836 usb_syncmem(&std->dma, 2837 std->offs + offsetof(uhci_td_t, td_status), 2838 sizeof(std->td.td_status), 2839 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2840 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2841 usb_syncmem(&std->dma, 2842 std->offs + offsetof(uhci_td_t, td_status), 2843 sizeof(std->td.td_status), 2844 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2845 } 2846 /* wait for completion */ 2847 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2848 2849 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2850 std = isoc->stds[i]; 2851 for (vstd = sc->sc_vframes[i].htd; 2852 vstd != NULL && vstd->link.std != std; 2853 vstd = vstd->link.std) 2854 ; 2855 if (vstd == NULL) { 2856 /*panic*/ 2857 printf("uhci_device_isoc_close: %p not found\n", std); 2858 mutex_exit(&sc->sc_lock); 2859 return; 2860 } 2861 vstd->link = std->link; 2862 usb_syncmem(&std->dma, 2863 std->offs + offsetof(uhci_td_t, td_link), 2864 sizeof(std->td.td_link), 2865 BUS_DMASYNC_POSTWRITE); 2866 vstd->td.td_link = std->td.td_link; 2867 usb_syncmem(&vstd->dma, 2868 vstd->offs + offsetof(uhci_td_t, td_link), 2869 sizeof(vstd->td.td_link), 2870 BUS_DMASYNC_PREWRITE); 2871 uhci_free_std(sc, std); 2872 } 2873 2874 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2875 } 2876 2877 usbd_status 2878 uhci_setup_isoc(struct usbd_pipe *pipe) 2879 { 2880 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2881 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2882 int addr = upipe->pipe.up_dev->ud_addr; 2883 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2884 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2885 uhci_soft_td_t *std, *vstd; 2886 uint32_t token; 2887 struct isoc *isoc; 2888 int i; 2889 2890 isoc = &upipe->isoc; 2891 isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2892 sizeof(uhci_soft_td_t *), 2893 KM_SLEEP); 2894 if (isoc->stds == NULL) 2895 return USBD_NOMEM; 2896 2897 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2898 UHCI_TD_OUT(0, endpt, addr, 0); 2899 2900 mutex_enter(&sc->sc_lock); 2901 2902 /* Allocate the TDs and mark as inactive; */ 2903 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2904 std = uhci_alloc_std(sc); 2905 if (std == 0) 2906 goto bad; 2907 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2908 std->td.td_token = htole32(token); 2909 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2910 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2911 isoc->stds[i] = std; 2912 } 2913 2914 /* Insert TDs into schedule. */ 2915 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2916 std = isoc->stds[i]; 2917 vstd = sc->sc_vframes[i].htd; 2918 usb_syncmem(&vstd->dma, 2919 vstd->offs + offsetof(uhci_td_t, td_link), 2920 sizeof(vstd->td.td_link), 2921 BUS_DMASYNC_POSTWRITE); 2922 std->link = vstd->link; 2923 std->td.td_link = vstd->td.td_link; 2924 usb_syncmem(&std->dma, 2925 std->offs + offsetof(uhci_td_t, td_link), 2926 sizeof(std->td.td_link), 2927 BUS_DMASYNC_PREWRITE); 2928 vstd->link.std = std; 2929 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2930 usb_syncmem(&vstd->dma, 2931 vstd->offs + offsetof(uhci_td_t, td_link), 2932 sizeof(vstd->td.td_link), 2933 BUS_DMASYNC_PREWRITE); 2934 } 2935 mutex_exit(&sc->sc_lock); 2936 2937 isoc->next = -1; 2938 isoc->inuse = 0; 2939 2940 return USBD_NORMAL_COMPLETION; 2941 2942 bad: 2943 while (--i >= 0) 2944 uhci_free_std(sc, isoc->stds[i]); 2945 mutex_exit(&sc->sc_lock); 2946 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2947 return USBD_NOMEM; 2948 } 2949 2950 void 2951 uhci_device_isoc_done(struct usbd_xfer *xfer) 2952 { 2953 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2954 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2955 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2956 int i, offs; 2957 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2958 2959 2960 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2961 DPRINTFN(4, "length=%d, ux_state=0x%08x", 2962 xfer->ux_actlen, xfer->ux_state, 0, 0); 2963 2964 if (!uhci_active_intr_info(ux)) 2965 return; 2966 2967 #ifdef DIAGNOSTIC 2968 if (ux->ux_stdend == NULL) { 2969 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2970 #ifdef UHCI_DEBUG 2971 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2972 uhci_dump_ii(ux); 2973 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2974 #endif 2975 return; 2976 } 2977 #endif 2978 2979 /* Turn off the interrupt since it is active even if the TD is not. */ 2980 usb_syncmem(&ux->ux_stdend->dma, 2981 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 2982 sizeof(ux->ux_stdend->td.td_status), 2983 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2984 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2985 usb_syncmem(&ux->ux_stdend->dma, 2986 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 2987 sizeof(ux->ux_stdend->td.td_status), 2988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2989 2990 uhci_del_intr_info(sc, ux); /* remove from active list */ 2991 2992 offs = 0; 2993 for (i = 0; i < xfer->ux_nframes; i++) { 2994 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2995 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2996 offs += xfer->ux_frlengths[i]; 2997 } 2998 } 2999 3000 void 3001 uhci_device_intr_done(struct usbd_xfer *xfer) 3002 { 3003 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3004 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3005 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3006 uhci_soft_qh_t *sqh; 3007 int i, npoll, isread; 3008 3009 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3010 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3011 3012 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3013 3014 npoll = upipe->intr.npoll; 3015 for(i = 0; i < npoll; i++) { 3016 sqh = upipe->intr.qhs[i]; 3017 sqh->elink = NULL; 3018 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3019 usb_syncmem(&sqh->dma, 3020 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3021 sizeof(sqh->qh.qh_elink), 3022 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3023 } 3024 uhci_free_std_chain(sc, ux->ux_stdstart, NULL); 3025 3026 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3027 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3028 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3029 3030 /* XXX Wasteful. */ 3031 if (xfer->ux_pipe->up_repeat) { 3032 uhci_soft_td_t *data, *dataend; 3033 3034 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3035 3036 /* This alloc cannot fail since we freed the chain above. */ 3037 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3038 upipe->intr.isread, xfer->ux_flags, 3039 &xfer->ux_dmabuf, &data, &dataend); 3040 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3041 usb_syncmem(&dataend->dma, 3042 dataend->offs + offsetof(uhci_td_t, td_status), 3043 sizeof(dataend->td.td_status), 3044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3045 3046 #ifdef UHCI_DEBUG 3047 if (uhcidebug >= 10) { 3048 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3049 uhci_dump_tds(data); 3050 uhci_dump_qh(upipe->intr.qhs[0]); 3051 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3052 } 3053 #endif 3054 3055 ux->ux_stdstart = data; 3056 ux->ux_stdend = dataend; 3057 KASSERT(ux->ux_isdone); 3058 #ifdef DIAGNOSTIC 3059 ux->ux_isdone = false; 3060 #endif 3061 for (i = 0; i < npoll; i++) { 3062 sqh = upipe->intr.qhs[i]; 3063 sqh->elink = data; 3064 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3065 usb_syncmem(&sqh->dma, 3066 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3067 sizeof(sqh->qh.qh_elink), 3068 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3069 } 3070 xfer->ux_status = USBD_IN_PROGRESS; 3071 /* The ux is already on the examined list, just leave it. */ 3072 } else { 3073 DPRINTFN(5, "removing", 0, 0, 0, 0); 3074 if (uhci_active_intr_info(ux)) 3075 uhci_del_intr_info(sc, ux); 3076 } 3077 } 3078 3079 /* Deallocate request data structures */ 3080 void 3081 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3082 { 3083 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3084 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3085 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3086 int len = UGETW(xfer->ux_request.wLength); 3087 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3088 3089 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3090 3091 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3092 3093 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3094 3095 if (!uhci_active_intr_info(ux)) 3096 return; 3097 3098 uhci_del_intr_info(sc, ux); /* remove from active list */ 3099 3100 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3101 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3102 else 3103 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3104 3105 if (upipe->ctrl.length != 0) 3106 uhci_free_std_chain(sc, ux->ux_stdstart->link.std, ux->ux_stdend); 3107 3108 if (len) { 3109 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3110 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3111 } 3112 usb_syncmem(&upipe->ctrl.reqdma, 0, 3113 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3114 3115 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3116 } 3117 3118 /* Deallocate request data structures */ 3119 void 3120 uhci_device_bulk_done(struct usbd_xfer *xfer) 3121 { 3122 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3123 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3124 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3125 3126 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3127 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3128 upipe); 3129 3130 KASSERT(mutex_owned(&sc->sc_lock)); 3131 3132 if (!uhci_active_intr_info(ux)) 3133 return; 3134 3135 uhci_del_intr_info(sc, ux); /* remove from active list */ 3136 3137 uhci_remove_bulk(sc, upipe->bulk.sqh); 3138 3139 uhci_free_std_chain(sc, ux->ux_stdstart, NULL); 3140 3141 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3142 } 3143 3144 /* Add interrupt QH, called with vflock. */ 3145 void 3146 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3147 { 3148 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3149 uhci_soft_qh_t *eqh; 3150 3151 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3152 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3153 3154 eqh = vf->eqh; 3155 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3156 sizeof(eqh->qh.qh_hlink), 3157 BUS_DMASYNC_POSTWRITE); 3158 sqh->hlink = eqh->hlink; 3159 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3160 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3161 sizeof(sqh->qh.qh_hlink), 3162 BUS_DMASYNC_PREWRITE); 3163 eqh->hlink = sqh; 3164 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3165 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3166 sizeof(eqh->qh.qh_hlink), 3167 BUS_DMASYNC_PREWRITE); 3168 vf->eqh = sqh; 3169 vf->bandwidth++; 3170 } 3171 3172 /* Remove interrupt QH. */ 3173 void 3174 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3175 { 3176 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3177 uhci_soft_qh_t *pqh; 3178 3179 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3180 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3181 3182 /* See comment in uhci_remove_ctrl() */ 3183 3184 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3185 sizeof(sqh->qh.qh_elink), 3186 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3187 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3188 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3189 usb_syncmem(&sqh->dma, 3190 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3191 sizeof(sqh->qh.qh_elink), 3192 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3193 delay(UHCI_QH_REMOVE_DELAY); 3194 } 3195 3196 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3197 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3198 sizeof(sqh->qh.qh_hlink), 3199 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3200 pqh->hlink = sqh->hlink; 3201 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3202 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3203 sizeof(pqh->qh.qh_hlink), 3204 BUS_DMASYNC_PREWRITE); 3205 delay(UHCI_QH_REMOVE_DELAY); 3206 if (vf->eqh == sqh) 3207 vf->eqh = pqh; 3208 vf->bandwidth--; 3209 } 3210 3211 usbd_status 3212 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3213 { 3214 uhci_soft_qh_t *sqh; 3215 int i, npoll; 3216 u_int bestbw, bw, bestoffs, offs; 3217 3218 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3219 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3220 if (ival == 0) { 3221 printf("uhci_device_setintr: 0 interval\n"); 3222 return USBD_INVAL; 3223 } 3224 3225 if (ival > UHCI_VFRAMELIST_COUNT) 3226 ival = UHCI_VFRAMELIST_COUNT; 3227 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3228 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3229 3230 upipe->intr.npoll = npoll; 3231 upipe->intr.qhs = 3232 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3233 if (upipe->intr.qhs == NULL) 3234 return USBD_NOMEM; 3235 3236 /* 3237 * Figure out which offset in the schedule that has most 3238 * bandwidth left over. 3239 */ 3240 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3241 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3242 for (bw = i = 0; i < npoll; i++) 3243 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3244 if (bw < bestbw) { 3245 bestbw = bw; 3246 bestoffs = offs; 3247 } 3248 } 3249 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3250 mutex_enter(&sc->sc_lock); 3251 for(i = 0; i < npoll; i++) { 3252 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3253 sqh->elink = NULL; 3254 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3255 usb_syncmem(&sqh->dma, 3256 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3257 sizeof(sqh->qh.qh_elink), 3258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3259 sqh->pos = MOD(i * ival + bestoffs); 3260 } 3261 #undef MOD 3262 3263 /* Enter QHs into the controller data structures. */ 3264 for(i = 0; i < npoll; i++) 3265 uhci_add_intr(sc, upipe->intr.qhs[i]); 3266 mutex_exit(&sc->sc_lock); 3267 3268 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3269 3270 return USBD_NORMAL_COMPLETION; 3271 } 3272 3273 /* Open a new pipe. */ 3274 usbd_status 3275 uhci_open(struct usbd_pipe *pipe) 3276 { 3277 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3278 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3279 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3280 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3281 usbd_status err = USBD_NOMEM; 3282 int ival; 3283 3284 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3285 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3286 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3287 3288 if (sc->sc_dying) 3289 return USBD_IOERROR; 3290 3291 upipe->aborting = 0; 3292 /* toggle state needed for bulk endpoints */ 3293 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3294 3295 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3296 switch (ed->bEndpointAddress) { 3297 case USB_CONTROL_ENDPOINT: 3298 pipe->up_methods = &roothub_ctrl_methods; 3299 break; 3300 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3301 pipe->up_methods = &uhci_root_intr_methods; 3302 break; 3303 default: 3304 return USBD_INVAL; 3305 } 3306 } else { 3307 switch (ed->bmAttributes & UE_XFERTYPE) { 3308 case UE_CONTROL: 3309 pipe->up_methods = &uhci_device_ctrl_methods; 3310 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3311 if (upipe->ctrl.sqh == NULL) 3312 goto bad; 3313 upipe->ctrl.setup = uhci_alloc_std(sc); 3314 if (upipe->ctrl.setup == NULL) { 3315 uhci_free_sqh(sc, upipe->ctrl.sqh); 3316 goto bad; 3317 } 3318 upipe->ctrl.stat = uhci_alloc_std(sc); 3319 if (upipe->ctrl.stat == NULL) { 3320 uhci_free_sqh(sc, upipe->ctrl.sqh); 3321 uhci_free_std(sc, upipe->ctrl.setup); 3322 goto bad; 3323 } 3324 err = usb_allocmem(&sc->sc_bus, 3325 sizeof(usb_device_request_t), 3326 0, &upipe->ctrl.reqdma); 3327 if (err) { 3328 uhci_free_sqh(sc, upipe->ctrl.sqh); 3329 uhci_free_std(sc, upipe->ctrl.setup); 3330 uhci_free_std(sc, upipe->ctrl.stat); 3331 goto bad; 3332 } 3333 break; 3334 case UE_INTERRUPT: 3335 pipe->up_methods = &uhci_device_intr_methods; 3336 ival = pipe->up_interval; 3337 if (ival == USBD_DEFAULT_INTERVAL) 3338 ival = ed->bInterval; 3339 return uhci_device_setintr(sc, upipe, ival); 3340 case UE_ISOCHRONOUS: 3341 pipe->up_methods = &uhci_device_isoc_methods; 3342 return uhci_setup_isoc(pipe); 3343 case UE_BULK: 3344 pipe->up_methods = &uhci_device_bulk_methods; 3345 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3346 if (upipe->bulk.sqh == NULL) 3347 goto bad; 3348 break; 3349 } 3350 } 3351 return USBD_NORMAL_COMPLETION; 3352 3353 bad: 3354 return USBD_NOMEM; 3355 } 3356 3357 /* 3358 * Data structures and routines to emulate the root hub. 3359 */ 3360 /* 3361 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3362 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3363 * should not be used by the USB subsystem. As we cannot issue a 3364 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3365 * will be enabled as part of the reset. 3366 * 3367 * On the VT83C572, the port cannot be successfully enabled until the 3368 * outstanding "port enable change" and "connection status change" 3369 * events have been reset. 3370 */ 3371 Static usbd_status 3372 uhci_portreset(uhci_softc_t *sc, int index) 3373 { 3374 int lim, port, x; 3375 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3376 3377 if (index == 1) 3378 port = UHCI_PORTSC1; 3379 else if (index == 2) 3380 port = UHCI_PORTSC2; 3381 else 3382 return USBD_IOERROR; 3383 3384 x = URWMASK(UREAD2(sc, port)); 3385 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3386 3387 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3388 3389 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3390 UREAD2(sc, port), 0, 0); 3391 3392 x = URWMASK(UREAD2(sc, port)); 3393 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3394 3395 delay(100); 3396 3397 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3398 UREAD2(sc, port), 0, 0); 3399 3400 x = URWMASK(UREAD2(sc, port)); 3401 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3402 3403 for (lim = 10; --lim > 0;) { 3404 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3405 3406 x = UREAD2(sc, port); 3407 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3408 lim, x, 0); 3409 3410 if (!(x & UHCI_PORTSC_CCS)) { 3411 /* 3412 * No device is connected (or was disconnected 3413 * during reset). Consider the port reset. 3414 * The delay must be long enough to ensure on 3415 * the initial iteration that the device 3416 * connection will have been registered. 50ms 3417 * appears to be sufficient, but 20ms is not. 3418 */ 3419 DPRINTFN(3, "uhci port %d loop %u, device detached", 3420 index, lim, 0, 0); 3421 break; 3422 } 3423 3424 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3425 /* 3426 * Port enabled changed and/or connection 3427 * status changed were set. Reset either or 3428 * both raised flags (by writing a 1 to that 3429 * bit), and wait again for state to settle. 3430 */ 3431 UWRITE2(sc, port, URWMASK(x) | 3432 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3433 continue; 3434 } 3435 3436 if (x & UHCI_PORTSC_PE) 3437 /* Port is enabled */ 3438 break; 3439 3440 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3441 } 3442 3443 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3444 UREAD2(sc, port), 0, 0); 3445 3446 if (lim <= 0) { 3447 DPRINTF("uhci port %d reset timed out", index, 3448 0, 0, 0); 3449 return USBD_TIMEOUT; 3450 } 3451 3452 sc->sc_isreset = 1; 3453 return USBD_NORMAL_COMPLETION; 3454 } 3455 3456 Static int 3457 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3458 void *buf, int buflen) 3459 { 3460 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3461 int port, x; 3462 int status, change, totlen = 0; 3463 uint16_t len, value, index; 3464 usb_port_status_t ps; 3465 usbd_status err; 3466 3467 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3468 3469 if (sc->sc_dying) 3470 return -1; 3471 3472 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3473 req->bRequest, 0, 0); 3474 3475 len = UGETW(req->wLength); 3476 value = UGETW(req->wValue); 3477 index = UGETW(req->wIndex); 3478 3479 #define C(x,y) ((x) | ((y) << 8)) 3480 switch (C(req->bRequest, req->bmRequestType)) { 3481 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3482 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3483 if (len == 0) 3484 break; 3485 switch (value) { 3486 case C(0, UDESC_DEVICE): { 3487 usb_device_descriptor_t devd; 3488 3489 totlen = min(buflen, sizeof(devd)); 3490 memcpy(&devd, buf, totlen); 3491 USETW(devd.idVendor, sc->sc_id_vendor); 3492 memcpy(buf, &devd, totlen); 3493 break; 3494 } 3495 case C(1, UDESC_STRING): 3496 #define sd ((usb_string_descriptor_t *)buf) 3497 /* Vendor */ 3498 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3499 break; 3500 case C(2, UDESC_STRING): 3501 /* Product */ 3502 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3503 break; 3504 #undef sd 3505 default: 3506 /* default from usbroothub */ 3507 return buflen; 3508 } 3509 break; 3510 3511 /* Hub requests */ 3512 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3513 break; 3514 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3515 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3516 value, 0, 0); 3517 if (index == 1) 3518 port = UHCI_PORTSC1; 3519 else if (index == 2) 3520 port = UHCI_PORTSC2; 3521 else { 3522 return -1; 3523 } 3524 switch(value) { 3525 case UHF_PORT_ENABLE: 3526 x = URWMASK(UREAD2(sc, port)); 3527 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3528 break; 3529 case UHF_PORT_SUSPEND: 3530 x = URWMASK(UREAD2(sc, port)); 3531 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3532 break; 3533 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3534 /* see USB2 spec ch. 7.1.7.7 */ 3535 usb_delay_ms(&sc->sc_bus, 20); 3536 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3537 /* 10ms resume delay must be provided by caller */ 3538 break; 3539 case UHF_PORT_RESET: 3540 x = URWMASK(UREAD2(sc, port)); 3541 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3542 break; 3543 case UHF_C_PORT_CONNECTION: 3544 x = URWMASK(UREAD2(sc, port)); 3545 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3546 break; 3547 case UHF_C_PORT_ENABLE: 3548 x = URWMASK(UREAD2(sc, port)); 3549 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3550 break; 3551 case UHF_C_PORT_OVER_CURRENT: 3552 x = URWMASK(UREAD2(sc, port)); 3553 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3554 break; 3555 case UHF_C_PORT_RESET: 3556 sc->sc_isreset = 0; 3557 break; 3558 case UHF_PORT_CONNECTION: 3559 case UHF_PORT_OVER_CURRENT: 3560 case UHF_PORT_POWER: 3561 case UHF_PORT_LOW_SPEED: 3562 case UHF_C_PORT_SUSPEND: 3563 default: 3564 return -1; 3565 } 3566 break; 3567 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3568 if (index == 1) 3569 port = UHCI_PORTSC1; 3570 else if (index == 2) 3571 port = UHCI_PORTSC2; 3572 else { 3573 return -1; 3574 } 3575 if (len > 0) { 3576 *(uint8_t *)buf = 3577 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3578 UHCI_PORTSC_LS_SHIFT; 3579 totlen = 1; 3580 } 3581 break; 3582 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3583 if (len == 0) 3584 break; 3585 if ((value & 0xff) != 0) { 3586 return -1; 3587 } 3588 usb_hub_descriptor_t hubd; 3589 3590 totlen = min(buflen, sizeof(hubd)); 3591 memcpy(&hubd, buf, totlen); 3592 hubd.bNbrPorts = 2; 3593 memcpy(buf, &hubd, totlen); 3594 break; 3595 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3596 if (len != 4) { 3597 return -1; 3598 } 3599 memset(buf, 0, len); 3600 totlen = len; 3601 break; 3602 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3603 if (index == 1) 3604 port = UHCI_PORTSC1; 3605 else if (index == 2) 3606 port = UHCI_PORTSC2; 3607 else { 3608 return -1; 3609 } 3610 if (len != 4) { 3611 return -1; 3612 } 3613 x = UREAD2(sc, port); 3614 status = change = 0; 3615 if (x & UHCI_PORTSC_CCS) 3616 status |= UPS_CURRENT_CONNECT_STATUS; 3617 if (x & UHCI_PORTSC_CSC) 3618 change |= UPS_C_CONNECT_STATUS; 3619 if (x & UHCI_PORTSC_PE) 3620 status |= UPS_PORT_ENABLED; 3621 if (x & UHCI_PORTSC_POEDC) 3622 change |= UPS_C_PORT_ENABLED; 3623 if (x & UHCI_PORTSC_OCI) 3624 status |= UPS_OVERCURRENT_INDICATOR; 3625 if (x & UHCI_PORTSC_OCIC) 3626 change |= UPS_C_OVERCURRENT_INDICATOR; 3627 if (x & UHCI_PORTSC_SUSP) 3628 status |= UPS_SUSPEND; 3629 if (x & UHCI_PORTSC_LSDA) 3630 status |= UPS_LOW_SPEED; 3631 status |= UPS_PORT_POWER; 3632 if (sc->sc_isreset) 3633 change |= UPS_C_PORT_RESET; 3634 USETW(ps.wPortStatus, status); 3635 USETW(ps.wPortChange, change); 3636 totlen = min(len, sizeof(ps)); 3637 memcpy(buf, &ps, totlen); 3638 break; 3639 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3640 return -1; 3641 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3642 break; 3643 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3644 if (index == 1) 3645 port = UHCI_PORTSC1; 3646 else if (index == 2) 3647 port = UHCI_PORTSC2; 3648 else { 3649 return -1; 3650 } 3651 switch(value) { 3652 case UHF_PORT_ENABLE: 3653 x = URWMASK(UREAD2(sc, port)); 3654 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3655 break; 3656 case UHF_PORT_SUSPEND: 3657 x = URWMASK(UREAD2(sc, port)); 3658 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3659 break; 3660 case UHF_PORT_RESET: 3661 err = uhci_portreset(sc, index); 3662 if (err != USBD_NORMAL_COMPLETION) 3663 return -1; 3664 return 0; 3665 case UHF_PORT_POWER: 3666 /* Pretend we turned on power */ 3667 return 0; 3668 case UHF_C_PORT_CONNECTION: 3669 case UHF_C_PORT_ENABLE: 3670 case UHF_C_PORT_OVER_CURRENT: 3671 case UHF_PORT_CONNECTION: 3672 case UHF_PORT_OVER_CURRENT: 3673 case UHF_PORT_LOW_SPEED: 3674 case UHF_C_PORT_SUSPEND: 3675 case UHF_C_PORT_RESET: 3676 default: 3677 return -1; 3678 } 3679 break; 3680 default: 3681 /* default from usbroothub */ 3682 DPRINTF("returning %d (usbroothub default)", 3683 buflen, 0, 0, 0); 3684 return buflen; 3685 } 3686 3687 DPRINTF("returning %d", totlen, 0, 0, 0); 3688 3689 return totlen; 3690 } 3691 3692 /* Abort a root interrupt request. */ 3693 void 3694 uhci_root_intr_abort(struct usbd_xfer *xfer) 3695 { 3696 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3697 3698 KASSERT(mutex_owned(&sc->sc_lock)); 3699 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3700 3701 callout_stop(&sc->sc_poll_handle); 3702 sc->sc_intr_xfer = NULL; 3703 3704 xfer->ux_status = USBD_CANCELLED; 3705 #ifdef DIAGNOSTIC 3706 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3707 #endif 3708 usb_transfer_complete(xfer); 3709 } 3710 3711 usbd_status 3712 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3713 { 3714 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3715 usbd_status err; 3716 3717 /* Insert last in queue. */ 3718 mutex_enter(&sc->sc_lock); 3719 err = usb_insert_transfer(xfer); 3720 mutex_exit(&sc->sc_lock); 3721 if (err) 3722 return err; 3723 3724 /* 3725 * Pipe isn't running (otherwise err would be USBD_INPROG), 3726 * start first 3727 */ 3728 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3729 } 3730 3731 /* Start a transfer on the root interrupt pipe */ 3732 usbd_status 3733 uhci_root_intr_start(struct usbd_xfer *xfer) 3734 { 3735 struct usbd_pipe *pipe = xfer->ux_pipe; 3736 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3737 unsigned int ival; 3738 3739 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3740 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3741 xfer->ux_flags, 0); 3742 3743 if (sc->sc_dying) 3744 return USBD_IOERROR; 3745 3746 /* XXX temporary variable needed to avoid gcc3 warning */ 3747 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3748 sc->sc_ival = mstohz(ival); 3749 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3750 sc->sc_intr_xfer = xfer; 3751 return USBD_IN_PROGRESS; 3752 } 3753 3754 /* Close the root interrupt pipe. */ 3755 void 3756 uhci_root_intr_close(struct usbd_pipe *pipe) 3757 { 3758 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3759 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3760 3761 KASSERT(mutex_owned(&sc->sc_lock)); 3762 3763 callout_stop(&sc->sc_poll_handle); 3764 sc->sc_intr_xfer = NULL; 3765 } 3766
Indexes created Tue Sep 30 20:09:53 GMT 2025