uhci.c revision 1.264.4.53
1 /* $NetBSD: uhci.c,v 1.264.4.53 2015/11/08 21:02:31 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.53 2015/11/08 21:02:31 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup, *stat; 143 u_int length; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 int isread; 149 uhci_soft_qh_t **qhs; 150 } intr; 151 /* Bulk pipe */ 152 struct { 153 uhci_soft_qh_t *sqh; 154 u_int length; 155 int isread; 156 } bulk; 157 /* Isochronous pipe */ 158 struct isoc { 159 uhci_soft_td_t **stds; 160 int next, inuse; 161 } isoc; 162 }; 163 }; 164 165 Static void uhci_globalreset(uhci_softc_t *); 166 Static usbd_status uhci_portreset(uhci_softc_t*, int); 167 Static void uhci_reset(uhci_softc_t *); 168 Static usbd_status uhci_run(uhci_softc_t *, int, int); 169 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 170 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, 180 uhci_soft_td_t *, uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(struct uhci_pipe *, 182 uhci_softc_t *, int, int, uint16_t, usb_dma_t *, 183 uhci_soft_td_t **, uhci_soft_td_t **); 184 Static void uhci_poll_hub(void *); 185 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 186 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *); 187 Static void uhci_idone(struct uhci_xfer *); 188 189 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 190 191 Static void uhci_timeout(void *); 192 Static void uhci_timeout_task(void *); 193 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 194 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 195 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 196 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 197 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 198 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 199 Static void uhci_add_loop(uhci_softc_t *); 200 Static void uhci_rem_loop(uhci_softc_t *); 201 202 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 203 Static void uhci_device_isoc_enter(struct usbd_xfer *); 204 205 Static struct usbd_xfer * 206 uhci_allocx(struct usbd_bus *, unsigned int); 207 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 208 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 209 Static int uhci_roothub_ctrl(struct usbd_bus *, 210 usb_device_request_t *, void *, int); 211 212 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 213 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 214 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 215 Static void uhci_device_ctrl_close(struct usbd_pipe *); 216 Static void uhci_device_ctrl_done(struct usbd_xfer *); 217 218 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 220 Static void uhci_device_intr_abort(struct usbd_xfer *); 221 Static void uhci_device_intr_close(struct usbd_pipe *); 222 Static void uhci_device_intr_done(struct usbd_xfer *); 223 224 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 225 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 226 Static void uhci_device_bulk_abort(struct usbd_xfer *); 227 Static void uhci_device_bulk_close(struct usbd_pipe *); 228 Static void uhci_device_bulk_done(struct usbd_xfer *); 229 230 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 231 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 232 Static void uhci_device_isoc_abort(struct usbd_xfer *); 233 Static void uhci_device_isoc_close(struct usbd_pipe *); 234 Static void uhci_device_isoc_done(struct usbd_xfer *); 235 236 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 238 Static void uhci_root_intr_abort(struct usbd_xfer *); 239 Static void uhci_root_intr_close(struct usbd_pipe *); 240 Static void uhci_root_intr_done(struct usbd_xfer *); 241 242 Static usbd_status uhci_open(struct usbd_pipe *); 243 Static void uhci_poll(struct usbd_bus *); 244 Static void uhci_softintr(void *); 245 246 Static usbd_status uhci_device_request(struct usbd_xfer *); 247 248 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 249 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 250 Static usbd_status uhci_device_setintr(uhci_softc_t *, 251 struct uhci_pipe *, int); 252 253 Static void uhci_device_clear_toggle(struct usbd_pipe *); 254 Static void uhci_noop(struct usbd_pipe *); 255 256 static inline uhci_soft_qh_t * 257 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 258 259 #ifdef UHCI_DEBUG 260 Static void uhci_dump_all(uhci_softc_t *); 261 Static void uhci_dumpregs(uhci_softc_t *); 262 Static void uhci_dump_qhs(uhci_soft_qh_t *); 263 Static void uhci_dump_qh(uhci_soft_qh_t *); 264 Static void uhci_dump_tds(uhci_soft_td_t *); 265 Static void uhci_dump_td(uhci_soft_td_t *); 266 Static void uhci_dump_ii(struct uhci_xfer *); 267 void uhci_dump(void); 268 #endif 269 270 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 271 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 272 #define UWRITE1(sc, r, x) \ 273 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 274 } while (/*CONSTCOND*/0) 275 #define UWRITE2(sc, r, x) \ 276 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 277 } while (/*CONSTCOND*/0) 278 #define UWRITE4(sc, r, x) \ 279 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 280 } while (/*CONSTCOND*/0) 281 282 static __inline uint8_t 283 UREAD1(uhci_softc_t *sc, bus_size_t r) 284 { 285 286 UBARR(sc); 287 return bus_space_read_1(sc->iot, sc->ioh, r); 288 } 289 290 static __inline uint16_t 291 UREAD2(uhci_softc_t *sc, bus_size_t r) 292 { 293 294 UBARR(sc); 295 return bus_space_read_2(sc->iot, sc->ioh, r); 296 } 297 298 #ifdef UHCI_DEBUG 299 static __inline uint32_t 300 UREAD4(uhci_softc_t *sc, bus_size_t r) 301 { 302 303 UBARR(sc); 304 return bus_space_read_4(sc->iot, sc->ioh, r); 305 } 306 #endif 307 308 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 309 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 310 311 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 312 313 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 314 315 const struct usbd_bus_methods uhci_bus_methods = { 316 .ubm_open = uhci_open, 317 .ubm_softint = uhci_softintr, 318 .ubm_dopoll = uhci_poll, 319 .ubm_allocx = uhci_allocx, 320 .ubm_freex = uhci_freex, 321 .ubm_getlock = uhci_get_lock, 322 .ubm_rhctrl = uhci_roothub_ctrl, 323 }; 324 325 const struct usbd_pipe_methods uhci_root_intr_methods = { 326 .upm_transfer = uhci_root_intr_transfer, 327 .upm_start = uhci_root_intr_start, 328 .upm_abort = uhci_root_intr_abort, 329 .upm_close = uhci_root_intr_close, 330 .upm_cleartoggle = uhci_noop, 331 .upm_done = uhci_root_intr_done, 332 }; 333 334 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 335 .upm_transfer = uhci_device_ctrl_transfer, 336 .upm_start = uhci_device_ctrl_start, 337 .upm_abort = uhci_device_ctrl_abort, 338 .upm_close = uhci_device_ctrl_close, 339 .upm_cleartoggle = uhci_noop, 340 .upm_done = uhci_device_ctrl_done, 341 }; 342 343 const struct usbd_pipe_methods uhci_device_intr_methods = { 344 .upm_transfer = uhci_device_intr_transfer, 345 .upm_start = uhci_device_intr_start, 346 .upm_abort = uhci_device_intr_abort, 347 .upm_close = uhci_device_intr_close, 348 .upm_cleartoggle = uhci_device_clear_toggle, 349 .upm_done = uhci_device_intr_done, 350 }; 351 352 const struct usbd_pipe_methods uhci_device_bulk_methods = { 353 .upm_transfer = uhci_device_bulk_transfer, 354 .upm_start = uhci_device_bulk_start, 355 .upm_abort = uhci_device_bulk_abort, 356 .upm_close = uhci_device_bulk_close, 357 .upm_cleartoggle = uhci_device_clear_toggle, 358 .upm_done = uhci_device_bulk_done, 359 }; 360 361 const struct usbd_pipe_methods uhci_device_isoc_methods = { 362 .upm_transfer = uhci_device_isoc_transfer, 363 .upm_start = uhci_device_isoc_start, 364 .upm_abort = uhci_device_isoc_abort, 365 .upm_close = uhci_device_isoc_close, 366 .upm_cleartoggle = uhci_noop, 367 .upm_done = uhci_device_isoc_done, 368 }; 369 370 #define uhci_add_intr_info(sc, ux) \ 371 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ux), ux_list) 372 #define uhci_del_intr_info(sc, ux) \ 373 do { \ 374 TAILQ_REMOVE(&(sc)->sc_intrhead, (ux), ux_list); \ 375 (ux)->ux_list.tqe_prev = NULL; \ 376 } while (0) 377 #define uhci_active_intr_info(ux) ((ux)->ux_list.tqe_prev != NULL) 378 379 static inline uhci_soft_qh_t * 380 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 381 { 382 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 383 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 384 385 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 386 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 387 usb_syncmem(&pqh->dma, 388 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 389 sizeof(pqh->qh.qh_hlink), 390 BUS_DMASYNC_POSTWRITE); 391 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 392 printf("uhci_find_prev_qh: QH not found\n"); 393 return NULL; 394 } 395 #endif 396 } 397 return pqh; 398 } 399 400 void 401 uhci_globalreset(uhci_softc_t *sc) 402 { 403 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 404 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 405 UHCICMD(sc, 0); /* do nothing */ 406 } 407 408 int 409 uhci_init(uhci_softc_t *sc) 410 { 411 usbd_status err; 412 int i, j; 413 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 414 uhci_soft_td_t *std; 415 416 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 417 418 #ifdef UHCI_DEBUG 419 thesc = sc; 420 421 if (uhcidebug >= 2) 422 uhci_dumpregs(sc); 423 #endif 424 425 sc->sc_suspend = PWR_RESUME; 426 427 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 428 uhci_globalreset(sc); /* reset the controller */ 429 uhci_reset(sc); 430 431 /* Allocate and initialize real frame array. */ 432 err = usb_allocmem(&sc->sc_bus, 433 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 434 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 435 if (err) 436 return err; 437 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 438 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 439 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 440 441 /* 442 * Allocate a TD, inactive, that hangs from the last QH. 443 * This is to avoid a bug in the PIIX that makes it run berserk 444 * otherwise. 445 */ 446 std = uhci_alloc_std(sc); 447 if (std == NULL) 448 return ENOMEM; 449 std->link.std = NULL; 450 std->td.td_link = htole32(UHCI_PTR_T); 451 std->td.td_status = htole32(0); /* inactive */ 452 std->td.td_token = htole32(0); 453 std->td.td_buffer = htole32(0); 454 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 456 457 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 458 lsqh = uhci_alloc_sqh(sc); 459 if (lsqh == NULL) 460 return ENOMEM; 461 lsqh->hlink = NULL; 462 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 463 lsqh->elink = std; 464 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 465 sc->sc_last_qh = lsqh; 466 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 468 469 /* Allocate the dummy QH where bulk traffic will be queued. */ 470 bsqh = uhci_alloc_sqh(sc); 471 if (bsqh == NULL) 472 return ENOMEM; 473 bsqh->hlink = lsqh; 474 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 475 bsqh->elink = NULL; 476 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 477 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 478 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 480 481 /* Allocate dummy QH where high speed control traffic will be queued. */ 482 chsqh = uhci_alloc_sqh(sc); 483 if (chsqh == NULL) 484 return ENOMEM; 485 chsqh->hlink = bsqh; 486 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 487 chsqh->elink = NULL; 488 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 489 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 490 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 492 493 /* Allocate dummy QH where control traffic will be queued. */ 494 clsqh = uhci_alloc_sqh(sc); 495 if (clsqh == NULL) 496 return ENOMEM; 497 clsqh->hlink = chsqh; 498 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 499 clsqh->elink = NULL; 500 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 501 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 502 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 504 505 /* 506 * Make all (virtual) frame list pointers point to the interrupt 507 * queue heads and the interrupt queue heads at the control 508 * queue head and point the physical frame list to the virtual. 509 */ 510 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 511 std = uhci_alloc_std(sc); 512 sqh = uhci_alloc_sqh(sc); 513 if (std == NULL || sqh == NULL) 514 return USBD_NOMEM; 515 std->link.sqh = sqh; 516 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 517 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 518 std->td.td_token = htole32(0); 519 std->td.td_buffer = htole32(0); 520 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 521 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 522 sqh->hlink = clsqh; 523 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 524 sqh->elink = NULL; 525 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 526 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 528 sc->sc_vframes[i].htd = std; 529 sc->sc_vframes[i].etd = std; 530 sc->sc_vframes[i].hqh = sqh; 531 sc->sc_vframes[i].eqh = sqh; 532 for (j = i; 533 j < UHCI_FRAMELIST_COUNT; 534 j += UHCI_VFRAMELIST_COUNT) 535 sc->sc_pframes[j] = htole32(std->physaddr); 536 } 537 usb_syncmem(&sc->sc_dma, 0, 538 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 539 BUS_DMASYNC_PREWRITE); 540 541 542 TAILQ_INIT(&sc->sc_intrhead); 543 544 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 545 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 546 547 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 548 549 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 550 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 551 cv_init(&sc->sc_softwake_cv, "uhciab"); 552 553 /* Set up the bus struct. */ 554 sc->sc_bus.ub_methods = &uhci_bus_methods; 555 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 556 sc->sc_bus.ub_usedma = true; 557 558 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 559 560 DPRINTF("Enabling...", 0, 0, 0, 0); 561 562 err = uhci_run(sc, 1, 0); /* and here we go... */ 563 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 564 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 565 return err; 566 } 567 568 int 569 uhci_activate(device_t self, enum devact act) 570 { 571 struct uhci_softc *sc = device_private(self); 572 573 switch (act) { 574 case DVACT_DEACTIVATE: 575 sc->sc_dying = 1; 576 return 0; 577 default: 578 return EOPNOTSUPP; 579 } 580 } 581 582 void 583 uhci_childdet(device_t self, device_t child) 584 { 585 struct uhci_softc *sc = device_private(self); 586 587 KASSERT(sc->sc_child == child); 588 sc->sc_child = NULL; 589 } 590 591 int 592 uhci_detach(struct uhci_softc *sc, int flags) 593 { 594 int rv = 0; 595 596 if (sc->sc_child != NULL) 597 rv = config_detach(sc->sc_child, flags); 598 599 if (rv != 0) 600 return rv; 601 602 callout_halt(&sc->sc_poll_handle, NULL); 603 callout_destroy(&sc->sc_poll_handle); 604 605 cv_destroy(&sc->sc_softwake_cv); 606 607 mutex_destroy(&sc->sc_lock); 608 mutex_destroy(&sc->sc_intr_lock); 609 610 pool_cache_destroy(sc->sc_xferpool); 611 612 /* XXX free other data structures XXX */ 613 614 return rv; 615 } 616 617 struct usbd_xfer * 618 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 619 { 620 struct uhci_softc *sc = UHCI_BUS2SC(bus); 621 struct usbd_xfer *xfer; 622 623 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 624 if (xfer != NULL) { 625 memset(xfer, 0, sizeof(struct uhci_xfer)); 626 627 #ifdef DIAGNOSTIC 628 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 629 uxfer->ux_isdone = true; 630 xfer->ux_state = XFER_BUSY; 631 #endif 632 } 633 return xfer; 634 } 635 636 void 637 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 638 { 639 struct uhci_softc *sc = UHCI_BUS2SC(bus); 640 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 641 642 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 643 xfer->ux_state); 644 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 645 #ifdef DIAGNOSTIC 646 xfer->ux_state = XFER_FREE; 647 #endif 648 pool_cache_put(sc->sc_xferpool, xfer); 649 } 650 651 Static void 652 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 653 { 654 struct uhci_softc *sc = UHCI_BUS2SC(bus); 655 656 *lock = &sc->sc_lock; 657 } 658 659 660 /* 661 * Handle suspend/resume. 662 * 663 * We need to switch to polling mode here, because this routine is 664 * called from an interrupt context. This is all right since we 665 * are almost suspended anyway. 666 */ 667 bool 668 uhci_resume(device_t dv, const pmf_qual_t *qual) 669 { 670 uhci_softc_t *sc = device_private(dv); 671 int cmd; 672 673 mutex_spin_enter(&sc->sc_intr_lock); 674 675 cmd = UREAD2(sc, UHCI_CMD); 676 sc->sc_bus.ub_usepolling++; 677 UWRITE2(sc, UHCI_INTR, 0); 678 uhci_globalreset(sc); 679 uhci_reset(sc); 680 if (cmd & UHCI_CMD_RS) 681 uhci_run(sc, 0, 1); 682 683 /* restore saved state */ 684 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 685 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 686 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 687 688 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 689 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 690 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 691 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 692 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 693 UHCICMD(sc, UHCI_CMD_MAXP); 694 uhci_run(sc, 1, 1); /* and start traffic again */ 695 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 696 sc->sc_bus.ub_usepolling--; 697 if (sc->sc_intr_xfer != NULL) 698 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 699 sc->sc_intr_xfer); 700 #ifdef UHCI_DEBUG 701 if (uhcidebug >= 2) 702 uhci_dumpregs(sc); 703 #endif 704 705 sc->sc_suspend = PWR_RESUME; 706 mutex_spin_exit(&sc->sc_intr_lock); 707 708 return true; 709 } 710 711 bool 712 uhci_suspend(device_t dv, const pmf_qual_t *qual) 713 { 714 uhci_softc_t *sc = device_private(dv); 715 int cmd; 716 717 mutex_spin_enter(&sc->sc_intr_lock); 718 719 cmd = UREAD2(sc, UHCI_CMD); 720 721 #ifdef UHCI_DEBUG 722 if (uhcidebug >= 2) 723 uhci_dumpregs(sc); 724 #endif 725 if (sc->sc_intr_xfer != NULL) 726 callout_stop(&sc->sc_poll_handle); 727 sc->sc_suspend = PWR_SUSPEND; 728 sc->sc_bus.ub_usepolling++; 729 730 uhci_run(sc, 0, 1); /* stop the controller */ 731 cmd &= ~UHCI_CMD_RS; 732 733 /* save some state if BIOS doesn't */ 734 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 735 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 736 737 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 738 739 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 740 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 741 sc->sc_bus.ub_usepolling--; 742 743 mutex_spin_exit(&sc->sc_intr_lock); 744 745 return true; 746 } 747 748 #ifdef UHCI_DEBUG 749 Static void 750 uhci_dumpregs(uhci_softc_t *sc) 751 { 752 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 753 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 754 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 755 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 756 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 757 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 758 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 759 } 760 761 void 762 uhci_dump_td(uhci_soft_td_t *p) 763 { 764 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 765 766 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 768 769 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 770 DPRINTF(" link=0x%08x status=0x%08x " 771 "token=0x%08x buffer=0x%08x", 772 le32toh(p->td.td_link), 773 le32toh(p->td.td_status), 774 le32toh(p->td.td_token), 775 le32toh(p->td.td_buffer)); 776 777 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 778 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 779 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 780 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 781 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 782 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 783 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 784 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 785 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 786 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 787 DPRINTF("ios =%d ls =%d spd =%d", 788 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 789 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 790 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 791 DPRINTF("errcnt =%d actlen =%d pid=%02x", 792 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 793 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 794 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 795 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 796 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 797 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 798 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 799 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 800 } 801 802 void 803 uhci_dump_qh(uhci_soft_qh_t *sqh) 804 { 805 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 806 807 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 808 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 809 810 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 811 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 812 le32toh(sqh->qh.qh_elink)); 813 814 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 815 } 816 817 818 #if 1 819 void 820 uhci_dump(void) 821 { 822 uhci_dump_all(thesc); 823 } 824 #endif 825 826 void 827 uhci_dump_all(uhci_softc_t *sc) 828 { 829 uhci_dumpregs(sc); 830 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 831 uhci_dump_qhs(sc->sc_lctl_start); 832 } 833 834 835 void 836 uhci_dump_qhs(uhci_soft_qh_t *sqh) 837 { 838 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 839 840 uhci_dump_qh(sqh); 841 842 /* 843 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 844 * Traverses sideways first, then down. 845 * 846 * QH1 847 * QH2 848 * No QH 849 * TD2.1 850 * TD2.2 851 * TD1.1 852 * etc. 853 * 854 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 855 */ 856 857 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 858 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 859 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 860 uhci_dump_qhs(sqh->hlink); 861 else 862 DPRINTF("No QH", 0, 0, 0, 0); 863 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 864 865 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 866 uhci_dump_tds(sqh->elink); 867 else 868 DPRINTF("No QH", 0, 0, 0, 0); 869 } 870 871 void 872 uhci_dump_tds(uhci_soft_td_t *std) 873 { 874 uhci_soft_td_t *td; 875 int stop; 876 877 for (td = std; td != NULL; td = td->link.std) { 878 uhci_dump_td(td); 879 880 /* 881 * Check whether the link pointer in this TD marks 882 * the link pointer as end of queue. This avoids 883 * printing the free list in case the queue/TD has 884 * already been moved there (seatbelt). 885 */ 886 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 887 sizeof(td->td.td_link), 888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 889 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 890 le32toh(td->td.td_link) == 0); 891 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 892 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 893 if (stop) 894 break; 895 } 896 } 897 898 Static void 899 uhci_dump_ii(struct uhci_xfer *ux) 900 { 901 struct usbd_pipe *pipe; 902 usb_endpoint_descriptor_t *ed; 903 struct usbd_device *dev; 904 905 if (ux == NULL) { 906 printf("ux NULL\n"); 907 return; 908 } 909 pipe = ux->ux_xfer.ux_pipe; 910 if (pipe == NULL) { 911 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 912 return; 913 } 914 if (pipe->up_endpoint == NULL) { 915 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 916 ux, ux->ux_isdone, pipe); 917 return; 918 } 919 if (pipe->up_dev == NULL) { 920 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 921 ux, ux->ux_isdone, pipe); 922 return; 923 } 924 ed = pipe->up_endpoint->ue_edesc; 925 dev = pipe->up_dev; 926 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 927 ux, ux->ux_isdone, dev, 928 UGETW(dev->ud_ddesc.idVendor), 929 UGETW(dev->ud_ddesc.idProduct), 930 dev->ud_addr, pipe, 931 ed->bEndpointAddress, ed->bmAttributes); 932 } 933 934 void uhci_dump_iis(struct uhci_softc *sc); 935 void 936 uhci_dump_iis(struct uhci_softc *sc) 937 { 938 struct uhci_xfer *ux; 939 940 printf("interrupt list:\n"); 941 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = TAILQ_NEXT(ux, ux_list)) 942 uhci_dump_ii(ux); 943 } 944 945 void iidump(void); 946 void iidump(void) { uhci_dump_iis(thesc); } 947 948 #endif 949 950 /* 951 * This routine is executed periodically and simulates interrupts 952 * from the root controller interrupt pipe for port status change. 953 */ 954 void 955 uhci_poll_hub(void *addr) 956 { 957 struct usbd_xfer *xfer = addr; 958 struct usbd_pipe *pipe = xfer->ux_pipe; 959 uhci_softc_t *sc; 960 u_char *p; 961 962 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 963 964 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 965 return; /* device has detached */ 966 sc = UHCI_PIPE2SC(pipe); 967 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 968 969 p = xfer->ux_buf; 970 p[0] = 0; 971 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 972 p[0] |= 1<<1; 973 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 974 p[0] |= 1<<2; 975 if (p[0] == 0) 976 /* No change, try again in a while */ 977 return; 978 979 xfer->ux_actlen = 1; 980 xfer->ux_status = USBD_NORMAL_COMPLETION; 981 mutex_enter(&sc->sc_lock); 982 usb_transfer_complete(xfer); 983 mutex_exit(&sc->sc_lock); 984 } 985 986 void 987 uhci_root_intr_done(struct usbd_xfer *xfer) 988 { 989 } 990 991 /* 992 * Let the last QH loop back to the high speed control transfer QH. 993 * This is what intel calls "bandwidth reclamation" and improves 994 * USB performance a lot for some devices. 995 * If we are already looping, just count it. 996 */ 997 void 998 uhci_add_loop(uhci_softc_t *sc) 999 { 1000 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1001 1002 #ifdef UHCI_DEBUG 1003 if (uhcinoloop) 1004 return; 1005 #endif 1006 if (++sc->sc_loops == 1) { 1007 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1008 /* Note, we don't loop back the soft pointer. */ 1009 sc->sc_last_qh->qh.qh_hlink = 1010 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1011 usb_syncmem(&sc->sc_last_qh->dma, 1012 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1013 sizeof(sc->sc_last_qh->qh.qh_hlink), 1014 BUS_DMASYNC_PREWRITE); 1015 } 1016 } 1017 1018 void 1019 uhci_rem_loop(uhci_softc_t *sc) 1020 { 1021 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1022 1023 #ifdef UHCI_DEBUG 1024 if (uhcinoloop) 1025 return; 1026 #endif 1027 if (--sc->sc_loops == 0) { 1028 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1029 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1030 usb_syncmem(&sc->sc_last_qh->dma, 1031 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1032 sizeof(sc->sc_last_qh->qh.qh_hlink), 1033 BUS_DMASYNC_PREWRITE); 1034 } 1035 } 1036 1037 /* Add high speed control QH, called with lock held. */ 1038 void 1039 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1040 { 1041 uhci_soft_qh_t *eqh; 1042 1043 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1044 1045 KASSERT(mutex_owned(&sc->sc_lock)); 1046 1047 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1048 eqh = sc->sc_hctl_end; 1049 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1050 sizeof(eqh->qh.qh_hlink), 1051 BUS_DMASYNC_POSTWRITE); 1052 sqh->hlink = eqh->hlink; 1053 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1054 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1055 BUS_DMASYNC_PREWRITE); 1056 eqh->hlink = sqh; 1057 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1058 sc->sc_hctl_end = sqh; 1059 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1060 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1061 #ifdef UHCI_CTL_LOOP 1062 uhci_add_loop(sc); 1063 #endif 1064 } 1065 1066 /* Remove high speed control QH, called with lock held. */ 1067 void 1068 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1069 { 1070 uhci_soft_qh_t *pqh; 1071 uint32_t elink; 1072 1073 KASSERT(mutex_owned(&sc->sc_lock)); 1074 1075 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1076 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1077 #ifdef UHCI_CTL_LOOP 1078 uhci_rem_loop(sc); 1079 #endif 1080 /* 1081 * The T bit should be set in the elink of the QH so that the HC 1082 * doesn't follow the pointer. This condition may fail if the 1083 * the transferred packet was short so that the QH still points 1084 * at the last used TD. 1085 * In this case we set the T bit and wait a little for the HC 1086 * to stop looking at the TD. 1087 * Note that if the TD chain is large enough, the controller 1088 * may still be looking at the chain at the end of this function. 1089 * uhci_free_std_chain() will make sure the controller stops 1090 * looking at it quickly, but until then we should not change 1091 * sqh->hlink. 1092 */ 1093 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1094 sizeof(sqh->qh.qh_elink), 1095 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1096 elink = le32toh(sqh->qh.qh_elink); 1097 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1098 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1099 if (!(elink & UHCI_PTR_T)) { 1100 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1101 usb_syncmem(&sqh->dma, 1102 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1103 sizeof(sqh->qh.qh_elink), 1104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1105 delay(UHCI_QH_REMOVE_DELAY); 1106 } 1107 1108 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1109 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1110 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1111 pqh->hlink = sqh->hlink; 1112 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1113 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1114 sizeof(pqh->qh.qh_hlink), 1115 BUS_DMASYNC_PREWRITE); 1116 delay(UHCI_QH_REMOVE_DELAY); 1117 if (sc->sc_hctl_end == sqh) 1118 sc->sc_hctl_end = pqh; 1119 } 1120 1121 /* Add low speed control QH, called with lock held. */ 1122 void 1123 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1124 { 1125 uhci_soft_qh_t *eqh; 1126 1127 KASSERT(mutex_owned(&sc->sc_lock)); 1128 1129 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1130 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1131 1132 eqh = sc->sc_lctl_end; 1133 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1134 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1135 sqh->hlink = eqh->hlink; 1136 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1137 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1138 BUS_DMASYNC_PREWRITE); 1139 eqh->hlink = sqh; 1140 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1141 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1142 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1143 sc->sc_lctl_end = sqh; 1144 } 1145 1146 /* Remove low speed control QH, called with lock held. */ 1147 void 1148 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1149 { 1150 uhci_soft_qh_t *pqh; 1151 uint32_t elink; 1152 1153 KASSERT(mutex_owned(&sc->sc_lock)); 1154 1155 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1156 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1157 1158 /* See comment in uhci_remove_hs_ctrl() */ 1159 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1160 sizeof(sqh->qh.qh_elink), 1161 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1162 elink = le32toh(sqh->qh.qh_elink); 1163 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1164 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1165 if (!(elink & UHCI_PTR_T)) { 1166 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1167 usb_syncmem(&sqh->dma, 1168 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1169 sizeof(sqh->qh.qh_elink), 1170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1171 delay(UHCI_QH_REMOVE_DELAY); 1172 } 1173 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1174 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1175 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1176 pqh->hlink = sqh->hlink; 1177 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1178 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1179 sizeof(pqh->qh.qh_hlink), 1180 BUS_DMASYNC_PREWRITE); 1181 delay(UHCI_QH_REMOVE_DELAY); 1182 if (sc->sc_lctl_end == sqh) 1183 sc->sc_lctl_end = pqh; 1184 } 1185 1186 /* Add bulk QH, called with lock held. */ 1187 void 1188 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1189 { 1190 uhci_soft_qh_t *eqh; 1191 1192 KASSERT(mutex_owned(&sc->sc_lock)); 1193 1194 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1195 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1196 1197 eqh = sc->sc_bulk_end; 1198 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1199 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1200 sqh->hlink = eqh->hlink; 1201 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1202 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1203 BUS_DMASYNC_PREWRITE); 1204 eqh->hlink = sqh; 1205 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1206 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1207 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1208 sc->sc_bulk_end = sqh; 1209 uhci_add_loop(sc); 1210 } 1211 1212 /* Remove bulk QH, called with lock held. */ 1213 void 1214 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1215 { 1216 uhci_soft_qh_t *pqh; 1217 1218 KASSERT(mutex_owned(&sc->sc_lock)); 1219 1220 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1221 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1222 1223 uhci_rem_loop(sc); 1224 /* See comment in uhci_remove_hs_ctrl() */ 1225 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1226 sizeof(sqh->qh.qh_elink), 1227 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1228 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1229 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1230 usb_syncmem(&sqh->dma, 1231 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1232 sizeof(sqh->qh.qh_elink), 1233 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1234 delay(UHCI_QH_REMOVE_DELAY); 1235 } 1236 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1237 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1238 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1239 pqh->hlink = sqh->hlink; 1240 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1241 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1242 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1243 delay(UHCI_QH_REMOVE_DELAY); 1244 if (sc->sc_bulk_end == sqh) 1245 sc->sc_bulk_end = pqh; 1246 } 1247 1248 Static int uhci_intr1(uhci_softc_t *); 1249 1250 int 1251 uhci_intr(void *arg) 1252 { 1253 uhci_softc_t *sc = arg; 1254 int ret = 0; 1255 1256 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 1260 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1261 goto done; 1262 1263 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1264 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1265 goto done; 1266 } 1267 1268 ret = uhci_intr1(sc); 1269 1270 done: 1271 mutex_spin_exit(&sc->sc_intr_lock); 1272 return ret; 1273 } 1274 1275 int 1276 uhci_intr1(uhci_softc_t *sc) 1277 { 1278 int status; 1279 int ack; 1280 1281 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1282 1283 #ifdef UHCI_DEBUG 1284 if (uhcidebug >= 15) { 1285 DPRINTF("sc %p", sc, 0, 0, 0); 1286 uhci_dumpregs(sc); 1287 } 1288 #endif 1289 1290 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1291 1292 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1293 if (status == 0) /* The interrupt was not for us. */ 1294 return 0; 1295 1296 if (sc->sc_suspend != PWR_RESUME) { 1297 #ifdef DIAGNOSTIC 1298 printf("%s: interrupt while not operating ignored\n", 1299 device_xname(sc->sc_dev)); 1300 #endif 1301 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1302 return 0; 1303 } 1304 1305 ack = 0; 1306 if (status & UHCI_STS_USBINT) 1307 ack |= UHCI_STS_USBINT; 1308 if (status & UHCI_STS_USBEI) 1309 ack |= UHCI_STS_USBEI; 1310 if (status & UHCI_STS_RD) { 1311 ack |= UHCI_STS_RD; 1312 #ifdef UHCI_DEBUG 1313 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1314 #endif 1315 } 1316 if (status & UHCI_STS_HSE) { 1317 ack |= UHCI_STS_HSE; 1318 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1319 } 1320 if (status & UHCI_STS_HCPE) { 1321 ack |= UHCI_STS_HCPE; 1322 printf("%s: host controller process error\n", 1323 device_xname(sc->sc_dev)); 1324 } 1325 1326 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1327 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1328 /* no acknowledge needed */ 1329 if (!sc->sc_dying) { 1330 printf("%s: host controller halted\n", 1331 device_xname(sc->sc_dev)); 1332 #ifdef UHCI_DEBUG 1333 uhci_dump_all(sc); 1334 #endif 1335 } 1336 sc->sc_dying = 1; 1337 } 1338 1339 if (!ack) 1340 return 0; /* nothing to acknowledge */ 1341 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1342 1343 usb_schedsoftintr(&sc->sc_bus); 1344 1345 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1346 1347 return 1; 1348 } 1349 1350 void 1351 uhci_softintr(void *v) 1352 { 1353 struct usbd_bus *bus = v; 1354 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1355 struct uhci_xfer *ux, *nextux; 1356 1357 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1358 DPRINTF("sc %p", sc, 0, 0, 0); 1359 1360 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1361 1362 /* 1363 * Interrupts on UHCI really suck. When the host controller 1364 * interrupts because a transfer is completed there is no 1365 * way of knowing which transfer it was. You can scan down 1366 * the TDs and QHs of the previous frame to limit the search, 1367 * but that assumes that the interrupt was not delayed by more 1368 * than 1 ms, which may not always be true (e.g. after debug 1369 * output on a slow console). 1370 * We scan all interrupt descriptors to see if any have 1371 * completed. 1372 */ 1373 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux; ux = nextux) { 1374 nextux = TAILQ_NEXT(ux, ux_list); 1375 uhci_check_intr(sc, ux); 1376 } 1377 1378 if (sc->sc_softwake) { 1379 sc->sc_softwake = 0; 1380 cv_broadcast(&sc->sc_softwake_cv); 1381 } 1382 } 1383 1384 /* Check for an interrupt. */ 1385 void 1386 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux) 1387 { 1388 uhci_soft_td_t *std, *lstd; 1389 uint32_t status; 1390 1391 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1392 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1393 1394 KASSERT(ux != NULL); 1395 1396 struct usbd_xfer *xfer = &ux->ux_xfer; 1397 if (xfer->ux_status == USBD_CANCELLED || 1398 xfer->ux_status == USBD_TIMEOUT) { 1399 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1400 return; 1401 } 1402 1403 if (ux->ux_stdstart == NULL) 1404 return; 1405 lstd = ux->ux_stdend; 1406 1407 KASSERT(lstd != NULL); 1408 1409 usb_syncmem(&lstd->dma, 1410 lstd->offs + offsetof(uhci_td_t, td_status), 1411 sizeof(lstd->td.td_status), 1412 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1413 status = le32toh(lstd->td.td_status); 1414 usb_syncmem(&lstd->dma, 1415 lstd->offs + offsetof(uhci_td_t, td_status), 1416 sizeof(lstd->td.td_status), 1417 BUS_DMASYNC_PREREAD); 1418 1419 /* If the last TD is not marked active we can complete */ 1420 if (!(status & UHCI_TD_ACTIVE)) { 1421 done: 1422 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1423 1424 callout_stop(&xfer->ux_callout); 1425 uhci_idone(ux); 1426 return; 1427 } 1428 1429 /* 1430 * If the last TD is still active we need to check whether there 1431 * is an error somewhere in the middle, or whether there was a 1432 * short packet (SPD and not ACTIVE). 1433 */ 1434 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1435 for (std = ux->ux_stdstart; std != lstd; std = std->link.std) { 1436 usb_syncmem(&std->dma, 1437 std->offs + offsetof(uhci_td_t, td_status), 1438 sizeof(std->td.td_status), 1439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1440 status = le32toh(std->td.td_status); 1441 usb_syncmem(&std->dma, 1442 std->offs + offsetof(uhci_td_t, td_status), 1443 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1444 1445 /* If there's an active TD the xfer isn't done. */ 1446 if (status & UHCI_TD_ACTIVE) { 1447 DPRINTFN(12, "ux=%p std=%p still active", 1448 ux, std, 0, 0); 1449 return; 1450 } 1451 1452 /* Any kind of error makes the xfer done. */ 1453 if (status & UHCI_TD_STALLED) 1454 goto done; 1455 1456 /* 1457 * If the data phase of a control transfer is short, we need 1458 * to complete the status stage 1459 */ 1460 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 1461 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1462 1463 if ((status & UHCI_TD_SPD) && xfertype == UE_CONTROL) { 1464 struct uhci_pipe *upipe = 1465 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1466 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1467 uhci_soft_td_t *stat = upipe->ctrl.stat; 1468 1469 DPRINTFN(12, "ux=%p std=%p control status" 1470 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1471 1472 sqh->qh.qh_elink = 1473 htole32(stat->physaddr | UHCI_PTR_TD); 1474 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1475 BUS_DMASYNC_PREWRITE); 1476 break; 1477 } 1478 1479 /* We want short packets, and it is short: it's done */ 1480 usb_syncmem(&std->dma, 1481 std->offs + offsetof(uhci_td_t, td_token), 1482 sizeof(std->td.td_token), 1483 BUS_DMASYNC_POSTWRITE); 1484 1485 if ((status & UHCI_TD_SPD) && 1486 UHCI_TD_GET_ACTLEN(status) < 1487 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1488 goto done; 1489 } 1490 } 1491 } 1492 1493 /* Called with USB lock held. */ 1494 void 1495 uhci_idone(struct uhci_xfer *ux) 1496 { 1497 struct usbd_xfer *xfer = &ux->ux_xfer; 1498 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1499 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1500 uhci_soft_td_t *std; 1501 uint32_t status = 0, nstatus; 1502 int actlen; 1503 1504 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1505 1506 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1507 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1508 1509 #ifdef DIAGNOSTIC 1510 #ifdef UHCI_DEBUG 1511 if (ux->ux_isdone) { 1512 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1513 uhci_dump_ii(ux); 1514 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1515 } 1516 #endif 1517 KASSERT(!ux->ux_isdone); 1518 ux->ux_isdone = true; 1519 #endif 1520 1521 if (xfer->ux_nframes != 0) { 1522 /* Isoc transfer, do things differently. */ 1523 uhci_soft_td_t **stds = upipe->isoc.stds; 1524 int i, n, nframes, len; 1525 1526 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1527 1528 nframes = xfer->ux_nframes; 1529 actlen = 0; 1530 n = UHCI_XFER2UXFER(xfer)->ux_curframe; 1531 for (i = 0; i < nframes; i++) { 1532 std = stds[n]; 1533 #ifdef UHCI_DEBUG 1534 if (uhcidebug >= 5) { 1535 DPRINTF("isoc TD %d", i, 0, 0, 0); 1536 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1537 uhci_dump_td(std); 1538 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1539 } 1540 #endif 1541 if (++n >= UHCI_VFRAMELIST_COUNT) 1542 n = 0; 1543 usb_syncmem(&std->dma, 1544 std->offs + offsetof(uhci_td_t, td_status), 1545 sizeof(std->td.td_status), 1546 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1547 status = le32toh(std->td.td_status); 1548 len = UHCI_TD_GET_ACTLEN(status); 1549 xfer->ux_frlengths[i] = len; 1550 actlen += len; 1551 } 1552 upipe->isoc.inuse -= nframes; 1553 xfer->ux_actlen = actlen; 1554 xfer->ux_status = USBD_NORMAL_COMPLETION; 1555 goto end; 1556 } 1557 1558 #ifdef UHCI_DEBUG 1559 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1560 if (uhcidebug >= 10) { 1561 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1562 uhci_dump_tds(ux->ux_stdstart); 1563 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1564 } 1565 #endif 1566 1567 /* The transfer is done, compute actual length and status. */ 1568 actlen = 0; 1569 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1570 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1571 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1572 nstatus = le32toh(std->td.td_status); 1573 if (nstatus & UHCI_TD_ACTIVE) 1574 break; 1575 1576 status = nstatus; 1577 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1578 UHCI_TD_PID_SETUP) 1579 actlen += UHCI_TD_GET_ACTLEN(status); 1580 else { 1581 /* 1582 * UHCI will report CRCTO in addition to a STALL or NAK 1583 * for a SETUP transaction. See section 3.2.2, "TD 1584 * CONTROL AND STATUS". 1585 */ 1586 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1587 status &= ~UHCI_TD_CRCTO; 1588 } 1589 } 1590 /* If there are left over TDs we need to update the toggle. */ 1591 if (std != NULL) 1592 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1593 1594 status &= UHCI_TD_ERROR; 1595 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1596 xfer->ux_actlen = actlen; 1597 if (status != 0) { 1598 1599 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1600 "error, addr=%d, endpt=0x%02x", 1601 xfer->ux_pipe->up_dev->ud_addr, 1602 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1603 0, 0); 1604 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1605 "bitstuff=%d crcto =%d nak =%d babble =%d", 1606 !!(status & UHCI_TD_BITSTUFF), 1607 !!(status & UHCI_TD_CRCTO), 1608 !!(status & UHCI_TD_NAK), 1609 !!(status & UHCI_TD_BABBLE)); 1610 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1611 "dbuffer =%d stalled =%d active =%d", 1612 !!(status & UHCI_TD_DBUFFER), 1613 !!(status & UHCI_TD_STALLED), 1614 !!(status & UHCI_TD_ACTIVE), 1615 0); 1616 1617 if (status == UHCI_TD_STALLED) 1618 xfer->ux_status = USBD_STALLED; 1619 else 1620 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1621 } else { 1622 xfer->ux_status = USBD_NORMAL_COMPLETION; 1623 } 1624 1625 end: 1626 usb_transfer_complete(xfer); 1627 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1628 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1629 } 1630 1631 /* 1632 * Called when a request does not complete. 1633 */ 1634 void 1635 uhci_timeout(void *addr) 1636 { 1637 struct usbd_xfer *xfer = addr; 1638 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1639 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1640 1641 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1642 1643 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1644 1645 if (sc->sc_dying) { 1646 mutex_enter(&sc->sc_lock); 1647 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1648 mutex_exit(&sc->sc_lock); 1649 return; 1650 } 1651 1652 /* Execute the abort in a process context. */ 1653 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1654 USB_TASKQ_MPSAFE); 1655 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1656 USB_TASKQ_HC); 1657 } 1658 1659 void 1660 uhci_timeout_task(void *addr) 1661 { 1662 struct usbd_xfer *xfer = addr; 1663 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1664 1665 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1666 1667 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1668 1669 mutex_enter(&sc->sc_lock); 1670 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1671 mutex_exit(&sc->sc_lock); 1672 } 1673 1674 /* 1675 * Wait here until controller claims to have an interrupt. 1676 * Then call uhci_intr and return. Use timeout to avoid waiting 1677 * too long. 1678 * Only used during boot when interrupts are not enabled yet. 1679 */ 1680 void 1681 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1682 { 1683 int timo = xfer->ux_timeout; 1684 struct uhci_xfer *ux; 1685 1686 mutex_enter(&sc->sc_lock); 1687 1688 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1689 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1690 1691 xfer->ux_status = USBD_IN_PROGRESS; 1692 for (; timo >= 0; timo--) { 1693 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1694 DPRINTFN(20, "0x%04x", 1695 UREAD2(sc, UHCI_STS), 0, 0, 0); 1696 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1697 mutex_spin_enter(&sc->sc_intr_lock); 1698 uhci_intr1(sc); 1699 mutex_spin_exit(&sc->sc_intr_lock); 1700 if (xfer->ux_status != USBD_IN_PROGRESS) 1701 goto done; 1702 } 1703 } 1704 1705 /* Timeout */ 1706 DPRINTF("timeout", 0, 0, 0, 0); 1707 for (ux = TAILQ_FIRST(&sc->sc_intrhead); ux != NULL; 1708 ux = TAILQ_NEXT(ux, ux_list)) 1709 if (&ux->ux_xfer == xfer) 1710 break; 1711 1712 KASSERT(ux != NULL); 1713 1714 uhci_idone(ux); 1715 1716 done: 1717 mutex_exit(&sc->sc_lock); 1718 } 1719 1720 void 1721 uhci_poll(struct usbd_bus *bus) 1722 { 1723 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1724 1725 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1726 mutex_spin_enter(&sc->sc_intr_lock); 1727 uhci_intr1(sc); 1728 mutex_spin_exit(&sc->sc_intr_lock); 1729 } 1730 } 1731 1732 void 1733 uhci_reset(uhci_softc_t *sc) 1734 { 1735 int n; 1736 1737 UHCICMD(sc, UHCI_CMD_HCRESET); 1738 /* The reset bit goes low when the controller is done. */ 1739 for (n = 0; n < UHCI_RESET_TIMEOUT && 1740 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1741 usb_delay_ms(&sc->sc_bus, 1); 1742 if (n >= UHCI_RESET_TIMEOUT) 1743 printf("%s: controller did not reset\n", 1744 device_xname(sc->sc_dev)); 1745 } 1746 1747 usbd_status 1748 uhci_run(uhci_softc_t *sc, int run, int locked) 1749 { 1750 int n, running; 1751 uint16_t cmd; 1752 1753 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1754 1755 run = run != 0; 1756 if (!locked) 1757 mutex_spin_enter(&sc->sc_intr_lock); 1758 1759 DPRINTF("setting run=%d", run, 0, 0, 0); 1760 cmd = UREAD2(sc, UHCI_CMD); 1761 if (run) 1762 cmd |= UHCI_CMD_RS; 1763 else 1764 cmd &= ~UHCI_CMD_RS; 1765 UHCICMD(sc, cmd); 1766 for(n = 0; n < 10; n++) { 1767 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1768 /* return when we've entered the state we want */ 1769 if (run == running) { 1770 if (!locked) 1771 mutex_spin_exit(&sc->sc_intr_lock); 1772 DPRINTF("done cmd=0x%x sts=0x%x", 1773 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1774 return USBD_NORMAL_COMPLETION; 1775 } 1776 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1777 } 1778 if (!locked) 1779 mutex_spin_exit(&sc->sc_intr_lock); 1780 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1781 run ? "start" : "stop"); 1782 return USBD_IOERROR; 1783 } 1784 1785 /* 1786 * Memory management routines. 1787 * uhci_alloc_std allocates TDs 1788 * uhci_alloc_sqh allocates QHs 1789 * These two routines do their own free list management, 1790 * partly for speed, partly because allocating DMAable memory 1791 * has page size granularity so much memory would be wasted if 1792 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1793 */ 1794 1795 uhci_soft_td_t * 1796 uhci_alloc_std(uhci_softc_t *sc) 1797 { 1798 uhci_soft_td_t *std; 1799 usbd_status err; 1800 int i, offs; 1801 usb_dma_t dma; 1802 1803 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1804 1805 if (sc->sc_freetds == NULL) { 1806 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1807 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1808 UHCI_TD_ALIGN, &dma); 1809 if (err) 1810 return NULL; 1811 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1812 offs = i * UHCI_STD_SIZE; 1813 std = KERNADDR(&dma, offs); 1814 std->physaddr = DMAADDR(&dma, offs); 1815 std->dma = dma; 1816 std->offs = offs; 1817 std->link.std = sc->sc_freetds; 1818 sc->sc_freetds = std; 1819 } 1820 } 1821 std = sc->sc_freetds; 1822 sc->sc_freetds = std->link.std; 1823 memset(&std->td, 0, sizeof(uhci_td_t)); 1824 return std; 1825 } 1826 1827 void 1828 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1829 { 1830 #ifdef DIAGNOSTIC 1831 #define TD_IS_FREE 0x12345678 1832 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1833 printf("uhci_free_std: freeing free TD %p\n", std); 1834 return; 1835 } 1836 std->td.td_token = htole32(TD_IS_FREE); 1837 #endif 1838 std->link.std = sc->sc_freetds; 1839 sc->sc_freetds = std; 1840 } 1841 1842 uhci_soft_qh_t * 1843 uhci_alloc_sqh(uhci_softc_t *sc) 1844 { 1845 uhci_soft_qh_t *sqh; 1846 usbd_status err; 1847 int i, offs; 1848 usb_dma_t dma; 1849 1850 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1851 1852 if (sc->sc_freeqhs == NULL) { 1853 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1854 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1855 UHCI_QH_ALIGN, &dma); 1856 if (err) 1857 return NULL; 1858 for(i = 0; i < UHCI_SQH_CHUNK; i++) { 1859 offs = i * UHCI_SQH_SIZE; 1860 sqh = KERNADDR(&dma, offs); 1861 sqh->physaddr = DMAADDR(&dma, offs); 1862 sqh->dma = dma; 1863 sqh->offs = offs; 1864 sqh->hlink = sc->sc_freeqhs; 1865 sc->sc_freeqhs = sqh; 1866 } 1867 } 1868 sqh = sc->sc_freeqhs; 1869 sc->sc_freeqhs = sqh->hlink; 1870 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1871 return sqh; 1872 } 1873 1874 void 1875 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1876 { 1877 sqh->hlink = sc->sc_freeqhs; 1878 sc->sc_freeqhs = sqh; 1879 } 1880 1881 void 1882 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1883 uhci_soft_td_t *stdend) 1884 { 1885 uhci_soft_td_t *p; 1886 uint32_t td_link; 1887 1888 /* 1889 * to avoid race condition with the controller which may be looking 1890 * at this chain, we need to first invalidate all links, and 1891 * then wait for the controller to move to another queue 1892 */ 1893 for (p = std; p != stdend; p = p->link.std) { 1894 usb_syncmem(&p->dma, 1895 p->offs + offsetof(uhci_td_t, td_link), 1896 sizeof(p->td.td_link), 1897 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1898 td_link = le32toh(p->td.td_link); 1899 usb_syncmem(&p->dma, 1900 p->offs + offsetof(uhci_td_t, td_link), 1901 sizeof(p->td.td_link), 1902 BUS_DMASYNC_PREREAD); 1903 if ((td_link & UHCI_PTR_T) == 0) { 1904 p->td.td_link = htole32(UHCI_PTR_T); 1905 usb_syncmem(&p->dma, 1906 p->offs + offsetof(uhci_td_t, td_link), 1907 sizeof(p->td.td_link), 1908 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1909 } 1910 } 1911 delay(UHCI_QH_REMOVE_DELAY); 1912 1913 for (; std != stdend; std = p) { 1914 p = std->link.std; 1915 uhci_free_std(sc, std); 1916 } 1917 } 1918 1919 usbd_status 1920 uhci_alloc_std_chain(struct uhci_pipe *upipe, uhci_softc_t *sc, int len, 1921 int rd, uint16_t flags, usb_dma_t *dma, 1922 uhci_soft_td_t **sp, uhci_soft_td_t **ep) 1923 { 1924 uhci_soft_td_t *p, *lastp; 1925 uhci_physaddr_t lastlink; 1926 int i, ntd, l, tog, maxp; 1927 uint32_t status; 1928 int addr = upipe->pipe.up_dev->ud_addr; 1929 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 1930 1931 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1932 1933 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 1934 addr, UE_GET_ADDR(endpt), len, upipe->pipe.up_dev->ud_speed); 1935 1936 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1937 1938 maxp = UGETW(upipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 1939 if (maxp == 0) { 1940 printf("uhci_alloc_std_chain: maxp=0\n"); 1941 return USBD_INVAL; 1942 } 1943 ntd = (len + maxp - 1) / maxp; 1944 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 1945 ntd++; 1946 DPRINTFN(10, "maxp=%d ntd=%d", 1947 maxp, ntd, 0, 0); 1948 1949 if (ntd == 0) { 1950 *sp = *ep = NULL; 1951 DPRINTF("ntd=0", 0, 0, 0, 0); 1952 return USBD_NORMAL_COMPLETION; 1953 } 1954 tog = upipe->nexttoggle; 1955 if (ntd % 2 == 0) 1956 tog ^= 1; 1957 upipe->nexttoggle = tog ^ 1; 1958 lastp = NULL; 1959 lastlink = UHCI_PTR_T; 1960 ntd--; 1961 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 1962 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 1963 status |= UHCI_TD_LS; 1964 if (flags & USBD_SHORT_XFER_OK) 1965 status |= UHCI_TD_SPD; 1966 usb_syncmem(dma, 0, len, 1967 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1968 for (i = ntd; i >= 0; i--) { 1969 p = uhci_alloc_std(sc); 1970 if (p == NULL) { 1971 KASSERT(lastp != NULL); 1972 uhci_free_std_chain(sc, lastp, NULL); 1973 return USBD_NOMEM; 1974 } 1975 p->link.std = lastp; 1976 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 1977 lastp = p; 1978 lastlink = p->physaddr; 1979 p->td.td_status = htole32(status); 1980 if (i == ntd) { 1981 /* last TD */ 1982 l = len % maxp; 1983 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 1984 l = maxp; 1985 *ep = p; 1986 } else 1987 l = maxp; 1988 p->td.td_token = 1989 htole32(rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1990 UHCI_TD_OUT(l, endpt, addr, tog)); 1991 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 1992 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 1993 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1994 tog ^= 1; 1995 } 1996 *sp = lastp; 1997 DPRINTFN(10, "nexttog=%d", upipe->nexttoggle, 1998 0, 0, 0); 1999 2000 return USBD_NORMAL_COMPLETION; 2001 } 2002 2003 void 2004 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2005 { 2006 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2007 upipe->nexttoggle = 0; 2008 } 2009 2010 void 2011 uhci_noop(struct usbd_pipe *pipe) 2012 { 2013 } 2014 2015 usbd_status 2016 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2017 { 2018 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2019 usbd_status err; 2020 2021 /* Insert last in queue. */ 2022 mutex_enter(&sc->sc_lock); 2023 err = usb_insert_transfer(xfer); 2024 mutex_exit(&sc->sc_lock); 2025 if (err) 2026 return err; 2027 2028 /* 2029 * Pipe isn't running (otherwise err would be USBD_INPROG), 2030 * so start it first. 2031 */ 2032 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2033 } 2034 2035 usbd_status 2036 uhci_device_bulk_start(struct usbd_xfer *xfer) 2037 { 2038 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2039 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2040 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2041 uhci_soft_td_t *data, *dataend; 2042 uhci_soft_qh_t *sqh; 2043 usbd_status err; 2044 int len, isread, endpt; 2045 2046 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2047 DPRINTFN(3, "xfer=%p len=%d flags=%d ux=%p", 2048 xfer, xfer->ux_length, xfer->ux_flags, ux); 2049 2050 if (sc->sc_dying) 2051 return USBD_IOERROR; 2052 2053 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2054 2055 mutex_enter(&sc->sc_lock); 2056 2057 len = xfer->ux_length; 2058 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2059 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2060 sqh = upipe->bulk.sqh; 2061 2062 upipe->bulk.isread = isread; 2063 upipe->bulk.length = len; 2064 2065 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2066 &xfer->ux_dmabuf, &data, &dataend); 2067 if (err) { 2068 mutex_exit(&sc->sc_lock); 2069 return err; 2070 } 2071 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2072 usb_syncmem(&dataend->dma, 2073 dataend->offs + offsetof(uhci_td_t, td_status), 2074 sizeof(dataend->td.td_status), 2075 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2076 2077 2078 #ifdef UHCI_DEBUG 2079 if (uhcidebug >= 8) { 2080 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2081 DPRINTFN(8, "data(1)", 0, 0, 0, 0); 2082 uhci_dump_tds(data); 2083 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2084 } 2085 #endif 2086 2087 /* Set up interrupt info. */ 2088 ux->ux_stdstart = data; 2089 ux->ux_stdend = dataend; 2090 2091 KASSERT(ux->ux_isdone); 2092 #ifdef DIAGNOSTIC 2093 ux->ux_isdone = false; 2094 #endif 2095 2096 sqh->elink = data; 2097 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2098 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2099 2100 uhci_add_bulk(sc, sqh); 2101 uhci_add_intr_info(sc, ux); 2102 2103 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2104 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2105 uhci_timeout, xfer); 2106 } 2107 xfer->ux_status = USBD_IN_PROGRESS; 2108 2109 #ifdef UHCI_DEBUG 2110 if (uhcidebug >= 10) { 2111 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2112 DPRINTFN(10, "data(2)", 0, 0, 0, 0); 2113 uhci_dump_tds(data); 2114 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2115 } 2116 #endif 2117 2118 if (sc->sc_bus.ub_usepolling) 2119 uhci_waitintr(sc, xfer); 2120 2121 mutex_exit(&sc->sc_lock); 2122 return USBD_IN_PROGRESS; 2123 } 2124 2125 /* Abort a device bulk request. */ 2126 void 2127 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2128 { 2129 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2130 2131 KASSERT(mutex_owned(&sc->sc_lock)); 2132 2133 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2134 2135 uhci_abort_xfer(xfer, USBD_CANCELLED); 2136 } 2137 2138 /* 2139 * Abort a device request. 2140 * If this routine is called at splusb() it guarantees that the request 2141 * will be removed from the hardware scheduling and that the callback 2142 * for it will be called with USBD_CANCELLED status. 2143 * It's impossible to guarantee that the requested transfer will not 2144 * have happened since the hardware runs concurrently. 2145 * If the transaction has already happened we rely on the ordinary 2146 * interrupt processing to process it. 2147 * XXX This is most probably wrong. 2148 * XXXMRG this doesn't make sense anymore. 2149 */ 2150 void 2151 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2152 { 2153 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2154 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2155 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2156 uhci_soft_td_t *std; 2157 int wake; 2158 2159 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2160 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2161 2162 KASSERT(mutex_owned(&sc->sc_lock)); 2163 ASSERT_SLEEPABLE(); 2164 2165 if (sc->sc_dying) { 2166 /* If we're dying, just do the software part. */ 2167 xfer->ux_status = status; /* make software ignore it */ 2168 callout_stop(&xfer->ux_callout); 2169 usb_transfer_complete(xfer); 2170 return; 2171 } 2172 2173 /* 2174 * If an abort is already in progress then just wait for it to 2175 * complete and return. 2176 */ 2177 if (xfer->ux_hcflags & UXFER_ABORTING) { 2178 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2179 #ifdef DIAGNOSTIC 2180 if (status == USBD_TIMEOUT) 2181 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2182 #endif 2183 /* Override the status which might be USBD_TIMEOUT. */ 2184 xfer->ux_status = status; 2185 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2186 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2187 while (xfer->ux_hcflags & UXFER_ABORTING) 2188 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2189 goto done; 2190 } 2191 xfer->ux_hcflags |= UXFER_ABORTING; 2192 2193 /* 2194 * Step 1: Make interrupt routine and hardware ignore xfer. 2195 */ 2196 xfer->ux_status = status; /* make software ignore it */ 2197 callout_stop(&xfer->ux_callout); 2198 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2199 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2200 usb_syncmem(&std->dma, 2201 std->offs + offsetof(uhci_td_t, td_status), 2202 sizeof(std->td.td_status), 2203 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2204 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2205 usb_syncmem(&std->dma, 2206 std->offs + offsetof(uhci_td_t, td_status), 2207 sizeof(std->td.td_status), 2208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2209 } 2210 2211 /* 2212 * Step 2: Wait until we know hardware has finished any possible 2213 * use of the xfer. Also make sure the soft interrupt routine 2214 * has run. 2215 */ 2216 /* Hardware finishes in 1ms */ 2217 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2218 sc->sc_softwake = 1; 2219 usb_schedsoftintr(&sc->sc_bus); 2220 DPRINTF("cv_wait", 0, 0, 0, 0); 2221 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2222 2223 /* 2224 * Step 3: Execute callback. 2225 */ 2226 DPRINTF("callback", 0, 0, 0, 0); 2227 #ifdef DIAGNOSTIC 2228 ux->ux_isdone = true; 2229 #endif 2230 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2231 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2232 usb_transfer_complete(xfer); 2233 if (wake) 2234 cv_broadcast(&xfer->ux_hccv); 2235 done: 2236 KASSERT(mutex_owned(&sc->sc_lock)); 2237 } 2238 2239 /* Close a device bulk pipe. */ 2240 void 2241 uhci_device_bulk_close(struct usbd_pipe *pipe) 2242 { 2243 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2244 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2245 2246 KASSERT(mutex_owned(&sc->sc_lock)); 2247 2248 uhci_free_sqh(sc, upipe->bulk.sqh); 2249 2250 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2251 } 2252 2253 usbd_status 2254 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2255 { 2256 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2257 usbd_status err; 2258 2259 /* Insert last in queue. */ 2260 mutex_enter(&sc->sc_lock); 2261 err = usb_insert_transfer(xfer); 2262 mutex_exit(&sc->sc_lock); 2263 if (err) 2264 return err; 2265 2266 /* 2267 * Pipe isn't running (otherwise err would be USBD_INPROG), 2268 * so start it first. 2269 */ 2270 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2271 } 2272 2273 usbd_status 2274 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2275 { 2276 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2277 usbd_status err; 2278 2279 if (sc->sc_dying) 2280 return USBD_IOERROR; 2281 2282 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2283 2284 mutex_enter(&sc->sc_lock); 2285 err = uhci_device_request(xfer); 2286 mutex_exit(&sc->sc_lock); 2287 if (err) 2288 return err; 2289 2290 if (sc->sc_bus.ub_usepolling) 2291 uhci_waitintr(sc, xfer); 2292 return USBD_IN_PROGRESS; 2293 } 2294 2295 usbd_status 2296 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2297 { 2298 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2299 usbd_status err; 2300 2301 /* Insert last in queue. */ 2302 mutex_enter(&sc->sc_lock); 2303 err = usb_insert_transfer(xfer); 2304 mutex_exit(&sc->sc_lock); 2305 if (err) 2306 return err; 2307 2308 /* 2309 * Pipe isn't running (otherwise err would be USBD_INPROG), 2310 * so start it first. 2311 */ 2312 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2313 } 2314 2315 usbd_status 2316 uhci_device_intr_start(struct usbd_xfer *xfer) 2317 { 2318 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2319 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2320 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2321 uhci_soft_td_t *data, *dataend; 2322 uhci_soft_qh_t *sqh; 2323 usbd_status err; 2324 int isread, endpt; 2325 int i; 2326 2327 if (sc->sc_dying) 2328 return USBD_IOERROR; 2329 2330 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2331 2332 DPRINTFN(3, "xfer=%p len=%d flags=%d", 2333 xfer, xfer->ux_length, xfer->ux_flags, 0); 2334 2335 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2336 2337 mutex_enter(&sc->sc_lock); 2338 2339 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2340 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2341 2342 upipe->intr.isread = isread; 2343 2344 err = uhci_alloc_std_chain(upipe, sc, xfer->ux_length, isread, 2345 xfer->ux_flags, &xfer->ux_dmabuf, &data, 2346 &dataend); 2347 if (err) { 2348 mutex_exit(&sc->sc_lock); 2349 return err; 2350 } 2351 2352 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2353 usb_syncmem(&dataend->dma, 2354 dataend->offs + offsetof(uhci_td_t, td_status), 2355 sizeof(dataend->td.td_status), 2356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2357 2358 #ifdef UHCI_DEBUG 2359 if (uhcidebug >= 10) { 2360 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2361 uhci_dump_tds(data); 2362 uhci_dump_qh(upipe->intr.qhs[0]); 2363 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2364 } 2365 #endif 2366 2367 /* Set up interrupt info. */ 2368 ux->ux_stdstart = data; 2369 ux->ux_stdend = dataend; 2370 KASSERT(ux->ux_isdone); 2371 #ifdef DIAGNOSTIC 2372 ux->ux_isdone = false; 2373 #endif 2374 2375 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2376 for (i = 0; i < upipe->intr.npoll; i++) { 2377 sqh = upipe->intr.qhs[i]; 2378 sqh->elink = data; 2379 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2380 usb_syncmem(&sqh->dma, 2381 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2382 sizeof(sqh->qh.qh_elink), 2383 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2384 } 2385 uhci_add_intr_info(sc, ux); 2386 xfer->ux_status = USBD_IN_PROGRESS; 2387 mutex_exit(&sc->sc_lock); 2388 2389 #ifdef UHCI_DEBUG 2390 if (uhcidebug >= 10) { 2391 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2392 uhci_dump_tds(data); 2393 uhci_dump_qh(upipe->intr.qhs[0]); 2394 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2395 } 2396 #endif 2397 2398 return USBD_IN_PROGRESS; 2399 } 2400 2401 /* Abort a device control request. */ 2402 void 2403 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2404 { 2405 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2406 2407 KASSERT(mutex_owned(&sc->sc_lock)); 2408 2409 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2410 uhci_abort_xfer(xfer, USBD_CANCELLED); 2411 } 2412 2413 /* Close a device control pipe. */ 2414 void 2415 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2416 { 2417 } 2418 2419 /* Abort a device interrupt request. */ 2420 void 2421 uhci_device_intr_abort(struct usbd_xfer *xfer) 2422 { 2423 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2424 2425 KASSERT(mutex_owned(&sc->sc_lock)); 2426 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2427 2428 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2429 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2430 2431 uhci_abort_xfer(xfer, USBD_CANCELLED); 2432 } 2433 2434 /* Close a device interrupt pipe. */ 2435 void 2436 uhci_device_intr_close(struct usbd_pipe *pipe) 2437 { 2438 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2439 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2440 int i, npoll; 2441 2442 KASSERT(mutex_owned(&sc->sc_lock)); 2443 2444 /* Unlink descriptors from controller data structures. */ 2445 npoll = upipe->intr.npoll; 2446 for (i = 0; i < npoll; i++) 2447 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2448 2449 /* 2450 * We now have to wait for any activity on the physical 2451 * descriptors to stop. 2452 */ 2453 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2454 2455 for(i = 0; i < npoll; i++) 2456 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2457 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2458 2459 /* XXX free other resources */ 2460 } 2461 2462 usbd_status 2463 uhci_device_request(struct usbd_xfer *xfer) 2464 { 2465 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2466 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2467 usb_device_request_t *req = &xfer->ux_request; 2468 struct usbd_device *dev = upipe->pipe.up_dev; 2469 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2470 int addr = dev->ud_addr; 2471 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2472 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2473 uhci_soft_qh_t *sqh; 2474 int len; 2475 uint32_t ls; 2476 usbd_status err; 2477 int isread; 2478 2479 KASSERT(mutex_owned(&sc->sc_lock)); 2480 2481 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2482 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2483 "wValue=0x%04x, wIndex=0x%04x", 2484 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2485 UGETW(req->wIndex)); 2486 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2487 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2488 2489 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2490 isread = req->bmRequestType & UT_READ; 2491 len = UGETW(req->wLength); 2492 2493 setup = upipe->ctrl.setup; 2494 stat = upipe->ctrl.stat; 2495 sqh = upipe->ctrl.sqh; 2496 2497 /* Set up data transaction */ 2498 if (len != 0) { 2499 upipe->nexttoggle = 1; 2500 err = uhci_alloc_std_chain(upipe, sc, len, isread, xfer->ux_flags, 2501 &xfer->ux_dmabuf, &data, &dataend); 2502 if (err) 2503 return err; 2504 next = data; 2505 dataend->link.std = stat; 2506 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2507 usb_syncmem(&dataend->dma, 2508 dataend->offs + offsetof(uhci_td_t, td_link), 2509 sizeof(dataend->td.td_link), 2510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2511 } else { 2512 next = stat; 2513 } 2514 upipe->ctrl.length = len; 2515 2516 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2517 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2518 2519 setup->link.std = next; 2520 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2521 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2522 UHCI_TD_ACTIVE); 2523 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2524 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2525 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2526 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2527 2528 stat->link.std = NULL; 2529 stat->td.td_link = htole32(UHCI_PTR_T); 2530 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2531 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2532 stat->td.td_token = 2533 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2534 UHCI_TD_IN (0, endpt, addr, 1)); 2535 stat->td.td_buffer = htole32(0); 2536 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2538 2539 #ifdef UHCI_DEBUG 2540 if (uhcidebug >= 10) { 2541 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2542 DPRINTF("before transfer", 0, 0, 0, 0); 2543 uhci_dump_tds(setup); 2544 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2545 } 2546 #endif 2547 2548 /* Set up interrupt info. */ 2549 uxfer->ux_stdstart = setup; 2550 uxfer->ux_stdend = stat; 2551 KASSERT(uxfer->ux_isdone); 2552 #ifdef DIAGNOSTIC 2553 uxfer->ux_isdone = false; 2554 #endif 2555 2556 sqh->elink = setup; 2557 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2558 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2559 2560 if (dev->ud_speed == USB_SPEED_LOW) 2561 uhci_add_ls_ctrl(sc, sqh); 2562 else 2563 uhci_add_hs_ctrl(sc, sqh); 2564 uhci_add_intr_info(sc, uxfer); 2565 #ifdef UHCI_DEBUG 2566 if (uhcidebug >= 12) { 2567 uhci_soft_td_t *std; 2568 uhci_soft_qh_t *xqh; 2569 uhci_soft_qh_t *sxqh; 2570 int maxqh = 0; 2571 uhci_physaddr_t link; 2572 2573 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2574 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2575 for (std = sc->sc_vframes[0].htd, link = 0; 2576 (link & UHCI_PTR_QH) == 0; 2577 std = std->link.std) { 2578 link = le32toh(std->td.td_link); 2579 uhci_dump_td(std); 2580 } 2581 sxqh = (uhci_soft_qh_t *)std; 2582 uhci_dump_qh(sxqh); 2583 for (xqh = sxqh; 2584 xqh != NULL; 2585 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2586 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2587 uhci_dump_qh(xqh); 2588 } 2589 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2590 uhci_dump_qh(sqh); 2591 uhci_dump_tds(sqh->elink); 2592 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2593 } 2594 #endif 2595 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2596 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2597 uhci_timeout, xfer); 2598 } 2599 xfer->ux_status = USBD_IN_PROGRESS; 2600 2601 return USBD_NORMAL_COMPLETION; 2602 } 2603 2604 usbd_status 2605 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2606 { 2607 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2608 usbd_status err; 2609 2610 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2611 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2612 2613 /* Put it on our queue, */ 2614 mutex_enter(&sc->sc_lock); 2615 err = usb_insert_transfer(xfer); 2616 mutex_exit(&sc->sc_lock); 2617 2618 /* bail out on error, */ 2619 if (err && err != USBD_IN_PROGRESS) 2620 return err; 2621 2622 /* XXX should check inuse here */ 2623 2624 /* insert into schedule, */ 2625 uhci_device_isoc_enter(xfer); 2626 2627 /* and start if the pipe wasn't running */ 2628 if (!err) 2629 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2630 2631 return err; 2632 } 2633 2634 void 2635 uhci_device_isoc_enter(struct usbd_xfer *xfer) 2636 { 2637 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2638 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2639 struct isoc *isoc = &upipe->isoc; 2640 uhci_soft_td_t *std; 2641 uint32_t buf, len, status, offs; 2642 int i, next, nframes; 2643 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2644 2645 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2646 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2647 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2648 2649 if (sc->sc_dying) 2650 return; 2651 2652 if (xfer->ux_status == USBD_IN_PROGRESS) { 2653 /* This request has already been entered into the frame list */ 2654 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 2655 /* XXX */ 2656 } 2657 2658 #ifdef DIAGNOSTIC 2659 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2660 printf("uhci_device_isoc_enter: overflow!\n"); 2661 #endif 2662 2663 next = isoc->next; 2664 if (next == -1) { 2665 /* Not in use yet, schedule it a few frames ahead. */ 2666 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2667 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2668 } 2669 2670 xfer->ux_status = USBD_IN_PROGRESS; 2671 UHCI_XFER2UXFER(xfer)->ux_curframe = next; 2672 2673 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2674 offs = 0; 2675 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2676 UHCI_TD_ACTIVE | 2677 UHCI_TD_IOS); 2678 nframes = xfer->ux_nframes; 2679 mutex_enter(&sc->sc_lock); 2680 for (i = 0; i < nframes; i++) { 2681 std = isoc->stds[next]; 2682 if (++next >= UHCI_VFRAMELIST_COUNT) 2683 next = 0; 2684 len = xfer->ux_frlengths[i]; 2685 std->td.td_buffer = htole32(buf); 2686 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2687 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2688 if (i == nframes - 1) 2689 status |= UHCI_TD_IOC; 2690 std->td.td_status = htole32(status); 2691 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2692 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2693 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2694 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2695 #ifdef UHCI_DEBUG 2696 if (uhcidebug >= 5) { 2697 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2698 DPRINTF("TD %d", i, 0, 0, 0); 2699 uhci_dump_td(std); 2700 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2701 } 2702 #endif 2703 buf += len; 2704 offs += len; 2705 } 2706 isoc->next = next; 2707 isoc->inuse += xfer->ux_nframes; 2708 2709 mutex_exit(&sc->sc_lock); 2710 } 2711 2712 usbd_status 2713 uhci_device_isoc_start(struct usbd_xfer *xfer) 2714 { 2715 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2716 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2717 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2718 uhci_soft_td_t *end; 2719 int i; 2720 2721 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2722 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2723 2724 mutex_enter(&sc->sc_lock); 2725 2726 if (sc->sc_dying) { 2727 mutex_exit(&sc->sc_lock); 2728 return USBD_IOERROR; 2729 } 2730 2731 #ifdef DIAGNOSTIC 2732 if (xfer->ux_status != USBD_IN_PROGRESS) 2733 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 2734 #endif 2735 2736 /* Find the last TD */ 2737 i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes; 2738 if (i >= UHCI_VFRAMELIST_COUNT) 2739 i -= UHCI_VFRAMELIST_COUNT; 2740 end = upipe->isoc.stds[i]; 2741 2742 KASSERT(end != NULL); 2743 2744 /* Set up interrupt info. */ 2745 ux->ux_stdstart = end; 2746 ux->ux_stdend = end; 2747 2748 KASSERT(ux->ux_isdone); 2749 #ifdef DIAGNOSTIC 2750 ux->ux_isdone = false; 2751 #endif 2752 uhci_add_intr_info(sc, ux); 2753 2754 mutex_exit(&sc->sc_lock); 2755 2756 return USBD_IN_PROGRESS; 2757 } 2758 2759 void 2760 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2761 { 2762 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2763 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2764 uhci_soft_td_t **stds = upipe->isoc.stds; 2765 uhci_soft_td_t *std; 2766 int i, n, nframes, maxlen, len; 2767 2768 KASSERT(mutex_owned(&sc->sc_lock)); 2769 2770 /* Transfer is already done. */ 2771 if (xfer->ux_status != USBD_NOT_STARTED && 2772 xfer->ux_status != USBD_IN_PROGRESS) { 2773 return; 2774 } 2775 2776 /* Give xfer the requested abort code. */ 2777 xfer->ux_status = USBD_CANCELLED; 2778 2779 /* make hardware ignore it, */ 2780 nframes = xfer->ux_nframes; 2781 n = UHCI_XFER2UXFER(xfer)->ux_curframe; 2782 maxlen = 0; 2783 for (i = 0; i < nframes; i++) { 2784 std = stds[n]; 2785 usb_syncmem(&std->dma, 2786 std->offs + offsetof(uhci_td_t, td_status), 2787 sizeof(std->td.td_status), 2788 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2789 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2790 usb_syncmem(&std->dma, 2791 std->offs + offsetof(uhci_td_t, td_status), 2792 sizeof(std->td.td_status), 2793 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2794 usb_syncmem(&std->dma, 2795 std->offs + offsetof(uhci_td_t, td_token), 2796 sizeof(std->td.td_token), 2797 BUS_DMASYNC_POSTWRITE); 2798 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 2799 if (len > maxlen) 2800 maxlen = len; 2801 if (++n >= UHCI_VFRAMELIST_COUNT) 2802 n = 0; 2803 } 2804 2805 /* and wait until we are sure the hardware has finished. */ 2806 delay(maxlen); 2807 2808 #ifdef DIAGNOSTIC 2809 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 2810 #endif 2811 /* Run callback and remove from interrupt list. */ 2812 usb_transfer_complete(xfer); 2813 2814 KASSERT(mutex_owned(&sc->sc_lock)); 2815 } 2816 2817 void 2818 uhci_device_isoc_close(struct usbd_pipe *pipe) 2819 { 2820 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2821 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2822 uhci_soft_td_t *std, *vstd; 2823 struct isoc *isoc; 2824 int i; 2825 2826 KASSERT(mutex_owned(&sc->sc_lock)); 2827 2828 /* 2829 * Make sure all TDs are marked as inactive. 2830 * Wait for completion. 2831 * Unschedule. 2832 * Deallocate. 2833 */ 2834 isoc = &upipe->isoc; 2835 2836 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2837 std = isoc->stds[i]; 2838 usb_syncmem(&std->dma, 2839 std->offs + offsetof(uhci_td_t, td_status), 2840 sizeof(std->td.td_status), 2841 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2842 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 2843 usb_syncmem(&std->dma, 2844 std->offs + offsetof(uhci_td_t, td_status), 2845 sizeof(std->td.td_status), 2846 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2847 } 2848 /* wait for completion */ 2849 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2850 2851 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2852 std = isoc->stds[i]; 2853 for (vstd = sc->sc_vframes[i].htd; 2854 vstd != NULL && vstd->link.std != std; 2855 vstd = vstd->link.std) 2856 ; 2857 if (vstd == NULL) { 2858 /*panic*/ 2859 printf("uhci_device_isoc_close: %p not found\n", std); 2860 mutex_exit(&sc->sc_lock); 2861 return; 2862 } 2863 vstd->link = std->link; 2864 usb_syncmem(&std->dma, 2865 std->offs + offsetof(uhci_td_t, td_link), 2866 sizeof(std->td.td_link), 2867 BUS_DMASYNC_POSTWRITE); 2868 vstd->td.td_link = std->td.td_link; 2869 usb_syncmem(&vstd->dma, 2870 vstd->offs + offsetof(uhci_td_t, td_link), 2871 sizeof(vstd->td.td_link), 2872 BUS_DMASYNC_PREWRITE); 2873 uhci_free_std(sc, std); 2874 } 2875 2876 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2877 } 2878 2879 usbd_status 2880 uhci_setup_isoc(struct usbd_pipe *pipe) 2881 { 2882 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2883 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2884 int addr = upipe->pipe.up_dev->ud_addr; 2885 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2886 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 2887 uhci_soft_td_t *std, *vstd; 2888 uint32_t token; 2889 struct isoc *isoc; 2890 int i; 2891 2892 isoc = &upipe->isoc; 2893 isoc->stds = kmem_alloc(UHCI_VFRAMELIST_COUNT * 2894 sizeof(uhci_soft_td_t *), 2895 KM_SLEEP); 2896 if (isoc->stds == NULL) 2897 return USBD_NOMEM; 2898 2899 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 2900 UHCI_TD_OUT(0, endpt, addr, 0); 2901 2902 mutex_enter(&sc->sc_lock); 2903 2904 /* Allocate the TDs and mark as inactive; */ 2905 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2906 std = uhci_alloc_std(sc); 2907 if (std == 0) 2908 goto bad; 2909 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 2910 std->td.td_token = htole32(token); 2911 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2912 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2913 isoc->stds[i] = std; 2914 } 2915 2916 /* Insert TDs into schedule. */ 2917 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 2918 std = isoc->stds[i]; 2919 vstd = sc->sc_vframes[i].htd; 2920 usb_syncmem(&vstd->dma, 2921 vstd->offs + offsetof(uhci_td_t, td_link), 2922 sizeof(vstd->td.td_link), 2923 BUS_DMASYNC_POSTWRITE); 2924 std->link = vstd->link; 2925 std->td.td_link = vstd->td.td_link; 2926 usb_syncmem(&std->dma, 2927 std->offs + offsetof(uhci_td_t, td_link), 2928 sizeof(std->td.td_link), 2929 BUS_DMASYNC_PREWRITE); 2930 vstd->link.std = std; 2931 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 2932 usb_syncmem(&vstd->dma, 2933 vstd->offs + offsetof(uhci_td_t, td_link), 2934 sizeof(vstd->td.td_link), 2935 BUS_DMASYNC_PREWRITE); 2936 } 2937 mutex_exit(&sc->sc_lock); 2938 2939 isoc->next = -1; 2940 isoc->inuse = 0; 2941 2942 return USBD_NORMAL_COMPLETION; 2943 2944 bad: 2945 while (--i >= 0) 2946 uhci_free_std(sc, isoc->stds[i]); 2947 mutex_exit(&sc->sc_lock); 2948 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 2949 return USBD_NOMEM; 2950 } 2951 2952 void 2953 uhci_device_isoc_done(struct usbd_xfer *xfer) 2954 { 2955 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2956 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2957 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2958 int i, offs; 2959 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2960 2961 2962 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2963 DPRINTFN(4, "length=%d, ux_state=0x%08x", 2964 xfer->ux_actlen, xfer->ux_state, 0, 0); 2965 2966 if (!uhci_active_intr_info(ux)) 2967 return; 2968 2969 #ifdef DIAGNOSTIC 2970 if (ux->ux_stdend == NULL) { 2971 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 2972 #ifdef UHCI_DEBUG 2973 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2974 uhci_dump_ii(ux); 2975 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2976 #endif 2977 return; 2978 } 2979 #endif 2980 2981 /* Turn off the interrupt since it is active even if the TD is not. */ 2982 usb_syncmem(&ux->ux_stdend->dma, 2983 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 2984 sizeof(ux->ux_stdend->td.td_status), 2985 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2986 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 2987 usb_syncmem(&ux->ux_stdend->dma, 2988 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 2989 sizeof(ux->ux_stdend->td.td_status), 2990 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2991 2992 uhci_del_intr_info(sc, ux); /* remove from active list */ 2993 2994 offs = 0; 2995 for (i = 0; i < xfer->ux_nframes; i++) { 2996 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 2997 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2998 offs += xfer->ux_frlengths[i]; 2999 } 3000 } 3001 3002 void 3003 uhci_device_intr_done(struct usbd_xfer *xfer) 3004 { 3005 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3006 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3007 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3008 uhci_soft_qh_t *sqh; 3009 int i, npoll, isread; 3010 3011 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3012 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3013 3014 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3015 3016 npoll = upipe->intr.npoll; 3017 for(i = 0; i < npoll; i++) { 3018 sqh = upipe->intr.qhs[i]; 3019 sqh->elink = NULL; 3020 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3021 usb_syncmem(&sqh->dma, 3022 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3023 sizeof(sqh->qh.qh_elink), 3024 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3025 } 3026 uhci_free_std_chain(sc, ux->ux_stdstart, NULL); 3027 3028 isread = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3029 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3030 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3031 3032 /* XXX Wasteful. */ 3033 if (xfer->ux_pipe->up_repeat) { 3034 uhci_soft_td_t *data, *dataend; 3035 3036 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3037 3038 /* This alloc cannot fail since we freed the chain above. */ 3039 uhci_alloc_std_chain(upipe, sc, xfer->ux_length, 3040 upipe->intr.isread, xfer->ux_flags, 3041 &xfer->ux_dmabuf, &data, &dataend); 3042 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3043 usb_syncmem(&dataend->dma, 3044 dataend->offs + offsetof(uhci_td_t, td_status), 3045 sizeof(dataend->td.td_status), 3046 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3047 3048 #ifdef UHCI_DEBUG 3049 if (uhcidebug >= 10) { 3050 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3051 uhci_dump_tds(data); 3052 uhci_dump_qh(upipe->intr.qhs[0]); 3053 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3054 } 3055 #endif 3056 3057 ux->ux_stdstart = data; 3058 ux->ux_stdend = dataend; 3059 KASSERT(ux->ux_isdone); 3060 #ifdef DIAGNOSTIC 3061 ux->ux_isdone = false; 3062 #endif 3063 for (i = 0; i < npoll; i++) { 3064 sqh = upipe->intr.qhs[i]; 3065 sqh->elink = data; 3066 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3067 usb_syncmem(&sqh->dma, 3068 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3069 sizeof(sqh->qh.qh_elink), 3070 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3071 } 3072 xfer->ux_status = USBD_IN_PROGRESS; 3073 /* The ux is already on the examined list, just leave it. */ 3074 } else { 3075 DPRINTFN(5, "removing", 0, 0, 0, 0); 3076 if (uhci_active_intr_info(ux)) 3077 uhci_del_intr_info(sc, ux); 3078 } 3079 } 3080 3081 /* Deallocate request data structures */ 3082 void 3083 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3084 { 3085 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3086 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3087 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3088 int len = UGETW(xfer->ux_request.wLength); 3089 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3090 3091 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3092 3093 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3094 3095 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3096 3097 if (!uhci_active_intr_info(ux)) 3098 return; 3099 3100 uhci_del_intr_info(sc, ux); /* remove from active list */ 3101 3102 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3103 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3104 else 3105 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3106 3107 if (upipe->ctrl.length != 0) 3108 uhci_free_std_chain(sc, ux->ux_stdstart->link.std, ux->ux_stdend); 3109 3110 if (len) { 3111 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3112 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3113 } 3114 usb_syncmem(&upipe->ctrl.reqdma, 0, 3115 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3116 3117 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3118 } 3119 3120 /* Deallocate request data structures */ 3121 void 3122 uhci_device_bulk_done(struct usbd_xfer *xfer) 3123 { 3124 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3125 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3126 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3127 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3128 int endpt = ed->bEndpointAddress; 3129 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3130 3131 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3132 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3133 upipe); 3134 3135 KASSERT(mutex_owned(&sc->sc_lock)); 3136 3137 if (!uhci_active_intr_info(ux)) 3138 return; 3139 3140 uhci_del_intr_info(sc, ux); /* remove from active list */ 3141 3142 uhci_remove_bulk(sc, upipe->bulk.sqh); 3143 3144 uhci_free_std_chain(sc, ux->ux_stdstart, NULL); 3145 if (xfer->ux_length) { 3146 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3147 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3148 } 3149 3150 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3151 } 3152 3153 /* Add interrupt QH, called with vflock. */ 3154 void 3155 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3156 { 3157 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3158 uhci_soft_qh_t *eqh; 3159 3160 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3161 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3162 3163 eqh = vf->eqh; 3164 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3165 sizeof(eqh->qh.qh_hlink), 3166 BUS_DMASYNC_POSTWRITE); 3167 sqh->hlink = eqh->hlink; 3168 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3169 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3170 sizeof(sqh->qh.qh_hlink), 3171 BUS_DMASYNC_PREWRITE); 3172 eqh->hlink = sqh; 3173 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3174 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3175 sizeof(eqh->qh.qh_hlink), 3176 BUS_DMASYNC_PREWRITE); 3177 vf->eqh = sqh; 3178 vf->bandwidth++; 3179 } 3180 3181 /* Remove interrupt QH. */ 3182 void 3183 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3184 { 3185 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3186 uhci_soft_qh_t *pqh; 3187 3188 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3189 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3190 3191 /* See comment in uhci_remove_ctrl() */ 3192 3193 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3194 sizeof(sqh->qh.qh_elink), 3195 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3196 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3197 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3198 usb_syncmem(&sqh->dma, 3199 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3200 sizeof(sqh->qh.qh_elink), 3201 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3202 delay(UHCI_QH_REMOVE_DELAY); 3203 } 3204 3205 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3206 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3207 sizeof(sqh->qh.qh_hlink), 3208 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3209 pqh->hlink = sqh->hlink; 3210 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3211 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3212 sizeof(pqh->qh.qh_hlink), 3213 BUS_DMASYNC_PREWRITE); 3214 delay(UHCI_QH_REMOVE_DELAY); 3215 if (vf->eqh == sqh) 3216 vf->eqh = pqh; 3217 vf->bandwidth--; 3218 } 3219 3220 usbd_status 3221 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3222 { 3223 uhci_soft_qh_t *sqh; 3224 int i, npoll; 3225 u_int bestbw, bw, bestoffs, offs; 3226 3227 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3228 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3229 if (ival == 0) { 3230 printf("uhci_device_setintr: 0 interval\n"); 3231 return USBD_INVAL; 3232 } 3233 3234 if (ival > UHCI_VFRAMELIST_COUNT) 3235 ival = UHCI_VFRAMELIST_COUNT; 3236 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3237 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3238 3239 upipe->intr.npoll = npoll; 3240 upipe->intr.qhs = 3241 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3242 if (upipe->intr.qhs == NULL) 3243 return USBD_NOMEM; 3244 3245 /* 3246 * Figure out which offset in the schedule that has most 3247 * bandwidth left over. 3248 */ 3249 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3250 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3251 for (bw = i = 0; i < npoll; i++) 3252 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3253 if (bw < bestbw) { 3254 bestbw = bw; 3255 bestoffs = offs; 3256 } 3257 } 3258 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3259 mutex_enter(&sc->sc_lock); 3260 for(i = 0; i < npoll; i++) { 3261 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3262 sqh->elink = NULL; 3263 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3264 usb_syncmem(&sqh->dma, 3265 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3266 sizeof(sqh->qh.qh_elink), 3267 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3268 sqh->pos = MOD(i * ival + bestoffs); 3269 } 3270 #undef MOD 3271 3272 /* Enter QHs into the controller data structures. */ 3273 for(i = 0; i < npoll; i++) 3274 uhci_add_intr(sc, upipe->intr.qhs[i]); 3275 mutex_exit(&sc->sc_lock); 3276 3277 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3278 3279 return USBD_NORMAL_COMPLETION; 3280 } 3281 3282 /* Open a new pipe. */ 3283 usbd_status 3284 uhci_open(struct usbd_pipe *pipe) 3285 { 3286 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3287 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3288 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3289 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3290 usbd_status err = USBD_NOMEM; 3291 int ival; 3292 3293 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3294 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3295 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3296 3297 if (sc->sc_dying) 3298 return USBD_IOERROR; 3299 3300 upipe->aborting = 0; 3301 /* toggle state needed for bulk endpoints */ 3302 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3303 3304 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3305 switch (ed->bEndpointAddress) { 3306 case USB_CONTROL_ENDPOINT: 3307 pipe->up_methods = &roothub_ctrl_methods; 3308 break; 3309 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3310 pipe->up_methods = &uhci_root_intr_methods; 3311 break; 3312 default: 3313 return USBD_INVAL; 3314 } 3315 } else { 3316 switch (ed->bmAttributes & UE_XFERTYPE) { 3317 case UE_CONTROL: 3318 pipe->up_methods = &uhci_device_ctrl_methods; 3319 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3320 if (upipe->ctrl.sqh == NULL) 3321 goto bad; 3322 upipe->ctrl.setup = uhci_alloc_std(sc); 3323 if (upipe->ctrl.setup == NULL) { 3324 uhci_free_sqh(sc, upipe->ctrl.sqh); 3325 goto bad; 3326 } 3327 upipe->ctrl.stat = uhci_alloc_std(sc); 3328 if (upipe->ctrl.stat == NULL) { 3329 uhci_free_sqh(sc, upipe->ctrl.sqh); 3330 uhci_free_std(sc, upipe->ctrl.setup); 3331 goto bad; 3332 } 3333 err = usb_allocmem(&sc->sc_bus, 3334 sizeof(usb_device_request_t), 3335 0, &upipe->ctrl.reqdma); 3336 if (err) { 3337 uhci_free_sqh(sc, upipe->ctrl.sqh); 3338 uhci_free_std(sc, upipe->ctrl.setup); 3339 uhci_free_std(sc, upipe->ctrl.stat); 3340 goto bad; 3341 } 3342 break; 3343 case UE_INTERRUPT: 3344 pipe->up_methods = &uhci_device_intr_methods; 3345 ival = pipe->up_interval; 3346 if (ival == USBD_DEFAULT_INTERVAL) 3347 ival = ed->bInterval; 3348 return uhci_device_setintr(sc, upipe, ival); 3349 case UE_ISOCHRONOUS: 3350 pipe->up_methods = &uhci_device_isoc_methods; 3351 return uhci_setup_isoc(pipe); 3352 case UE_BULK: 3353 pipe->up_methods = &uhci_device_bulk_methods; 3354 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3355 if (upipe->bulk.sqh == NULL) 3356 goto bad; 3357 break; 3358 } 3359 } 3360 return USBD_NORMAL_COMPLETION; 3361 3362 bad: 3363 return USBD_NOMEM; 3364 } 3365 3366 /* 3367 * Data structures and routines to emulate the root hub. 3368 */ 3369 /* 3370 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3371 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3372 * should not be used by the USB subsystem. As we cannot issue a 3373 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3374 * will be enabled as part of the reset. 3375 * 3376 * On the VT83C572, the port cannot be successfully enabled until the 3377 * outstanding "port enable change" and "connection status change" 3378 * events have been reset. 3379 */ 3380 Static usbd_status 3381 uhci_portreset(uhci_softc_t *sc, int index) 3382 { 3383 int lim, port, x; 3384 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3385 3386 if (index == 1) 3387 port = UHCI_PORTSC1; 3388 else if (index == 2) 3389 port = UHCI_PORTSC2; 3390 else 3391 return USBD_IOERROR; 3392 3393 x = URWMASK(UREAD2(sc, port)); 3394 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3395 3396 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3397 3398 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3399 UREAD2(sc, port), 0, 0); 3400 3401 x = URWMASK(UREAD2(sc, port)); 3402 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3403 3404 delay(100); 3405 3406 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3407 UREAD2(sc, port), 0, 0); 3408 3409 x = URWMASK(UREAD2(sc, port)); 3410 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3411 3412 for (lim = 10; --lim > 0;) { 3413 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3414 3415 x = UREAD2(sc, port); 3416 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3417 lim, x, 0); 3418 3419 if (!(x & UHCI_PORTSC_CCS)) { 3420 /* 3421 * No device is connected (or was disconnected 3422 * during reset). Consider the port reset. 3423 * The delay must be long enough to ensure on 3424 * the initial iteration that the device 3425 * connection will have been registered. 50ms 3426 * appears to be sufficient, but 20ms is not. 3427 */ 3428 DPRINTFN(3, "uhci port %d loop %u, device detached", 3429 index, lim, 0, 0); 3430 break; 3431 } 3432 3433 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3434 /* 3435 * Port enabled changed and/or connection 3436 * status changed were set. Reset either or 3437 * both raised flags (by writing a 1 to that 3438 * bit), and wait again for state to settle. 3439 */ 3440 UWRITE2(sc, port, URWMASK(x) | 3441 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3442 continue; 3443 } 3444 3445 if (x & UHCI_PORTSC_PE) 3446 /* Port is enabled */ 3447 break; 3448 3449 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3450 } 3451 3452 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3453 UREAD2(sc, port), 0, 0); 3454 3455 if (lim <= 0) { 3456 DPRINTF("uhci port %d reset timed out", index, 3457 0, 0, 0); 3458 return USBD_TIMEOUT; 3459 } 3460 3461 sc->sc_isreset = 1; 3462 return USBD_NORMAL_COMPLETION; 3463 } 3464 3465 Static int 3466 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3467 void *buf, int buflen) 3468 { 3469 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3470 int port, x; 3471 int status, change, totlen = 0; 3472 uint16_t len, value, index; 3473 usb_port_status_t ps; 3474 usbd_status err; 3475 3476 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3477 3478 if (sc->sc_dying) 3479 return -1; 3480 3481 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3482 req->bRequest, 0, 0); 3483 3484 len = UGETW(req->wLength); 3485 value = UGETW(req->wValue); 3486 index = UGETW(req->wIndex); 3487 3488 #define C(x,y) ((x) | ((y) << 8)) 3489 switch (C(req->bRequest, req->bmRequestType)) { 3490 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3491 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3492 if (len == 0) 3493 break; 3494 switch (value) { 3495 case C(0, UDESC_DEVICE): { 3496 usb_device_descriptor_t devd; 3497 3498 totlen = min(buflen, sizeof(devd)); 3499 memcpy(&devd, buf, totlen); 3500 USETW(devd.idVendor, sc->sc_id_vendor); 3501 memcpy(buf, &devd, totlen); 3502 break; 3503 } 3504 case C(1, UDESC_STRING): 3505 #define sd ((usb_string_descriptor_t *)buf) 3506 /* Vendor */ 3507 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3508 break; 3509 case C(2, UDESC_STRING): 3510 /* Product */ 3511 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3512 break; 3513 #undef sd 3514 default: 3515 /* default from usbroothub */ 3516 return buflen; 3517 } 3518 break; 3519 3520 /* Hub requests */ 3521 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3522 break; 3523 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3524 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3525 value, 0, 0); 3526 if (index == 1) 3527 port = UHCI_PORTSC1; 3528 else if (index == 2) 3529 port = UHCI_PORTSC2; 3530 else { 3531 return -1; 3532 } 3533 switch(value) { 3534 case UHF_PORT_ENABLE: 3535 x = URWMASK(UREAD2(sc, port)); 3536 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3537 break; 3538 case UHF_PORT_SUSPEND: 3539 x = URWMASK(UREAD2(sc, port)); 3540 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3541 break; 3542 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3543 /* see USB2 spec ch. 7.1.7.7 */ 3544 usb_delay_ms(&sc->sc_bus, 20); 3545 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3546 /* 10ms resume delay must be provided by caller */ 3547 break; 3548 case UHF_PORT_RESET: 3549 x = URWMASK(UREAD2(sc, port)); 3550 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3551 break; 3552 case UHF_C_PORT_CONNECTION: 3553 x = URWMASK(UREAD2(sc, port)); 3554 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3555 break; 3556 case UHF_C_PORT_ENABLE: 3557 x = URWMASK(UREAD2(sc, port)); 3558 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3559 break; 3560 case UHF_C_PORT_OVER_CURRENT: 3561 x = URWMASK(UREAD2(sc, port)); 3562 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3563 break; 3564 case UHF_C_PORT_RESET: 3565 sc->sc_isreset = 0; 3566 break; 3567 case UHF_PORT_CONNECTION: 3568 case UHF_PORT_OVER_CURRENT: 3569 case UHF_PORT_POWER: 3570 case UHF_PORT_LOW_SPEED: 3571 case UHF_C_PORT_SUSPEND: 3572 default: 3573 return -1; 3574 } 3575 break; 3576 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3577 if (index == 1) 3578 port = UHCI_PORTSC1; 3579 else if (index == 2) 3580 port = UHCI_PORTSC2; 3581 else { 3582 return -1; 3583 } 3584 if (len > 0) { 3585 *(uint8_t *)buf = 3586 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3587 UHCI_PORTSC_LS_SHIFT; 3588 totlen = 1; 3589 } 3590 break; 3591 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3592 if (len == 0) 3593 break; 3594 if ((value & 0xff) != 0) { 3595 return -1; 3596 } 3597 usb_hub_descriptor_t hubd; 3598 3599 totlen = min(buflen, sizeof(hubd)); 3600 memcpy(&hubd, buf, totlen); 3601 hubd.bNbrPorts = 2; 3602 memcpy(buf, &hubd, totlen); 3603 break; 3604 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3605 if (len != 4) { 3606 return -1; 3607 } 3608 memset(buf, 0, len); 3609 totlen = len; 3610 break; 3611 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3612 if (index == 1) 3613 port = UHCI_PORTSC1; 3614 else if (index == 2) 3615 port = UHCI_PORTSC2; 3616 else { 3617 return -1; 3618 } 3619 if (len != 4) { 3620 return -1; 3621 } 3622 x = UREAD2(sc, port); 3623 status = change = 0; 3624 if (x & UHCI_PORTSC_CCS) 3625 status |= UPS_CURRENT_CONNECT_STATUS; 3626 if (x & UHCI_PORTSC_CSC) 3627 change |= UPS_C_CONNECT_STATUS; 3628 if (x & UHCI_PORTSC_PE) 3629 status |= UPS_PORT_ENABLED; 3630 if (x & UHCI_PORTSC_POEDC) 3631 change |= UPS_C_PORT_ENABLED; 3632 if (x & UHCI_PORTSC_OCI) 3633 status |= UPS_OVERCURRENT_INDICATOR; 3634 if (x & UHCI_PORTSC_OCIC) 3635 change |= UPS_C_OVERCURRENT_INDICATOR; 3636 if (x & UHCI_PORTSC_SUSP) 3637 status |= UPS_SUSPEND; 3638 if (x & UHCI_PORTSC_LSDA) 3639 status |= UPS_LOW_SPEED; 3640 status |= UPS_PORT_POWER; 3641 if (sc->sc_isreset) 3642 change |= UPS_C_PORT_RESET; 3643 USETW(ps.wPortStatus, status); 3644 USETW(ps.wPortChange, change); 3645 totlen = min(len, sizeof(ps)); 3646 memcpy(buf, &ps, totlen); 3647 break; 3648 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3649 return -1; 3650 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3651 break; 3652 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3653 if (index == 1) 3654 port = UHCI_PORTSC1; 3655 else if (index == 2) 3656 port = UHCI_PORTSC2; 3657 else { 3658 return -1; 3659 } 3660 switch(value) { 3661 case UHF_PORT_ENABLE: 3662 x = URWMASK(UREAD2(sc, port)); 3663 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3664 break; 3665 case UHF_PORT_SUSPEND: 3666 x = URWMASK(UREAD2(sc, port)); 3667 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3668 break; 3669 case UHF_PORT_RESET: 3670 err = uhci_portreset(sc, index); 3671 if (err != USBD_NORMAL_COMPLETION) 3672 return -1; 3673 return 0; 3674 case UHF_PORT_POWER: 3675 /* Pretend we turned on power */ 3676 return 0; 3677 case UHF_C_PORT_CONNECTION: 3678 case UHF_C_PORT_ENABLE: 3679 case UHF_C_PORT_OVER_CURRENT: 3680 case UHF_PORT_CONNECTION: 3681 case UHF_PORT_OVER_CURRENT: 3682 case UHF_PORT_LOW_SPEED: 3683 case UHF_C_PORT_SUSPEND: 3684 case UHF_C_PORT_RESET: 3685 default: 3686 return -1; 3687 } 3688 break; 3689 default: 3690 /* default from usbroothub */ 3691 DPRINTF("returning %d (usbroothub default)", 3692 buflen, 0, 0, 0); 3693 return buflen; 3694 } 3695 3696 DPRINTF("returning %d", totlen, 0, 0, 0); 3697 3698 return totlen; 3699 } 3700 3701 /* Abort a root interrupt request. */ 3702 void 3703 uhci_root_intr_abort(struct usbd_xfer *xfer) 3704 { 3705 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3706 3707 KASSERT(mutex_owned(&sc->sc_lock)); 3708 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3709 3710 callout_stop(&sc->sc_poll_handle); 3711 sc->sc_intr_xfer = NULL; 3712 3713 xfer->ux_status = USBD_CANCELLED; 3714 #ifdef DIAGNOSTIC 3715 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3716 #endif 3717 usb_transfer_complete(xfer); 3718 } 3719 3720 usbd_status 3721 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3722 { 3723 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3724 usbd_status err; 3725 3726 /* Insert last in queue. */ 3727 mutex_enter(&sc->sc_lock); 3728 err = usb_insert_transfer(xfer); 3729 mutex_exit(&sc->sc_lock); 3730 if (err) 3731 return err; 3732 3733 /* 3734 * Pipe isn't running (otherwise err would be USBD_INPROG), 3735 * start first 3736 */ 3737 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3738 } 3739 3740 /* Start a transfer on the root interrupt pipe */ 3741 usbd_status 3742 uhci_root_intr_start(struct usbd_xfer *xfer) 3743 { 3744 struct usbd_pipe *pipe = xfer->ux_pipe; 3745 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3746 unsigned int ival; 3747 3748 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3749 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3750 xfer->ux_flags, 0); 3751 3752 if (sc->sc_dying) 3753 return USBD_IOERROR; 3754 3755 /* XXX temporary variable needed to avoid gcc3 warning */ 3756 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3757 sc->sc_ival = mstohz(ival); 3758 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3759 sc->sc_intr_xfer = xfer; 3760 return USBD_IN_PROGRESS; 3761 } 3762 3763 /* Close the root interrupt pipe. */ 3764 void 3765 uhci_root_intr_close(struct usbd_pipe *pipe) 3766 { 3767 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3768 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3769 3770 KASSERT(mutex_owned(&sc->sc_lock)); 3771 3772 callout_stop(&sc->sc_poll_handle); 3773 sc->sc_intr_xfer = NULL; 3774 } 3775
Indexes created Tue Sep 30 20:09:53 GMT 2025