uhci.c revision 1.264.4.61
1 /* $NetBSD: uhci.c,v 1.264.4.61 2016/02/16 21:17:27 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.61 2016/02/16 21:17:27 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup; 143 uhci_soft_td_t *stat; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 uhci_soft_qh_t **qhs; 149 } intr; 150 /* Bulk pipe */ 151 struct { 152 uhci_soft_qh_t *sqh; 153 } bulk; 154 /* Isochronous pipe */ 155 struct isoc { 156 uhci_soft_td_t **stds; 157 int next, inuse; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 163 164 Static void uhci_globalreset(uhci_softc_t *); 165 Static usbd_status uhci_portreset(uhci_softc_t*, int); 166 Static void uhci_reset(uhci_softc_t *); 167 Static usbd_status uhci_run(uhci_softc_t *, int, int); 168 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 169 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 170 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 180 uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 182 int, int, uhci_soft_td_t **, uhci_soft_td_t **); 183 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 184 185 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, int *, uhci_soft_td_t **); 187 188 Static void uhci_poll_hub(void *); 189 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 190 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 191 ux_completeq_t *); 192 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 193 194 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 195 196 Static void uhci_timeout(void *); 197 Static void uhci_timeout_task(void *); 198 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 199 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 200 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 201 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 202 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 203 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 204 Static void uhci_add_loop(uhci_softc_t *); 205 Static void uhci_rem_loop(uhci_softc_t *); 206 207 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 208 Static void uhci_device_isoc_enter(struct usbd_xfer *); 209 210 Static struct usbd_xfer * 211 uhci_allocx(struct usbd_bus *, unsigned int); 212 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 213 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 214 Static int uhci_roothub_ctrl(struct usbd_bus *, 215 usb_device_request_t *, void *, int); 216 217 Static int uhci_device_ctrl_init(struct usbd_xfer *); 218 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 219 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 220 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 221 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 222 Static void uhci_device_ctrl_close(struct usbd_pipe *); 223 Static void uhci_device_ctrl_done(struct usbd_xfer *); 224 225 Static int uhci_device_intr_init(struct usbd_xfer *); 226 Static void uhci_device_intr_fini(struct usbd_xfer *); 227 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 228 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 229 Static void uhci_device_intr_abort(struct usbd_xfer *); 230 Static void uhci_device_intr_close(struct usbd_pipe *); 231 Static void uhci_device_intr_done(struct usbd_xfer *); 232 233 Static int uhci_device_bulk_init(struct usbd_xfer *); 234 Static void uhci_device_bulk_fini(struct usbd_xfer *); 235 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 236 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 237 Static void uhci_device_bulk_abort(struct usbd_xfer *); 238 Static void uhci_device_bulk_close(struct usbd_pipe *); 239 Static void uhci_device_bulk_done(struct usbd_xfer *); 240 241 Static int uhci_device_isoc_init(struct usbd_xfer *); 242 Static void uhci_device_isoc_fini(struct usbd_xfer *); 243 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 244 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 245 Static void uhci_device_isoc_abort(struct usbd_xfer *); 246 Static void uhci_device_isoc_close(struct usbd_pipe *); 247 Static void uhci_device_isoc_done(struct usbd_xfer *); 248 249 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 250 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 251 Static void uhci_root_intr_abort(struct usbd_xfer *); 252 Static void uhci_root_intr_close(struct usbd_pipe *); 253 Static void uhci_root_intr_done(struct usbd_xfer *); 254 255 Static usbd_status uhci_open(struct usbd_pipe *); 256 Static void uhci_poll(struct usbd_bus *); 257 Static void uhci_softintr(void *); 258 259 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 260 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 261 Static usbd_status uhci_device_setintr(uhci_softc_t *, 262 struct uhci_pipe *, int); 263 264 Static void uhci_device_clear_toggle(struct usbd_pipe *); 265 Static void uhci_noop(struct usbd_pipe *); 266 267 static inline uhci_soft_qh_t * 268 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 269 270 #ifdef UHCI_DEBUG 271 Static void uhci_dump_all(uhci_softc_t *); 272 Static void uhci_dumpregs(uhci_softc_t *); 273 Static void uhci_dump_qhs(uhci_soft_qh_t *); 274 Static void uhci_dump_qh(uhci_soft_qh_t *); 275 Static void uhci_dump_tds(uhci_soft_td_t *); 276 Static void uhci_dump_td(uhci_soft_td_t *); 277 Static void uhci_dump_ii(struct uhci_xfer *); 278 void uhci_dump(void); 279 #endif 280 281 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 282 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 283 #define UWRITE1(sc, r, x) \ 284 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 285 } while (/*CONSTCOND*/0) 286 #define UWRITE2(sc, r, x) \ 287 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 288 } while (/*CONSTCOND*/0) 289 #define UWRITE4(sc, r, x) \ 290 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 291 } while (/*CONSTCOND*/0) 292 293 static __inline uint8_t 294 UREAD1(uhci_softc_t *sc, bus_size_t r) 295 { 296 297 UBARR(sc); 298 return bus_space_read_1(sc->iot, sc->ioh, r); 299 } 300 301 static __inline uint16_t 302 UREAD2(uhci_softc_t *sc, bus_size_t r) 303 { 304 305 UBARR(sc); 306 return bus_space_read_2(sc->iot, sc->ioh, r); 307 } 308 309 #ifdef UHCI_DEBUG 310 static __inline uint32_t 311 UREAD4(uhci_softc_t *sc, bus_size_t r) 312 { 313 314 UBARR(sc); 315 return bus_space_read_4(sc->iot, sc->ioh, r); 316 } 317 #endif 318 319 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 320 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 321 322 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 323 324 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 325 326 const struct usbd_bus_methods uhci_bus_methods = { 327 .ubm_open = uhci_open, 328 .ubm_softint = uhci_softintr, 329 .ubm_dopoll = uhci_poll, 330 .ubm_allocx = uhci_allocx, 331 .ubm_freex = uhci_freex, 332 .ubm_getlock = uhci_get_lock, 333 .ubm_rhctrl = uhci_roothub_ctrl, 334 }; 335 336 const struct usbd_pipe_methods uhci_root_intr_methods = { 337 .upm_transfer = uhci_root_intr_transfer, 338 .upm_start = uhci_root_intr_start, 339 .upm_abort = uhci_root_intr_abort, 340 .upm_close = uhci_root_intr_close, 341 .upm_cleartoggle = uhci_noop, 342 .upm_done = uhci_root_intr_done, 343 }; 344 345 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 346 .upm_init = uhci_device_ctrl_init, 347 .upm_fini = uhci_device_ctrl_fini, 348 .upm_transfer = uhci_device_ctrl_transfer, 349 .upm_start = uhci_device_ctrl_start, 350 .upm_abort = uhci_device_ctrl_abort, 351 .upm_close = uhci_device_ctrl_close, 352 .upm_cleartoggle = uhci_noop, 353 .upm_done = uhci_device_ctrl_done, 354 }; 355 356 const struct usbd_pipe_methods uhci_device_intr_methods = { 357 .upm_init = uhci_device_intr_init, 358 .upm_fini = uhci_device_intr_fini, 359 .upm_transfer = uhci_device_intr_transfer, 360 .upm_start = uhci_device_intr_start, 361 .upm_abort = uhci_device_intr_abort, 362 .upm_close = uhci_device_intr_close, 363 .upm_cleartoggle = uhci_device_clear_toggle, 364 .upm_done = uhci_device_intr_done, 365 }; 366 367 const struct usbd_pipe_methods uhci_device_bulk_methods = { 368 .upm_init = uhci_device_bulk_init, 369 .upm_fini = uhci_device_bulk_fini, 370 .upm_transfer = uhci_device_bulk_transfer, 371 .upm_start = uhci_device_bulk_start, 372 .upm_abort = uhci_device_bulk_abort, 373 .upm_close = uhci_device_bulk_close, 374 .upm_cleartoggle = uhci_device_clear_toggle, 375 .upm_done = uhci_device_bulk_done, 376 }; 377 378 const struct usbd_pipe_methods uhci_device_isoc_methods = { 379 .upm_init = uhci_device_isoc_init, 380 .upm_fini = uhci_device_isoc_fini, 381 .upm_transfer = uhci_device_isoc_transfer, 382 .upm_start = uhci_device_isoc_start, 383 .upm_abort = uhci_device_isoc_abort, 384 .upm_close = uhci_device_isoc_close, 385 .upm_cleartoggle = uhci_noop, 386 .upm_done = uhci_device_isoc_done, 387 }; 388 389 static inline void 390 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 391 { 392 393 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 394 } 395 396 static inline void 397 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 398 { 399 400 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 401 } 402 403 static inline uhci_soft_qh_t * 404 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 405 { 406 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 407 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 408 409 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 410 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 411 usb_syncmem(&pqh->dma, 412 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 413 sizeof(pqh->qh.qh_hlink), 414 BUS_DMASYNC_POSTWRITE); 415 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 416 printf("uhci_find_prev_qh: QH not found\n"); 417 return NULL; 418 } 419 #endif 420 } 421 return pqh; 422 } 423 424 void 425 uhci_globalreset(uhci_softc_t *sc) 426 { 427 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 428 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 429 UHCICMD(sc, 0); /* do nothing */ 430 } 431 432 int 433 uhci_init(uhci_softc_t *sc) 434 { 435 usbd_status err; 436 int i, j; 437 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 438 uhci_soft_td_t *std; 439 440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 441 442 #ifdef UHCI_DEBUG 443 thesc = sc; 444 445 if (uhcidebug >= 2) 446 uhci_dumpregs(sc); 447 #endif 448 449 sc->sc_suspend = PWR_RESUME; 450 451 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 452 uhci_globalreset(sc); /* reset the controller */ 453 uhci_reset(sc); 454 455 /* Allocate and initialize real frame array. */ 456 err = usb_allocmem(&sc->sc_bus, 457 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 458 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 459 if (err) 460 return err; 461 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 462 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 463 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 464 465 /* Initialise mutex early for uhci_alloc_* */ 466 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 467 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 468 469 /* 470 * Allocate a TD, inactive, that hangs from the last QH. 471 * This is to avoid a bug in the PIIX that makes it run berserk 472 * otherwise. 473 */ 474 std = uhci_alloc_std(sc); 475 if (std == NULL) 476 return ENOMEM; 477 std->link.std = NULL; 478 std->td.td_link = htole32(UHCI_PTR_T); 479 std->td.td_status = htole32(0); /* inactive */ 480 std->td.td_token = htole32(0); 481 std->td.td_buffer = htole32(0); 482 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 486 lsqh = uhci_alloc_sqh(sc); 487 if (lsqh == NULL) 488 goto fail1; 489 lsqh->hlink = NULL; 490 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 491 lsqh->elink = std; 492 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 493 sc->sc_last_qh = lsqh; 494 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 495 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 496 497 /* Allocate the dummy QH where bulk traffic will be queued. */ 498 bsqh = uhci_alloc_sqh(sc); 499 if (bsqh == NULL) 500 goto fail2; 501 bsqh->hlink = lsqh; 502 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 503 bsqh->elink = NULL; 504 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 506 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 509 /* Allocate dummy QH where high speed control traffic will be queued. */ 510 chsqh = uhci_alloc_sqh(sc); 511 if (chsqh == NULL) 512 goto fail3; 513 chsqh->hlink = bsqh; 514 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 515 chsqh->elink = NULL; 516 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 517 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 518 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 521 /* Allocate dummy QH where control traffic will be queued. */ 522 clsqh = uhci_alloc_sqh(sc); 523 if (clsqh == NULL) 524 goto fail4; 525 clsqh->hlink = chsqh; 526 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 527 clsqh->elink = NULL; 528 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 529 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 530 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 533 /* 534 * Make all (virtual) frame list pointers point to the interrupt 535 * queue heads and the interrupt queue heads at the control 536 * queue head and point the physical frame list to the virtual. 537 */ 538 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 539 std = uhci_alloc_std(sc); 540 sqh = uhci_alloc_sqh(sc); 541 if (std == NULL || sqh == NULL) 542 return USBD_NOMEM; 543 std->link.sqh = sqh; 544 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 545 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 546 std->td.td_token = htole32(0); 547 std->td.td_buffer = htole32(0); 548 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 sqh->hlink = clsqh; 551 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 552 sqh->elink = NULL; 553 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 554 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 556 sc->sc_vframes[i].htd = std; 557 sc->sc_vframes[i].etd = std; 558 sc->sc_vframes[i].hqh = sqh; 559 sc->sc_vframes[i].eqh = sqh; 560 for (j = i; 561 j < UHCI_FRAMELIST_COUNT; 562 j += UHCI_VFRAMELIST_COUNT) 563 sc->sc_pframes[j] = htole32(std->physaddr); 564 } 565 usb_syncmem(&sc->sc_dma, 0, 566 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 567 BUS_DMASYNC_PREWRITE); 568 569 570 TAILQ_INIT(&sc->sc_intrhead); 571 572 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 573 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 574 575 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 576 577 cv_init(&sc->sc_softwake_cv, "uhciab"); 578 579 /* Set up the bus struct. */ 580 sc->sc_bus.ub_methods = &uhci_bus_methods; 581 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 582 sc->sc_bus.ub_usedma = true; 583 584 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 585 586 DPRINTF("Enabling...", 0, 0, 0, 0); 587 588 err = uhci_run(sc, 1, 0); /* and here we go... */ 589 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 590 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 591 return err; 592 593 fail4: 594 uhci_free_sqh(sc, chsqh); 595 fail3: 596 uhci_free_sqh(sc, lsqh); 597 fail2: 598 uhci_free_sqh(sc, lsqh); 599 fail1: 600 uhci_free_std(sc, std); 601 602 return ENOMEM; 603 } 604 605 int 606 uhci_activate(device_t self, enum devact act) 607 { 608 struct uhci_softc *sc = device_private(self); 609 610 switch (act) { 611 case DVACT_DEACTIVATE: 612 sc->sc_dying = 1; 613 return 0; 614 default: 615 return EOPNOTSUPP; 616 } 617 } 618 619 void 620 uhci_childdet(device_t self, device_t child) 621 { 622 struct uhci_softc *sc = device_private(self); 623 624 KASSERT(sc->sc_child == child); 625 sc->sc_child = NULL; 626 } 627 628 int 629 uhci_detach(struct uhci_softc *sc, int flags) 630 { 631 int rv = 0; 632 633 if (sc->sc_child != NULL) 634 rv = config_detach(sc->sc_child, flags); 635 636 if (rv != 0) 637 return rv; 638 639 callout_halt(&sc->sc_poll_handle, NULL); 640 callout_destroy(&sc->sc_poll_handle); 641 642 cv_destroy(&sc->sc_softwake_cv); 643 644 mutex_destroy(&sc->sc_lock); 645 mutex_destroy(&sc->sc_intr_lock); 646 647 pool_cache_destroy(sc->sc_xferpool); 648 649 /* XXX free other data structures XXX */ 650 651 return rv; 652 } 653 654 struct usbd_xfer * 655 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 656 { 657 struct uhci_softc *sc = UHCI_BUS2SC(bus); 658 struct usbd_xfer *xfer; 659 660 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 661 if (xfer != NULL) { 662 memset(xfer, 0, sizeof(struct uhci_xfer)); 663 664 #ifdef DIAGNOSTIC 665 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 666 uxfer->ux_isdone = true; 667 xfer->ux_state = XFER_BUSY; 668 #endif 669 } 670 return xfer; 671 } 672 673 void 674 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 675 { 676 struct uhci_softc *sc = UHCI_BUS2SC(bus); 677 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 678 679 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 680 xfer->ux_state); 681 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 682 #ifdef DIAGNOSTIC 683 xfer->ux_state = XFER_FREE; 684 #endif 685 pool_cache_put(sc->sc_xferpool, xfer); 686 } 687 688 Static void 689 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 690 { 691 struct uhci_softc *sc = UHCI_BUS2SC(bus); 692 693 *lock = &sc->sc_lock; 694 } 695 696 697 /* 698 * Handle suspend/resume. 699 * 700 * We need to switch to polling mode here, because this routine is 701 * called from an interrupt context. This is all right since we 702 * are almost suspended anyway. 703 */ 704 bool 705 uhci_resume(device_t dv, const pmf_qual_t *qual) 706 { 707 uhci_softc_t *sc = device_private(dv); 708 int cmd; 709 710 mutex_spin_enter(&sc->sc_intr_lock); 711 712 cmd = UREAD2(sc, UHCI_CMD); 713 sc->sc_bus.ub_usepolling++; 714 UWRITE2(sc, UHCI_INTR, 0); 715 uhci_globalreset(sc); 716 uhci_reset(sc); 717 if (cmd & UHCI_CMD_RS) 718 uhci_run(sc, 0, 1); 719 720 /* restore saved state */ 721 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 722 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 723 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 724 725 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 726 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 727 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 728 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 729 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 730 UHCICMD(sc, UHCI_CMD_MAXP); 731 uhci_run(sc, 1, 1); /* and start traffic again */ 732 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 733 sc->sc_bus.ub_usepolling--; 734 if (sc->sc_intr_xfer != NULL) 735 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 736 sc->sc_intr_xfer); 737 #ifdef UHCI_DEBUG 738 if (uhcidebug >= 2) 739 uhci_dumpregs(sc); 740 #endif 741 742 sc->sc_suspend = PWR_RESUME; 743 mutex_spin_exit(&sc->sc_intr_lock); 744 745 return true; 746 } 747 748 bool 749 uhci_suspend(device_t dv, const pmf_qual_t *qual) 750 { 751 uhci_softc_t *sc = device_private(dv); 752 int cmd; 753 754 mutex_spin_enter(&sc->sc_intr_lock); 755 756 cmd = UREAD2(sc, UHCI_CMD); 757 758 #ifdef UHCI_DEBUG 759 if (uhcidebug >= 2) 760 uhci_dumpregs(sc); 761 #endif 762 if (sc->sc_intr_xfer != NULL) 763 callout_stop(&sc->sc_poll_handle); 764 sc->sc_suspend = PWR_SUSPEND; 765 sc->sc_bus.ub_usepolling++; 766 767 uhci_run(sc, 0, 1); /* stop the controller */ 768 cmd &= ~UHCI_CMD_RS; 769 770 /* save some state if BIOS doesn't */ 771 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 772 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 773 774 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 775 776 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 777 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 778 sc->sc_bus.ub_usepolling--; 779 780 mutex_spin_exit(&sc->sc_intr_lock); 781 782 return true; 783 } 784 785 #ifdef UHCI_DEBUG 786 Static void 787 uhci_dumpregs(uhci_softc_t *sc) 788 { 789 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 790 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 791 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 792 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 793 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 794 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 795 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 796 } 797 798 void 799 uhci_dump_td(uhci_soft_td_t *p) 800 { 801 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 802 803 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 805 806 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 807 DPRINTF(" link=0x%08x status=0x%08x " 808 "token=0x%08x buffer=0x%08x", 809 le32toh(p->td.td_link), 810 le32toh(p->td.td_status), 811 le32toh(p->td.td_token), 812 le32toh(p->td.td_buffer)); 813 814 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 815 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 816 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 817 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 818 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 819 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 820 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 821 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 822 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 823 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 824 DPRINTF("ios =%d ls =%d spd =%d", 825 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 826 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 827 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 828 DPRINTF("errcnt =%d actlen =%d pid=%02x", 829 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 830 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 831 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 832 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 833 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 834 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 835 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 836 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 837 } 838 839 void 840 uhci_dump_qh(uhci_soft_qh_t *sqh) 841 { 842 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 843 844 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 845 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 846 847 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 848 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 849 le32toh(sqh->qh.qh_elink)); 850 851 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 852 } 853 854 855 #if 1 856 void 857 uhci_dump(void) 858 { 859 uhci_dump_all(thesc); 860 } 861 #endif 862 863 void 864 uhci_dump_all(uhci_softc_t *sc) 865 { 866 uhci_dumpregs(sc); 867 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 868 uhci_dump_qhs(sc->sc_lctl_start); 869 } 870 871 872 void 873 uhci_dump_qhs(uhci_soft_qh_t *sqh) 874 { 875 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 876 877 uhci_dump_qh(sqh); 878 879 /* 880 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 881 * Traverses sideways first, then down. 882 * 883 * QH1 884 * QH2 885 * No QH 886 * TD2.1 887 * TD2.2 888 * TD1.1 889 * etc. 890 * 891 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 892 */ 893 894 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 895 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 896 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 897 uhci_dump_qhs(sqh->hlink); 898 else 899 DPRINTF("No QH", 0, 0, 0, 0); 900 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 901 902 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 903 uhci_dump_tds(sqh->elink); 904 else 905 DPRINTF("No QH", 0, 0, 0, 0); 906 } 907 908 void 909 uhci_dump_tds(uhci_soft_td_t *std) 910 { 911 uhci_soft_td_t *td; 912 int stop; 913 914 for (td = std; td != NULL; td = td->link.std) { 915 uhci_dump_td(td); 916 917 /* 918 * Check whether the link pointer in this TD marks 919 * the link pointer as end of queue. This avoids 920 * printing the free list in case the queue/TD has 921 * already been moved there (seatbelt). 922 */ 923 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 924 sizeof(td->td.td_link), 925 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 926 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 927 le32toh(td->td.td_link) == 0); 928 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 929 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 930 if (stop) 931 break; 932 } 933 } 934 935 Static void 936 uhci_dump_ii(struct uhci_xfer *ux) 937 { 938 struct usbd_pipe *pipe; 939 usb_endpoint_descriptor_t *ed; 940 struct usbd_device *dev; 941 942 if (ux == NULL) { 943 printf("ux NULL\n"); 944 return; 945 } 946 pipe = ux->ux_xfer.ux_pipe; 947 if (pipe == NULL) { 948 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 949 return; 950 } 951 if (pipe->up_endpoint == NULL) { 952 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 953 ux, ux->ux_isdone, pipe); 954 return; 955 } 956 if (pipe->up_dev == NULL) { 957 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 958 ux, ux->ux_isdone, pipe); 959 return; 960 } 961 ed = pipe->up_endpoint->ue_edesc; 962 dev = pipe->up_dev; 963 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 964 ux, ux->ux_isdone, dev, 965 UGETW(dev->ud_ddesc.idVendor), 966 UGETW(dev->ud_ddesc.idProduct), 967 dev->ud_addr, pipe, 968 ed->bEndpointAddress, ed->bmAttributes); 969 } 970 971 void uhci_dump_iis(struct uhci_softc *sc); 972 void 973 uhci_dump_iis(struct uhci_softc *sc) 974 { 975 struct uhci_xfer *ux; 976 977 printf("interrupt list:\n"); 978 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 979 uhci_dump_ii(ux); 980 } 981 982 void iidump(void); 983 void iidump(void) { uhci_dump_iis(thesc); } 984 985 #endif 986 987 /* 988 * This routine is executed periodically and simulates interrupts 989 * from the root controller interrupt pipe for port status change. 990 */ 991 void 992 uhci_poll_hub(void *addr) 993 { 994 struct usbd_xfer *xfer = addr; 995 struct usbd_pipe *pipe = xfer->ux_pipe; 996 uhci_softc_t *sc; 997 u_char *p; 998 999 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1000 1001 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1002 return; /* device has detached */ 1003 sc = UHCI_PIPE2SC(pipe); 1004 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1005 1006 p = xfer->ux_buf; 1007 p[0] = 0; 1008 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<1; 1010 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1011 p[0] |= 1<<2; 1012 if (p[0] == 0) 1013 /* No change, try again in a while */ 1014 return; 1015 1016 xfer->ux_actlen = 1; 1017 xfer->ux_status = USBD_NORMAL_COMPLETION; 1018 mutex_enter(&sc->sc_lock); 1019 usb_transfer_complete(xfer); 1020 mutex_exit(&sc->sc_lock); 1021 } 1022 1023 void 1024 uhci_root_intr_done(struct usbd_xfer *xfer) 1025 { 1026 } 1027 1028 /* 1029 * Let the last QH loop back to the high speed control transfer QH. 1030 * This is what intel calls "bandwidth reclamation" and improves 1031 * USB performance a lot for some devices. 1032 * If we are already looping, just count it. 1033 */ 1034 void 1035 uhci_add_loop(uhci_softc_t *sc) 1036 { 1037 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1038 1039 #ifdef UHCI_DEBUG 1040 if (uhcinoloop) 1041 return; 1042 #endif 1043 if (++sc->sc_loops == 1) { 1044 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1045 /* Note, we don't loop back the soft pointer. */ 1046 sc->sc_last_qh->qh.qh_hlink = 1047 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1048 usb_syncmem(&sc->sc_last_qh->dma, 1049 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1050 sizeof(sc->sc_last_qh->qh.qh_hlink), 1051 BUS_DMASYNC_PREWRITE); 1052 } 1053 } 1054 1055 void 1056 uhci_rem_loop(uhci_softc_t *sc) 1057 { 1058 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1059 1060 #ifdef UHCI_DEBUG 1061 if (uhcinoloop) 1062 return; 1063 #endif 1064 if (--sc->sc_loops == 0) { 1065 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1066 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1067 usb_syncmem(&sc->sc_last_qh->dma, 1068 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1069 sizeof(sc->sc_last_qh->qh.qh_hlink), 1070 BUS_DMASYNC_PREWRITE); 1071 } 1072 } 1073 1074 /* Add high speed control QH, called with lock held. */ 1075 void 1076 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1077 { 1078 uhci_soft_qh_t *eqh; 1079 1080 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1081 1082 KASSERT(mutex_owned(&sc->sc_lock)); 1083 1084 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1085 eqh = sc->sc_hctl_end; 1086 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1087 sizeof(eqh->qh.qh_hlink), 1088 BUS_DMASYNC_POSTWRITE); 1089 sqh->hlink = eqh->hlink; 1090 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1091 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1092 BUS_DMASYNC_PREWRITE); 1093 eqh->hlink = sqh; 1094 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1095 sc->sc_hctl_end = sqh; 1096 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1097 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1098 #ifdef UHCI_CTL_LOOP 1099 uhci_add_loop(sc); 1100 #endif 1101 } 1102 1103 /* Remove high speed control QH, called with lock held. */ 1104 void 1105 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1106 { 1107 uhci_soft_qh_t *pqh; 1108 uint32_t elink; 1109 1110 KASSERT(mutex_owned(&sc->sc_lock)); 1111 1112 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1113 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1114 #ifdef UHCI_CTL_LOOP 1115 uhci_rem_loop(sc); 1116 #endif 1117 /* 1118 * The T bit should be set in the elink of the QH so that the HC 1119 * doesn't follow the pointer. This condition may fail if the 1120 * the transferred packet was short so that the QH still points 1121 * at the last used TD. 1122 * In this case we set the T bit and wait a little for the HC 1123 * to stop looking at the TD. 1124 * Note that if the TD chain is large enough, the controller 1125 * may still be looking at the chain at the end of this function. 1126 * uhci_free_std_chain() will make sure the controller stops 1127 * looking at it quickly, but until then we should not change 1128 * sqh->hlink. 1129 */ 1130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1131 sizeof(sqh->qh.qh_elink), 1132 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1133 elink = le32toh(sqh->qh.qh_elink); 1134 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1135 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1136 if (!(elink & UHCI_PTR_T)) { 1137 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1138 usb_syncmem(&sqh->dma, 1139 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1140 sizeof(sqh->qh.qh_elink), 1141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1142 delay(UHCI_QH_REMOVE_DELAY); 1143 } 1144 1145 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1146 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1147 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1148 pqh->hlink = sqh->hlink; 1149 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1150 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1151 sizeof(pqh->qh.qh_hlink), 1152 BUS_DMASYNC_PREWRITE); 1153 delay(UHCI_QH_REMOVE_DELAY); 1154 if (sc->sc_hctl_end == sqh) 1155 sc->sc_hctl_end = pqh; 1156 } 1157 1158 /* Add low speed control QH, called with lock held. */ 1159 void 1160 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1161 { 1162 uhci_soft_qh_t *eqh; 1163 1164 KASSERT(mutex_owned(&sc->sc_lock)); 1165 1166 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1167 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1168 1169 eqh = sc->sc_lctl_end; 1170 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1171 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1172 sqh->hlink = eqh->hlink; 1173 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1174 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1175 BUS_DMASYNC_PREWRITE); 1176 eqh->hlink = sqh; 1177 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1178 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1179 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1180 sc->sc_lctl_end = sqh; 1181 } 1182 1183 /* Remove low speed control QH, called with lock held. */ 1184 void 1185 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1186 { 1187 uhci_soft_qh_t *pqh; 1188 uint32_t elink; 1189 1190 KASSERT(mutex_owned(&sc->sc_lock)); 1191 1192 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1193 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1194 1195 /* See comment in uhci_remove_hs_ctrl() */ 1196 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1197 sizeof(sqh->qh.qh_elink), 1198 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1199 elink = le32toh(sqh->qh.qh_elink); 1200 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1201 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1202 if (!(elink & UHCI_PTR_T)) { 1203 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1204 usb_syncmem(&sqh->dma, 1205 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1206 sizeof(sqh->qh.qh_elink), 1207 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1208 delay(UHCI_QH_REMOVE_DELAY); 1209 } 1210 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1211 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1212 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1213 pqh->hlink = sqh->hlink; 1214 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1215 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1216 sizeof(pqh->qh.qh_hlink), 1217 BUS_DMASYNC_PREWRITE); 1218 delay(UHCI_QH_REMOVE_DELAY); 1219 if (sc->sc_lctl_end == sqh) 1220 sc->sc_lctl_end = pqh; 1221 } 1222 1223 /* Add bulk QH, called with lock held. */ 1224 void 1225 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1226 { 1227 uhci_soft_qh_t *eqh; 1228 1229 KASSERT(mutex_owned(&sc->sc_lock)); 1230 1231 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1232 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1233 1234 eqh = sc->sc_bulk_end; 1235 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1236 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1237 sqh->hlink = eqh->hlink; 1238 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1239 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1240 BUS_DMASYNC_PREWRITE); 1241 eqh->hlink = sqh; 1242 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1243 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1244 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1245 sc->sc_bulk_end = sqh; 1246 uhci_add_loop(sc); 1247 } 1248 1249 /* Remove bulk QH, called with lock held. */ 1250 void 1251 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1252 { 1253 uhci_soft_qh_t *pqh; 1254 1255 KASSERT(mutex_owned(&sc->sc_lock)); 1256 1257 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1258 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1259 1260 uhci_rem_loop(sc); 1261 /* See comment in uhci_remove_hs_ctrl() */ 1262 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1263 sizeof(sqh->qh.qh_elink), 1264 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1265 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1266 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1267 usb_syncmem(&sqh->dma, 1268 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1269 sizeof(sqh->qh.qh_elink), 1270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1271 delay(UHCI_QH_REMOVE_DELAY); 1272 } 1273 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1274 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1275 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1276 pqh->hlink = sqh->hlink; 1277 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1278 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1279 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1280 delay(UHCI_QH_REMOVE_DELAY); 1281 if (sc->sc_bulk_end == sqh) 1282 sc->sc_bulk_end = pqh; 1283 } 1284 1285 Static int uhci_intr1(uhci_softc_t *); 1286 1287 int 1288 uhci_intr(void *arg) 1289 { 1290 uhci_softc_t *sc = arg; 1291 int ret = 0; 1292 1293 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1294 1295 mutex_spin_enter(&sc->sc_intr_lock); 1296 1297 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1298 goto done; 1299 1300 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1301 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1302 goto done; 1303 } 1304 1305 ret = uhci_intr1(sc); 1306 1307 done: 1308 mutex_spin_exit(&sc->sc_intr_lock); 1309 return ret; 1310 } 1311 1312 int 1313 uhci_intr1(uhci_softc_t *sc) 1314 { 1315 int status; 1316 int ack; 1317 1318 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1319 1320 #ifdef UHCI_DEBUG 1321 if (uhcidebug >= 15) { 1322 DPRINTF("sc %p", sc, 0, 0, 0); 1323 uhci_dumpregs(sc); 1324 } 1325 #endif 1326 1327 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1328 1329 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1330 /* Check if the interrupt was for us. */ 1331 if (status == 0) 1332 return 0; 1333 1334 if (sc->sc_suspend != PWR_RESUME) { 1335 #ifdef DIAGNOSTIC 1336 printf("%s: interrupt while not operating ignored\n", 1337 device_xname(sc->sc_dev)); 1338 #endif 1339 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1340 return 0; 1341 } 1342 1343 ack = 0; 1344 if (status & UHCI_STS_USBINT) 1345 ack |= UHCI_STS_USBINT; 1346 if (status & UHCI_STS_USBEI) 1347 ack |= UHCI_STS_USBEI; 1348 if (status & UHCI_STS_RD) { 1349 ack |= UHCI_STS_RD; 1350 #ifdef UHCI_DEBUG 1351 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1352 #endif 1353 } 1354 if (status & UHCI_STS_HSE) { 1355 ack |= UHCI_STS_HSE; 1356 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1357 } 1358 if (status & UHCI_STS_HCPE) { 1359 ack |= UHCI_STS_HCPE; 1360 printf("%s: host controller process error\n", 1361 device_xname(sc->sc_dev)); 1362 } 1363 1364 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1365 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1366 /* no acknowledge needed */ 1367 if (!sc->sc_dying) { 1368 printf("%s: host controller halted\n", 1369 device_xname(sc->sc_dev)); 1370 #ifdef UHCI_DEBUG 1371 uhci_dump_all(sc); 1372 #endif 1373 } 1374 sc->sc_dying = 1; 1375 } 1376 1377 if (!ack) 1378 return 0; /* nothing to acknowledge */ 1379 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1380 1381 usb_schedsoftintr(&sc->sc_bus); 1382 1383 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1384 1385 return 1; 1386 } 1387 1388 void 1389 uhci_softintr(void *v) 1390 { 1391 struct usbd_bus *bus = v; 1392 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1393 struct uhci_xfer *ux, *nextux; 1394 ux_completeq_t cq; 1395 1396 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1397 DPRINTF("sc %p", sc, 0, 0, 0); 1398 1399 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1400 1401 TAILQ_INIT(&cq); 1402 /* 1403 * Interrupts on UHCI really suck. When the host controller 1404 * interrupts because a transfer is completed there is no 1405 * way of knowing which transfer it was. You can scan down 1406 * the TDs and QHs of the previous frame to limit the search, 1407 * but that assumes that the interrupt was not delayed by more 1408 * than 1 ms, which may not always be true (e.g. after debug 1409 * output on a slow console). 1410 * We scan all interrupt descriptors to see if any have 1411 * completed. 1412 */ 1413 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1414 uhci_check_intr(sc, ux, &cq); 1415 } 1416 1417 /* 1418 * We abuse ux_list for the interrupt and complete lists and 1419 * interrupt transfers will get re-added here so use 1420 * the _SAFE version of TAILQ_FOREACH. 1421 */ 1422 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1423 DPRINTF("ux %p", ux, 0, 0, 0); 1424 usb_transfer_complete(&ux->ux_xfer); 1425 } 1426 1427 if (sc->sc_softwake) { 1428 sc->sc_softwake = 0; 1429 cv_broadcast(&sc->sc_softwake_cv); 1430 } 1431 } 1432 1433 /* Check for an interrupt. */ 1434 void 1435 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1436 { 1437 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1438 uint32_t status; 1439 1440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1441 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1442 1443 KASSERT(ux != NULL); 1444 1445 struct usbd_xfer *xfer = &ux->ux_xfer; 1446 if (xfer->ux_status == USBD_CANCELLED || 1447 xfer->ux_status == USBD_TIMEOUT) { 1448 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1449 return; 1450 } 1451 1452 switch (ux->ux_type) { 1453 case UX_CTRL: 1454 fstd = ux->ux_setup; 1455 lstd = ux->ux_stat; 1456 break; 1457 case UX_BULK: 1458 case UX_INTR: 1459 case UX_ISOC: 1460 fstd = ux->ux_stdstart; 1461 lstd = ux->ux_stdend; 1462 break; 1463 default: 1464 KASSERT(false); 1465 break; 1466 } 1467 if (fstd == NULL) 1468 return; 1469 1470 KASSERT(lstd != NULL); 1471 1472 usb_syncmem(&lstd->dma, 1473 lstd->offs + offsetof(uhci_td_t, td_status), 1474 sizeof(lstd->td.td_status), 1475 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1476 status = le32toh(lstd->td.td_status); 1477 usb_syncmem(&lstd->dma, 1478 lstd->offs + offsetof(uhci_td_t, td_status), 1479 sizeof(lstd->td.td_status), 1480 BUS_DMASYNC_PREREAD); 1481 1482 /* If the last TD is not marked active we can complete */ 1483 if (!(status & UHCI_TD_ACTIVE)) { 1484 done: 1485 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1486 1487 callout_stop(&xfer->ux_callout); 1488 uhci_idone(ux, cqp); 1489 return; 1490 } 1491 1492 /* 1493 * If the last TD is still active we need to check whether there 1494 * is an error somewhere in the middle, or whether there was a 1495 * short packet (SPD and not ACTIVE). 1496 */ 1497 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1498 for (std = fstd; std != lstd; std = std->link.std) { 1499 usb_syncmem(&std->dma, 1500 std->offs + offsetof(uhci_td_t, td_status), 1501 sizeof(std->td.td_status), 1502 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1503 status = le32toh(std->td.td_status); 1504 usb_syncmem(&std->dma, 1505 std->offs + offsetof(uhci_td_t, td_status), 1506 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1507 1508 /* If there's an active TD the xfer isn't done. */ 1509 if (status & UHCI_TD_ACTIVE) { 1510 DPRINTFN(12, "ux=%p std=%p still active", 1511 ux, std, 0, 0); 1512 return; 1513 } 1514 1515 /* Any kind of error makes the xfer done. */ 1516 if (status & UHCI_TD_STALLED) 1517 goto done; 1518 1519 /* 1520 * If the data phase of a control transfer is short, we need 1521 * to complete the status stage 1522 */ 1523 1524 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1525 struct uhci_pipe *upipe = 1526 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1527 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1528 uhci_soft_td_t *stat = upipe->ctrl.stat; 1529 1530 DPRINTFN(12, "ux=%p std=%p control status" 1531 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1532 1533 sqh->qh.qh_elink = 1534 htole32(stat->physaddr | UHCI_PTR_TD); 1535 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1536 BUS_DMASYNC_PREWRITE); 1537 break; 1538 } 1539 1540 /* We want short packets, and it is short: it's done */ 1541 usb_syncmem(&std->dma, 1542 std->offs + offsetof(uhci_td_t, td_token), 1543 sizeof(std->td.td_token), 1544 BUS_DMASYNC_POSTWRITE); 1545 1546 if ((status & UHCI_TD_SPD) && 1547 UHCI_TD_GET_ACTLEN(status) < 1548 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1549 goto done; 1550 } 1551 } 1552 } 1553 1554 /* Called with USB lock held. */ 1555 void 1556 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1557 { 1558 struct usbd_xfer *xfer = &ux->ux_xfer; 1559 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1560 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1561 uhci_soft_td_t *std; 1562 uint32_t status = 0, nstatus; 1563 int actlen; 1564 1565 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1566 1567 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1568 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1569 1570 #ifdef DIAGNOSTIC 1571 #ifdef UHCI_DEBUG 1572 if (ux->ux_isdone) { 1573 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1574 uhci_dump_ii(ux); 1575 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1576 } 1577 #endif 1578 KASSERT(!ux->ux_isdone); 1579 ux->ux_isdone = true; 1580 #endif 1581 1582 if (xfer->ux_nframes != 0) { 1583 /* Isoc transfer, do things differently. */ 1584 uhci_soft_td_t **stds = upipe->isoc.stds; 1585 int i, n, nframes, len; 1586 1587 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1588 1589 nframes = xfer->ux_nframes; 1590 actlen = 0; 1591 n = ux->ux_curframe; 1592 for (i = 0; i < nframes; i++) { 1593 std = stds[n]; 1594 #ifdef UHCI_DEBUG 1595 if (uhcidebug >= 5) { 1596 DPRINTF("isoc TD %d", i, 0, 0, 0); 1597 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1598 uhci_dump_td(std); 1599 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1600 } 1601 #endif 1602 if (++n >= UHCI_VFRAMELIST_COUNT) 1603 n = 0; 1604 usb_syncmem(&std->dma, 1605 std->offs + offsetof(uhci_td_t, td_status), 1606 sizeof(std->td.td_status), 1607 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1608 status = le32toh(std->td.td_status); 1609 len = UHCI_TD_GET_ACTLEN(status); 1610 xfer->ux_frlengths[i] = len; 1611 actlen += len; 1612 } 1613 upipe->isoc.inuse -= nframes; 1614 xfer->ux_actlen = actlen; 1615 xfer->ux_status = USBD_NORMAL_COMPLETION; 1616 goto end; 1617 } 1618 1619 #ifdef UHCI_DEBUG 1620 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1621 if (uhcidebug >= 10) { 1622 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1623 uhci_dump_tds(ux->ux_stdstart); 1624 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1625 } 1626 #endif 1627 1628 /* The transfer is done, compute actual length and status. */ 1629 actlen = 0; 1630 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1631 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1632 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1633 nstatus = le32toh(std->td.td_status); 1634 if (nstatus & UHCI_TD_ACTIVE) 1635 break; 1636 1637 status = nstatus; 1638 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1639 UHCI_TD_PID_SETUP) 1640 actlen += UHCI_TD_GET_ACTLEN(status); 1641 else { 1642 /* 1643 * UHCI will report CRCTO in addition to a STALL or NAK 1644 * for a SETUP transaction. See section 3.2.2, "TD 1645 * CONTROL AND STATUS". 1646 */ 1647 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1648 status &= ~UHCI_TD_CRCTO; 1649 } 1650 } 1651 /* If there are left over TDs we need to update the toggle. */ 1652 if (std != NULL) 1653 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1654 1655 status &= UHCI_TD_ERROR; 1656 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1657 xfer->ux_actlen = actlen; 1658 if (status != 0) { 1659 1660 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1661 "error, addr=%d, endpt=0x%02x", 1662 xfer->ux_pipe->up_dev->ud_addr, 1663 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1664 0, 0); 1665 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1666 "bitstuff=%d crcto =%d nak =%d babble =%d", 1667 !!(status & UHCI_TD_BITSTUFF), 1668 !!(status & UHCI_TD_CRCTO), 1669 !!(status & UHCI_TD_NAK), 1670 !!(status & UHCI_TD_BABBLE)); 1671 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1672 "dbuffer =%d stalled =%d active =%d", 1673 !!(status & UHCI_TD_DBUFFER), 1674 !!(status & UHCI_TD_STALLED), 1675 !!(status & UHCI_TD_ACTIVE), 1676 0); 1677 1678 if (status == UHCI_TD_STALLED) 1679 xfer->ux_status = USBD_STALLED; 1680 else 1681 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1682 } else { 1683 xfer->ux_status = USBD_NORMAL_COMPLETION; 1684 } 1685 1686 end: 1687 uhci_del_intr_list(sc, ux); 1688 if (cqp) 1689 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1690 1691 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1692 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1693 } 1694 1695 /* 1696 * Called when a request does not complete. 1697 */ 1698 void 1699 uhci_timeout(void *addr) 1700 { 1701 struct usbd_xfer *xfer = addr; 1702 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1703 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1704 1705 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1706 1707 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1708 1709 if (sc->sc_dying) { 1710 mutex_enter(&sc->sc_lock); 1711 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1712 mutex_exit(&sc->sc_lock); 1713 return; 1714 } 1715 1716 /* Execute the abort in a process context. */ 1717 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1718 USB_TASKQ_MPSAFE); 1719 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1720 USB_TASKQ_HC); 1721 } 1722 1723 void 1724 uhci_timeout_task(void *addr) 1725 { 1726 struct usbd_xfer *xfer = addr; 1727 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1728 1729 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1730 1731 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1732 1733 mutex_enter(&sc->sc_lock); 1734 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1735 mutex_exit(&sc->sc_lock); 1736 } 1737 1738 /* 1739 * Wait here until controller claims to have an interrupt. 1740 * Then call uhci_intr and return. Use timeout to avoid waiting 1741 * too long. 1742 * Only used during boot when interrupts are not enabled yet. 1743 */ 1744 void 1745 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1746 { 1747 int timo = xfer->ux_timeout; 1748 struct uhci_xfer *ux; 1749 1750 mutex_enter(&sc->sc_lock); 1751 1752 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1753 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1754 1755 xfer->ux_status = USBD_IN_PROGRESS; 1756 for (; timo >= 0; timo--) { 1757 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1758 DPRINTFN(20, "0x%04x", 1759 UREAD2(sc, UHCI_STS), 0, 0, 0); 1760 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1761 mutex_spin_enter(&sc->sc_intr_lock); 1762 uhci_intr1(sc); 1763 mutex_spin_exit(&sc->sc_intr_lock); 1764 if (xfer->ux_status != USBD_IN_PROGRESS) 1765 goto done; 1766 } 1767 } 1768 1769 /* Timeout */ 1770 DPRINTF("timeout", 0, 0, 0, 0); 1771 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 1772 if (&ux->ux_xfer == xfer) 1773 break; 1774 1775 KASSERT(ux != NULL); 1776 1777 uhci_idone(ux, NULL); 1778 usb_transfer_complete(&ux->ux_xfer); 1779 1780 done: 1781 mutex_exit(&sc->sc_lock); 1782 } 1783 1784 void 1785 uhci_poll(struct usbd_bus *bus) 1786 { 1787 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1788 1789 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1790 mutex_spin_enter(&sc->sc_intr_lock); 1791 uhci_intr1(sc); 1792 mutex_spin_exit(&sc->sc_intr_lock); 1793 } 1794 } 1795 1796 void 1797 uhci_reset(uhci_softc_t *sc) 1798 { 1799 int n; 1800 1801 UHCICMD(sc, UHCI_CMD_HCRESET); 1802 /* The reset bit goes low when the controller is done. */ 1803 for (n = 0; n < UHCI_RESET_TIMEOUT && 1804 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1805 usb_delay_ms(&sc->sc_bus, 1); 1806 if (n >= UHCI_RESET_TIMEOUT) 1807 printf("%s: controller did not reset\n", 1808 device_xname(sc->sc_dev)); 1809 } 1810 1811 usbd_status 1812 uhci_run(uhci_softc_t *sc, int run, int locked) 1813 { 1814 int n, running; 1815 uint16_t cmd; 1816 1817 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1818 1819 run = run != 0; 1820 if (!locked) 1821 mutex_spin_enter(&sc->sc_intr_lock); 1822 1823 DPRINTF("setting run=%d", run, 0, 0, 0); 1824 cmd = UREAD2(sc, UHCI_CMD); 1825 if (run) 1826 cmd |= UHCI_CMD_RS; 1827 else 1828 cmd &= ~UHCI_CMD_RS; 1829 UHCICMD(sc, cmd); 1830 for (n = 0; n < 10; n++) { 1831 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1832 /* return when we've entered the state we want */ 1833 if (run == running) { 1834 if (!locked) 1835 mutex_spin_exit(&sc->sc_intr_lock); 1836 DPRINTF("done cmd=0x%x sts=0x%x", 1837 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1838 return USBD_NORMAL_COMPLETION; 1839 } 1840 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1841 } 1842 if (!locked) 1843 mutex_spin_exit(&sc->sc_intr_lock); 1844 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1845 run ? "start" : "stop"); 1846 return USBD_IOERROR; 1847 } 1848 1849 /* 1850 * Memory management routines. 1851 * uhci_alloc_std allocates TDs 1852 * uhci_alloc_sqh allocates QHs 1853 * These two routines do their own free list management, 1854 * partly for speed, partly because allocating DMAable memory 1855 * has page size granularity so much memory would be wasted if 1856 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1857 */ 1858 1859 uhci_soft_td_t * 1860 uhci_alloc_std(uhci_softc_t *sc) 1861 { 1862 uhci_soft_td_t *std; 1863 usbd_status err; 1864 int i, offs; 1865 usb_dma_t dma; 1866 1867 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1868 1869 mutex_enter(&sc->sc_lock); 1870 if (sc->sc_freetds == NULL) { 1871 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1872 mutex_exit(&sc->sc_lock); 1873 1874 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1875 UHCI_TD_ALIGN, &dma); 1876 if (err) 1877 return NULL; 1878 1879 mutex_enter(&sc->sc_lock); 1880 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1881 offs = i * UHCI_STD_SIZE; 1882 std = KERNADDR(&dma, offs); 1883 std->physaddr = DMAADDR(&dma, offs); 1884 std->dma = dma; 1885 std->offs = offs; 1886 std->link.std = sc->sc_freetds; 1887 sc->sc_freetds = std; 1888 } 1889 } 1890 std = sc->sc_freetds; 1891 sc->sc_freetds = std->link.std; 1892 mutex_exit(&sc->sc_lock); 1893 1894 memset(&std->td, 0, sizeof(uhci_td_t)); 1895 1896 return std; 1897 } 1898 1899 #define TD_IS_FREE 0x12345678 1900 1901 void 1902 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1903 { 1904 KASSERT(mutex_owned(&sc->sc_lock)); 1905 1906 #ifdef DIAGNOSTIC 1907 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1908 printf("uhci_free_std: freeing free TD %p\n", std); 1909 return; 1910 } 1911 std->td.td_token = htole32(TD_IS_FREE); 1912 #endif 1913 1914 std->link.std = sc->sc_freetds; 1915 sc->sc_freetds = std; 1916 } 1917 1918 void 1919 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1920 { 1921 mutex_enter(&sc->sc_lock); 1922 uhci_free_std_locked(sc, std); 1923 mutex_exit(&sc->sc_lock); 1924 } 1925 1926 uhci_soft_qh_t * 1927 uhci_alloc_sqh(uhci_softc_t *sc) 1928 { 1929 uhci_soft_qh_t *sqh; 1930 usbd_status err; 1931 int i, offs; 1932 usb_dma_t dma; 1933 1934 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1935 1936 mutex_enter(&sc->sc_lock); 1937 if (sc->sc_freeqhs == NULL) { 1938 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1939 mutex_exit(&sc->sc_lock); 1940 1941 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1942 UHCI_QH_ALIGN, &dma); 1943 if (err) 1944 return NULL; 1945 1946 mutex_enter(&sc->sc_lock); 1947 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1948 offs = i * UHCI_SQH_SIZE; 1949 sqh = KERNADDR(&dma, offs); 1950 sqh->physaddr = DMAADDR(&dma, offs); 1951 sqh->dma = dma; 1952 sqh->offs = offs; 1953 sqh->hlink = sc->sc_freeqhs; 1954 sc->sc_freeqhs = sqh; 1955 } 1956 } 1957 sqh = sc->sc_freeqhs; 1958 sc->sc_freeqhs = sqh->hlink; 1959 mutex_exit(&sc->sc_lock); 1960 1961 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1962 1963 return sqh; 1964 } 1965 1966 void 1967 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1968 { 1969 KASSERT(mutex_owned(&sc->sc_lock)); 1970 1971 sqh->hlink = sc->sc_freeqhs; 1972 sc->sc_freeqhs = sqh; 1973 } 1974 1975 void 1976 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1977 uhci_soft_td_t *stdend) 1978 { 1979 uhci_soft_td_t *p; 1980 uint32_t td_link; 1981 1982 /* 1983 * to avoid race condition with the controller which may be looking 1984 * at this chain, we need to first invalidate all links, and 1985 * then wait for the controller to move to another queue 1986 */ 1987 for (p = std; p != stdend; p = p->link.std) { 1988 usb_syncmem(&p->dma, 1989 p->offs + offsetof(uhci_td_t, td_link), 1990 sizeof(p->td.td_link), 1991 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1992 td_link = le32toh(p->td.td_link); 1993 usb_syncmem(&p->dma, 1994 p->offs + offsetof(uhci_td_t, td_link), 1995 sizeof(p->td.td_link), 1996 BUS_DMASYNC_PREREAD); 1997 if ((td_link & UHCI_PTR_T) == 0) { 1998 p->td.td_link = htole32(UHCI_PTR_T); 1999 usb_syncmem(&p->dma, 2000 p->offs + offsetof(uhci_td_t, td_link), 2001 sizeof(p->td.td_link), 2002 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2003 } 2004 } 2005 delay(UHCI_QH_REMOVE_DELAY); 2006 2007 for (; std != stdend; std = p) { 2008 p = std->link.std; 2009 uhci_free_std(sc, std); 2010 } 2011 } 2012 2013 usbd_status 2014 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int alen, 2015 int rd, uhci_soft_td_t **sp, uhci_soft_td_t **ep) 2016 { 2017 uhci_soft_td_t *p, *lastp; 2018 uhci_physaddr_t lastlink; 2019 int i, l, maxp; 2020 int len; 2021 uint32_t status; 2022 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2023 int addr = xfer->ux_pipe->up_dev->ud_addr; 2024 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2025 usb_dma_t *dma = &xfer->ux_dmabuf; 2026 uint16_t flags = xfer->ux_flags; 2027 2028 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2029 2030 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 2031 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 2032 addr, UE_GET_ADDR(endpt), alen, xfer->ux_pipe->up_dev->ud_speed); 2033 2034 ASSERT_SLEEPABLE(); 2035 KASSERT(sp); 2036 2037 len = alen; 2038 maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2039 if (maxp == 0) { 2040 printf("uhci_alloc_std_chain: maxp=0\n"); 2041 return USBD_INVAL; 2042 } 2043 size_t ntd = (len + maxp - 1) / maxp; 2044 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 2045 ntd++; 2046 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 2047 2048 uxfer->ux_stds = NULL; 2049 uxfer->ux_nstd = ntd; 2050 if (ntd == 0) { 2051 *sp = NULL; 2052 if (ep) 2053 *ep = NULL; 2054 DPRINTF("ntd=0", 0, 0, 0, 0); 2055 return USBD_NORMAL_COMPLETION; 2056 } 2057 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2058 KM_SLEEP); 2059 2060 lastp = NULL; 2061 ntd--; 2062 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2063 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_LOW) 2064 status |= UHCI_TD_LS; 2065 if (flags & USBD_SHORT_XFER_OK) 2066 status |= UHCI_TD_SPD; 2067 for (i = ntd; i >= 0; i--) { 2068 p = uhci_alloc_std(sc); 2069 if (p == NULL) { 2070 uhci_free_std_chain(sc, lastp, NULL); 2071 return USBD_NOMEM; 2072 } 2073 uxfer->ux_stds[i] = p; 2074 if (i == ntd) { 2075 /* last TD */ 2076 l = len % maxp; 2077 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 2078 l = maxp; 2079 if (ep) 2080 *ep = p; 2081 lastlink = UHCI_PTR_T; 2082 } else { 2083 l = maxp; 2084 lastlink = p->physaddr; 2085 } 2086 p->link.std = lastp; 2087 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 2088 p->td.td_status = htole32(status); 2089 p->td.td_token = htole32( 2090 (rd ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2091 UHCI_TD_SET_MAXLEN(l) | 2092 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2093 UHCI_TD_SET_DEVADDR(addr) 2094 ); 2095 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2096 DPRINTF("std %p link 0x%08x status 0x%08x token 0x%08x", 2097 p, le32toh(p->td.td_link), le32toh(p->td.td_status), 2098 le32toh(p->td.td_token)); 2099 2100 lastp = p; 2101 } 2102 *sp = lastp; 2103 2104 return USBD_NORMAL_COMPLETION; 2105 } 2106 2107 Static void 2108 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2109 { 2110 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2111 2112 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2113 2114 mutex_enter(&sc->sc_lock); 2115 for (size_t i = 0; i < ux->ux_nstd; i++) { 2116 uhci_soft_td_t *std = ux->ux_stds[i]; 2117 #ifdef DIAGNOSTIC 2118 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2119 printf("uhci_free_std: freeing free TD %p\n", std); 2120 return; 2121 } 2122 std->td.td_token = htole32(TD_IS_FREE); 2123 #endif 2124 ux->ux_stds[i]->link.std = sc->sc_freetds; 2125 sc->sc_freetds = std; 2126 } 2127 mutex_exit(&sc->sc_lock); 2128 } 2129 2130 2131 Static void 2132 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2133 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2134 { 2135 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2136 struct usbd_pipe *pipe = xfer->ux_pipe; 2137 usb_dma_t *dma = &xfer->ux_dmabuf; 2138 uint16_t flags = xfer->ux_flags; 2139 uhci_soft_td_t *std, *prev; 2140 int len = length; 2141 int tog = *toggle; 2142 int maxp; 2143 uint32_t status; 2144 size_t i; 2145 2146 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2147 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2148 len, isread, *toggle); 2149 2150 KASSERT(len != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2151 2152 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2153 KASSERT(maxp != 0); 2154 2155 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2156 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2157 status |= UHCI_TD_LS; 2158 if (flags & USBD_SHORT_XFER_OK) 2159 status |= UHCI_TD_SPD; 2160 usb_syncmem(dma, 0, len, 2161 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2162 2163 std = prev = NULL; 2164 for (i = 0; i < uxfer->ux_nstd; i++, prev = std) { 2165 int l = len; 2166 std = uxfer->ux_stds[i]; 2167 if (l > maxp) 2168 l = maxp; 2169 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 2170 break; 2171 2172 if (prev) { 2173 prev->link.std = std; 2174 prev->td.td_link = htole32( 2175 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2176 ); 2177 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2178 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2179 } 2180 2181 int addr __diagused = xfer->ux_pipe->up_dev->ud_addr; 2182 int endpt __diagused = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2183 KASSERTMSG(UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)) == UE_GET_ADDR(endpt), 2184 "%" __PRIuBIT " vs %d (0x%08x) in %p", 2185 UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)), 2186 UE_GET_ADDR(endpt), le32toh(std->td.td_token), std); 2187 KASSERTMSG(UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)) == addr, 2188 "%" __PRIuBIT " vs %d (0x%08x) in %p", 2189 UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)), addr, 2190 le32toh(std->td.td_token), std); 2191 2192 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2194 2195 std->td.td_status = htole32(status); 2196 std->td.td_token &= ~htole32( 2197 UHCI_TD_PID_MASK | 2198 UHCI_TD_DT_MASK | 2199 UHCI_TD_MAXLEN_MASK 2200 ); 2201 std->td.td_token |= htole32( 2202 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2203 UHCI_TD_SET_DT(tog) | 2204 UHCI_TD_SET_MAXLEN(l) 2205 ); 2206 std->td.td_link &= ~htole32(UHCI_PTR_T); 2207 2208 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2210 tog ^= 1; 2211 2212 len -= l; 2213 if (len == 0) 2214 break; 2215 } 2216 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2217 xfer, length, len, maxp, uxfer->ux_nstd, i); 2218 2219 if (i < uxfer->ux_nstd) { 2220 /* 2221 * The full allocation chain wasn't used, so we need to 2222 * terminate it. 2223 */ 2224 std->link.std = NULL; 2225 std->td.td_link = htole32(UHCI_PTR_T); 2226 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2228 } 2229 *lstd = std; 2230 *toggle = tog; 2231 } 2232 2233 void 2234 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2235 { 2236 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2237 upipe->nexttoggle = 0; 2238 } 2239 2240 void 2241 uhci_noop(struct usbd_pipe *pipe) 2242 { 2243 } 2244 2245 int 2246 uhci_device_bulk_init(struct usbd_xfer *xfer) 2247 { 2248 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2249 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2250 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2251 int endpt = ed->bEndpointAddress; 2252 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2253 int len = xfer->ux_bufsize; 2254 int err = 0; 2255 2256 2257 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2258 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2259 2260 if (sc->sc_dying) 2261 return USBD_IOERROR; 2262 2263 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2264 2265 uxfer->ux_type = UX_BULK; 2266 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart, 2267 &uxfer->ux_stdend); 2268 if (err) 2269 return err; 2270 2271 #ifdef UHCI_DEBUG 2272 if (uhcidebug >= 10) { 2273 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2274 uhci_dump_tds(uxfer->ux_stdstart); 2275 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2276 } 2277 #endif 2278 2279 return 0; 2280 } 2281 2282 Static void 2283 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2284 { 2285 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2286 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2287 2288 KASSERT(ux->ux_type == UX_BULK); 2289 2290 uhci_free_stds(sc, ux); 2291 if (ux->ux_nstd) 2292 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2293 } 2294 2295 usbd_status 2296 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2297 { 2298 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2299 usbd_status err; 2300 2301 /* Insert last in queue. */ 2302 mutex_enter(&sc->sc_lock); 2303 err = usb_insert_transfer(xfer); 2304 mutex_exit(&sc->sc_lock); 2305 if (err) 2306 return err; 2307 2308 /* 2309 * Pipe isn't running (otherwise err would be USBD_INPROG), 2310 * so start it first. 2311 */ 2312 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2313 } 2314 2315 usbd_status 2316 uhci_device_bulk_start(struct usbd_xfer *xfer) 2317 { 2318 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2319 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2320 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2321 uhci_soft_td_t *data, *dataend; 2322 uhci_soft_qh_t *sqh; 2323 int len; 2324 int endpt; 2325 int isread; 2326 2327 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2328 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2329 xfer->ux_flags, 0); 2330 2331 if (sc->sc_dying) 2332 return USBD_IOERROR; 2333 2334 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2335 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2336 2337 len = xfer->ux_length; 2338 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2339 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2340 sqh = upipe->bulk.sqh; 2341 2342 /* Take lock here to protect nexttoggle */ 2343 mutex_enter(&sc->sc_lock); 2344 2345 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2346 &dataend); 2347 2348 data = ux->ux_stdstart; 2349 ux->ux_stdend = dataend; 2350 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2351 usb_syncmem(&dataend->dma, 2352 dataend->offs + offsetof(uhci_td_t, td_status), 2353 sizeof(dataend->td.td_status), 2354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2355 2356 #ifdef UHCI_DEBUG 2357 if (uhcidebug >= 10) { 2358 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2359 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2360 uhci_dump_tds(data); 2361 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2362 } 2363 #endif 2364 2365 KASSERT(ux->ux_isdone); 2366 #ifdef DIAGNOSTIC 2367 ux->ux_isdone = false; 2368 #endif 2369 2370 sqh->elink = data; 2371 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2372 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2373 2374 uhci_add_bulk(sc, sqh); 2375 uhci_add_intr_list(sc, ux); 2376 2377 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2378 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2379 uhci_timeout, xfer); 2380 } 2381 xfer->ux_status = USBD_IN_PROGRESS; 2382 mutex_exit(&sc->sc_lock); 2383 2384 if (sc->sc_bus.ub_usepolling) 2385 uhci_waitintr(sc, xfer); 2386 2387 return USBD_IN_PROGRESS; 2388 } 2389 2390 /* Abort a device bulk request. */ 2391 void 2392 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2393 { 2394 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2395 2396 KASSERT(mutex_owned(&sc->sc_lock)); 2397 2398 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2399 2400 uhci_abort_xfer(xfer, USBD_CANCELLED); 2401 } 2402 2403 /* 2404 * Abort a device request. 2405 * If this routine is called at splusb() it guarantees that the request 2406 * will be removed from the hardware scheduling and that the callback 2407 * for it will be called with USBD_CANCELLED status. 2408 * It's impossible to guarantee that the requested transfer will not 2409 * have happened since the hardware runs concurrently. 2410 * If the transaction has already happened we rely on the ordinary 2411 * interrupt processing to process it. 2412 * XXX This is most probably wrong. 2413 * XXXMRG this doesn't make sense anymore. 2414 */ 2415 void 2416 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2417 { 2418 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2419 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2420 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2421 uhci_soft_td_t *std; 2422 int wake; 2423 2424 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2425 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2426 2427 KASSERT(mutex_owned(&sc->sc_lock)); 2428 ASSERT_SLEEPABLE(); 2429 2430 if (sc->sc_dying) { 2431 /* If we're dying, just do the software part. */ 2432 xfer->ux_status = status; /* make software ignore it */ 2433 callout_stop(&xfer->ux_callout); 2434 usb_transfer_complete(xfer); 2435 return; 2436 } 2437 2438 /* 2439 * If an abort is already in progress then just wait for it to 2440 * complete and return. 2441 */ 2442 if (xfer->ux_hcflags & UXFER_ABORTING) { 2443 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2444 #ifdef DIAGNOSTIC 2445 if (status == USBD_TIMEOUT) 2446 printf("uhci_abort_xfer: TIMEOUT while aborting\n"); 2447 #endif 2448 /* Override the status which might be USBD_TIMEOUT. */ 2449 xfer->ux_status = status; 2450 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2451 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2452 while (xfer->ux_hcflags & UXFER_ABORTING) 2453 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2454 goto done; 2455 } 2456 xfer->ux_hcflags |= UXFER_ABORTING; 2457 2458 /* 2459 * Step 1: Make interrupt routine and hardware ignore xfer. 2460 */ 2461 xfer->ux_status = status; /* make software ignore it */ 2462 callout_stop(&xfer->ux_callout); 2463 uhci_del_intr_list(sc, ux); 2464 2465 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2466 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2467 usb_syncmem(&std->dma, 2468 std->offs + offsetof(uhci_td_t, td_status), 2469 sizeof(std->td.td_status), 2470 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2471 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2472 usb_syncmem(&std->dma, 2473 std->offs + offsetof(uhci_td_t, td_status), 2474 sizeof(std->td.td_status), 2475 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2476 } 2477 2478 /* 2479 * Step 2: Wait until we know hardware has finished any possible 2480 * use of the xfer. Also make sure the soft interrupt routine 2481 * has run. 2482 */ 2483 /* Hardware finishes in 1ms */ 2484 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2485 sc->sc_softwake = 1; 2486 usb_schedsoftintr(&sc->sc_bus); 2487 DPRINTF("cv_wait", 0, 0, 0, 0); 2488 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2489 2490 /* 2491 * Step 3: Execute callback. 2492 */ 2493 DPRINTF("callback", 0, 0, 0, 0); 2494 #ifdef DIAGNOSTIC 2495 ux->ux_isdone = true; 2496 #endif 2497 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2498 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2499 usb_transfer_complete(xfer); 2500 if (wake) 2501 cv_broadcast(&xfer->ux_hccv); 2502 done: 2503 KASSERT(mutex_owned(&sc->sc_lock)); 2504 } 2505 2506 /* Close a device bulk pipe. */ 2507 void 2508 uhci_device_bulk_close(struct usbd_pipe *pipe) 2509 { 2510 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2511 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2512 2513 KASSERT(mutex_owned(&sc->sc_lock)); 2514 2515 uhci_free_sqh(sc, upipe->bulk.sqh); 2516 2517 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2518 } 2519 2520 int 2521 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2522 { 2523 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2524 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2525 usb_device_request_t *req = &xfer->ux_request; 2526 struct usbd_device *dev = upipe->pipe.up_dev; 2527 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2528 int addr = dev->ud_addr; 2529 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2530 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2531 int len; 2532 uint32_t ls; 2533 usbd_status err; 2534 int isread; 2535 2536 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2537 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", xfer->ux_bufsize, 2538 dev->ud_addr, endpt, 0); 2539 2540 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2541 isread = req->bmRequestType & UT_READ; 2542 len = xfer->ux_bufsize; 2543 2544 uxfer->ux_type = UX_CTRL; 2545 setup = upipe->ctrl.setup; 2546 stat = upipe->ctrl.stat; 2547 2548 /* Set up data transaction */ 2549 if (len != 0) { 2550 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data, 2551 &dataend); 2552 if (err) 2553 return err; 2554 next = data; 2555 dataend->link.std = stat; 2556 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2557 } else { 2558 next = stat; 2559 } 2560 2561 setup->link.std = next; 2562 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2563 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2564 UHCI_TD_ACTIVE); 2565 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2566 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2567 2568 stat->link.std = NULL; 2569 stat->td.td_link = htole32(UHCI_PTR_T); 2570 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2571 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2572 stat->td.td_token = 2573 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2574 UHCI_TD_IN (0, endpt, addr, 1)); 2575 stat->td.td_buffer = htole32(0); 2576 2577 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2578 #ifdef UHCI_DEBUG 2579 if (uhcidebug >= 10) { 2580 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2581 uhci_dump_tds(setup); 2582 } 2583 #endif 2584 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2585 2586 /* Set up interrupt info. */ 2587 uxfer->ux_setup = setup; 2588 uxfer->ux_data = data; 2589 uxfer->ux_stat = stat; 2590 2591 return 0; 2592 } 2593 2594 Static void 2595 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2596 { 2597 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2598 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2599 2600 KASSERT(ux->ux_type == UX_CTRL); 2601 2602 uhci_free_stds(sc, ux); 2603 if (ux->ux_nstd) 2604 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2605 } 2606 2607 usbd_status 2608 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2609 { 2610 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2611 usbd_status err; 2612 2613 /* Insert last in queue. */ 2614 mutex_enter(&sc->sc_lock); 2615 err = usb_insert_transfer(xfer); 2616 mutex_exit(&sc->sc_lock); 2617 if (err) 2618 return err; 2619 2620 /* 2621 * Pipe isn't running (otherwise err would be USBD_INPROG), 2622 * so start it first. 2623 */ 2624 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2625 } 2626 2627 usbd_status 2628 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2629 { 2630 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2631 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2632 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2633 usb_device_request_t *req = &xfer->ux_request; 2634 struct usbd_device *dev = upipe->pipe.up_dev; 2635 int addr = dev->ud_addr; 2636 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2637 uhci_soft_td_t *setup, *stat, *next, *dataend; 2638 uhci_soft_qh_t *sqh; 2639 int len; 2640 uint32_t ls; 2641 int isread; 2642 2643 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2644 2645 if (sc->sc_dying) 2646 return USBD_IOERROR; 2647 2648 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2649 2650 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2651 "wValue=0x%04x, wIndex=0x%04x", 2652 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2653 UGETW(req->wIndex)); 2654 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2655 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2656 2657 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2658 isread = req->bmRequestType & UT_READ; 2659 len = UGETW(req->wLength); 2660 2661 setup = upipe->ctrl.setup; 2662 stat = upipe->ctrl.stat; 2663 sqh = upipe->ctrl.sqh; 2664 2665 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2666 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2667 2668 mutex_enter(&sc->sc_lock); 2669 2670 /* Set up data transaction */ 2671 if (len != 0) { 2672 upipe->nexttoggle = 1; 2673 next = uxfer->ux_data; 2674 uhci_reset_std_chain(sc, xfer, len, isread, 2675 &upipe->nexttoggle, &dataend); 2676 dataend->link.std = stat; 2677 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2678 usb_syncmem(&dataend->dma, 2679 dataend->offs + offsetof(uhci_td_t, td_link), 2680 sizeof(dataend->td.td_link), 2681 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2682 } else { 2683 next = stat; 2684 } 2685 2686 setup->link.std = next; 2687 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2688 setup->td.td_status |= htole32( 2689 UHCI_TD_SET_ERRCNT(3) | 2690 ls | 2691 UHCI_TD_ACTIVE 2692 ); 2693 setup->td.td_token &= ~htole32(UHCI_TD_MAXLEN_MASK); 2694 setup->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(sizeof(*req))); 2695 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2696 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2697 2698 stat->link.std = NULL; 2699 stat->td.td_link = htole32(UHCI_PTR_T); 2700 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2701 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2702 stat->td.td_token = 2703 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2704 UHCI_TD_IN (0, endpt, addr, 1)); 2705 stat->td.td_buffer = htole32(0); 2706 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2707 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2708 2709 #ifdef UHCI_DEBUG 2710 if (uhcidebug >= 10) { 2711 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2712 DPRINTF("before transfer", 0, 0, 0, 0); 2713 uhci_dump_tds(setup); 2714 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2715 } 2716 #endif 2717 2718 /* Set up interrupt info. */ 2719 uxfer->ux_setup = setup; 2720 uxfer->ux_stat = stat; 2721 KASSERT(uxfer->ux_isdone); 2722 #ifdef DIAGNOSTIC 2723 uxfer->ux_isdone = false; 2724 #endif 2725 2726 sqh->elink = setup; 2727 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2728 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2729 2730 if (dev->ud_speed == USB_SPEED_LOW) 2731 uhci_add_ls_ctrl(sc, sqh); 2732 else 2733 uhci_add_hs_ctrl(sc, sqh); 2734 uhci_add_intr_list(sc, uxfer); 2735 #ifdef UHCI_DEBUG 2736 if (uhcidebug >= 12) { 2737 uhci_soft_td_t *std; 2738 uhci_soft_qh_t *xqh; 2739 uhci_soft_qh_t *sxqh; 2740 int maxqh = 0; 2741 uhci_physaddr_t link; 2742 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2743 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2744 for (std = sc->sc_vframes[0].htd, link = 0; 2745 (link & UHCI_PTR_QH) == 0; 2746 std = std->link.std) { 2747 link = le32toh(std->td.td_link); 2748 uhci_dump_td(std); 2749 } 2750 sxqh = (uhci_soft_qh_t *)std; 2751 uhci_dump_qh(sxqh); 2752 for (xqh = sxqh; 2753 xqh != NULL; 2754 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2755 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2756 uhci_dump_qh(xqh); 2757 } 2758 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2759 uhci_dump_qh(sqh); 2760 uhci_dump_tds(sqh->elink); 2761 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2762 } 2763 #endif 2764 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2765 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2766 uhci_timeout, xfer); 2767 } 2768 xfer->ux_status = USBD_IN_PROGRESS; 2769 mutex_exit(&sc->sc_lock); 2770 2771 if (sc->sc_bus.ub_usepolling) 2772 uhci_waitintr(sc, xfer); 2773 2774 return USBD_IN_PROGRESS; 2775 } 2776 2777 int 2778 uhci_device_intr_init(struct usbd_xfer *xfer) 2779 { 2780 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2781 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2782 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2783 int endpt = ed->bEndpointAddress; 2784 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2785 int len = xfer->ux_bufsize; 2786 int err; 2787 2788 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2789 2790 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2791 xfer->ux_flags, 0); 2792 2793 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2794 KASSERT(len != 0); 2795 2796 ux->ux_type = UX_INTR; 2797 ux->ux_nstd = 0; 2798 err = uhci_alloc_std_chain(sc, xfer, len, isread, 2799 &ux->ux_stdstart, &ux->ux_stdend); 2800 2801 return err; 2802 } 2803 2804 Static void 2805 uhci_device_intr_fini(struct usbd_xfer *xfer) 2806 { 2807 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2808 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2809 2810 KASSERT(ux->ux_type == UX_INTR); 2811 2812 uhci_free_stds(sc, ux); 2813 if (ux->ux_nstd) 2814 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2815 } 2816 2817 usbd_status 2818 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2819 { 2820 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2821 usbd_status err; 2822 2823 /* Insert last in queue. */ 2824 mutex_enter(&sc->sc_lock); 2825 err = usb_insert_transfer(xfer); 2826 mutex_exit(&sc->sc_lock); 2827 if (err) 2828 return err; 2829 2830 /* 2831 * Pipe isn't running (otherwise err would be USBD_INPROG), 2832 * so start it first. 2833 */ 2834 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2835 } 2836 2837 usbd_status 2838 uhci_device_intr_start(struct usbd_xfer *xfer) 2839 { 2840 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2841 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2842 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2843 uhci_soft_td_t *data, *dataend; 2844 uhci_soft_qh_t *sqh; 2845 int isread, endpt; 2846 int i; 2847 2848 if (sc->sc_dying) 2849 return USBD_IOERROR; 2850 2851 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2852 2853 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2854 xfer->ux_flags, 0); 2855 2856 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2857 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2858 2859 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2860 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2861 2862 data = ux->ux_stdstart; 2863 2864 KASSERT(ux->ux_isdone); 2865 #ifdef DIAGNOSTIC 2866 ux->ux_isdone = false; 2867 #endif 2868 2869 /* Take lock to protect nexttoggle */ 2870 mutex_enter(&sc->sc_lock); 2871 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2872 &upipe->nexttoggle, &dataend); 2873 2874 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2875 usb_syncmem(&dataend->dma, 2876 dataend->offs + offsetof(uhci_td_t, td_status), 2877 sizeof(dataend->td.td_status), 2878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2879 ux->ux_stdend = dataend; 2880 2881 #ifdef UHCI_DEBUG 2882 if (uhcidebug >= 10) { 2883 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2884 uhci_dump_tds(data); 2885 uhci_dump_qh(upipe->intr.qhs[0]); 2886 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2887 } 2888 #endif 2889 2890 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2891 for (i = 0; i < upipe->intr.npoll; i++) { 2892 sqh = upipe->intr.qhs[i]; 2893 sqh->elink = data; 2894 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2895 usb_syncmem(&sqh->dma, 2896 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2897 sizeof(sqh->qh.qh_elink), 2898 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2899 } 2900 uhci_add_intr_list(sc, ux); 2901 xfer->ux_status = USBD_IN_PROGRESS; 2902 mutex_exit(&sc->sc_lock); 2903 2904 #ifdef UHCI_DEBUG 2905 if (uhcidebug >= 10) { 2906 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2907 uhci_dump_tds(data); 2908 uhci_dump_qh(upipe->intr.qhs[0]); 2909 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2910 } 2911 #endif 2912 2913 return USBD_IN_PROGRESS; 2914 } 2915 2916 /* Abort a device control request. */ 2917 void 2918 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2919 { 2920 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2921 2922 KASSERT(mutex_owned(&sc->sc_lock)); 2923 2924 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2925 uhci_abort_xfer(xfer, USBD_CANCELLED); 2926 } 2927 2928 /* Close a device control pipe. */ 2929 void 2930 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2931 { 2932 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2933 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2934 2935 uhci_free_sqh(sc, upipe->ctrl.sqh); 2936 uhci_free_std_locked(sc, upipe->ctrl.setup); 2937 uhci_free_std_locked(sc, upipe->ctrl.stat); 2938 2939 } 2940 2941 /* Abort a device interrupt request. */ 2942 void 2943 uhci_device_intr_abort(struct usbd_xfer *xfer) 2944 { 2945 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2946 2947 KASSERT(mutex_owned(&sc->sc_lock)); 2948 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2949 2950 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2951 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2952 2953 uhci_abort_xfer(xfer, USBD_CANCELLED); 2954 } 2955 2956 /* Close a device interrupt pipe. */ 2957 void 2958 uhci_device_intr_close(struct usbd_pipe *pipe) 2959 { 2960 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2961 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2962 int i, npoll; 2963 2964 KASSERT(mutex_owned(&sc->sc_lock)); 2965 2966 /* Unlink descriptors from controller data structures. */ 2967 npoll = upipe->intr.npoll; 2968 for (i = 0; i < npoll; i++) 2969 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2970 2971 /* 2972 * We now have to wait for any activity on the physical 2973 * descriptors to stop. 2974 */ 2975 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2976 2977 for (i = 0; i < npoll; i++) 2978 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2979 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2980 } 2981 2982 int 2983 uhci_device_isoc_init(struct usbd_xfer *xfer) 2984 { 2985 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2986 2987 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2988 KASSERT(xfer->ux_nframes != 0); 2989 KASSERT(ux->ux_isdone); 2990 2991 ux->ux_type = UX_ISOC; 2992 return 0; 2993 } 2994 2995 Static void 2996 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2997 { 2998 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2999 3000 KASSERT(ux->ux_type == UX_ISOC); 3001 } 3002 3003 usbd_status 3004 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 3005 { 3006 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3007 usbd_status err; 3008 3009 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3010 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3011 3012 /* Put it on our queue, */ 3013 mutex_enter(&sc->sc_lock); 3014 err = usb_insert_transfer(xfer); 3015 mutex_exit(&sc->sc_lock); 3016 3017 /* bail out on error, */ 3018 if (err && err != USBD_IN_PROGRESS) 3019 return err; 3020 3021 /* XXX should check inuse here */ 3022 3023 /* insert into schedule, */ 3024 uhci_device_isoc_enter(xfer); 3025 3026 /* and start if the pipe wasn't running */ 3027 if (!err) 3028 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3029 3030 return err; 3031 } 3032 3033 void 3034 uhci_device_isoc_enter(struct usbd_xfer *xfer) 3035 { 3036 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3037 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3038 struct isoc *isoc = &upipe->isoc; 3039 uhci_soft_td_t *std; 3040 uint32_t buf, len, status, offs; 3041 int i, next, nframes; 3042 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3043 3044 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3045 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 3046 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3047 3048 if (sc->sc_dying) 3049 return; 3050 3051 if (xfer->ux_status == USBD_IN_PROGRESS) { 3052 /* This request has already been entered into the frame list */ 3053 printf("uhci_device_isoc_enter: xfer=%p in frame list\n", xfer); 3054 /* XXX */ 3055 } 3056 3057 #ifdef DIAGNOSTIC 3058 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 3059 printf("uhci_device_isoc_enter: overflow!\n"); 3060 #endif 3061 3062 next = isoc->next; 3063 if (next == -1) { 3064 /* Not in use yet, schedule it a few frames ahead. */ 3065 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 3066 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 3067 } 3068 3069 xfer->ux_status = USBD_IN_PROGRESS; 3070 UHCI_XFER2UXFER(xfer)->ux_curframe = next; 3071 3072 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3073 offs = 0; 3074 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 3075 UHCI_TD_ACTIVE | 3076 UHCI_TD_IOS); 3077 nframes = xfer->ux_nframes; 3078 mutex_enter(&sc->sc_lock); 3079 for (i = 0; i < nframes; i++) { 3080 std = isoc->stds[next]; 3081 if (++next >= UHCI_VFRAMELIST_COUNT) 3082 next = 0; 3083 len = xfer->ux_frlengths[i]; 3084 std->td.td_buffer = htole32(buf); 3085 usb_syncmem(&xfer->ux_dmabuf, offs, len, 3086 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3087 if (i == nframes - 1) 3088 status |= UHCI_TD_IOC; 3089 std->td.td_status = htole32(status); 3090 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 3091 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 3092 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3093 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3094 #ifdef UHCI_DEBUG 3095 if (uhcidebug >= 5) { 3096 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3097 DPRINTF("TD %d", i, 0, 0, 0); 3098 uhci_dump_td(std); 3099 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3100 } 3101 #endif 3102 buf += len; 3103 offs += len; 3104 } 3105 isoc->next = next; 3106 isoc->inuse += xfer->ux_nframes; 3107 3108 mutex_exit(&sc->sc_lock); 3109 } 3110 3111 usbd_status 3112 uhci_device_isoc_start(struct usbd_xfer *xfer) 3113 { 3114 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3115 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3116 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3117 uhci_soft_td_t *end; 3118 int i; 3119 3120 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3121 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3122 3123 mutex_enter(&sc->sc_lock); 3124 3125 if (sc->sc_dying) { 3126 mutex_exit(&sc->sc_lock); 3127 return USBD_IOERROR; 3128 } 3129 3130 #ifdef DIAGNOSTIC 3131 if (xfer->ux_status != USBD_IN_PROGRESS) 3132 printf("uhci_device_isoc_start: not in progress %p\n", xfer); 3133 #endif 3134 3135 /* Find the last TD */ 3136 i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes; 3137 if (i >= UHCI_VFRAMELIST_COUNT) 3138 i -= UHCI_VFRAMELIST_COUNT; 3139 end = upipe->isoc.stds[i]; 3140 3141 KASSERT(end != NULL); 3142 3143 /* Set up interrupt info. */ 3144 ux->ux_stdstart = end; 3145 ux->ux_stdend = end; 3146 3147 KASSERT(ux->ux_isdone); 3148 #ifdef DIAGNOSTIC 3149 ux->ux_isdone = false; 3150 #endif 3151 uhci_add_intr_list(sc, ux); 3152 3153 mutex_exit(&sc->sc_lock); 3154 3155 return USBD_IN_PROGRESS; 3156 } 3157 3158 void 3159 uhci_device_isoc_abort(struct usbd_xfer *xfer) 3160 { 3161 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3162 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3163 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3164 uhci_soft_td_t **stds = upipe->isoc.stds; 3165 uhci_soft_td_t *std; 3166 int i, n, nframes, maxlen, len; 3167 3168 KASSERT(mutex_owned(&sc->sc_lock)); 3169 3170 /* Transfer is already done. */ 3171 if (xfer->ux_status != USBD_NOT_STARTED && 3172 xfer->ux_status != USBD_IN_PROGRESS) { 3173 return; 3174 } 3175 3176 /* Give xfer the requested abort code. */ 3177 xfer->ux_status = USBD_CANCELLED; 3178 3179 /* make hardware ignore it, */ 3180 nframes = xfer->ux_nframes; 3181 n = ux->ux_curframe; 3182 maxlen = 0; 3183 for (i = 0; i < nframes; i++) { 3184 std = stds[n]; 3185 usb_syncmem(&std->dma, 3186 std->offs + offsetof(uhci_td_t, td_status), 3187 sizeof(std->td.td_status), 3188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3189 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3190 usb_syncmem(&std->dma, 3191 std->offs + offsetof(uhci_td_t, td_status), 3192 sizeof(std->td.td_status), 3193 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3194 usb_syncmem(&std->dma, 3195 std->offs + offsetof(uhci_td_t, td_token), 3196 sizeof(std->td.td_token), 3197 BUS_DMASYNC_POSTWRITE); 3198 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3199 if (len > maxlen) 3200 maxlen = len; 3201 if (++n >= UHCI_VFRAMELIST_COUNT) 3202 n = 0; 3203 } 3204 3205 /* and wait until we are sure the hardware has finished. */ 3206 delay(maxlen); 3207 3208 #ifdef DIAGNOSTIC 3209 ux->ux_isdone = true; 3210 #endif 3211 /* Remove from interrupt list. */ 3212 uhci_del_intr_list(sc, ux); 3213 3214 /* Run callback. */ 3215 usb_transfer_complete(xfer); 3216 3217 KASSERT(mutex_owned(&sc->sc_lock)); 3218 } 3219 3220 void 3221 uhci_device_isoc_close(struct usbd_pipe *pipe) 3222 { 3223 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3224 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3225 uhci_soft_td_t *std, *vstd; 3226 struct isoc *isoc; 3227 int i; 3228 3229 KASSERT(mutex_owned(&sc->sc_lock)); 3230 3231 /* 3232 * Make sure all TDs are marked as inactive. 3233 * Wait for completion. 3234 * Unschedule. 3235 * Deallocate. 3236 */ 3237 isoc = &upipe->isoc; 3238 3239 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3240 std = isoc->stds[i]; 3241 usb_syncmem(&std->dma, 3242 std->offs + offsetof(uhci_td_t, td_status), 3243 sizeof(std->td.td_status), 3244 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3245 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3246 usb_syncmem(&std->dma, 3247 std->offs + offsetof(uhci_td_t, td_status), 3248 sizeof(std->td.td_status), 3249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3250 } 3251 /* wait for completion */ 3252 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3253 3254 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3255 std = isoc->stds[i]; 3256 for (vstd = sc->sc_vframes[i].htd; 3257 vstd != NULL && vstd->link.std != std; 3258 vstd = vstd->link.std) 3259 ; 3260 if (vstd == NULL) { 3261 /*panic*/ 3262 printf("uhci_device_isoc_close: %p not found\n", std); 3263 mutex_exit(&sc->sc_lock); 3264 return; 3265 } 3266 vstd->link = std->link; 3267 usb_syncmem(&std->dma, 3268 std->offs + offsetof(uhci_td_t, td_link), 3269 sizeof(std->td.td_link), 3270 BUS_DMASYNC_POSTWRITE); 3271 vstd->td.td_link = std->td.td_link; 3272 usb_syncmem(&vstd->dma, 3273 vstd->offs + offsetof(uhci_td_t, td_link), 3274 sizeof(vstd->td.td_link), 3275 BUS_DMASYNC_PREWRITE); 3276 uhci_free_std_locked(sc, std); 3277 } 3278 3279 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3280 } 3281 3282 usbd_status 3283 uhci_setup_isoc(struct usbd_pipe *pipe) 3284 { 3285 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3286 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3287 int addr = upipe->pipe.up_dev->ud_addr; 3288 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3289 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3290 uhci_soft_td_t *std, *vstd; 3291 uint32_t token; 3292 struct isoc *isoc; 3293 int i; 3294 3295 isoc = &upipe->isoc; 3296 3297 isoc->stds = kmem_alloc( 3298 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3299 if (isoc->stds == NULL) 3300 return USBD_NOMEM; 3301 3302 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3303 UHCI_TD_OUT(0, endpt, addr, 0); 3304 3305 /* Allocate the TDs and mark as inactive; */ 3306 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3307 std = uhci_alloc_std(sc); 3308 if (std == 0) 3309 goto bad; 3310 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3311 std->td.td_token = htole32(token); 3312 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3313 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3314 isoc->stds[i] = std; 3315 } 3316 3317 mutex_enter(&sc->sc_lock); 3318 3319 /* Insert TDs into schedule. */ 3320 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3321 std = isoc->stds[i]; 3322 vstd = sc->sc_vframes[i].htd; 3323 usb_syncmem(&vstd->dma, 3324 vstd->offs + offsetof(uhci_td_t, td_link), 3325 sizeof(vstd->td.td_link), 3326 BUS_DMASYNC_POSTWRITE); 3327 std->link = vstd->link; 3328 std->td.td_link = vstd->td.td_link; 3329 usb_syncmem(&std->dma, 3330 std->offs + offsetof(uhci_td_t, td_link), 3331 sizeof(std->td.td_link), 3332 BUS_DMASYNC_PREWRITE); 3333 vstd->link.std = std; 3334 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3335 usb_syncmem(&vstd->dma, 3336 vstd->offs + offsetof(uhci_td_t, td_link), 3337 sizeof(vstd->td.td_link), 3338 BUS_DMASYNC_PREWRITE); 3339 } 3340 mutex_exit(&sc->sc_lock); 3341 3342 isoc->next = -1; 3343 isoc->inuse = 0; 3344 3345 return USBD_NORMAL_COMPLETION; 3346 3347 bad: 3348 while (--i >= 0) 3349 uhci_free_std(sc, isoc->stds[i]); 3350 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3351 return USBD_NOMEM; 3352 } 3353 3354 void 3355 uhci_device_isoc_done(struct usbd_xfer *xfer) 3356 { 3357 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3358 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3359 int i, offs; 3360 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3361 3362 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3363 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3364 xfer->ux_actlen, xfer->ux_state, 0, 0); 3365 3366 #ifdef DIAGNOSTIC 3367 if (ux->ux_stdend == NULL) { 3368 printf("uhci_device_isoc_done: xfer=%p stdend==NULL\n", xfer); 3369 #ifdef UHCI_DEBUG 3370 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3371 uhci_dump_ii(ux); 3372 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3373 #endif 3374 return; 3375 } 3376 #endif 3377 3378 /* Turn off the interrupt since it is active even if the TD is not. */ 3379 usb_syncmem(&ux->ux_stdend->dma, 3380 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3381 sizeof(ux->ux_stdend->td.td_status), 3382 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3383 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3384 usb_syncmem(&ux->ux_stdend->dma, 3385 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3386 sizeof(ux->ux_stdend->td.td_status), 3387 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3388 3389 offs = 0; 3390 for (i = 0; i < xfer->ux_nframes; i++) { 3391 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3392 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3393 offs += xfer->ux_frlengths[i]; 3394 } 3395 } 3396 3397 void 3398 uhci_device_intr_done(struct usbd_xfer *xfer) 3399 { 3400 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3401 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3402 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3403 uhci_soft_qh_t *sqh; 3404 int i, npoll; 3405 3406 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3407 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3408 3409 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3410 3411 npoll = upipe->intr.npoll; 3412 for (i = 0; i < npoll; i++) { 3413 sqh = upipe->intr.qhs[i]; 3414 sqh->elink = NULL; 3415 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3416 usb_syncmem(&sqh->dma, 3417 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3418 sizeof(sqh->qh.qh_elink), 3419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3420 } 3421 3422 if (xfer->ux_pipe->up_repeat) { 3423 uhci_soft_td_t *data, *dataend; 3424 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3425 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3426 3427 KASSERT(ux->ux_isdone); 3428 #ifdef DIAGNOSTIC 3429 ux->ux_isdone = false; 3430 #endif 3431 DPRINTFN(5, "re-queueing", 0, 0, 0, 0); 3432 3433 data = ux->ux_stdstart; 3434 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 3435 &upipe->nexttoggle, &dataend); 3436 dataend->td.td_status |= htole32(UHCI_TD_IOC); 3437 usb_syncmem(&dataend->dma, 3438 dataend->offs + offsetof(uhci_td_t, td_status), 3439 sizeof(dataend->td.td_status), 3440 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3441 3442 #ifdef UHCI_DEBUG 3443 if (uhcidebug >= 10) { 3444 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3445 uhci_dump_tds(data); 3446 uhci_dump_qh(upipe->intr.qhs[0]); 3447 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3448 } 3449 #endif 3450 3451 ux->ux_stdend = dataend; 3452 for (i = 0; i < npoll; i++) { 3453 sqh = upipe->intr.qhs[i]; 3454 sqh->elink = data; 3455 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 3456 usb_syncmem(&sqh->dma, 3457 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3458 sizeof(sqh->qh.qh_elink), 3459 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3460 } 3461 xfer->ux_status = USBD_IN_PROGRESS; 3462 uhci_add_intr_list(sc, ux); 3463 } 3464 } 3465 3466 /* Deallocate request data structures */ 3467 void 3468 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3469 { 3470 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3471 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3472 int len = UGETW(xfer->ux_request.wLength); 3473 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3474 3475 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3476 3477 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3478 3479 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3480 3481 /* XXXNH move to uhci_idone??? */ 3482 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3483 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3484 else 3485 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3486 3487 if (len) { 3488 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3489 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3490 } 3491 usb_syncmem(&upipe->ctrl.reqdma, 0, 3492 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3493 3494 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3495 } 3496 3497 /* Deallocate request data structures */ 3498 void 3499 uhci_device_bulk_done(struct usbd_xfer *xfer) 3500 { 3501 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3502 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3503 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3504 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3505 int endpt = ed->bEndpointAddress; 3506 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3507 3508 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3509 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3510 upipe); 3511 3512 KASSERT(mutex_owned(&sc->sc_lock)); 3513 3514 uhci_remove_bulk(sc, upipe->bulk.sqh); 3515 3516 if (xfer->ux_length) { 3517 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3518 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3519 } 3520 3521 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3522 } 3523 3524 /* Add interrupt QH, called with vflock. */ 3525 void 3526 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3527 { 3528 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3529 uhci_soft_qh_t *eqh; 3530 3531 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3532 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3533 3534 eqh = vf->eqh; 3535 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3536 sizeof(eqh->qh.qh_hlink), 3537 BUS_DMASYNC_POSTWRITE); 3538 sqh->hlink = eqh->hlink; 3539 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3540 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3541 sizeof(sqh->qh.qh_hlink), 3542 BUS_DMASYNC_PREWRITE); 3543 eqh->hlink = sqh; 3544 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3545 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3546 sizeof(eqh->qh.qh_hlink), 3547 BUS_DMASYNC_PREWRITE); 3548 vf->eqh = sqh; 3549 vf->bandwidth++; 3550 } 3551 3552 /* Remove interrupt QH. */ 3553 void 3554 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3555 { 3556 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3557 uhci_soft_qh_t *pqh; 3558 3559 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3560 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3561 3562 /* See comment in uhci_remove_ctrl() */ 3563 3564 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3565 sizeof(sqh->qh.qh_elink), 3566 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3567 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3568 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3569 usb_syncmem(&sqh->dma, 3570 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3571 sizeof(sqh->qh.qh_elink), 3572 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3573 delay(UHCI_QH_REMOVE_DELAY); 3574 } 3575 3576 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3577 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3578 sizeof(sqh->qh.qh_hlink), 3579 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3580 pqh->hlink = sqh->hlink; 3581 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3582 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3583 sizeof(pqh->qh.qh_hlink), 3584 BUS_DMASYNC_PREWRITE); 3585 delay(UHCI_QH_REMOVE_DELAY); 3586 if (vf->eqh == sqh) 3587 vf->eqh = pqh; 3588 vf->bandwidth--; 3589 } 3590 3591 usbd_status 3592 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3593 { 3594 uhci_soft_qh_t *sqh; 3595 int i, npoll; 3596 u_int bestbw, bw, bestoffs, offs; 3597 3598 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3599 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3600 if (ival == 0) { 3601 printf("uhci_device_setintr: 0 interval\n"); 3602 return USBD_INVAL; 3603 } 3604 3605 if (ival > UHCI_VFRAMELIST_COUNT) 3606 ival = UHCI_VFRAMELIST_COUNT; 3607 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3608 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3609 3610 upipe->intr.npoll = npoll; 3611 upipe->intr.qhs = 3612 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3613 if (upipe->intr.qhs == NULL) 3614 return USBD_NOMEM; 3615 3616 /* 3617 * Figure out which offset in the schedule that has most 3618 * bandwidth left over. 3619 */ 3620 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3621 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3622 for (bw = i = 0; i < npoll; i++) 3623 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3624 if (bw < bestbw) { 3625 bestbw = bw; 3626 bestoffs = offs; 3627 } 3628 } 3629 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3630 for (i = 0; i < npoll; i++) { 3631 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3632 sqh->elink = NULL; 3633 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3634 usb_syncmem(&sqh->dma, 3635 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3636 sizeof(sqh->qh.qh_elink), 3637 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3638 sqh->pos = MOD(i * ival + bestoffs); 3639 } 3640 #undef MOD 3641 3642 mutex_enter(&sc->sc_lock); 3643 /* Enter QHs into the controller data structures. */ 3644 for (i = 0; i < npoll; i++) 3645 uhci_add_intr(sc, upipe->intr.qhs[i]); 3646 mutex_exit(&sc->sc_lock); 3647 3648 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3649 3650 return USBD_NORMAL_COMPLETION; 3651 } 3652 3653 /* Open a new pipe. */ 3654 usbd_status 3655 uhci_open(struct usbd_pipe *pipe) 3656 { 3657 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3658 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3659 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3660 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3661 usbd_status err = USBD_NOMEM; 3662 int ival; 3663 3664 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3665 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3666 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3667 3668 if (sc->sc_dying) 3669 return USBD_IOERROR; 3670 3671 upipe->aborting = 0; 3672 /* toggle state needed for bulk endpoints */ 3673 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3674 3675 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3676 switch (ed->bEndpointAddress) { 3677 case USB_CONTROL_ENDPOINT: 3678 pipe->up_methods = &roothub_ctrl_methods; 3679 break; 3680 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3681 pipe->up_methods = &uhci_root_intr_methods; 3682 break; 3683 default: 3684 return USBD_INVAL; 3685 } 3686 } else { 3687 switch (ed->bmAttributes & UE_XFERTYPE) { 3688 case UE_CONTROL: 3689 pipe->up_methods = &uhci_device_ctrl_methods; 3690 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3691 if (upipe->ctrl.sqh == NULL) 3692 goto bad; 3693 upipe->ctrl.setup = uhci_alloc_std(sc); 3694 if (upipe->ctrl.setup == NULL) { 3695 uhci_free_sqh(sc, upipe->ctrl.sqh); 3696 goto bad; 3697 } 3698 upipe->ctrl.stat = uhci_alloc_std(sc); 3699 if (upipe->ctrl.stat == NULL) { 3700 uhci_free_sqh(sc, upipe->ctrl.sqh); 3701 uhci_free_std(sc, upipe->ctrl.setup); 3702 goto bad; 3703 } 3704 err = usb_allocmem(&sc->sc_bus, 3705 sizeof(usb_device_request_t), 3706 0, &upipe->ctrl.reqdma); 3707 if (err) { 3708 uhci_free_sqh(sc, upipe->ctrl.sqh); 3709 uhci_free_std(sc, upipe->ctrl.setup); 3710 uhci_free_std(sc, upipe->ctrl.stat); 3711 goto bad; 3712 } 3713 break; 3714 case UE_INTERRUPT: 3715 pipe->up_methods = &uhci_device_intr_methods; 3716 ival = pipe->up_interval; 3717 if (ival == USBD_DEFAULT_INTERVAL) 3718 ival = ed->bInterval; 3719 return uhci_device_setintr(sc, upipe, ival); 3720 case UE_ISOCHRONOUS: 3721 pipe->up_methods = &uhci_device_isoc_methods; 3722 return uhci_setup_isoc(pipe); 3723 case UE_BULK: 3724 pipe->up_methods = &uhci_device_bulk_methods; 3725 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3726 if (upipe->bulk.sqh == NULL) 3727 goto bad; 3728 break; 3729 } 3730 } 3731 return USBD_NORMAL_COMPLETION; 3732 3733 bad: 3734 return USBD_NOMEM; 3735 } 3736 3737 /* 3738 * Data structures and routines to emulate the root hub. 3739 */ 3740 /* 3741 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3742 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3743 * should not be used by the USB subsystem. As we cannot issue a 3744 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3745 * will be enabled as part of the reset. 3746 * 3747 * On the VT83C572, the port cannot be successfully enabled until the 3748 * outstanding "port enable change" and "connection status change" 3749 * events have been reset. 3750 */ 3751 Static usbd_status 3752 uhci_portreset(uhci_softc_t *sc, int index) 3753 { 3754 int lim, port, x; 3755 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3756 3757 if (index == 1) 3758 port = UHCI_PORTSC1; 3759 else if (index == 2) 3760 port = UHCI_PORTSC2; 3761 else 3762 return USBD_IOERROR; 3763 3764 x = URWMASK(UREAD2(sc, port)); 3765 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3766 3767 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3768 3769 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3770 UREAD2(sc, port), 0, 0); 3771 3772 x = URWMASK(UREAD2(sc, port)); 3773 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3774 3775 delay(100); 3776 3777 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3778 UREAD2(sc, port), 0, 0); 3779 3780 x = URWMASK(UREAD2(sc, port)); 3781 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3782 3783 for (lim = 10; --lim > 0;) { 3784 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3785 3786 x = UREAD2(sc, port); 3787 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3788 lim, x, 0); 3789 3790 if (!(x & UHCI_PORTSC_CCS)) { 3791 /* 3792 * No device is connected (or was disconnected 3793 * during reset). Consider the port reset. 3794 * The delay must be long enough to ensure on 3795 * the initial iteration that the device 3796 * connection will have been registered. 50ms 3797 * appears to be sufficient, but 20ms is not. 3798 */ 3799 DPRINTFN(3, "uhci port %d loop %u, device detached", 3800 index, lim, 0, 0); 3801 break; 3802 } 3803 3804 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3805 /* 3806 * Port enabled changed and/or connection 3807 * status changed were set. Reset either or 3808 * both raised flags (by writing a 1 to that 3809 * bit), and wait again for state to settle. 3810 */ 3811 UWRITE2(sc, port, URWMASK(x) | 3812 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3813 continue; 3814 } 3815 3816 if (x & UHCI_PORTSC_PE) 3817 /* Port is enabled */ 3818 break; 3819 3820 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3821 } 3822 3823 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3824 UREAD2(sc, port), 0, 0); 3825 3826 if (lim <= 0) { 3827 DPRINTF("uhci port %d reset timed out", index, 3828 0, 0, 0); 3829 return USBD_TIMEOUT; 3830 } 3831 3832 sc->sc_isreset = 1; 3833 return USBD_NORMAL_COMPLETION; 3834 } 3835 3836 Static int 3837 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3838 void *buf, int buflen) 3839 { 3840 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3841 int port, x; 3842 int status, change, totlen = 0; 3843 uint16_t len, value, index; 3844 usb_port_status_t ps; 3845 usbd_status err; 3846 3847 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3848 3849 if (sc->sc_dying) 3850 return -1; 3851 3852 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3853 req->bRequest, 0, 0); 3854 3855 len = UGETW(req->wLength); 3856 value = UGETW(req->wValue); 3857 index = UGETW(req->wIndex); 3858 3859 #define C(x,y) ((x) | ((y) << 8)) 3860 switch (C(req->bRequest, req->bmRequestType)) { 3861 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3862 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3863 if (len == 0) 3864 break; 3865 switch (value) { 3866 case C(0, UDESC_DEVICE): { 3867 usb_device_descriptor_t devd; 3868 3869 totlen = min(buflen, sizeof(devd)); 3870 memcpy(&devd, buf, totlen); 3871 USETW(devd.idVendor, sc->sc_id_vendor); 3872 memcpy(buf, &devd, totlen); 3873 break; 3874 } 3875 case C(1, UDESC_STRING): 3876 #define sd ((usb_string_descriptor_t *)buf) 3877 /* Vendor */ 3878 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3879 break; 3880 case C(2, UDESC_STRING): 3881 /* Product */ 3882 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3883 break; 3884 #undef sd 3885 default: 3886 /* default from usbroothub */ 3887 return buflen; 3888 } 3889 break; 3890 3891 /* Hub requests */ 3892 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3893 break; 3894 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3895 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3896 value, 0, 0); 3897 if (index == 1) 3898 port = UHCI_PORTSC1; 3899 else if (index == 2) 3900 port = UHCI_PORTSC2; 3901 else { 3902 return -1; 3903 } 3904 switch(value) { 3905 case UHF_PORT_ENABLE: 3906 x = URWMASK(UREAD2(sc, port)); 3907 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3908 break; 3909 case UHF_PORT_SUSPEND: 3910 x = URWMASK(UREAD2(sc, port)); 3911 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3912 break; 3913 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3914 /* see USB2 spec ch. 7.1.7.7 */ 3915 usb_delay_ms(&sc->sc_bus, 20); 3916 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3917 /* 10ms resume delay must be provided by caller */ 3918 break; 3919 case UHF_PORT_RESET: 3920 x = URWMASK(UREAD2(sc, port)); 3921 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3922 break; 3923 case UHF_C_PORT_CONNECTION: 3924 x = URWMASK(UREAD2(sc, port)); 3925 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3926 break; 3927 case UHF_C_PORT_ENABLE: 3928 x = URWMASK(UREAD2(sc, port)); 3929 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3930 break; 3931 case UHF_C_PORT_OVER_CURRENT: 3932 x = URWMASK(UREAD2(sc, port)); 3933 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3934 break; 3935 case UHF_C_PORT_RESET: 3936 sc->sc_isreset = 0; 3937 break; 3938 case UHF_PORT_CONNECTION: 3939 case UHF_PORT_OVER_CURRENT: 3940 case UHF_PORT_POWER: 3941 case UHF_PORT_LOW_SPEED: 3942 case UHF_C_PORT_SUSPEND: 3943 default: 3944 return -1; 3945 } 3946 break; 3947 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3948 if (index == 1) 3949 port = UHCI_PORTSC1; 3950 else if (index == 2) 3951 port = UHCI_PORTSC2; 3952 else { 3953 return -1; 3954 } 3955 if (len > 0) { 3956 *(uint8_t *)buf = 3957 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3958 UHCI_PORTSC_LS_SHIFT; 3959 totlen = 1; 3960 } 3961 break; 3962 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3963 if (len == 0) 3964 break; 3965 if ((value & 0xff) != 0) { 3966 return -1; 3967 } 3968 usb_hub_descriptor_t hubd; 3969 3970 totlen = min(buflen, sizeof(hubd)); 3971 memcpy(&hubd, buf, totlen); 3972 hubd.bNbrPorts = 2; 3973 memcpy(buf, &hubd, totlen); 3974 break; 3975 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3976 if (len != 4) { 3977 return -1; 3978 } 3979 memset(buf, 0, len); 3980 totlen = len; 3981 break; 3982 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3983 if (index == 1) 3984 port = UHCI_PORTSC1; 3985 else if (index == 2) 3986 port = UHCI_PORTSC2; 3987 else { 3988 return -1; 3989 } 3990 if (len != 4) { 3991 return -1; 3992 } 3993 x = UREAD2(sc, port); 3994 status = change = 0; 3995 if (x & UHCI_PORTSC_CCS) 3996 status |= UPS_CURRENT_CONNECT_STATUS; 3997 if (x & UHCI_PORTSC_CSC) 3998 change |= UPS_C_CONNECT_STATUS; 3999 if (x & UHCI_PORTSC_PE) 4000 status |= UPS_PORT_ENABLED; 4001 if (x & UHCI_PORTSC_POEDC) 4002 change |= UPS_C_PORT_ENABLED; 4003 if (x & UHCI_PORTSC_OCI) 4004 status |= UPS_OVERCURRENT_INDICATOR; 4005 if (x & UHCI_PORTSC_OCIC) 4006 change |= UPS_C_OVERCURRENT_INDICATOR; 4007 if (x & UHCI_PORTSC_SUSP) 4008 status |= UPS_SUSPEND; 4009 if (x & UHCI_PORTSC_LSDA) 4010 status |= UPS_LOW_SPEED; 4011 status |= UPS_PORT_POWER; 4012 if (sc->sc_isreset) 4013 change |= UPS_C_PORT_RESET; 4014 USETW(ps.wPortStatus, status); 4015 USETW(ps.wPortChange, change); 4016 totlen = min(len, sizeof(ps)); 4017 memcpy(buf, &ps, totlen); 4018 break; 4019 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 4020 return -1; 4021 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 4022 break; 4023 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 4024 if (index == 1) 4025 port = UHCI_PORTSC1; 4026 else if (index == 2) 4027 port = UHCI_PORTSC2; 4028 else { 4029 return -1; 4030 } 4031 switch(value) { 4032 case UHF_PORT_ENABLE: 4033 x = URWMASK(UREAD2(sc, port)); 4034 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 4035 break; 4036 case UHF_PORT_SUSPEND: 4037 x = URWMASK(UREAD2(sc, port)); 4038 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 4039 break; 4040 case UHF_PORT_RESET: 4041 err = uhci_portreset(sc, index); 4042 if (err != USBD_NORMAL_COMPLETION) 4043 return -1; 4044 return 0; 4045 case UHF_PORT_POWER: 4046 /* Pretend we turned on power */ 4047 return 0; 4048 case UHF_C_PORT_CONNECTION: 4049 case UHF_C_PORT_ENABLE: 4050 case UHF_C_PORT_OVER_CURRENT: 4051 case UHF_PORT_CONNECTION: 4052 case UHF_PORT_OVER_CURRENT: 4053 case UHF_PORT_LOW_SPEED: 4054 case UHF_C_PORT_SUSPEND: 4055 case UHF_C_PORT_RESET: 4056 default: 4057 return -1; 4058 } 4059 break; 4060 default: 4061 /* default from usbroothub */ 4062 DPRINTF("returning %d (usbroothub default)", 4063 buflen, 0, 0, 0); 4064 return buflen; 4065 } 4066 4067 DPRINTF("returning %d", totlen, 0, 0, 0); 4068 4069 return totlen; 4070 } 4071 4072 /* Abort a root interrupt request. */ 4073 void 4074 uhci_root_intr_abort(struct usbd_xfer *xfer) 4075 { 4076 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 4077 4078 KASSERT(mutex_owned(&sc->sc_lock)); 4079 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4080 4081 callout_stop(&sc->sc_poll_handle); 4082 sc->sc_intr_xfer = NULL; 4083 4084 xfer->ux_status = USBD_CANCELLED; 4085 #ifdef DIAGNOSTIC 4086 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 4087 #endif 4088 usb_transfer_complete(xfer); 4089 } 4090 4091 usbd_status 4092 uhci_root_intr_transfer(struct usbd_xfer *xfer) 4093 { 4094 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 4095 usbd_status err; 4096 4097 /* Insert last in queue. */ 4098 mutex_enter(&sc->sc_lock); 4099 err = usb_insert_transfer(xfer); 4100 mutex_exit(&sc->sc_lock); 4101 if (err) 4102 return err; 4103 4104 /* 4105 * Pipe isn't running (otherwise err would be USBD_INPROG), 4106 * start first 4107 */ 4108 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4109 } 4110 4111 /* Start a transfer on the root interrupt pipe */ 4112 usbd_status 4113 uhci_root_intr_start(struct usbd_xfer *xfer) 4114 { 4115 struct usbd_pipe *pipe = xfer->ux_pipe; 4116 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 4117 unsigned int ival; 4118 4119 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 4120 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4121 xfer->ux_flags, 0); 4122 4123 if (sc->sc_dying) 4124 return USBD_IOERROR; 4125 4126 /* XXX temporary variable needed to avoid gcc3 warning */ 4127 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 4128 sc->sc_ival = mstohz(ival); 4129 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 4130 sc->sc_intr_xfer = xfer; 4131 return USBD_IN_PROGRESS; 4132 } 4133 4134 /* Close the root interrupt pipe. */ 4135 void 4136 uhci_root_intr_close(struct usbd_pipe *pipe) 4137 { 4138 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 4139 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 4140 4141 KASSERT(mutex_owned(&sc->sc_lock)); 4142 4143 callout_stop(&sc->sc_poll_handle); 4144 sc->sc_intr_xfer = NULL; 4145 } 4146
Indexes created Tue Sep 30 20:09:53 GMT 2025