uhci.c revision 1.264.4.67
1 /* $NetBSD: uhci.c,v 1.264.4.67 2016/03/17 07:59:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.67 2016/03/17 07:59:45 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup; 143 uhci_soft_td_t *stat; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 uhci_soft_qh_t **qhs; 149 } intr; 150 /* Bulk pipe */ 151 struct { 152 uhci_soft_qh_t *sqh; 153 } bulk; 154 /* Isochronous pipe */ 155 struct isoc { 156 uhci_soft_td_t **stds; 157 int next, inuse; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 163 164 Static void uhci_globalreset(uhci_softc_t *); 165 Static usbd_status uhci_portreset(uhci_softc_t*, int); 166 Static void uhci_reset(uhci_softc_t *); 167 Static usbd_status uhci_run(uhci_softc_t *, int, int); 168 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 169 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 170 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 180 uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 182 int, int, uhci_soft_td_t **, uhci_soft_td_t **); 183 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 184 185 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, int *, uhci_soft_td_t **); 187 188 Static void uhci_poll_hub(void *); 189 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 190 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 191 ux_completeq_t *); 192 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 193 194 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 195 196 Static void uhci_timeout(void *); 197 Static void uhci_timeout_task(void *); 198 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 199 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 200 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 201 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 202 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 203 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 204 Static void uhci_add_loop(uhci_softc_t *); 205 Static void uhci_rem_loop(uhci_softc_t *); 206 207 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 208 Static void uhci_device_isoc_enter(struct usbd_xfer *); 209 210 Static struct usbd_xfer * 211 uhci_allocx(struct usbd_bus *, unsigned int); 212 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 213 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 214 Static int uhci_roothub_ctrl(struct usbd_bus *, 215 usb_device_request_t *, void *, int); 216 217 Static int uhci_device_ctrl_init(struct usbd_xfer *); 218 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 219 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 220 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 221 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 222 Static void uhci_device_ctrl_close(struct usbd_pipe *); 223 Static void uhci_device_ctrl_done(struct usbd_xfer *); 224 225 Static int uhci_device_intr_init(struct usbd_xfer *); 226 Static void uhci_device_intr_fini(struct usbd_xfer *); 227 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 228 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 229 Static void uhci_device_intr_abort(struct usbd_xfer *); 230 Static void uhci_device_intr_close(struct usbd_pipe *); 231 Static void uhci_device_intr_done(struct usbd_xfer *); 232 233 Static int uhci_device_bulk_init(struct usbd_xfer *); 234 Static void uhci_device_bulk_fini(struct usbd_xfer *); 235 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 236 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 237 Static void uhci_device_bulk_abort(struct usbd_xfer *); 238 Static void uhci_device_bulk_close(struct usbd_pipe *); 239 Static void uhci_device_bulk_done(struct usbd_xfer *); 240 241 Static int uhci_device_isoc_init(struct usbd_xfer *); 242 Static void uhci_device_isoc_fini(struct usbd_xfer *); 243 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 244 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 245 Static void uhci_device_isoc_abort(struct usbd_xfer *); 246 Static void uhci_device_isoc_close(struct usbd_pipe *); 247 Static void uhci_device_isoc_done(struct usbd_xfer *); 248 249 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 250 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 251 Static void uhci_root_intr_abort(struct usbd_xfer *); 252 Static void uhci_root_intr_close(struct usbd_pipe *); 253 Static void uhci_root_intr_done(struct usbd_xfer *); 254 255 Static usbd_status uhci_open(struct usbd_pipe *); 256 Static void uhci_poll(struct usbd_bus *); 257 Static void uhci_softintr(void *); 258 259 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 260 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 261 Static usbd_status uhci_device_setintr(uhci_softc_t *, 262 struct uhci_pipe *, int); 263 264 Static void uhci_device_clear_toggle(struct usbd_pipe *); 265 Static void uhci_noop(struct usbd_pipe *); 266 267 static inline uhci_soft_qh_t * 268 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 269 270 #ifdef UHCI_DEBUG 271 Static void uhci_dump_all(uhci_softc_t *); 272 Static void uhci_dumpregs(uhci_softc_t *); 273 Static void uhci_dump_qhs(uhci_soft_qh_t *); 274 Static void uhci_dump_qh(uhci_soft_qh_t *); 275 Static void uhci_dump_tds(uhci_soft_td_t *); 276 Static void uhci_dump_td(uhci_soft_td_t *); 277 Static void uhci_dump_ii(struct uhci_xfer *); 278 void uhci_dump(void); 279 #endif 280 281 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 282 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 283 #define UWRITE1(sc, r, x) \ 284 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 285 } while (/*CONSTCOND*/0) 286 #define UWRITE2(sc, r, x) \ 287 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 288 } while (/*CONSTCOND*/0) 289 #define UWRITE4(sc, r, x) \ 290 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 291 } while (/*CONSTCOND*/0) 292 293 static __inline uint8_t 294 UREAD1(uhci_softc_t *sc, bus_size_t r) 295 { 296 297 UBARR(sc); 298 return bus_space_read_1(sc->iot, sc->ioh, r); 299 } 300 301 static __inline uint16_t 302 UREAD2(uhci_softc_t *sc, bus_size_t r) 303 { 304 305 UBARR(sc); 306 return bus_space_read_2(sc->iot, sc->ioh, r); 307 } 308 309 #ifdef UHCI_DEBUG 310 static __inline uint32_t 311 UREAD4(uhci_softc_t *sc, bus_size_t r) 312 { 313 314 UBARR(sc); 315 return bus_space_read_4(sc->iot, sc->ioh, r); 316 } 317 #endif 318 319 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 320 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 321 322 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 323 324 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 325 326 const struct usbd_bus_methods uhci_bus_methods = { 327 .ubm_open = uhci_open, 328 .ubm_softint = uhci_softintr, 329 .ubm_dopoll = uhci_poll, 330 .ubm_allocx = uhci_allocx, 331 .ubm_freex = uhci_freex, 332 .ubm_getlock = uhci_get_lock, 333 .ubm_rhctrl = uhci_roothub_ctrl, 334 }; 335 336 const struct usbd_pipe_methods uhci_root_intr_methods = { 337 .upm_transfer = uhci_root_intr_transfer, 338 .upm_start = uhci_root_intr_start, 339 .upm_abort = uhci_root_intr_abort, 340 .upm_close = uhci_root_intr_close, 341 .upm_cleartoggle = uhci_noop, 342 .upm_done = uhci_root_intr_done, 343 }; 344 345 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 346 .upm_init = uhci_device_ctrl_init, 347 .upm_fini = uhci_device_ctrl_fini, 348 .upm_transfer = uhci_device_ctrl_transfer, 349 .upm_start = uhci_device_ctrl_start, 350 .upm_abort = uhci_device_ctrl_abort, 351 .upm_close = uhci_device_ctrl_close, 352 .upm_cleartoggle = uhci_noop, 353 .upm_done = uhci_device_ctrl_done, 354 }; 355 356 const struct usbd_pipe_methods uhci_device_intr_methods = { 357 .upm_init = uhci_device_intr_init, 358 .upm_fini = uhci_device_intr_fini, 359 .upm_transfer = uhci_device_intr_transfer, 360 .upm_start = uhci_device_intr_start, 361 .upm_abort = uhci_device_intr_abort, 362 .upm_close = uhci_device_intr_close, 363 .upm_cleartoggle = uhci_device_clear_toggle, 364 .upm_done = uhci_device_intr_done, 365 }; 366 367 const struct usbd_pipe_methods uhci_device_bulk_methods = { 368 .upm_init = uhci_device_bulk_init, 369 .upm_fini = uhci_device_bulk_fini, 370 .upm_transfer = uhci_device_bulk_transfer, 371 .upm_start = uhci_device_bulk_start, 372 .upm_abort = uhci_device_bulk_abort, 373 .upm_close = uhci_device_bulk_close, 374 .upm_cleartoggle = uhci_device_clear_toggle, 375 .upm_done = uhci_device_bulk_done, 376 }; 377 378 const struct usbd_pipe_methods uhci_device_isoc_methods = { 379 .upm_init = uhci_device_isoc_init, 380 .upm_fini = uhci_device_isoc_fini, 381 .upm_transfer = uhci_device_isoc_transfer, 382 .upm_start = uhci_device_isoc_start, 383 .upm_abort = uhci_device_isoc_abort, 384 .upm_close = uhci_device_isoc_close, 385 .upm_cleartoggle = uhci_noop, 386 .upm_done = uhci_device_isoc_done, 387 }; 388 389 static inline void 390 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 391 { 392 393 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 394 } 395 396 static inline void 397 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 398 { 399 400 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 401 } 402 403 static inline uhci_soft_qh_t * 404 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 405 { 406 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 407 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 408 409 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 410 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 411 usb_syncmem(&pqh->dma, 412 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 413 sizeof(pqh->qh.qh_hlink), 414 BUS_DMASYNC_POSTWRITE); 415 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 416 printf("%s: QH not found\n", __func__); 417 return NULL; 418 } 419 #endif 420 } 421 return pqh; 422 } 423 424 void 425 uhci_globalreset(uhci_softc_t *sc) 426 { 427 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 428 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 429 UHCICMD(sc, 0); /* do nothing */ 430 } 431 432 int 433 uhci_init(uhci_softc_t *sc) 434 { 435 usbd_status err; 436 int i, j; 437 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 438 uhci_soft_td_t *std; 439 440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 441 442 #ifdef UHCI_DEBUG 443 thesc = sc; 444 445 if (uhcidebug >= 2) 446 uhci_dumpregs(sc); 447 #endif 448 449 sc->sc_suspend = PWR_RESUME; 450 451 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 452 uhci_globalreset(sc); /* reset the controller */ 453 uhci_reset(sc); 454 455 /* Allocate and initialize real frame array. */ 456 err = usb_allocmem(&sc->sc_bus, 457 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 458 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 459 if (err) 460 return err; 461 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 462 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 463 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 464 465 /* Initialise mutex early for uhci_alloc_* */ 466 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 467 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 468 469 /* 470 * Allocate a TD, inactive, that hangs from the last QH. 471 * This is to avoid a bug in the PIIX that makes it run berserk 472 * otherwise. 473 */ 474 std = uhci_alloc_std(sc); 475 if (std == NULL) 476 return ENOMEM; 477 std->link.std = NULL; 478 std->td.td_link = htole32(UHCI_PTR_T); 479 std->td.td_status = htole32(0); /* inactive */ 480 std->td.td_token = htole32(0); 481 std->td.td_buffer = htole32(0); 482 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 486 lsqh = uhci_alloc_sqh(sc); 487 if (lsqh == NULL) 488 goto fail1; 489 lsqh->hlink = NULL; 490 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 491 lsqh->elink = std; 492 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 493 sc->sc_last_qh = lsqh; 494 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 495 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 496 497 /* Allocate the dummy QH where bulk traffic will be queued. */ 498 bsqh = uhci_alloc_sqh(sc); 499 if (bsqh == NULL) 500 goto fail2; 501 bsqh->hlink = lsqh; 502 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 503 bsqh->elink = NULL; 504 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 506 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 509 /* Allocate dummy QH where high speed control traffic will be queued. */ 510 chsqh = uhci_alloc_sqh(sc); 511 if (chsqh == NULL) 512 goto fail3; 513 chsqh->hlink = bsqh; 514 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 515 chsqh->elink = NULL; 516 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 517 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 518 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 521 /* Allocate dummy QH where control traffic will be queued. */ 522 clsqh = uhci_alloc_sqh(sc); 523 if (clsqh == NULL) 524 goto fail4; 525 clsqh->hlink = chsqh; 526 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 527 clsqh->elink = NULL; 528 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 529 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 530 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 533 /* 534 * Make all (virtual) frame list pointers point to the interrupt 535 * queue heads and the interrupt queue heads at the control 536 * queue head and point the physical frame list to the virtual. 537 */ 538 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 539 std = uhci_alloc_std(sc); 540 sqh = uhci_alloc_sqh(sc); 541 if (std == NULL || sqh == NULL) 542 return USBD_NOMEM; 543 std->link.sqh = sqh; 544 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 545 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 546 std->td.td_token = htole32(0); 547 std->td.td_buffer = htole32(0); 548 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 sqh->hlink = clsqh; 551 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 552 sqh->elink = NULL; 553 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 554 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 556 sc->sc_vframes[i].htd = std; 557 sc->sc_vframes[i].etd = std; 558 sc->sc_vframes[i].hqh = sqh; 559 sc->sc_vframes[i].eqh = sqh; 560 for (j = i; 561 j < UHCI_FRAMELIST_COUNT; 562 j += UHCI_VFRAMELIST_COUNT) 563 sc->sc_pframes[j] = htole32(std->physaddr); 564 } 565 usb_syncmem(&sc->sc_dma, 0, 566 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 567 BUS_DMASYNC_PREWRITE); 568 569 570 TAILQ_INIT(&sc->sc_intrhead); 571 572 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 573 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 574 575 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 576 577 cv_init(&sc->sc_softwake_cv, "uhciab"); 578 579 /* Set up the bus struct. */ 580 sc->sc_bus.ub_methods = &uhci_bus_methods; 581 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 582 sc->sc_bus.ub_usedma = true; 583 584 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 585 586 DPRINTF("Enabling...", 0, 0, 0, 0); 587 588 err = uhci_run(sc, 1, 0); /* and here we go... */ 589 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 590 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 591 return err; 592 593 fail4: 594 uhci_free_sqh(sc, chsqh); 595 fail3: 596 uhci_free_sqh(sc, lsqh); 597 fail2: 598 uhci_free_sqh(sc, lsqh); 599 fail1: 600 uhci_free_std(sc, std); 601 602 return ENOMEM; 603 } 604 605 int 606 uhci_activate(device_t self, enum devact act) 607 { 608 struct uhci_softc *sc = device_private(self); 609 610 switch (act) { 611 case DVACT_DEACTIVATE: 612 sc->sc_dying = 1; 613 return 0; 614 default: 615 return EOPNOTSUPP; 616 } 617 } 618 619 void 620 uhci_childdet(device_t self, device_t child) 621 { 622 struct uhci_softc *sc = device_private(self); 623 624 KASSERT(sc->sc_child == child); 625 sc->sc_child = NULL; 626 } 627 628 int 629 uhci_detach(struct uhci_softc *sc, int flags) 630 { 631 int rv = 0; 632 633 if (sc->sc_child != NULL) 634 rv = config_detach(sc->sc_child, flags); 635 636 if (rv != 0) 637 return rv; 638 639 callout_halt(&sc->sc_poll_handle, NULL); 640 callout_destroy(&sc->sc_poll_handle); 641 642 cv_destroy(&sc->sc_softwake_cv); 643 644 mutex_destroy(&sc->sc_lock); 645 mutex_destroy(&sc->sc_intr_lock); 646 647 pool_cache_destroy(sc->sc_xferpool); 648 649 /* XXX free other data structures XXX */ 650 651 return rv; 652 } 653 654 struct usbd_xfer * 655 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 656 { 657 struct uhci_softc *sc = UHCI_BUS2SC(bus); 658 struct usbd_xfer *xfer; 659 660 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 661 if (xfer != NULL) { 662 memset(xfer, 0, sizeof(struct uhci_xfer)); 663 664 #ifdef DIAGNOSTIC 665 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 666 uxfer->ux_isdone = true; 667 xfer->ux_state = XFER_BUSY; 668 #endif 669 } 670 return xfer; 671 } 672 673 void 674 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 675 { 676 struct uhci_softc *sc = UHCI_BUS2SC(bus); 677 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 678 679 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 680 xfer->ux_state); 681 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 682 #ifdef DIAGNOSTIC 683 xfer->ux_state = XFER_FREE; 684 #endif 685 pool_cache_put(sc->sc_xferpool, xfer); 686 } 687 688 Static void 689 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 690 { 691 struct uhci_softc *sc = UHCI_BUS2SC(bus); 692 693 *lock = &sc->sc_lock; 694 } 695 696 697 /* 698 * Handle suspend/resume. 699 * 700 * We need to switch to polling mode here, because this routine is 701 * called from an interrupt context. This is all right since we 702 * are almost suspended anyway. 703 */ 704 bool 705 uhci_resume(device_t dv, const pmf_qual_t *qual) 706 { 707 uhci_softc_t *sc = device_private(dv); 708 int cmd; 709 710 mutex_spin_enter(&sc->sc_intr_lock); 711 712 cmd = UREAD2(sc, UHCI_CMD); 713 sc->sc_bus.ub_usepolling++; 714 UWRITE2(sc, UHCI_INTR, 0); 715 uhci_globalreset(sc); 716 uhci_reset(sc); 717 if (cmd & UHCI_CMD_RS) 718 uhci_run(sc, 0, 1); 719 720 /* restore saved state */ 721 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 722 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 723 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 724 725 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 726 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 727 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 728 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 729 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 730 UHCICMD(sc, UHCI_CMD_MAXP); 731 uhci_run(sc, 1, 1); /* and start traffic again */ 732 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 733 sc->sc_bus.ub_usepolling--; 734 if (sc->sc_intr_xfer != NULL) 735 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 736 sc->sc_intr_xfer); 737 #ifdef UHCI_DEBUG 738 if (uhcidebug >= 2) 739 uhci_dumpregs(sc); 740 #endif 741 742 sc->sc_suspend = PWR_RESUME; 743 mutex_spin_exit(&sc->sc_intr_lock); 744 745 return true; 746 } 747 748 bool 749 uhci_suspend(device_t dv, const pmf_qual_t *qual) 750 { 751 uhci_softc_t *sc = device_private(dv); 752 int cmd; 753 754 mutex_spin_enter(&sc->sc_intr_lock); 755 756 cmd = UREAD2(sc, UHCI_CMD); 757 758 #ifdef UHCI_DEBUG 759 if (uhcidebug >= 2) 760 uhci_dumpregs(sc); 761 #endif 762 if (sc->sc_intr_xfer != NULL) 763 callout_stop(&sc->sc_poll_handle); 764 sc->sc_suspend = PWR_SUSPEND; 765 sc->sc_bus.ub_usepolling++; 766 767 uhci_run(sc, 0, 1); /* stop the controller */ 768 cmd &= ~UHCI_CMD_RS; 769 770 /* save some state if BIOS doesn't */ 771 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 772 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 773 774 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 775 776 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 777 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 778 sc->sc_bus.ub_usepolling--; 779 780 mutex_spin_exit(&sc->sc_intr_lock); 781 782 return true; 783 } 784 785 #ifdef UHCI_DEBUG 786 Static void 787 uhci_dumpregs(uhci_softc_t *sc) 788 { 789 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 790 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 791 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 792 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 793 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 794 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 795 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 796 } 797 798 void 799 uhci_dump_td(uhci_soft_td_t *p) 800 { 801 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 802 803 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 805 806 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 807 DPRINTF(" link=0x%08x status=0x%08x " 808 "token=0x%08x buffer=0x%08x", 809 le32toh(p->td.td_link), 810 le32toh(p->td.td_status), 811 le32toh(p->td.td_token), 812 le32toh(p->td.td_buffer)); 813 814 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 815 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 816 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 817 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 818 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 819 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 820 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 821 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 822 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 823 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 824 DPRINTF("ios =%d ls =%d spd =%d", 825 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 826 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 827 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 828 DPRINTF("errcnt =%d actlen =%d pid=%02x", 829 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 830 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 831 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 832 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 833 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 834 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 835 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 836 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 837 } 838 839 void 840 uhci_dump_qh(uhci_soft_qh_t *sqh) 841 { 842 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 843 844 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 845 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 846 847 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 848 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 849 le32toh(sqh->qh.qh_elink)); 850 851 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 852 } 853 854 855 #if 1 856 void 857 uhci_dump(void) 858 { 859 uhci_dump_all(thesc); 860 } 861 #endif 862 863 void 864 uhci_dump_all(uhci_softc_t *sc) 865 { 866 uhci_dumpregs(sc); 867 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 868 uhci_dump_qhs(sc->sc_lctl_start); 869 } 870 871 872 void 873 uhci_dump_qhs(uhci_soft_qh_t *sqh) 874 { 875 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 876 877 uhci_dump_qh(sqh); 878 879 /* 880 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 881 * Traverses sideways first, then down. 882 * 883 * QH1 884 * QH2 885 * No QH 886 * TD2.1 887 * TD2.2 888 * TD1.1 889 * etc. 890 * 891 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 892 */ 893 894 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 895 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 896 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 897 uhci_dump_qhs(sqh->hlink); 898 else 899 DPRINTF("No QH", 0, 0, 0, 0); 900 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 901 902 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 903 uhci_dump_tds(sqh->elink); 904 else 905 DPRINTF("No QH", 0, 0, 0, 0); 906 } 907 908 void 909 uhci_dump_tds(uhci_soft_td_t *std) 910 { 911 uhci_soft_td_t *td; 912 int stop; 913 914 for (td = std; td != NULL; td = td->link.std) { 915 uhci_dump_td(td); 916 917 /* 918 * Check whether the link pointer in this TD marks 919 * the link pointer as end of queue. This avoids 920 * printing the free list in case the queue/TD has 921 * already been moved there (seatbelt). 922 */ 923 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 924 sizeof(td->td.td_link), 925 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 926 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 927 le32toh(td->td.td_link) == 0); 928 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 929 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 930 if (stop) 931 break; 932 } 933 } 934 935 Static void 936 uhci_dump_ii(struct uhci_xfer *ux) 937 { 938 struct usbd_pipe *pipe; 939 usb_endpoint_descriptor_t *ed; 940 struct usbd_device *dev; 941 942 if (ux == NULL) { 943 printf("ux NULL\n"); 944 return; 945 } 946 pipe = ux->ux_xfer.ux_pipe; 947 if (pipe == NULL) { 948 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 949 return; 950 } 951 if (pipe->up_endpoint == NULL) { 952 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 953 ux, ux->ux_isdone, pipe); 954 return; 955 } 956 if (pipe->up_dev == NULL) { 957 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 958 ux, ux->ux_isdone, pipe); 959 return; 960 } 961 ed = pipe->up_endpoint->ue_edesc; 962 dev = pipe->up_dev; 963 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 964 ux, ux->ux_isdone, dev, 965 UGETW(dev->ud_ddesc.idVendor), 966 UGETW(dev->ud_ddesc.idProduct), 967 dev->ud_addr, pipe, 968 ed->bEndpointAddress, ed->bmAttributes); 969 } 970 971 void uhci_dump_iis(struct uhci_softc *sc); 972 void 973 uhci_dump_iis(struct uhci_softc *sc) 974 { 975 struct uhci_xfer *ux; 976 977 printf("interrupt list:\n"); 978 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 979 uhci_dump_ii(ux); 980 } 981 982 void iidump(void); 983 void iidump(void) { uhci_dump_iis(thesc); } 984 985 #endif 986 987 /* 988 * This routine is executed periodically and simulates interrupts 989 * from the root controller interrupt pipe for port status change. 990 */ 991 void 992 uhci_poll_hub(void *addr) 993 { 994 struct usbd_xfer *xfer = addr; 995 struct usbd_pipe *pipe = xfer->ux_pipe; 996 uhci_softc_t *sc; 997 u_char *p; 998 999 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1000 1001 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1002 return; /* device has detached */ 1003 sc = UHCI_PIPE2SC(pipe); 1004 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1005 1006 p = xfer->ux_buf; 1007 p[0] = 0; 1008 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<1; 1010 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1011 p[0] |= 1<<2; 1012 if (p[0] == 0) 1013 /* No change, try again in a while */ 1014 return; 1015 1016 xfer->ux_actlen = 1; 1017 xfer->ux_status = USBD_NORMAL_COMPLETION; 1018 mutex_enter(&sc->sc_lock); 1019 usb_transfer_complete(xfer); 1020 mutex_exit(&sc->sc_lock); 1021 } 1022 1023 void 1024 uhci_root_intr_done(struct usbd_xfer *xfer) 1025 { 1026 } 1027 1028 /* 1029 * Let the last QH loop back to the high speed control transfer QH. 1030 * This is what intel calls "bandwidth reclamation" and improves 1031 * USB performance a lot for some devices. 1032 * If we are already looping, just count it. 1033 */ 1034 void 1035 uhci_add_loop(uhci_softc_t *sc) 1036 { 1037 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1038 1039 #ifdef UHCI_DEBUG 1040 if (uhcinoloop) 1041 return; 1042 #endif 1043 if (++sc->sc_loops == 1) { 1044 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1045 /* Note, we don't loop back the soft pointer. */ 1046 sc->sc_last_qh->qh.qh_hlink = 1047 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1048 usb_syncmem(&sc->sc_last_qh->dma, 1049 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1050 sizeof(sc->sc_last_qh->qh.qh_hlink), 1051 BUS_DMASYNC_PREWRITE); 1052 } 1053 } 1054 1055 void 1056 uhci_rem_loop(uhci_softc_t *sc) 1057 { 1058 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1059 1060 #ifdef UHCI_DEBUG 1061 if (uhcinoloop) 1062 return; 1063 #endif 1064 if (--sc->sc_loops == 0) { 1065 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1066 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1067 usb_syncmem(&sc->sc_last_qh->dma, 1068 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1069 sizeof(sc->sc_last_qh->qh.qh_hlink), 1070 BUS_DMASYNC_PREWRITE); 1071 } 1072 } 1073 1074 /* Add high speed control QH, called with lock held. */ 1075 void 1076 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1077 { 1078 uhci_soft_qh_t *eqh; 1079 1080 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1081 1082 KASSERT(mutex_owned(&sc->sc_lock)); 1083 1084 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1085 eqh = sc->sc_hctl_end; 1086 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1087 sizeof(eqh->qh.qh_hlink), 1088 BUS_DMASYNC_POSTWRITE); 1089 sqh->hlink = eqh->hlink; 1090 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1091 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1092 BUS_DMASYNC_PREWRITE); 1093 eqh->hlink = sqh; 1094 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1095 sc->sc_hctl_end = sqh; 1096 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1097 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1098 #ifdef UHCI_CTL_LOOP 1099 uhci_add_loop(sc); 1100 #endif 1101 } 1102 1103 /* Remove high speed control QH, called with lock held. */ 1104 void 1105 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1106 { 1107 uhci_soft_qh_t *pqh; 1108 uint32_t elink; 1109 1110 KASSERT(mutex_owned(&sc->sc_lock)); 1111 1112 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1113 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1114 #ifdef UHCI_CTL_LOOP 1115 uhci_rem_loop(sc); 1116 #endif 1117 /* 1118 * The T bit should be set in the elink of the QH so that the HC 1119 * doesn't follow the pointer. This condition may fail if the 1120 * the transferred packet was short so that the QH still points 1121 * at the last used TD. 1122 * In this case we set the T bit and wait a little for the HC 1123 * to stop looking at the TD. 1124 * Note that if the TD chain is large enough, the controller 1125 * may still be looking at the chain at the end of this function. 1126 * uhci_free_std_chain() will make sure the controller stops 1127 * looking at it quickly, but until then we should not change 1128 * sqh->hlink. 1129 */ 1130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1131 sizeof(sqh->qh.qh_elink), 1132 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1133 elink = le32toh(sqh->qh.qh_elink); 1134 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1135 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1136 if (!(elink & UHCI_PTR_T)) { 1137 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1138 usb_syncmem(&sqh->dma, 1139 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1140 sizeof(sqh->qh.qh_elink), 1141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1142 delay(UHCI_QH_REMOVE_DELAY); 1143 } 1144 1145 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1146 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1147 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1148 pqh->hlink = sqh->hlink; 1149 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1150 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1151 sizeof(pqh->qh.qh_hlink), 1152 BUS_DMASYNC_PREWRITE); 1153 delay(UHCI_QH_REMOVE_DELAY); 1154 if (sc->sc_hctl_end == sqh) 1155 sc->sc_hctl_end = pqh; 1156 } 1157 1158 /* Add low speed control QH, called with lock held. */ 1159 void 1160 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1161 { 1162 uhci_soft_qh_t *eqh; 1163 1164 KASSERT(mutex_owned(&sc->sc_lock)); 1165 1166 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1167 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1168 1169 eqh = sc->sc_lctl_end; 1170 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1171 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1172 sqh->hlink = eqh->hlink; 1173 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1174 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1175 BUS_DMASYNC_PREWRITE); 1176 eqh->hlink = sqh; 1177 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1178 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1179 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1180 sc->sc_lctl_end = sqh; 1181 } 1182 1183 /* Remove low speed control QH, called with lock held. */ 1184 void 1185 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1186 { 1187 uhci_soft_qh_t *pqh; 1188 uint32_t elink; 1189 1190 KASSERT(mutex_owned(&sc->sc_lock)); 1191 1192 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1193 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1194 1195 /* See comment in uhci_remove_hs_ctrl() */ 1196 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1197 sizeof(sqh->qh.qh_elink), 1198 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1199 elink = le32toh(sqh->qh.qh_elink); 1200 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1201 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1202 if (!(elink & UHCI_PTR_T)) { 1203 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1204 usb_syncmem(&sqh->dma, 1205 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1206 sizeof(sqh->qh.qh_elink), 1207 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1208 delay(UHCI_QH_REMOVE_DELAY); 1209 } 1210 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1211 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1212 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1213 pqh->hlink = sqh->hlink; 1214 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1215 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1216 sizeof(pqh->qh.qh_hlink), 1217 BUS_DMASYNC_PREWRITE); 1218 delay(UHCI_QH_REMOVE_DELAY); 1219 if (sc->sc_lctl_end == sqh) 1220 sc->sc_lctl_end = pqh; 1221 } 1222 1223 /* Add bulk QH, called with lock held. */ 1224 void 1225 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1226 { 1227 uhci_soft_qh_t *eqh; 1228 1229 KASSERT(mutex_owned(&sc->sc_lock)); 1230 1231 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1232 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1233 1234 eqh = sc->sc_bulk_end; 1235 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1236 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1237 sqh->hlink = eqh->hlink; 1238 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1239 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1240 BUS_DMASYNC_PREWRITE); 1241 eqh->hlink = sqh; 1242 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1243 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1244 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1245 sc->sc_bulk_end = sqh; 1246 uhci_add_loop(sc); 1247 } 1248 1249 /* Remove bulk QH, called with lock held. */ 1250 void 1251 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1252 { 1253 uhci_soft_qh_t *pqh; 1254 1255 KASSERT(mutex_owned(&sc->sc_lock)); 1256 1257 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1258 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1259 1260 uhci_rem_loop(sc); 1261 /* See comment in uhci_remove_hs_ctrl() */ 1262 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1263 sizeof(sqh->qh.qh_elink), 1264 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1265 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1266 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1267 usb_syncmem(&sqh->dma, 1268 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1269 sizeof(sqh->qh.qh_elink), 1270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1271 delay(UHCI_QH_REMOVE_DELAY); 1272 } 1273 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1274 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1275 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1276 pqh->hlink = sqh->hlink; 1277 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1278 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1279 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1280 delay(UHCI_QH_REMOVE_DELAY); 1281 if (sc->sc_bulk_end == sqh) 1282 sc->sc_bulk_end = pqh; 1283 } 1284 1285 Static int uhci_intr1(uhci_softc_t *); 1286 1287 int 1288 uhci_intr(void *arg) 1289 { 1290 uhci_softc_t *sc = arg; 1291 int ret = 0; 1292 1293 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1294 1295 mutex_spin_enter(&sc->sc_intr_lock); 1296 1297 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1298 goto done; 1299 1300 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1301 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1302 goto done; 1303 } 1304 1305 ret = uhci_intr1(sc); 1306 1307 done: 1308 mutex_spin_exit(&sc->sc_intr_lock); 1309 return ret; 1310 } 1311 1312 int 1313 uhci_intr1(uhci_softc_t *sc) 1314 { 1315 int status; 1316 int ack; 1317 1318 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1319 1320 #ifdef UHCI_DEBUG 1321 if (uhcidebug >= 15) { 1322 DPRINTF("sc %p", sc, 0, 0, 0); 1323 uhci_dumpregs(sc); 1324 } 1325 #endif 1326 1327 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1328 1329 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1330 /* Check if the interrupt was for us. */ 1331 if (status == 0) 1332 return 0; 1333 1334 if (sc->sc_suspend != PWR_RESUME) { 1335 #ifdef DIAGNOSTIC 1336 printf("%s: interrupt while not operating ignored\n", 1337 device_xname(sc->sc_dev)); 1338 #endif 1339 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1340 return 0; 1341 } 1342 1343 ack = 0; 1344 if (status & UHCI_STS_USBINT) 1345 ack |= UHCI_STS_USBINT; 1346 if (status & UHCI_STS_USBEI) 1347 ack |= UHCI_STS_USBEI; 1348 if (status & UHCI_STS_RD) { 1349 ack |= UHCI_STS_RD; 1350 #ifdef UHCI_DEBUG 1351 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1352 #endif 1353 } 1354 if (status & UHCI_STS_HSE) { 1355 ack |= UHCI_STS_HSE; 1356 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1357 } 1358 if (status & UHCI_STS_HCPE) { 1359 ack |= UHCI_STS_HCPE; 1360 printf("%s: host controller process error\n", 1361 device_xname(sc->sc_dev)); 1362 } 1363 1364 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1365 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1366 /* no acknowledge needed */ 1367 if (!sc->sc_dying) { 1368 printf("%s: host controller halted\n", 1369 device_xname(sc->sc_dev)); 1370 #ifdef UHCI_DEBUG 1371 uhci_dump_all(sc); 1372 #endif 1373 } 1374 sc->sc_dying = 1; 1375 } 1376 1377 if (!ack) 1378 return 0; /* nothing to acknowledge */ 1379 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1380 1381 usb_schedsoftintr(&sc->sc_bus); 1382 1383 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1384 1385 return 1; 1386 } 1387 1388 void 1389 uhci_softintr(void *v) 1390 { 1391 struct usbd_bus *bus = v; 1392 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1393 struct uhci_xfer *ux, *nextux; 1394 ux_completeq_t cq; 1395 1396 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1397 DPRINTF("sc %p", sc, 0, 0, 0); 1398 1399 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1400 1401 TAILQ_INIT(&cq); 1402 /* 1403 * Interrupts on UHCI really suck. When the host controller 1404 * interrupts because a transfer is completed there is no 1405 * way of knowing which transfer it was. You can scan down 1406 * the TDs and QHs of the previous frame to limit the search, 1407 * but that assumes that the interrupt was not delayed by more 1408 * than 1 ms, which may not always be true (e.g. after debug 1409 * output on a slow console). 1410 * We scan all interrupt descriptors to see if any have 1411 * completed. 1412 */ 1413 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1414 uhci_check_intr(sc, ux, &cq); 1415 } 1416 1417 /* 1418 * We abuse ux_list for the interrupt and complete lists and 1419 * interrupt transfers will get re-added here so use 1420 * the _SAFE version of TAILQ_FOREACH. 1421 */ 1422 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1423 DPRINTF("ux %p", ux, 0, 0, 0); 1424 usb_transfer_complete(&ux->ux_xfer); 1425 } 1426 1427 if (sc->sc_softwake) { 1428 sc->sc_softwake = 0; 1429 cv_broadcast(&sc->sc_softwake_cv); 1430 } 1431 } 1432 1433 /* Check for an interrupt. */ 1434 void 1435 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1436 { 1437 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1438 uint32_t status; 1439 1440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1441 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1442 1443 KASSERT(ux != NULL); 1444 1445 struct usbd_xfer *xfer = &ux->ux_xfer; 1446 if (xfer->ux_status == USBD_CANCELLED || 1447 xfer->ux_status == USBD_TIMEOUT) { 1448 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1449 return; 1450 } 1451 1452 switch (ux->ux_type) { 1453 case UX_CTRL: 1454 fstd = ux->ux_setup; 1455 lstd = ux->ux_stat; 1456 break; 1457 case UX_BULK: 1458 case UX_INTR: 1459 case UX_ISOC: 1460 fstd = ux->ux_stdstart; 1461 lstd = ux->ux_stdend; 1462 break; 1463 default: 1464 KASSERT(false); 1465 break; 1466 } 1467 if (fstd == NULL) 1468 return; 1469 1470 KASSERT(lstd != NULL); 1471 1472 usb_syncmem(&lstd->dma, 1473 lstd->offs + offsetof(uhci_td_t, td_status), 1474 sizeof(lstd->td.td_status), 1475 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1476 status = le32toh(lstd->td.td_status); 1477 usb_syncmem(&lstd->dma, 1478 lstd->offs + offsetof(uhci_td_t, td_status), 1479 sizeof(lstd->td.td_status), 1480 BUS_DMASYNC_PREREAD); 1481 1482 /* If the last TD is not marked active we can complete */ 1483 if (!(status & UHCI_TD_ACTIVE)) { 1484 done: 1485 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1486 1487 callout_stop(&xfer->ux_callout); 1488 uhci_idone(ux, cqp); 1489 return; 1490 } 1491 1492 /* 1493 * If the last TD is still active we need to check whether there 1494 * is an error somewhere in the middle, or whether there was a 1495 * short packet (SPD and not ACTIVE). 1496 */ 1497 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1498 for (std = fstd; std != lstd; std = std->link.std) { 1499 usb_syncmem(&std->dma, 1500 std->offs + offsetof(uhci_td_t, td_status), 1501 sizeof(std->td.td_status), 1502 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1503 status = le32toh(std->td.td_status); 1504 usb_syncmem(&std->dma, 1505 std->offs + offsetof(uhci_td_t, td_status), 1506 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1507 1508 /* If there's an active TD the xfer isn't done. */ 1509 if (status & UHCI_TD_ACTIVE) { 1510 DPRINTFN(12, "ux=%p std=%p still active", 1511 ux, std, 0, 0); 1512 return; 1513 } 1514 1515 /* Any kind of error makes the xfer done. */ 1516 if (status & UHCI_TD_STALLED) 1517 goto done; 1518 1519 /* 1520 * If the data phase of a control transfer is short, we need 1521 * to complete the status stage 1522 */ 1523 1524 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1525 struct uhci_pipe *upipe = 1526 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1527 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1528 uhci_soft_td_t *stat = upipe->ctrl.stat; 1529 1530 DPRINTFN(12, "ux=%p std=%p control status" 1531 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1532 1533 sqh->qh.qh_elink = 1534 htole32(stat->physaddr | UHCI_PTR_TD); 1535 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1536 BUS_DMASYNC_PREWRITE); 1537 break; 1538 } 1539 1540 /* We want short packets, and it is short: it's done */ 1541 usb_syncmem(&std->dma, 1542 std->offs + offsetof(uhci_td_t, td_token), 1543 sizeof(std->td.td_token), 1544 BUS_DMASYNC_POSTWRITE); 1545 1546 if ((status & UHCI_TD_SPD) && 1547 UHCI_TD_GET_ACTLEN(status) < 1548 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1549 goto done; 1550 } 1551 } 1552 } 1553 1554 /* Called with USB lock held. */ 1555 void 1556 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1557 { 1558 struct usbd_xfer *xfer = &ux->ux_xfer; 1559 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1560 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1561 uhci_soft_td_t *std; 1562 uint32_t status = 0, nstatus; 1563 int actlen; 1564 1565 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1566 1567 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1568 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1569 1570 #ifdef DIAGNOSTIC 1571 #ifdef UHCI_DEBUG 1572 if (ux->ux_isdone) { 1573 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1574 uhci_dump_ii(ux); 1575 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1576 } 1577 #endif 1578 KASSERT(!ux->ux_isdone); 1579 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1580 ux->ux_type, xfer->ux_status); 1581 ux->ux_isdone = true; 1582 #endif 1583 1584 if (xfer->ux_nframes != 0) { 1585 /* Isoc transfer, do things differently. */ 1586 uhci_soft_td_t **stds = upipe->isoc.stds; 1587 int i, n, nframes, len; 1588 1589 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1590 1591 nframes = xfer->ux_nframes; 1592 actlen = 0; 1593 n = ux->ux_curframe; 1594 for (i = 0; i < nframes; i++) { 1595 std = stds[n]; 1596 #ifdef UHCI_DEBUG 1597 if (uhcidebug >= 5) { 1598 DPRINTF("isoc TD %d", i, 0, 0, 0); 1599 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1600 uhci_dump_td(std); 1601 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1602 } 1603 #endif 1604 if (++n >= UHCI_VFRAMELIST_COUNT) 1605 n = 0; 1606 usb_syncmem(&std->dma, 1607 std->offs + offsetof(uhci_td_t, td_status), 1608 sizeof(std->td.td_status), 1609 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1610 status = le32toh(std->td.td_status); 1611 len = UHCI_TD_GET_ACTLEN(status); 1612 xfer->ux_frlengths[i] = len; 1613 actlen += len; 1614 } 1615 upipe->isoc.inuse -= nframes; 1616 xfer->ux_actlen = actlen; 1617 xfer->ux_status = USBD_NORMAL_COMPLETION; 1618 goto end; 1619 } 1620 1621 #ifdef UHCI_DEBUG 1622 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1623 if (uhcidebug >= 10) { 1624 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1625 uhci_dump_tds(ux->ux_stdstart); 1626 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1627 } 1628 #endif 1629 1630 /* The transfer is done, compute actual length and status. */ 1631 actlen = 0; 1632 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1633 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1634 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1635 nstatus = le32toh(std->td.td_status); 1636 if (nstatus & UHCI_TD_ACTIVE) 1637 break; 1638 1639 status = nstatus; 1640 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1641 UHCI_TD_PID_SETUP) 1642 actlen += UHCI_TD_GET_ACTLEN(status); 1643 else { 1644 /* 1645 * UHCI will report CRCTO in addition to a STALL or NAK 1646 * for a SETUP transaction. See section 3.2.2, "TD 1647 * CONTROL AND STATUS". 1648 */ 1649 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1650 status &= ~UHCI_TD_CRCTO; 1651 } 1652 } 1653 /* If there are left over TDs we need to update the toggle. */ 1654 if (std != NULL) 1655 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1656 1657 status &= UHCI_TD_ERROR; 1658 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1659 xfer->ux_actlen = actlen; 1660 if (status != 0) { 1661 1662 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1663 "error, addr=%d, endpt=0x%02x", 1664 xfer->ux_pipe->up_dev->ud_addr, 1665 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1666 0, 0); 1667 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1668 "bitstuff=%d crcto =%d nak =%d babble =%d", 1669 !!(status & UHCI_TD_BITSTUFF), 1670 !!(status & UHCI_TD_CRCTO), 1671 !!(status & UHCI_TD_NAK), 1672 !!(status & UHCI_TD_BABBLE)); 1673 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1674 "dbuffer =%d stalled =%d active =%d", 1675 !!(status & UHCI_TD_DBUFFER), 1676 !!(status & UHCI_TD_STALLED), 1677 !!(status & UHCI_TD_ACTIVE), 1678 0); 1679 1680 if (status == UHCI_TD_STALLED) 1681 xfer->ux_status = USBD_STALLED; 1682 else 1683 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1684 } else { 1685 xfer->ux_status = USBD_NORMAL_COMPLETION; 1686 } 1687 1688 end: 1689 uhci_del_intr_list(sc, ux); 1690 if (cqp) 1691 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1692 1693 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1694 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1695 } 1696 1697 /* 1698 * Called when a request does not complete. 1699 */ 1700 void 1701 uhci_timeout(void *addr) 1702 { 1703 struct usbd_xfer *xfer = addr; 1704 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1705 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1706 1707 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1708 1709 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1710 1711 if (sc->sc_dying) { 1712 mutex_enter(&sc->sc_lock); 1713 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1714 mutex_exit(&sc->sc_lock); 1715 return; 1716 } 1717 1718 /* Execute the abort in a process context. */ 1719 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1720 USB_TASKQ_MPSAFE); 1721 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1722 USB_TASKQ_HC); 1723 } 1724 1725 void 1726 uhci_timeout_task(void *addr) 1727 { 1728 struct usbd_xfer *xfer = addr; 1729 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1730 1731 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1732 1733 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1734 1735 mutex_enter(&sc->sc_lock); 1736 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1737 mutex_exit(&sc->sc_lock); 1738 } 1739 1740 /* 1741 * Wait here until controller claims to have an interrupt. 1742 * Then call uhci_intr and return. Use timeout to avoid waiting 1743 * too long. 1744 * Only used during boot when interrupts are not enabled yet. 1745 */ 1746 void 1747 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1748 { 1749 int timo = xfer->ux_timeout; 1750 struct uhci_xfer *ux; 1751 1752 mutex_enter(&sc->sc_lock); 1753 1754 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1755 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1756 1757 xfer->ux_status = USBD_IN_PROGRESS; 1758 for (; timo >= 0; timo--) { 1759 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1760 DPRINTFN(20, "0x%04x", 1761 UREAD2(sc, UHCI_STS), 0, 0, 0); 1762 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1763 mutex_spin_enter(&sc->sc_intr_lock); 1764 uhci_intr1(sc); 1765 mutex_spin_exit(&sc->sc_intr_lock); 1766 if (xfer->ux_status != USBD_IN_PROGRESS) 1767 goto done; 1768 } 1769 } 1770 1771 /* Timeout */ 1772 DPRINTF("timeout", 0, 0, 0, 0); 1773 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 1774 if (&ux->ux_xfer == xfer) 1775 break; 1776 1777 KASSERT(ux != NULL); 1778 1779 uhci_idone(ux, NULL); 1780 usb_transfer_complete(&ux->ux_xfer); 1781 1782 done: 1783 mutex_exit(&sc->sc_lock); 1784 } 1785 1786 void 1787 uhci_poll(struct usbd_bus *bus) 1788 { 1789 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1790 1791 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1792 mutex_spin_enter(&sc->sc_intr_lock); 1793 uhci_intr1(sc); 1794 mutex_spin_exit(&sc->sc_intr_lock); 1795 } 1796 } 1797 1798 void 1799 uhci_reset(uhci_softc_t *sc) 1800 { 1801 int n; 1802 1803 UHCICMD(sc, UHCI_CMD_HCRESET); 1804 /* The reset bit goes low when the controller is done. */ 1805 for (n = 0; n < UHCI_RESET_TIMEOUT && 1806 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1807 usb_delay_ms(&sc->sc_bus, 1); 1808 if (n >= UHCI_RESET_TIMEOUT) 1809 printf("%s: controller did not reset\n", 1810 device_xname(sc->sc_dev)); 1811 } 1812 1813 usbd_status 1814 uhci_run(uhci_softc_t *sc, int run, int locked) 1815 { 1816 int n, running; 1817 uint16_t cmd; 1818 1819 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1820 1821 run = run != 0; 1822 if (!locked) 1823 mutex_spin_enter(&sc->sc_intr_lock); 1824 1825 DPRINTF("setting run=%d", run, 0, 0, 0); 1826 cmd = UREAD2(sc, UHCI_CMD); 1827 if (run) 1828 cmd |= UHCI_CMD_RS; 1829 else 1830 cmd &= ~UHCI_CMD_RS; 1831 UHCICMD(sc, cmd); 1832 for (n = 0; n < 10; n++) { 1833 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1834 /* return when we've entered the state we want */ 1835 if (run == running) { 1836 if (!locked) 1837 mutex_spin_exit(&sc->sc_intr_lock); 1838 DPRINTF("done cmd=0x%x sts=0x%x", 1839 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1840 return USBD_NORMAL_COMPLETION; 1841 } 1842 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1843 } 1844 if (!locked) 1845 mutex_spin_exit(&sc->sc_intr_lock); 1846 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1847 run ? "start" : "stop"); 1848 return USBD_IOERROR; 1849 } 1850 1851 /* 1852 * Memory management routines. 1853 * uhci_alloc_std allocates TDs 1854 * uhci_alloc_sqh allocates QHs 1855 * These two routines do their own free list management, 1856 * partly for speed, partly because allocating DMAable memory 1857 * has page size granularity so much memory would be wasted if 1858 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1859 */ 1860 1861 uhci_soft_td_t * 1862 uhci_alloc_std(uhci_softc_t *sc) 1863 { 1864 uhci_soft_td_t *std; 1865 usbd_status err; 1866 int i, offs; 1867 usb_dma_t dma; 1868 1869 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1870 1871 mutex_enter(&sc->sc_lock); 1872 if (sc->sc_freetds == NULL) { 1873 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1874 mutex_exit(&sc->sc_lock); 1875 1876 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1877 UHCI_TD_ALIGN, &dma); 1878 if (err) 1879 return NULL; 1880 1881 mutex_enter(&sc->sc_lock); 1882 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1883 offs = i * UHCI_STD_SIZE; 1884 std = KERNADDR(&dma, offs); 1885 std->physaddr = DMAADDR(&dma, offs); 1886 std->dma = dma; 1887 std->offs = offs; 1888 std->link.std = sc->sc_freetds; 1889 sc->sc_freetds = std; 1890 } 1891 } 1892 std = sc->sc_freetds; 1893 sc->sc_freetds = std->link.std; 1894 mutex_exit(&sc->sc_lock); 1895 1896 memset(&std->td, 0, sizeof(uhci_td_t)); 1897 1898 return std; 1899 } 1900 1901 #define TD_IS_FREE 0x12345678 1902 1903 void 1904 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1905 { 1906 KASSERT(mutex_owned(&sc->sc_lock)); 1907 1908 #ifdef DIAGNOSTIC 1909 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1910 printf("%s: freeing free TD %p\n", __func__, std); 1911 return; 1912 } 1913 std->td.td_token = htole32(TD_IS_FREE); 1914 #endif 1915 1916 std->link.std = sc->sc_freetds; 1917 sc->sc_freetds = std; 1918 } 1919 1920 void 1921 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1922 { 1923 mutex_enter(&sc->sc_lock); 1924 uhci_free_std_locked(sc, std); 1925 mutex_exit(&sc->sc_lock); 1926 } 1927 1928 uhci_soft_qh_t * 1929 uhci_alloc_sqh(uhci_softc_t *sc) 1930 { 1931 uhci_soft_qh_t *sqh; 1932 usbd_status err; 1933 int i, offs; 1934 usb_dma_t dma; 1935 1936 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1937 1938 mutex_enter(&sc->sc_lock); 1939 if (sc->sc_freeqhs == NULL) { 1940 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1941 mutex_exit(&sc->sc_lock); 1942 1943 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1944 UHCI_QH_ALIGN, &dma); 1945 if (err) 1946 return NULL; 1947 1948 mutex_enter(&sc->sc_lock); 1949 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1950 offs = i * UHCI_SQH_SIZE; 1951 sqh = KERNADDR(&dma, offs); 1952 sqh->physaddr = DMAADDR(&dma, offs); 1953 sqh->dma = dma; 1954 sqh->offs = offs; 1955 sqh->hlink = sc->sc_freeqhs; 1956 sc->sc_freeqhs = sqh; 1957 } 1958 } 1959 sqh = sc->sc_freeqhs; 1960 sc->sc_freeqhs = sqh->hlink; 1961 mutex_exit(&sc->sc_lock); 1962 1963 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1964 1965 return sqh; 1966 } 1967 1968 void 1969 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1970 { 1971 KASSERT(mutex_owned(&sc->sc_lock)); 1972 1973 sqh->hlink = sc->sc_freeqhs; 1974 sc->sc_freeqhs = sqh; 1975 } 1976 1977 void 1978 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1979 uhci_soft_td_t *stdend) 1980 { 1981 uhci_soft_td_t *p; 1982 uint32_t td_link; 1983 1984 /* 1985 * to avoid race condition with the controller which may be looking 1986 * at this chain, we need to first invalidate all links, and 1987 * then wait for the controller to move to another queue 1988 */ 1989 for (p = std; p != stdend; p = p->link.std) { 1990 usb_syncmem(&p->dma, 1991 p->offs + offsetof(uhci_td_t, td_link), 1992 sizeof(p->td.td_link), 1993 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1994 td_link = le32toh(p->td.td_link); 1995 usb_syncmem(&p->dma, 1996 p->offs + offsetof(uhci_td_t, td_link), 1997 sizeof(p->td.td_link), 1998 BUS_DMASYNC_PREREAD); 1999 if ((td_link & UHCI_PTR_T) == 0) { 2000 p->td.td_link = htole32(UHCI_PTR_T); 2001 usb_syncmem(&p->dma, 2002 p->offs + offsetof(uhci_td_t, td_link), 2003 sizeof(p->td.td_link), 2004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2005 } 2006 } 2007 delay(UHCI_QH_REMOVE_DELAY); 2008 2009 for (; std != stdend; std = p) { 2010 p = std->link.std; 2011 uhci_free_std(sc, std); 2012 } 2013 } 2014 2015 usbd_status 2016 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int alen, 2017 int rd, uhci_soft_td_t **sp, uhci_soft_td_t **ep) 2018 { 2019 uhci_soft_td_t *p, *lastp; 2020 uhci_physaddr_t lastlink; 2021 int i, l, maxp; 2022 int len; 2023 uint32_t status; 2024 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2025 int addr = xfer->ux_pipe->up_dev->ud_addr; 2026 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2027 usb_dma_t *dma = &xfer->ux_dmabuf; 2028 uint16_t flags = xfer->ux_flags; 2029 2030 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2031 2032 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 2033 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 2034 addr, UE_GET_ADDR(endpt), alen, xfer->ux_pipe->up_dev->ud_speed); 2035 2036 ASSERT_SLEEPABLE(); 2037 KASSERT(sp); 2038 2039 len = alen; 2040 maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2041 if (maxp == 0) { 2042 printf("%s: maxp=0\n", __func__); 2043 return USBD_INVAL; 2044 } 2045 size_t ntd = (len + maxp - 1) / maxp; 2046 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 2047 ntd++; 2048 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 2049 2050 uxfer->ux_stds = NULL; 2051 uxfer->ux_nstd = ntd; 2052 if (ntd == 0) { 2053 *sp = NULL; 2054 if (ep) 2055 *ep = NULL; 2056 DPRINTF("ntd=0", 0, 0, 0, 0); 2057 return USBD_NORMAL_COMPLETION; 2058 } 2059 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2060 KM_SLEEP); 2061 2062 lastp = NULL; 2063 ntd--; 2064 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2065 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_LOW) 2066 status |= UHCI_TD_LS; 2067 if (flags & USBD_SHORT_XFER_OK) 2068 status |= UHCI_TD_SPD; 2069 for (i = ntd; i >= 0; i--) { 2070 p = uhci_alloc_std(sc); 2071 if (p == NULL) { 2072 uhci_free_std_chain(sc, lastp, NULL); 2073 return USBD_NOMEM; 2074 } 2075 uxfer->ux_stds[i] = p; 2076 if (i == ntd) { 2077 /* last TD */ 2078 l = len % maxp; 2079 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 2080 l = maxp; 2081 if (ep) 2082 *ep = p; 2083 lastlink = UHCI_PTR_T; 2084 } else { 2085 l = maxp; 2086 lastlink = p->physaddr; 2087 } 2088 p->link.std = lastp; 2089 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 2090 p->td.td_status = htole32(status); 2091 p->td.td_token = htole32( 2092 (rd ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2093 UHCI_TD_SET_MAXLEN(l) | 2094 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2095 UHCI_TD_SET_DEVADDR(addr) 2096 ); 2097 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2098 DPRINTF("std %p link 0x%08x status 0x%08x token 0x%08x", 2099 p, le32toh(p->td.td_link), le32toh(p->td.td_status), 2100 le32toh(p->td.td_token)); 2101 2102 lastp = p; 2103 } 2104 *sp = lastp; 2105 2106 return USBD_NORMAL_COMPLETION; 2107 } 2108 2109 Static void 2110 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2111 { 2112 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2113 2114 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2115 2116 mutex_enter(&sc->sc_lock); 2117 for (size_t i = 0; i < ux->ux_nstd; i++) { 2118 uhci_soft_td_t *std = ux->ux_stds[i]; 2119 #ifdef DIAGNOSTIC 2120 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2121 printf("%s: freeing free TD %p\n", __func__, std); 2122 return; 2123 } 2124 std->td.td_token = htole32(TD_IS_FREE); 2125 #endif 2126 ux->ux_stds[i]->link.std = sc->sc_freetds; 2127 sc->sc_freetds = std; 2128 } 2129 mutex_exit(&sc->sc_lock); 2130 } 2131 2132 2133 Static void 2134 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2135 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2136 { 2137 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2138 struct usbd_pipe *pipe = xfer->ux_pipe; 2139 usb_dma_t *dma = &xfer->ux_dmabuf; 2140 uint16_t flags = xfer->ux_flags; 2141 uhci_soft_td_t *std, *prev; 2142 int len = length; 2143 int tog = *toggle; 2144 int maxp; 2145 uint32_t status; 2146 size_t i; 2147 2148 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2149 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2150 len, isread, *toggle); 2151 2152 KASSERT(len != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2153 2154 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2155 KASSERT(maxp != 0); 2156 2157 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2158 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2159 status |= UHCI_TD_LS; 2160 if (flags & USBD_SHORT_XFER_OK) 2161 status |= UHCI_TD_SPD; 2162 usb_syncmem(dma, 0, len, 2163 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2164 2165 std = prev = NULL; 2166 for (i = 0; i < uxfer->ux_nstd; i++, prev = std) { 2167 int l = len; 2168 std = uxfer->ux_stds[i]; 2169 if (l > maxp) 2170 l = maxp; 2171 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 2172 break; 2173 2174 if (prev) { 2175 prev->link.std = std; 2176 prev->td.td_link = htole32( 2177 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2178 ); 2179 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2181 } 2182 2183 int addr __diagused = xfer->ux_pipe->up_dev->ud_addr; 2184 int endpt __diagused = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2185 KASSERTMSG(UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)) == UE_GET_ADDR(endpt), 2186 "%" __PRIuBIT " vs %d (0x%08x) in %p", 2187 UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)), 2188 UE_GET_ADDR(endpt), le32toh(std->td.td_token), std); 2189 KASSERTMSG(UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)) == addr, 2190 "%" __PRIuBIT " vs %d (0x%08x) in %p", 2191 UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)), addr, 2192 le32toh(std->td.td_token), std); 2193 2194 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2195 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2196 2197 std->td.td_status = htole32(status); 2198 std->td.td_token &= ~htole32( 2199 UHCI_TD_PID_MASK | 2200 UHCI_TD_DT_MASK | 2201 UHCI_TD_MAXLEN_MASK 2202 ); 2203 std->td.td_token |= htole32( 2204 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2205 UHCI_TD_SET_DT(tog) | 2206 UHCI_TD_SET_MAXLEN(l) 2207 ); 2208 std->td.td_link &= ~htole32(UHCI_PTR_T); 2209 2210 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2211 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2212 tog ^= 1; 2213 2214 len -= l; 2215 if (len == 0) 2216 break; 2217 } 2218 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2219 xfer, length, len, maxp, uxfer->ux_nstd, i); 2220 2221 if (i < uxfer->ux_nstd) { 2222 /* 2223 * The full allocation chain wasn't used, so we need to 2224 * terminate it. 2225 */ 2226 std->link.std = NULL; 2227 std->td.td_link = htole32(UHCI_PTR_T); 2228 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2229 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2230 } 2231 *lstd = std; 2232 *toggle = tog; 2233 } 2234 2235 void 2236 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2237 { 2238 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2239 upipe->nexttoggle = 0; 2240 } 2241 2242 void 2243 uhci_noop(struct usbd_pipe *pipe) 2244 { 2245 } 2246 2247 int 2248 uhci_device_bulk_init(struct usbd_xfer *xfer) 2249 { 2250 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2251 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2252 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2253 int endpt = ed->bEndpointAddress; 2254 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2255 int len = xfer->ux_bufsize; 2256 int err = 0; 2257 2258 2259 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2260 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2261 2262 if (sc->sc_dying) 2263 return USBD_IOERROR; 2264 2265 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2266 2267 uxfer->ux_type = UX_BULK; 2268 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart, 2269 &uxfer->ux_stdend); 2270 if (err) 2271 return err; 2272 2273 #ifdef UHCI_DEBUG 2274 if (uhcidebug >= 10) { 2275 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2276 uhci_dump_tds(uxfer->ux_stdstart); 2277 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2278 } 2279 #endif 2280 2281 return 0; 2282 } 2283 2284 Static void 2285 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2286 { 2287 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2288 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2289 2290 KASSERT(ux->ux_type == UX_BULK); 2291 2292 uhci_free_stds(sc, ux); 2293 if (ux->ux_nstd) 2294 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2295 } 2296 2297 usbd_status 2298 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2299 { 2300 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2301 usbd_status err; 2302 2303 /* Insert last in queue. */ 2304 mutex_enter(&sc->sc_lock); 2305 err = usb_insert_transfer(xfer); 2306 mutex_exit(&sc->sc_lock); 2307 if (err) 2308 return err; 2309 2310 /* 2311 * Pipe isn't running (otherwise err would be USBD_INPROG), 2312 * so start it first. 2313 */ 2314 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2315 } 2316 2317 usbd_status 2318 uhci_device_bulk_start(struct usbd_xfer *xfer) 2319 { 2320 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2321 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2322 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2323 uhci_soft_td_t *data, *dataend; 2324 uhci_soft_qh_t *sqh; 2325 int len; 2326 int endpt; 2327 int isread; 2328 2329 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2330 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2331 xfer->ux_flags, 0); 2332 2333 if (sc->sc_dying) 2334 return USBD_IOERROR; 2335 2336 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2337 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2338 2339 len = xfer->ux_length; 2340 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2341 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2342 sqh = upipe->bulk.sqh; 2343 2344 /* Take lock here to protect nexttoggle */ 2345 mutex_enter(&sc->sc_lock); 2346 2347 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2348 &dataend); 2349 2350 data = ux->ux_stdstart; 2351 ux->ux_stdend = dataend; 2352 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2353 usb_syncmem(&dataend->dma, 2354 dataend->offs + offsetof(uhci_td_t, td_status), 2355 sizeof(dataend->td.td_status), 2356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2357 2358 #ifdef UHCI_DEBUG 2359 if (uhcidebug >= 10) { 2360 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2361 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2362 uhci_dump_tds(data); 2363 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2364 } 2365 #endif 2366 2367 KASSERT(ux->ux_isdone); 2368 #ifdef DIAGNOSTIC 2369 ux->ux_isdone = false; 2370 #endif 2371 2372 sqh->elink = data; 2373 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2374 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2375 2376 uhci_add_bulk(sc, sqh); 2377 uhci_add_intr_list(sc, ux); 2378 2379 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2380 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2381 uhci_timeout, xfer); 2382 } 2383 xfer->ux_status = USBD_IN_PROGRESS; 2384 mutex_exit(&sc->sc_lock); 2385 2386 if (sc->sc_bus.ub_usepolling) 2387 uhci_waitintr(sc, xfer); 2388 2389 return USBD_IN_PROGRESS; 2390 } 2391 2392 /* Abort a device bulk request. */ 2393 void 2394 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2395 { 2396 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2397 2398 KASSERT(mutex_owned(&sc->sc_lock)); 2399 2400 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2401 2402 uhci_abort_xfer(xfer, USBD_CANCELLED); 2403 } 2404 2405 /* 2406 * Abort a device request. 2407 * If this routine is called at splusb() it guarantees that the request 2408 * will be removed from the hardware scheduling and that the callback 2409 * for it will be called with USBD_CANCELLED status. 2410 * It's impossible to guarantee that the requested transfer will not 2411 * have happened since the hardware runs concurrently. 2412 * If the transaction has already happened we rely on the ordinary 2413 * interrupt processing to process it. 2414 * XXX This is most probably wrong. 2415 * XXXMRG this doesn't make sense anymore. 2416 */ 2417 void 2418 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2419 { 2420 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2421 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2422 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2423 uhci_soft_td_t *std; 2424 int wake; 2425 2426 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2427 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2428 2429 KASSERT(mutex_owned(&sc->sc_lock)); 2430 ASSERT_SLEEPABLE(); 2431 2432 if (sc->sc_dying) { 2433 /* If we're dying, just do the software part. */ 2434 xfer->ux_status = status; /* make software ignore it */ 2435 callout_stop(&xfer->ux_callout); 2436 usb_transfer_complete(xfer); 2437 return; 2438 } 2439 2440 /* 2441 * If an abort is already in progress then just wait for it to 2442 * complete and return. 2443 */ 2444 if (xfer->ux_hcflags & UXFER_ABORTING) { 2445 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2446 #ifdef DIAGNOSTIC 2447 if (status == USBD_TIMEOUT) 2448 printf("%s: TIMEOUT while aborting\n", __func__); 2449 #endif 2450 /* Override the status which might be USBD_TIMEOUT. */ 2451 xfer->ux_status = status; 2452 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2453 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2454 while (xfer->ux_hcflags & UXFER_ABORTING) 2455 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2456 goto done; 2457 } 2458 xfer->ux_hcflags |= UXFER_ABORTING; 2459 2460 /* 2461 * Step 1: Make interrupt routine and hardware ignore xfer. 2462 */ 2463 xfer->ux_status = status; /* make software ignore it */ 2464 callout_stop(&xfer->ux_callout); 2465 uhci_del_intr_list(sc, ux); 2466 2467 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2468 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2469 usb_syncmem(&std->dma, 2470 std->offs + offsetof(uhci_td_t, td_status), 2471 sizeof(std->td.td_status), 2472 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2473 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2474 usb_syncmem(&std->dma, 2475 std->offs + offsetof(uhci_td_t, td_status), 2476 sizeof(std->td.td_status), 2477 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2478 } 2479 2480 /* 2481 * Step 2: Wait until we know hardware has finished any possible 2482 * use of the xfer. Also make sure the soft interrupt routine 2483 * has run. 2484 */ 2485 /* Hardware finishes in 1ms */ 2486 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2487 sc->sc_softwake = 1; 2488 usb_schedsoftintr(&sc->sc_bus); 2489 DPRINTF("cv_wait", 0, 0, 0, 0); 2490 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2491 2492 /* 2493 * Step 3: Execute callback. 2494 */ 2495 DPRINTF("callback", 0, 0, 0, 0); 2496 #ifdef DIAGNOSTIC 2497 ux->ux_isdone = true; 2498 #endif 2499 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2500 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2501 usb_transfer_complete(xfer); 2502 if (wake) 2503 cv_broadcast(&xfer->ux_hccv); 2504 done: 2505 KASSERT(mutex_owned(&sc->sc_lock)); 2506 } 2507 2508 /* Close a device bulk pipe. */ 2509 void 2510 uhci_device_bulk_close(struct usbd_pipe *pipe) 2511 { 2512 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2513 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2514 2515 KASSERT(mutex_owned(&sc->sc_lock)); 2516 2517 uhci_free_sqh(sc, upipe->bulk.sqh); 2518 2519 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2520 } 2521 2522 int 2523 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2524 { 2525 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2526 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2527 usb_device_request_t *req = &xfer->ux_request; 2528 struct usbd_device *dev = upipe->pipe.up_dev; 2529 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2530 int addr = dev->ud_addr; 2531 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2532 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2533 int len; 2534 uint32_t ls; 2535 usbd_status err; 2536 int isread; 2537 2538 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2539 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", xfer->ux_bufsize, 2540 dev->ud_addr, endpt, 0); 2541 2542 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2543 isread = req->bmRequestType & UT_READ; 2544 len = xfer->ux_bufsize; 2545 2546 uxfer->ux_type = UX_CTRL; 2547 setup = upipe->ctrl.setup; 2548 stat = upipe->ctrl.stat; 2549 2550 /* Set up data transaction */ 2551 if (len != 0) { 2552 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data, 2553 &dataend); 2554 if (err) 2555 return err; 2556 next = data; 2557 dataend->link.std = stat; 2558 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2559 } else { 2560 next = stat; 2561 } 2562 2563 setup->link.std = next; 2564 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2565 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2566 UHCI_TD_ACTIVE); 2567 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2568 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2569 2570 stat->link.std = NULL; 2571 stat->td.td_link = htole32(UHCI_PTR_T); 2572 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2573 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2574 stat->td.td_token = 2575 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2576 UHCI_TD_IN (0, endpt, addr, 1)); 2577 stat->td.td_buffer = htole32(0); 2578 2579 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2580 #ifdef UHCI_DEBUG 2581 if (uhcidebug >= 10) { 2582 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2583 uhci_dump_tds(setup); 2584 } 2585 #endif 2586 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2587 2588 /* Set up interrupt info. */ 2589 uxfer->ux_setup = setup; 2590 uxfer->ux_data = data; 2591 uxfer->ux_stat = stat; 2592 2593 return 0; 2594 } 2595 2596 Static void 2597 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2598 { 2599 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2600 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2601 2602 KASSERT(ux->ux_type == UX_CTRL); 2603 2604 uhci_free_stds(sc, ux); 2605 if (ux->ux_nstd) 2606 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2607 } 2608 2609 usbd_status 2610 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2611 { 2612 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2613 usbd_status err; 2614 2615 /* Insert last in queue. */ 2616 mutex_enter(&sc->sc_lock); 2617 err = usb_insert_transfer(xfer); 2618 mutex_exit(&sc->sc_lock); 2619 if (err) 2620 return err; 2621 2622 /* 2623 * Pipe isn't running (otherwise err would be USBD_INPROG), 2624 * so start it first. 2625 */ 2626 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2627 } 2628 2629 usbd_status 2630 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2631 { 2632 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2633 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2634 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2635 usb_device_request_t *req = &xfer->ux_request; 2636 struct usbd_device *dev = upipe->pipe.up_dev; 2637 int addr = dev->ud_addr; 2638 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2639 uhci_soft_td_t *setup, *stat, *next, *dataend; 2640 uhci_soft_qh_t *sqh; 2641 int len; 2642 uint32_t ls; 2643 int isread; 2644 2645 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2646 2647 if (sc->sc_dying) 2648 return USBD_IOERROR; 2649 2650 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2651 2652 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2653 "wValue=0x%04x, wIndex=0x%04x", 2654 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2655 UGETW(req->wIndex)); 2656 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2657 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2658 2659 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2660 isread = req->bmRequestType & UT_READ; 2661 len = UGETW(req->wLength); 2662 2663 setup = upipe->ctrl.setup; 2664 stat = upipe->ctrl.stat; 2665 sqh = upipe->ctrl.sqh; 2666 2667 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2668 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2669 2670 mutex_enter(&sc->sc_lock); 2671 2672 /* Set up data transaction */ 2673 if (len != 0) { 2674 upipe->nexttoggle = 1; 2675 next = uxfer->ux_data; 2676 uhci_reset_std_chain(sc, xfer, len, isread, 2677 &upipe->nexttoggle, &dataend); 2678 dataend->link.std = stat; 2679 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2680 usb_syncmem(&dataend->dma, 2681 dataend->offs + offsetof(uhci_td_t, td_link), 2682 sizeof(dataend->td.td_link), 2683 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2684 } else { 2685 next = stat; 2686 } 2687 2688 setup->link.std = next; 2689 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2690 setup->td.td_status |= htole32( 2691 UHCI_TD_SET_ERRCNT(3) | 2692 ls | 2693 UHCI_TD_ACTIVE 2694 ); 2695 setup->td.td_token &= ~htole32(UHCI_TD_MAXLEN_MASK); 2696 setup->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(sizeof(*req))); 2697 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2698 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2699 2700 stat->link.std = NULL; 2701 stat->td.td_link = htole32(UHCI_PTR_T); 2702 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2703 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2704 stat->td.td_token = 2705 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2706 UHCI_TD_IN (0, endpt, addr, 1)); 2707 stat->td.td_buffer = htole32(0); 2708 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2709 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2710 2711 #ifdef UHCI_DEBUG 2712 if (uhcidebug >= 10) { 2713 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2714 DPRINTF("before transfer", 0, 0, 0, 0); 2715 uhci_dump_tds(setup); 2716 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2717 } 2718 #endif 2719 2720 /* Set up interrupt info. */ 2721 uxfer->ux_setup = setup; 2722 uxfer->ux_stat = stat; 2723 KASSERT(uxfer->ux_isdone); 2724 #ifdef DIAGNOSTIC 2725 uxfer->ux_isdone = false; 2726 #endif 2727 2728 sqh->elink = setup; 2729 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2730 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2731 2732 if (dev->ud_speed == USB_SPEED_LOW) 2733 uhci_add_ls_ctrl(sc, sqh); 2734 else 2735 uhci_add_hs_ctrl(sc, sqh); 2736 uhci_add_intr_list(sc, uxfer); 2737 #ifdef UHCI_DEBUG 2738 if (uhcidebug >= 12) { 2739 uhci_soft_td_t *std; 2740 uhci_soft_qh_t *xqh; 2741 uhci_soft_qh_t *sxqh; 2742 int maxqh = 0; 2743 uhci_physaddr_t link; 2744 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2745 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2746 for (std = sc->sc_vframes[0].htd, link = 0; 2747 (link & UHCI_PTR_QH) == 0; 2748 std = std->link.std) { 2749 link = le32toh(std->td.td_link); 2750 uhci_dump_td(std); 2751 } 2752 sxqh = (uhci_soft_qh_t *)std; 2753 uhci_dump_qh(sxqh); 2754 for (xqh = sxqh; 2755 xqh != NULL; 2756 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2757 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2758 uhci_dump_qh(xqh); 2759 } 2760 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2761 uhci_dump_qh(sqh); 2762 uhci_dump_tds(sqh->elink); 2763 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2764 } 2765 #endif 2766 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2767 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2768 uhci_timeout, xfer); 2769 } 2770 xfer->ux_status = USBD_IN_PROGRESS; 2771 mutex_exit(&sc->sc_lock); 2772 2773 if (sc->sc_bus.ub_usepolling) 2774 uhci_waitintr(sc, xfer); 2775 2776 return USBD_IN_PROGRESS; 2777 } 2778 2779 int 2780 uhci_device_intr_init(struct usbd_xfer *xfer) 2781 { 2782 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2783 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2784 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2785 int endpt = ed->bEndpointAddress; 2786 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2787 int len = xfer->ux_bufsize; 2788 int err; 2789 2790 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2791 2792 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2793 xfer->ux_flags, 0); 2794 2795 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2796 KASSERT(len != 0); 2797 2798 ux->ux_type = UX_INTR; 2799 ux->ux_nstd = 0; 2800 err = uhci_alloc_std_chain(sc, xfer, len, isread, 2801 &ux->ux_stdstart, &ux->ux_stdend); 2802 2803 return err; 2804 } 2805 2806 Static void 2807 uhci_device_intr_fini(struct usbd_xfer *xfer) 2808 { 2809 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2810 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2811 2812 KASSERT(ux->ux_type == UX_INTR); 2813 2814 uhci_free_stds(sc, ux); 2815 if (ux->ux_nstd) 2816 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2817 } 2818 2819 usbd_status 2820 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2821 { 2822 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2823 usbd_status err; 2824 2825 /* Insert last in queue. */ 2826 mutex_enter(&sc->sc_lock); 2827 err = usb_insert_transfer(xfer); 2828 mutex_exit(&sc->sc_lock); 2829 if (err) 2830 return err; 2831 2832 /* 2833 * Pipe isn't running (otherwise err would be USBD_INPROG), 2834 * so start it first. 2835 */ 2836 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2837 } 2838 2839 usbd_status 2840 uhci_device_intr_start(struct usbd_xfer *xfer) 2841 { 2842 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2843 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2844 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2845 uhci_soft_td_t *data, *dataend; 2846 uhci_soft_qh_t *sqh; 2847 int isread, endpt; 2848 int i; 2849 2850 if (sc->sc_dying) 2851 return USBD_IOERROR; 2852 2853 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2854 2855 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2856 xfer->ux_flags, 0); 2857 2858 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2859 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2860 2861 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2862 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2863 2864 data = ux->ux_stdstart; 2865 2866 KASSERT(ux->ux_isdone); 2867 #ifdef DIAGNOSTIC 2868 ux->ux_isdone = false; 2869 #endif 2870 2871 /* Take lock to protect nexttoggle */ 2872 mutex_enter(&sc->sc_lock); 2873 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2874 &upipe->nexttoggle, &dataend); 2875 2876 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2877 usb_syncmem(&dataend->dma, 2878 dataend->offs + offsetof(uhci_td_t, td_status), 2879 sizeof(dataend->td.td_status), 2880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2881 ux->ux_stdend = dataend; 2882 2883 #ifdef UHCI_DEBUG 2884 if (uhcidebug >= 10) { 2885 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2886 uhci_dump_tds(data); 2887 uhci_dump_qh(upipe->intr.qhs[0]); 2888 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2889 } 2890 #endif 2891 2892 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2893 for (i = 0; i < upipe->intr.npoll; i++) { 2894 sqh = upipe->intr.qhs[i]; 2895 sqh->elink = data; 2896 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2897 usb_syncmem(&sqh->dma, 2898 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2899 sizeof(sqh->qh.qh_elink), 2900 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2901 } 2902 uhci_add_intr_list(sc, ux); 2903 xfer->ux_status = USBD_IN_PROGRESS; 2904 mutex_exit(&sc->sc_lock); 2905 2906 #ifdef UHCI_DEBUG 2907 if (uhcidebug >= 10) { 2908 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2909 uhci_dump_tds(data); 2910 uhci_dump_qh(upipe->intr.qhs[0]); 2911 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2912 } 2913 #endif 2914 2915 return USBD_IN_PROGRESS; 2916 } 2917 2918 /* Abort a device control request. */ 2919 void 2920 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2921 { 2922 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2923 2924 KASSERT(mutex_owned(&sc->sc_lock)); 2925 2926 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2927 uhci_abort_xfer(xfer, USBD_CANCELLED); 2928 } 2929 2930 /* Close a device control pipe. */ 2931 void 2932 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2933 { 2934 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2935 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2936 2937 uhci_free_sqh(sc, upipe->ctrl.sqh); 2938 uhci_free_std_locked(sc, upipe->ctrl.setup); 2939 uhci_free_std_locked(sc, upipe->ctrl.stat); 2940 2941 } 2942 2943 /* Abort a device interrupt request. */ 2944 void 2945 uhci_device_intr_abort(struct usbd_xfer *xfer) 2946 { 2947 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2948 2949 KASSERT(mutex_owned(&sc->sc_lock)); 2950 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2951 2952 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2953 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2954 2955 uhci_abort_xfer(xfer, USBD_CANCELLED); 2956 } 2957 2958 /* Close a device interrupt pipe. */ 2959 void 2960 uhci_device_intr_close(struct usbd_pipe *pipe) 2961 { 2962 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2963 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2964 int i, npoll; 2965 2966 KASSERT(mutex_owned(&sc->sc_lock)); 2967 2968 /* Unlink descriptors from controller data structures. */ 2969 npoll = upipe->intr.npoll; 2970 for (i = 0; i < npoll; i++) 2971 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2972 2973 /* 2974 * We now have to wait for any activity on the physical 2975 * descriptors to stop. 2976 */ 2977 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2978 2979 for (i = 0; i < npoll; i++) 2980 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2981 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2982 } 2983 2984 int 2985 uhci_device_isoc_init(struct usbd_xfer *xfer) 2986 { 2987 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2988 2989 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2990 KASSERT(xfer->ux_nframes != 0); 2991 KASSERT(ux->ux_isdone); 2992 2993 ux->ux_type = UX_ISOC; 2994 return 0; 2995 } 2996 2997 Static void 2998 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2999 { 3000 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3001 3002 KASSERT(ux->ux_type == UX_ISOC); 3003 } 3004 3005 usbd_status 3006 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 3007 { 3008 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3009 usbd_status err; 3010 3011 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3012 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3013 3014 /* Put it on our queue, */ 3015 mutex_enter(&sc->sc_lock); 3016 err = usb_insert_transfer(xfer); 3017 mutex_exit(&sc->sc_lock); 3018 3019 /* bail out on error, */ 3020 if (err && err != USBD_IN_PROGRESS) 3021 return err; 3022 3023 /* XXX should check inuse here */ 3024 3025 /* insert into schedule, */ 3026 uhci_device_isoc_enter(xfer); 3027 3028 /* and start if the pipe wasn't running */ 3029 if (!err) 3030 uhci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3031 3032 return err; 3033 } 3034 3035 void 3036 uhci_device_isoc_enter(struct usbd_xfer *xfer) 3037 { 3038 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3039 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3040 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3041 struct isoc *isoc = &upipe->isoc; 3042 uhci_soft_td_t *std; 3043 uint32_t buf, len, status, offs; 3044 int i, next, nframes; 3045 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3046 3047 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3048 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 3049 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3050 3051 if (sc->sc_dying) 3052 return; 3053 3054 if (xfer->ux_status == USBD_IN_PROGRESS) { 3055 /* This request has already been entered into the frame list */ 3056 printf("%s: xfer=%p in frame list\n", __func__, xfer); 3057 /* XXX */ 3058 } 3059 3060 #ifdef DIAGNOSTIC 3061 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 3062 printf("%s: overflow!\n", __func__); 3063 #endif 3064 3065 mutex_enter(&sc->sc_lock); 3066 next = isoc->next; 3067 if (next == -1) { 3068 /* Not in use yet, schedule it a few frames ahead. */ 3069 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 3070 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 3071 } 3072 3073 xfer->ux_status = USBD_IN_PROGRESS; 3074 ux->ux_curframe = next; 3075 3076 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3077 offs = 0; 3078 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 3079 UHCI_TD_ACTIVE | 3080 UHCI_TD_IOS); 3081 nframes = xfer->ux_nframes; 3082 for (i = 0; i < nframes; i++) { 3083 std = isoc->stds[next]; 3084 if (++next >= UHCI_VFRAMELIST_COUNT) 3085 next = 0; 3086 len = xfer->ux_frlengths[i]; 3087 std->td.td_buffer = htole32(buf); 3088 usb_syncmem(&xfer->ux_dmabuf, offs, len, 3089 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3090 if (i == nframes - 1) 3091 status |= UHCI_TD_IOC; 3092 std->td.td_status = htole32(status); 3093 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 3094 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 3095 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3096 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3097 #ifdef UHCI_DEBUG 3098 if (uhcidebug >= 5) { 3099 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3100 DPRINTF("TD %d", i, 0, 0, 0); 3101 uhci_dump_td(std); 3102 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3103 } 3104 #endif 3105 buf += len; 3106 offs += len; 3107 } 3108 isoc->next = next; 3109 isoc->inuse += xfer->ux_nframes; 3110 3111 mutex_exit(&sc->sc_lock); 3112 } 3113 3114 usbd_status 3115 uhci_device_isoc_start(struct usbd_xfer *xfer) 3116 { 3117 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3118 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3119 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3120 uhci_soft_td_t *end; 3121 int i; 3122 3123 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3124 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3125 3126 mutex_enter(&sc->sc_lock); 3127 3128 if (sc->sc_dying) { 3129 mutex_exit(&sc->sc_lock); 3130 return USBD_IOERROR; 3131 } 3132 3133 #ifdef DIAGNOSTIC 3134 if (xfer->ux_status != USBD_IN_PROGRESS) 3135 printf("%s: not in progress %p\n", __func__, xfer); 3136 #endif 3137 3138 /* Find the last TD */ 3139 i = UHCI_XFER2UXFER(xfer)->ux_curframe + xfer->ux_nframes; 3140 if (i >= UHCI_VFRAMELIST_COUNT) 3141 i -= UHCI_VFRAMELIST_COUNT; 3142 end = upipe->isoc.stds[i]; 3143 3144 KASSERT(end != NULL); 3145 3146 /* Set up interrupt info. */ 3147 ux->ux_stdstart = end; 3148 ux->ux_stdend = end; 3149 3150 KASSERT(ux->ux_isdone); 3151 #ifdef DIAGNOSTIC 3152 ux->ux_isdone = false; 3153 #endif 3154 uhci_add_intr_list(sc, ux); 3155 3156 mutex_exit(&sc->sc_lock); 3157 3158 return USBD_IN_PROGRESS; 3159 } 3160 3161 void 3162 uhci_device_isoc_abort(struct usbd_xfer *xfer) 3163 { 3164 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3165 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3166 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3167 uhci_soft_td_t **stds = upipe->isoc.stds; 3168 uhci_soft_td_t *std; 3169 int i, n, nframes, maxlen, len; 3170 3171 KASSERT(mutex_owned(&sc->sc_lock)); 3172 3173 /* Transfer is already done. */ 3174 if (xfer->ux_status != USBD_NOT_STARTED && 3175 xfer->ux_status != USBD_IN_PROGRESS) { 3176 return; 3177 } 3178 3179 /* Give xfer the requested abort code. */ 3180 xfer->ux_status = USBD_CANCELLED; 3181 3182 /* make hardware ignore it, */ 3183 nframes = xfer->ux_nframes; 3184 n = ux->ux_curframe; 3185 maxlen = 0; 3186 for (i = 0; i < nframes; i++) { 3187 std = stds[n]; 3188 usb_syncmem(&std->dma, 3189 std->offs + offsetof(uhci_td_t, td_status), 3190 sizeof(std->td.td_status), 3191 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3192 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3193 usb_syncmem(&std->dma, 3194 std->offs + offsetof(uhci_td_t, td_status), 3195 sizeof(std->td.td_status), 3196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3197 usb_syncmem(&std->dma, 3198 std->offs + offsetof(uhci_td_t, td_token), 3199 sizeof(std->td.td_token), 3200 BUS_DMASYNC_POSTWRITE); 3201 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3202 if (len > maxlen) 3203 maxlen = len; 3204 if (++n >= UHCI_VFRAMELIST_COUNT) 3205 n = 0; 3206 } 3207 3208 /* and wait until we are sure the hardware has finished. */ 3209 delay(maxlen); 3210 3211 #ifdef DIAGNOSTIC 3212 ux->ux_isdone = true; 3213 #endif 3214 /* Remove from interrupt list. */ 3215 uhci_del_intr_list(sc, ux); 3216 3217 /* Run callback. */ 3218 usb_transfer_complete(xfer); 3219 3220 KASSERT(mutex_owned(&sc->sc_lock)); 3221 } 3222 3223 void 3224 uhci_device_isoc_close(struct usbd_pipe *pipe) 3225 { 3226 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3227 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3228 uhci_soft_td_t *std, *vstd; 3229 struct isoc *isoc; 3230 int i; 3231 3232 KASSERT(mutex_owned(&sc->sc_lock)); 3233 3234 /* 3235 * Make sure all TDs are marked as inactive. 3236 * Wait for completion. 3237 * Unschedule. 3238 * Deallocate. 3239 */ 3240 isoc = &upipe->isoc; 3241 3242 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3243 std = isoc->stds[i]; 3244 usb_syncmem(&std->dma, 3245 std->offs + offsetof(uhci_td_t, td_status), 3246 sizeof(std->td.td_status), 3247 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3248 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3249 usb_syncmem(&std->dma, 3250 std->offs + offsetof(uhci_td_t, td_status), 3251 sizeof(std->td.td_status), 3252 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3253 } 3254 /* wait for completion */ 3255 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3256 3257 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3258 std = isoc->stds[i]; 3259 for (vstd = sc->sc_vframes[i].htd; 3260 vstd != NULL && vstd->link.std != std; 3261 vstd = vstd->link.std) 3262 ; 3263 if (vstd == NULL) { 3264 /*panic*/ 3265 printf("%s: %p not found\n", __func__, std); 3266 mutex_exit(&sc->sc_lock); 3267 return; 3268 } 3269 vstd->link = std->link; 3270 usb_syncmem(&std->dma, 3271 std->offs + offsetof(uhci_td_t, td_link), 3272 sizeof(std->td.td_link), 3273 BUS_DMASYNC_POSTWRITE); 3274 vstd->td.td_link = std->td.td_link; 3275 usb_syncmem(&vstd->dma, 3276 vstd->offs + offsetof(uhci_td_t, td_link), 3277 sizeof(vstd->td.td_link), 3278 BUS_DMASYNC_PREWRITE); 3279 uhci_free_std_locked(sc, std); 3280 } 3281 3282 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3283 } 3284 3285 usbd_status 3286 uhci_setup_isoc(struct usbd_pipe *pipe) 3287 { 3288 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3289 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3290 int addr = upipe->pipe.up_dev->ud_addr; 3291 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3292 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3293 uhci_soft_td_t *std, *vstd; 3294 uint32_t token; 3295 struct isoc *isoc; 3296 int i; 3297 3298 isoc = &upipe->isoc; 3299 3300 isoc->stds = kmem_alloc( 3301 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3302 if (isoc->stds == NULL) 3303 return USBD_NOMEM; 3304 3305 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3306 UHCI_TD_OUT(0, endpt, addr, 0); 3307 3308 /* Allocate the TDs and mark as inactive; */ 3309 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3310 std = uhci_alloc_std(sc); 3311 if (std == 0) 3312 goto bad; 3313 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3314 std->td.td_token = htole32(token); 3315 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3316 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3317 isoc->stds[i] = std; 3318 } 3319 3320 mutex_enter(&sc->sc_lock); 3321 3322 /* Insert TDs into schedule. */ 3323 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3324 std = isoc->stds[i]; 3325 vstd = sc->sc_vframes[i].htd; 3326 usb_syncmem(&vstd->dma, 3327 vstd->offs + offsetof(uhci_td_t, td_link), 3328 sizeof(vstd->td.td_link), 3329 BUS_DMASYNC_POSTWRITE); 3330 std->link = vstd->link; 3331 std->td.td_link = vstd->td.td_link; 3332 usb_syncmem(&std->dma, 3333 std->offs + offsetof(uhci_td_t, td_link), 3334 sizeof(std->td.td_link), 3335 BUS_DMASYNC_PREWRITE); 3336 vstd->link.std = std; 3337 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3338 usb_syncmem(&vstd->dma, 3339 vstd->offs + offsetof(uhci_td_t, td_link), 3340 sizeof(vstd->td.td_link), 3341 BUS_DMASYNC_PREWRITE); 3342 } 3343 mutex_exit(&sc->sc_lock); 3344 3345 isoc->next = -1; 3346 isoc->inuse = 0; 3347 3348 return USBD_NORMAL_COMPLETION; 3349 3350 bad: 3351 while (--i >= 0) 3352 uhci_free_std(sc, isoc->stds[i]); 3353 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3354 return USBD_NOMEM; 3355 } 3356 3357 void 3358 uhci_device_isoc_done(struct usbd_xfer *xfer) 3359 { 3360 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3361 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3362 int i, offs; 3363 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3364 3365 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3366 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3367 xfer->ux_actlen, xfer->ux_state, 0, 0); 3368 3369 #ifdef DIAGNOSTIC 3370 if (ux->ux_stdend == NULL) { 3371 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3372 #ifdef UHCI_DEBUG 3373 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3374 uhci_dump_ii(ux); 3375 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3376 #endif 3377 return; 3378 } 3379 #endif 3380 3381 /* Turn off the interrupt since it is active even if the TD is not. */ 3382 usb_syncmem(&ux->ux_stdend->dma, 3383 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3384 sizeof(ux->ux_stdend->td.td_status), 3385 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3386 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3387 usb_syncmem(&ux->ux_stdend->dma, 3388 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3389 sizeof(ux->ux_stdend->td.td_status), 3390 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3391 3392 offs = 0; 3393 for (i = 0; i < xfer->ux_nframes; i++) { 3394 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3395 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3396 offs += xfer->ux_frlengths[i]; 3397 } 3398 } 3399 3400 void 3401 uhci_device_intr_done(struct usbd_xfer *xfer) 3402 { 3403 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3404 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3405 uhci_soft_qh_t *sqh; 3406 int i, npoll; 3407 3408 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3409 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3410 3411 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3412 3413 npoll = upipe->intr.npoll; 3414 for (i = 0; i < npoll; i++) { 3415 sqh = upipe->intr.qhs[i]; 3416 sqh->elink = NULL; 3417 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3418 usb_syncmem(&sqh->dma, 3419 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3420 sizeof(sqh->qh.qh_elink), 3421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3422 } 3423 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3424 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3425 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3426 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3427 } 3428 3429 /* Deallocate request data structures */ 3430 void 3431 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3432 { 3433 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3434 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3435 int len = UGETW(xfer->ux_request.wLength); 3436 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3437 3438 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3439 3440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3441 3442 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3443 3444 /* XXXNH move to uhci_idone??? */ 3445 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3446 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3447 else 3448 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3449 3450 if (len) { 3451 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3452 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3453 } 3454 usb_syncmem(&upipe->ctrl.reqdma, 0, 3455 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3456 3457 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3458 } 3459 3460 /* Deallocate request data structures */ 3461 void 3462 uhci_device_bulk_done(struct usbd_xfer *xfer) 3463 { 3464 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3465 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3466 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3467 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3468 int endpt = ed->bEndpointAddress; 3469 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3470 3471 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3472 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3473 upipe); 3474 3475 KASSERT(mutex_owned(&sc->sc_lock)); 3476 3477 uhci_remove_bulk(sc, upipe->bulk.sqh); 3478 3479 if (xfer->ux_length) { 3480 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3481 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3482 } 3483 3484 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3485 } 3486 3487 /* Add interrupt QH, called with vflock. */ 3488 void 3489 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3490 { 3491 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3492 uhci_soft_qh_t *eqh; 3493 3494 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3495 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3496 3497 eqh = vf->eqh; 3498 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3499 sizeof(eqh->qh.qh_hlink), 3500 BUS_DMASYNC_POSTWRITE); 3501 sqh->hlink = eqh->hlink; 3502 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3503 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3504 sizeof(sqh->qh.qh_hlink), 3505 BUS_DMASYNC_PREWRITE); 3506 eqh->hlink = sqh; 3507 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3508 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3509 sizeof(eqh->qh.qh_hlink), 3510 BUS_DMASYNC_PREWRITE); 3511 vf->eqh = sqh; 3512 vf->bandwidth++; 3513 } 3514 3515 /* Remove interrupt QH. */ 3516 void 3517 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3518 { 3519 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3520 uhci_soft_qh_t *pqh; 3521 3522 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3523 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3524 3525 /* See comment in uhci_remove_ctrl() */ 3526 3527 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3528 sizeof(sqh->qh.qh_elink), 3529 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3530 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3531 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3532 usb_syncmem(&sqh->dma, 3533 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3534 sizeof(sqh->qh.qh_elink), 3535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3536 delay(UHCI_QH_REMOVE_DELAY); 3537 } 3538 3539 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3540 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3541 sizeof(sqh->qh.qh_hlink), 3542 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3543 pqh->hlink = sqh->hlink; 3544 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3545 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3546 sizeof(pqh->qh.qh_hlink), 3547 BUS_DMASYNC_PREWRITE); 3548 delay(UHCI_QH_REMOVE_DELAY); 3549 if (vf->eqh == sqh) 3550 vf->eqh = pqh; 3551 vf->bandwidth--; 3552 } 3553 3554 usbd_status 3555 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3556 { 3557 uhci_soft_qh_t *sqh; 3558 int i, npoll; 3559 u_int bestbw, bw, bestoffs, offs; 3560 3561 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3562 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3563 if (ival == 0) { 3564 printf("%s: 0 interval\n", __func__); 3565 return USBD_INVAL; 3566 } 3567 3568 if (ival > UHCI_VFRAMELIST_COUNT) 3569 ival = UHCI_VFRAMELIST_COUNT; 3570 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3571 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3572 3573 upipe->intr.npoll = npoll; 3574 upipe->intr.qhs = 3575 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3576 if (upipe->intr.qhs == NULL) 3577 return USBD_NOMEM; 3578 3579 /* 3580 * Figure out which offset in the schedule that has most 3581 * bandwidth left over. 3582 */ 3583 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3584 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3585 for (bw = i = 0; i < npoll; i++) 3586 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3587 if (bw < bestbw) { 3588 bestbw = bw; 3589 bestoffs = offs; 3590 } 3591 } 3592 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3593 for (i = 0; i < npoll; i++) { 3594 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3595 sqh->elink = NULL; 3596 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3597 usb_syncmem(&sqh->dma, 3598 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3599 sizeof(sqh->qh.qh_elink), 3600 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3601 sqh->pos = MOD(i * ival + bestoffs); 3602 } 3603 #undef MOD 3604 3605 mutex_enter(&sc->sc_lock); 3606 /* Enter QHs into the controller data structures. */ 3607 for (i = 0; i < npoll; i++) 3608 uhci_add_intr(sc, upipe->intr.qhs[i]); 3609 mutex_exit(&sc->sc_lock); 3610 3611 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3612 3613 return USBD_NORMAL_COMPLETION; 3614 } 3615 3616 /* Open a new pipe. */ 3617 usbd_status 3618 uhci_open(struct usbd_pipe *pipe) 3619 { 3620 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3621 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3622 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3623 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3624 usbd_status err = USBD_NOMEM; 3625 int ival; 3626 3627 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3628 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3629 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3630 3631 if (sc->sc_dying) 3632 return USBD_IOERROR; 3633 3634 upipe->aborting = 0; 3635 /* toggle state needed for bulk endpoints */ 3636 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3637 3638 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3639 switch (ed->bEndpointAddress) { 3640 case USB_CONTROL_ENDPOINT: 3641 pipe->up_methods = &roothub_ctrl_methods; 3642 break; 3643 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3644 pipe->up_methods = &uhci_root_intr_methods; 3645 break; 3646 default: 3647 return USBD_INVAL; 3648 } 3649 } else { 3650 switch (ed->bmAttributes & UE_XFERTYPE) { 3651 case UE_CONTROL: 3652 pipe->up_methods = &uhci_device_ctrl_methods; 3653 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3654 if (upipe->ctrl.sqh == NULL) 3655 goto bad; 3656 upipe->ctrl.setup = uhci_alloc_std(sc); 3657 if (upipe->ctrl.setup == NULL) { 3658 uhci_free_sqh(sc, upipe->ctrl.sqh); 3659 goto bad; 3660 } 3661 upipe->ctrl.stat = uhci_alloc_std(sc); 3662 if (upipe->ctrl.stat == NULL) { 3663 uhci_free_sqh(sc, upipe->ctrl.sqh); 3664 uhci_free_std(sc, upipe->ctrl.setup); 3665 goto bad; 3666 } 3667 err = usb_allocmem(&sc->sc_bus, 3668 sizeof(usb_device_request_t), 3669 0, &upipe->ctrl.reqdma); 3670 if (err) { 3671 uhci_free_sqh(sc, upipe->ctrl.sqh); 3672 uhci_free_std(sc, upipe->ctrl.setup); 3673 uhci_free_std(sc, upipe->ctrl.stat); 3674 goto bad; 3675 } 3676 break; 3677 case UE_INTERRUPT: 3678 pipe->up_methods = &uhci_device_intr_methods; 3679 ival = pipe->up_interval; 3680 if (ival == USBD_DEFAULT_INTERVAL) 3681 ival = ed->bInterval; 3682 return uhci_device_setintr(sc, upipe, ival); 3683 case UE_ISOCHRONOUS: 3684 pipe->up_methods = &uhci_device_isoc_methods; 3685 return uhci_setup_isoc(pipe); 3686 case UE_BULK: 3687 pipe->up_methods = &uhci_device_bulk_methods; 3688 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3689 if (upipe->bulk.sqh == NULL) 3690 goto bad; 3691 break; 3692 } 3693 } 3694 return USBD_NORMAL_COMPLETION; 3695 3696 bad: 3697 return USBD_NOMEM; 3698 } 3699 3700 /* 3701 * Data structures and routines to emulate the root hub. 3702 */ 3703 /* 3704 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3705 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3706 * should not be used by the USB subsystem. As we cannot issue a 3707 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3708 * will be enabled as part of the reset. 3709 * 3710 * On the VT83C572, the port cannot be successfully enabled until the 3711 * outstanding "port enable change" and "connection status change" 3712 * events have been reset. 3713 */ 3714 Static usbd_status 3715 uhci_portreset(uhci_softc_t *sc, int index) 3716 { 3717 int lim, port, x; 3718 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3719 3720 if (index == 1) 3721 port = UHCI_PORTSC1; 3722 else if (index == 2) 3723 port = UHCI_PORTSC2; 3724 else 3725 return USBD_IOERROR; 3726 3727 x = URWMASK(UREAD2(sc, port)); 3728 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3729 3730 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3731 3732 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3733 UREAD2(sc, port), 0, 0); 3734 3735 x = URWMASK(UREAD2(sc, port)); 3736 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3737 3738 delay(100); 3739 3740 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3741 UREAD2(sc, port), 0, 0); 3742 3743 x = URWMASK(UREAD2(sc, port)); 3744 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3745 3746 for (lim = 10; --lim > 0;) { 3747 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3748 3749 x = UREAD2(sc, port); 3750 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3751 lim, x, 0); 3752 3753 if (!(x & UHCI_PORTSC_CCS)) { 3754 /* 3755 * No device is connected (or was disconnected 3756 * during reset). Consider the port reset. 3757 * The delay must be long enough to ensure on 3758 * the initial iteration that the device 3759 * connection will have been registered. 50ms 3760 * appears to be sufficient, but 20ms is not. 3761 */ 3762 DPRINTFN(3, "uhci port %d loop %u, device detached", 3763 index, lim, 0, 0); 3764 break; 3765 } 3766 3767 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3768 /* 3769 * Port enabled changed and/or connection 3770 * status changed were set. Reset either or 3771 * both raised flags (by writing a 1 to that 3772 * bit), and wait again for state to settle. 3773 */ 3774 UWRITE2(sc, port, URWMASK(x) | 3775 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3776 continue; 3777 } 3778 3779 if (x & UHCI_PORTSC_PE) 3780 /* Port is enabled */ 3781 break; 3782 3783 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3784 } 3785 3786 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3787 UREAD2(sc, port), 0, 0); 3788 3789 if (lim <= 0) { 3790 DPRINTF("uhci port %d reset timed out", index, 3791 0, 0, 0); 3792 return USBD_TIMEOUT; 3793 } 3794 3795 sc->sc_isreset = 1; 3796 return USBD_NORMAL_COMPLETION; 3797 } 3798 3799 Static int 3800 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3801 void *buf, int buflen) 3802 { 3803 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3804 int port, x; 3805 int status, change, totlen = 0; 3806 uint16_t len, value, index; 3807 usb_port_status_t ps; 3808 usbd_status err; 3809 3810 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3811 3812 if (sc->sc_dying) 3813 return -1; 3814 3815 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3816 req->bRequest, 0, 0); 3817 3818 len = UGETW(req->wLength); 3819 value = UGETW(req->wValue); 3820 index = UGETW(req->wIndex); 3821 3822 #define C(x,y) ((x) | ((y) << 8)) 3823 switch (C(req->bRequest, req->bmRequestType)) { 3824 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3825 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3826 if (len == 0) 3827 break; 3828 switch (value) { 3829 case C(0, UDESC_DEVICE): { 3830 usb_device_descriptor_t devd; 3831 3832 totlen = min(buflen, sizeof(devd)); 3833 memcpy(&devd, buf, totlen); 3834 USETW(devd.idVendor, sc->sc_id_vendor); 3835 memcpy(buf, &devd, totlen); 3836 break; 3837 } 3838 case C(1, UDESC_STRING): 3839 #define sd ((usb_string_descriptor_t *)buf) 3840 /* Vendor */ 3841 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3842 break; 3843 case C(2, UDESC_STRING): 3844 /* Product */ 3845 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3846 break; 3847 #undef sd 3848 default: 3849 /* default from usbroothub */ 3850 return buflen; 3851 } 3852 break; 3853 3854 /* Hub requests */ 3855 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3856 break; 3857 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3858 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3859 value, 0, 0); 3860 if (index == 1) 3861 port = UHCI_PORTSC1; 3862 else if (index == 2) 3863 port = UHCI_PORTSC2; 3864 else { 3865 return -1; 3866 } 3867 switch(value) { 3868 case UHF_PORT_ENABLE: 3869 x = URWMASK(UREAD2(sc, port)); 3870 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3871 break; 3872 case UHF_PORT_SUSPEND: 3873 x = URWMASK(UREAD2(sc, port)); 3874 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3875 break; 3876 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3877 /* see USB2 spec ch. 7.1.7.7 */ 3878 usb_delay_ms(&sc->sc_bus, 20); 3879 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3880 /* 10ms resume delay must be provided by caller */ 3881 break; 3882 case UHF_PORT_RESET: 3883 x = URWMASK(UREAD2(sc, port)); 3884 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3885 break; 3886 case UHF_C_PORT_CONNECTION: 3887 x = URWMASK(UREAD2(sc, port)); 3888 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3889 break; 3890 case UHF_C_PORT_ENABLE: 3891 x = URWMASK(UREAD2(sc, port)); 3892 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3893 break; 3894 case UHF_C_PORT_OVER_CURRENT: 3895 x = URWMASK(UREAD2(sc, port)); 3896 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3897 break; 3898 case UHF_C_PORT_RESET: 3899 sc->sc_isreset = 0; 3900 break; 3901 case UHF_PORT_CONNECTION: 3902 case UHF_PORT_OVER_CURRENT: 3903 case UHF_PORT_POWER: 3904 case UHF_PORT_LOW_SPEED: 3905 case UHF_C_PORT_SUSPEND: 3906 default: 3907 return -1; 3908 } 3909 break; 3910 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3911 if (index == 1) 3912 port = UHCI_PORTSC1; 3913 else if (index == 2) 3914 port = UHCI_PORTSC2; 3915 else { 3916 return -1; 3917 } 3918 if (len > 0) { 3919 *(uint8_t *)buf = 3920 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 3921 UHCI_PORTSC_LS_SHIFT; 3922 totlen = 1; 3923 } 3924 break; 3925 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3926 if (len == 0) 3927 break; 3928 if ((value & 0xff) != 0) { 3929 return -1; 3930 } 3931 usb_hub_descriptor_t hubd; 3932 3933 totlen = min(buflen, sizeof(hubd)); 3934 memcpy(&hubd, buf, totlen); 3935 hubd.bNbrPorts = 2; 3936 memcpy(buf, &hubd, totlen); 3937 break; 3938 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3939 if (len != 4) { 3940 return -1; 3941 } 3942 memset(buf, 0, len); 3943 totlen = len; 3944 break; 3945 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3946 if (index == 1) 3947 port = UHCI_PORTSC1; 3948 else if (index == 2) 3949 port = UHCI_PORTSC2; 3950 else { 3951 return -1; 3952 } 3953 if (len != 4) { 3954 return -1; 3955 } 3956 x = UREAD2(sc, port); 3957 status = change = 0; 3958 if (x & UHCI_PORTSC_CCS) 3959 status |= UPS_CURRENT_CONNECT_STATUS; 3960 if (x & UHCI_PORTSC_CSC) 3961 change |= UPS_C_CONNECT_STATUS; 3962 if (x & UHCI_PORTSC_PE) 3963 status |= UPS_PORT_ENABLED; 3964 if (x & UHCI_PORTSC_POEDC) 3965 change |= UPS_C_PORT_ENABLED; 3966 if (x & UHCI_PORTSC_OCI) 3967 status |= UPS_OVERCURRENT_INDICATOR; 3968 if (x & UHCI_PORTSC_OCIC) 3969 change |= UPS_C_OVERCURRENT_INDICATOR; 3970 if (x & UHCI_PORTSC_SUSP) 3971 status |= UPS_SUSPEND; 3972 if (x & UHCI_PORTSC_LSDA) 3973 status |= UPS_LOW_SPEED; 3974 status |= UPS_PORT_POWER; 3975 if (sc->sc_isreset) 3976 change |= UPS_C_PORT_RESET; 3977 USETW(ps.wPortStatus, status); 3978 USETW(ps.wPortChange, change); 3979 totlen = min(len, sizeof(ps)); 3980 memcpy(buf, &ps, totlen); 3981 break; 3982 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3983 return -1; 3984 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3985 break; 3986 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3987 if (index == 1) 3988 port = UHCI_PORTSC1; 3989 else if (index == 2) 3990 port = UHCI_PORTSC2; 3991 else { 3992 return -1; 3993 } 3994 switch(value) { 3995 case UHF_PORT_ENABLE: 3996 x = URWMASK(UREAD2(sc, port)); 3997 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3998 break; 3999 case UHF_PORT_SUSPEND: 4000 x = URWMASK(UREAD2(sc, port)); 4001 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 4002 break; 4003 case UHF_PORT_RESET: 4004 err = uhci_portreset(sc, index); 4005 if (err != USBD_NORMAL_COMPLETION) 4006 return -1; 4007 return 0; 4008 case UHF_PORT_POWER: 4009 /* Pretend we turned on power */ 4010 return 0; 4011 case UHF_C_PORT_CONNECTION: 4012 case UHF_C_PORT_ENABLE: 4013 case UHF_C_PORT_OVER_CURRENT: 4014 case UHF_PORT_CONNECTION: 4015 case UHF_PORT_OVER_CURRENT: 4016 case UHF_PORT_LOW_SPEED: 4017 case UHF_C_PORT_SUSPEND: 4018 case UHF_C_PORT_RESET: 4019 default: 4020 return -1; 4021 } 4022 break; 4023 default: 4024 /* default from usbroothub */ 4025 DPRINTF("returning %d (usbroothub default)", 4026 buflen, 0, 0, 0); 4027 return buflen; 4028 } 4029 4030 DPRINTF("returning %d", totlen, 0, 0, 0); 4031 4032 return totlen; 4033 } 4034 4035 /* Abort a root interrupt request. */ 4036 void 4037 uhci_root_intr_abort(struct usbd_xfer *xfer) 4038 { 4039 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 4040 4041 KASSERT(mutex_owned(&sc->sc_lock)); 4042 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4043 4044 callout_stop(&sc->sc_poll_handle); 4045 sc->sc_intr_xfer = NULL; 4046 4047 xfer->ux_status = USBD_CANCELLED; 4048 #ifdef DIAGNOSTIC 4049 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 4050 #endif 4051 usb_transfer_complete(xfer); 4052 } 4053 4054 usbd_status 4055 uhci_root_intr_transfer(struct usbd_xfer *xfer) 4056 { 4057 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 4058 usbd_status err; 4059 4060 /* Insert last in queue. */ 4061 mutex_enter(&sc->sc_lock); 4062 err = usb_insert_transfer(xfer); 4063 mutex_exit(&sc->sc_lock); 4064 if (err) 4065 return err; 4066 4067 /* 4068 * Pipe isn't running (otherwise err would be USBD_INPROG), 4069 * start first 4070 */ 4071 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4072 } 4073 4074 /* Start a transfer on the root interrupt pipe */ 4075 usbd_status 4076 uhci_root_intr_start(struct usbd_xfer *xfer) 4077 { 4078 struct usbd_pipe *pipe = xfer->ux_pipe; 4079 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 4080 unsigned int ival; 4081 4082 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 4083 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4084 xfer->ux_flags, 0); 4085 4086 if (sc->sc_dying) 4087 return USBD_IOERROR; 4088 4089 /* XXX temporary variable needed to avoid gcc3 warning */ 4090 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 4091 sc->sc_ival = mstohz(ival); 4092 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 4093 sc->sc_intr_xfer = xfer; 4094 return USBD_IN_PROGRESS; 4095 } 4096 4097 /* Close the root interrupt pipe. */ 4098 void 4099 uhci_root_intr_close(struct usbd_pipe *pipe) 4100 { 4101 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 4102 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 4103 4104 KASSERT(mutex_owned(&sc->sc_lock)); 4105 4106 callout_stop(&sc->sc_poll_handle); 4107 sc->sc_intr_xfer = NULL; 4108 } 4109
Indexes created Tue Sep 30 20:09:53 GMT 2025