uhci.c revision 1.264.4.69
1 /* $NetBSD: uhci.c,v 1.264.4.69 2016/03/25 17:44:00 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.69 2016/03/25 17:44:00 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup; 143 uhci_soft_td_t *stat; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 uhci_soft_qh_t **qhs; 149 } intr; 150 /* Bulk pipe */ 151 struct { 152 uhci_soft_qh_t *sqh; 153 } bulk; 154 /* Isochronous pipe */ 155 struct isoc { 156 uhci_soft_td_t **stds; 157 int next, inuse; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 163 164 Static void uhci_globalreset(uhci_softc_t *); 165 Static usbd_status uhci_portreset(uhci_softc_t*, int); 166 Static void uhci_reset(uhci_softc_t *); 167 Static usbd_status uhci_run(uhci_softc_t *, int, int); 168 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 169 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 170 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 180 uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 182 int, int, uhci_soft_td_t **, uhci_soft_td_t **); 183 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 184 185 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, int *, uhci_soft_td_t **); 187 188 Static void uhci_poll_hub(void *); 189 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 190 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 191 ux_completeq_t *); 192 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 193 194 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 195 196 Static void uhci_timeout(void *); 197 Static void uhci_timeout_task(void *); 198 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 199 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 200 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 201 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 202 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 203 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 204 Static void uhci_add_loop(uhci_softc_t *); 205 Static void uhci_rem_loop(uhci_softc_t *); 206 207 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 208 209 Static struct usbd_xfer * 210 uhci_allocx(struct usbd_bus *, unsigned int); 211 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 212 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 213 Static int uhci_roothub_ctrl(struct usbd_bus *, 214 usb_device_request_t *, void *, int); 215 216 Static int uhci_device_ctrl_init(struct usbd_xfer *); 217 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 218 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 220 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 221 Static void uhci_device_ctrl_close(struct usbd_pipe *); 222 Static void uhci_device_ctrl_done(struct usbd_xfer *); 223 224 Static int uhci_device_intr_init(struct usbd_xfer *); 225 Static void uhci_device_intr_fini(struct usbd_xfer *); 226 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 227 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 228 Static void uhci_device_intr_abort(struct usbd_xfer *); 229 Static void uhci_device_intr_close(struct usbd_pipe *); 230 Static void uhci_device_intr_done(struct usbd_xfer *); 231 232 Static int uhci_device_bulk_init(struct usbd_xfer *); 233 Static void uhci_device_bulk_fini(struct usbd_xfer *); 234 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 235 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 236 Static void uhci_device_bulk_abort(struct usbd_xfer *); 237 Static void uhci_device_bulk_close(struct usbd_pipe *); 238 Static void uhci_device_bulk_done(struct usbd_xfer *); 239 240 Static int uhci_device_isoc_init(struct usbd_xfer *); 241 Static void uhci_device_isoc_fini(struct usbd_xfer *); 242 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 243 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 244 Static void uhci_device_isoc_abort(struct usbd_xfer *); 245 Static void uhci_device_isoc_close(struct usbd_pipe *); 246 Static void uhci_device_isoc_done(struct usbd_xfer *); 247 248 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 249 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 250 Static void uhci_root_intr_abort(struct usbd_xfer *); 251 Static void uhci_root_intr_close(struct usbd_pipe *); 252 Static void uhci_root_intr_done(struct usbd_xfer *); 253 254 Static usbd_status uhci_open(struct usbd_pipe *); 255 Static void uhci_poll(struct usbd_bus *); 256 Static void uhci_softintr(void *); 257 258 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 259 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 260 Static usbd_status uhci_device_setintr(uhci_softc_t *, 261 struct uhci_pipe *, int); 262 263 Static void uhci_device_clear_toggle(struct usbd_pipe *); 264 Static void uhci_noop(struct usbd_pipe *); 265 266 static inline uhci_soft_qh_t * 267 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 268 269 #ifdef UHCI_DEBUG 270 Static void uhci_dump_all(uhci_softc_t *); 271 Static void uhci_dumpregs(uhci_softc_t *); 272 Static void uhci_dump_qhs(uhci_soft_qh_t *); 273 Static void uhci_dump_qh(uhci_soft_qh_t *); 274 Static void uhci_dump_tds(uhci_soft_td_t *); 275 Static void uhci_dump_td(uhci_soft_td_t *); 276 Static void uhci_dump_ii(struct uhci_xfer *); 277 void uhci_dump(void); 278 #endif 279 280 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 281 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 282 #define UWRITE1(sc, r, x) \ 283 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 284 } while (/*CONSTCOND*/0) 285 #define UWRITE2(sc, r, x) \ 286 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 287 } while (/*CONSTCOND*/0) 288 #define UWRITE4(sc, r, x) \ 289 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 290 } while (/*CONSTCOND*/0) 291 292 static __inline uint8_t 293 UREAD1(uhci_softc_t *sc, bus_size_t r) 294 { 295 296 UBARR(sc); 297 return bus_space_read_1(sc->iot, sc->ioh, r); 298 } 299 300 static __inline uint16_t 301 UREAD2(uhci_softc_t *sc, bus_size_t r) 302 { 303 304 UBARR(sc); 305 return bus_space_read_2(sc->iot, sc->ioh, r); 306 } 307 308 #ifdef UHCI_DEBUG 309 static __inline uint32_t 310 UREAD4(uhci_softc_t *sc, bus_size_t r) 311 { 312 313 UBARR(sc); 314 return bus_space_read_4(sc->iot, sc->ioh, r); 315 } 316 #endif 317 318 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 319 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 320 321 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 322 323 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 324 325 const struct usbd_bus_methods uhci_bus_methods = { 326 .ubm_open = uhci_open, 327 .ubm_softint = uhci_softintr, 328 .ubm_dopoll = uhci_poll, 329 .ubm_allocx = uhci_allocx, 330 .ubm_freex = uhci_freex, 331 .ubm_getlock = uhci_get_lock, 332 .ubm_rhctrl = uhci_roothub_ctrl, 333 }; 334 335 const struct usbd_pipe_methods uhci_root_intr_methods = { 336 .upm_transfer = uhci_root_intr_transfer, 337 .upm_start = uhci_root_intr_start, 338 .upm_abort = uhci_root_intr_abort, 339 .upm_close = uhci_root_intr_close, 340 .upm_cleartoggle = uhci_noop, 341 .upm_done = uhci_root_intr_done, 342 }; 343 344 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 345 .upm_init = uhci_device_ctrl_init, 346 .upm_fini = uhci_device_ctrl_fini, 347 .upm_transfer = uhci_device_ctrl_transfer, 348 .upm_start = uhci_device_ctrl_start, 349 .upm_abort = uhci_device_ctrl_abort, 350 .upm_close = uhci_device_ctrl_close, 351 .upm_cleartoggle = uhci_noop, 352 .upm_done = uhci_device_ctrl_done, 353 }; 354 355 const struct usbd_pipe_methods uhci_device_intr_methods = { 356 .upm_init = uhci_device_intr_init, 357 .upm_fini = uhci_device_intr_fini, 358 .upm_transfer = uhci_device_intr_transfer, 359 .upm_start = uhci_device_intr_start, 360 .upm_abort = uhci_device_intr_abort, 361 .upm_close = uhci_device_intr_close, 362 .upm_cleartoggle = uhci_device_clear_toggle, 363 .upm_done = uhci_device_intr_done, 364 }; 365 366 const struct usbd_pipe_methods uhci_device_bulk_methods = { 367 .upm_init = uhci_device_bulk_init, 368 .upm_fini = uhci_device_bulk_fini, 369 .upm_transfer = uhci_device_bulk_transfer, 370 .upm_start = uhci_device_bulk_start, 371 .upm_abort = uhci_device_bulk_abort, 372 .upm_close = uhci_device_bulk_close, 373 .upm_cleartoggle = uhci_device_clear_toggle, 374 .upm_done = uhci_device_bulk_done, 375 }; 376 377 const struct usbd_pipe_methods uhci_device_isoc_methods = { 378 .upm_init = uhci_device_isoc_init, 379 .upm_fini = uhci_device_isoc_fini, 380 .upm_transfer = uhci_device_isoc_transfer, 381 .upm_abort = uhci_device_isoc_abort, 382 .upm_close = uhci_device_isoc_close, 383 .upm_cleartoggle = uhci_noop, 384 .upm_done = uhci_device_isoc_done, 385 }; 386 387 static inline void 388 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 389 { 390 391 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 392 } 393 394 static inline void 395 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 396 { 397 398 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 399 } 400 401 static inline uhci_soft_qh_t * 402 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 403 { 404 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 405 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 406 407 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 408 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 409 usb_syncmem(&pqh->dma, 410 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 411 sizeof(pqh->qh.qh_hlink), 412 BUS_DMASYNC_POSTWRITE); 413 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 414 printf("%s: QH not found\n", __func__); 415 return NULL; 416 } 417 #endif 418 } 419 return pqh; 420 } 421 422 void 423 uhci_globalreset(uhci_softc_t *sc) 424 { 425 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 426 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 427 UHCICMD(sc, 0); /* do nothing */ 428 } 429 430 int 431 uhci_init(uhci_softc_t *sc) 432 { 433 usbd_status err; 434 int i, j; 435 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 436 uhci_soft_td_t *std; 437 438 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 439 440 #ifdef UHCI_DEBUG 441 thesc = sc; 442 443 if (uhcidebug >= 2) 444 uhci_dumpregs(sc); 445 #endif 446 447 sc->sc_suspend = PWR_RESUME; 448 449 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 450 uhci_globalreset(sc); /* reset the controller */ 451 uhci_reset(sc); 452 453 /* Allocate and initialize real frame array. */ 454 err = usb_allocmem(&sc->sc_bus, 455 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 456 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 457 if (err) 458 return err; 459 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 460 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 461 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 462 463 /* Initialise mutex early for uhci_alloc_* */ 464 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 465 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 466 467 /* 468 * Allocate a TD, inactive, that hangs from the last QH. 469 * This is to avoid a bug in the PIIX that makes it run berserk 470 * otherwise. 471 */ 472 std = uhci_alloc_std(sc); 473 if (std == NULL) 474 return ENOMEM; 475 std->link.std = NULL; 476 std->td.td_link = htole32(UHCI_PTR_T); 477 std->td.td_status = htole32(0); /* inactive */ 478 std->td.td_token = htole32(0); 479 std->td.td_buffer = htole32(0); 480 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 482 483 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 484 lsqh = uhci_alloc_sqh(sc); 485 if (lsqh == NULL) 486 goto fail1; 487 lsqh->hlink = NULL; 488 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 489 lsqh->elink = std; 490 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 491 sc->sc_last_qh = lsqh; 492 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 494 495 /* Allocate the dummy QH where bulk traffic will be queued. */ 496 bsqh = uhci_alloc_sqh(sc); 497 if (bsqh == NULL) 498 goto fail2; 499 bsqh->hlink = lsqh; 500 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 501 bsqh->elink = NULL; 502 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 503 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 504 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 506 507 /* Allocate dummy QH where high speed control traffic will be queued. */ 508 chsqh = uhci_alloc_sqh(sc); 509 if (chsqh == NULL) 510 goto fail3; 511 chsqh->hlink = bsqh; 512 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 513 chsqh->elink = NULL; 514 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 515 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 516 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 517 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 518 519 /* Allocate dummy QH where control traffic will be queued. */ 520 clsqh = uhci_alloc_sqh(sc); 521 if (clsqh == NULL) 522 goto fail4; 523 clsqh->hlink = chsqh; 524 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 525 clsqh->elink = NULL; 526 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 527 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 528 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 530 531 /* 532 * Make all (virtual) frame list pointers point to the interrupt 533 * queue heads and the interrupt queue heads at the control 534 * queue head and point the physical frame list to the virtual. 535 */ 536 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 537 std = uhci_alloc_std(sc); 538 sqh = uhci_alloc_sqh(sc); 539 if (std == NULL || sqh == NULL) 540 return USBD_NOMEM; 541 std->link.sqh = sqh; 542 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 543 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 544 std->td.td_token = htole32(0); 545 std->td.td_buffer = htole32(0); 546 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 548 sqh->hlink = clsqh; 549 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 550 sqh->elink = NULL; 551 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 552 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 553 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 554 sc->sc_vframes[i].htd = std; 555 sc->sc_vframes[i].etd = std; 556 sc->sc_vframes[i].hqh = sqh; 557 sc->sc_vframes[i].eqh = sqh; 558 for (j = i; 559 j < UHCI_FRAMELIST_COUNT; 560 j += UHCI_VFRAMELIST_COUNT) 561 sc->sc_pframes[j] = htole32(std->physaddr); 562 } 563 usb_syncmem(&sc->sc_dma, 0, 564 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 565 BUS_DMASYNC_PREWRITE); 566 567 568 TAILQ_INIT(&sc->sc_intrhead); 569 570 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 571 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 572 573 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 574 575 cv_init(&sc->sc_softwake_cv, "uhciab"); 576 577 /* Set up the bus struct. */ 578 sc->sc_bus.ub_methods = &uhci_bus_methods; 579 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 580 sc->sc_bus.ub_usedma = true; 581 582 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 583 584 DPRINTF("Enabling...", 0, 0, 0, 0); 585 586 err = uhci_run(sc, 1, 0); /* and here we go... */ 587 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 588 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 589 return err; 590 591 fail4: 592 uhci_free_sqh(sc, chsqh); 593 fail3: 594 uhci_free_sqh(sc, lsqh); 595 fail2: 596 uhci_free_sqh(sc, lsqh); 597 fail1: 598 uhci_free_std(sc, std); 599 600 return ENOMEM; 601 } 602 603 int 604 uhci_activate(device_t self, enum devact act) 605 { 606 struct uhci_softc *sc = device_private(self); 607 608 switch (act) { 609 case DVACT_DEACTIVATE: 610 sc->sc_dying = 1; 611 return 0; 612 default: 613 return EOPNOTSUPP; 614 } 615 } 616 617 void 618 uhci_childdet(device_t self, device_t child) 619 { 620 struct uhci_softc *sc = device_private(self); 621 622 KASSERT(sc->sc_child == child); 623 sc->sc_child = NULL; 624 } 625 626 int 627 uhci_detach(struct uhci_softc *sc, int flags) 628 { 629 int rv = 0; 630 631 if (sc->sc_child != NULL) 632 rv = config_detach(sc->sc_child, flags); 633 634 if (rv != 0) 635 return rv; 636 637 callout_halt(&sc->sc_poll_handle, NULL); 638 callout_destroy(&sc->sc_poll_handle); 639 640 cv_destroy(&sc->sc_softwake_cv); 641 642 mutex_destroy(&sc->sc_lock); 643 mutex_destroy(&sc->sc_intr_lock); 644 645 pool_cache_destroy(sc->sc_xferpool); 646 647 /* XXX free other data structures XXX */ 648 649 return rv; 650 } 651 652 struct usbd_xfer * 653 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 654 { 655 struct uhci_softc *sc = UHCI_BUS2SC(bus); 656 struct usbd_xfer *xfer; 657 658 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 659 if (xfer != NULL) { 660 memset(xfer, 0, sizeof(struct uhci_xfer)); 661 662 #ifdef DIAGNOSTIC 663 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 664 uxfer->ux_isdone = true; 665 xfer->ux_state = XFER_BUSY; 666 #endif 667 } 668 return xfer; 669 } 670 671 void 672 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 673 { 674 struct uhci_softc *sc = UHCI_BUS2SC(bus); 675 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 676 677 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 678 xfer->ux_state); 679 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 680 #ifdef DIAGNOSTIC 681 xfer->ux_state = XFER_FREE; 682 #endif 683 pool_cache_put(sc->sc_xferpool, xfer); 684 } 685 686 Static void 687 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 688 { 689 struct uhci_softc *sc = UHCI_BUS2SC(bus); 690 691 *lock = &sc->sc_lock; 692 } 693 694 695 /* 696 * Handle suspend/resume. 697 * 698 * We need to switch to polling mode here, because this routine is 699 * called from an interrupt context. This is all right since we 700 * are almost suspended anyway. 701 */ 702 bool 703 uhci_resume(device_t dv, const pmf_qual_t *qual) 704 { 705 uhci_softc_t *sc = device_private(dv); 706 int cmd; 707 708 mutex_spin_enter(&sc->sc_intr_lock); 709 710 cmd = UREAD2(sc, UHCI_CMD); 711 sc->sc_bus.ub_usepolling++; 712 UWRITE2(sc, UHCI_INTR, 0); 713 uhci_globalreset(sc); 714 uhci_reset(sc); 715 if (cmd & UHCI_CMD_RS) 716 uhci_run(sc, 0, 1); 717 718 /* restore saved state */ 719 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 720 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 721 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 722 723 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 724 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 725 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 726 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 727 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 728 UHCICMD(sc, UHCI_CMD_MAXP); 729 uhci_run(sc, 1, 1); /* and start traffic again */ 730 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 731 sc->sc_bus.ub_usepolling--; 732 if (sc->sc_intr_xfer != NULL) 733 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 734 sc->sc_intr_xfer); 735 #ifdef UHCI_DEBUG 736 if (uhcidebug >= 2) 737 uhci_dumpregs(sc); 738 #endif 739 740 sc->sc_suspend = PWR_RESUME; 741 mutex_spin_exit(&sc->sc_intr_lock); 742 743 return true; 744 } 745 746 bool 747 uhci_suspend(device_t dv, const pmf_qual_t *qual) 748 { 749 uhci_softc_t *sc = device_private(dv); 750 int cmd; 751 752 mutex_spin_enter(&sc->sc_intr_lock); 753 754 cmd = UREAD2(sc, UHCI_CMD); 755 756 #ifdef UHCI_DEBUG 757 if (uhcidebug >= 2) 758 uhci_dumpregs(sc); 759 #endif 760 if (sc->sc_intr_xfer != NULL) 761 callout_stop(&sc->sc_poll_handle); 762 sc->sc_suspend = PWR_SUSPEND; 763 sc->sc_bus.ub_usepolling++; 764 765 uhci_run(sc, 0, 1); /* stop the controller */ 766 cmd &= ~UHCI_CMD_RS; 767 768 /* save some state if BIOS doesn't */ 769 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 770 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 771 772 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 773 774 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 775 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 776 sc->sc_bus.ub_usepolling--; 777 778 mutex_spin_exit(&sc->sc_intr_lock); 779 780 return true; 781 } 782 783 #ifdef UHCI_DEBUG 784 Static void 785 uhci_dumpregs(uhci_softc_t *sc) 786 { 787 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 788 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 789 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 790 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 791 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 792 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 793 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 794 } 795 796 void 797 uhci_dump_td(uhci_soft_td_t *p) 798 { 799 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 800 801 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 802 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 803 804 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 805 DPRINTF(" link=0x%08x status=0x%08x " 806 "token=0x%08x buffer=0x%08x", 807 le32toh(p->td.td_link), 808 le32toh(p->td.td_status), 809 le32toh(p->td.td_token), 810 le32toh(p->td.td_buffer)); 811 812 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 813 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 814 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 815 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 816 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 817 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 818 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 819 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 820 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 821 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 822 DPRINTF("ios =%d ls =%d spd =%d", 823 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 824 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 825 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 826 DPRINTF("errcnt =%d actlen =%d pid=%02x", 827 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 828 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 829 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 830 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 831 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 832 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 833 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 834 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 835 } 836 837 void 838 uhci_dump_qh(uhci_soft_qh_t *sqh) 839 { 840 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 841 842 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 844 845 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 846 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 847 le32toh(sqh->qh.qh_elink)); 848 849 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 850 } 851 852 853 #if 1 854 void 855 uhci_dump(void) 856 { 857 uhci_dump_all(thesc); 858 } 859 #endif 860 861 void 862 uhci_dump_all(uhci_softc_t *sc) 863 { 864 uhci_dumpregs(sc); 865 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 866 uhci_dump_qhs(sc->sc_lctl_start); 867 } 868 869 870 void 871 uhci_dump_qhs(uhci_soft_qh_t *sqh) 872 { 873 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 874 875 uhci_dump_qh(sqh); 876 877 /* 878 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 879 * Traverses sideways first, then down. 880 * 881 * QH1 882 * QH2 883 * No QH 884 * TD2.1 885 * TD2.2 886 * TD1.1 887 * etc. 888 * 889 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 890 */ 891 892 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 893 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 894 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 895 uhci_dump_qhs(sqh->hlink); 896 else 897 DPRINTF("No QH", 0, 0, 0, 0); 898 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 899 900 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 901 uhci_dump_tds(sqh->elink); 902 else 903 DPRINTF("No QH", 0, 0, 0, 0); 904 } 905 906 void 907 uhci_dump_tds(uhci_soft_td_t *std) 908 { 909 uhci_soft_td_t *td; 910 int stop; 911 912 for (td = std; td != NULL; td = td->link.std) { 913 uhci_dump_td(td); 914 915 /* 916 * Check whether the link pointer in this TD marks 917 * the link pointer as end of queue. This avoids 918 * printing the free list in case the queue/TD has 919 * already been moved there (seatbelt). 920 */ 921 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 922 sizeof(td->td.td_link), 923 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 924 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 925 le32toh(td->td.td_link) == 0); 926 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 927 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 928 if (stop) 929 break; 930 } 931 } 932 933 Static void 934 uhci_dump_ii(struct uhci_xfer *ux) 935 { 936 struct usbd_pipe *pipe; 937 usb_endpoint_descriptor_t *ed; 938 struct usbd_device *dev; 939 940 if (ux == NULL) { 941 printf("ux NULL\n"); 942 return; 943 } 944 pipe = ux->ux_xfer.ux_pipe; 945 if (pipe == NULL) { 946 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 947 return; 948 } 949 if (pipe->up_endpoint == NULL) { 950 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 951 ux, ux->ux_isdone, pipe); 952 return; 953 } 954 if (pipe->up_dev == NULL) { 955 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 956 ux, ux->ux_isdone, pipe); 957 return; 958 } 959 ed = pipe->up_endpoint->ue_edesc; 960 dev = pipe->up_dev; 961 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 962 ux, ux->ux_isdone, dev, 963 UGETW(dev->ud_ddesc.idVendor), 964 UGETW(dev->ud_ddesc.idProduct), 965 dev->ud_addr, pipe, 966 ed->bEndpointAddress, ed->bmAttributes); 967 } 968 969 void uhci_dump_iis(struct uhci_softc *sc); 970 void 971 uhci_dump_iis(struct uhci_softc *sc) 972 { 973 struct uhci_xfer *ux; 974 975 printf("interrupt list:\n"); 976 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 977 uhci_dump_ii(ux); 978 } 979 980 void iidump(void); 981 void iidump(void) { uhci_dump_iis(thesc); } 982 983 #endif 984 985 /* 986 * This routine is executed periodically and simulates interrupts 987 * from the root controller interrupt pipe for port status change. 988 */ 989 void 990 uhci_poll_hub(void *addr) 991 { 992 struct usbd_xfer *xfer = addr; 993 struct usbd_pipe *pipe = xfer->ux_pipe; 994 uhci_softc_t *sc; 995 u_char *p; 996 997 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 998 999 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1000 return; /* device has detached */ 1001 sc = UHCI_PIPE2SC(pipe); 1002 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1003 1004 p = xfer->ux_buf; 1005 p[0] = 0; 1006 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<1; 1008 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<2; 1010 if (p[0] == 0) 1011 /* No change, try again in a while */ 1012 return; 1013 1014 xfer->ux_actlen = 1; 1015 xfer->ux_status = USBD_NORMAL_COMPLETION; 1016 mutex_enter(&sc->sc_lock); 1017 usb_transfer_complete(xfer); 1018 mutex_exit(&sc->sc_lock); 1019 } 1020 1021 void 1022 uhci_root_intr_done(struct usbd_xfer *xfer) 1023 { 1024 } 1025 1026 /* 1027 * Let the last QH loop back to the high speed control transfer QH. 1028 * This is what intel calls "bandwidth reclamation" and improves 1029 * USB performance a lot for some devices. 1030 * If we are already looping, just count it. 1031 */ 1032 void 1033 uhci_add_loop(uhci_softc_t *sc) 1034 { 1035 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1036 1037 #ifdef UHCI_DEBUG 1038 if (uhcinoloop) 1039 return; 1040 #endif 1041 if (++sc->sc_loops == 1) { 1042 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1043 /* Note, we don't loop back the soft pointer. */ 1044 sc->sc_last_qh->qh.qh_hlink = 1045 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1046 usb_syncmem(&sc->sc_last_qh->dma, 1047 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1048 sizeof(sc->sc_last_qh->qh.qh_hlink), 1049 BUS_DMASYNC_PREWRITE); 1050 } 1051 } 1052 1053 void 1054 uhci_rem_loop(uhci_softc_t *sc) 1055 { 1056 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1057 1058 #ifdef UHCI_DEBUG 1059 if (uhcinoloop) 1060 return; 1061 #endif 1062 if (--sc->sc_loops == 0) { 1063 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1064 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1065 usb_syncmem(&sc->sc_last_qh->dma, 1066 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1067 sizeof(sc->sc_last_qh->qh.qh_hlink), 1068 BUS_DMASYNC_PREWRITE); 1069 } 1070 } 1071 1072 /* Add high speed control QH, called with lock held. */ 1073 void 1074 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1075 { 1076 uhci_soft_qh_t *eqh; 1077 1078 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1079 1080 KASSERT(mutex_owned(&sc->sc_lock)); 1081 1082 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1083 eqh = sc->sc_hctl_end; 1084 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1085 sizeof(eqh->qh.qh_hlink), 1086 BUS_DMASYNC_POSTWRITE); 1087 sqh->hlink = eqh->hlink; 1088 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1089 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1090 BUS_DMASYNC_PREWRITE); 1091 eqh->hlink = sqh; 1092 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1093 sc->sc_hctl_end = sqh; 1094 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1095 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1096 #ifdef UHCI_CTL_LOOP 1097 uhci_add_loop(sc); 1098 #endif 1099 } 1100 1101 /* Remove high speed control QH, called with lock held. */ 1102 void 1103 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1104 { 1105 uhci_soft_qh_t *pqh; 1106 uint32_t elink; 1107 1108 KASSERT(mutex_owned(&sc->sc_lock)); 1109 1110 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1111 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1112 #ifdef UHCI_CTL_LOOP 1113 uhci_rem_loop(sc); 1114 #endif 1115 /* 1116 * The T bit should be set in the elink of the QH so that the HC 1117 * doesn't follow the pointer. This condition may fail if the 1118 * the transferred packet was short so that the QH still points 1119 * at the last used TD. 1120 * In this case we set the T bit and wait a little for the HC 1121 * to stop looking at the TD. 1122 * Note that if the TD chain is large enough, the controller 1123 * may still be looking at the chain at the end of this function. 1124 * uhci_free_std_chain() will make sure the controller stops 1125 * looking at it quickly, but until then we should not change 1126 * sqh->hlink. 1127 */ 1128 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1129 sizeof(sqh->qh.qh_elink), 1130 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1131 elink = le32toh(sqh->qh.qh_elink); 1132 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1133 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1134 if (!(elink & UHCI_PTR_T)) { 1135 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1136 usb_syncmem(&sqh->dma, 1137 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1138 sizeof(sqh->qh.qh_elink), 1139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1140 delay(UHCI_QH_REMOVE_DELAY); 1141 } 1142 1143 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1144 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1145 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1146 pqh->hlink = sqh->hlink; 1147 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1148 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1149 sizeof(pqh->qh.qh_hlink), 1150 BUS_DMASYNC_PREWRITE); 1151 delay(UHCI_QH_REMOVE_DELAY); 1152 if (sc->sc_hctl_end == sqh) 1153 sc->sc_hctl_end = pqh; 1154 } 1155 1156 /* Add low speed control QH, called with lock held. */ 1157 void 1158 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1159 { 1160 uhci_soft_qh_t *eqh; 1161 1162 KASSERT(mutex_owned(&sc->sc_lock)); 1163 1164 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1165 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1166 1167 eqh = sc->sc_lctl_end; 1168 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1169 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1170 sqh->hlink = eqh->hlink; 1171 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1172 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1173 BUS_DMASYNC_PREWRITE); 1174 eqh->hlink = sqh; 1175 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1176 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1177 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1178 sc->sc_lctl_end = sqh; 1179 } 1180 1181 /* Remove low speed control QH, called with lock held. */ 1182 void 1183 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1184 { 1185 uhci_soft_qh_t *pqh; 1186 uint32_t elink; 1187 1188 KASSERT(mutex_owned(&sc->sc_lock)); 1189 1190 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1191 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1192 1193 /* See comment in uhci_remove_hs_ctrl() */ 1194 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1195 sizeof(sqh->qh.qh_elink), 1196 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1197 elink = le32toh(sqh->qh.qh_elink); 1198 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1199 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1200 if (!(elink & UHCI_PTR_T)) { 1201 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1202 usb_syncmem(&sqh->dma, 1203 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1204 sizeof(sqh->qh.qh_elink), 1205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1206 delay(UHCI_QH_REMOVE_DELAY); 1207 } 1208 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1209 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1210 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1211 pqh->hlink = sqh->hlink; 1212 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1213 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1214 sizeof(pqh->qh.qh_hlink), 1215 BUS_DMASYNC_PREWRITE); 1216 delay(UHCI_QH_REMOVE_DELAY); 1217 if (sc->sc_lctl_end == sqh) 1218 sc->sc_lctl_end = pqh; 1219 } 1220 1221 /* Add bulk QH, called with lock held. */ 1222 void 1223 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1224 { 1225 uhci_soft_qh_t *eqh; 1226 1227 KASSERT(mutex_owned(&sc->sc_lock)); 1228 1229 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1230 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1231 1232 eqh = sc->sc_bulk_end; 1233 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1234 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1235 sqh->hlink = eqh->hlink; 1236 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1237 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1238 BUS_DMASYNC_PREWRITE); 1239 eqh->hlink = sqh; 1240 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1241 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1242 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1243 sc->sc_bulk_end = sqh; 1244 uhci_add_loop(sc); 1245 } 1246 1247 /* Remove bulk QH, called with lock held. */ 1248 void 1249 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1250 { 1251 uhci_soft_qh_t *pqh; 1252 1253 KASSERT(mutex_owned(&sc->sc_lock)); 1254 1255 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1256 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1257 1258 uhci_rem_loop(sc); 1259 /* See comment in uhci_remove_hs_ctrl() */ 1260 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1261 sizeof(sqh->qh.qh_elink), 1262 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1263 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1264 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1265 usb_syncmem(&sqh->dma, 1266 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1267 sizeof(sqh->qh.qh_elink), 1268 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269 delay(UHCI_QH_REMOVE_DELAY); 1270 } 1271 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1272 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1273 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1274 pqh->hlink = sqh->hlink; 1275 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1276 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1277 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1278 delay(UHCI_QH_REMOVE_DELAY); 1279 if (sc->sc_bulk_end == sqh) 1280 sc->sc_bulk_end = pqh; 1281 } 1282 1283 Static int uhci_intr1(uhci_softc_t *); 1284 1285 int 1286 uhci_intr(void *arg) 1287 { 1288 uhci_softc_t *sc = arg; 1289 int ret = 0; 1290 1291 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1292 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 1295 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1296 goto done; 1297 1298 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1299 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1300 goto done; 1301 } 1302 1303 ret = uhci_intr1(sc); 1304 1305 done: 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 return ret; 1308 } 1309 1310 int 1311 uhci_intr1(uhci_softc_t *sc) 1312 { 1313 int status; 1314 int ack; 1315 1316 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1317 1318 #ifdef UHCI_DEBUG 1319 if (uhcidebug >= 15) { 1320 DPRINTF("sc %p", sc, 0, 0, 0); 1321 uhci_dumpregs(sc); 1322 } 1323 #endif 1324 1325 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1326 1327 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1328 /* Check if the interrupt was for us. */ 1329 if (status == 0) 1330 return 0; 1331 1332 if (sc->sc_suspend != PWR_RESUME) { 1333 #ifdef DIAGNOSTIC 1334 printf("%s: interrupt while not operating ignored\n", 1335 device_xname(sc->sc_dev)); 1336 #endif 1337 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1338 return 0; 1339 } 1340 1341 ack = 0; 1342 if (status & UHCI_STS_USBINT) 1343 ack |= UHCI_STS_USBINT; 1344 if (status & UHCI_STS_USBEI) 1345 ack |= UHCI_STS_USBEI; 1346 if (status & UHCI_STS_RD) { 1347 ack |= UHCI_STS_RD; 1348 #ifdef UHCI_DEBUG 1349 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1350 #endif 1351 } 1352 if (status & UHCI_STS_HSE) { 1353 ack |= UHCI_STS_HSE; 1354 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1355 } 1356 if (status & UHCI_STS_HCPE) { 1357 ack |= UHCI_STS_HCPE; 1358 printf("%s: host controller process error\n", 1359 device_xname(sc->sc_dev)); 1360 } 1361 1362 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1363 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1364 /* no acknowledge needed */ 1365 if (!sc->sc_dying) { 1366 printf("%s: host controller halted\n", 1367 device_xname(sc->sc_dev)); 1368 #ifdef UHCI_DEBUG 1369 uhci_dump_all(sc); 1370 #endif 1371 } 1372 sc->sc_dying = 1; 1373 } 1374 1375 if (!ack) 1376 return 0; /* nothing to acknowledge */ 1377 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1378 1379 usb_schedsoftintr(&sc->sc_bus); 1380 1381 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1382 1383 return 1; 1384 } 1385 1386 void 1387 uhci_softintr(void *v) 1388 { 1389 struct usbd_bus *bus = v; 1390 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1391 struct uhci_xfer *ux, *nextux; 1392 ux_completeq_t cq; 1393 1394 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1395 DPRINTF("sc %p", sc, 0, 0, 0); 1396 1397 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1398 1399 TAILQ_INIT(&cq); 1400 /* 1401 * Interrupts on UHCI really suck. When the host controller 1402 * interrupts because a transfer is completed there is no 1403 * way of knowing which transfer it was. You can scan down 1404 * the TDs and QHs of the previous frame to limit the search, 1405 * but that assumes that the interrupt was not delayed by more 1406 * than 1 ms, which may not always be true (e.g. after debug 1407 * output on a slow console). 1408 * We scan all interrupt descriptors to see if any have 1409 * completed. 1410 */ 1411 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1412 uhci_check_intr(sc, ux, &cq); 1413 } 1414 1415 /* 1416 * We abuse ux_list for the interrupt and complete lists and 1417 * interrupt transfers will get re-added here so use 1418 * the _SAFE version of TAILQ_FOREACH. 1419 */ 1420 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1421 DPRINTF("ux %p", ux, 0, 0, 0); 1422 usb_transfer_complete(&ux->ux_xfer); 1423 } 1424 1425 if (sc->sc_softwake) { 1426 sc->sc_softwake = 0; 1427 cv_broadcast(&sc->sc_softwake_cv); 1428 } 1429 } 1430 1431 /* Check for an interrupt. */ 1432 void 1433 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1434 { 1435 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1436 uint32_t status; 1437 1438 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1439 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1440 1441 KASSERT(ux != NULL); 1442 1443 struct usbd_xfer *xfer = &ux->ux_xfer; 1444 if (xfer->ux_status == USBD_CANCELLED || 1445 xfer->ux_status == USBD_TIMEOUT) { 1446 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1447 return; 1448 } 1449 1450 switch (ux->ux_type) { 1451 case UX_CTRL: 1452 fstd = ux->ux_setup; 1453 lstd = ux->ux_stat; 1454 break; 1455 case UX_BULK: 1456 case UX_INTR: 1457 case UX_ISOC: 1458 fstd = ux->ux_stdstart; 1459 lstd = ux->ux_stdend; 1460 break; 1461 default: 1462 KASSERT(false); 1463 break; 1464 } 1465 if (fstd == NULL) 1466 return; 1467 1468 KASSERT(lstd != NULL); 1469 1470 usb_syncmem(&lstd->dma, 1471 lstd->offs + offsetof(uhci_td_t, td_status), 1472 sizeof(lstd->td.td_status), 1473 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1474 status = le32toh(lstd->td.td_status); 1475 usb_syncmem(&lstd->dma, 1476 lstd->offs + offsetof(uhci_td_t, td_status), 1477 sizeof(lstd->td.td_status), 1478 BUS_DMASYNC_PREREAD); 1479 1480 /* If the last TD is not marked active we can complete */ 1481 if (!(status & UHCI_TD_ACTIVE)) { 1482 done: 1483 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1484 1485 callout_stop(&xfer->ux_callout); 1486 uhci_idone(ux, cqp); 1487 return; 1488 } 1489 1490 /* 1491 * If the last TD is still active we need to check whether there 1492 * is an error somewhere in the middle, or whether there was a 1493 * short packet (SPD and not ACTIVE). 1494 */ 1495 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1496 for (std = fstd; std != lstd; std = std->link.std) { 1497 usb_syncmem(&std->dma, 1498 std->offs + offsetof(uhci_td_t, td_status), 1499 sizeof(std->td.td_status), 1500 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1501 status = le32toh(std->td.td_status); 1502 usb_syncmem(&std->dma, 1503 std->offs + offsetof(uhci_td_t, td_status), 1504 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1505 1506 /* If there's an active TD the xfer isn't done. */ 1507 if (status & UHCI_TD_ACTIVE) { 1508 DPRINTFN(12, "ux=%p std=%p still active", 1509 ux, std, 0, 0); 1510 return; 1511 } 1512 1513 /* Any kind of error makes the xfer done. */ 1514 if (status & UHCI_TD_STALLED) 1515 goto done; 1516 1517 /* 1518 * If the data phase of a control transfer is short, we need 1519 * to complete the status stage 1520 */ 1521 1522 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1523 struct uhci_pipe *upipe = 1524 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1525 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1526 uhci_soft_td_t *stat = upipe->ctrl.stat; 1527 1528 DPRINTFN(12, "ux=%p std=%p control status" 1529 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1530 1531 sqh->qh.qh_elink = 1532 htole32(stat->physaddr | UHCI_PTR_TD); 1533 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1534 BUS_DMASYNC_PREWRITE); 1535 break; 1536 } 1537 1538 /* We want short packets, and it is short: it's done */ 1539 usb_syncmem(&std->dma, 1540 std->offs + offsetof(uhci_td_t, td_token), 1541 sizeof(std->td.td_token), 1542 BUS_DMASYNC_POSTWRITE); 1543 1544 if ((status & UHCI_TD_SPD) && 1545 UHCI_TD_GET_ACTLEN(status) < 1546 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1547 goto done; 1548 } 1549 } 1550 } 1551 1552 /* Called with USB lock held. */ 1553 void 1554 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1555 { 1556 struct usbd_xfer *xfer = &ux->ux_xfer; 1557 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1558 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1559 uhci_soft_td_t *std; 1560 uint32_t status = 0, nstatus; 1561 int actlen; 1562 1563 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1564 1565 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1566 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1567 1568 #ifdef DIAGNOSTIC 1569 #ifdef UHCI_DEBUG 1570 if (ux->ux_isdone) { 1571 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1572 uhci_dump_ii(ux); 1573 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1574 } 1575 #endif 1576 KASSERT(!ux->ux_isdone); 1577 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1578 ux->ux_type, xfer->ux_status); 1579 ux->ux_isdone = true; 1580 #endif 1581 1582 if (xfer->ux_nframes != 0) { 1583 /* Isoc transfer, do things differently. */ 1584 uhci_soft_td_t **stds = upipe->isoc.stds; 1585 int i, n, nframes, len; 1586 1587 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1588 1589 nframes = xfer->ux_nframes; 1590 actlen = 0; 1591 n = ux->ux_curframe; 1592 for (i = 0; i < nframes; i++) { 1593 std = stds[n]; 1594 #ifdef UHCI_DEBUG 1595 if (uhcidebug >= 5) { 1596 DPRINTF("isoc TD %d", i, 0, 0, 0); 1597 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1598 uhci_dump_td(std); 1599 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1600 } 1601 #endif 1602 if (++n >= UHCI_VFRAMELIST_COUNT) 1603 n = 0; 1604 usb_syncmem(&std->dma, 1605 std->offs + offsetof(uhci_td_t, td_status), 1606 sizeof(std->td.td_status), 1607 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1608 status = le32toh(std->td.td_status); 1609 len = UHCI_TD_GET_ACTLEN(status); 1610 xfer->ux_frlengths[i] = len; 1611 actlen += len; 1612 } 1613 upipe->isoc.inuse -= nframes; 1614 xfer->ux_actlen = actlen; 1615 xfer->ux_status = USBD_NORMAL_COMPLETION; 1616 goto end; 1617 } 1618 1619 #ifdef UHCI_DEBUG 1620 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1621 if (uhcidebug >= 10) { 1622 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1623 uhci_dump_tds(ux->ux_stdstart); 1624 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1625 } 1626 #endif 1627 1628 /* The transfer is done, compute actual length and status. */ 1629 actlen = 0; 1630 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1631 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1632 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1633 nstatus = le32toh(std->td.td_status); 1634 if (nstatus & UHCI_TD_ACTIVE) 1635 break; 1636 1637 status = nstatus; 1638 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1639 UHCI_TD_PID_SETUP) 1640 actlen += UHCI_TD_GET_ACTLEN(status); 1641 else { 1642 /* 1643 * UHCI will report CRCTO in addition to a STALL or NAK 1644 * for a SETUP transaction. See section 3.2.2, "TD 1645 * CONTROL AND STATUS". 1646 */ 1647 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1648 status &= ~UHCI_TD_CRCTO; 1649 } 1650 } 1651 /* If there are left over TDs we need to update the toggle. */ 1652 if (std != NULL) 1653 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1654 1655 status &= UHCI_TD_ERROR; 1656 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1657 xfer->ux_actlen = actlen; 1658 if (status != 0) { 1659 1660 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1661 "error, addr=%d, endpt=0x%02x", 1662 xfer->ux_pipe->up_dev->ud_addr, 1663 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1664 0, 0); 1665 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1666 "bitstuff=%d crcto =%d nak =%d babble =%d", 1667 !!(status & UHCI_TD_BITSTUFF), 1668 !!(status & UHCI_TD_CRCTO), 1669 !!(status & UHCI_TD_NAK), 1670 !!(status & UHCI_TD_BABBLE)); 1671 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1672 "dbuffer =%d stalled =%d active =%d", 1673 !!(status & UHCI_TD_DBUFFER), 1674 !!(status & UHCI_TD_STALLED), 1675 !!(status & UHCI_TD_ACTIVE), 1676 0); 1677 1678 if (status == UHCI_TD_STALLED) 1679 xfer->ux_status = USBD_STALLED; 1680 else 1681 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1682 } else { 1683 xfer->ux_status = USBD_NORMAL_COMPLETION; 1684 } 1685 1686 end: 1687 uhci_del_intr_list(sc, ux); 1688 if (cqp) 1689 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1690 1691 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1692 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1693 } 1694 1695 /* 1696 * Called when a request does not complete. 1697 */ 1698 void 1699 uhci_timeout(void *addr) 1700 { 1701 struct usbd_xfer *xfer = addr; 1702 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1703 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1704 1705 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1706 1707 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1708 1709 if (sc->sc_dying) { 1710 mutex_enter(&sc->sc_lock); 1711 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1712 mutex_exit(&sc->sc_lock); 1713 return; 1714 } 1715 1716 /* Execute the abort in a process context. */ 1717 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1718 USB_TASKQ_MPSAFE); 1719 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1720 USB_TASKQ_HC); 1721 } 1722 1723 void 1724 uhci_timeout_task(void *addr) 1725 { 1726 struct usbd_xfer *xfer = addr; 1727 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1728 1729 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1730 1731 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1732 1733 mutex_enter(&sc->sc_lock); 1734 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1735 mutex_exit(&sc->sc_lock); 1736 } 1737 1738 /* 1739 * Wait here until controller claims to have an interrupt. 1740 * Then call uhci_intr and return. Use timeout to avoid waiting 1741 * too long. 1742 * Only used during boot when interrupts are not enabled yet. 1743 */ 1744 void 1745 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1746 { 1747 int timo = xfer->ux_timeout; 1748 struct uhci_xfer *ux; 1749 1750 mutex_enter(&sc->sc_lock); 1751 1752 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1753 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1754 1755 xfer->ux_status = USBD_IN_PROGRESS; 1756 for (; timo >= 0; timo--) { 1757 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1758 DPRINTFN(20, "0x%04x", 1759 UREAD2(sc, UHCI_STS), 0, 0, 0); 1760 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1761 mutex_spin_enter(&sc->sc_intr_lock); 1762 uhci_intr1(sc); 1763 mutex_spin_exit(&sc->sc_intr_lock); 1764 if (xfer->ux_status != USBD_IN_PROGRESS) 1765 goto done; 1766 } 1767 } 1768 1769 /* Timeout */ 1770 DPRINTF("timeout", 0, 0, 0, 0); 1771 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 1772 if (&ux->ux_xfer == xfer) 1773 break; 1774 1775 KASSERT(ux != NULL); 1776 1777 uhci_idone(ux, NULL); 1778 usb_transfer_complete(&ux->ux_xfer); 1779 1780 done: 1781 mutex_exit(&sc->sc_lock); 1782 } 1783 1784 void 1785 uhci_poll(struct usbd_bus *bus) 1786 { 1787 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1788 1789 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1790 mutex_spin_enter(&sc->sc_intr_lock); 1791 uhci_intr1(sc); 1792 mutex_spin_exit(&sc->sc_intr_lock); 1793 } 1794 } 1795 1796 void 1797 uhci_reset(uhci_softc_t *sc) 1798 { 1799 int n; 1800 1801 UHCICMD(sc, UHCI_CMD_HCRESET); 1802 /* The reset bit goes low when the controller is done. */ 1803 for (n = 0; n < UHCI_RESET_TIMEOUT && 1804 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1805 usb_delay_ms(&sc->sc_bus, 1); 1806 if (n >= UHCI_RESET_TIMEOUT) 1807 printf("%s: controller did not reset\n", 1808 device_xname(sc->sc_dev)); 1809 } 1810 1811 usbd_status 1812 uhci_run(uhci_softc_t *sc, int run, int locked) 1813 { 1814 int n, running; 1815 uint16_t cmd; 1816 1817 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1818 1819 run = run != 0; 1820 if (!locked) 1821 mutex_spin_enter(&sc->sc_intr_lock); 1822 1823 DPRINTF("setting run=%d", run, 0, 0, 0); 1824 cmd = UREAD2(sc, UHCI_CMD); 1825 if (run) 1826 cmd |= UHCI_CMD_RS; 1827 else 1828 cmd &= ~UHCI_CMD_RS; 1829 UHCICMD(sc, cmd); 1830 for (n = 0; n < 10; n++) { 1831 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1832 /* return when we've entered the state we want */ 1833 if (run == running) { 1834 if (!locked) 1835 mutex_spin_exit(&sc->sc_intr_lock); 1836 DPRINTF("done cmd=0x%x sts=0x%x", 1837 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1838 return USBD_NORMAL_COMPLETION; 1839 } 1840 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1841 } 1842 if (!locked) 1843 mutex_spin_exit(&sc->sc_intr_lock); 1844 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1845 run ? "start" : "stop"); 1846 return USBD_IOERROR; 1847 } 1848 1849 /* 1850 * Memory management routines. 1851 * uhci_alloc_std allocates TDs 1852 * uhci_alloc_sqh allocates QHs 1853 * These two routines do their own free list management, 1854 * partly for speed, partly because allocating DMAable memory 1855 * has page size granularity so much memory would be wasted if 1856 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1857 */ 1858 1859 uhci_soft_td_t * 1860 uhci_alloc_std(uhci_softc_t *sc) 1861 { 1862 uhci_soft_td_t *std; 1863 usbd_status err; 1864 int i, offs; 1865 usb_dma_t dma; 1866 1867 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1868 1869 mutex_enter(&sc->sc_lock); 1870 if (sc->sc_freetds == NULL) { 1871 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1872 mutex_exit(&sc->sc_lock); 1873 1874 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1875 UHCI_TD_ALIGN, &dma); 1876 if (err) 1877 return NULL; 1878 1879 mutex_enter(&sc->sc_lock); 1880 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1881 offs = i * UHCI_STD_SIZE; 1882 std = KERNADDR(&dma, offs); 1883 std->physaddr = DMAADDR(&dma, offs); 1884 std->dma = dma; 1885 std->offs = offs; 1886 std->link.std = sc->sc_freetds; 1887 sc->sc_freetds = std; 1888 } 1889 } 1890 std = sc->sc_freetds; 1891 sc->sc_freetds = std->link.std; 1892 mutex_exit(&sc->sc_lock); 1893 1894 memset(&std->td, 0, sizeof(uhci_td_t)); 1895 1896 return std; 1897 } 1898 1899 #define TD_IS_FREE 0x12345678 1900 1901 void 1902 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1903 { 1904 KASSERT(mutex_owned(&sc->sc_lock)); 1905 1906 #ifdef DIAGNOSTIC 1907 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1908 printf("%s: freeing free TD %p\n", __func__, std); 1909 return; 1910 } 1911 std->td.td_token = htole32(TD_IS_FREE); 1912 #endif 1913 1914 std->link.std = sc->sc_freetds; 1915 sc->sc_freetds = std; 1916 } 1917 1918 void 1919 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1920 { 1921 mutex_enter(&sc->sc_lock); 1922 uhci_free_std_locked(sc, std); 1923 mutex_exit(&sc->sc_lock); 1924 } 1925 1926 uhci_soft_qh_t * 1927 uhci_alloc_sqh(uhci_softc_t *sc) 1928 { 1929 uhci_soft_qh_t *sqh; 1930 usbd_status err; 1931 int i, offs; 1932 usb_dma_t dma; 1933 1934 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1935 1936 mutex_enter(&sc->sc_lock); 1937 if (sc->sc_freeqhs == NULL) { 1938 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1939 mutex_exit(&sc->sc_lock); 1940 1941 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1942 UHCI_QH_ALIGN, &dma); 1943 if (err) 1944 return NULL; 1945 1946 mutex_enter(&sc->sc_lock); 1947 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1948 offs = i * UHCI_SQH_SIZE; 1949 sqh = KERNADDR(&dma, offs); 1950 sqh->physaddr = DMAADDR(&dma, offs); 1951 sqh->dma = dma; 1952 sqh->offs = offs; 1953 sqh->hlink = sc->sc_freeqhs; 1954 sc->sc_freeqhs = sqh; 1955 } 1956 } 1957 sqh = sc->sc_freeqhs; 1958 sc->sc_freeqhs = sqh->hlink; 1959 mutex_exit(&sc->sc_lock); 1960 1961 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1962 1963 return sqh; 1964 } 1965 1966 void 1967 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1968 { 1969 KASSERT(mutex_owned(&sc->sc_lock)); 1970 1971 sqh->hlink = sc->sc_freeqhs; 1972 sc->sc_freeqhs = sqh; 1973 } 1974 1975 void 1976 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1977 uhci_soft_td_t *stdend) 1978 { 1979 uhci_soft_td_t *p; 1980 uint32_t td_link; 1981 1982 /* 1983 * to avoid race condition with the controller which may be looking 1984 * at this chain, we need to first invalidate all links, and 1985 * then wait for the controller to move to another queue 1986 */ 1987 for (p = std; p != stdend; p = p->link.std) { 1988 usb_syncmem(&p->dma, 1989 p->offs + offsetof(uhci_td_t, td_link), 1990 sizeof(p->td.td_link), 1991 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1992 td_link = le32toh(p->td.td_link); 1993 usb_syncmem(&p->dma, 1994 p->offs + offsetof(uhci_td_t, td_link), 1995 sizeof(p->td.td_link), 1996 BUS_DMASYNC_PREREAD); 1997 if ((td_link & UHCI_PTR_T) == 0) { 1998 p->td.td_link = htole32(UHCI_PTR_T); 1999 usb_syncmem(&p->dma, 2000 p->offs + offsetof(uhci_td_t, td_link), 2001 sizeof(p->td.td_link), 2002 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2003 } 2004 } 2005 delay(UHCI_QH_REMOVE_DELAY); 2006 2007 for (; std != stdend; std = p) { 2008 p = std->link.std; 2009 uhci_free_std(sc, std); 2010 } 2011 } 2012 2013 usbd_status 2014 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int alen, 2015 int rd, uhci_soft_td_t **sp, uhci_soft_td_t **ep) 2016 { 2017 uhci_soft_td_t *p, *lastp; 2018 uhci_physaddr_t lastlink; 2019 int i, l, maxp; 2020 int len; 2021 uint32_t status; 2022 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2023 int addr = xfer->ux_pipe->up_dev->ud_addr; 2024 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2025 usb_dma_t *dma = &xfer->ux_dmabuf; 2026 uint16_t flags = xfer->ux_flags; 2027 2028 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2029 2030 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 2031 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 2032 addr, UE_GET_ADDR(endpt), alen, xfer->ux_pipe->up_dev->ud_speed); 2033 2034 ASSERT_SLEEPABLE(); 2035 KASSERT(sp); 2036 2037 len = alen; 2038 maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2039 if (maxp == 0) { 2040 printf("%s: maxp=0\n", __func__); 2041 return USBD_INVAL; 2042 } 2043 size_t ntd = (len + maxp - 1) / maxp; 2044 if ((flags & USBD_FORCE_SHORT_XFER) && len % maxp == 0) 2045 ntd++; 2046 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 2047 2048 uxfer->ux_stds = NULL; 2049 uxfer->ux_nstd = ntd; 2050 if (ntd == 0) { 2051 *sp = NULL; 2052 if (ep) 2053 *ep = NULL; 2054 DPRINTF("ntd=0", 0, 0, 0, 0); 2055 return USBD_NORMAL_COMPLETION; 2056 } 2057 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2058 KM_SLEEP); 2059 2060 lastp = NULL; 2061 ntd--; 2062 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2063 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_LOW) 2064 status |= UHCI_TD_LS; 2065 if (flags & USBD_SHORT_XFER_OK) 2066 status |= UHCI_TD_SPD; 2067 for (i = ntd; i >= 0; i--) { 2068 p = uhci_alloc_std(sc); 2069 if (p == NULL) { 2070 uhci_free_std_chain(sc, lastp, NULL); 2071 return USBD_NOMEM; 2072 } 2073 uxfer->ux_stds[i] = p; 2074 if (i == ntd) { 2075 /* last TD */ 2076 l = len % maxp; 2077 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 2078 l = maxp; 2079 if (ep) 2080 *ep = p; 2081 lastlink = UHCI_PTR_T; 2082 } else { 2083 l = maxp; 2084 lastlink = p->physaddr; 2085 } 2086 p->link.std = lastp; 2087 p->td.td_link = htole32(lastlink | UHCI_PTR_VF | UHCI_PTR_TD); 2088 p->td.td_status = htole32(status); 2089 p->td.td_token = htole32( 2090 (rd ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2091 UHCI_TD_SET_MAXLEN(l) | 2092 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2093 UHCI_TD_SET_DEVADDR(addr) 2094 ); 2095 p->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2096 DPRINTF("std %p link 0x%08x status 0x%08x token 0x%08x", 2097 p, le32toh(p->td.td_link), le32toh(p->td.td_status), 2098 le32toh(p->td.td_token)); 2099 2100 lastp = p; 2101 } 2102 *sp = lastp; 2103 2104 return USBD_NORMAL_COMPLETION; 2105 } 2106 2107 Static void 2108 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2109 { 2110 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2111 2112 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2113 2114 mutex_enter(&sc->sc_lock); 2115 for (size_t i = 0; i < ux->ux_nstd; i++) { 2116 uhci_soft_td_t *std = ux->ux_stds[i]; 2117 #ifdef DIAGNOSTIC 2118 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2119 printf("%s: freeing free TD %p\n", __func__, std); 2120 return; 2121 } 2122 std->td.td_token = htole32(TD_IS_FREE); 2123 #endif 2124 ux->ux_stds[i]->link.std = sc->sc_freetds; 2125 sc->sc_freetds = std; 2126 } 2127 mutex_exit(&sc->sc_lock); 2128 } 2129 2130 2131 Static void 2132 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2133 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2134 { 2135 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2136 struct usbd_pipe *pipe = xfer->ux_pipe; 2137 usb_dma_t *dma = &xfer->ux_dmabuf; 2138 uint16_t flags = xfer->ux_flags; 2139 uhci_soft_td_t *std, *prev; 2140 int len = length; 2141 int tog = *toggle; 2142 int maxp; 2143 uint32_t status; 2144 size_t i; 2145 2146 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2147 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2148 len, isread, *toggle); 2149 2150 KASSERT(len != 0 || (flags & USBD_FORCE_SHORT_XFER)); 2151 2152 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2153 KASSERT(maxp != 0); 2154 2155 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2156 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2157 status |= UHCI_TD_LS; 2158 if (flags & USBD_SHORT_XFER_OK) 2159 status |= UHCI_TD_SPD; 2160 usb_syncmem(dma, 0, len, 2161 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2162 2163 std = prev = NULL; 2164 for (i = 0; i < uxfer->ux_nstd; i++, prev = std) { 2165 int l = len; 2166 std = uxfer->ux_stds[i]; 2167 if (l > maxp) 2168 l = maxp; 2169 if (l == 0 && !(flags & USBD_FORCE_SHORT_XFER)) 2170 break; 2171 2172 if (prev) { 2173 prev->link.std = std; 2174 prev->td.td_link = htole32( 2175 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2176 ); 2177 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2178 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2179 } 2180 2181 int addr __diagused = xfer->ux_pipe->up_dev->ud_addr; 2182 int endpt __diagused = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2183 KASSERTMSG(UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)) == UE_GET_ADDR(endpt), 2184 "%" __PRIuBIT " vs %d (0x%08x) in %p", 2185 UHCI_TD_GET_ENDPT(le32toh(std->td.td_token)), 2186 UE_GET_ADDR(endpt), le32toh(std->td.td_token), std); 2187 KASSERTMSG(UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)) == addr, 2188 "%" __PRIuBIT " vs %d (0x%08x) in %p", 2189 UHCI_TD_GET_DEVADDR(le32toh(std->td.td_token)), addr, 2190 le32toh(std->td.td_token), std); 2191 2192 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2194 2195 std->td.td_status = htole32(status); 2196 std->td.td_token &= ~htole32( 2197 UHCI_TD_PID_MASK | 2198 UHCI_TD_DT_MASK | 2199 UHCI_TD_MAXLEN_MASK 2200 ); 2201 std->td.td_token |= htole32( 2202 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2203 UHCI_TD_SET_DT(tog) | 2204 UHCI_TD_SET_MAXLEN(l) 2205 ); 2206 std->td.td_link &= ~htole32(UHCI_PTR_T); 2207 2208 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2210 tog ^= 1; 2211 2212 len -= l; 2213 if (len == 0) 2214 break; 2215 } 2216 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2217 xfer, length, len, maxp, uxfer->ux_nstd, i); 2218 2219 if (i < uxfer->ux_nstd) { 2220 /* 2221 * The full allocation chain wasn't used, so we need to 2222 * terminate it. 2223 */ 2224 std->link.std = NULL; 2225 std->td.td_link = htole32(UHCI_PTR_T); 2226 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2228 } 2229 *lstd = std; 2230 *toggle = tog; 2231 } 2232 2233 void 2234 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2235 { 2236 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2237 upipe->nexttoggle = 0; 2238 } 2239 2240 void 2241 uhci_noop(struct usbd_pipe *pipe) 2242 { 2243 } 2244 2245 int 2246 uhci_device_bulk_init(struct usbd_xfer *xfer) 2247 { 2248 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2249 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2250 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2251 int endpt = ed->bEndpointAddress; 2252 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2253 int len = xfer->ux_bufsize; 2254 int err = 0; 2255 2256 2257 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2258 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2259 2260 if (sc->sc_dying) 2261 return USBD_IOERROR; 2262 2263 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2264 2265 uxfer->ux_type = UX_BULK; 2266 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart, 2267 &uxfer->ux_stdend); 2268 if (err) 2269 return err; 2270 2271 #ifdef UHCI_DEBUG 2272 if (uhcidebug >= 10) { 2273 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2274 uhci_dump_tds(uxfer->ux_stdstart); 2275 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2276 } 2277 #endif 2278 2279 return 0; 2280 } 2281 2282 Static void 2283 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2284 { 2285 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2286 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2287 2288 KASSERT(ux->ux_type == UX_BULK); 2289 2290 uhci_free_stds(sc, ux); 2291 if (ux->ux_nstd) 2292 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2293 } 2294 2295 usbd_status 2296 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2297 { 2298 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2299 usbd_status err; 2300 2301 /* Insert last in queue. */ 2302 mutex_enter(&sc->sc_lock); 2303 err = usb_insert_transfer(xfer); 2304 mutex_exit(&sc->sc_lock); 2305 if (err) 2306 return err; 2307 2308 /* 2309 * Pipe isn't running (otherwise err would be USBD_INPROG), 2310 * so start it first. 2311 */ 2312 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2313 } 2314 2315 usbd_status 2316 uhci_device_bulk_start(struct usbd_xfer *xfer) 2317 { 2318 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2319 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2320 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2321 uhci_soft_td_t *data, *dataend; 2322 uhci_soft_qh_t *sqh; 2323 int len; 2324 int endpt; 2325 int isread; 2326 2327 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2328 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2329 xfer->ux_flags, 0); 2330 2331 if (sc->sc_dying) 2332 return USBD_IOERROR; 2333 2334 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2335 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2336 2337 len = xfer->ux_length; 2338 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2339 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2340 sqh = upipe->bulk.sqh; 2341 2342 /* Take lock here to protect nexttoggle */ 2343 mutex_enter(&sc->sc_lock); 2344 2345 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2346 &dataend); 2347 2348 data = ux->ux_stdstart; 2349 ux->ux_stdend = dataend; 2350 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2351 usb_syncmem(&dataend->dma, 2352 dataend->offs + offsetof(uhci_td_t, td_status), 2353 sizeof(dataend->td.td_status), 2354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2355 2356 #ifdef UHCI_DEBUG 2357 if (uhcidebug >= 10) { 2358 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2359 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2360 uhci_dump_tds(data); 2361 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2362 } 2363 #endif 2364 2365 KASSERT(ux->ux_isdone); 2366 #ifdef DIAGNOSTIC 2367 ux->ux_isdone = false; 2368 #endif 2369 2370 sqh->elink = data; 2371 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2372 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2373 2374 uhci_add_bulk(sc, sqh); 2375 uhci_add_intr_list(sc, ux); 2376 2377 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2378 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2379 uhci_timeout, xfer); 2380 } 2381 xfer->ux_status = USBD_IN_PROGRESS; 2382 mutex_exit(&sc->sc_lock); 2383 2384 if (sc->sc_bus.ub_usepolling) 2385 uhci_waitintr(sc, xfer); 2386 2387 return USBD_IN_PROGRESS; 2388 } 2389 2390 /* Abort a device bulk request. */ 2391 void 2392 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2393 { 2394 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2395 2396 KASSERT(mutex_owned(&sc->sc_lock)); 2397 2398 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2399 2400 uhci_abort_xfer(xfer, USBD_CANCELLED); 2401 } 2402 2403 /* 2404 * Abort a device request. 2405 * If this routine is called at splusb() it guarantees that the request 2406 * will be removed from the hardware scheduling and that the callback 2407 * for it will be called with USBD_CANCELLED status. 2408 * It's impossible to guarantee that the requested transfer will not 2409 * have happened since the hardware runs concurrently. 2410 * If the transaction has already happened we rely on the ordinary 2411 * interrupt processing to process it. 2412 * XXX This is most probably wrong. 2413 * XXXMRG this doesn't make sense anymore. 2414 */ 2415 void 2416 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2417 { 2418 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2419 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2420 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2421 uhci_soft_td_t *std; 2422 int wake; 2423 2424 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2425 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2426 2427 KASSERT(mutex_owned(&sc->sc_lock)); 2428 ASSERT_SLEEPABLE(); 2429 2430 if (sc->sc_dying) { 2431 /* If we're dying, just do the software part. */ 2432 xfer->ux_status = status; /* make software ignore it */ 2433 callout_stop(&xfer->ux_callout); 2434 usb_transfer_complete(xfer); 2435 return; 2436 } 2437 2438 /* 2439 * If an abort is already in progress then just wait for it to 2440 * complete and return. 2441 */ 2442 if (xfer->ux_hcflags & UXFER_ABORTING) { 2443 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2444 #ifdef DIAGNOSTIC 2445 if (status == USBD_TIMEOUT) 2446 printf("%s: TIMEOUT while aborting\n", __func__); 2447 #endif 2448 /* Override the status which might be USBD_TIMEOUT. */ 2449 xfer->ux_status = status; 2450 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2451 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2452 while (xfer->ux_hcflags & UXFER_ABORTING) 2453 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2454 goto done; 2455 } 2456 xfer->ux_hcflags |= UXFER_ABORTING; 2457 2458 /* 2459 * Step 1: Make interrupt routine and hardware ignore xfer. 2460 */ 2461 xfer->ux_status = status; /* make software ignore it */ 2462 callout_stop(&xfer->ux_callout); 2463 uhci_del_intr_list(sc, ux); 2464 2465 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2466 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2467 usb_syncmem(&std->dma, 2468 std->offs + offsetof(uhci_td_t, td_status), 2469 sizeof(std->td.td_status), 2470 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2471 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2472 usb_syncmem(&std->dma, 2473 std->offs + offsetof(uhci_td_t, td_status), 2474 sizeof(std->td.td_status), 2475 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2476 } 2477 2478 /* 2479 * Step 2: Wait until we know hardware has finished any possible 2480 * use of the xfer. Also make sure the soft interrupt routine 2481 * has run. 2482 */ 2483 /* Hardware finishes in 1ms */ 2484 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2485 sc->sc_softwake = 1; 2486 usb_schedsoftintr(&sc->sc_bus); 2487 DPRINTF("cv_wait", 0, 0, 0, 0); 2488 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2489 2490 /* 2491 * Step 3: Execute callback. 2492 */ 2493 DPRINTF("callback", 0, 0, 0, 0); 2494 #ifdef DIAGNOSTIC 2495 ux->ux_isdone = true; 2496 #endif 2497 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2498 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2499 usb_transfer_complete(xfer); 2500 if (wake) 2501 cv_broadcast(&xfer->ux_hccv); 2502 done: 2503 KASSERT(mutex_owned(&sc->sc_lock)); 2504 } 2505 2506 /* Close a device bulk pipe. */ 2507 void 2508 uhci_device_bulk_close(struct usbd_pipe *pipe) 2509 { 2510 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2511 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2512 2513 KASSERT(mutex_owned(&sc->sc_lock)); 2514 2515 uhci_free_sqh(sc, upipe->bulk.sqh); 2516 2517 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2518 } 2519 2520 int 2521 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2522 { 2523 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2524 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2525 usb_device_request_t *req = &xfer->ux_request; 2526 struct usbd_device *dev = upipe->pipe.up_dev; 2527 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2528 int addr = dev->ud_addr; 2529 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2530 uhci_soft_td_t *setup, *data, *stat, *next, *dataend; 2531 int len; 2532 uint32_t ls; 2533 usbd_status err; 2534 int isread; 2535 2536 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2537 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", xfer->ux_bufsize, 2538 dev->ud_addr, endpt, 0); 2539 2540 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2541 isread = req->bmRequestType & UT_READ; 2542 len = xfer->ux_bufsize; 2543 2544 uxfer->ux_type = UX_CTRL; 2545 setup = upipe->ctrl.setup; 2546 stat = upipe->ctrl.stat; 2547 2548 /* Set up data transaction */ 2549 if (len != 0) { 2550 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data, 2551 &dataend); 2552 if (err) 2553 return err; 2554 next = data; 2555 dataend->link.std = stat; 2556 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2557 } else { 2558 next = stat; 2559 } 2560 2561 setup->link.std = next; 2562 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2563 setup->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2564 UHCI_TD_ACTIVE); 2565 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2566 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2567 2568 stat->link.std = NULL; 2569 stat->td.td_link = htole32(UHCI_PTR_T); 2570 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2571 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2572 stat->td.td_token = 2573 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2574 UHCI_TD_IN (0, endpt, addr, 1)); 2575 stat->td.td_buffer = htole32(0); 2576 2577 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 2578 #ifdef UHCI_DEBUG 2579 if (uhcidebug >= 10) { 2580 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2581 uhci_dump_tds(setup); 2582 } 2583 #endif 2584 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 2585 2586 /* Set up interrupt info. */ 2587 uxfer->ux_setup = setup; 2588 uxfer->ux_data = data; 2589 uxfer->ux_stat = stat; 2590 2591 return 0; 2592 } 2593 2594 Static void 2595 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2596 { 2597 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2598 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2599 2600 KASSERT(ux->ux_type == UX_CTRL); 2601 2602 uhci_free_stds(sc, ux); 2603 if (ux->ux_nstd) 2604 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2605 } 2606 2607 usbd_status 2608 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2609 { 2610 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2611 usbd_status err; 2612 2613 /* Insert last in queue. */ 2614 mutex_enter(&sc->sc_lock); 2615 err = usb_insert_transfer(xfer); 2616 mutex_exit(&sc->sc_lock); 2617 if (err) 2618 return err; 2619 2620 /* 2621 * Pipe isn't running (otherwise err would be USBD_INPROG), 2622 * so start it first. 2623 */ 2624 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2625 } 2626 2627 usbd_status 2628 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2629 { 2630 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2631 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2632 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2633 usb_device_request_t *req = &xfer->ux_request; 2634 struct usbd_device *dev = upipe->pipe.up_dev; 2635 int addr = dev->ud_addr; 2636 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2637 uhci_soft_td_t *setup, *stat, *next, *dataend; 2638 uhci_soft_qh_t *sqh; 2639 int len; 2640 uint32_t ls; 2641 int isread; 2642 2643 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2644 2645 if (sc->sc_dying) 2646 return USBD_IOERROR; 2647 2648 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2649 2650 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2651 "wValue=0x%04x, wIndex=0x%04x", 2652 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2653 UGETW(req->wIndex)); 2654 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2655 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2656 2657 ls = dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0; 2658 isread = req->bmRequestType & UT_READ; 2659 len = UGETW(req->wLength); 2660 2661 setup = upipe->ctrl.setup; 2662 stat = upipe->ctrl.stat; 2663 sqh = upipe->ctrl.sqh; 2664 2665 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2666 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2667 2668 mutex_enter(&sc->sc_lock); 2669 2670 /* Set up data transaction */ 2671 if (len != 0) { 2672 upipe->nexttoggle = 1; 2673 next = uxfer->ux_data; 2674 uhci_reset_std_chain(sc, xfer, len, isread, 2675 &upipe->nexttoggle, &dataend); 2676 dataend->link.std = stat; 2677 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2678 usb_syncmem(&dataend->dma, 2679 dataend->offs + offsetof(uhci_td_t, td_link), 2680 sizeof(dataend->td.td_link), 2681 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2682 } else { 2683 next = stat; 2684 } 2685 2686 setup->link.std = next; 2687 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2688 setup->td.td_status |= htole32( 2689 UHCI_TD_SET_ERRCNT(3) | 2690 ls | 2691 UHCI_TD_ACTIVE 2692 ); 2693 setup->td.td_token &= ~htole32(UHCI_TD_MAXLEN_MASK); 2694 setup->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(sizeof(*req))); 2695 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2696 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2697 2698 stat->link.std = NULL; 2699 stat->td.td_link = htole32(UHCI_PTR_T); 2700 stat->td.td_status = htole32(UHCI_TD_SET_ERRCNT(3) | ls | 2701 UHCI_TD_ACTIVE | UHCI_TD_IOC); 2702 stat->td.td_token = 2703 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2704 UHCI_TD_IN (0, endpt, addr, 1)); 2705 stat->td.td_buffer = htole32(0); 2706 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2707 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2708 2709 #ifdef UHCI_DEBUG 2710 if (uhcidebug >= 10) { 2711 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2712 DPRINTF("before transfer", 0, 0, 0, 0); 2713 uhci_dump_tds(setup); 2714 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2715 } 2716 #endif 2717 2718 /* Set up interrupt info. */ 2719 uxfer->ux_setup = setup; 2720 uxfer->ux_stat = stat; 2721 KASSERT(uxfer->ux_isdone); 2722 #ifdef DIAGNOSTIC 2723 uxfer->ux_isdone = false; 2724 #endif 2725 2726 sqh->elink = setup; 2727 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2728 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2729 2730 if (dev->ud_speed == USB_SPEED_LOW) 2731 uhci_add_ls_ctrl(sc, sqh); 2732 else 2733 uhci_add_hs_ctrl(sc, sqh); 2734 uhci_add_intr_list(sc, uxfer); 2735 #ifdef UHCI_DEBUG 2736 if (uhcidebug >= 12) { 2737 uhci_soft_td_t *std; 2738 uhci_soft_qh_t *xqh; 2739 uhci_soft_qh_t *sxqh; 2740 int maxqh = 0; 2741 uhci_physaddr_t link; 2742 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2743 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2744 for (std = sc->sc_vframes[0].htd, link = 0; 2745 (link & UHCI_PTR_QH) == 0; 2746 std = std->link.std) { 2747 link = le32toh(std->td.td_link); 2748 uhci_dump_td(std); 2749 } 2750 sxqh = (uhci_soft_qh_t *)std; 2751 uhci_dump_qh(sxqh); 2752 for (xqh = sxqh; 2753 xqh != NULL; 2754 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2755 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2756 uhci_dump_qh(xqh); 2757 } 2758 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2759 uhci_dump_qh(sqh); 2760 uhci_dump_tds(sqh->elink); 2761 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2762 } 2763 #endif 2764 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2765 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2766 uhci_timeout, xfer); 2767 } 2768 xfer->ux_status = USBD_IN_PROGRESS; 2769 mutex_exit(&sc->sc_lock); 2770 2771 if (sc->sc_bus.ub_usepolling) 2772 uhci_waitintr(sc, xfer); 2773 2774 return USBD_IN_PROGRESS; 2775 } 2776 2777 int 2778 uhci_device_intr_init(struct usbd_xfer *xfer) 2779 { 2780 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2781 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2782 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2783 int endpt = ed->bEndpointAddress; 2784 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2785 int len = xfer->ux_bufsize; 2786 int err; 2787 2788 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2789 2790 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2791 xfer->ux_flags, 0); 2792 2793 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2794 KASSERT(len != 0); 2795 2796 ux->ux_type = UX_INTR; 2797 ux->ux_nstd = 0; 2798 err = uhci_alloc_std_chain(sc, xfer, len, isread, 2799 &ux->ux_stdstart, &ux->ux_stdend); 2800 2801 return err; 2802 } 2803 2804 Static void 2805 uhci_device_intr_fini(struct usbd_xfer *xfer) 2806 { 2807 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2808 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2809 2810 KASSERT(ux->ux_type == UX_INTR); 2811 2812 uhci_free_stds(sc, ux); 2813 if (ux->ux_nstd) 2814 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2815 } 2816 2817 usbd_status 2818 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2819 { 2820 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2821 usbd_status err; 2822 2823 /* Insert last in queue. */ 2824 mutex_enter(&sc->sc_lock); 2825 err = usb_insert_transfer(xfer); 2826 mutex_exit(&sc->sc_lock); 2827 if (err) 2828 return err; 2829 2830 /* 2831 * Pipe isn't running (otherwise err would be USBD_INPROG), 2832 * so start it first. 2833 */ 2834 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2835 } 2836 2837 usbd_status 2838 uhci_device_intr_start(struct usbd_xfer *xfer) 2839 { 2840 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2841 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2842 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2843 uhci_soft_td_t *data, *dataend; 2844 uhci_soft_qh_t *sqh; 2845 int isread, endpt; 2846 int i; 2847 2848 if (sc->sc_dying) 2849 return USBD_IOERROR; 2850 2851 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2852 2853 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2854 xfer->ux_flags, 0); 2855 2856 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2857 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2858 2859 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2860 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2861 2862 data = ux->ux_stdstart; 2863 2864 KASSERT(ux->ux_isdone); 2865 #ifdef DIAGNOSTIC 2866 ux->ux_isdone = false; 2867 #endif 2868 2869 /* Take lock to protect nexttoggle */ 2870 mutex_enter(&sc->sc_lock); 2871 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2872 &upipe->nexttoggle, &dataend); 2873 2874 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2875 usb_syncmem(&dataend->dma, 2876 dataend->offs + offsetof(uhci_td_t, td_status), 2877 sizeof(dataend->td.td_status), 2878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2879 ux->ux_stdend = dataend; 2880 2881 #ifdef UHCI_DEBUG 2882 if (uhcidebug >= 10) { 2883 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2884 uhci_dump_tds(data); 2885 uhci_dump_qh(upipe->intr.qhs[0]); 2886 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2887 } 2888 #endif 2889 2890 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2891 for (i = 0; i < upipe->intr.npoll; i++) { 2892 sqh = upipe->intr.qhs[i]; 2893 sqh->elink = data; 2894 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2895 usb_syncmem(&sqh->dma, 2896 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2897 sizeof(sqh->qh.qh_elink), 2898 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2899 } 2900 uhci_add_intr_list(sc, ux); 2901 xfer->ux_status = USBD_IN_PROGRESS; 2902 mutex_exit(&sc->sc_lock); 2903 2904 #ifdef UHCI_DEBUG 2905 if (uhcidebug >= 10) { 2906 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2907 uhci_dump_tds(data); 2908 uhci_dump_qh(upipe->intr.qhs[0]); 2909 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2910 } 2911 #endif 2912 2913 return USBD_IN_PROGRESS; 2914 } 2915 2916 /* Abort a device control request. */ 2917 void 2918 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2919 { 2920 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2921 2922 KASSERT(mutex_owned(&sc->sc_lock)); 2923 2924 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2925 uhci_abort_xfer(xfer, USBD_CANCELLED); 2926 } 2927 2928 /* Close a device control pipe. */ 2929 void 2930 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2931 { 2932 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2933 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2934 2935 uhci_free_sqh(sc, upipe->ctrl.sqh); 2936 uhci_free_std_locked(sc, upipe->ctrl.setup); 2937 uhci_free_std_locked(sc, upipe->ctrl.stat); 2938 2939 } 2940 2941 /* Abort a device interrupt request. */ 2942 void 2943 uhci_device_intr_abort(struct usbd_xfer *xfer) 2944 { 2945 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2946 2947 KASSERT(mutex_owned(&sc->sc_lock)); 2948 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2949 2950 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2951 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2952 2953 uhci_abort_xfer(xfer, USBD_CANCELLED); 2954 } 2955 2956 /* Close a device interrupt pipe. */ 2957 void 2958 uhci_device_intr_close(struct usbd_pipe *pipe) 2959 { 2960 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2961 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2962 int i, npoll; 2963 2964 KASSERT(mutex_owned(&sc->sc_lock)); 2965 2966 /* Unlink descriptors from controller data structures. */ 2967 npoll = upipe->intr.npoll; 2968 for (i = 0; i < npoll; i++) 2969 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2970 2971 /* 2972 * We now have to wait for any activity on the physical 2973 * descriptors to stop. 2974 */ 2975 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2976 2977 for (i = 0; i < npoll; i++) 2978 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2979 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2980 } 2981 2982 int 2983 uhci_device_isoc_init(struct usbd_xfer *xfer) 2984 { 2985 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2986 2987 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2988 KASSERT(xfer->ux_nframes != 0); 2989 KASSERT(ux->ux_isdone); 2990 2991 ux->ux_type = UX_ISOC; 2992 return 0; 2993 } 2994 2995 Static void 2996 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2997 { 2998 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2999 3000 KASSERT(ux->ux_type == UX_ISOC); 3001 } 3002 3003 usbd_status 3004 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 3005 { 3006 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3007 usbd_status err __diagused; 3008 3009 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3010 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3011 3012 /* Put it on our queue, */ 3013 mutex_enter(&sc->sc_lock); 3014 err = usb_insert_transfer(xfer); 3015 mutex_exit(&sc->sc_lock); 3016 3017 KASSERT(err == USBD_NORMAL_COMPLETION); 3018 3019 /* insert into schedule, */ 3020 3021 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3022 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3023 struct isoc *isoc = &upipe->isoc; 3024 uhci_soft_td_t *std = NULL; 3025 uint32_t buf, len, status, offs; 3026 int i, next, nframes; 3027 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3028 3029 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 3030 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3031 3032 if (sc->sc_dying) 3033 return USBD_IOERROR; 3034 3035 if (xfer->ux_status == USBD_IN_PROGRESS) { 3036 /* This request has already been entered into the frame list */ 3037 printf("%s: xfer=%p in frame list\n", __func__, xfer); 3038 /* XXX */ 3039 } 3040 3041 #ifdef DIAGNOSTIC 3042 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 3043 printf("%s: overflow!\n", __func__); 3044 #endif 3045 3046 KASSERT(xfer->ux_nframes != 0); 3047 3048 mutex_enter(&sc->sc_lock); 3049 next = isoc->next; 3050 if (next == -1) { 3051 /* Not in use yet, schedule it a few frames ahead. */ 3052 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 3053 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 3054 } 3055 3056 xfer->ux_status = USBD_IN_PROGRESS; 3057 ux->ux_curframe = next; 3058 3059 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3060 offs = 0; 3061 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 3062 UHCI_TD_ACTIVE | 3063 UHCI_TD_IOS); 3064 nframes = xfer->ux_nframes; 3065 for (i = 0; i < nframes; i++) { 3066 std = isoc->stds[next]; 3067 if (++next >= UHCI_VFRAMELIST_COUNT) 3068 next = 0; 3069 len = xfer->ux_frlengths[i]; 3070 std->td.td_buffer = htole32(buf); 3071 usb_syncmem(&xfer->ux_dmabuf, offs, len, 3072 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3073 if (i == nframes - 1) 3074 status |= UHCI_TD_IOC; 3075 std->td.td_status = htole32(status); 3076 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 3077 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 3078 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3079 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3080 #ifdef UHCI_DEBUG 3081 if (uhcidebug >= 5) { 3082 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3083 DPRINTF("TD %d", i, 0, 0, 0); 3084 uhci_dump_td(std); 3085 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3086 } 3087 #endif 3088 buf += len; 3089 offs += len; 3090 } 3091 isoc->next = next; 3092 isoc->inuse += xfer->ux_nframes; 3093 3094 /* Set up interrupt info. */ 3095 ux->ux_stdstart = std; 3096 ux->ux_stdend = std; 3097 3098 KASSERT(ux->ux_isdone); 3099 #ifdef DIAGNOSTIC 3100 ux->ux_isdone = false; 3101 #endif 3102 uhci_add_intr_list(sc, ux); 3103 3104 mutex_exit(&sc->sc_lock); 3105 3106 return USBD_IN_PROGRESS; 3107 } 3108 3109 void 3110 uhci_device_isoc_abort(struct usbd_xfer *xfer) 3111 { 3112 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3113 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3114 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3115 uhci_soft_td_t **stds = upipe->isoc.stds; 3116 uhci_soft_td_t *std; 3117 int i, n, nframes, maxlen, len; 3118 3119 KASSERT(mutex_owned(&sc->sc_lock)); 3120 3121 /* Transfer is already done. */ 3122 if (xfer->ux_status != USBD_NOT_STARTED && 3123 xfer->ux_status != USBD_IN_PROGRESS) { 3124 return; 3125 } 3126 3127 /* Give xfer the requested abort code. */ 3128 xfer->ux_status = USBD_CANCELLED; 3129 3130 /* make hardware ignore it, */ 3131 nframes = xfer->ux_nframes; 3132 n = ux->ux_curframe; 3133 maxlen = 0; 3134 for (i = 0; i < nframes; i++) { 3135 std = stds[n]; 3136 usb_syncmem(&std->dma, 3137 std->offs + offsetof(uhci_td_t, td_status), 3138 sizeof(std->td.td_status), 3139 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3140 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3141 usb_syncmem(&std->dma, 3142 std->offs + offsetof(uhci_td_t, td_status), 3143 sizeof(std->td.td_status), 3144 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3145 usb_syncmem(&std->dma, 3146 std->offs + offsetof(uhci_td_t, td_token), 3147 sizeof(std->td.td_token), 3148 BUS_DMASYNC_POSTWRITE); 3149 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3150 if (len > maxlen) 3151 maxlen = len; 3152 if (++n >= UHCI_VFRAMELIST_COUNT) 3153 n = 0; 3154 } 3155 3156 /* and wait until we are sure the hardware has finished. */ 3157 delay(maxlen); 3158 3159 #ifdef DIAGNOSTIC 3160 ux->ux_isdone = true; 3161 #endif 3162 /* Remove from interrupt list. */ 3163 uhci_del_intr_list(sc, ux); 3164 3165 /* Run callback. */ 3166 usb_transfer_complete(xfer); 3167 3168 KASSERT(mutex_owned(&sc->sc_lock)); 3169 } 3170 3171 void 3172 uhci_device_isoc_close(struct usbd_pipe *pipe) 3173 { 3174 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3175 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3176 uhci_soft_td_t *std, *vstd; 3177 struct isoc *isoc; 3178 int i; 3179 3180 KASSERT(mutex_owned(&sc->sc_lock)); 3181 3182 /* 3183 * Make sure all TDs are marked as inactive. 3184 * Wait for completion. 3185 * Unschedule. 3186 * Deallocate. 3187 */ 3188 isoc = &upipe->isoc; 3189 3190 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3191 std = isoc->stds[i]; 3192 usb_syncmem(&std->dma, 3193 std->offs + offsetof(uhci_td_t, td_status), 3194 sizeof(std->td.td_status), 3195 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3196 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3197 usb_syncmem(&std->dma, 3198 std->offs + offsetof(uhci_td_t, td_status), 3199 sizeof(std->td.td_status), 3200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3201 } 3202 /* wait for completion */ 3203 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3204 3205 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3206 std = isoc->stds[i]; 3207 for (vstd = sc->sc_vframes[i].htd; 3208 vstd != NULL && vstd->link.std != std; 3209 vstd = vstd->link.std) 3210 ; 3211 if (vstd == NULL) { 3212 /*panic*/ 3213 printf("%s: %p not found\n", __func__, std); 3214 mutex_exit(&sc->sc_lock); 3215 return; 3216 } 3217 vstd->link = std->link; 3218 usb_syncmem(&std->dma, 3219 std->offs + offsetof(uhci_td_t, td_link), 3220 sizeof(std->td.td_link), 3221 BUS_DMASYNC_POSTWRITE); 3222 vstd->td.td_link = std->td.td_link; 3223 usb_syncmem(&vstd->dma, 3224 vstd->offs + offsetof(uhci_td_t, td_link), 3225 sizeof(vstd->td.td_link), 3226 BUS_DMASYNC_PREWRITE); 3227 uhci_free_std_locked(sc, std); 3228 } 3229 3230 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3231 } 3232 3233 usbd_status 3234 uhci_setup_isoc(struct usbd_pipe *pipe) 3235 { 3236 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3237 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3238 int addr = upipe->pipe.up_dev->ud_addr; 3239 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3240 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3241 uhci_soft_td_t *std, *vstd; 3242 uint32_t token; 3243 struct isoc *isoc; 3244 int i; 3245 3246 isoc = &upipe->isoc; 3247 3248 isoc->stds = kmem_alloc( 3249 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3250 if (isoc->stds == NULL) 3251 return USBD_NOMEM; 3252 3253 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3254 UHCI_TD_OUT(0, endpt, addr, 0); 3255 3256 /* Allocate the TDs and mark as inactive; */ 3257 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3258 std = uhci_alloc_std(sc); 3259 if (std == 0) 3260 goto bad; 3261 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3262 std->td.td_token = htole32(token); 3263 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3264 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3265 isoc->stds[i] = std; 3266 } 3267 3268 mutex_enter(&sc->sc_lock); 3269 3270 /* Insert TDs into schedule. */ 3271 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3272 std = isoc->stds[i]; 3273 vstd = sc->sc_vframes[i].htd; 3274 usb_syncmem(&vstd->dma, 3275 vstd->offs + offsetof(uhci_td_t, td_link), 3276 sizeof(vstd->td.td_link), 3277 BUS_DMASYNC_POSTWRITE); 3278 std->link = vstd->link; 3279 std->td.td_link = vstd->td.td_link; 3280 usb_syncmem(&std->dma, 3281 std->offs + offsetof(uhci_td_t, td_link), 3282 sizeof(std->td.td_link), 3283 BUS_DMASYNC_PREWRITE); 3284 vstd->link.std = std; 3285 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3286 usb_syncmem(&vstd->dma, 3287 vstd->offs + offsetof(uhci_td_t, td_link), 3288 sizeof(vstd->td.td_link), 3289 BUS_DMASYNC_PREWRITE); 3290 } 3291 mutex_exit(&sc->sc_lock); 3292 3293 isoc->next = -1; 3294 isoc->inuse = 0; 3295 3296 return USBD_NORMAL_COMPLETION; 3297 3298 bad: 3299 while (--i >= 0) 3300 uhci_free_std(sc, isoc->stds[i]); 3301 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3302 return USBD_NOMEM; 3303 } 3304 3305 void 3306 uhci_device_isoc_done(struct usbd_xfer *xfer) 3307 { 3308 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3309 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3310 int i, offs; 3311 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3312 3313 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3314 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3315 xfer->ux_actlen, xfer->ux_state, 0, 0); 3316 3317 #ifdef DIAGNOSTIC 3318 if (ux->ux_stdend == NULL) { 3319 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3320 #ifdef UHCI_DEBUG 3321 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3322 uhci_dump_ii(ux); 3323 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3324 #endif 3325 return; 3326 } 3327 #endif 3328 3329 /* Turn off the interrupt since it is active even if the TD is not. */ 3330 usb_syncmem(&ux->ux_stdend->dma, 3331 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3332 sizeof(ux->ux_stdend->td.td_status), 3333 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3334 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3335 usb_syncmem(&ux->ux_stdend->dma, 3336 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3337 sizeof(ux->ux_stdend->td.td_status), 3338 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3339 3340 offs = 0; 3341 for (i = 0; i < xfer->ux_nframes; i++) { 3342 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3343 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3344 offs += xfer->ux_frlengths[i]; 3345 } 3346 } 3347 3348 void 3349 uhci_device_intr_done(struct usbd_xfer *xfer) 3350 { 3351 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3352 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3353 uhci_soft_qh_t *sqh; 3354 int i, npoll; 3355 3356 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3357 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3358 3359 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3360 3361 npoll = upipe->intr.npoll; 3362 for (i = 0; i < npoll; i++) { 3363 sqh = upipe->intr.qhs[i]; 3364 sqh->elink = NULL; 3365 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3366 usb_syncmem(&sqh->dma, 3367 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3368 sizeof(sqh->qh.qh_elink), 3369 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3370 } 3371 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3372 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3373 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3374 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3375 } 3376 3377 /* Deallocate request data structures */ 3378 void 3379 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3380 { 3381 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3382 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3383 int len = UGETW(xfer->ux_request.wLength); 3384 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3385 3386 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3387 3388 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3389 3390 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3391 3392 /* XXXNH move to uhci_idone??? */ 3393 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3394 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3395 else 3396 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3397 3398 if (len) { 3399 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3400 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3401 } 3402 usb_syncmem(&upipe->ctrl.reqdma, 0, 3403 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3404 3405 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3406 } 3407 3408 /* Deallocate request data structures */ 3409 void 3410 uhci_device_bulk_done(struct usbd_xfer *xfer) 3411 { 3412 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3413 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3414 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3415 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3416 int endpt = ed->bEndpointAddress; 3417 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3418 3419 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3420 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3421 upipe); 3422 3423 KASSERT(mutex_owned(&sc->sc_lock)); 3424 3425 uhci_remove_bulk(sc, upipe->bulk.sqh); 3426 3427 if (xfer->ux_length) { 3428 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3429 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3430 } 3431 3432 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3433 } 3434 3435 /* Add interrupt QH, called with vflock. */ 3436 void 3437 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3438 { 3439 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3440 uhci_soft_qh_t *eqh; 3441 3442 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3443 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3444 3445 eqh = vf->eqh; 3446 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3447 sizeof(eqh->qh.qh_hlink), 3448 BUS_DMASYNC_POSTWRITE); 3449 sqh->hlink = eqh->hlink; 3450 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3451 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3452 sizeof(sqh->qh.qh_hlink), 3453 BUS_DMASYNC_PREWRITE); 3454 eqh->hlink = sqh; 3455 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3456 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3457 sizeof(eqh->qh.qh_hlink), 3458 BUS_DMASYNC_PREWRITE); 3459 vf->eqh = sqh; 3460 vf->bandwidth++; 3461 } 3462 3463 /* Remove interrupt QH. */ 3464 void 3465 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3466 { 3467 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3468 uhci_soft_qh_t *pqh; 3469 3470 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3471 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3472 3473 /* See comment in uhci_remove_ctrl() */ 3474 3475 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3476 sizeof(sqh->qh.qh_elink), 3477 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3478 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3479 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3480 usb_syncmem(&sqh->dma, 3481 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3482 sizeof(sqh->qh.qh_elink), 3483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3484 delay(UHCI_QH_REMOVE_DELAY); 3485 } 3486 3487 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3488 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3489 sizeof(sqh->qh.qh_hlink), 3490 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3491 pqh->hlink = sqh->hlink; 3492 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3493 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3494 sizeof(pqh->qh.qh_hlink), 3495 BUS_DMASYNC_PREWRITE); 3496 delay(UHCI_QH_REMOVE_DELAY); 3497 if (vf->eqh == sqh) 3498 vf->eqh = pqh; 3499 vf->bandwidth--; 3500 } 3501 3502 usbd_status 3503 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3504 { 3505 uhci_soft_qh_t *sqh; 3506 int i, npoll; 3507 u_int bestbw, bw, bestoffs, offs; 3508 3509 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3510 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3511 if (ival == 0) { 3512 printf("%s: 0 interval\n", __func__); 3513 return USBD_INVAL; 3514 } 3515 3516 if (ival > UHCI_VFRAMELIST_COUNT) 3517 ival = UHCI_VFRAMELIST_COUNT; 3518 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3519 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3520 3521 upipe->intr.npoll = npoll; 3522 upipe->intr.qhs = 3523 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3524 if (upipe->intr.qhs == NULL) 3525 return USBD_NOMEM; 3526 3527 /* 3528 * Figure out which offset in the schedule that has most 3529 * bandwidth left over. 3530 */ 3531 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3532 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3533 for (bw = i = 0; i < npoll; i++) 3534 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3535 if (bw < bestbw) { 3536 bestbw = bw; 3537 bestoffs = offs; 3538 } 3539 } 3540 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3541 for (i = 0; i < npoll; i++) { 3542 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3543 sqh->elink = NULL; 3544 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3545 usb_syncmem(&sqh->dma, 3546 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3547 sizeof(sqh->qh.qh_elink), 3548 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3549 sqh->pos = MOD(i * ival + bestoffs); 3550 } 3551 #undef MOD 3552 3553 mutex_enter(&sc->sc_lock); 3554 /* Enter QHs into the controller data structures. */ 3555 for (i = 0; i < npoll; i++) 3556 uhci_add_intr(sc, upipe->intr.qhs[i]); 3557 mutex_exit(&sc->sc_lock); 3558 3559 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3560 3561 return USBD_NORMAL_COMPLETION; 3562 } 3563 3564 /* Open a new pipe. */ 3565 usbd_status 3566 uhci_open(struct usbd_pipe *pipe) 3567 { 3568 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3569 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3570 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3571 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3572 usbd_status err = USBD_NOMEM; 3573 int ival; 3574 3575 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3576 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3577 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3578 3579 if (sc->sc_dying) 3580 return USBD_IOERROR; 3581 3582 upipe->aborting = 0; 3583 /* toggle state needed for bulk endpoints */ 3584 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3585 3586 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3587 switch (ed->bEndpointAddress) { 3588 case USB_CONTROL_ENDPOINT: 3589 pipe->up_methods = &roothub_ctrl_methods; 3590 break; 3591 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3592 pipe->up_methods = &uhci_root_intr_methods; 3593 break; 3594 default: 3595 return USBD_INVAL; 3596 } 3597 } else { 3598 switch (ed->bmAttributes & UE_XFERTYPE) { 3599 case UE_CONTROL: 3600 pipe->up_methods = &uhci_device_ctrl_methods; 3601 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3602 if (upipe->ctrl.sqh == NULL) 3603 goto bad; 3604 upipe->ctrl.setup = uhci_alloc_std(sc); 3605 if (upipe->ctrl.setup == NULL) { 3606 uhci_free_sqh(sc, upipe->ctrl.sqh); 3607 goto bad; 3608 } 3609 upipe->ctrl.stat = uhci_alloc_std(sc); 3610 if (upipe->ctrl.stat == NULL) { 3611 uhci_free_sqh(sc, upipe->ctrl.sqh); 3612 uhci_free_std(sc, upipe->ctrl.setup); 3613 goto bad; 3614 } 3615 err = usb_allocmem(&sc->sc_bus, 3616 sizeof(usb_device_request_t), 3617 0, &upipe->ctrl.reqdma); 3618 if (err) { 3619 uhci_free_sqh(sc, upipe->ctrl.sqh); 3620 uhci_free_std(sc, upipe->ctrl.setup); 3621 uhci_free_std(sc, upipe->ctrl.stat); 3622 goto bad; 3623 } 3624 break; 3625 case UE_INTERRUPT: 3626 pipe->up_methods = &uhci_device_intr_methods; 3627 ival = pipe->up_interval; 3628 if (ival == USBD_DEFAULT_INTERVAL) 3629 ival = ed->bInterval; 3630 return uhci_device_setintr(sc, upipe, ival); 3631 case UE_ISOCHRONOUS: 3632 pipe->up_serialise = false; 3633 pipe->up_methods = &uhci_device_isoc_methods; 3634 return uhci_setup_isoc(pipe); 3635 case UE_BULK: 3636 pipe->up_methods = &uhci_device_bulk_methods; 3637 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3638 if (upipe->bulk.sqh == NULL) 3639 goto bad; 3640 break; 3641 } 3642 } 3643 return USBD_NORMAL_COMPLETION; 3644 3645 bad: 3646 return USBD_NOMEM; 3647 } 3648 3649 /* 3650 * Data structures and routines to emulate the root hub. 3651 */ 3652 /* 3653 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3654 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3655 * should not be used by the USB subsystem. As we cannot issue a 3656 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3657 * will be enabled as part of the reset. 3658 * 3659 * On the VT83C572, the port cannot be successfully enabled until the 3660 * outstanding "port enable change" and "connection status change" 3661 * events have been reset. 3662 */ 3663 Static usbd_status 3664 uhci_portreset(uhci_softc_t *sc, int index) 3665 { 3666 int lim, port, x; 3667 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3668 3669 if (index == 1) 3670 port = UHCI_PORTSC1; 3671 else if (index == 2) 3672 port = UHCI_PORTSC2; 3673 else 3674 return USBD_IOERROR; 3675 3676 x = URWMASK(UREAD2(sc, port)); 3677 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3678 3679 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3680 3681 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3682 UREAD2(sc, port), 0, 0); 3683 3684 x = URWMASK(UREAD2(sc, port)); 3685 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3686 3687 delay(100); 3688 3689 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3690 UREAD2(sc, port), 0, 0); 3691 3692 x = URWMASK(UREAD2(sc, port)); 3693 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3694 3695 for (lim = 10; --lim > 0;) { 3696 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3697 3698 x = UREAD2(sc, port); 3699 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3700 lim, x, 0); 3701 3702 if (!(x & UHCI_PORTSC_CCS)) { 3703 /* 3704 * No device is connected (or was disconnected 3705 * during reset). Consider the port reset. 3706 * The delay must be long enough to ensure on 3707 * the initial iteration that the device 3708 * connection will have been registered. 50ms 3709 * appears to be sufficient, but 20ms is not. 3710 */ 3711 DPRINTFN(3, "uhci port %d loop %u, device detached", 3712 index, lim, 0, 0); 3713 break; 3714 } 3715 3716 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3717 /* 3718 * Port enabled changed and/or connection 3719 * status changed were set. Reset either or 3720 * both raised flags (by writing a 1 to that 3721 * bit), and wait again for state to settle. 3722 */ 3723 UWRITE2(sc, port, URWMASK(x) | 3724 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3725 continue; 3726 } 3727 3728 if (x & UHCI_PORTSC_PE) 3729 /* Port is enabled */ 3730 break; 3731 3732 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3733 } 3734 3735 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3736 UREAD2(sc, port), 0, 0); 3737 3738 if (lim <= 0) { 3739 DPRINTF("uhci port %d reset timed out", index, 3740 0, 0, 0); 3741 return USBD_TIMEOUT; 3742 } 3743 3744 sc->sc_isreset = 1; 3745 return USBD_NORMAL_COMPLETION; 3746 } 3747 3748 Static int 3749 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3750 void *buf, int buflen) 3751 { 3752 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3753 int port, x; 3754 int status, change, totlen = 0; 3755 uint16_t len, value, index; 3756 usb_port_status_t ps; 3757 usbd_status err; 3758 3759 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3760 3761 if (sc->sc_dying) 3762 return -1; 3763 3764 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3765 req->bRequest, 0, 0); 3766 3767 len = UGETW(req->wLength); 3768 value = UGETW(req->wValue); 3769 index = UGETW(req->wIndex); 3770 3771 #define C(x,y) ((x) | ((y) << 8)) 3772 switch (C(req->bRequest, req->bmRequestType)) { 3773 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3774 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3775 if (len == 0) 3776 break; 3777 switch (value) { 3778 case C(0, UDESC_DEVICE): { 3779 usb_device_descriptor_t devd; 3780 3781 totlen = min(buflen, sizeof(devd)); 3782 memcpy(&devd, buf, totlen); 3783 USETW(devd.idVendor, sc->sc_id_vendor); 3784 memcpy(buf, &devd, totlen); 3785 break; 3786 } 3787 case C(1, UDESC_STRING): 3788 #define sd ((usb_string_descriptor_t *)buf) 3789 /* Vendor */ 3790 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3791 break; 3792 case C(2, UDESC_STRING): 3793 /* Product */ 3794 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3795 break; 3796 #undef sd 3797 default: 3798 /* default from usbroothub */ 3799 return buflen; 3800 } 3801 break; 3802 3803 /* Hub requests */ 3804 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3805 break; 3806 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3807 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3808 value, 0, 0); 3809 if (index == 1) 3810 port = UHCI_PORTSC1; 3811 else if (index == 2) 3812 port = UHCI_PORTSC2; 3813 else { 3814 return -1; 3815 } 3816 switch(value) { 3817 case UHF_PORT_ENABLE: 3818 x = URWMASK(UREAD2(sc, port)); 3819 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3820 break; 3821 case UHF_PORT_SUSPEND: 3822 x = URWMASK(UREAD2(sc, port)); 3823 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3824 break; 3825 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3826 /* see USB2 spec ch. 7.1.7.7 */ 3827 usb_delay_ms(&sc->sc_bus, 20); 3828 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3829 /* 10ms resume delay must be provided by caller */ 3830 break; 3831 case UHF_PORT_RESET: 3832 x = URWMASK(UREAD2(sc, port)); 3833 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3834 break; 3835 case UHF_C_PORT_CONNECTION: 3836 x = URWMASK(UREAD2(sc, port)); 3837 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3838 break; 3839 case UHF_C_PORT_ENABLE: 3840 x = URWMASK(UREAD2(sc, port)); 3841 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3842 break; 3843 case UHF_C_PORT_OVER_CURRENT: 3844 x = URWMASK(UREAD2(sc, port)); 3845 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3846 break; 3847 case UHF_C_PORT_RESET: 3848 sc->sc_isreset = 0; 3849 break; 3850 case UHF_PORT_CONNECTION: 3851 case UHF_PORT_OVER_CURRENT: 3852 case UHF_PORT_POWER: 3853 case UHF_PORT_LOW_SPEED: 3854 case UHF_C_PORT_SUSPEND: 3855 default: 3856 return -1; 3857 } 3858 break; 3859 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3860 if (index == 1) 3861 port = UHCI_PORTSC1; 3862 else if (index == 2) 3863 port = UHCI_PORTSC2; 3864 else { 3865 return -1; 3866 } 3867 if (len > 0) { 3868 *(uint8_t *)buf = 3869 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3870 totlen = 1; 3871 } 3872 break; 3873 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3874 if (len == 0) 3875 break; 3876 if ((value & 0xff) != 0) { 3877 return -1; 3878 } 3879 usb_hub_descriptor_t hubd; 3880 3881 totlen = min(buflen, sizeof(hubd)); 3882 memcpy(&hubd, buf, totlen); 3883 hubd.bNbrPorts = 2; 3884 memcpy(buf, &hubd, totlen); 3885 break; 3886 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3887 if (len != 4) { 3888 return -1; 3889 } 3890 memset(buf, 0, len); 3891 totlen = len; 3892 break; 3893 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3894 if (index == 1) 3895 port = UHCI_PORTSC1; 3896 else if (index == 2) 3897 port = UHCI_PORTSC2; 3898 else { 3899 return -1; 3900 } 3901 if (len != 4) { 3902 return -1; 3903 } 3904 x = UREAD2(sc, port); 3905 status = change = 0; 3906 if (x & UHCI_PORTSC_CCS) 3907 status |= UPS_CURRENT_CONNECT_STATUS; 3908 if (x & UHCI_PORTSC_CSC) 3909 change |= UPS_C_CONNECT_STATUS; 3910 if (x & UHCI_PORTSC_PE) 3911 status |= UPS_PORT_ENABLED; 3912 if (x & UHCI_PORTSC_POEDC) 3913 change |= UPS_C_PORT_ENABLED; 3914 if (x & UHCI_PORTSC_OCI) 3915 status |= UPS_OVERCURRENT_INDICATOR; 3916 if (x & UHCI_PORTSC_OCIC) 3917 change |= UPS_C_OVERCURRENT_INDICATOR; 3918 if (x & UHCI_PORTSC_SUSP) 3919 status |= UPS_SUSPEND; 3920 if (x & UHCI_PORTSC_LSDA) 3921 status |= UPS_LOW_SPEED; 3922 status |= UPS_PORT_POWER; 3923 if (sc->sc_isreset) 3924 change |= UPS_C_PORT_RESET; 3925 USETW(ps.wPortStatus, status); 3926 USETW(ps.wPortChange, change); 3927 totlen = min(len, sizeof(ps)); 3928 memcpy(buf, &ps, totlen); 3929 break; 3930 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3931 return -1; 3932 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3933 break; 3934 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3935 if (index == 1) 3936 port = UHCI_PORTSC1; 3937 else if (index == 2) 3938 port = UHCI_PORTSC2; 3939 else { 3940 return -1; 3941 } 3942 switch(value) { 3943 case UHF_PORT_ENABLE: 3944 x = URWMASK(UREAD2(sc, port)); 3945 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3946 break; 3947 case UHF_PORT_SUSPEND: 3948 x = URWMASK(UREAD2(sc, port)); 3949 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3950 break; 3951 case UHF_PORT_RESET: 3952 err = uhci_portreset(sc, index); 3953 if (err != USBD_NORMAL_COMPLETION) 3954 return -1; 3955 return 0; 3956 case UHF_PORT_POWER: 3957 /* Pretend we turned on power */ 3958 return 0; 3959 case UHF_C_PORT_CONNECTION: 3960 case UHF_C_PORT_ENABLE: 3961 case UHF_C_PORT_OVER_CURRENT: 3962 case UHF_PORT_CONNECTION: 3963 case UHF_PORT_OVER_CURRENT: 3964 case UHF_PORT_LOW_SPEED: 3965 case UHF_C_PORT_SUSPEND: 3966 case UHF_C_PORT_RESET: 3967 default: 3968 return -1; 3969 } 3970 break; 3971 default: 3972 /* default from usbroothub */ 3973 DPRINTF("returning %d (usbroothub default)", 3974 buflen, 0, 0, 0); 3975 return buflen; 3976 } 3977 3978 DPRINTF("returning %d", totlen, 0, 0, 0); 3979 3980 return totlen; 3981 } 3982 3983 /* Abort a root interrupt request. */ 3984 void 3985 uhci_root_intr_abort(struct usbd_xfer *xfer) 3986 { 3987 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3988 3989 KASSERT(mutex_owned(&sc->sc_lock)); 3990 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3991 3992 callout_stop(&sc->sc_poll_handle); 3993 sc->sc_intr_xfer = NULL; 3994 3995 xfer->ux_status = USBD_CANCELLED; 3996 #ifdef DIAGNOSTIC 3997 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3998 #endif 3999 usb_transfer_complete(xfer); 4000 } 4001 4002 usbd_status 4003 uhci_root_intr_transfer(struct usbd_xfer *xfer) 4004 { 4005 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 4006 usbd_status err; 4007 4008 /* Insert last in queue. */ 4009 mutex_enter(&sc->sc_lock); 4010 err = usb_insert_transfer(xfer); 4011 mutex_exit(&sc->sc_lock); 4012 if (err) 4013 return err; 4014 4015 /* 4016 * Pipe isn't running (otherwise err would be USBD_INPROG), 4017 * start first 4018 */ 4019 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4020 } 4021 4022 /* Start a transfer on the root interrupt pipe */ 4023 usbd_status 4024 uhci_root_intr_start(struct usbd_xfer *xfer) 4025 { 4026 struct usbd_pipe *pipe = xfer->ux_pipe; 4027 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 4028 unsigned int ival; 4029 4030 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 4031 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4032 xfer->ux_flags, 0); 4033 4034 if (sc->sc_dying) 4035 return USBD_IOERROR; 4036 4037 /* XXX temporary variable needed to avoid gcc3 warning */ 4038 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 4039 sc->sc_ival = mstohz(ival); 4040 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 4041 sc->sc_intr_xfer = xfer; 4042 return USBD_IN_PROGRESS; 4043 } 4044 4045 /* Close the root interrupt pipe. */ 4046 void 4047 uhci_root_intr_close(struct usbd_pipe *pipe) 4048 { 4049 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 4050 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 4051 4052 KASSERT(mutex_owned(&sc->sc_lock)); 4053 4054 callout_stop(&sc->sc_poll_handle); 4055 sc->sc_intr_xfer = NULL; 4056 } 4057
Indexes created Tue Sep 30 20:09:53 GMT 2025