uhci.c revision 1.264.4.71
1 /* $NetBSD: uhci.c,v 1.264.4.71 2016/04/11 07:36:21 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.71 2016/04/11 07:36:21 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup; 143 uhci_soft_td_t *stat; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 uhci_soft_qh_t **qhs; 149 } intr; 150 /* Bulk pipe */ 151 struct { 152 uhci_soft_qh_t *sqh; 153 } bulk; 154 /* Isochronous pipe */ 155 struct isoc { 156 uhci_soft_td_t **stds; 157 int next, inuse; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 163 164 Static void uhci_globalreset(uhci_softc_t *); 165 Static usbd_status uhci_portreset(uhci_softc_t*, int); 166 Static void uhci_reset(uhci_softc_t *); 167 Static usbd_status uhci_run(uhci_softc_t *, int, int); 168 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 169 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 170 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 180 uhci_soft_td_t *); 181 Static usbd_status uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 182 int, int, uhci_soft_td_t **); 183 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 184 185 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, int *, uhci_soft_td_t **); 187 188 Static void uhci_poll_hub(void *); 189 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 190 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 191 ux_completeq_t *); 192 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 193 194 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 195 196 Static void uhci_timeout(void *); 197 Static void uhci_timeout_task(void *); 198 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 199 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 200 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 201 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 202 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 203 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 204 Static void uhci_add_loop(uhci_softc_t *); 205 Static void uhci_rem_loop(uhci_softc_t *); 206 207 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 208 209 Static struct usbd_xfer * 210 uhci_allocx(struct usbd_bus *, unsigned int); 211 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 212 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 213 Static int uhci_roothub_ctrl(struct usbd_bus *, 214 usb_device_request_t *, void *, int); 215 216 Static int uhci_device_ctrl_init(struct usbd_xfer *); 217 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 218 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 219 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 220 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 221 Static void uhci_device_ctrl_close(struct usbd_pipe *); 222 Static void uhci_device_ctrl_done(struct usbd_xfer *); 223 224 Static int uhci_device_intr_init(struct usbd_xfer *); 225 Static void uhci_device_intr_fini(struct usbd_xfer *); 226 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 227 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 228 Static void uhci_device_intr_abort(struct usbd_xfer *); 229 Static void uhci_device_intr_close(struct usbd_pipe *); 230 Static void uhci_device_intr_done(struct usbd_xfer *); 231 232 Static int uhci_device_bulk_init(struct usbd_xfer *); 233 Static void uhci_device_bulk_fini(struct usbd_xfer *); 234 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 235 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 236 Static void uhci_device_bulk_abort(struct usbd_xfer *); 237 Static void uhci_device_bulk_close(struct usbd_pipe *); 238 Static void uhci_device_bulk_done(struct usbd_xfer *); 239 240 Static int uhci_device_isoc_init(struct usbd_xfer *); 241 Static void uhci_device_isoc_fini(struct usbd_xfer *); 242 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 243 Static usbd_status uhci_device_isoc_start(struct usbd_xfer *); 244 Static void uhci_device_isoc_abort(struct usbd_xfer *); 245 Static void uhci_device_isoc_close(struct usbd_pipe *); 246 Static void uhci_device_isoc_done(struct usbd_xfer *); 247 248 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 249 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 250 Static void uhci_root_intr_abort(struct usbd_xfer *); 251 Static void uhci_root_intr_close(struct usbd_pipe *); 252 Static void uhci_root_intr_done(struct usbd_xfer *); 253 254 Static usbd_status uhci_open(struct usbd_pipe *); 255 Static void uhci_poll(struct usbd_bus *); 256 Static void uhci_softintr(void *); 257 258 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 259 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 260 Static usbd_status uhci_device_setintr(uhci_softc_t *, 261 struct uhci_pipe *, int); 262 263 Static void uhci_device_clear_toggle(struct usbd_pipe *); 264 Static void uhci_noop(struct usbd_pipe *); 265 266 static inline uhci_soft_qh_t * 267 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 268 269 #ifdef UHCI_DEBUG 270 Static void uhci_dump_all(uhci_softc_t *); 271 Static void uhci_dumpregs(uhci_softc_t *); 272 Static void uhci_dump_qhs(uhci_soft_qh_t *); 273 Static void uhci_dump_qh(uhci_soft_qh_t *); 274 Static void uhci_dump_tds(uhci_soft_td_t *); 275 Static void uhci_dump_td(uhci_soft_td_t *); 276 Static void uhci_dump_ii(struct uhci_xfer *); 277 void uhci_dump(void); 278 #endif 279 280 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 281 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 282 #define UWRITE1(sc, r, x) \ 283 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 284 } while (/*CONSTCOND*/0) 285 #define UWRITE2(sc, r, x) \ 286 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 287 } while (/*CONSTCOND*/0) 288 #define UWRITE4(sc, r, x) \ 289 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 290 } while (/*CONSTCOND*/0) 291 292 static __inline uint8_t 293 UREAD1(uhci_softc_t *sc, bus_size_t r) 294 { 295 296 UBARR(sc); 297 return bus_space_read_1(sc->iot, sc->ioh, r); 298 } 299 300 static __inline uint16_t 301 UREAD2(uhci_softc_t *sc, bus_size_t r) 302 { 303 304 UBARR(sc); 305 return bus_space_read_2(sc->iot, sc->ioh, r); 306 } 307 308 #ifdef UHCI_DEBUG 309 static __inline uint32_t 310 UREAD4(uhci_softc_t *sc, bus_size_t r) 311 { 312 313 UBARR(sc); 314 return bus_space_read_4(sc->iot, sc->ioh, r); 315 } 316 #endif 317 318 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 319 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 320 321 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 322 323 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 324 325 const struct usbd_bus_methods uhci_bus_methods = { 326 .ubm_open = uhci_open, 327 .ubm_softint = uhci_softintr, 328 .ubm_dopoll = uhci_poll, 329 .ubm_allocx = uhci_allocx, 330 .ubm_freex = uhci_freex, 331 .ubm_getlock = uhci_get_lock, 332 .ubm_rhctrl = uhci_roothub_ctrl, 333 }; 334 335 const struct usbd_pipe_methods uhci_root_intr_methods = { 336 .upm_transfer = uhci_root_intr_transfer, 337 .upm_start = uhci_root_intr_start, 338 .upm_abort = uhci_root_intr_abort, 339 .upm_close = uhci_root_intr_close, 340 .upm_cleartoggle = uhci_noop, 341 .upm_done = uhci_root_intr_done, 342 }; 343 344 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 345 .upm_init = uhci_device_ctrl_init, 346 .upm_fini = uhci_device_ctrl_fini, 347 .upm_transfer = uhci_device_ctrl_transfer, 348 .upm_start = uhci_device_ctrl_start, 349 .upm_abort = uhci_device_ctrl_abort, 350 .upm_close = uhci_device_ctrl_close, 351 .upm_cleartoggle = uhci_noop, 352 .upm_done = uhci_device_ctrl_done, 353 }; 354 355 const struct usbd_pipe_methods uhci_device_intr_methods = { 356 .upm_init = uhci_device_intr_init, 357 .upm_fini = uhci_device_intr_fini, 358 .upm_transfer = uhci_device_intr_transfer, 359 .upm_start = uhci_device_intr_start, 360 .upm_abort = uhci_device_intr_abort, 361 .upm_close = uhci_device_intr_close, 362 .upm_cleartoggle = uhci_device_clear_toggle, 363 .upm_done = uhci_device_intr_done, 364 }; 365 366 const struct usbd_pipe_methods uhci_device_bulk_methods = { 367 .upm_init = uhci_device_bulk_init, 368 .upm_fini = uhci_device_bulk_fini, 369 .upm_transfer = uhci_device_bulk_transfer, 370 .upm_start = uhci_device_bulk_start, 371 .upm_abort = uhci_device_bulk_abort, 372 .upm_close = uhci_device_bulk_close, 373 .upm_cleartoggle = uhci_device_clear_toggle, 374 .upm_done = uhci_device_bulk_done, 375 }; 376 377 const struct usbd_pipe_methods uhci_device_isoc_methods = { 378 .upm_init = uhci_device_isoc_init, 379 .upm_fini = uhci_device_isoc_fini, 380 .upm_transfer = uhci_device_isoc_transfer, 381 .upm_abort = uhci_device_isoc_abort, 382 .upm_close = uhci_device_isoc_close, 383 .upm_cleartoggle = uhci_noop, 384 .upm_done = uhci_device_isoc_done, 385 }; 386 387 static inline void 388 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 389 { 390 391 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 392 } 393 394 static inline void 395 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 396 { 397 398 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 399 } 400 401 static inline uhci_soft_qh_t * 402 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 403 { 404 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 405 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 406 407 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 408 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 409 usb_syncmem(&pqh->dma, 410 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 411 sizeof(pqh->qh.qh_hlink), 412 BUS_DMASYNC_POSTWRITE); 413 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 414 printf("%s: QH not found\n", __func__); 415 return NULL; 416 } 417 #endif 418 } 419 return pqh; 420 } 421 422 void 423 uhci_globalreset(uhci_softc_t *sc) 424 { 425 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 426 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 427 UHCICMD(sc, 0); /* do nothing */ 428 } 429 430 int 431 uhci_init(uhci_softc_t *sc) 432 { 433 usbd_status err; 434 int i, j; 435 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 436 uhci_soft_td_t *std; 437 438 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 439 440 #ifdef UHCI_DEBUG 441 thesc = sc; 442 443 if (uhcidebug >= 2) 444 uhci_dumpregs(sc); 445 #endif 446 447 sc->sc_suspend = PWR_RESUME; 448 449 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 450 uhci_globalreset(sc); /* reset the controller */ 451 uhci_reset(sc); 452 453 /* Allocate and initialize real frame array. */ 454 err = usb_allocmem(&sc->sc_bus, 455 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 456 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 457 if (err) 458 return err; 459 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 460 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 461 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 462 463 /* Initialise mutex early for uhci_alloc_* */ 464 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 465 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 466 467 /* 468 * Allocate a TD, inactive, that hangs from the last QH. 469 * This is to avoid a bug in the PIIX that makes it run berserk 470 * otherwise. 471 */ 472 std = uhci_alloc_std(sc); 473 if (std == NULL) 474 return ENOMEM; 475 std->link.std = NULL; 476 std->td.td_link = htole32(UHCI_PTR_T); 477 std->td.td_status = htole32(0); /* inactive */ 478 std->td.td_token = htole32(0); 479 std->td.td_buffer = htole32(0); 480 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 482 483 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 484 lsqh = uhci_alloc_sqh(sc); 485 if (lsqh == NULL) 486 goto fail1; 487 lsqh->hlink = NULL; 488 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 489 lsqh->elink = std; 490 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 491 sc->sc_last_qh = lsqh; 492 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 494 495 /* Allocate the dummy QH where bulk traffic will be queued. */ 496 bsqh = uhci_alloc_sqh(sc); 497 if (bsqh == NULL) 498 goto fail2; 499 bsqh->hlink = lsqh; 500 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 501 bsqh->elink = NULL; 502 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 503 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 504 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 506 507 /* Allocate dummy QH where high speed control traffic will be queued. */ 508 chsqh = uhci_alloc_sqh(sc); 509 if (chsqh == NULL) 510 goto fail3; 511 chsqh->hlink = bsqh; 512 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 513 chsqh->elink = NULL; 514 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 515 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 516 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 517 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 518 519 /* Allocate dummy QH where control traffic will be queued. */ 520 clsqh = uhci_alloc_sqh(sc); 521 if (clsqh == NULL) 522 goto fail4; 523 clsqh->hlink = chsqh; 524 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 525 clsqh->elink = NULL; 526 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 527 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 528 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 530 531 /* 532 * Make all (virtual) frame list pointers point to the interrupt 533 * queue heads and the interrupt queue heads at the control 534 * queue head and point the physical frame list to the virtual. 535 */ 536 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 537 std = uhci_alloc_std(sc); 538 sqh = uhci_alloc_sqh(sc); 539 if (std == NULL || sqh == NULL) 540 return USBD_NOMEM; 541 std->link.sqh = sqh; 542 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 543 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 544 std->td.td_token = htole32(0); 545 std->td.td_buffer = htole32(0); 546 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 548 sqh->hlink = clsqh; 549 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 550 sqh->elink = NULL; 551 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 552 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 553 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 554 sc->sc_vframes[i].htd = std; 555 sc->sc_vframes[i].etd = std; 556 sc->sc_vframes[i].hqh = sqh; 557 sc->sc_vframes[i].eqh = sqh; 558 for (j = i; 559 j < UHCI_FRAMELIST_COUNT; 560 j += UHCI_VFRAMELIST_COUNT) 561 sc->sc_pframes[j] = htole32(std->physaddr); 562 } 563 usb_syncmem(&sc->sc_dma, 0, 564 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 565 BUS_DMASYNC_PREWRITE); 566 567 568 TAILQ_INIT(&sc->sc_intrhead); 569 570 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 571 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 572 573 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 574 575 cv_init(&sc->sc_softwake_cv, "uhciab"); 576 577 /* Set up the bus struct. */ 578 sc->sc_bus.ub_methods = &uhci_bus_methods; 579 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 580 sc->sc_bus.ub_usedma = true; 581 582 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 583 584 DPRINTF("Enabling...", 0, 0, 0, 0); 585 586 err = uhci_run(sc, 1, 0); /* and here we go... */ 587 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 588 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 589 return err; 590 591 fail4: 592 uhci_free_sqh(sc, chsqh); 593 fail3: 594 uhci_free_sqh(sc, lsqh); 595 fail2: 596 uhci_free_sqh(sc, lsqh); 597 fail1: 598 uhci_free_std(sc, std); 599 600 return ENOMEM; 601 } 602 603 int 604 uhci_activate(device_t self, enum devact act) 605 { 606 struct uhci_softc *sc = device_private(self); 607 608 switch (act) { 609 case DVACT_DEACTIVATE: 610 sc->sc_dying = 1; 611 return 0; 612 default: 613 return EOPNOTSUPP; 614 } 615 } 616 617 void 618 uhci_childdet(device_t self, device_t child) 619 { 620 struct uhci_softc *sc = device_private(self); 621 622 KASSERT(sc->sc_child == child); 623 sc->sc_child = NULL; 624 } 625 626 int 627 uhci_detach(struct uhci_softc *sc, int flags) 628 { 629 int rv = 0; 630 631 if (sc->sc_child != NULL) 632 rv = config_detach(sc->sc_child, flags); 633 634 if (rv != 0) 635 return rv; 636 637 callout_halt(&sc->sc_poll_handle, NULL); 638 callout_destroy(&sc->sc_poll_handle); 639 640 cv_destroy(&sc->sc_softwake_cv); 641 642 mutex_destroy(&sc->sc_lock); 643 mutex_destroy(&sc->sc_intr_lock); 644 645 pool_cache_destroy(sc->sc_xferpool); 646 647 /* XXX free other data structures XXX */ 648 649 return rv; 650 } 651 652 struct usbd_xfer * 653 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 654 { 655 struct uhci_softc *sc = UHCI_BUS2SC(bus); 656 struct usbd_xfer *xfer; 657 658 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 659 if (xfer != NULL) { 660 memset(xfer, 0, sizeof(struct uhci_xfer)); 661 662 #ifdef DIAGNOSTIC 663 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 664 uxfer->ux_isdone = true; 665 xfer->ux_state = XFER_BUSY; 666 #endif 667 } 668 return xfer; 669 } 670 671 void 672 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 673 { 674 struct uhci_softc *sc = UHCI_BUS2SC(bus); 675 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 676 677 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 678 xfer->ux_state); 679 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 680 #ifdef DIAGNOSTIC 681 xfer->ux_state = XFER_FREE; 682 #endif 683 pool_cache_put(sc->sc_xferpool, xfer); 684 } 685 686 Static void 687 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 688 { 689 struct uhci_softc *sc = UHCI_BUS2SC(bus); 690 691 *lock = &sc->sc_lock; 692 } 693 694 695 /* 696 * Handle suspend/resume. 697 * 698 * We need to switch to polling mode here, because this routine is 699 * called from an interrupt context. This is all right since we 700 * are almost suspended anyway. 701 */ 702 bool 703 uhci_resume(device_t dv, const pmf_qual_t *qual) 704 { 705 uhci_softc_t *sc = device_private(dv); 706 int cmd; 707 708 mutex_spin_enter(&sc->sc_intr_lock); 709 710 cmd = UREAD2(sc, UHCI_CMD); 711 sc->sc_bus.ub_usepolling++; 712 UWRITE2(sc, UHCI_INTR, 0); 713 uhci_globalreset(sc); 714 uhci_reset(sc); 715 if (cmd & UHCI_CMD_RS) 716 uhci_run(sc, 0, 1); 717 718 /* restore saved state */ 719 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 720 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 721 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 722 723 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 724 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 725 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 726 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 727 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 728 UHCICMD(sc, UHCI_CMD_MAXP); 729 uhci_run(sc, 1, 1); /* and start traffic again */ 730 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 731 sc->sc_bus.ub_usepolling--; 732 if (sc->sc_intr_xfer != NULL) 733 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 734 sc->sc_intr_xfer); 735 #ifdef UHCI_DEBUG 736 if (uhcidebug >= 2) 737 uhci_dumpregs(sc); 738 #endif 739 740 sc->sc_suspend = PWR_RESUME; 741 mutex_spin_exit(&sc->sc_intr_lock); 742 743 return true; 744 } 745 746 bool 747 uhci_suspend(device_t dv, const pmf_qual_t *qual) 748 { 749 uhci_softc_t *sc = device_private(dv); 750 int cmd; 751 752 mutex_spin_enter(&sc->sc_intr_lock); 753 754 cmd = UREAD2(sc, UHCI_CMD); 755 756 #ifdef UHCI_DEBUG 757 if (uhcidebug >= 2) 758 uhci_dumpregs(sc); 759 #endif 760 if (sc->sc_intr_xfer != NULL) 761 callout_stop(&sc->sc_poll_handle); 762 sc->sc_suspend = PWR_SUSPEND; 763 sc->sc_bus.ub_usepolling++; 764 765 uhci_run(sc, 0, 1); /* stop the controller */ 766 cmd &= ~UHCI_CMD_RS; 767 768 /* save some state if BIOS doesn't */ 769 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 770 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 771 772 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 773 774 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 775 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 776 sc->sc_bus.ub_usepolling--; 777 778 mutex_spin_exit(&sc->sc_intr_lock); 779 780 return true; 781 } 782 783 #ifdef UHCI_DEBUG 784 Static void 785 uhci_dumpregs(uhci_softc_t *sc) 786 { 787 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 788 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 789 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 790 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 791 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 792 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 793 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 794 } 795 796 void 797 uhci_dump_td(uhci_soft_td_t *p) 798 { 799 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 800 801 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 802 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 803 804 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 805 DPRINTF(" link=0x%08x status=0x%08x " 806 "token=0x%08x buffer=0x%08x", 807 le32toh(p->td.td_link), 808 le32toh(p->td.td_status), 809 le32toh(p->td.td_token), 810 le32toh(p->td.td_buffer)); 811 812 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 813 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 814 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 815 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 816 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 817 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 818 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 819 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 820 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 821 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 822 DPRINTF("ios =%d ls =%d spd =%d", 823 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 824 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 825 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 826 DPRINTF("errcnt =%d actlen =%d pid=%02x", 827 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 828 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 829 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 830 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 831 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 832 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 833 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 834 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 835 } 836 837 void 838 uhci_dump_qh(uhci_soft_qh_t *sqh) 839 { 840 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 841 842 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 844 845 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 846 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 847 le32toh(sqh->qh.qh_elink)); 848 849 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 850 } 851 852 853 #if 1 854 void 855 uhci_dump(void) 856 { 857 uhci_dump_all(thesc); 858 } 859 #endif 860 861 void 862 uhci_dump_all(uhci_softc_t *sc) 863 { 864 uhci_dumpregs(sc); 865 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 866 uhci_dump_qhs(sc->sc_lctl_start); 867 } 868 869 870 void 871 uhci_dump_qhs(uhci_soft_qh_t *sqh) 872 { 873 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 874 875 uhci_dump_qh(sqh); 876 877 /* 878 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 879 * Traverses sideways first, then down. 880 * 881 * QH1 882 * QH2 883 * No QH 884 * TD2.1 885 * TD2.2 886 * TD1.1 887 * etc. 888 * 889 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 890 */ 891 892 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 893 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 894 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 895 uhci_dump_qhs(sqh->hlink); 896 else 897 DPRINTF("No QH", 0, 0, 0, 0); 898 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 899 900 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 901 uhci_dump_tds(sqh->elink); 902 else 903 DPRINTF("No QH", 0, 0, 0, 0); 904 } 905 906 void 907 uhci_dump_tds(uhci_soft_td_t *std) 908 { 909 uhci_soft_td_t *td; 910 int stop; 911 912 for (td = std; td != NULL; td = td->link.std) { 913 uhci_dump_td(td); 914 915 /* 916 * Check whether the link pointer in this TD marks 917 * the link pointer as end of queue. This avoids 918 * printing the free list in case the queue/TD has 919 * already been moved there (seatbelt). 920 */ 921 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 922 sizeof(td->td.td_link), 923 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 924 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 925 le32toh(td->td.td_link) == 0); 926 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 927 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 928 if (stop) 929 break; 930 } 931 } 932 933 Static void 934 uhci_dump_ii(struct uhci_xfer *ux) 935 { 936 struct usbd_pipe *pipe; 937 usb_endpoint_descriptor_t *ed; 938 struct usbd_device *dev; 939 940 if (ux == NULL) { 941 printf("ux NULL\n"); 942 return; 943 } 944 pipe = ux->ux_xfer.ux_pipe; 945 if (pipe == NULL) { 946 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 947 return; 948 } 949 if (pipe->up_endpoint == NULL) { 950 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 951 ux, ux->ux_isdone, pipe); 952 return; 953 } 954 if (pipe->up_dev == NULL) { 955 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 956 ux, ux->ux_isdone, pipe); 957 return; 958 } 959 ed = pipe->up_endpoint->ue_edesc; 960 dev = pipe->up_dev; 961 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 962 ux, ux->ux_isdone, dev, 963 UGETW(dev->ud_ddesc.idVendor), 964 UGETW(dev->ud_ddesc.idProduct), 965 dev->ud_addr, pipe, 966 ed->bEndpointAddress, ed->bmAttributes); 967 } 968 969 void uhci_dump_iis(struct uhci_softc *sc); 970 void 971 uhci_dump_iis(struct uhci_softc *sc) 972 { 973 struct uhci_xfer *ux; 974 975 printf("interrupt list:\n"); 976 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 977 uhci_dump_ii(ux); 978 } 979 980 void iidump(void); 981 void iidump(void) { uhci_dump_iis(thesc); } 982 983 #endif 984 985 /* 986 * This routine is executed periodically and simulates interrupts 987 * from the root controller interrupt pipe for port status change. 988 */ 989 void 990 uhci_poll_hub(void *addr) 991 { 992 struct usbd_xfer *xfer = addr; 993 struct usbd_pipe *pipe = xfer->ux_pipe; 994 uhci_softc_t *sc; 995 u_char *p; 996 997 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 998 999 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1000 return; /* device has detached */ 1001 sc = UHCI_PIPE2SC(pipe); 1002 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1003 1004 p = xfer->ux_buf; 1005 p[0] = 0; 1006 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<1; 1008 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<2; 1010 if (p[0] == 0) 1011 /* No change, try again in a while */ 1012 return; 1013 1014 xfer->ux_actlen = 1; 1015 xfer->ux_status = USBD_NORMAL_COMPLETION; 1016 mutex_enter(&sc->sc_lock); 1017 usb_transfer_complete(xfer); 1018 mutex_exit(&sc->sc_lock); 1019 } 1020 1021 void 1022 uhci_root_intr_done(struct usbd_xfer *xfer) 1023 { 1024 } 1025 1026 /* 1027 * Let the last QH loop back to the high speed control transfer QH. 1028 * This is what intel calls "bandwidth reclamation" and improves 1029 * USB performance a lot for some devices. 1030 * If we are already looping, just count it. 1031 */ 1032 void 1033 uhci_add_loop(uhci_softc_t *sc) 1034 { 1035 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1036 1037 #ifdef UHCI_DEBUG 1038 if (uhcinoloop) 1039 return; 1040 #endif 1041 if (++sc->sc_loops == 1) { 1042 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1043 /* Note, we don't loop back the soft pointer. */ 1044 sc->sc_last_qh->qh.qh_hlink = 1045 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1046 usb_syncmem(&sc->sc_last_qh->dma, 1047 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1048 sizeof(sc->sc_last_qh->qh.qh_hlink), 1049 BUS_DMASYNC_PREWRITE); 1050 } 1051 } 1052 1053 void 1054 uhci_rem_loop(uhci_softc_t *sc) 1055 { 1056 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1057 1058 #ifdef UHCI_DEBUG 1059 if (uhcinoloop) 1060 return; 1061 #endif 1062 if (--sc->sc_loops == 0) { 1063 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1064 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1065 usb_syncmem(&sc->sc_last_qh->dma, 1066 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1067 sizeof(sc->sc_last_qh->qh.qh_hlink), 1068 BUS_DMASYNC_PREWRITE); 1069 } 1070 } 1071 1072 /* Add high speed control QH, called with lock held. */ 1073 void 1074 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1075 { 1076 uhci_soft_qh_t *eqh; 1077 1078 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1079 1080 KASSERT(mutex_owned(&sc->sc_lock)); 1081 1082 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1083 eqh = sc->sc_hctl_end; 1084 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1085 sizeof(eqh->qh.qh_hlink), 1086 BUS_DMASYNC_POSTWRITE); 1087 sqh->hlink = eqh->hlink; 1088 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1089 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1090 BUS_DMASYNC_PREWRITE); 1091 eqh->hlink = sqh; 1092 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1093 sc->sc_hctl_end = sqh; 1094 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1095 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1096 #ifdef UHCI_CTL_LOOP 1097 uhci_add_loop(sc); 1098 #endif 1099 } 1100 1101 /* Remove high speed control QH, called with lock held. */ 1102 void 1103 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1104 { 1105 uhci_soft_qh_t *pqh; 1106 uint32_t elink; 1107 1108 KASSERT(mutex_owned(&sc->sc_lock)); 1109 1110 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1111 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1112 #ifdef UHCI_CTL_LOOP 1113 uhci_rem_loop(sc); 1114 #endif 1115 /* 1116 * The T bit should be set in the elink of the QH so that the HC 1117 * doesn't follow the pointer. This condition may fail if the 1118 * the transferred packet was short so that the QH still points 1119 * at the last used TD. 1120 * In this case we set the T bit and wait a little for the HC 1121 * to stop looking at the TD. 1122 * Note that if the TD chain is large enough, the controller 1123 * may still be looking at the chain at the end of this function. 1124 * uhci_free_std_chain() will make sure the controller stops 1125 * looking at it quickly, but until then we should not change 1126 * sqh->hlink. 1127 */ 1128 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1129 sizeof(sqh->qh.qh_elink), 1130 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1131 elink = le32toh(sqh->qh.qh_elink); 1132 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1133 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1134 if (!(elink & UHCI_PTR_T)) { 1135 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1136 usb_syncmem(&sqh->dma, 1137 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1138 sizeof(sqh->qh.qh_elink), 1139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1140 delay(UHCI_QH_REMOVE_DELAY); 1141 } 1142 1143 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1144 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1145 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1146 pqh->hlink = sqh->hlink; 1147 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1148 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1149 sizeof(pqh->qh.qh_hlink), 1150 BUS_DMASYNC_PREWRITE); 1151 delay(UHCI_QH_REMOVE_DELAY); 1152 if (sc->sc_hctl_end == sqh) 1153 sc->sc_hctl_end = pqh; 1154 } 1155 1156 /* Add low speed control QH, called with lock held. */ 1157 void 1158 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1159 { 1160 uhci_soft_qh_t *eqh; 1161 1162 KASSERT(mutex_owned(&sc->sc_lock)); 1163 1164 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1165 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1166 1167 eqh = sc->sc_lctl_end; 1168 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1169 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1170 sqh->hlink = eqh->hlink; 1171 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1172 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1173 BUS_DMASYNC_PREWRITE); 1174 eqh->hlink = sqh; 1175 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1176 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1177 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1178 sc->sc_lctl_end = sqh; 1179 } 1180 1181 /* Remove low speed control QH, called with lock held. */ 1182 void 1183 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1184 { 1185 uhci_soft_qh_t *pqh; 1186 uint32_t elink; 1187 1188 KASSERT(mutex_owned(&sc->sc_lock)); 1189 1190 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1191 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1192 1193 /* See comment in uhci_remove_hs_ctrl() */ 1194 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1195 sizeof(sqh->qh.qh_elink), 1196 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1197 elink = le32toh(sqh->qh.qh_elink); 1198 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1199 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1200 if (!(elink & UHCI_PTR_T)) { 1201 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1202 usb_syncmem(&sqh->dma, 1203 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1204 sizeof(sqh->qh.qh_elink), 1205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1206 delay(UHCI_QH_REMOVE_DELAY); 1207 } 1208 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1209 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1210 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1211 pqh->hlink = sqh->hlink; 1212 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1213 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1214 sizeof(pqh->qh.qh_hlink), 1215 BUS_DMASYNC_PREWRITE); 1216 delay(UHCI_QH_REMOVE_DELAY); 1217 if (sc->sc_lctl_end == sqh) 1218 sc->sc_lctl_end = pqh; 1219 } 1220 1221 /* Add bulk QH, called with lock held. */ 1222 void 1223 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1224 { 1225 uhci_soft_qh_t *eqh; 1226 1227 KASSERT(mutex_owned(&sc->sc_lock)); 1228 1229 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1230 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1231 1232 eqh = sc->sc_bulk_end; 1233 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1234 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1235 sqh->hlink = eqh->hlink; 1236 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1237 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1238 BUS_DMASYNC_PREWRITE); 1239 eqh->hlink = sqh; 1240 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1241 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1242 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1243 sc->sc_bulk_end = sqh; 1244 uhci_add_loop(sc); 1245 } 1246 1247 /* Remove bulk QH, called with lock held. */ 1248 void 1249 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1250 { 1251 uhci_soft_qh_t *pqh; 1252 1253 KASSERT(mutex_owned(&sc->sc_lock)); 1254 1255 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1256 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1257 1258 uhci_rem_loop(sc); 1259 /* See comment in uhci_remove_hs_ctrl() */ 1260 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1261 sizeof(sqh->qh.qh_elink), 1262 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1263 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1264 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1265 usb_syncmem(&sqh->dma, 1266 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1267 sizeof(sqh->qh.qh_elink), 1268 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269 delay(UHCI_QH_REMOVE_DELAY); 1270 } 1271 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1272 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1273 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1274 pqh->hlink = sqh->hlink; 1275 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1276 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1277 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1278 delay(UHCI_QH_REMOVE_DELAY); 1279 if (sc->sc_bulk_end == sqh) 1280 sc->sc_bulk_end = pqh; 1281 } 1282 1283 Static int uhci_intr1(uhci_softc_t *); 1284 1285 int 1286 uhci_intr(void *arg) 1287 { 1288 uhci_softc_t *sc = arg; 1289 int ret = 0; 1290 1291 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1292 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 1295 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1296 goto done; 1297 1298 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1299 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1300 goto done; 1301 } 1302 1303 ret = uhci_intr1(sc); 1304 1305 done: 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 return ret; 1308 } 1309 1310 int 1311 uhci_intr1(uhci_softc_t *sc) 1312 { 1313 int status; 1314 int ack; 1315 1316 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1317 1318 #ifdef UHCI_DEBUG 1319 if (uhcidebug >= 15) { 1320 DPRINTF("sc %p", sc, 0, 0, 0); 1321 uhci_dumpregs(sc); 1322 } 1323 #endif 1324 1325 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1326 1327 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1328 /* Check if the interrupt was for us. */ 1329 if (status == 0) 1330 return 0; 1331 1332 if (sc->sc_suspend != PWR_RESUME) { 1333 #ifdef DIAGNOSTIC 1334 printf("%s: interrupt while not operating ignored\n", 1335 device_xname(sc->sc_dev)); 1336 #endif 1337 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1338 return 0; 1339 } 1340 1341 ack = 0; 1342 if (status & UHCI_STS_USBINT) 1343 ack |= UHCI_STS_USBINT; 1344 if (status & UHCI_STS_USBEI) 1345 ack |= UHCI_STS_USBEI; 1346 if (status & UHCI_STS_RD) { 1347 ack |= UHCI_STS_RD; 1348 #ifdef UHCI_DEBUG 1349 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1350 #endif 1351 } 1352 if (status & UHCI_STS_HSE) { 1353 ack |= UHCI_STS_HSE; 1354 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1355 } 1356 if (status & UHCI_STS_HCPE) { 1357 ack |= UHCI_STS_HCPE; 1358 printf("%s: host controller process error\n", 1359 device_xname(sc->sc_dev)); 1360 } 1361 1362 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1363 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1364 /* no acknowledge needed */ 1365 if (!sc->sc_dying) { 1366 printf("%s: host controller halted\n", 1367 device_xname(sc->sc_dev)); 1368 #ifdef UHCI_DEBUG 1369 uhci_dump_all(sc); 1370 #endif 1371 } 1372 sc->sc_dying = 1; 1373 } 1374 1375 if (!ack) 1376 return 0; /* nothing to acknowledge */ 1377 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1378 1379 usb_schedsoftintr(&sc->sc_bus); 1380 1381 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1382 1383 return 1; 1384 } 1385 1386 void 1387 uhci_softintr(void *v) 1388 { 1389 struct usbd_bus *bus = v; 1390 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1391 struct uhci_xfer *ux, *nextux; 1392 ux_completeq_t cq; 1393 1394 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1395 DPRINTF("sc %p", sc, 0, 0, 0); 1396 1397 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1398 1399 TAILQ_INIT(&cq); 1400 /* 1401 * Interrupts on UHCI really suck. When the host controller 1402 * interrupts because a transfer is completed there is no 1403 * way of knowing which transfer it was. You can scan down 1404 * the TDs and QHs of the previous frame to limit the search, 1405 * but that assumes that the interrupt was not delayed by more 1406 * than 1 ms, which may not always be true (e.g. after debug 1407 * output on a slow console). 1408 * We scan all interrupt descriptors to see if any have 1409 * completed. 1410 */ 1411 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1412 uhci_check_intr(sc, ux, &cq); 1413 } 1414 1415 /* 1416 * We abuse ux_list for the interrupt and complete lists and 1417 * interrupt transfers will get re-added here so use 1418 * the _SAFE version of TAILQ_FOREACH. 1419 */ 1420 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1421 DPRINTF("ux %p", ux, 0, 0, 0); 1422 usb_transfer_complete(&ux->ux_xfer); 1423 } 1424 1425 if (sc->sc_softwake) { 1426 sc->sc_softwake = 0; 1427 cv_broadcast(&sc->sc_softwake_cv); 1428 } 1429 } 1430 1431 /* Check for an interrupt. */ 1432 void 1433 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1434 { 1435 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1436 uint32_t status; 1437 1438 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1439 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1440 1441 KASSERT(ux != NULL); 1442 1443 struct usbd_xfer *xfer = &ux->ux_xfer; 1444 if (xfer->ux_status == USBD_CANCELLED || 1445 xfer->ux_status == USBD_TIMEOUT) { 1446 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1447 return; 1448 } 1449 1450 switch (ux->ux_type) { 1451 case UX_CTRL: 1452 fstd = ux->ux_setup; 1453 lstd = ux->ux_stat; 1454 break; 1455 case UX_BULK: 1456 case UX_INTR: 1457 case UX_ISOC: 1458 fstd = ux->ux_stdstart; 1459 lstd = ux->ux_stdend; 1460 break; 1461 default: 1462 KASSERT(false); 1463 break; 1464 } 1465 if (fstd == NULL) 1466 return; 1467 1468 KASSERT(lstd != NULL); 1469 1470 usb_syncmem(&lstd->dma, 1471 lstd->offs + offsetof(uhci_td_t, td_status), 1472 sizeof(lstd->td.td_status), 1473 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1474 status = le32toh(lstd->td.td_status); 1475 usb_syncmem(&lstd->dma, 1476 lstd->offs + offsetof(uhci_td_t, td_status), 1477 sizeof(lstd->td.td_status), 1478 BUS_DMASYNC_PREREAD); 1479 1480 /* If the last TD is not marked active we can complete */ 1481 if (!(status & UHCI_TD_ACTIVE)) { 1482 done: 1483 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1484 1485 callout_stop(&xfer->ux_callout); 1486 uhci_idone(ux, cqp); 1487 return; 1488 } 1489 1490 /* 1491 * If the last TD is still active we need to check whether there 1492 * is an error somewhere in the middle, or whether there was a 1493 * short packet (SPD and not ACTIVE). 1494 */ 1495 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1496 for (std = fstd; std != lstd; std = std->link.std) { 1497 usb_syncmem(&std->dma, 1498 std->offs + offsetof(uhci_td_t, td_status), 1499 sizeof(std->td.td_status), 1500 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1501 status = le32toh(std->td.td_status); 1502 usb_syncmem(&std->dma, 1503 std->offs + offsetof(uhci_td_t, td_status), 1504 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1505 1506 /* If there's an active TD the xfer isn't done. */ 1507 if (status & UHCI_TD_ACTIVE) { 1508 DPRINTFN(12, "ux=%p std=%p still active", 1509 ux, std, 0, 0); 1510 return; 1511 } 1512 1513 /* Any kind of error makes the xfer done. */ 1514 if (status & UHCI_TD_STALLED) 1515 goto done; 1516 1517 /* 1518 * If the data phase of a control transfer is short, we need 1519 * to complete the status stage 1520 */ 1521 1522 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1523 struct uhci_pipe *upipe = 1524 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1525 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1526 uhci_soft_td_t *stat = upipe->ctrl.stat; 1527 1528 DPRINTFN(12, "ux=%p std=%p control status" 1529 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1530 1531 sqh->qh.qh_elink = 1532 htole32(stat->physaddr | UHCI_PTR_TD); 1533 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1534 BUS_DMASYNC_PREWRITE); 1535 break; 1536 } 1537 1538 /* We want short packets, and it is short: it's done */ 1539 usb_syncmem(&std->dma, 1540 std->offs + offsetof(uhci_td_t, td_token), 1541 sizeof(std->td.td_token), 1542 BUS_DMASYNC_POSTWRITE); 1543 1544 if ((status & UHCI_TD_SPD) && 1545 UHCI_TD_GET_ACTLEN(status) < 1546 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1547 goto done; 1548 } 1549 } 1550 } 1551 1552 /* Called with USB lock held. */ 1553 void 1554 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1555 { 1556 struct usbd_xfer *xfer = &ux->ux_xfer; 1557 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1558 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1559 uhci_soft_td_t *std; 1560 uint32_t status = 0, nstatus; 1561 int actlen; 1562 1563 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1564 1565 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1566 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1567 1568 #ifdef DIAGNOSTIC 1569 #ifdef UHCI_DEBUG 1570 if (ux->ux_isdone) { 1571 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1572 uhci_dump_ii(ux); 1573 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1574 } 1575 #endif 1576 KASSERT(!ux->ux_isdone); 1577 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1578 ux->ux_type, xfer->ux_status); 1579 ux->ux_isdone = true; 1580 #endif 1581 1582 if (xfer->ux_nframes != 0) { 1583 /* Isoc transfer, do things differently. */ 1584 uhci_soft_td_t **stds = upipe->isoc.stds; 1585 int i, n, nframes, len; 1586 1587 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1588 1589 nframes = xfer->ux_nframes; 1590 actlen = 0; 1591 n = ux->ux_curframe; 1592 for (i = 0; i < nframes; i++) { 1593 std = stds[n]; 1594 #ifdef UHCI_DEBUG 1595 if (uhcidebug >= 5) { 1596 DPRINTF("isoc TD %d", i, 0, 0, 0); 1597 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1598 uhci_dump_td(std); 1599 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1600 } 1601 #endif 1602 if (++n >= UHCI_VFRAMELIST_COUNT) 1603 n = 0; 1604 usb_syncmem(&std->dma, 1605 std->offs + offsetof(uhci_td_t, td_status), 1606 sizeof(std->td.td_status), 1607 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1608 status = le32toh(std->td.td_status); 1609 len = UHCI_TD_GET_ACTLEN(status); 1610 xfer->ux_frlengths[i] = len; 1611 actlen += len; 1612 } 1613 upipe->isoc.inuse -= nframes; 1614 xfer->ux_actlen = actlen; 1615 xfer->ux_status = USBD_NORMAL_COMPLETION; 1616 goto end; 1617 } 1618 1619 #ifdef UHCI_DEBUG 1620 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1621 if (uhcidebug >= 10) { 1622 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1623 uhci_dump_tds(ux->ux_stdstart); 1624 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1625 } 1626 #endif 1627 1628 /* The transfer is done, compute actual length and status. */ 1629 actlen = 0; 1630 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1631 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1632 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1633 nstatus = le32toh(std->td.td_status); 1634 if (nstatus & UHCI_TD_ACTIVE) 1635 break; 1636 1637 status = nstatus; 1638 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1639 UHCI_TD_PID_SETUP) 1640 actlen += UHCI_TD_GET_ACTLEN(status); 1641 else { 1642 /* 1643 * UHCI will report CRCTO in addition to a STALL or NAK 1644 * for a SETUP transaction. See section 3.2.2, "TD 1645 * CONTROL AND STATUS". 1646 */ 1647 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1648 status &= ~UHCI_TD_CRCTO; 1649 } 1650 } 1651 /* If there are left over TDs we need to update the toggle. */ 1652 if (std != NULL) 1653 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1654 1655 status &= UHCI_TD_ERROR; 1656 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1657 xfer->ux_actlen = actlen; 1658 if (status != 0) { 1659 1660 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1661 "error, addr=%d, endpt=0x%02x", 1662 xfer->ux_pipe->up_dev->ud_addr, 1663 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1664 0, 0); 1665 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1666 "bitstuff=%d crcto =%d nak =%d babble =%d", 1667 !!(status & UHCI_TD_BITSTUFF), 1668 !!(status & UHCI_TD_CRCTO), 1669 !!(status & UHCI_TD_NAK), 1670 !!(status & UHCI_TD_BABBLE)); 1671 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1672 "dbuffer =%d stalled =%d active =%d", 1673 !!(status & UHCI_TD_DBUFFER), 1674 !!(status & UHCI_TD_STALLED), 1675 !!(status & UHCI_TD_ACTIVE), 1676 0); 1677 1678 if (status == UHCI_TD_STALLED) 1679 xfer->ux_status = USBD_STALLED; 1680 else 1681 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1682 } else { 1683 xfer->ux_status = USBD_NORMAL_COMPLETION; 1684 } 1685 1686 end: 1687 uhci_del_intr_list(sc, ux); 1688 if (cqp) 1689 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1690 1691 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1692 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1693 } 1694 1695 /* 1696 * Called when a request does not complete. 1697 */ 1698 void 1699 uhci_timeout(void *addr) 1700 { 1701 struct usbd_xfer *xfer = addr; 1702 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1703 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1704 1705 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1706 1707 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1708 1709 if (sc->sc_dying) { 1710 mutex_enter(&sc->sc_lock); 1711 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1712 mutex_exit(&sc->sc_lock); 1713 return; 1714 } 1715 1716 /* Execute the abort in a process context. */ 1717 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1718 USB_TASKQ_MPSAFE); 1719 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1720 USB_TASKQ_HC); 1721 } 1722 1723 void 1724 uhci_timeout_task(void *addr) 1725 { 1726 struct usbd_xfer *xfer = addr; 1727 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1728 1729 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1730 1731 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1732 1733 mutex_enter(&sc->sc_lock); 1734 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1735 mutex_exit(&sc->sc_lock); 1736 } 1737 1738 /* 1739 * Wait here until controller claims to have an interrupt. 1740 * Then call uhci_intr and return. Use timeout to avoid waiting 1741 * too long. 1742 * Only used during boot when interrupts are not enabled yet. 1743 */ 1744 void 1745 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1746 { 1747 int timo = xfer->ux_timeout; 1748 struct uhci_xfer *ux; 1749 1750 mutex_enter(&sc->sc_lock); 1751 1752 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1753 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1754 1755 xfer->ux_status = USBD_IN_PROGRESS; 1756 for (; timo >= 0; timo--) { 1757 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1758 DPRINTFN(20, "0x%04x", 1759 UREAD2(sc, UHCI_STS), 0, 0, 0); 1760 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1761 mutex_spin_enter(&sc->sc_intr_lock); 1762 uhci_intr1(sc); 1763 mutex_spin_exit(&sc->sc_intr_lock); 1764 if (xfer->ux_status != USBD_IN_PROGRESS) 1765 goto done; 1766 } 1767 } 1768 1769 /* Timeout */ 1770 DPRINTF("timeout", 0, 0, 0, 0); 1771 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 1772 if (&ux->ux_xfer == xfer) 1773 break; 1774 1775 KASSERT(ux != NULL); 1776 1777 uhci_idone(ux, NULL); 1778 usb_transfer_complete(&ux->ux_xfer); 1779 1780 done: 1781 mutex_exit(&sc->sc_lock); 1782 } 1783 1784 void 1785 uhci_poll(struct usbd_bus *bus) 1786 { 1787 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1788 1789 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1790 mutex_spin_enter(&sc->sc_intr_lock); 1791 uhci_intr1(sc); 1792 mutex_spin_exit(&sc->sc_intr_lock); 1793 } 1794 } 1795 1796 void 1797 uhci_reset(uhci_softc_t *sc) 1798 { 1799 int n; 1800 1801 UHCICMD(sc, UHCI_CMD_HCRESET); 1802 /* The reset bit goes low when the controller is done. */ 1803 for (n = 0; n < UHCI_RESET_TIMEOUT && 1804 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1805 usb_delay_ms(&sc->sc_bus, 1); 1806 if (n >= UHCI_RESET_TIMEOUT) 1807 printf("%s: controller did not reset\n", 1808 device_xname(sc->sc_dev)); 1809 } 1810 1811 usbd_status 1812 uhci_run(uhci_softc_t *sc, int run, int locked) 1813 { 1814 int n, running; 1815 uint16_t cmd; 1816 1817 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1818 1819 run = run != 0; 1820 if (!locked) 1821 mutex_spin_enter(&sc->sc_intr_lock); 1822 1823 DPRINTF("setting run=%d", run, 0, 0, 0); 1824 cmd = UREAD2(sc, UHCI_CMD); 1825 if (run) 1826 cmd |= UHCI_CMD_RS; 1827 else 1828 cmd &= ~UHCI_CMD_RS; 1829 UHCICMD(sc, cmd); 1830 for (n = 0; n < 10; n++) { 1831 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1832 /* return when we've entered the state we want */ 1833 if (run == running) { 1834 if (!locked) 1835 mutex_spin_exit(&sc->sc_intr_lock); 1836 DPRINTF("done cmd=0x%x sts=0x%x", 1837 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1838 return USBD_NORMAL_COMPLETION; 1839 } 1840 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1841 } 1842 if (!locked) 1843 mutex_spin_exit(&sc->sc_intr_lock); 1844 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1845 run ? "start" : "stop"); 1846 return USBD_IOERROR; 1847 } 1848 1849 /* 1850 * Memory management routines. 1851 * uhci_alloc_std allocates TDs 1852 * uhci_alloc_sqh allocates QHs 1853 * These two routines do their own free list management, 1854 * partly for speed, partly because allocating DMAable memory 1855 * has page size granularity so much memory would be wasted if 1856 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1857 */ 1858 1859 uhci_soft_td_t * 1860 uhci_alloc_std(uhci_softc_t *sc) 1861 { 1862 uhci_soft_td_t *std; 1863 usbd_status err; 1864 int i, offs; 1865 usb_dma_t dma; 1866 1867 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1868 1869 mutex_enter(&sc->sc_lock); 1870 if (sc->sc_freetds == NULL) { 1871 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1872 mutex_exit(&sc->sc_lock); 1873 1874 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1875 UHCI_TD_ALIGN, &dma); 1876 if (err) 1877 return NULL; 1878 1879 mutex_enter(&sc->sc_lock); 1880 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1881 offs = i * UHCI_STD_SIZE; 1882 std = KERNADDR(&dma, offs); 1883 std->physaddr = DMAADDR(&dma, offs); 1884 std->dma = dma; 1885 std->offs = offs; 1886 std->link.std = sc->sc_freetds; 1887 sc->sc_freetds = std; 1888 } 1889 } 1890 std = sc->sc_freetds; 1891 sc->sc_freetds = std->link.std; 1892 mutex_exit(&sc->sc_lock); 1893 1894 memset(&std->td, 0, sizeof(uhci_td_t)); 1895 1896 return std; 1897 } 1898 1899 #define TD_IS_FREE 0x12345678 1900 1901 void 1902 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1903 { 1904 KASSERT(mutex_owned(&sc->sc_lock)); 1905 1906 #ifdef DIAGNOSTIC 1907 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1908 printf("%s: freeing free TD %p\n", __func__, std); 1909 return; 1910 } 1911 std->td.td_token = htole32(TD_IS_FREE); 1912 #endif 1913 1914 std->link.std = sc->sc_freetds; 1915 sc->sc_freetds = std; 1916 } 1917 1918 void 1919 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1920 { 1921 mutex_enter(&sc->sc_lock); 1922 uhci_free_std_locked(sc, std); 1923 mutex_exit(&sc->sc_lock); 1924 } 1925 1926 uhci_soft_qh_t * 1927 uhci_alloc_sqh(uhci_softc_t *sc) 1928 { 1929 uhci_soft_qh_t *sqh; 1930 usbd_status err; 1931 int i, offs; 1932 usb_dma_t dma; 1933 1934 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1935 1936 mutex_enter(&sc->sc_lock); 1937 if (sc->sc_freeqhs == NULL) { 1938 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1939 mutex_exit(&sc->sc_lock); 1940 1941 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1942 UHCI_QH_ALIGN, &dma); 1943 if (err) 1944 return NULL; 1945 1946 mutex_enter(&sc->sc_lock); 1947 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1948 offs = i * UHCI_SQH_SIZE; 1949 sqh = KERNADDR(&dma, offs); 1950 sqh->physaddr = DMAADDR(&dma, offs); 1951 sqh->dma = dma; 1952 sqh->offs = offs; 1953 sqh->hlink = sc->sc_freeqhs; 1954 sc->sc_freeqhs = sqh; 1955 } 1956 } 1957 sqh = sc->sc_freeqhs; 1958 sc->sc_freeqhs = sqh->hlink; 1959 mutex_exit(&sc->sc_lock); 1960 1961 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1962 1963 return sqh; 1964 } 1965 1966 void 1967 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1968 { 1969 KASSERT(mutex_owned(&sc->sc_lock)); 1970 1971 sqh->hlink = sc->sc_freeqhs; 1972 sc->sc_freeqhs = sqh; 1973 } 1974 1975 void 1976 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1977 uhci_soft_td_t *stdend) 1978 { 1979 uhci_soft_td_t *p; 1980 uint32_t td_link; 1981 1982 /* 1983 * to avoid race condition with the controller which may be looking 1984 * at this chain, we need to first invalidate all links, and 1985 * then wait for the controller to move to another queue 1986 */ 1987 for (p = std; p != stdend; p = p->link.std) { 1988 usb_syncmem(&p->dma, 1989 p->offs + offsetof(uhci_td_t, td_link), 1990 sizeof(p->td.td_link), 1991 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1992 td_link = le32toh(p->td.td_link); 1993 usb_syncmem(&p->dma, 1994 p->offs + offsetof(uhci_td_t, td_link), 1995 sizeof(p->td.td_link), 1996 BUS_DMASYNC_PREREAD); 1997 if ((td_link & UHCI_PTR_T) == 0) { 1998 p->td.td_link = htole32(UHCI_PTR_T); 1999 usb_syncmem(&p->dma, 2000 p->offs + offsetof(uhci_td_t, td_link), 2001 sizeof(p->td.td_link), 2002 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2003 } 2004 } 2005 delay(UHCI_QH_REMOVE_DELAY); 2006 2007 for (; std != stdend; std = p) { 2008 p = std->link.std; 2009 uhci_free_std(sc, std); 2010 } 2011 } 2012 2013 usbd_status 2014 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len, 2015 int rd, uhci_soft_td_t **sp) 2016 { 2017 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2018 uint16_t flags = xfer->ux_flags; 2019 uhci_soft_td_t *p; 2020 2021 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2022 2023 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 2024 2025 ASSERT_SLEEPABLE(); 2026 KASSERT(sp); 2027 2028 int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2029 if (maxp == 0) { 2030 printf("%s: maxp=0\n", __func__); 2031 return USBD_INVAL; 2032 } 2033 size_t ntd = (len + maxp - 1) / maxp; 2034 if (!rd && (flags & USBD_FORCE_SHORT_XFER)) { 2035 ntd++; 2036 } 2037 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 2038 2039 uxfer->ux_stds = NULL; 2040 uxfer->ux_nstd = ntd; 2041 p = NULL; 2042 if (ntd == 0) { 2043 *sp = NULL; 2044 DPRINTF("ntd=0", 0, 0, 0, 0); 2045 return USBD_NORMAL_COMPLETION; 2046 } 2047 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2048 KM_SLEEP); 2049 2050 ntd--; 2051 for (int i = ntd; i >= 0; i--) { 2052 p = uhci_alloc_std(sc); 2053 if (p == NULL) { 2054 uhci_free_stds(sc, uxfer); 2055 return USBD_NOMEM; 2056 } 2057 uxfer->ux_stds[i] = p; 2058 } 2059 2060 *sp = uxfer->ux_stds[0]; 2061 2062 return USBD_NORMAL_COMPLETION; 2063 } 2064 2065 Static void 2066 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2067 { 2068 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2069 2070 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2071 2072 mutex_enter(&sc->sc_lock); 2073 for (size_t i = 0; i < ux->ux_nstd; i++) { 2074 uhci_soft_td_t *std = ux->ux_stds[i]; 2075 #ifdef DIAGNOSTIC 2076 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2077 printf("%s: freeing free TD %p\n", __func__, std); 2078 return; 2079 } 2080 std->td.td_token = htole32(TD_IS_FREE); 2081 #endif 2082 ux->ux_stds[i]->link.std = sc->sc_freetds; 2083 sc->sc_freetds = std; 2084 } 2085 mutex_exit(&sc->sc_lock); 2086 } 2087 2088 2089 Static void 2090 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2091 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2092 { 2093 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2094 struct usbd_pipe *pipe = xfer->ux_pipe; 2095 usb_dma_t *dma = &xfer->ux_dmabuf; 2096 uint16_t flags = xfer->ux_flags; 2097 uhci_soft_td_t *std, *prev; 2098 int len = length; 2099 int tog = *toggle; 2100 int maxp; 2101 uint32_t status; 2102 size_t i; 2103 2104 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2105 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2106 len, isread, *toggle); 2107 2108 KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2109 2110 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2111 KASSERT(maxp != 0); 2112 2113 int addr = xfer->ux_pipe->up_dev->ud_addr; 2114 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2115 2116 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2117 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2118 status |= UHCI_TD_LS; 2119 if (flags & USBD_SHORT_XFER_OK) 2120 status |= UHCI_TD_SPD; 2121 usb_syncmem(dma, 0, len, 2122 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2123 std = prev = NULL; 2124 for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) { 2125 int l = len; 2126 std = uxfer->ux_stds[i]; 2127 if (l > maxp) 2128 l = maxp; 2129 2130 if (prev) { 2131 prev->link.std = std; 2132 prev->td.td_link = htole32( 2133 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2134 ); 2135 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2136 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2137 } 2138 2139 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2140 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2141 2142 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2143 std->td.td_status = htole32(status); 2144 std->td.td_token = htole32( 2145 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2146 UHCI_TD_SET_DEVADDR(addr) | 2147 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2148 UHCI_TD_SET_DT(tog) | 2149 UHCI_TD_SET_MAXLEN(l) 2150 ); 2151 std->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2152 2153 std->link.std = NULL; 2154 2155 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2156 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2157 tog ^= 1; 2158 2159 len -= l; 2160 } 2161 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2162 xfer, length, len, maxp, uxfer->ux_nstd, i); 2163 2164 if (!isread && 2165 (flags & USBD_FORCE_SHORT_XFER) && 2166 length % maxp == 0) { 2167 /* Force a 0 length transfer at the end. */ 2168 KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i, 2169 uxfer->ux_nstd); 2170 std = uxfer->ux_stds[i++]; 2171 2172 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2173 std->td.td_status = htole32(status); 2174 std->td.td_token = htole32( 2175 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2176 UHCI_TD_SET_DEVADDR(addr) | 2177 UHCI_TD_SET_PID(UHCI_TD_PID_OUT) | 2178 UHCI_TD_SET_DT(tog) | 2179 UHCI_TD_SET_MAXLEN(0) 2180 ); 2181 std->td.td_buffer = 0; 2182 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2184 2185 std->link.std = NULL; 2186 if (prev) { 2187 prev->link.std = std; 2188 prev->td.td_link = htole32( 2189 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2190 ); 2191 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2192 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2193 } 2194 tog ^= 1; 2195 } 2196 *lstd = std; 2197 *toggle = tog; 2198 } 2199 2200 void 2201 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2202 { 2203 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2204 upipe->nexttoggle = 0; 2205 } 2206 2207 void 2208 uhci_noop(struct usbd_pipe *pipe) 2209 { 2210 } 2211 2212 int 2213 uhci_device_bulk_init(struct usbd_xfer *xfer) 2214 { 2215 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2216 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2217 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2218 int endpt = ed->bEndpointAddress; 2219 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2220 int len = xfer->ux_bufsize; 2221 int err = 0; 2222 2223 2224 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2225 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2226 2227 if (sc->sc_dying) 2228 return USBD_IOERROR; 2229 2230 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2231 2232 uxfer->ux_type = UX_BULK; 2233 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart); 2234 if (err) 2235 return err; 2236 2237 #ifdef UHCI_DEBUG 2238 if (uhcidebug >= 10) { 2239 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2240 uhci_dump_tds(uxfer->ux_stdstart); 2241 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2242 } 2243 #endif 2244 2245 return 0; 2246 } 2247 2248 Static void 2249 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2250 { 2251 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2252 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2253 2254 KASSERT(ux->ux_type == UX_BULK); 2255 2256 uhci_free_stds(sc, ux); 2257 if (ux->ux_nstd) 2258 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2259 } 2260 2261 usbd_status 2262 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2263 { 2264 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2265 usbd_status err; 2266 2267 /* Insert last in queue. */ 2268 mutex_enter(&sc->sc_lock); 2269 err = usb_insert_transfer(xfer); 2270 mutex_exit(&sc->sc_lock); 2271 if (err) 2272 return err; 2273 2274 /* 2275 * Pipe isn't running (otherwise err would be USBD_INPROG), 2276 * so start it first. 2277 */ 2278 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2279 } 2280 2281 usbd_status 2282 uhci_device_bulk_start(struct usbd_xfer *xfer) 2283 { 2284 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2285 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2286 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2287 uhci_soft_td_t *data, *dataend; 2288 uhci_soft_qh_t *sqh; 2289 int len; 2290 int endpt; 2291 int isread; 2292 2293 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2294 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2295 xfer->ux_flags, 0); 2296 2297 if (sc->sc_dying) 2298 return USBD_IOERROR; 2299 2300 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2301 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2302 2303 len = xfer->ux_length; 2304 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2305 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2306 sqh = upipe->bulk.sqh; 2307 2308 /* Take lock here to protect nexttoggle */ 2309 mutex_enter(&sc->sc_lock); 2310 2311 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2312 &dataend); 2313 2314 data = ux->ux_stdstart; 2315 ux->ux_stdend = dataend; 2316 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2317 usb_syncmem(&dataend->dma, 2318 dataend->offs + offsetof(uhci_td_t, td_status), 2319 sizeof(dataend->td.td_status), 2320 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2321 2322 #ifdef UHCI_DEBUG 2323 if (uhcidebug >= 10) { 2324 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2325 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2326 uhci_dump_tds(data); 2327 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2328 } 2329 #endif 2330 2331 KASSERT(ux->ux_isdone); 2332 #ifdef DIAGNOSTIC 2333 ux->ux_isdone = false; 2334 #endif 2335 2336 sqh->elink = data; 2337 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2338 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2339 2340 uhci_add_bulk(sc, sqh); 2341 uhci_add_intr_list(sc, ux); 2342 2343 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2344 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2345 uhci_timeout, xfer); 2346 } 2347 xfer->ux_status = USBD_IN_PROGRESS; 2348 mutex_exit(&sc->sc_lock); 2349 2350 if (sc->sc_bus.ub_usepolling) 2351 uhci_waitintr(sc, xfer); 2352 2353 return USBD_IN_PROGRESS; 2354 } 2355 2356 /* Abort a device bulk request. */ 2357 void 2358 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2359 { 2360 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2361 2362 KASSERT(mutex_owned(&sc->sc_lock)); 2363 2364 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2365 2366 uhci_abort_xfer(xfer, USBD_CANCELLED); 2367 } 2368 2369 /* 2370 * Abort a device request. 2371 * If this routine is called at splusb() it guarantees that the request 2372 * will be removed from the hardware scheduling and that the callback 2373 * for it will be called with USBD_CANCELLED status. 2374 * It's impossible to guarantee that the requested transfer will not 2375 * have happened since the hardware runs concurrently. 2376 * If the transaction has already happened we rely on the ordinary 2377 * interrupt processing to process it. 2378 * XXX This is most probably wrong. 2379 * XXXMRG this doesn't make sense anymore. 2380 */ 2381 void 2382 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2383 { 2384 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2385 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2386 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2387 uhci_soft_td_t *std; 2388 int wake; 2389 2390 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2391 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2392 2393 KASSERT(mutex_owned(&sc->sc_lock)); 2394 ASSERT_SLEEPABLE(); 2395 2396 if (sc->sc_dying) { 2397 /* If we're dying, just do the software part. */ 2398 xfer->ux_status = status; /* make software ignore it */ 2399 callout_stop(&xfer->ux_callout); 2400 usb_transfer_complete(xfer); 2401 return; 2402 } 2403 2404 /* 2405 * If an abort is already in progress then just wait for it to 2406 * complete and return. 2407 */ 2408 if (xfer->ux_hcflags & UXFER_ABORTING) { 2409 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2410 #ifdef DIAGNOSTIC 2411 if (status == USBD_TIMEOUT) 2412 printf("%s: TIMEOUT while aborting\n", __func__); 2413 #endif 2414 /* Override the status which might be USBD_TIMEOUT. */ 2415 xfer->ux_status = status; 2416 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2417 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2418 while (xfer->ux_hcflags & UXFER_ABORTING) 2419 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2420 goto done; 2421 } 2422 xfer->ux_hcflags |= UXFER_ABORTING; 2423 2424 /* 2425 * Step 1: Make interrupt routine and hardware ignore xfer. 2426 */ 2427 xfer->ux_status = status; /* make software ignore it */ 2428 callout_stop(&xfer->ux_callout); 2429 uhci_del_intr_list(sc, ux); 2430 2431 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2432 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2433 usb_syncmem(&std->dma, 2434 std->offs + offsetof(uhci_td_t, td_status), 2435 sizeof(std->td.td_status), 2436 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2437 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2438 usb_syncmem(&std->dma, 2439 std->offs + offsetof(uhci_td_t, td_status), 2440 sizeof(std->td.td_status), 2441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2442 } 2443 2444 /* 2445 * Step 2: Wait until we know hardware has finished any possible 2446 * use of the xfer. Also make sure the soft interrupt routine 2447 * has run. 2448 */ 2449 /* Hardware finishes in 1ms */ 2450 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2451 sc->sc_softwake = 1; 2452 usb_schedsoftintr(&sc->sc_bus); 2453 DPRINTF("cv_wait", 0, 0, 0, 0); 2454 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2455 2456 /* 2457 * Step 3: Execute callback. 2458 */ 2459 DPRINTF("callback", 0, 0, 0, 0); 2460 #ifdef DIAGNOSTIC 2461 ux->ux_isdone = true; 2462 #endif 2463 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2464 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2465 usb_transfer_complete(xfer); 2466 if (wake) 2467 cv_broadcast(&xfer->ux_hccv); 2468 done: 2469 KASSERT(mutex_owned(&sc->sc_lock)); 2470 } 2471 2472 /* Close a device bulk pipe. */ 2473 void 2474 uhci_device_bulk_close(struct usbd_pipe *pipe) 2475 { 2476 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2477 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2478 2479 KASSERT(mutex_owned(&sc->sc_lock)); 2480 2481 uhci_free_sqh(sc, upipe->bulk.sqh); 2482 2483 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2484 } 2485 2486 int 2487 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2488 { 2489 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2490 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2491 usb_device_request_t *req = &xfer->ux_request; 2492 struct usbd_device *dev = upipe->pipe.up_dev; 2493 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2494 uhci_soft_td_t *data; 2495 int len; 2496 usbd_status err; 2497 int isread; 2498 2499 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2500 DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize, 2501 dev->ud_addr, upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2502 2503 isread = req->bmRequestType & UT_READ; 2504 len = xfer->ux_bufsize; 2505 2506 uxfer->ux_type = UX_CTRL; 2507 /* Set up data transaction */ 2508 if (len != 0) { 2509 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data); 2510 if (err) 2511 return err; 2512 } 2513 /* Set up interrupt info. */ 2514 uxfer->ux_setup = upipe->ctrl.setup; 2515 uxfer->ux_stat = upipe->ctrl.stat; 2516 uxfer->ux_data = data; 2517 2518 return 0; 2519 } 2520 2521 Static void 2522 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2523 { 2524 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2525 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2526 2527 KASSERT(ux->ux_type == UX_CTRL); 2528 2529 uhci_free_stds(sc, ux); 2530 if (ux->ux_nstd) 2531 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2532 } 2533 2534 usbd_status 2535 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2536 { 2537 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2538 usbd_status err; 2539 2540 /* Insert last in queue. */ 2541 mutex_enter(&sc->sc_lock); 2542 err = usb_insert_transfer(xfer); 2543 mutex_exit(&sc->sc_lock); 2544 if (err) 2545 return err; 2546 2547 /* 2548 * Pipe isn't running (otherwise err would be USBD_INPROG), 2549 * so start it first. 2550 */ 2551 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2552 } 2553 2554 usbd_status 2555 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2556 { 2557 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2558 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2559 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2560 usb_device_request_t *req = &xfer->ux_request; 2561 struct usbd_device *dev = upipe->pipe.up_dev; 2562 int addr = dev->ud_addr; 2563 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2564 uhci_soft_td_t *setup, *stat, *next, *dataend; 2565 uhci_soft_qh_t *sqh; 2566 int len; 2567 int isread; 2568 2569 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2570 2571 if (sc->sc_dying) 2572 return USBD_IOERROR; 2573 2574 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2575 2576 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2577 "wValue=0x%04x, wIndex=0x%04x", 2578 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2579 UGETW(req->wIndex)); 2580 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2581 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2582 2583 isread = req->bmRequestType & UT_READ; 2584 len = UGETW(req->wLength); 2585 2586 setup = upipe->ctrl.setup; 2587 stat = upipe->ctrl.stat; 2588 sqh = upipe->ctrl.sqh; 2589 2590 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2591 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2592 2593 mutex_enter(&sc->sc_lock); 2594 2595 /* Set up data transaction */ 2596 if (len != 0) { 2597 upipe->nexttoggle = 1; 2598 next = uxfer->ux_data; 2599 uhci_reset_std_chain(sc, xfer, len, isread, 2600 &upipe->nexttoggle, &dataend); 2601 dataend->link.std = stat; 2602 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2603 usb_syncmem(&dataend->dma, 2604 dataend->offs + offsetof(uhci_td_t, td_link), 2605 sizeof(dataend->td.td_link), 2606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2607 } else { 2608 next = stat; 2609 } 2610 2611 const uint32_t status = UHCI_TD_ZERO_ACTLEN( 2612 UHCI_TD_SET_ERRCNT(3) | 2613 UHCI_TD_ACTIVE | 2614 (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0) 2615 ); 2616 setup->link.std = next; 2617 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2618 setup->td.td_status = htole32(status); 2619 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2620 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2621 2622 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2624 2625 stat->link.std = NULL; 2626 stat->td.td_link = htole32(UHCI_PTR_T); 2627 stat->td.td_status = htole32(status | UHCI_TD_IOC); 2628 stat->td.td_token = 2629 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2630 UHCI_TD_IN (0, endpt, addr, 1)); 2631 stat->td.td_buffer = htole32(0); 2632 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2633 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2634 2635 #ifdef UHCI_DEBUG 2636 if (uhcidebug >= 10) { 2637 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2638 DPRINTF("before transfer", 0, 0, 0, 0); 2639 uhci_dump_tds(setup); 2640 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2641 } 2642 #endif 2643 2644 /* Set up interrupt info. */ 2645 uxfer->ux_setup = setup; 2646 uxfer->ux_stat = stat; 2647 KASSERT(uxfer->ux_isdone); 2648 #ifdef DIAGNOSTIC 2649 uxfer->ux_isdone = false; 2650 #endif 2651 2652 sqh->elink = setup; 2653 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2654 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2655 2656 if (dev->ud_speed == USB_SPEED_LOW) 2657 uhci_add_ls_ctrl(sc, sqh); 2658 else 2659 uhci_add_hs_ctrl(sc, sqh); 2660 uhci_add_intr_list(sc, uxfer); 2661 #ifdef UHCI_DEBUG 2662 if (uhcidebug >= 12) { 2663 uhci_soft_td_t *std; 2664 uhci_soft_qh_t *xqh; 2665 uhci_soft_qh_t *sxqh; 2666 int maxqh = 0; 2667 uhci_physaddr_t link; 2668 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2669 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2670 for (std = sc->sc_vframes[0].htd, link = 0; 2671 (link & UHCI_PTR_QH) == 0; 2672 std = std->link.std) { 2673 link = le32toh(std->td.td_link); 2674 uhci_dump_td(std); 2675 } 2676 sxqh = (uhci_soft_qh_t *)std; 2677 uhci_dump_qh(sxqh); 2678 for (xqh = sxqh; 2679 xqh != NULL; 2680 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2681 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2682 uhci_dump_qh(xqh); 2683 } 2684 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2685 uhci_dump_qh(sqh); 2686 uhci_dump_tds(sqh->elink); 2687 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2688 } 2689 #endif 2690 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2691 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2692 uhci_timeout, xfer); 2693 } 2694 xfer->ux_status = USBD_IN_PROGRESS; 2695 mutex_exit(&sc->sc_lock); 2696 2697 if (sc->sc_bus.ub_usepolling) 2698 uhci_waitintr(sc, xfer); 2699 2700 return USBD_IN_PROGRESS; 2701 } 2702 2703 int 2704 uhci_device_intr_init(struct usbd_xfer *xfer) 2705 { 2706 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2707 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2708 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2709 int endpt = ed->bEndpointAddress; 2710 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2711 int len = xfer->ux_bufsize; 2712 int err; 2713 2714 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2715 2716 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2717 xfer->ux_flags, 0); 2718 2719 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2720 KASSERT(len != 0); 2721 2722 ux->ux_type = UX_INTR; 2723 ux->ux_nstd = 0; 2724 err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart); 2725 2726 return err; 2727 } 2728 2729 Static void 2730 uhci_device_intr_fini(struct usbd_xfer *xfer) 2731 { 2732 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2733 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2734 2735 KASSERT(ux->ux_type == UX_INTR); 2736 2737 uhci_free_stds(sc, ux); 2738 if (ux->ux_nstd) 2739 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2740 } 2741 2742 usbd_status 2743 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2744 { 2745 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2746 usbd_status err; 2747 2748 /* Insert last in queue. */ 2749 mutex_enter(&sc->sc_lock); 2750 err = usb_insert_transfer(xfer); 2751 mutex_exit(&sc->sc_lock); 2752 if (err) 2753 return err; 2754 2755 /* 2756 * Pipe isn't running (otherwise err would be USBD_INPROG), 2757 * so start it first. 2758 */ 2759 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2760 } 2761 2762 usbd_status 2763 uhci_device_intr_start(struct usbd_xfer *xfer) 2764 { 2765 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2766 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2767 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2768 uhci_soft_td_t *data, *dataend; 2769 uhci_soft_qh_t *sqh; 2770 int isread, endpt; 2771 int i; 2772 2773 if (sc->sc_dying) 2774 return USBD_IOERROR; 2775 2776 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2777 2778 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2779 xfer->ux_flags, 0); 2780 2781 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2782 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2783 2784 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2785 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2786 2787 data = ux->ux_stdstart; 2788 2789 KASSERT(ux->ux_isdone); 2790 #ifdef DIAGNOSTIC 2791 ux->ux_isdone = false; 2792 #endif 2793 2794 /* Take lock to protect nexttoggle */ 2795 mutex_enter(&sc->sc_lock); 2796 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2797 &upipe->nexttoggle, &dataend); 2798 2799 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2800 usb_syncmem(&dataend->dma, 2801 dataend->offs + offsetof(uhci_td_t, td_status), 2802 sizeof(dataend->td.td_status), 2803 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2804 ux->ux_stdend = dataend; 2805 2806 #ifdef UHCI_DEBUG 2807 if (uhcidebug >= 10) { 2808 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2809 uhci_dump_tds(data); 2810 uhci_dump_qh(upipe->intr.qhs[0]); 2811 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2812 } 2813 #endif 2814 2815 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2816 for (i = 0; i < upipe->intr.npoll; i++) { 2817 sqh = upipe->intr.qhs[i]; 2818 sqh->elink = data; 2819 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2820 usb_syncmem(&sqh->dma, 2821 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2822 sizeof(sqh->qh.qh_elink), 2823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2824 } 2825 uhci_add_intr_list(sc, ux); 2826 xfer->ux_status = USBD_IN_PROGRESS; 2827 mutex_exit(&sc->sc_lock); 2828 2829 #ifdef UHCI_DEBUG 2830 if (uhcidebug >= 10) { 2831 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2832 uhci_dump_tds(data); 2833 uhci_dump_qh(upipe->intr.qhs[0]); 2834 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2835 } 2836 #endif 2837 2838 return USBD_IN_PROGRESS; 2839 } 2840 2841 /* Abort a device control request. */ 2842 void 2843 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2844 { 2845 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2846 2847 KASSERT(mutex_owned(&sc->sc_lock)); 2848 2849 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2850 uhci_abort_xfer(xfer, USBD_CANCELLED); 2851 } 2852 2853 /* Close a device control pipe. */ 2854 void 2855 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2856 { 2857 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2858 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2859 2860 uhci_free_sqh(sc, upipe->ctrl.sqh); 2861 uhci_free_std_locked(sc, upipe->ctrl.setup); 2862 uhci_free_std_locked(sc, upipe->ctrl.stat); 2863 2864 } 2865 2866 /* Abort a device interrupt request. */ 2867 void 2868 uhci_device_intr_abort(struct usbd_xfer *xfer) 2869 { 2870 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2871 2872 KASSERT(mutex_owned(&sc->sc_lock)); 2873 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2874 2875 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2876 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2877 2878 uhci_abort_xfer(xfer, USBD_CANCELLED); 2879 } 2880 2881 /* Close a device interrupt pipe. */ 2882 void 2883 uhci_device_intr_close(struct usbd_pipe *pipe) 2884 { 2885 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2886 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2887 int i, npoll; 2888 2889 KASSERT(mutex_owned(&sc->sc_lock)); 2890 2891 /* Unlink descriptors from controller data structures. */ 2892 npoll = upipe->intr.npoll; 2893 for (i = 0; i < npoll; i++) 2894 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2895 2896 /* 2897 * We now have to wait for any activity on the physical 2898 * descriptors to stop. 2899 */ 2900 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2901 2902 for (i = 0; i < npoll; i++) 2903 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2904 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2905 } 2906 2907 int 2908 uhci_device_isoc_init(struct usbd_xfer *xfer) 2909 { 2910 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2911 2912 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2913 KASSERT(xfer->ux_nframes != 0); 2914 KASSERT(ux->ux_isdone); 2915 2916 ux->ux_type = UX_ISOC; 2917 return 0; 2918 } 2919 2920 Static void 2921 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2922 { 2923 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2924 2925 KASSERT(ux->ux_type == UX_ISOC); 2926 } 2927 2928 usbd_status 2929 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2930 { 2931 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2932 usbd_status err __diagused; 2933 2934 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2935 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2936 2937 /* Put it on our queue, */ 2938 mutex_enter(&sc->sc_lock); 2939 err = usb_insert_transfer(xfer); 2940 mutex_exit(&sc->sc_lock); 2941 2942 KASSERT(err == USBD_NORMAL_COMPLETION); 2943 2944 /* insert into schedule, */ 2945 2946 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2947 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2948 struct isoc *isoc = &upipe->isoc; 2949 uhci_soft_td_t *std = NULL; 2950 uint32_t buf, len, status, offs; 2951 int i, next, nframes; 2952 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2953 2954 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2955 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2956 2957 if (sc->sc_dying) 2958 return USBD_IOERROR; 2959 2960 if (xfer->ux_status == USBD_IN_PROGRESS) { 2961 /* This request has already been entered into the frame list */ 2962 printf("%s: xfer=%p in frame list\n", __func__, xfer); 2963 /* XXX */ 2964 } 2965 2966 #ifdef DIAGNOSTIC 2967 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2968 printf("%s: overflow!\n", __func__); 2969 #endif 2970 2971 KASSERT(xfer->ux_nframes != 0); 2972 2973 mutex_enter(&sc->sc_lock); 2974 next = isoc->next; 2975 if (next == -1) { 2976 /* Not in use yet, schedule it a few frames ahead. */ 2977 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2978 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2979 } 2980 2981 xfer->ux_status = USBD_IN_PROGRESS; 2982 ux->ux_curframe = next; 2983 2984 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2985 offs = 0; 2986 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2987 UHCI_TD_ACTIVE | 2988 UHCI_TD_IOS); 2989 nframes = xfer->ux_nframes; 2990 for (i = 0; i < nframes; i++) { 2991 std = isoc->stds[next]; 2992 if (++next >= UHCI_VFRAMELIST_COUNT) 2993 next = 0; 2994 len = xfer->ux_frlengths[i]; 2995 std->td.td_buffer = htole32(buf); 2996 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2997 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2998 if (i == nframes - 1) 2999 status |= UHCI_TD_IOC; 3000 std->td.td_status = htole32(status); 3001 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 3002 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 3003 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3005 #ifdef UHCI_DEBUG 3006 if (uhcidebug >= 5) { 3007 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3008 DPRINTF("TD %d", i, 0, 0, 0); 3009 uhci_dump_td(std); 3010 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3011 } 3012 #endif 3013 buf += len; 3014 offs += len; 3015 } 3016 isoc->next = next; 3017 isoc->inuse += xfer->ux_nframes; 3018 3019 /* Set up interrupt info. */ 3020 ux->ux_stdstart = std; 3021 ux->ux_stdend = std; 3022 3023 KASSERT(ux->ux_isdone); 3024 #ifdef DIAGNOSTIC 3025 ux->ux_isdone = false; 3026 #endif 3027 uhci_add_intr_list(sc, ux); 3028 3029 mutex_exit(&sc->sc_lock); 3030 3031 return USBD_IN_PROGRESS; 3032 } 3033 3034 void 3035 uhci_device_isoc_abort(struct usbd_xfer *xfer) 3036 { 3037 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3038 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3039 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3040 uhci_soft_td_t **stds = upipe->isoc.stds; 3041 uhci_soft_td_t *std; 3042 int i, n, nframes, maxlen, len; 3043 3044 KASSERT(mutex_owned(&sc->sc_lock)); 3045 3046 /* Transfer is already done. */ 3047 if (xfer->ux_status != USBD_NOT_STARTED && 3048 xfer->ux_status != USBD_IN_PROGRESS) { 3049 return; 3050 } 3051 3052 /* Give xfer the requested abort code. */ 3053 xfer->ux_status = USBD_CANCELLED; 3054 3055 /* make hardware ignore it, */ 3056 nframes = xfer->ux_nframes; 3057 n = ux->ux_curframe; 3058 maxlen = 0; 3059 for (i = 0; i < nframes; i++) { 3060 std = stds[n]; 3061 usb_syncmem(&std->dma, 3062 std->offs + offsetof(uhci_td_t, td_status), 3063 sizeof(std->td.td_status), 3064 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3065 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3066 usb_syncmem(&std->dma, 3067 std->offs + offsetof(uhci_td_t, td_status), 3068 sizeof(std->td.td_status), 3069 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3070 usb_syncmem(&std->dma, 3071 std->offs + offsetof(uhci_td_t, td_token), 3072 sizeof(std->td.td_token), 3073 BUS_DMASYNC_POSTWRITE); 3074 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3075 if (len > maxlen) 3076 maxlen = len; 3077 if (++n >= UHCI_VFRAMELIST_COUNT) 3078 n = 0; 3079 } 3080 3081 /* and wait until we are sure the hardware has finished. */ 3082 delay(maxlen); 3083 3084 #ifdef DIAGNOSTIC 3085 ux->ux_isdone = true; 3086 #endif 3087 /* Remove from interrupt list. */ 3088 uhci_del_intr_list(sc, ux); 3089 3090 /* Run callback. */ 3091 usb_transfer_complete(xfer); 3092 3093 KASSERT(mutex_owned(&sc->sc_lock)); 3094 } 3095 3096 void 3097 uhci_device_isoc_close(struct usbd_pipe *pipe) 3098 { 3099 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3100 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3101 uhci_soft_td_t *std, *vstd; 3102 struct isoc *isoc; 3103 int i; 3104 3105 KASSERT(mutex_owned(&sc->sc_lock)); 3106 3107 /* 3108 * Make sure all TDs are marked as inactive. 3109 * Wait for completion. 3110 * Unschedule. 3111 * Deallocate. 3112 */ 3113 isoc = &upipe->isoc; 3114 3115 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3116 std = isoc->stds[i]; 3117 usb_syncmem(&std->dma, 3118 std->offs + offsetof(uhci_td_t, td_status), 3119 sizeof(std->td.td_status), 3120 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3121 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3122 usb_syncmem(&std->dma, 3123 std->offs + offsetof(uhci_td_t, td_status), 3124 sizeof(std->td.td_status), 3125 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3126 } 3127 /* wait for completion */ 3128 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3129 3130 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3131 std = isoc->stds[i]; 3132 for (vstd = sc->sc_vframes[i].htd; 3133 vstd != NULL && vstd->link.std != std; 3134 vstd = vstd->link.std) 3135 ; 3136 if (vstd == NULL) { 3137 /*panic*/ 3138 printf("%s: %p not found\n", __func__, std); 3139 mutex_exit(&sc->sc_lock); 3140 return; 3141 } 3142 vstd->link = std->link; 3143 usb_syncmem(&std->dma, 3144 std->offs + offsetof(uhci_td_t, td_link), 3145 sizeof(std->td.td_link), 3146 BUS_DMASYNC_POSTWRITE); 3147 vstd->td.td_link = std->td.td_link; 3148 usb_syncmem(&vstd->dma, 3149 vstd->offs + offsetof(uhci_td_t, td_link), 3150 sizeof(vstd->td.td_link), 3151 BUS_DMASYNC_PREWRITE); 3152 uhci_free_std_locked(sc, std); 3153 } 3154 3155 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3156 } 3157 3158 usbd_status 3159 uhci_setup_isoc(struct usbd_pipe *pipe) 3160 { 3161 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3162 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3163 int addr = upipe->pipe.up_dev->ud_addr; 3164 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3165 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3166 uhci_soft_td_t *std, *vstd; 3167 uint32_t token; 3168 struct isoc *isoc; 3169 int i; 3170 3171 isoc = &upipe->isoc; 3172 3173 isoc->stds = kmem_alloc( 3174 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3175 if (isoc->stds == NULL) 3176 return USBD_NOMEM; 3177 3178 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3179 UHCI_TD_OUT(0, endpt, addr, 0); 3180 3181 /* Allocate the TDs and mark as inactive; */ 3182 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3183 std = uhci_alloc_std(sc); 3184 if (std == 0) 3185 goto bad; 3186 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3187 std->td.td_token = htole32(token); 3188 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3189 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3190 isoc->stds[i] = std; 3191 } 3192 3193 mutex_enter(&sc->sc_lock); 3194 3195 /* Insert TDs into schedule. */ 3196 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3197 std = isoc->stds[i]; 3198 vstd = sc->sc_vframes[i].htd; 3199 usb_syncmem(&vstd->dma, 3200 vstd->offs + offsetof(uhci_td_t, td_link), 3201 sizeof(vstd->td.td_link), 3202 BUS_DMASYNC_POSTWRITE); 3203 std->link = vstd->link; 3204 std->td.td_link = vstd->td.td_link; 3205 usb_syncmem(&std->dma, 3206 std->offs + offsetof(uhci_td_t, td_link), 3207 sizeof(std->td.td_link), 3208 BUS_DMASYNC_PREWRITE); 3209 vstd->link.std = std; 3210 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3211 usb_syncmem(&vstd->dma, 3212 vstd->offs + offsetof(uhci_td_t, td_link), 3213 sizeof(vstd->td.td_link), 3214 BUS_DMASYNC_PREWRITE); 3215 } 3216 mutex_exit(&sc->sc_lock); 3217 3218 isoc->next = -1; 3219 isoc->inuse = 0; 3220 3221 return USBD_NORMAL_COMPLETION; 3222 3223 bad: 3224 while (--i >= 0) 3225 uhci_free_std(sc, isoc->stds[i]); 3226 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3227 return USBD_NOMEM; 3228 } 3229 3230 void 3231 uhci_device_isoc_done(struct usbd_xfer *xfer) 3232 { 3233 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3234 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3235 int i, offs; 3236 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3237 3238 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3239 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3240 xfer->ux_actlen, xfer->ux_state, 0, 0); 3241 3242 #ifdef DIAGNOSTIC 3243 if (ux->ux_stdend == NULL) { 3244 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3245 #ifdef UHCI_DEBUG 3246 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3247 uhci_dump_ii(ux); 3248 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3249 #endif 3250 return; 3251 } 3252 #endif 3253 3254 /* Turn off the interrupt since it is active even if the TD is not. */ 3255 usb_syncmem(&ux->ux_stdend->dma, 3256 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3257 sizeof(ux->ux_stdend->td.td_status), 3258 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3259 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3260 usb_syncmem(&ux->ux_stdend->dma, 3261 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3262 sizeof(ux->ux_stdend->td.td_status), 3263 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3264 3265 offs = 0; 3266 for (i = 0; i < xfer->ux_nframes; i++) { 3267 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3268 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3269 offs += xfer->ux_frlengths[i]; 3270 } 3271 } 3272 3273 void 3274 uhci_device_intr_done(struct usbd_xfer *xfer) 3275 { 3276 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3277 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3278 uhci_soft_qh_t *sqh; 3279 int i, npoll; 3280 3281 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3282 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3283 3284 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3285 3286 npoll = upipe->intr.npoll; 3287 for (i = 0; i < npoll; i++) { 3288 sqh = upipe->intr.qhs[i]; 3289 sqh->elink = NULL; 3290 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3291 usb_syncmem(&sqh->dma, 3292 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3293 sizeof(sqh->qh.qh_elink), 3294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3295 } 3296 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3297 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3298 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3299 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3300 } 3301 3302 /* Deallocate request data structures */ 3303 void 3304 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3305 { 3306 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3307 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3308 int len = UGETW(xfer->ux_request.wLength); 3309 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3310 3311 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3312 3313 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3314 3315 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3316 3317 /* XXXNH move to uhci_idone??? */ 3318 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3319 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3320 else 3321 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3322 3323 if (len) { 3324 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3325 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3326 } 3327 usb_syncmem(&upipe->ctrl.reqdma, 0, 3328 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3329 3330 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3331 } 3332 3333 /* Deallocate request data structures */ 3334 void 3335 uhci_device_bulk_done(struct usbd_xfer *xfer) 3336 { 3337 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3338 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3339 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3340 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3341 int endpt = ed->bEndpointAddress; 3342 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3343 3344 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3345 DPRINTFN(5, "xfer=%p ux=%p sc=%p upipe=%p", xfer, ux, sc, 3346 upipe); 3347 3348 KASSERT(mutex_owned(&sc->sc_lock)); 3349 3350 uhci_remove_bulk(sc, upipe->bulk.sqh); 3351 3352 if (xfer->ux_length) { 3353 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3354 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3355 } 3356 3357 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3358 } 3359 3360 /* Add interrupt QH, called with vflock. */ 3361 void 3362 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3363 { 3364 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3365 uhci_soft_qh_t *eqh; 3366 3367 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3368 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3369 3370 eqh = vf->eqh; 3371 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3372 sizeof(eqh->qh.qh_hlink), 3373 BUS_DMASYNC_POSTWRITE); 3374 sqh->hlink = eqh->hlink; 3375 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3376 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3377 sizeof(sqh->qh.qh_hlink), 3378 BUS_DMASYNC_PREWRITE); 3379 eqh->hlink = sqh; 3380 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3381 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3382 sizeof(eqh->qh.qh_hlink), 3383 BUS_DMASYNC_PREWRITE); 3384 vf->eqh = sqh; 3385 vf->bandwidth++; 3386 } 3387 3388 /* Remove interrupt QH. */ 3389 void 3390 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3391 { 3392 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3393 uhci_soft_qh_t *pqh; 3394 3395 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3396 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3397 3398 /* See comment in uhci_remove_ctrl() */ 3399 3400 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3401 sizeof(sqh->qh.qh_elink), 3402 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3403 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3404 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3405 usb_syncmem(&sqh->dma, 3406 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3407 sizeof(sqh->qh.qh_elink), 3408 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3409 delay(UHCI_QH_REMOVE_DELAY); 3410 } 3411 3412 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3413 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3414 sizeof(sqh->qh.qh_hlink), 3415 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3416 pqh->hlink = sqh->hlink; 3417 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3418 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3419 sizeof(pqh->qh.qh_hlink), 3420 BUS_DMASYNC_PREWRITE); 3421 delay(UHCI_QH_REMOVE_DELAY); 3422 if (vf->eqh == sqh) 3423 vf->eqh = pqh; 3424 vf->bandwidth--; 3425 } 3426 3427 usbd_status 3428 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3429 { 3430 uhci_soft_qh_t *sqh; 3431 int i, npoll; 3432 u_int bestbw, bw, bestoffs, offs; 3433 3434 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3435 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3436 if (ival == 0) { 3437 printf("%s: 0 interval\n", __func__); 3438 return USBD_INVAL; 3439 } 3440 3441 if (ival > UHCI_VFRAMELIST_COUNT) 3442 ival = UHCI_VFRAMELIST_COUNT; 3443 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3444 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3445 3446 upipe->intr.npoll = npoll; 3447 upipe->intr.qhs = 3448 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3449 if (upipe->intr.qhs == NULL) 3450 return USBD_NOMEM; 3451 3452 /* 3453 * Figure out which offset in the schedule that has most 3454 * bandwidth left over. 3455 */ 3456 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3457 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3458 for (bw = i = 0; i < npoll; i++) 3459 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3460 if (bw < bestbw) { 3461 bestbw = bw; 3462 bestoffs = offs; 3463 } 3464 } 3465 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3466 for (i = 0; i < npoll; i++) { 3467 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3468 sqh->elink = NULL; 3469 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3470 usb_syncmem(&sqh->dma, 3471 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3472 sizeof(sqh->qh.qh_elink), 3473 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3474 sqh->pos = MOD(i * ival + bestoffs); 3475 } 3476 #undef MOD 3477 3478 mutex_enter(&sc->sc_lock); 3479 /* Enter QHs into the controller data structures. */ 3480 for (i = 0; i < npoll; i++) 3481 uhci_add_intr(sc, upipe->intr.qhs[i]); 3482 mutex_exit(&sc->sc_lock); 3483 3484 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3485 3486 return USBD_NORMAL_COMPLETION; 3487 } 3488 3489 /* Open a new pipe. */ 3490 usbd_status 3491 uhci_open(struct usbd_pipe *pipe) 3492 { 3493 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3494 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3495 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3496 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3497 usbd_status err = USBD_NOMEM; 3498 int ival; 3499 3500 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3501 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3502 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3503 3504 if (sc->sc_dying) 3505 return USBD_IOERROR; 3506 3507 upipe->aborting = 0; 3508 /* toggle state needed for bulk endpoints */ 3509 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3510 3511 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3512 switch (ed->bEndpointAddress) { 3513 case USB_CONTROL_ENDPOINT: 3514 pipe->up_methods = &roothub_ctrl_methods; 3515 break; 3516 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3517 pipe->up_methods = &uhci_root_intr_methods; 3518 break; 3519 default: 3520 return USBD_INVAL; 3521 } 3522 } else { 3523 switch (ed->bmAttributes & UE_XFERTYPE) { 3524 case UE_CONTROL: 3525 pipe->up_methods = &uhci_device_ctrl_methods; 3526 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3527 if (upipe->ctrl.sqh == NULL) 3528 goto bad; 3529 upipe->ctrl.setup = uhci_alloc_std(sc); 3530 if (upipe->ctrl.setup == NULL) { 3531 uhci_free_sqh(sc, upipe->ctrl.sqh); 3532 goto bad; 3533 } 3534 upipe->ctrl.stat = uhci_alloc_std(sc); 3535 if (upipe->ctrl.stat == NULL) { 3536 uhci_free_sqh(sc, upipe->ctrl.sqh); 3537 uhci_free_std(sc, upipe->ctrl.setup); 3538 goto bad; 3539 } 3540 err = usb_allocmem(&sc->sc_bus, 3541 sizeof(usb_device_request_t), 3542 0, &upipe->ctrl.reqdma); 3543 if (err) { 3544 uhci_free_sqh(sc, upipe->ctrl.sqh); 3545 uhci_free_std(sc, upipe->ctrl.setup); 3546 uhci_free_std(sc, upipe->ctrl.stat); 3547 goto bad; 3548 } 3549 break; 3550 case UE_INTERRUPT: 3551 pipe->up_methods = &uhci_device_intr_methods; 3552 ival = pipe->up_interval; 3553 if (ival == USBD_DEFAULT_INTERVAL) 3554 ival = ed->bInterval; 3555 return uhci_device_setintr(sc, upipe, ival); 3556 case UE_ISOCHRONOUS: 3557 pipe->up_serialise = false; 3558 pipe->up_methods = &uhci_device_isoc_methods; 3559 return uhci_setup_isoc(pipe); 3560 case UE_BULK: 3561 pipe->up_methods = &uhci_device_bulk_methods; 3562 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3563 if (upipe->bulk.sqh == NULL) 3564 goto bad; 3565 break; 3566 } 3567 } 3568 return USBD_NORMAL_COMPLETION; 3569 3570 bad: 3571 return USBD_NOMEM; 3572 } 3573 3574 /* 3575 * Data structures and routines to emulate the root hub. 3576 */ 3577 /* 3578 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3579 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3580 * should not be used by the USB subsystem. As we cannot issue a 3581 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3582 * will be enabled as part of the reset. 3583 * 3584 * On the VT83C572, the port cannot be successfully enabled until the 3585 * outstanding "port enable change" and "connection status change" 3586 * events have been reset. 3587 */ 3588 Static usbd_status 3589 uhci_portreset(uhci_softc_t *sc, int index) 3590 { 3591 int lim, port, x; 3592 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3593 3594 if (index == 1) 3595 port = UHCI_PORTSC1; 3596 else if (index == 2) 3597 port = UHCI_PORTSC2; 3598 else 3599 return USBD_IOERROR; 3600 3601 x = URWMASK(UREAD2(sc, port)); 3602 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3603 3604 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3605 3606 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3607 UREAD2(sc, port), 0, 0); 3608 3609 x = URWMASK(UREAD2(sc, port)); 3610 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3611 3612 delay(100); 3613 3614 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3615 UREAD2(sc, port), 0, 0); 3616 3617 x = URWMASK(UREAD2(sc, port)); 3618 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3619 3620 for (lim = 10; --lim > 0;) { 3621 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3622 3623 x = UREAD2(sc, port); 3624 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3625 lim, x, 0); 3626 3627 if (!(x & UHCI_PORTSC_CCS)) { 3628 /* 3629 * No device is connected (or was disconnected 3630 * during reset). Consider the port reset. 3631 * The delay must be long enough to ensure on 3632 * the initial iteration that the device 3633 * connection will have been registered. 50ms 3634 * appears to be sufficient, but 20ms is not. 3635 */ 3636 DPRINTFN(3, "uhci port %d loop %u, device detached", 3637 index, lim, 0, 0); 3638 break; 3639 } 3640 3641 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3642 /* 3643 * Port enabled changed and/or connection 3644 * status changed were set. Reset either or 3645 * both raised flags (by writing a 1 to that 3646 * bit), and wait again for state to settle. 3647 */ 3648 UWRITE2(sc, port, URWMASK(x) | 3649 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3650 continue; 3651 } 3652 3653 if (x & UHCI_PORTSC_PE) 3654 /* Port is enabled */ 3655 break; 3656 3657 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3658 } 3659 3660 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3661 UREAD2(sc, port), 0, 0); 3662 3663 if (lim <= 0) { 3664 DPRINTF("uhci port %d reset timed out", index, 3665 0, 0, 0); 3666 return USBD_TIMEOUT; 3667 } 3668 3669 sc->sc_isreset = 1; 3670 return USBD_NORMAL_COMPLETION; 3671 } 3672 3673 Static int 3674 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3675 void *buf, int buflen) 3676 { 3677 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3678 int port, x; 3679 int status, change, totlen = 0; 3680 uint16_t len, value, index; 3681 usb_port_status_t ps; 3682 usbd_status err; 3683 3684 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3685 3686 if (sc->sc_dying) 3687 return -1; 3688 3689 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3690 req->bRequest, 0, 0); 3691 3692 len = UGETW(req->wLength); 3693 value = UGETW(req->wValue); 3694 index = UGETW(req->wIndex); 3695 3696 #define C(x,y) ((x) | ((y) << 8)) 3697 switch (C(req->bRequest, req->bmRequestType)) { 3698 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3699 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3700 if (len == 0) 3701 break; 3702 switch (value) { 3703 case C(0, UDESC_DEVICE): { 3704 usb_device_descriptor_t devd; 3705 3706 totlen = min(buflen, sizeof(devd)); 3707 memcpy(&devd, buf, totlen); 3708 USETW(devd.idVendor, sc->sc_id_vendor); 3709 memcpy(buf, &devd, totlen); 3710 break; 3711 } 3712 case C(1, UDESC_STRING): 3713 #define sd ((usb_string_descriptor_t *)buf) 3714 /* Vendor */ 3715 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3716 break; 3717 case C(2, UDESC_STRING): 3718 /* Product */ 3719 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3720 break; 3721 #undef sd 3722 default: 3723 /* default from usbroothub */ 3724 return buflen; 3725 } 3726 break; 3727 3728 /* Hub requests */ 3729 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3730 break; 3731 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3732 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3733 value, 0, 0); 3734 if (index == 1) 3735 port = UHCI_PORTSC1; 3736 else if (index == 2) 3737 port = UHCI_PORTSC2; 3738 else { 3739 return -1; 3740 } 3741 switch(value) { 3742 case UHF_PORT_ENABLE: 3743 x = URWMASK(UREAD2(sc, port)); 3744 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3745 break; 3746 case UHF_PORT_SUSPEND: 3747 x = URWMASK(UREAD2(sc, port)); 3748 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3749 break; 3750 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3751 /* see USB2 spec ch. 7.1.7.7 */ 3752 usb_delay_ms(&sc->sc_bus, 20); 3753 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3754 /* 10ms resume delay must be provided by caller */ 3755 break; 3756 case UHF_PORT_RESET: 3757 x = URWMASK(UREAD2(sc, port)); 3758 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3759 break; 3760 case UHF_C_PORT_CONNECTION: 3761 x = URWMASK(UREAD2(sc, port)); 3762 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3763 break; 3764 case UHF_C_PORT_ENABLE: 3765 x = URWMASK(UREAD2(sc, port)); 3766 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3767 break; 3768 case UHF_C_PORT_OVER_CURRENT: 3769 x = URWMASK(UREAD2(sc, port)); 3770 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3771 break; 3772 case UHF_C_PORT_RESET: 3773 sc->sc_isreset = 0; 3774 break; 3775 case UHF_PORT_CONNECTION: 3776 case UHF_PORT_OVER_CURRENT: 3777 case UHF_PORT_POWER: 3778 case UHF_PORT_LOW_SPEED: 3779 case UHF_C_PORT_SUSPEND: 3780 default: 3781 return -1; 3782 } 3783 break; 3784 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3785 if (index == 1) 3786 port = UHCI_PORTSC1; 3787 else if (index == 2) 3788 port = UHCI_PORTSC2; 3789 else { 3790 return -1; 3791 } 3792 if (len > 0) { 3793 *(uint8_t *)buf = 3794 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3795 totlen = 1; 3796 } 3797 break; 3798 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3799 if (len == 0) 3800 break; 3801 if ((value & 0xff) != 0) { 3802 return -1; 3803 } 3804 usb_hub_descriptor_t hubd; 3805 3806 totlen = min(buflen, sizeof(hubd)); 3807 memcpy(&hubd, buf, totlen); 3808 hubd.bNbrPorts = 2; 3809 memcpy(buf, &hubd, totlen); 3810 break; 3811 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3812 if (len != 4) { 3813 return -1; 3814 } 3815 memset(buf, 0, len); 3816 totlen = len; 3817 break; 3818 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3819 if (index == 1) 3820 port = UHCI_PORTSC1; 3821 else if (index == 2) 3822 port = UHCI_PORTSC2; 3823 else { 3824 return -1; 3825 } 3826 if (len != 4) { 3827 return -1; 3828 } 3829 x = UREAD2(sc, port); 3830 status = change = 0; 3831 if (x & UHCI_PORTSC_CCS) 3832 status |= UPS_CURRENT_CONNECT_STATUS; 3833 if (x & UHCI_PORTSC_CSC) 3834 change |= UPS_C_CONNECT_STATUS; 3835 if (x & UHCI_PORTSC_PE) 3836 status |= UPS_PORT_ENABLED; 3837 if (x & UHCI_PORTSC_POEDC) 3838 change |= UPS_C_PORT_ENABLED; 3839 if (x & UHCI_PORTSC_OCI) 3840 status |= UPS_OVERCURRENT_INDICATOR; 3841 if (x & UHCI_PORTSC_OCIC) 3842 change |= UPS_C_OVERCURRENT_INDICATOR; 3843 if (x & UHCI_PORTSC_SUSP) 3844 status |= UPS_SUSPEND; 3845 if (x & UHCI_PORTSC_LSDA) 3846 status |= UPS_LOW_SPEED; 3847 status |= UPS_PORT_POWER; 3848 if (sc->sc_isreset) 3849 change |= UPS_C_PORT_RESET; 3850 USETW(ps.wPortStatus, status); 3851 USETW(ps.wPortChange, change); 3852 totlen = min(len, sizeof(ps)); 3853 memcpy(buf, &ps, totlen); 3854 break; 3855 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3856 return -1; 3857 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3858 break; 3859 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3860 if (index == 1) 3861 port = UHCI_PORTSC1; 3862 else if (index == 2) 3863 port = UHCI_PORTSC2; 3864 else { 3865 return -1; 3866 } 3867 switch(value) { 3868 case UHF_PORT_ENABLE: 3869 x = URWMASK(UREAD2(sc, port)); 3870 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3871 break; 3872 case UHF_PORT_SUSPEND: 3873 x = URWMASK(UREAD2(sc, port)); 3874 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3875 break; 3876 case UHF_PORT_RESET: 3877 err = uhci_portreset(sc, index); 3878 if (err != USBD_NORMAL_COMPLETION) 3879 return -1; 3880 return 0; 3881 case UHF_PORT_POWER: 3882 /* Pretend we turned on power */ 3883 return 0; 3884 case UHF_C_PORT_CONNECTION: 3885 case UHF_C_PORT_ENABLE: 3886 case UHF_C_PORT_OVER_CURRENT: 3887 case UHF_PORT_CONNECTION: 3888 case UHF_PORT_OVER_CURRENT: 3889 case UHF_PORT_LOW_SPEED: 3890 case UHF_C_PORT_SUSPEND: 3891 case UHF_C_PORT_RESET: 3892 default: 3893 return -1; 3894 } 3895 break; 3896 default: 3897 /* default from usbroothub */ 3898 DPRINTF("returning %d (usbroothub default)", 3899 buflen, 0, 0, 0); 3900 return buflen; 3901 } 3902 3903 DPRINTF("returning %d", totlen, 0, 0, 0); 3904 3905 return totlen; 3906 } 3907 3908 /* Abort a root interrupt request. */ 3909 void 3910 uhci_root_intr_abort(struct usbd_xfer *xfer) 3911 { 3912 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3913 3914 KASSERT(mutex_owned(&sc->sc_lock)); 3915 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3916 3917 callout_stop(&sc->sc_poll_handle); 3918 sc->sc_intr_xfer = NULL; 3919 3920 xfer->ux_status = USBD_CANCELLED; 3921 #ifdef DIAGNOSTIC 3922 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3923 #endif 3924 usb_transfer_complete(xfer); 3925 } 3926 3927 usbd_status 3928 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3929 { 3930 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3931 usbd_status err; 3932 3933 /* Insert last in queue. */ 3934 mutex_enter(&sc->sc_lock); 3935 err = usb_insert_transfer(xfer); 3936 mutex_exit(&sc->sc_lock); 3937 if (err) 3938 return err; 3939 3940 /* 3941 * Pipe isn't running (otherwise err would be USBD_INPROG), 3942 * start first 3943 */ 3944 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3945 } 3946 3947 /* Start a transfer on the root interrupt pipe */ 3948 usbd_status 3949 uhci_root_intr_start(struct usbd_xfer *xfer) 3950 { 3951 struct usbd_pipe *pipe = xfer->ux_pipe; 3952 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3953 unsigned int ival; 3954 3955 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3956 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3957 xfer->ux_flags, 0); 3958 3959 if (sc->sc_dying) 3960 return USBD_IOERROR; 3961 3962 /* XXX temporary variable needed to avoid gcc3 warning */ 3963 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3964 sc->sc_ival = mstohz(ival); 3965 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3966 sc->sc_intr_xfer = xfer; 3967 return USBD_IN_PROGRESS; 3968 } 3969 3970 /* Close the root interrupt pipe. */ 3971 void 3972 uhci_root_intr_close(struct usbd_pipe *pipe) 3973 { 3974 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3975 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3976 3977 KASSERT(mutex_owned(&sc->sc_lock)); 3978 3979 callout_stop(&sc->sc_poll_handle); 3980 sc->sc_intr_xfer = NULL; 3981 } 3982
Indexes created Tue Sep 30 20:09:53 GMT 2025