uhci.c revision 1.264.4.72
1 /* $NetBSD: uhci.c,v 1.264.4.72 2016/04/11 08:02:25 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.72 2016/04/11 08:02:25 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup; 143 uhci_soft_td_t *stat; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 uhci_soft_qh_t **qhs; 149 } intr; 150 /* Bulk pipe */ 151 struct { 152 uhci_soft_qh_t *sqh; 153 } bulk; 154 /* Isochronous pipe */ 155 struct isoc { 156 uhci_soft_td_t **stds; 157 int next, inuse; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 163 164 Static void uhci_globalreset(uhci_softc_t *); 165 Static usbd_status uhci_portreset(uhci_softc_t*, int); 166 Static void uhci_reset(uhci_softc_t *); 167 Static usbd_status uhci_run(uhci_softc_t *, int, int); 168 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 169 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 170 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 #if 0 180 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 181 uhci_soft_td_t *); 182 #endif 183 Static usbd_status uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 184 int, int, uhci_soft_td_t **); 185 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 186 187 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 188 int, int, int *, uhci_soft_td_t **); 189 190 Static void uhci_poll_hub(void *); 191 Static void uhci_waitintr(uhci_softc_t *, struct usbd_xfer *); 192 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 193 ux_completeq_t *); 194 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 195 196 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 197 198 Static void uhci_timeout(void *); 199 Static void uhci_timeout_task(void *); 200 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 201 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 202 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 203 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 204 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 205 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 206 Static void uhci_add_loop(uhci_softc_t *); 207 Static void uhci_rem_loop(uhci_softc_t *); 208 209 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 210 211 Static struct usbd_xfer * 212 uhci_allocx(struct usbd_bus *, unsigned int); 213 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 214 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 215 Static int uhci_roothub_ctrl(struct usbd_bus *, 216 usb_device_request_t *, void *, int); 217 218 Static int uhci_device_ctrl_init(struct usbd_xfer *); 219 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 220 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 221 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 222 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 223 Static void uhci_device_ctrl_close(struct usbd_pipe *); 224 Static void uhci_device_ctrl_done(struct usbd_xfer *); 225 226 Static int uhci_device_intr_init(struct usbd_xfer *); 227 Static void uhci_device_intr_fini(struct usbd_xfer *); 228 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 229 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 230 Static void uhci_device_intr_abort(struct usbd_xfer *); 231 Static void uhci_device_intr_close(struct usbd_pipe *); 232 Static void uhci_device_intr_done(struct usbd_xfer *); 233 234 Static int uhci_device_bulk_init(struct usbd_xfer *); 235 Static void uhci_device_bulk_fini(struct usbd_xfer *); 236 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 238 Static void uhci_device_bulk_abort(struct usbd_xfer *); 239 Static void uhci_device_bulk_close(struct usbd_pipe *); 240 Static void uhci_device_bulk_done(struct usbd_xfer *); 241 242 Static int uhci_device_isoc_init(struct usbd_xfer *); 243 Static void uhci_device_isoc_fini(struct usbd_xfer *); 244 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 245 Static void uhci_device_isoc_abort(struct usbd_xfer *); 246 Static void uhci_device_isoc_close(struct usbd_pipe *); 247 Static void uhci_device_isoc_done(struct usbd_xfer *); 248 249 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 250 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 251 Static void uhci_root_intr_abort(struct usbd_xfer *); 252 Static void uhci_root_intr_close(struct usbd_pipe *); 253 Static void uhci_root_intr_done(struct usbd_xfer *); 254 255 Static usbd_status uhci_open(struct usbd_pipe *); 256 Static void uhci_poll(struct usbd_bus *); 257 Static void uhci_softintr(void *); 258 259 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 260 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 261 Static usbd_status uhci_device_setintr(uhci_softc_t *, 262 struct uhci_pipe *, int); 263 264 Static void uhci_device_clear_toggle(struct usbd_pipe *); 265 Static void uhci_noop(struct usbd_pipe *); 266 267 static inline uhci_soft_qh_t * 268 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 269 270 #ifdef UHCI_DEBUG 271 Static void uhci_dump_all(uhci_softc_t *); 272 Static void uhci_dumpregs(uhci_softc_t *); 273 Static void uhci_dump_qhs(uhci_soft_qh_t *); 274 Static void uhci_dump_qh(uhci_soft_qh_t *); 275 Static void uhci_dump_tds(uhci_soft_td_t *); 276 Static void uhci_dump_td(uhci_soft_td_t *); 277 Static void uhci_dump_ii(struct uhci_xfer *); 278 void uhci_dump(void); 279 #endif 280 281 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 282 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 283 #define UWRITE1(sc, r, x) \ 284 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 285 } while (/*CONSTCOND*/0) 286 #define UWRITE2(sc, r, x) \ 287 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 288 } while (/*CONSTCOND*/0) 289 #define UWRITE4(sc, r, x) \ 290 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 291 } while (/*CONSTCOND*/0) 292 293 static __inline uint8_t 294 UREAD1(uhci_softc_t *sc, bus_size_t r) 295 { 296 297 UBARR(sc); 298 return bus_space_read_1(sc->iot, sc->ioh, r); 299 } 300 301 static __inline uint16_t 302 UREAD2(uhci_softc_t *sc, bus_size_t r) 303 { 304 305 UBARR(sc); 306 return bus_space_read_2(sc->iot, sc->ioh, r); 307 } 308 309 #ifdef UHCI_DEBUG 310 static __inline uint32_t 311 UREAD4(uhci_softc_t *sc, bus_size_t r) 312 { 313 314 UBARR(sc); 315 return bus_space_read_4(sc->iot, sc->ioh, r); 316 } 317 #endif 318 319 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 320 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 321 322 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 323 324 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 325 326 const struct usbd_bus_methods uhci_bus_methods = { 327 .ubm_open = uhci_open, 328 .ubm_softint = uhci_softintr, 329 .ubm_dopoll = uhci_poll, 330 .ubm_allocx = uhci_allocx, 331 .ubm_freex = uhci_freex, 332 .ubm_getlock = uhci_get_lock, 333 .ubm_rhctrl = uhci_roothub_ctrl, 334 }; 335 336 const struct usbd_pipe_methods uhci_root_intr_methods = { 337 .upm_transfer = uhci_root_intr_transfer, 338 .upm_start = uhci_root_intr_start, 339 .upm_abort = uhci_root_intr_abort, 340 .upm_close = uhci_root_intr_close, 341 .upm_cleartoggle = uhci_noop, 342 .upm_done = uhci_root_intr_done, 343 }; 344 345 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 346 .upm_init = uhci_device_ctrl_init, 347 .upm_fini = uhci_device_ctrl_fini, 348 .upm_transfer = uhci_device_ctrl_transfer, 349 .upm_start = uhci_device_ctrl_start, 350 .upm_abort = uhci_device_ctrl_abort, 351 .upm_close = uhci_device_ctrl_close, 352 .upm_cleartoggle = uhci_noop, 353 .upm_done = uhci_device_ctrl_done, 354 }; 355 356 const struct usbd_pipe_methods uhci_device_intr_methods = { 357 .upm_init = uhci_device_intr_init, 358 .upm_fini = uhci_device_intr_fini, 359 .upm_transfer = uhci_device_intr_transfer, 360 .upm_start = uhci_device_intr_start, 361 .upm_abort = uhci_device_intr_abort, 362 .upm_close = uhci_device_intr_close, 363 .upm_cleartoggle = uhci_device_clear_toggle, 364 .upm_done = uhci_device_intr_done, 365 }; 366 367 const struct usbd_pipe_methods uhci_device_bulk_methods = { 368 .upm_init = uhci_device_bulk_init, 369 .upm_fini = uhci_device_bulk_fini, 370 .upm_transfer = uhci_device_bulk_transfer, 371 .upm_start = uhci_device_bulk_start, 372 .upm_abort = uhci_device_bulk_abort, 373 .upm_close = uhci_device_bulk_close, 374 .upm_cleartoggle = uhci_device_clear_toggle, 375 .upm_done = uhci_device_bulk_done, 376 }; 377 378 const struct usbd_pipe_methods uhci_device_isoc_methods = { 379 .upm_init = uhci_device_isoc_init, 380 .upm_fini = uhci_device_isoc_fini, 381 .upm_transfer = uhci_device_isoc_transfer, 382 .upm_abort = uhci_device_isoc_abort, 383 .upm_close = uhci_device_isoc_close, 384 .upm_cleartoggle = uhci_noop, 385 .upm_done = uhci_device_isoc_done, 386 }; 387 388 static inline void 389 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 390 { 391 392 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 393 } 394 395 static inline void 396 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 397 { 398 399 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 400 } 401 402 static inline uhci_soft_qh_t * 403 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 404 { 405 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 406 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 407 408 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 409 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 410 usb_syncmem(&pqh->dma, 411 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 412 sizeof(pqh->qh.qh_hlink), 413 BUS_DMASYNC_POSTWRITE); 414 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 415 printf("%s: QH not found\n", __func__); 416 return NULL; 417 } 418 #endif 419 } 420 return pqh; 421 } 422 423 void 424 uhci_globalreset(uhci_softc_t *sc) 425 { 426 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 427 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 428 UHCICMD(sc, 0); /* do nothing */ 429 } 430 431 int 432 uhci_init(uhci_softc_t *sc) 433 { 434 usbd_status err; 435 int i, j; 436 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 437 uhci_soft_td_t *std; 438 439 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 440 441 #ifdef UHCI_DEBUG 442 thesc = sc; 443 444 if (uhcidebug >= 2) 445 uhci_dumpregs(sc); 446 #endif 447 448 sc->sc_suspend = PWR_RESUME; 449 450 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 451 uhci_globalreset(sc); /* reset the controller */ 452 uhci_reset(sc); 453 454 /* Allocate and initialize real frame array. */ 455 err = usb_allocmem(&sc->sc_bus, 456 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 457 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 458 if (err) 459 return err; 460 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 461 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 462 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 463 464 /* Initialise mutex early for uhci_alloc_* */ 465 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 466 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 467 468 /* 469 * Allocate a TD, inactive, that hangs from the last QH. 470 * This is to avoid a bug in the PIIX that makes it run berserk 471 * otherwise. 472 */ 473 std = uhci_alloc_std(sc); 474 if (std == NULL) 475 return ENOMEM; 476 std->link.std = NULL; 477 std->td.td_link = htole32(UHCI_PTR_T); 478 std->td.td_status = htole32(0); /* inactive */ 479 std->td.td_token = htole32(0); 480 std->td.td_buffer = htole32(0); 481 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 483 484 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 485 lsqh = uhci_alloc_sqh(sc); 486 if (lsqh == NULL) 487 goto fail1; 488 lsqh->hlink = NULL; 489 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 490 lsqh->elink = std; 491 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 492 sc->sc_last_qh = lsqh; 493 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 494 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 495 496 /* Allocate the dummy QH where bulk traffic will be queued. */ 497 bsqh = uhci_alloc_sqh(sc); 498 if (bsqh == NULL) 499 goto fail2; 500 bsqh->hlink = lsqh; 501 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 502 bsqh->elink = NULL; 503 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 504 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 505 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 508 /* Allocate dummy QH where high speed control traffic will be queued. */ 509 chsqh = uhci_alloc_sqh(sc); 510 if (chsqh == NULL) 511 goto fail3; 512 chsqh->hlink = bsqh; 513 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 514 chsqh->elink = NULL; 515 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 516 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 517 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 518 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 519 520 /* Allocate dummy QH where control traffic will be queued. */ 521 clsqh = uhci_alloc_sqh(sc); 522 if (clsqh == NULL) 523 goto fail4; 524 clsqh->hlink = chsqh; 525 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 526 clsqh->elink = NULL; 527 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 528 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 529 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 532 /* 533 * Make all (virtual) frame list pointers point to the interrupt 534 * queue heads and the interrupt queue heads at the control 535 * queue head and point the physical frame list to the virtual. 536 */ 537 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 538 std = uhci_alloc_std(sc); 539 sqh = uhci_alloc_sqh(sc); 540 if (std == NULL || sqh == NULL) 541 return USBD_NOMEM; 542 std->link.sqh = sqh; 543 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 544 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 545 std->td.td_token = htole32(0); 546 std->td.td_buffer = htole32(0); 547 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 548 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 549 sqh->hlink = clsqh; 550 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 551 sqh->elink = NULL; 552 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 553 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 554 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 555 sc->sc_vframes[i].htd = std; 556 sc->sc_vframes[i].etd = std; 557 sc->sc_vframes[i].hqh = sqh; 558 sc->sc_vframes[i].eqh = sqh; 559 for (j = i; 560 j < UHCI_FRAMELIST_COUNT; 561 j += UHCI_VFRAMELIST_COUNT) 562 sc->sc_pframes[j] = htole32(std->physaddr); 563 } 564 usb_syncmem(&sc->sc_dma, 0, 565 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 566 BUS_DMASYNC_PREWRITE); 567 568 569 TAILQ_INIT(&sc->sc_intrhead); 570 571 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 572 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 573 574 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 575 576 cv_init(&sc->sc_softwake_cv, "uhciab"); 577 578 /* Set up the bus struct. */ 579 sc->sc_bus.ub_methods = &uhci_bus_methods; 580 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 581 sc->sc_bus.ub_usedma = true; 582 583 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 584 585 DPRINTF("Enabling...", 0, 0, 0, 0); 586 587 err = uhci_run(sc, 1, 0); /* and here we go... */ 588 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 589 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 590 return err; 591 592 fail4: 593 uhci_free_sqh(sc, chsqh); 594 fail3: 595 uhci_free_sqh(sc, lsqh); 596 fail2: 597 uhci_free_sqh(sc, lsqh); 598 fail1: 599 uhci_free_std(sc, std); 600 601 return ENOMEM; 602 } 603 604 int 605 uhci_activate(device_t self, enum devact act) 606 { 607 struct uhci_softc *sc = device_private(self); 608 609 switch (act) { 610 case DVACT_DEACTIVATE: 611 sc->sc_dying = 1; 612 return 0; 613 default: 614 return EOPNOTSUPP; 615 } 616 } 617 618 void 619 uhci_childdet(device_t self, device_t child) 620 { 621 struct uhci_softc *sc = device_private(self); 622 623 KASSERT(sc->sc_child == child); 624 sc->sc_child = NULL; 625 } 626 627 int 628 uhci_detach(struct uhci_softc *sc, int flags) 629 { 630 int rv = 0; 631 632 if (sc->sc_child != NULL) 633 rv = config_detach(sc->sc_child, flags); 634 635 if (rv != 0) 636 return rv; 637 638 callout_halt(&sc->sc_poll_handle, NULL); 639 callout_destroy(&sc->sc_poll_handle); 640 641 cv_destroy(&sc->sc_softwake_cv); 642 643 mutex_destroy(&sc->sc_lock); 644 mutex_destroy(&sc->sc_intr_lock); 645 646 pool_cache_destroy(sc->sc_xferpool); 647 648 /* XXX free other data structures XXX */ 649 650 return rv; 651 } 652 653 struct usbd_xfer * 654 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 655 { 656 struct uhci_softc *sc = UHCI_BUS2SC(bus); 657 struct usbd_xfer *xfer; 658 659 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 660 if (xfer != NULL) { 661 memset(xfer, 0, sizeof(struct uhci_xfer)); 662 663 #ifdef DIAGNOSTIC 664 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 665 uxfer->ux_isdone = true; 666 xfer->ux_state = XFER_BUSY; 667 #endif 668 } 669 return xfer; 670 } 671 672 void 673 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 674 { 675 struct uhci_softc *sc = UHCI_BUS2SC(bus); 676 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 677 678 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 679 xfer->ux_state); 680 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 681 #ifdef DIAGNOSTIC 682 xfer->ux_state = XFER_FREE; 683 #endif 684 pool_cache_put(sc->sc_xferpool, xfer); 685 } 686 687 Static void 688 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 689 { 690 struct uhci_softc *sc = UHCI_BUS2SC(bus); 691 692 *lock = &sc->sc_lock; 693 } 694 695 696 /* 697 * Handle suspend/resume. 698 * 699 * We need to switch to polling mode here, because this routine is 700 * called from an interrupt context. This is all right since we 701 * are almost suspended anyway. 702 */ 703 bool 704 uhci_resume(device_t dv, const pmf_qual_t *qual) 705 { 706 uhci_softc_t *sc = device_private(dv); 707 int cmd; 708 709 mutex_spin_enter(&sc->sc_intr_lock); 710 711 cmd = UREAD2(sc, UHCI_CMD); 712 sc->sc_bus.ub_usepolling++; 713 UWRITE2(sc, UHCI_INTR, 0); 714 uhci_globalreset(sc); 715 uhci_reset(sc); 716 if (cmd & UHCI_CMD_RS) 717 uhci_run(sc, 0, 1); 718 719 /* restore saved state */ 720 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 721 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 722 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 723 724 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 725 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 726 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 727 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 728 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 729 UHCICMD(sc, UHCI_CMD_MAXP); 730 uhci_run(sc, 1, 1); /* and start traffic again */ 731 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 732 sc->sc_bus.ub_usepolling--; 733 if (sc->sc_intr_xfer != NULL) 734 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 735 sc->sc_intr_xfer); 736 #ifdef UHCI_DEBUG 737 if (uhcidebug >= 2) 738 uhci_dumpregs(sc); 739 #endif 740 741 sc->sc_suspend = PWR_RESUME; 742 mutex_spin_exit(&sc->sc_intr_lock); 743 744 return true; 745 } 746 747 bool 748 uhci_suspend(device_t dv, const pmf_qual_t *qual) 749 { 750 uhci_softc_t *sc = device_private(dv); 751 int cmd; 752 753 mutex_spin_enter(&sc->sc_intr_lock); 754 755 cmd = UREAD2(sc, UHCI_CMD); 756 757 #ifdef UHCI_DEBUG 758 if (uhcidebug >= 2) 759 uhci_dumpregs(sc); 760 #endif 761 if (sc->sc_intr_xfer != NULL) 762 callout_stop(&sc->sc_poll_handle); 763 sc->sc_suspend = PWR_SUSPEND; 764 sc->sc_bus.ub_usepolling++; 765 766 uhci_run(sc, 0, 1); /* stop the controller */ 767 cmd &= ~UHCI_CMD_RS; 768 769 /* save some state if BIOS doesn't */ 770 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 771 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 772 773 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 774 775 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 776 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 777 sc->sc_bus.ub_usepolling--; 778 779 mutex_spin_exit(&sc->sc_intr_lock); 780 781 return true; 782 } 783 784 #ifdef UHCI_DEBUG 785 Static void 786 uhci_dumpregs(uhci_softc_t *sc) 787 { 788 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 789 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 790 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 791 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 792 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 793 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 794 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 795 } 796 797 void 798 uhci_dump_td(uhci_soft_td_t *p) 799 { 800 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 801 802 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 803 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 804 805 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 806 DPRINTF(" link=0x%08x status=0x%08x " 807 "token=0x%08x buffer=0x%08x", 808 le32toh(p->td.td_link), 809 le32toh(p->td.td_status), 810 le32toh(p->td.td_token), 811 le32toh(p->td.td_buffer)); 812 813 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 814 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 815 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 816 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 817 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 818 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 819 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 820 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 821 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 822 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 823 DPRINTF("ios =%d ls =%d spd =%d", 824 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 825 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 826 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 827 DPRINTF("errcnt =%d actlen =%d pid=%02x", 828 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 829 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 830 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 831 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 832 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 833 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 834 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 835 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 836 } 837 838 void 839 uhci_dump_qh(uhci_soft_qh_t *sqh) 840 { 841 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 842 843 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 844 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 845 846 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 847 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 848 le32toh(sqh->qh.qh_elink)); 849 850 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 851 } 852 853 854 #if 1 855 void 856 uhci_dump(void) 857 { 858 uhci_dump_all(thesc); 859 } 860 #endif 861 862 void 863 uhci_dump_all(uhci_softc_t *sc) 864 { 865 uhci_dumpregs(sc); 866 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 867 uhci_dump_qhs(sc->sc_lctl_start); 868 } 869 870 871 void 872 uhci_dump_qhs(uhci_soft_qh_t *sqh) 873 { 874 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 875 876 uhci_dump_qh(sqh); 877 878 /* 879 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 880 * Traverses sideways first, then down. 881 * 882 * QH1 883 * QH2 884 * No QH 885 * TD2.1 886 * TD2.2 887 * TD1.1 888 * etc. 889 * 890 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 891 */ 892 893 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 894 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 895 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 896 uhci_dump_qhs(sqh->hlink); 897 else 898 DPRINTF("No QH", 0, 0, 0, 0); 899 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 900 901 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 902 uhci_dump_tds(sqh->elink); 903 else 904 DPRINTF("No QH", 0, 0, 0, 0); 905 } 906 907 void 908 uhci_dump_tds(uhci_soft_td_t *std) 909 { 910 uhci_soft_td_t *td; 911 int stop; 912 913 for (td = std; td != NULL; td = td->link.std) { 914 uhci_dump_td(td); 915 916 /* 917 * Check whether the link pointer in this TD marks 918 * the link pointer as end of queue. This avoids 919 * printing the free list in case the queue/TD has 920 * already been moved there (seatbelt). 921 */ 922 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 923 sizeof(td->td.td_link), 924 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 925 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 926 le32toh(td->td.td_link) == 0); 927 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 928 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 929 if (stop) 930 break; 931 } 932 } 933 934 Static void 935 uhci_dump_ii(struct uhci_xfer *ux) 936 { 937 struct usbd_pipe *pipe; 938 usb_endpoint_descriptor_t *ed; 939 struct usbd_device *dev; 940 941 if (ux == NULL) { 942 printf("ux NULL\n"); 943 return; 944 } 945 pipe = ux->ux_xfer.ux_pipe; 946 if (pipe == NULL) { 947 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 948 return; 949 } 950 if (pipe->up_endpoint == NULL) { 951 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 952 ux, ux->ux_isdone, pipe); 953 return; 954 } 955 if (pipe->up_dev == NULL) { 956 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 957 ux, ux->ux_isdone, pipe); 958 return; 959 } 960 ed = pipe->up_endpoint->ue_edesc; 961 dev = pipe->up_dev; 962 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 963 ux, ux->ux_isdone, dev, 964 UGETW(dev->ud_ddesc.idVendor), 965 UGETW(dev->ud_ddesc.idProduct), 966 dev->ud_addr, pipe, 967 ed->bEndpointAddress, ed->bmAttributes); 968 } 969 970 void uhci_dump_iis(struct uhci_softc *sc); 971 void 972 uhci_dump_iis(struct uhci_softc *sc) 973 { 974 struct uhci_xfer *ux; 975 976 printf("interrupt list:\n"); 977 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 978 uhci_dump_ii(ux); 979 } 980 981 void iidump(void); 982 void iidump(void) { uhci_dump_iis(thesc); } 983 984 #endif 985 986 /* 987 * This routine is executed periodically and simulates interrupts 988 * from the root controller interrupt pipe for port status change. 989 */ 990 void 991 uhci_poll_hub(void *addr) 992 { 993 struct usbd_xfer *xfer = addr; 994 struct usbd_pipe *pipe = xfer->ux_pipe; 995 uhci_softc_t *sc; 996 u_char *p; 997 998 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 999 1000 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1001 return; /* device has detached */ 1002 sc = UHCI_PIPE2SC(pipe); 1003 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1004 1005 p = xfer->ux_buf; 1006 p[0] = 0; 1007 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1008 p[0] |= 1<<1; 1009 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1010 p[0] |= 1<<2; 1011 if (p[0] == 0) 1012 /* No change, try again in a while */ 1013 return; 1014 1015 xfer->ux_actlen = 1; 1016 xfer->ux_status = USBD_NORMAL_COMPLETION; 1017 mutex_enter(&sc->sc_lock); 1018 usb_transfer_complete(xfer); 1019 mutex_exit(&sc->sc_lock); 1020 } 1021 1022 void 1023 uhci_root_intr_done(struct usbd_xfer *xfer) 1024 { 1025 } 1026 1027 /* 1028 * Let the last QH loop back to the high speed control transfer QH. 1029 * This is what intel calls "bandwidth reclamation" and improves 1030 * USB performance a lot for some devices. 1031 * If we are already looping, just count it. 1032 */ 1033 void 1034 uhci_add_loop(uhci_softc_t *sc) 1035 { 1036 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1037 1038 #ifdef UHCI_DEBUG 1039 if (uhcinoloop) 1040 return; 1041 #endif 1042 if (++sc->sc_loops == 1) { 1043 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1044 /* Note, we don't loop back the soft pointer. */ 1045 sc->sc_last_qh->qh.qh_hlink = 1046 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1047 usb_syncmem(&sc->sc_last_qh->dma, 1048 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1049 sizeof(sc->sc_last_qh->qh.qh_hlink), 1050 BUS_DMASYNC_PREWRITE); 1051 } 1052 } 1053 1054 void 1055 uhci_rem_loop(uhci_softc_t *sc) 1056 { 1057 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1058 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (--sc->sc_loops == 0) { 1064 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1065 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1066 usb_syncmem(&sc->sc_last_qh->dma, 1067 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1068 sizeof(sc->sc_last_qh->qh.qh_hlink), 1069 BUS_DMASYNC_PREWRITE); 1070 } 1071 } 1072 1073 /* Add high speed control QH, called with lock held. */ 1074 void 1075 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1076 { 1077 uhci_soft_qh_t *eqh; 1078 1079 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1080 1081 KASSERT(mutex_owned(&sc->sc_lock)); 1082 1083 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1084 eqh = sc->sc_hctl_end; 1085 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1086 sizeof(eqh->qh.qh_hlink), 1087 BUS_DMASYNC_POSTWRITE); 1088 sqh->hlink = eqh->hlink; 1089 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1090 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1091 BUS_DMASYNC_PREWRITE); 1092 eqh->hlink = sqh; 1093 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1094 sc->sc_hctl_end = sqh; 1095 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1096 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1097 #ifdef UHCI_CTL_LOOP 1098 uhci_add_loop(sc); 1099 #endif 1100 } 1101 1102 /* Remove high speed control QH, called with lock held. */ 1103 void 1104 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1105 { 1106 uhci_soft_qh_t *pqh; 1107 uint32_t elink; 1108 1109 KASSERT(mutex_owned(&sc->sc_lock)); 1110 1111 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1112 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1113 #ifdef UHCI_CTL_LOOP 1114 uhci_rem_loop(sc); 1115 #endif 1116 /* 1117 * The T bit should be set in the elink of the QH so that the HC 1118 * doesn't follow the pointer. This condition may fail if the 1119 * the transferred packet was short so that the QH still points 1120 * at the last used TD. 1121 * In this case we set the T bit and wait a little for the HC 1122 * to stop looking at the TD. 1123 * Note that if the TD chain is large enough, the controller 1124 * may still be looking at the chain at the end of this function. 1125 * uhci_free_std_chain() will make sure the controller stops 1126 * looking at it quickly, but until then we should not change 1127 * sqh->hlink. 1128 */ 1129 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1130 sizeof(sqh->qh.qh_elink), 1131 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1132 elink = le32toh(sqh->qh.qh_elink); 1133 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1134 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1135 if (!(elink & UHCI_PTR_T)) { 1136 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1137 usb_syncmem(&sqh->dma, 1138 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1139 sizeof(sqh->qh.qh_elink), 1140 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1141 delay(UHCI_QH_REMOVE_DELAY); 1142 } 1143 1144 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1145 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1146 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1147 pqh->hlink = sqh->hlink; 1148 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1149 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1150 sizeof(pqh->qh.qh_hlink), 1151 BUS_DMASYNC_PREWRITE); 1152 delay(UHCI_QH_REMOVE_DELAY); 1153 if (sc->sc_hctl_end == sqh) 1154 sc->sc_hctl_end = pqh; 1155 } 1156 1157 /* Add low speed control QH, called with lock held. */ 1158 void 1159 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1160 { 1161 uhci_soft_qh_t *eqh; 1162 1163 KASSERT(mutex_owned(&sc->sc_lock)); 1164 1165 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1166 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1167 1168 eqh = sc->sc_lctl_end; 1169 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1170 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1171 sqh->hlink = eqh->hlink; 1172 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1173 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1174 BUS_DMASYNC_PREWRITE); 1175 eqh->hlink = sqh; 1176 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1177 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1178 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1179 sc->sc_lctl_end = sqh; 1180 } 1181 1182 /* Remove low speed control QH, called with lock held. */ 1183 void 1184 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1185 { 1186 uhci_soft_qh_t *pqh; 1187 uint32_t elink; 1188 1189 KASSERT(mutex_owned(&sc->sc_lock)); 1190 1191 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1192 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1193 1194 /* See comment in uhci_remove_hs_ctrl() */ 1195 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1196 sizeof(sqh->qh.qh_elink), 1197 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1198 elink = le32toh(sqh->qh.qh_elink); 1199 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1200 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1201 if (!(elink & UHCI_PTR_T)) { 1202 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1203 usb_syncmem(&sqh->dma, 1204 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1205 sizeof(sqh->qh.qh_elink), 1206 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1207 delay(UHCI_QH_REMOVE_DELAY); 1208 } 1209 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1210 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1211 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1212 pqh->hlink = sqh->hlink; 1213 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1214 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1215 sizeof(pqh->qh.qh_hlink), 1216 BUS_DMASYNC_PREWRITE); 1217 delay(UHCI_QH_REMOVE_DELAY); 1218 if (sc->sc_lctl_end == sqh) 1219 sc->sc_lctl_end = pqh; 1220 } 1221 1222 /* Add bulk QH, called with lock held. */ 1223 void 1224 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1225 { 1226 uhci_soft_qh_t *eqh; 1227 1228 KASSERT(mutex_owned(&sc->sc_lock)); 1229 1230 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1231 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1232 1233 eqh = sc->sc_bulk_end; 1234 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1235 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1236 sqh->hlink = eqh->hlink; 1237 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1238 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1239 BUS_DMASYNC_PREWRITE); 1240 eqh->hlink = sqh; 1241 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1242 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1243 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1244 sc->sc_bulk_end = sqh; 1245 uhci_add_loop(sc); 1246 } 1247 1248 /* Remove bulk QH, called with lock held. */ 1249 void 1250 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1251 { 1252 uhci_soft_qh_t *pqh; 1253 1254 KASSERT(mutex_owned(&sc->sc_lock)); 1255 1256 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1257 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1258 1259 uhci_rem_loop(sc); 1260 /* See comment in uhci_remove_hs_ctrl() */ 1261 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1262 sizeof(sqh->qh.qh_elink), 1263 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1264 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1265 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1266 usb_syncmem(&sqh->dma, 1267 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1268 sizeof(sqh->qh.qh_elink), 1269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1270 delay(UHCI_QH_REMOVE_DELAY); 1271 } 1272 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1273 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1274 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1275 pqh->hlink = sqh->hlink; 1276 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1277 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1278 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1279 delay(UHCI_QH_REMOVE_DELAY); 1280 if (sc->sc_bulk_end == sqh) 1281 sc->sc_bulk_end = pqh; 1282 } 1283 1284 Static int uhci_intr1(uhci_softc_t *); 1285 1286 int 1287 uhci_intr(void *arg) 1288 { 1289 uhci_softc_t *sc = arg; 1290 int ret = 0; 1291 1292 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1293 1294 mutex_spin_enter(&sc->sc_intr_lock); 1295 1296 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1297 goto done; 1298 1299 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1300 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1301 goto done; 1302 } 1303 1304 ret = uhci_intr1(sc); 1305 1306 done: 1307 mutex_spin_exit(&sc->sc_intr_lock); 1308 return ret; 1309 } 1310 1311 int 1312 uhci_intr1(uhci_softc_t *sc) 1313 { 1314 int status; 1315 int ack; 1316 1317 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1318 1319 #ifdef UHCI_DEBUG 1320 if (uhcidebug >= 15) { 1321 DPRINTF("sc %p", sc, 0, 0, 0); 1322 uhci_dumpregs(sc); 1323 } 1324 #endif 1325 1326 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1327 1328 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1329 /* Check if the interrupt was for us. */ 1330 if (status == 0) 1331 return 0; 1332 1333 if (sc->sc_suspend != PWR_RESUME) { 1334 #ifdef DIAGNOSTIC 1335 printf("%s: interrupt while not operating ignored\n", 1336 device_xname(sc->sc_dev)); 1337 #endif 1338 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1339 return 0; 1340 } 1341 1342 ack = 0; 1343 if (status & UHCI_STS_USBINT) 1344 ack |= UHCI_STS_USBINT; 1345 if (status & UHCI_STS_USBEI) 1346 ack |= UHCI_STS_USBEI; 1347 if (status & UHCI_STS_RD) { 1348 ack |= UHCI_STS_RD; 1349 #ifdef UHCI_DEBUG 1350 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1351 #endif 1352 } 1353 if (status & UHCI_STS_HSE) { 1354 ack |= UHCI_STS_HSE; 1355 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1356 } 1357 if (status & UHCI_STS_HCPE) { 1358 ack |= UHCI_STS_HCPE; 1359 printf("%s: host controller process error\n", 1360 device_xname(sc->sc_dev)); 1361 } 1362 1363 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1364 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1365 /* no acknowledge needed */ 1366 if (!sc->sc_dying) { 1367 printf("%s: host controller halted\n", 1368 device_xname(sc->sc_dev)); 1369 #ifdef UHCI_DEBUG 1370 uhci_dump_all(sc); 1371 #endif 1372 } 1373 sc->sc_dying = 1; 1374 } 1375 1376 if (!ack) 1377 return 0; /* nothing to acknowledge */ 1378 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1379 1380 usb_schedsoftintr(&sc->sc_bus); 1381 1382 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1383 1384 return 1; 1385 } 1386 1387 void 1388 uhci_softintr(void *v) 1389 { 1390 struct usbd_bus *bus = v; 1391 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1392 struct uhci_xfer *ux, *nextux; 1393 ux_completeq_t cq; 1394 1395 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1396 DPRINTF("sc %p", sc, 0, 0, 0); 1397 1398 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1399 1400 TAILQ_INIT(&cq); 1401 /* 1402 * Interrupts on UHCI really suck. When the host controller 1403 * interrupts because a transfer is completed there is no 1404 * way of knowing which transfer it was. You can scan down 1405 * the TDs and QHs of the previous frame to limit the search, 1406 * but that assumes that the interrupt was not delayed by more 1407 * than 1 ms, which may not always be true (e.g. after debug 1408 * output on a slow console). 1409 * We scan all interrupt descriptors to see if any have 1410 * completed. 1411 */ 1412 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1413 uhci_check_intr(sc, ux, &cq); 1414 } 1415 1416 /* 1417 * We abuse ux_list for the interrupt and complete lists and 1418 * interrupt transfers will get re-added here so use 1419 * the _SAFE version of TAILQ_FOREACH. 1420 */ 1421 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1422 DPRINTF("ux %p", ux, 0, 0, 0); 1423 usb_transfer_complete(&ux->ux_xfer); 1424 } 1425 1426 if (sc->sc_softwake) { 1427 sc->sc_softwake = 0; 1428 cv_broadcast(&sc->sc_softwake_cv); 1429 } 1430 } 1431 1432 /* Check for an interrupt. */ 1433 void 1434 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1435 { 1436 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1437 uint32_t status; 1438 1439 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1440 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1441 1442 KASSERT(ux != NULL); 1443 1444 struct usbd_xfer *xfer = &ux->ux_xfer; 1445 if (xfer->ux_status == USBD_CANCELLED || 1446 xfer->ux_status == USBD_TIMEOUT) { 1447 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1448 return; 1449 } 1450 1451 switch (ux->ux_type) { 1452 case UX_CTRL: 1453 fstd = ux->ux_setup; 1454 lstd = ux->ux_stat; 1455 break; 1456 case UX_BULK: 1457 case UX_INTR: 1458 case UX_ISOC: 1459 fstd = ux->ux_stdstart; 1460 lstd = ux->ux_stdend; 1461 break; 1462 default: 1463 KASSERT(false); 1464 break; 1465 } 1466 if (fstd == NULL) 1467 return; 1468 1469 KASSERT(lstd != NULL); 1470 1471 usb_syncmem(&lstd->dma, 1472 lstd->offs + offsetof(uhci_td_t, td_status), 1473 sizeof(lstd->td.td_status), 1474 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1475 status = le32toh(lstd->td.td_status); 1476 usb_syncmem(&lstd->dma, 1477 lstd->offs + offsetof(uhci_td_t, td_status), 1478 sizeof(lstd->td.td_status), 1479 BUS_DMASYNC_PREREAD); 1480 1481 /* If the last TD is not marked active we can complete */ 1482 if (!(status & UHCI_TD_ACTIVE)) { 1483 done: 1484 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1485 1486 callout_stop(&xfer->ux_callout); 1487 uhci_idone(ux, cqp); 1488 return; 1489 } 1490 1491 /* 1492 * If the last TD is still active we need to check whether there 1493 * is an error somewhere in the middle, or whether there was a 1494 * short packet (SPD and not ACTIVE). 1495 */ 1496 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1497 for (std = fstd; std != lstd; std = std->link.std) { 1498 usb_syncmem(&std->dma, 1499 std->offs + offsetof(uhci_td_t, td_status), 1500 sizeof(std->td.td_status), 1501 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1502 status = le32toh(std->td.td_status); 1503 usb_syncmem(&std->dma, 1504 std->offs + offsetof(uhci_td_t, td_status), 1505 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1506 1507 /* If there's an active TD the xfer isn't done. */ 1508 if (status & UHCI_TD_ACTIVE) { 1509 DPRINTFN(12, "ux=%p std=%p still active", 1510 ux, std, 0, 0); 1511 return; 1512 } 1513 1514 /* Any kind of error makes the xfer done. */ 1515 if (status & UHCI_TD_STALLED) 1516 goto done; 1517 1518 /* 1519 * If the data phase of a control transfer is short, we need 1520 * to complete the status stage 1521 */ 1522 1523 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1524 struct uhci_pipe *upipe = 1525 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1526 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1527 uhci_soft_td_t *stat = upipe->ctrl.stat; 1528 1529 DPRINTFN(12, "ux=%p std=%p control status" 1530 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1531 1532 sqh->qh.qh_elink = 1533 htole32(stat->physaddr | UHCI_PTR_TD); 1534 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1535 BUS_DMASYNC_PREWRITE); 1536 break; 1537 } 1538 1539 /* We want short packets, and it is short: it's done */ 1540 usb_syncmem(&std->dma, 1541 std->offs + offsetof(uhci_td_t, td_token), 1542 sizeof(std->td.td_token), 1543 BUS_DMASYNC_POSTWRITE); 1544 1545 if ((status & UHCI_TD_SPD) && 1546 UHCI_TD_GET_ACTLEN(status) < 1547 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1548 goto done; 1549 } 1550 } 1551 } 1552 1553 /* Called with USB lock held. */ 1554 void 1555 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1556 { 1557 struct usbd_xfer *xfer = &ux->ux_xfer; 1558 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1559 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1560 uhci_soft_td_t *std; 1561 uint32_t status = 0, nstatus; 1562 int actlen; 1563 1564 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1565 1566 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1567 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1568 1569 #ifdef DIAGNOSTIC 1570 #ifdef UHCI_DEBUG 1571 if (ux->ux_isdone) { 1572 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1573 uhci_dump_ii(ux); 1574 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1575 } 1576 #endif 1577 KASSERT(!ux->ux_isdone); 1578 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1579 ux->ux_type, xfer->ux_status); 1580 ux->ux_isdone = true; 1581 #endif 1582 1583 if (xfer->ux_nframes != 0) { 1584 /* Isoc transfer, do things differently. */ 1585 uhci_soft_td_t **stds = upipe->isoc.stds; 1586 int i, n, nframes, len; 1587 1588 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1589 1590 nframes = xfer->ux_nframes; 1591 actlen = 0; 1592 n = ux->ux_curframe; 1593 for (i = 0; i < nframes; i++) { 1594 std = stds[n]; 1595 #ifdef UHCI_DEBUG 1596 if (uhcidebug >= 5) { 1597 DPRINTF("isoc TD %d", i, 0, 0, 0); 1598 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1599 uhci_dump_td(std); 1600 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1601 } 1602 #endif 1603 if (++n >= UHCI_VFRAMELIST_COUNT) 1604 n = 0; 1605 usb_syncmem(&std->dma, 1606 std->offs + offsetof(uhci_td_t, td_status), 1607 sizeof(std->td.td_status), 1608 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1609 status = le32toh(std->td.td_status); 1610 len = UHCI_TD_GET_ACTLEN(status); 1611 xfer->ux_frlengths[i] = len; 1612 actlen += len; 1613 } 1614 upipe->isoc.inuse -= nframes; 1615 xfer->ux_actlen = actlen; 1616 xfer->ux_status = USBD_NORMAL_COMPLETION; 1617 goto end; 1618 } 1619 1620 #ifdef UHCI_DEBUG 1621 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1622 if (uhcidebug >= 10) { 1623 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1624 uhci_dump_tds(ux->ux_stdstart); 1625 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1626 } 1627 #endif 1628 1629 /* The transfer is done, compute actual length and status. */ 1630 actlen = 0; 1631 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1632 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1633 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1634 nstatus = le32toh(std->td.td_status); 1635 if (nstatus & UHCI_TD_ACTIVE) 1636 break; 1637 1638 status = nstatus; 1639 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1640 UHCI_TD_PID_SETUP) 1641 actlen += UHCI_TD_GET_ACTLEN(status); 1642 else { 1643 /* 1644 * UHCI will report CRCTO in addition to a STALL or NAK 1645 * for a SETUP transaction. See section 3.2.2, "TD 1646 * CONTROL AND STATUS". 1647 */ 1648 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1649 status &= ~UHCI_TD_CRCTO; 1650 } 1651 } 1652 /* If there are left over TDs we need to update the toggle. */ 1653 if (std != NULL) 1654 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1655 1656 status &= UHCI_TD_ERROR; 1657 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1658 xfer->ux_actlen = actlen; 1659 if (status != 0) { 1660 1661 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1662 "error, addr=%d, endpt=0x%02x", 1663 xfer->ux_pipe->up_dev->ud_addr, 1664 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1665 0, 0); 1666 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1667 "bitstuff=%d crcto =%d nak =%d babble =%d", 1668 !!(status & UHCI_TD_BITSTUFF), 1669 !!(status & UHCI_TD_CRCTO), 1670 !!(status & UHCI_TD_NAK), 1671 !!(status & UHCI_TD_BABBLE)); 1672 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1673 "dbuffer =%d stalled =%d active =%d", 1674 !!(status & UHCI_TD_DBUFFER), 1675 !!(status & UHCI_TD_STALLED), 1676 !!(status & UHCI_TD_ACTIVE), 1677 0); 1678 1679 if (status == UHCI_TD_STALLED) 1680 xfer->ux_status = USBD_STALLED; 1681 else 1682 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1683 } else { 1684 xfer->ux_status = USBD_NORMAL_COMPLETION; 1685 } 1686 1687 end: 1688 uhci_del_intr_list(sc, ux); 1689 if (cqp) 1690 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1691 1692 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1693 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1694 } 1695 1696 /* 1697 * Called when a request does not complete. 1698 */ 1699 void 1700 uhci_timeout(void *addr) 1701 { 1702 struct usbd_xfer *xfer = addr; 1703 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1704 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1705 1706 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1707 1708 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1709 1710 if (sc->sc_dying) { 1711 mutex_enter(&sc->sc_lock); 1712 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1713 mutex_exit(&sc->sc_lock); 1714 return; 1715 } 1716 1717 /* Execute the abort in a process context. */ 1718 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1719 USB_TASKQ_MPSAFE); 1720 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1721 USB_TASKQ_HC); 1722 } 1723 1724 void 1725 uhci_timeout_task(void *addr) 1726 { 1727 struct usbd_xfer *xfer = addr; 1728 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1729 1730 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1731 1732 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1733 1734 mutex_enter(&sc->sc_lock); 1735 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1736 mutex_exit(&sc->sc_lock); 1737 } 1738 1739 /* 1740 * Wait here until controller claims to have an interrupt. 1741 * Then call uhci_intr and return. Use timeout to avoid waiting 1742 * too long. 1743 * Only used during boot when interrupts are not enabled yet. 1744 */ 1745 void 1746 uhci_waitintr(uhci_softc_t *sc, struct usbd_xfer *xfer) 1747 { 1748 int timo = xfer->ux_timeout; 1749 struct uhci_xfer *ux; 1750 1751 mutex_enter(&sc->sc_lock); 1752 1753 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1754 DPRINTFN(10, "timeout = %dms", timo, 0, 0, 0); 1755 1756 xfer->ux_status = USBD_IN_PROGRESS; 1757 for (; timo >= 0; timo--) { 1758 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_lock); 1759 DPRINTFN(20, "0x%04x", 1760 UREAD2(sc, UHCI_STS), 0, 0, 0); 1761 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1762 mutex_spin_enter(&sc->sc_intr_lock); 1763 uhci_intr1(sc); 1764 mutex_spin_exit(&sc->sc_intr_lock); 1765 if (xfer->ux_status != USBD_IN_PROGRESS) 1766 goto done; 1767 } 1768 } 1769 1770 /* Timeout */ 1771 DPRINTF("timeout", 0, 0, 0, 0); 1772 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 1773 if (&ux->ux_xfer == xfer) 1774 break; 1775 1776 KASSERT(ux != NULL); 1777 1778 uhci_idone(ux, NULL); 1779 usb_transfer_complete(&ux->ux_xfer); 1780 1781 done: 1782 mutex_exit(&sc->sc_lock); 1783 } 1784 1785 void 1786 uhci_poll(struct usbd_bus *bus) 1787 { 1788 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1789 1790 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1791 mutex_spin_enter(&sc->sc_intr_lock); 1792 uhci_intr1(sc); 1793 mutex_spin_exit(&sc->sc_intr_lock); 1794 } 1795 } 1796 1797 void 1798 uhci_reset(uhci_softc_t *sc) 1799 { 1800 int n; 1801 1802 UHCICMD(sc, UHCI_CMD_HCRESET); 1803 /* The reset bit goes low when the controller is done. */ 1804 for (n = 0; n < UHCI_RESET_TIMEOUT && 1805 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1806 usb_delay_ms(&sc->sc_bus, 1); 1807 if (n >= UHCI_RESET_TIMEOUT) 1808 printf("%s: controller did not reset\n", 1809 device_xname(sc->sc_dev)); 1810 } 1811 1812 usbd_status 1813 uhci_run(uhci_softc_t *sc, int run, int locked) 1814 { 1815 int n, running; 1816 uint16_t cmd; 1817 1818 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1819 1820 run = run != 0; 1821 if (!locked) 1822 mutex_spin_enter(&sc->sc_intr_lock); 1823 1824 DPRINTF("setting run=%d", run, 0, 0, 0); 1825 cmd = UREAD2(sc, UHCI_CMD); 1826 if (run) 1827 cmd |= UHCI_CMD_RS; 1828 else 1829 cmd &= ~UHCI_CMD_RS; 1830 UHCICMD(sc, cmd); 1831 for (n = 0; n < 10; n++) { 1832 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1833 /* return when we've entered the state we want */ 1834 if (run == running) { 1835 if (!locked) 1836 mutex_spin_exit(&sc->sc_intr_lock); 1837 DPRINTF("done cmd=0x%x sts=0x%x", 1838 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1839 return USBD_NORMAL_COMPLETION; 1840 } 1841 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1842 } 1843 if (!locked) 1844 mutex_spin_exit(&sc->sc_intr_lock); 1845 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1846 run ? "start" : "stop"); 1847 return USBD_IOERROR; 1848 } 1849 1850 /* 1851 * Memory management routines. 1852 * uhci_alloc_std allocates TDs 1853 * uhci_alloc_sqh allocates QHs 1854 * These two routines do their own free list management, 1855 * partly for speed, partly because allocating DMAable memory 1856 * has page size granularity so much memory would be wasted if 1857 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1858 */ 1859 1860 uhci_soft_td_t * 1861 uhci_alloc_std(uhci_softc_t *sc) 1862 { 1863 uhci_soft_td_t *std; 1864 usbd_status err; 1865 int i, offs; 1866 usb_dma_t dma; 1867 1868 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1869 1870 mutex_enter(&sc->sc_lock); 1871 if (sc->sc_freetds == NULL) { 1872 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1873 mutex_exit(&sc->sc_lock); 1874 1875 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1876 UHCI_TD_ALIGN, &dma); 1877 if (err) 1878 return NULL; 1879 1880 mutex_enter(&sc->sc_lock); 1881 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1882 offs = i * UHCI_STD_SIZE; 1883 std = KERNADDR(&dma, offs); 1884 std->physaddr = DMAADDR(&dma, offs); 1885 std->dma = dma; 1886 std->offs = offs; 1887 std->link.std = sc->sc_freetds; 1888 sc->sc_freetds = std; 1889 } 1890 } 1891 std = sc->sc_freetds; 1892 sc->sc_freetds = std->link.std; 1893 mutex_exit(&sc->sc_lock); 1894 1895 memset(&std->td, 0, sizeof(uhci_td_t)); 1896 1897 return std; 1898 } 1899 1900 #define TD_IS_FREE 0x12345678 1901 1902 void 1903 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1904 { 1905 KASSERT(mutex_owned(&sc->sc_lock)); 1906 1907 #ifdef DIAGNOSTIC 1908 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1909 printf("%s: freeing free TD %p\n", __func__, std); 1910 return; 1911 } 1912 std->td.td_token = htole32(TD_IS_FREE); 1913 #endif 1914 1915 std->link.std = sc->sc_freetds; 1916 sc->sc_freetds = std; 1917 } 1918 1919 void 1920 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1921 { 1922 mutex_enter(&sc->sc_lock); 1923 uhci_free_std_locked(sc, std); 1924 mutex_exit(&sc->sc_lock); 1925 } 1926 1927 uhci_soft_qh_t * 1928 uhci_alloc_sqh(uhci_softc_t *sc) 1929 { 1930 uhci_soft_qh_t *sqh; 1931 usbd_status err; 1932 int i, offs; 1933 usb_dma_t dma; 1934 1935 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1936 1937 mutex_enter(&sc->sc_lock); 1938 if (sc->sc_freeqhs == NULL) { 1939 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1940 mutex_exit(&sc->sc_lock); 1941 1942 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1943 UHCI_QH_ALIGN, &dma); 1944 if (err) 1945 return NULL; 1946 1947 mutex_enter(&sc->sc_lock); 1948 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1949 offs = i * UHCI_SQH_SIZE; 1950 sqh = KERNADDR(&dma, offs); 1951 sqh->physaddr = DMAADDR(&dma, offs); 1952 sqh->dma = dma; 1953 sqh->offs = offs; 1954 sqh->hlink = sc->sc_freeqhs; 1955 sc->sc_freeqhs = sqh; 1956 } 1957 } 1958 sqh = sc->sc_freeqhs; 1959 sc->sc_freeqhs = sqh->hlink; 1960 mutex_exit(&sc->sc_lock); 1961 1962 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1963 1964 return sqh; 1965 } 1966 1967 void 1968 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1969 { 1970 KASSERT(mutex_owned(&sc->sc_lock)); 1971 1972 sqh->hlink = sc->sc_freeqhs; 1973 sc->sc_freeqhs = sqh; 1974 } 1975 1976 #if 0 1977 void 1978 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1979 uhci_soft_td_t *stdend) 1980 { 1981 uhci_soft_td_t *p; 1982 uint32_t td_link; 1983 1984 /* 1985 * to avoid race condition with the controller which may be looking 1986 * at this chain, we need to first invalidate all links, and 1987 * then wait for the controller to move to another queue 1988 */ 1989 for (p = std; p != stdend; p = p->link.std) { 1990 usb_syncmem(&p->dma, 1991 p->offs + offsetof(uhci_td_t, td_link), 1992 sizeof(p->td.td_link), 1993 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1994 td_link = le32toh(p->td.td_link); 1995 usb_syncmem(&p->dma, 1996 p->offs + offsetof(uhci_td_t, td_link), 1997 sizeof(p->td.td_link), 1998 BUS_DMASYNC_PREREAD); 1999 if ((td_link & UHCI_PTR_T) == 0) { 2000 p->td.td_link = htole32(UHCI_PTR_T); 2001 usb_syncmem(&p->dma, 2002 p->offs + offsetof(uhci_td_t, td_link), 2003 sizeof(p->td.td_link), 2004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2005 } 2006 } 2007 delay(UHCI_QH_REMOVE_DELAY); 2008 2009 for (; std != stdend; std = p) { 2010 p = std->link.std; 2011 uhci_free_std(sc, std); 2012 } 2013 } 2014 #endif 2015 2016 usbd_status 2017 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len, 2018 int rd, uhci_soft_td_t **sp) 2019 { 2020 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2021 uint16_t flags = xfer->ux_flags; 2022 uhci_soft_td_t *p; 2023 2024 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2025 2026 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 2027 2028 ASSERT_SLEEPABLE(); 2029 KASSERT(sp); 2030 2031 int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2032 if (maxp == 0) { 2033 printf("%s: maxp=0\n", __func__); 2034 return USBD_INVAL; 2035 } 2036 size_t ntd = (len + maxp - 1) / maxp; 2037 if (!rd && (flags & USBD_FORCE_SHORT_XFER)) { 2038 ntd++; 2039 } 2040 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 2041 2042 uxfer->ux_stds = NULL; 2043 uxfer->ux_nstd = ntd; 2044 p = NULL; 2045 if (ntd == 0) { 2046 *sp = NULL; 2047 DPRINTF("ntd=0", 0, 0, 0, 0); 2048 return USBD_NORMAL_COMPLETION; 2049 } 2050 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2051 KM_SLEEP); 2052 2053 ntd--; 2054 for (int i = ntd; i >= 0; i--) { 2055 p = uhci_alloc_std(sc); 2056 if (p == NULL) { 2057 uhci_free_stds(sc, uxfer); 2058 return USBD_NOMEM; 2059 } 2060 uxfer->ux_stds[i] = p; 2061 } 2062 2063 *sp = uxfer->ux_stds[0]; 2064 2065 return USBD_NORMAL_COMPLETION; 2066 } 2067 2068 Static void 2069 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2070 { 2071 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2072 2073 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2074 2075 mutex_enter(&sc->sc_lock); 2076 for (size_t i = 0; i < ux->ux_nstd; i++) { 2077 uhci_soft_td_t *std = ux->ux_stds[i]; 2078 #ifdef DIAGNOSTIC 2079 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2080 printf("%s: freeing free TD %p\n", __func__, std); 2081 return; 2082 } 2083 std->td.td_token = htole32(TD_IS_FREE); 2084 #endif 2085 ux->ux_stds[i]->link.std = sc->sc_freetds; 2086 sc->sc_freetds = std; 2087 } 2088 mutex_exit(&sc->sc_lock); 2089 } 2090 2091 2092 Static void 2093 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2094 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2095 { 2096 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2097 struct usbd_pipe *pipe = xfer->ux_pipe; 2098 usb_dma_t *dma = &xfer->ux_dmabuf; 2099 uint16_t flags = xfer->ux_flags; 2100 uhci_soft_td_t *std, *prev; 2101 int len = length; 2102 int tog = *toggle; 2103 int maxp; 2104 uint32_t status; 2105 size_t i; 2106 2107 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2108 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2109 len, isread, *toggle); 2110 2111 KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2112 2113 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2114 KASSERT(maxp != 0); 2115 2116 int addr = xfer->ux_pipe->up_dev->ud_addr; 2117 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2118 2119 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2120 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2121 status |= UHCI_TD_LS; 2122 if (flags & USBD_SHORT_XFER_OK) 2123 status |= UHCI_TD_SPD; 2124 usb_syncmem(dma, 0, len, 2125 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2126 std = prev = NULL; 2127 for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) { 2128 int l = len; 2129 std = uxfer->ux_stds[i]; 2130 if (l > maxp) 2131 l = maxp; 2132 2133 if (prev) { 2134 prev->link.std = std; 2135 prev->td.td_link = htole32( 2136 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2137 ); 2138 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2140 } 2141 2142 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2144 2145 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2146 std->td.td_status = htole32(status); 2147 std->td.td_token = htole32( 2148 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2149 UHCI_TD_SET_DEVADDR(addr) | 2150 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2151 UHCI_TD_SET_DT(tog) | 2152 UHCI_TD_SET_MAXLEN(l) 2153 ); 2154 std->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2155 2156 std->link.std = NULL; 2157 2158 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2159 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2160 tog ^= 1; 2161 2162 len -= l; 2163 } 2164 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2165 xfer, length, len, maxp, uxfer->ux_nstd, i); 2166 2167 if (!isread && 2168 (flags & USBD_FORCE_SHORT_XFER) && 2169 length % maxp == 0) { 2170 /* Force a 0 length transfer at the end. */ 2171 KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i, 2172 uxfer->ux_nstd); 2173 std = uxfer->ux_stds[i++]; 2174 2175 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2176 std->td.td_status = htole32(status); 2177 std->td.td_token = htole32( 2178 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2179 UHCI_TD_SET_DEVADDR(addr) | 2180 UHCI_TD_SET_PID(UHCI_TD_PID_OUT) | 2181 UHCI_TD_SET_DT(tog) | 2182 UHCI_TD_SET_MAXLEN(0) 2183 ); 2184 std->td.td_buffer = 0; 2185 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2186 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2187 2188 std->link.std = NULL; 2189 if (prev) { 2190 prev->link.std = std; 2191 prev->td.td_link = htole32( 2192 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2193 ); 2194 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2196 } 2197 tog ^= 1; 2198 } 2199 *lstd = std; 2200 *toggle = tog; 2201 } 2202 2203 void 2204 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2205 { 2206 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2207 upipe->nexttoggle = 0; 2208 } 2209 2210 void 2211 uhci_noop(struct usbd_pipe *pipe) 2212 { 2213 } 2214 2215 int 2216 uhci_device_bulk_init(struct usbd_xfer *xfer) 2217 { 2218 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2219 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2220 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2221 int endpt = ed->bEndpointAddress; 2222 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2223 int len = xfer->ux_bufsize; 2224 int err = 0; 2225 2226 2227 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2228 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2229 2230 if (sc->sc_dying) 2231 return USBD_IOERROR; 2232 2233 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2234 2235 uxfer->ux_type = UX_BULK; 2236 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart); 2237 if (err) 2238 return err; 2239 2240 #ifdef UHCI_DEBUG 2241 if (uhcidebug >= 10) { 2242 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2243 uhci_dump_tds(uxfer->ux_stdstart); 2244 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2245 } 2246 #endif 2247 2248 return 0; 2249 } 2250 2251 Static void 2252 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2253 { 2254 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2255 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2256 2257 KASSERT(ux->ux_type == UX_BULK); 2258 2259 uhci_free_stds(sc, ux); 2260 if (ux->ux_nstd) 2261 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2262 } 2263 2264 usbd_status 2265 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2266 { 2267 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2268 usbd_status err; 2269 2270 /* Insert last in queue. */ 2271 mutex_enter(&sc->sc_lock); 2272 err = usb_insert_transfer(xfer); 2273 mutex_exit(&sc->sc_lock); 2274 if (err) 2275 return err; 2276 2277 /* 2278 * Pipe isn't running (otherwise err would be USBD_INPROG), 2279 * so start it first. 2280 */ 2281 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2282 } 2283 2284 usbd_status 2285 uhci_device_bulk_start(struct usbd_xfer *xfer) 2286 { 2287 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2288 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2289 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2290 uhci_soft_td_t *data, *dataend; 2291 uhci_soft_qh_t *sqh; 2292 int len; 2293 int endpt; 2294 int isread; 2295 2296 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2297 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2298 xfer->ux_flags, 0); 2299 2300 if (sc->sc_dying) 2301 return USBD_IOERROR; 2302 2303 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2304 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2305 2306 len = xfer->ux_length; 2307 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2308 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2309 sqh = upipe->bulk.sqh; 2310 2311 /* Take lock here to protect nexttoggle */ 2312 mutex_enter(&sc->sc_lock); 2313 2314 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2315 &dataend); 2316 2317 data = ux->ux_stdstart; 2318 ux->ux_stdend = dataend; 2319 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2320 usb_syncmem(&dataend->dma, 2321 dataend->offs + offsetof(uhci_td_t, td_status), 2322 sizeof(dataend->td.td_status), 2323 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2324 2325 #ifdef UHCI_DEBUG 2326 if (uhcidebug >= 10) { 2327 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2328 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2329 uhci_dump_tds(data); 2330 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2331 } 2332 #endif 2333 2334 KASSERT(ux->ux_isdone); 2335 #ifdef DIAGNOSTIC 2336 ux->ux_isdone = false; 2337 #endif 2338 2339 sqh->elink = data; 2340 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2341 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2342 2343 uhci_add_bulk(sc, sqh); 2344 uhci_add_intr_list(sc, ux); 2345 2346 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2347 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2348 uhci_timeout, xfer); 2349 } 2350 xfer->ux_status = USBD_IN_PROGRESS; 2351 mutex_exit(&sc->sc_lock); 2352 2353 if (sc->sc_bus.ub_usepolling) 2354 uhci_waitintr(sc, xfer); 2355 2356 return USBD_IN_PROGRESS; 2357 } 2358 2359 /* Abort a device bulk request. */ 2360 void 2361 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2362 { 2363 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2364 2365 KASSERT(mutex_owned(&sc->sc_lock)); 2366 2367 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2368 2369 uhci_abort_xfer(xfer, USBD_CANCELLED); 2370 } 2371 2372 /* 2373 * Abort a device request. 2374 * If this routine is called at splusb() it guarantees that the request 2375 * will be removed from the hardware scheduling and that the callback 2376 * for it will be called with USBD_CANCELLED status. 2377 * It's impossible to guarantee that the requested transfer will not 2378 * have happened since the hardware runs concurrently. 2379 * If the transaction has already happened we rely on the ordinary 2380 * interrupt processing to process it. 2381 * XXX This is most probably wrong. 2382 * XXXMRG this doesn't make sense anymore. 2383 */ 2384 void 2385 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2386 { 2387 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2388 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2389 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2390 uhci_soft_td_t *std; 2391 int wake; 2392 2393 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2394 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2395 2396 KASSERT(mutex_owned(&sc->sc_lock)); 2397 ASSERT_SLEEPABLE(); 2398 2399 if (sc->sc_dying) { 2400 /* If we're dying, just do the software part. */ 2401 xfer->ux_status = status; /* make software ignore it */ 2402 callout_stop(&xfer->ux_callout); 2403 usb_transfer_complete(xfer); 2404 return; 2405 } 2406 2407 /* 2408 * If an abort is already in progress then just wait for it to 2409 * complete and return. 2410 */ 2411 if (xfer->ux_hcflags & UXFER_ABORTING) { 2412 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2413 #ifdef DIAGNOSTIC 2414 if (status == USBD_TIMEOUT) 2415 printf("%s: TIMEOUT while aborting\n", __func__); 2416 #endif 2417 /* Override the status which might be USBD_TIMEOUT. */ 2418 xfer->ux_status = status; 2419 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2420 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2421 while (xfer->ux_hcflags & UXFER_ABORTING) 2422 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2423 goto done; 2424 } 2425 xfer->ux_hcflags |= UXFER_ABORTING; 2426 2427 /* 2428 * Step 1: Make interrupt routine and hardware ignore xfer. 2429 */ 2430 xfer->ux_status = status; /* make software ignore it */ 2431 callout_stop(&xfer->ux_callout); 2432 uhci_del_intr_list(sc, ux); 2433 2434 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2435 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2436 usb_syncmem(&std->dma, 2437 std->offs + offsetof(uhci_td_t, td_status), 2438 sizeof(std->td.td_status), 2439 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2440 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2441 usb_syncmem(&std->dma, 2442 std->offs + offsetof(uhci_td_t, td_status), 2443 sizeof(std->td.td_status), 2444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2445 } 2446 2447 /* 2448 * Step 2: Wait until we know hardware has finished any possible 2449 * use of the xfer. Also make sure the soft interrupt routine 2450 * has run. 2451 */ 2452 /* Hardware finishes in 1ms */ 2453 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2454 sc->sc_softwake = 1; 2455 usb_schedsoftintr(&sc->sc_bus); 2456 DPRINTF("cv_wait", 0, 0, 0, 0); 2457 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2458 2459 /* 2460 * Step 3: Execute callback. 2461 */ 2462 DPRINTF("callback", 0, 0, 0, 0); 2463 #ifdef DIAGNOSTIC 2464 ux->ux_isdone = true; 2465 #endif 2466 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2467 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2468 usb_transfer_complete(xfer); 2469 if (wake) 2470 cv_broadcast(&xfer->ux_hccv); 2471 done: 2472 KASSERT(mutex_owned(&sc->sc_lock)); 2473 } 2474 2475 /* Close a device bulk pipe. */ 2476 void 2477 uhci_device_bulk_close(struct usbd_pipe *pipe) 2478 { 2479 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2480 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2481 2482 KASSERT(mutex_owned(&sc->sc_lock)); 2483 2484 uhci_free_sqh(sc, upipe->bulk.sqh); 2485 2486 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2487 } 2488 2489 int 2490 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2491 { 2492 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2493 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2494 usb_device_request_t *req = &xfer->ux_request; 2495 struct usbd_device *dev = upipe->pipe.up_dev; 2496 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2497 uhci_soft_td_t *data; 2498 int len; 2499 usbd_status err; 2500 int isread; 2501 2502 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2503 DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize, 2504 dev->ud_addr, upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2505 2506 isread = req->bmRequestType & UT_READ; 2507 len = xfer->ux_bufsize; 2508 2509 uxfer->ux_type = UX_CTRL; 2510 /* Set up data transaction */ 2511 if (len != 0) { 2512 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data); 2513 if (err) 2514 return err; 2515 } 2516 /* Set up interrupt info. */ 2517 uxfer->ux_setup = upipe->ctrl.setup; 2518 uxfer->ux_stat = upipe->ctrl.stat; 2519 uxfer->ux_data = data; 2520 2521 return 0; 2522 } 2523 2524 Static void 2525 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2526 { 2527 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2528 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2529 2530 KASSERT(ux->ux_type == UX_CTRL); 2531 2532 uhci_free_stds(sc, ux); 2533 if (ux->ux_nstd) 2534 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2535 } 2536 2537 usbd_status 2538 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2539 { 2540 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2541 usbd_status err; 2542 2543 /* Insert last in queue. */ 2544 mutex_enter(&sc->sc_lock); 2545 err = usb_insert_transfer(xfer); 2546 mutex_exit(&sc->sc_lock); 2547 if (err) 2548 return err; 2549 2550 /* 2551 * Pipe isn't running (otherwise err would be USBD_INPROG), 2552 * so start it first. 2553 */ 2554 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2555 } 2556 2557 usbd_status 2558 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2559 { 2560 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2561 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2562 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2563 usb_device_request_t *req = &xfer->ux_request; 2564 struct usbd_device *dev = upipe->pipe.up_dev; 2565 int addr = dev->ud_addr; 2566 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2567 uhci_soft_td_t *setup, *stat, *next, *dataend; 2568 uhci_soft_qh_t *sqh; 2569 int len; 2570 int isread; 2571 2572 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2573 2574 if (sc->sc_dying) 2575 return USBD_IOERROR; 2576 2577 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2578 2579 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2580 "wValue=0x%04x, wIndex=0x%04x", 2581 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2582 UGETW(req->wIndex)); 2583 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2584 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2585 2586 isread = req->bmRequestType & UT_READ; 2587 len = UGETW(req->wLength); 2588 2589 setup = upipe->ctrl.setup; 2590 stat = upipe->ctrl.stat; 2591 sqh = upipe->ctrl.sqh; 2592 2593 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2594 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2595 2596 mutex_enter(&sc->sc_lock); 2597 2598 /* Set up data transaction */ 2599 if (len != 0) { 2600 upipe->nexttoggle = 1; 2601 next = uxfer->ux_data; 2602 uhci_reset_std_chain(sc, xfer, len, isread, 2603 &upipe->nexttoggle, &dataend); 2604 dataend->link.std = stat; 2605 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2606 usb_syncmem(&dataend->dma, 2607 dataend->offs + offsetof(uhci_td_t, td_link), 2608 sizeof(dataend->td.td_link), 2609 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2610 } else { 2611 next = stat; 2612 } 2613 2614 const uint32_t status = UHCI_TD_ZERO_ACTLEN( 2615 UHCI_TD_SET_ERRCNT(3) | 2616 UHCI_TD_ACTIVE | 2617 (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0) 2618 ); 2619 setup->link.std = next; 2620 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2621 setup->td.td_status = htole32(status); 2622 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2623 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2624 2625 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2626 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2627 2628 stat->link.std = NULL; 2629 stat->td.td_link = htole32(UHCI_PTR_T); 2630 stat->td.td_status = htole32(status | UHCI_TD_IOC); 2631 stat->td.td_token = 2632 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2633 UHCI_TD_IN (0, endpt, addr, 1)); 2634 stat->td.td_buffer = htole32(0); 2635 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2636 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2637 2638 #ifdef UHCI_DEBUG 2639 if (uhcidebug >= 10) { 2640 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2641 DPRINTF("before transfer", 0, 0, 0, 0); 2642 uhci_dump_tds(setup); 2643 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2644 } 2645 #endif 2646 2647 /* Set up interrupt info. */ 2648 uxfer->ux_setup = setup; 2649 uxfer->ux_stat = stat; 2650 KASSERT(uxfer->ux_isdone); 2651 #ifdef DIAGNOSTIC 2652 uxfer->ux_isdone = false; 2653 #endif 2654 2655 sqh->elink = setup; 2656 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2657 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2658 2659 if (dev->ud_speed == USB_SPEED_LOW) 2660 uhci_add_ls_ctrl(sc, sqh); 2661 else 2662 uhci_add_hs_ctrl(sc, sqh); 2663 uhci_add_intr_list(sc, uxfer); 2664 #ifdef UHCI_DEBUG 2665 if (uhcidebug >= 12) { 2666 uhci_soft_td_t *std; 2667 uhci_soft_qh_t *xqh; 2668 uhci_soft_qh_t *sxqh; 2669 int maxqh = 0; 2670 uhci_physaddr_t link; 2671 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2672 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2673 for (std = sc->sc_vframes[0].htd, link = 0; 2674 (link & UHCI_PTR_QH) == 0; 2675 std = std->link.std) { 2676 link = le32toh(std->td.td_link); 2677 uhci_dump_td(std); 2678 } 2679 sxqh = (uhci_soft_qh_t *)std; 2680 uhci_dump_qh(sxqh); 2681 for (xqh = sxqh; 2682 xqh != NULL; 2683 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2684 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2685 uhci_dump_qh(xqh); 2686 } 2687 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2688 uhci_dump_qh(sqh); 2689 uhci_dump_tds(sqh->elink); 2690 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2691 } 2692 #endif 2693 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2694 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2695 uhci_timeout, xfer); 2696 } 2697 xfer->ux_status = USBD_IN_PROGRESS; 2698 mutex_exit(&sc->sc_lock); 2699 2700 if (sc->sc_bus.ub_usepolling) 2701 uhci_waitintr(sc, xfer); 2702 2703 return USBD_IN_PROGRESS; 2704 } 2705 2706 int 2707 uhci_device_intr_init(struct usbd_xfer *xfer) 2708 { 2709 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2710 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2711 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2712 int endpt = ed->bEndpointAddress; 2713 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2714 int len = xfer->ux_bufsize; 2715 int err; 2716 2717 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2718 2719 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2720 xfer->ux_flags, 0); 2721 2722 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2723 KASSERT(len != 0); 2724 2725 ux->ux_type = UX_INTR; 2726 ux->ux_nstd = 0; 2727 err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart); 2728 2729 return err; 2730 } 2731 2732 Static void 2733 uhci_device_intr_fini(struct usbd_xfer *xfer) 2734 { 2735 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2736 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2737 2738 KASSERT(ux->ux_type == UX_INTR); 2739 2740 uhci_free_stds(sc, ux); 2741 if (ux->ux_nstd) 2742 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2743 } 2744 2745 usbd_status 2746 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2747 { 2748 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2749 usbd_status err; 2750 2751 /* Insert last in queue. */ 2752 mutex_enter(&sc->sc_lock); 2753 err = usb_insert_transfer(xfer); 2754 mutex_exit(&sc->sc_lock); 2755 if (err) 2756 return err; 2757 2758 /* 2759 * Pipe isn't running (otherwise err would be USBD_INPROG), 2760 * so start it first. 2761 */ 2762 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2763 } 2764 2765 usbd_status 2766 uhci_device_intr_start(struct usbd_xfer *xfer) 2767 { 2768 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2769 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2770 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2771 uhci_soft_td_t *data, *dataend; 2772 uhci_soft_qh_t *sqh; 2773 int isread, endpt; 2774 int i; 2775 2776 if (sc->sc_dying) 2777 return USBD_IOERROR; 2778 2779 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2780 2781 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2782 xfer->ux_flags, 0); 2783 2784 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2785 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2786 2787 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2788 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2789 2790 data = ux->ux_stdstart; 2791 2792 KASSERT(ux->ux_isdone); 2793 #ifdef DIAGNOSTIC 2794 ux->ux_isdone = false; 2795 #endif 2796 2797 /* Take lock to protect nexttoggle */ 2798 mutex_enter(&sc->sc_lock); 2799 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2800 &upipe->nexttoggle, &dataend); 2801 2802 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2803 usb_syncmem(&dataend->dma, 2804 dataend->offs + offsetof(uhci_td_t, td_status), 2805 sizeof(dataend->td.td_status), 2806 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2807 ux->ux_stdend = dataend; 2808 2809 #ifdef UHCI_DEBUG 2810 if (uhcidebug >= 10) { 2811 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2812 uhci_dump_tds(data); 2813 uhci_dump_qh(upipe->intr.qhs[0]); 2814 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2815 } 2816 #endif 2817 2818 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2819 for (i = 0; i < upipe->intr.npoll; i++) { 2820 sqh = upipe->intr.qhs[i]; 2821 sqh->elink = data; 2822 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2823 usb_syncmem(&sqh->dma, 2824 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2825 sizeof(sqh->qh.qh_elink), 2826 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2827 } 2828 uhci_add_intr_list(sc, ux); 2829 xfer->ux_status = USBD_IN_PROGRESS; 2830 mutex_exit(&sc->sc_lock); 2831 2832 #ifdef UHCI_DEBUG 2833 if (uhcidebug >= 10) { 2834 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2835 uhci_dump_tds(data); 2836 uhci_dump_qh(upipe->intr.qhs[0]); 2837 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2838 } 2839 #endif 2840 2841 return USBD_IN_PROGRESS; 2842 } 2843 2844 /* Abort a device control request. */ 2845 void 2846 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2847 { 2848 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2849 2850 KASSERT(mutex_owned(&sc->sc_lock)); 2851 2852 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2853 uhci_abort_xfer(xfer, USBD_CANCELLED); 2854 } 2855 2856 /* Close a device control pipe. */ 2857 void 2858 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2859 { 2860 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2861 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2862 2863 uhci_free_sqh(sc, upipe->ctrl.sqh); 2864 uhci_free_std_locked(sc, upipe->ctrl.setup); 2865 uhci_free_std_locked(sc, upipe->ctrl.stat); 2866 2867 } 2868 2869 /* Abort a device interrupt request. */ 2870 void 2871 uhci_device_intr_abort(struct usbd_xfer *xfer) 2872 { 2873 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2874 2875 KASSERT(mutex_owned(&sc->sc_lock)); 2876 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2877 2878 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2879 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2880 2881 uhci_abort_xfer(xfer, USBD_CANCELLED); 2882 } 2883 2884 /* Close a device interrupt pipe. */ 2885 void 2886 uhci_device_intr_close(struct usbd_pipe *pipe) 2887 { 2888 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2889 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2890 int i, npoll; 2891 2892 KASSERT(mutex_owned(&sc->sc_lock)); 2893 2894 /* Unlink descriptors from controller data structures. */ 2895 npoll = upipe->intr.npoll; 2896 for (i = 0; i < npoll; i++) 2897 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2898 2899 /* 2900 * We now have to wait for any activity on the physical 2901 * descriptors to stop. 2902 */ 2903 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2904 2905 for (i = 0; i < npoll; i++) 2906 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2907 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2908 } 2909 2910 int 2911 uhci_device_isoc_init(struct usbd_xfer *xfer) 2912 { 2913 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2914 2915 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2916 KASSERT(xfer->ux_nframes != 0); 2917 KASSERT(ux->ux_isdone); 2918 2919 ux->ux_type = UX_ISOC; 2920 return 0; 2921 } 2922 2923 Static void 2924 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2925 { 2926 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2927 2928 KASSERT(ux->ux_type == UX_ISOC); 2929 } 2930 2931 usbd_status 2932 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2933 { 2934 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2935 usbd_status err __diagused; 2936 2937 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2938 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2939 2940 /* Put it on our queue, */ 2941 mutex_enter(&sc->sc_lock); 2942 err = usb_insert_transfer(xfer); 2943 mutex_exit(&sc->sc_lock); 2944 2945 KASSERT(err == USBD_NORMAL_COMPLETION); 2946 2947 /* insert into schedule, */ 2948 2949 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2950 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2951 struct isoc *isoc = &upipe->isoc; 2952 uhci_soft_td_t *std = NULL; 2953 uint32_t buf, len, status, offs; 2954 int i, next, nframes; 2955 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2956 2957 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2958 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2959 2960 if (sc->sc_dying) 2961 return USBD_IOERROR; 2962 2963 if (xfer->ux_status == USBD_IN_PROGRESS) { 2964 /* This request has already been entered into the frame list */ 2965 printf("%s: xfer=%p in frame list\n", __func__, xfer); 2966 /* XXX */ 2967 } 2968 2969 #ifdef DIAGNOSTIC 2970 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2971 printf("%s: overflow!\n", __func__); 2972 #endif 2973 2974 KASSERT(xfer->ux_nframes != 0); 2975 2976 mutex_enter(&sc->sc_lock); 2977 next = isoc->next; 2978 if (next == -1) { 2979 /* Not in use yet, schedule it a few frames ahead. */ 2980 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2981 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2982 } 2983 2984 xfer->ux_status = USBD_IN_PROGRESS; 2985 ux->ux_curframe = next; 2986 2987 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2988 offs = 0; 2989 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2990 UHCI_TD_ACTIVE | 2991 UHCI_TD_IOS); 2992 nframes = xfer->ux_nframes; 2993 for (i = 0; i < nframes; i++) { 2994 std = isoc->stds[next]; 2995 if (++next >= UHCI_VFRAMELIST_COUNT) 2996 next = 0; 2997 len = xfer->ux_frlengths[i]; 2998 std->td.td_buffer = htole32(buf); 2999 usb_syncmem(&xfer->ux_dmabuf, offs, len, 3000 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3001 if (i == nframes - 1) 3002 status |= UHCI_TD_IOC; 3003 std->td.td_status = htole32(status); 3004 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 3005 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 3006 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3007 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3008 #ifdef UHCI_DEBUG 3009 if (uhcidebug >= 5) { 3010 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3011 DPRINTF("TD %d", i, 0, 0, 0); 3012 uhci_dump_td(std); 3013 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3014 } 3015 #endif 3016 buf += len; 3017 offs += len; 3018 } 3019 isoc->next = next; 3020 isoc->inuse += xfer->ux_nframes; 3021 3022 /* Set up interrupt info. */ 3023 ux->ux_stdstart = std; 3024 ux->ux_stdend = std; 3025 3026 KASSERT(ux->ux_isdone); 3027 #ifdef DIAGNOSTIC 3028 ux->ux_isdone = false; 3029 #endif 3030 uhci_add_intr_list(sc, ux); 3031 3032 mutex_exit(&sc->sc_lock); 3033 3034 return USBD_IN_PROGRESS; 3035 } 3036 3037 void 3038 uhci_device_isoc_abort(struct usbd_xfer *xfer) 3039 { 3040 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3041 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3042 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3043 uhci_soft_td_t **stds = upipe->isoc.stds; 3044 uhci_soft_td_t *std; 3045 int i, n, nframes, maxlen, len; 3046 3047 KASSERT(mutex_owned(&sc->sc_lock)); 3048 3049 /* Transfer is already done. */ 3050 if (xfer->ux_status != USBD_NOT_STARTED && 3051 xfer->ux_status != USBD_IN_PROGRESS) { 3052 return; 3053 } 3054 3055 /* Give xfer the requested abort code. */ 3056 xfer->ux_status = USBD_CANCELLED; 3057 3058 /* make hardware ignore it, */ 3059 nframes = xfer->ux_nframes; 3060 n = ux->ux_curframe; 3061 maxlen = 0; 3062 for (i = 0; i < nframes; i++) { 3063 std = stds[n]; 3064 usb_syncmem(&std->dma, 3065 std->offs + offsetof(uhci_td_t, td_status), 3066 sizeof(std->td.td_status), 3067 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3068 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3069 usb_syncmem(&std->dma, 3070 std->offs + offsetof(uhci_td_t, td_status), 3071 sizeof(std->td.td_status), 3072 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3073 usb_syncmem(&std->dma, 3074 std->offs + offsetof(uhci_td_t, td_token), 3075 sizeof(std->td.td_token), 3076 BUS_DMASYNC_POSTWRITE); 3077 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3078 if (len > maxlen) 3079 maxlen = len; 3080 if (++n >= UHCI_VFRAMELIST_COUNT) 3081 n = 0; 3082 } 3083 3084 /* and wait until we are sure the hardware has finished. */ 3085 delay(maxlen); 3086 3087 #ifdef DIAGNOSTIC 3088 ux->ux_isdone = true; 3089 #endif 3090 /* Remove from interrupt list. */ 3091 uhci_del_intr_list(sc, ux); 3092 3093 /* Run callback. */ 3094 usb_transfer_complete(xfer); 3095 3096 KASSERT(mutex_owned(&sc->sc_lock)); 3097 } 3098 3099 void 3100 uhci_device_isoc_close(struct usbd_pipe *pipe) 3101 { 3102 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3103 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3104 uhci_soft_td_t *std, *vstd; 3105 struct isoc *isoc; 3106 int i; 3107 3108 KASSERT(mutex_owned(&sc->sc_lock)); 3109 3110 /* 3111 * Make sure all TDs are marked as inactive. 3112 * Wait for completion. 3113 * Unschedule. 3114 * Deallocate. 3115 */ 3116 isoc = &upipe->isoc; 3117 3118 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3119 std = isoc->stds[i]; 3120 usb_syncmem(&std->dma, 3121 std->offs + offsetof(uhci_td_t, td_status), 3122 sizeof(std->td.td_status), 3123 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3124 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3125 usb_syncmem(&std->dma, 3126 std->offs + offsetof(uhci_td_t, td_status), 3127 sizeof(std->td.td_status), 3128 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3129 } 3130 /* wait for completion */ 3131 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3132 3133 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3134 std = isoc->stds[i]; 3135 for (vstd = sc->sc_vframes[i].htd; 3136 vstd != NULL && vstd->link.std != std; 3137 vstd = vstd->link.std) 3138 ; 3139 if (vstd == NULL) { 3140 /*panic*/ 3141 printf("%s: %p not found\n", __func__, std); 3142 mutex_exit(&sc->sc_lock); 3143 return; 3144 } 3145 vstd->link = std->link; 3146 usb_syncmem(&std->dma, 3147 std->offs + offsetof(uhci_td_t, td_link), 3148 sizeof(std->td.td_link), 3149 BUS_DMASYNC_POSTWRITE); 3150 vstd->td.td_link = std->td.td_link; 3151 usb_syncmem(&vstd->dma, 3152 vstd->offs + offsetof(uhci_td_t, td_link), 3153 sizeof(vstd->td.td_link), 3154 BUS_DMASYNC_PREWRITE); 3155 uhci_free_std_locked(sc, std); 3156 } 3157 3158 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3159 } 3160 3161 usbd_status 3162 uhci_setup_isoc(struct usbd_pipe *pipe) 3163 { 3164 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3165 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3166 int addr = upipe->pipe.up_dev->ud_addr; 3167 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3168 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3169 uhci_soft_td_t *std, *vstd; 3170 uint32_t token; 3171 struct isoc *isoc; 3172 int i; 3173 3174 isoc = &upipe->isoc; 3175 3176 isoc->stds = kmem_alloc( 3177 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3178 if (isoc->stds == NULL) 3179 return USBD_NOMEM; 3180 3181 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3182 UHCI_TD_OUT(0, endpt, addr, 0); 3183 3184 /* Allocate the TDs and mark as inactive; */ 3185 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3186 std = uhci_alloc_std(sc); 3187 if (std == 0) 3188 goto bad; 3189 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3190 std->td.td_token = htole32(token); 3191 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3192 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3193 isoc->stds[i] = std; 3194 } 3195 3196 mutex_enter(&sc->sc_lock); 3197 3198 /* Insert TDs into schedule. */ 3199 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3200 std = isoc->stds[i]; 3201 vstd = sc->sc_vframes[i].htd; 3202 usb_syncmem(&vstd->dma, 3203 vstd->offs + offsetof(uhci_td_t, td_link), 3204 sizeof(vstd->td.td_link), 3205 BUS_DMASYNC_POSTWRITE); 3206 std->link = vstd->link; 3207 std->td.td_link = vstd->td.td_link; 3208 usb_syncmem(&std->dma, 3209 std->offs + offsetof(uhci_td_t, td_link), 3210 sizeof(std->td.td_link), 3211 BUS_DMASYNC_PREWRITE); 3212 vstd->link.std = std; 3213 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3214 usb_syncmem(&vstd->dma, 3215 vstd->offs + offsetof(uhci_td_t, td_link), 3216 sizeof(vstd->td.td_link), 3217 BUS_DMASYNC_PREWRITE); 3218 } 3219 mutex_exit(&sc->sc_lock); 3220 3221 isoc->next = -1; 3222 isoc->inuse = 0; 3223 3224 return USBD_NORMAL_COMPLETION; 3225 3226 bad: 3227 while (--i >= 0) 3228 uhci_free_std(sc, isoc->stds[i]); 3229 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3230 return USBD_NOMEM; 3231 } 3232 3233 void 3234 uhci_device_isoc_done(struct usbd_xfer *xfer) 3235 { 3236 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3237 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3238 int i, offs; 3239 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3240 3241 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3242 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3243 xfer->ux_actlen, xfer->ux_state, 0, 0); 3244 3245 #ifdef DIAGNOSTIC 3246 if (ux->ux_stdend == NULL) { 3247 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3248 #ifdef UHCI_DEBUG 3249 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3250 uhci_dump_ii(ux); 3251 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3252 #endif 3253 return; 3254 } 3255 #endif 3256 3257 /* Turn off the interrupt since it is active even if the TD is not. */ 3258 usb_syncmem(&ux->ux_stdend->dma, 3259 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3260 sizeof(ux->ux_stdend->td.td_status), 3261 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3262 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3263 usb_syncmem(&ux->ux_stdend->dma, 3264 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3265 sizeof(ux->ux_stdend->td.td_status), 3266 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3267 3268 offs = 0; 3269 for (i = 0; i < xfer->ux_nframes; i++) { 3270 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3271 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3272 offs += xfer->ux_frlengths[i]; 3273 } 3274 } 3275 3276 void 3277 uhci_device_intr_done(struct usbd_xfer *xfer) 3278 { 3279 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3280 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3281 uhci_soft_qh_t *sqh; 3282 int i, npoll; 3283 3284 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3285 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3286 3287 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3288 3289 npoll = upipe->intr.npoll; 3290 for (i = 0; i < npoll; i++) { 3291 sqh = upipe->intr.qhs[i]; 3292 sqh->elink = NULL; 3293 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3294 usb_syncmem(&sqh->dma, 3295 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3296 sizeof(sqh->qh.qh_elink), 3297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3298 } 3299 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3300 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3301 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3302 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3303 } 3304 3305 /* Deallocate request data structures */ 3306 void 3307 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3308 { 3309 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3310 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3311 int len = UGETW(xfer->ux_request.wLength); 3312 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3313 3314 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3315 3316 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3317 3318 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3319 3320 /* XXXNH move to uhci_idone??? */ 3321 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3322 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3323 else 3324 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3325 3326 if (len) { 3327 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3328 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3329 } 3330 usb_syncmem(&upipe->ctrl.reqdma, 0, 3331 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3332 3333 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3334 } 3335 3336 /* Deallocate request data structures */ 3337 void 3338 uhci_device_bulk_done(struct usbd_xfer *xfer) 3339 { 3340 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3341 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3342 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3343 int endpt = ed->bEndpointAddress; 3344 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3345 3346 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3347 DPRINTFN(5, "xfer=%p sc=%p upipe=%p", xfer, sc, upipe, 0); 3348 3349 KASSERT(mutex_owned(&sc->sc_lock)); 3350 3351 uhci_remove_bulk(sc, upipe->bulk.sqh); 3352 3353 if (xfer->ux_length) { 3354 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3355 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3356 } 3357 3358 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3359 } 3360 3361 /* Add interrupt QH, called with vflock. */ 3362 void 3363 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3364 { 3365 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3366 uhci_soft_qh_t *eqh; 3367 3368 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3369 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3370 3371 eqh = vf->eqh; 3372 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3373 sizeof(eqh->qh.qh_hlink), 3374 BUS_DMASYNC_POSTWRITE); 3375 sqh->hlink = eqh->hlink; 3376 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3377 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3378 sizeof(sqh->qh.qh_hlink), 3379 BUS_DMASYNC_PREWRITE); 3380 eqh->hlink = sqh; 3381 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3382 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3383 sizeof(eqh->qh.qh_hlink), 3384 BUS_DMASYNC_PREWRITE); 3385 vf->eqh = sqh; 3386 vf->bandwidth++; 3387 } 3388 3389 /* Remove interrupt QH. */ 3390 void 3391 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3392 { 3393 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3394 uhci_soft_qh_t *pqh; 3395 3396 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3397 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3398 3399 /* See comment in uhci_remove_ctrl() */ 3400 3401 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3402 sizeof(sqh->qh.qh_elink), 3403 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3404 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3405 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3406 usb_syncmem(&sqh->dma, 3407 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3408 sizeof(sqh->qh.qh_elink), 3409 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3410 delay(UHCI_QH_REMOVE_DELAY); 3411 } 3412 3413 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3414 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3415 sizeof(sqh->qh.qh_hlink), 3416 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3417 pqh->hlink = sqh->hlink; 3418 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3419 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3420 sizeof(pqh->qh.qh_hlink), 3421 BUS_DMASYNC_PREWRITE); 3422 delay(UHCI_QH_REMOVE_DELAY); 3423 if (vf->eqh == sqh) 3424 vf->eqh = pqh; 3425 vf->bandwidth--; 3426 } 3427 3428 usbd_status 3429 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3430 { 3431 uhci_soft_qh_t *sqh; 3432 int i, npoll; 3433 u_int bestbw, bw, bestoffs, offs; 3434 3435 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3436 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3437 if (ival == 0) { 3438 printf("%s: 0 interval\n", __func__); 3439 return USBD_INVAL; 3440 } 3441 3442 if (ival > UHCI_VFRAMELIST_COUNT) 3443 ival = UHCI_VFRAMELIST_COUNT; 3444 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3445 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3446 3447 upipe->intr.npoll = npoll; 3448 upipe->intr.qhs = 3449 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3450 if (upipe->intr.qhs == NULL) 3451 return USBD_NOMEM; 3452 3453 /* 3454 * Figure out which offset in the schedule that has most 3455 * bandwidth left over. 3456 */ 3457 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3458 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3459 for (bw = i = 0; i < npoll; i++) 3460 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3461 if (bw < bestbw) { 3462 bestbw = bw; 3463 bestoffs = offs; 3464 } 3465 } 3466 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3467 for (i = 0; i < npoll; i++) { 3468 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3469 sqh->elink = NULL; 3470 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3471 usb_syncmem(&sqh->dma, 3472 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3473 sizeof(sqh->qh.qh_elink), 3474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3475 sqh->pos = MOD(i * ival + bestoffs); 3476 } 3477 #undef MOD 3478 3479 mutex_enter(&sc->sc_lock); 3480 /* Enter QHs into the controller data structures. */ 3481 for (i = 0; i < npoll; i++) 3482 uhci_add_intr(sc, upipe->intr.qhs[i]); 3483 mutex_exit(&sc->sc_lock); 3484 3485 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3486 3487 return USBD_NORMAL_COMPLETION; 3488 } 3489 3490 /* Open a new pipe. */ 3491 usbd_status 3492 uhci_open(struct usbd_pipe *pipe) 3493 { 3494 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3495 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3496 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3497 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3498 usbd_status err = USBD_NOMEM; 3499 int ival; 3500 3501 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3502 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3503 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3504 3505 if (sc->sc_dying) 3506 return USBD_IOERROR; 3507 3508 upipe->aborting = 0; 3509 /* toggle state needed for bulk endpoints */ 3510 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3511 3512 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3513 switch (ed->bEndpointAddress) { 3514 case USB_CONTROL_ENDPOINT: 3515 pipe->up_methods = &roothub_ctrl_methods; 3516 break; 3517 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3518 pipe->up_methods = &uhci_root_intr_methods; 3519 break; 3520 default: 3521 return USBD_INVAL; 3522 } 3523 } else { 3524 switch (ed->bmAttributes & UE_XFERTYPE) { 3525 case UE_CONTROL: 3526 pipe->up_methods = &uhci_device_ctrl_methods; 3527 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3528 if (upipe->ctrl.sqh == NULL) 3529 goto bad; 3530 upipe->ctrl.setup = uhci_alloc_std(sc); 3531 if (upipe->ctrl.setup == NULL) { 3532 uhci_free_sqh(sc, upipe->ctrl.sqh); 3533 goto bad; 3534 } 3535 upipe->ctrl.stat = uhci_alloc_std(sc); 3536 if (upipe->ctrl.stat == NULL) { 3537 uhci_free_sqh(sc, upipe->ctrl.sqh); 3538 uhci_free_std(sc, upipe->ctrl.setup); 3539 goto bad; 3540 } 3541 err = usb_allocmem(&sc->sc_bus, 3542 sizeof(usb_device_request_t), 3543 0, &upipe->ctrl.reqdma); 3544 if (err) { 3545 uhci_free_sqh(sc, upipe->ctrl.sqh); 3546 uhci_free_std(sc, upipe->ctrl.setup); 3547 uhci_free_std(sc, upipe->ctrl.stat); 3548 goto bad; 3549 } 3550 break; 3551 case UE_INTERRUPT: 3552 pipe->up_methods = &uhci_device_intr_methods; 3553 ival = pipe->up_interval; 3554 if (ival == USBD_DEFAULT_INTERVAL) 3555 ival = ed->bInterval; 3556 return uhci_device_setintr(sc, upipe, ival); 3557 case UE_ISOCHRONOUS: 3558 pipe->up_serialise = false; 3559 pipe->up_methods = &uhci_device_isoc_methods; 3560 return uhci_setup_isoc(pipe); 3561 case UE_BULK: 3562 pipe->up_methods = &uhci_device_bulk_methods; 3563 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3564 if (upipe->bulk.sqh == NULL) 3565 goto bad; 3566 break; 3567 } 3568 } 3569 return USBD_NORMAL_COMPLETION; 3570 3571 bad: 3572 return USBD_NOMEM; 3573 } 3574 3575 /* 3576 * Data structures and routines to emulate the root hub. 3577 */ 3578 /* 3579 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3580 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3581 * should not be used by the USB subsystem. As we cannot issue a 3582 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3583 * will be enabled as part of the reset. 3584 * 3585 * On the VT83C572, the port cannot be successfully enabled until the 3586 * outstanding "port enable change" and "connection status change" 3587 * events have been reset. 3588 */ 3589 Static usbd_status 3590 uhci_portreset(uhci_softc_t *sc, int index) 3591 { 3592 int lim, port, x; 3593 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3594 3595 if (index == 1) 3596 port = UHCI_PORTSC1; 3597 else if (index == 2) 3598 port = UHCI_PORTSC2; 3599 else 3600 return USBD_IOERROR; 3601 3602 x = URWMASK(UREAD2(sc, port)); 3603 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3604 3605 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3606 3607 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3608 UREAD2(sc, port), 0, 0); 3609 3610 x = URWMASK(UREAD2(sc, port)); 3611 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3612 3613 delay(100); 3614 3615 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3616 UREAD2(sc, port), 0, 0); 3617 3618 x = URWMASK(UREAD2(sc, port)); 3619 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3620 3621 for (lim = 10; --lim > 0;) { 3622 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3623 3624 x = UREAD2(sc, port); 3625 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3626 lim, x, 0); 3627 3628 if (!(x & UHCI_PORTSC_CCS)) { 3629 /* 3630 * No device is connected (or was disconnected 3631 * during reset). Consider the port reset. 3632 * The delay must be long enough to ensure on 3633 * the initial iteration that the device 3634 * connection will have been registered. 50ms 3635 * appears to be sufficient, but 20ms is not. 3636 */ 3637 DPRINTFN(3, "uhci port %d loop %u, device detached", 3638 index, lim, 0, 0); 3639 break; 3640 } 3641 3642 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3643 /* 3644 * Port enabled changed and/or connection 3645 * status changed were set. Reset either or 3646 * both raised flags (by writing a 1 to that 3647 * bit), and wait again for state to settle. 3648 */ 3649 UWRITE2(sc, port, URWMASK(x) | 3650 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3651 continue; 3652 } 3653 3654 if (x & UHCI_PORTSC_PE) 3655 /* Port is enabled */ 3656 break; 3657 3658 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3659 } 3660 3661 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3662 UREAD2(sc, port), 0, 0); 3663 3664 if (lim <= 0) { 3665 DPRINTF("uhci port %d reset timed out", index, 3666 0, 0, 0); 3667 return USBD_TIMEOUT; 3668 } 3669 3670 sc->sc_isreset = 1; 3671 return USBD_NORMAL_COMPLETION; 3672 } 3673 3674 Static int 3675 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3676 void *buf, int buflen) 3677 { 3678 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3679 int port, x; 3680 int status, change, totlen = 0; 3681 uint16_t len, value, index; 3682 usb_port_status_t ps; 3683 usbd_status err; 3684 3685 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3686 3687 if (sc->sc_dying) 3688 return -1; 3689 3690 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3691 req->bRequest, 0, 0); 3692 3693 len = UGETW(req->wLength); 3694 value = UGETW(req->wValue); 3695 index = UGETW(req->wIndex); 3696 3697 #define C(x,y) ((x) | ((y) << 8)) 3698 switch (C(req->bRequest, req->bmRequestType)) { 3699 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3700 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3701 if (len == 0) 3702 break; 3703 switch (value) { 3704 case C(0, UDESC_DEVICE): { 3705 usb_device_descriptor_t devd; 3706 3707 totlen = min(buflen, sizeof(devd)); 3708 memcpy(&devd, buf, totlen); 3709 USETW(devd.idVendor, sc->sc_id_vendor); 3710 memcpy(buf, &devd, totlen); 3711 break; 3712 } 3713 case C(1, UDESC_STRING): 3714 #define sd ((usb_string_descriptor_t *)buf) 3715 /* Vendor */ 3716 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3717 break; 3718 case C(2, UDESC_STRING): 3719 /* Product */ 3720 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3721 break; 3722 #undef sd 3723 default: 3724 /* default from usbroothub */ 3725 return buflen; 3726 } 3727 break; 3728 3729 /* Hub requests */ 3730 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3731 break; 3732 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3733 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3734 value, 0, 0); 3735 if (index == 1) 3736 port = UHCI_PORTSC1; 3737 else if (index == 2) 3738 port = UHCI_PORTSC2; 3739 else { 3740 return -1; 3741 } 3742 switch(value) { 3743 case UHF_PORT_ENABLE: 3744 x = URWMASK(UREAD2(sc, port)); 3745 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3746 break; 3747 case UHF_PORT_SUSPEND: 3748 x = URWMASK(UREAD2(sc, port)); 3749 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3750 break; 3751 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3752 /* see USB2 spec ch. 7.1.7.7 */ 3753 usb_delay_ms(&sc->sc_bus, 20); 3754 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3755 /* 10ms resume delay must be provided by caller */ 3756 break; 3757 case UHF_PORT_RESET: 3758 x = URWMASK(UREAD2(sc, port)); 3759 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3760 break; 3761 case UHF_C_PORT_CONNECTION: 3762 x = URWMASK(UREAD2(sc, port)); 3763 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3764 break; 3765 case UHF_C_PORT_ENABLE: 3766 x = URWMASK(UREAD2(sc, port)); 3767 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3768 break; 3769 case UHF_C_PORT_OVER_CURRENT: 3770 x = URWMASK(UREAD2(sc, port)); 3771 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3772 break; 3773 case UHF_C_PORT_RESET: 3774 sc->sc_isreset = 0; 3775 break; 3776 case UHF_PORT_CONNECTION: 3777 case UHF_PORT_OVER_CURRENT: 3778 case UHF_PORT_POWER: 3779 case UHF_PORT_LOW_SPEED: 3780 case UHF_C_PORT_SUSPEND: 3781 default: 3782 return -1; 3783 } 3784 break; 3785 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3786 if (index == 1) 3787 port = UHCI_PORTSC1; 3788 else if (index == 2) 3789 port = UHCI_PORTSC2; 3790 else { 3791 return -1; 3792 } 3793 if (len > 0) { 3794 *(uint8_t *)buf = 3795 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3796 totlen = 1; 3797 } 3798 break; 3799 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3800 if (len == 0) 3801 break; 3802 if ((value & 0xff) != 0) { 3803 return -1; 3804 } 3805 usb_hub_descriptor_t hubd; 3806 3807 totlen = min(buflen, sizeof(hubd)); 3808 memcpy(&hubd, buf, totlen); 3809 hubd.bNbrPorts = 2; 3810 memcpy(buf, &hubd, totlen); 3811 break; 3812 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3813 if (len != 4) { 3814 return -1; 3815 } 3816 memset(buf, 0, len); 3817 totlen = len; 3818 break; 3819 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3820 if (index == 1) 3821 port = UHCI_PORTSC1; 3822 else if (index == 2) 3823 port = UHCI_PORTSC2; 3824 else { 3825 return -1; 3826 } 3827 if (len != 4) { 3828 return -1; 3829 } 3830 x = UREAD2(sc, port); 3831 status = change = 0; 3832 if (x & UHCI_PORTSC_CCS) 3833 status |= UPS_CURRENT_CONNECT_STATUS; 3834 if (x & UHCI_PORTSC_CSC) 3835 change |= UPS_C_CONNECT_STATUS; 3836 if (x & UHCI_PORTSC_PE) 3837 status |= UPS_PORT_ENABLED; 3838 if (x & UHCI_PORTSC_POEDC) 3839 change |= UPS_C_PORT_ENABLED; 3840 if (x & UHCI_PORTSC_OCI) 3841 status |= UPS_OVERCURRENT_INDICATOR; 3842 if (x & UHCI_PORTSC_OCIC) 3843 change |= UPS_C_OVERCURRENT_INDICATOR; 3844 if (x & UHCI_PORTSC_SUSP) 3845 status |= UPS_SUSPEND; 3846 if (x & UHCI_PORTSC_LSDA) 3847 status |= UPS_LOW_SPEED; 3848 status |= UPS_PORT_POWER; 3849 if (sc->sc_isreset) 3850 change |= UPS_C_PORT_RESET; 3851 USETW(ps.wPortStatus, status); 3852 USETW(ps.wPortChange, change); 3853 totlen = min(len, sizeof(ps)); 3854 memcpy(buf, &ps, totlen); 3855 break; 3856 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3857 return -1; 3858 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3859 break; 3860 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3861 if (index == 1) 3862 port = UHCI_PORTSC1; 3863 else if (index == 2) 3864 port = UHCI_PORTSC2; 3865 else { 3866 return -1; 3867 } 3868 switch(value) { 3869 case UHF_PORT_ENABLE: 3870 x = URWMASK(UREAD2(sc, port)); 3871 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3872 break; 3873 case UHF_PORT_SUSPEND: 3874 x = URWMASK(UREAD2(sc, port)); 3875 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3876 break; 3877 case UHF_PORT_RESET: 3878 err = uhci_portreset(sc, index); 3879 if (err != USBD_NORMAL_COMPLETION) 3880 return -1; 3881 return 0; 3882 case UHF_PORT_POWER: 3883 /* Pretend we turned on power */ 3884 return 0; 3885 case UHF_C_PORT_CONNECTION: 3886 case UHF_C_PORT_ENABLE: 3887 case UHF_C_PORT_OVER_CURRENT: 3888 case UHF_PORT_CONNECTION: 3889 case UHF_PORT_OVER_CURRENT: 3890 case UHF_PORT_LOW_SPEED: 3891 case UHF_C_PORT_SUSPEND: 3892 case UHF_C_PORT_RESET: 3893 default: 3894 return -1; 3895 } 3896 break; 3897 default: 3898 /* default from usbroothub */ 3899 DPRINTF("returning %d (usbroothub default)", 3900 buflen, 0, 0, 0); 3901 return buflen; 3902 } 3903 3904 DPRINTF("returning %d", totlen, 0, 0, 0); 3905 3906 return totlen; 3907 } 3908 3909 /* Abort a root interrupt request. */ 3910 void 3911 uhci_root_intr_abort(struct usbd_xfer *xfer) 3912 { 3913 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3914 3915 KASSERT(mutex_owned(&sc->sc_lock)); 3916 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3917 3918 callout_stop(&sc->sc_poll_handle); 3919 sc->sc_intr_xfer = NULL; 3920 3921 xfer->ux_status = USBD_CANCELLED; 3922 #ifdef DIAGNOSTIC 3923 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3924 #endif 3925 usb_transfer_complete(xfer); 3926 } 3927 3928 usbd_status 3929 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3930 { 3931 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3932 usbd_status err; 3933 3934 /* Insert last in queue. */ 3935 mutex_enter(&sc->sc_lock); 3936 err = usb_insert_transfer(xfer); 3937 mutex_exit(&sc->sc_lock); 3938 if (err) 3939 return err; 3940 3941 /* 3942 * Pipe isn't running (otherwise err would be USBD_INPROG), 3943 * start first 3944 */ 3945 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3946 } 3947 3948 /* Start a transfer on the root interrupt pipe */ 3949 usbd_status 3950 uhci_root_intr_start(struct usbd_xfer *xfer) 3951 { 3952 struct usbd_pipe *pipe = xfer->ux_pipe; 3953 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3954 unsigned int ival; 3955 3956 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3957 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3958 xfer->ux_flags, 0); 3959 3960 if (sc->sc_dying) 3961 return USBD_IOERROR; 3962 3963 /* XXX temporary variable needed to avoid gcc3 warning */ 3964 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3965 sc->sc_ival = mstohz(ival); 3966 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3967 sc->sc_intr_xfer = xfer; 3968 return USBD_IN_PROGRESS; 3969 } 3970 3971 /* Close the root interrupt pipe. */ 3972 void 3973 uhci_root_intr_close(struct usbd_pipe *pipe) 3974 { 3975 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3976 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3977 3978 KASSERT(mutex_owned(&sc->sc_lock)); 3979 3980 callout_stop(&sc->sc_poll_handle); 3981 sc->sc_intr_xfer = NULL; 3982 } 3983
Indexes created Tue Sep 30 20:09:53 GMT 2025