uhci.c revision 1.264.4.80
1 /* $NetBSD: uhci.c,v 1.264.4.80 2017/08/28 17:52:28 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.264.4.80 2017/08/28 17:52:28 skrll Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/device.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/mutex.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/select.h> 62 #include <sys/sysctl.h> 63 #include <sys/systm.h> 64 65 #include <machine/endian.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usb_mem.h> 71 72 #include <dev/usb/uhcireg.h> 73 #include <dev/usb/uhcivar.h> 74 #include <dev/usb/usbroothub.h> 75 #include <dev/usb/usbhist.h> 76 77 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 78 /*#define UHCI_CTL_LOOP */ 79 80 #ifdef UHCI_DEBUG 81 uhci_softc_t *thesc; 82 int uhcinoloop = 0; 83 #endif 84 85 #ifdef USB_DEBUG 86 #ifndef UHCI_DEBUG 87 #define uhcidebug 0 88 #else 89 static int uhcidebug = 0; 90 91 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 92 { 93 int err; 94 const struct sysctlnode *rnode; 95 const struct sysctlnode *cnode; 96 97 err = sysctl_createv(clog, 0, NULL, &rnode, 98 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 99 SYSCTL_DESCR("uhci global controls"), 100 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 101 102 if (err) 103 goto fail; 104 105 /* control debugging printfs */ 106 err = sysctl_createv(clog, 0, &rnode, &cnode, 107 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 108 "debug", SYSCTL_DESCR("Enable debugging output"), 109 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 110 if (err) 111 goto fail; 112 113 return; 114 fail: 115 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 116 } 117 118 #endif /* UHCI_DEBUG */ 119 #endif /* USB_DEBUG */ 120 121 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 122 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 123 #define UHCIHIST_FUNC() USBHIST_FUNC() 124 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 125 126 /* 127 * The UHCI controller is little endian, so on big endian machines 128 * the data stored in memory needs to be swapped. 129 */ 130 131 struct uhci_pipe { 132 struct usbd_pipe pipe; 133 int nexttoggle; 134 135 u_char aborting; 136 struct usbd_xfer *abortstart, abortend; 137 138 /* Info needed for different pipe kinds. */ 139 union { 140 /* Control pipe */ 141 struct { 142 uhci_soft_qh_t *sqh; 143 usb_dma_t reqdma; 144 uhci_soft_td_t *setup; 145 uhci_soft_td_t *stat; 146 } ctrl; 147 /* Interrupt pipe */ 148 struct { 149 int npoll; 150 uhci_soft_qh_t **qhs; 151 } intr; 152 /* Bulk pipe */ 153 struct { 154 uhci_soft_qh_t *sqh; 155 } bulk; 156 /* Isochronous pipe */ 157 struct isoc { 158 uhci_soft_td_t **stds; 159 int next, inuse; 160 } isoc; 161 }; 162 }; 163 164 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 165 166 Static void uhci_globalreset(uhci_softc_t *); 167 Static usbd_status uhci_portreset(uhci_softc_t*, int); 168 Static void uhci_reset(uhci_softc_t *); 169 Static usbd_status uhci_run(uhci_softc_t *, int, int); 170 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 171 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 172 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 173 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 174 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 175 #if 0 176 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 177 uhci_intr_info_t *); 178 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 179 #endif 180 181 #if 0 182 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 183 uhci_soft_td_t *); 184 #endif 185 Static int uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, uhci_soft_td_t **); 187 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 188 189 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 190 int, int, int *, uhci_soft_td_t **); 191 192 Static void uhci_poll_hub(void *); 193 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 194 ux_completeq_t *); 195 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 196 197 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 198 199 Static void uhci_timeout(void *); 200 Static void uhci_timeout_task(void *); 201 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 202 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 203 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 204 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 205 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 206 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 207 Static void uhci_add_loop(uhci_softc_t *); 208 Static void uhci_rem_loop(uhci_softc_t *); 209 210 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 211 212 Static struct usbd_xfer * 213 uhci_allocx(struct usbd_bus *, unsigned int); 214 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 215 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 216 Static int uhci_roothub_ctrl(struct usbd_bus *, 217 usb_device_request_t *, void *, int); 218 219 Static int uhci_device_ctrl_init(struct usbd_xfer *); 220 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 221 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 222 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 223 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 224 Static void uhci_device_ctrl_close(struct usbd_pipe *); 225 Static void uhci_device_ctrl_done(struct usbd_xfer *); 226 227 Static int uhci_device_intr_init(struct usbd_xfer *); 228 Static void uhci_device_intr_fini(struct usbd_xfer *); 229 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 230 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 231 Static void uhci_device_intr_abort(struct usbd_xfer *); 232 Static void uhci_device_intr_close(struct usbd_pipe *); 233 Static void uhci_device_intr_done(struct usbd_xfer *); 234 235 Static int uhci_device_bulk_init(struct usbd_xfer *); 236 Static void uhci_device_bulk_fini(struct usbd_xfer *); 237 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 238 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 239 Static void uhci_device_bulk_abort(struct usbd_xfer *); 240 Static void uhci_device_bulk_close(struct usbd_pipe *); 241 Static void uhci_device_bulk_done(struct usbd_xfer *); 242 243 Static int uhci_device_isoc_init(struct usbd_xfer *); 244 Static void uhci_device_isoc_fini(struct usbd_xfer *); 245 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 246 Static void uhci_device_isoc_abort(struct usbd_xfer *); 247 Static void uhci_device_isoc_close(struct usbd_pipe *); 248 Static void uhci_device_isoc_done(struct usbd_xfer *); 249 250 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 251 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 252 Static void uhci_root_intr_abort(struct usbd_xfer *); 253 Static void uhci_root_intr_close(struct usbd_pipe *); 254 Static void uhci_root_intr_done(struct usbd_xfer *); 255 256 Static usbd_status uhci_open(struct usbd_pipe *); 257 Static void uhci_poll(struct usbd_bus *); 258 Static void uhci_softintr(void *); 259 260 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 261 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 262 Static usbd_status uhci_device_setintr(uhci_softc_t *, 263 struct uhci_pipe *, int); 264 265 Static void uhci_device_clear_toggle(struct usbd_pipe *); 266 Static void uhci_noop(struct usbd_pipe *); 267 268 static inline uhci_soft_qh_t * 269 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 270 271 #ifdef UHCI_DEBUG 272 Static void uhci_dump_all(uhci_softc_t *); 273 Static void uhci_dumpregs(uhci_softc_t *); 274 Static void uhci_dump_qhs(uhci_soft_qh_t *); 275 Static void uhci_dump_qh(uhci_soft_qh_t *); 276 Static void uhci_dump_tds(uhci_soft_td_t *); 277 Static void uhci_dump_td(uhci_soft_td_t *); 278 Static void uhci_dump_ii(struct uhci_xfer *); 279 void uhci_dump(void); 280 #endif 281 282 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 283 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 284 #define UWRITE1(sc, r, x) \ 285 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 286 } while (/*CONSTCOND*/0) 287 #define UWRITE2(sc, r, x) \ 288 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 289 } while (/*CONSTCOND*/0) 290 #define UWRITE4(sc, r, x) \ 291 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 292 } while (/*CONSTCOND*/0) 293 294 static __inline uint8_t 295 UREAD1(uhci_softc_t *sc, bus_size_t r) 296 { 297 298 UBARR(sc); 299 return bus_space_read_1(sc->iot, sc->ioh, r); 300 } 301 302 static __inline uint16_t 303 UREAD2(uhci_softc_t *sc, bus_size_t r) 304 { 305 306 UBARR(sc); 307 return bus_space_read_2(sc->iot, sc->ioh, r); 308 } 309 310 #ifdef UHCI_DEBUG 311 static __inline uint32_t 312 UREAD4(uhci_softc_t *sc, bus_size_t r) 313 { 314 315 UBARR(sc); 316 return bus_space_read_4(sc->iot, sc->ioh, r); 317 } 318 #endif 319 320 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 321 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 322 323 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 324 325 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 326 327 const struct usbd_bus_methods uhci_bus_methods = { 328 .ubm_open = uhci_open, 329 .ubm_softint = uhci_softintr, 330 .ubm_dopoll = uhci_poll, 331 .ubm_allocx = uhci_allocx, 332 .ubm_freex = uhci_freex, 333 .ubm_getlock = uhci_get_lock, 334 .ubm_rhctrl = uhci_roothub_ctrl, 335 }; 336 337 const struct usbd_pipe_methods uhci_root_intr_methods = { 338 .upm_transfer = uhci_root_intr_transfer, 339 .upm_start = uhci_root_intr_start, 340 .upm_abort = uhci_root_intr_abort, 341 .upm_close = uhci_root_intr_close, 342 .upm_cleartoggle = uhci_noop, 343 .upm_done = uhci_root_intr_done, 344 }; 345 346 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 347 .upm_init = uhci_device_ctrl_init, 348 .upm_fini = uhci_device_ctrl_fini, 349 .upm_transfer = uhci_device_ctrl_transfer, 350 .upm_start = uhci_device_ctrl_start, 351 .upm_abort = uhci_device_ctrl_abort, 352 .upm_close = uhci_device_ctrl_close, 353 .upm_cleartoggle = uhci_noop, 354 .upm_done = uhci_device_ctrl_done, 355 }; 356 357 const struct usbd_pipe_methods uhci_device_intr_methods = { 358 .upm_init = uhci_device_intr_init, 359 .upm_fini = uhci_device_intr_fini, 360 .upm_transfer = uhci_device_intr_transfer, 361 .upm_start = uhci_device_intr_start, 362 .upm_abort = uhci_device_intr_abort, 363 .upm_close = uhci_device_intr_close, 364 .upm_cleartoggle = uhci_device_clear_toggle, 365 .upm_done = uhci_device_intr_done, 366 }; 367 368 const struct usbd_pipe_methods uhci_device_bulk_methods = { 369 .upm_init = uhci_device_bulk_init, 370 .upm_fini = uhci_device_bulk_fini, 371 .upm_transfer = uhci_device_bulk_transfer, 372 .upm_start = uhci_device_bulk_start, 373 .upm_abort = uhci_device_bulk_abort, 374 .upm_close = uhci_device_bulk_close, 375 .upm_cleartoggle = uhci_device_clear_toggle, 376 .upm_done = uhci_device_bulk_done, 377 }; 378 379 const struct usbd_pipe_methods uhci_device_isoc_methods = { 380 .upm_init = uhci_device_isoc_init, 381 .upm_fini = uhci_device_isoc_fini, 382 .upm_transfer = uhci_device_isoc_transfer, 383 .upm_abort = uhci_device_isoc_abort, 384 .upm_close = uhci_device_isoc_close, 385 .upm_cleartoggle = uhci_noop, 386 .upm_done = uhci_device_isoc_done, 387 }; 388 389 static inline void 390 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 391 { 392 393 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 394 } 395 396 static inline void 397 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 398 { 399 400 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 401 } 402 403 static inline uhci_soft_qh_t * 404 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 405 { 406 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 407 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 408 409 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 410 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 411 usb_syncmem(&pqh->dma, 412 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 413 sizeof(pqh->qh.qh_hlink), 414 BUS_DMASYNC_POSTWRITE); 415 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 416 printf("%s: QH not found\n", __func__); 417 return NULL; 418 } 419 #endif 420 } 421 return pqh; 422 } 423 424 void 425 uhci_globalreset(uhci_softc_t *sc) 426 { 427 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 428 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 429 UHCICMD(sc, 0); /* do nothing */ 430 } 431 432 int 433 uhci_init(uhci_softc_t *sc) 434 { 435 usbd_status err; 436 int i, j; 437 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 438 uhci_soft_td_t *std; 439 440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 441 442 #ifdef UHCI_DEBUG 443 thesc = sc; 444 445 if (uhcidebug >= 2) 446 uhci_dumpregs(sc); 447 #endif 448 449 sc->sc_suspend = PWR_RESUME; 450 451 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 452 uhci_globalreset(sc); /* reset the controller */ 453 uhci_reset(sc); 454 455 /* Allocate and initialize real frame array. */ 456 err = usb_allocmem(&sc->sc_bus, 457 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 458 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 459 if (err) 460 return err; 461 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 462 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 463 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 464 465 /* Initialise mutex early for uhci_alloc_* */ 466 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 467 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 468 469 /* 470 * Allocate a TD, inactive, that hangs from the last QH. 471 * This is to avoid a bug in the PIIX that makes it run berserk 472 * otherwise. 473 */ 474 std = uhci_alloc_std(sc); 475 if (std == NULL) 476 return ENOMEM; 477 std->link.std = NULL; 478 std->td.td_link = htole32(UHCI_PTR_T); 479 std->td.td_status = htole32(0); /* inactive */ 480 std->td.td_token = htole32(0); 481 std->td.td_buffer = htole32(0); 482 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 486 lsqh = uhci_alloc_sqh(sc); 487 if (lsqh == NULL) 488 goto fail1; 489 lsqh->hlink = NULL; 490 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 491 lsqh->elink = std; 492 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 493 sc->sc_last_qh = lsqh; 494 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 495 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 496 497 /* Allocate the dummy QH where bulk traffic will be queued. */ 498 bsqh = uhci_alloc_sqh(sc); 499 if (bsqh == NULL) 500 goto fail2; 501 bsqh->hlink = lsqh; 502 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 503 bsqh->elink = NULL; 504 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 506 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 509 /* Allocate dummy QH where high speed control traffic will be queued. */ 510 chsqh = uhci_alloc_sqh(sc); 511 if (chsqh == NULL) 512 goto fail3; 513 chsqh->hlink = bsqh; 514 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 515 chsqh->elink = NULL; 516 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 517 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 518 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 521 /* Allocate dummy QH where control traffic will be queued. */ 522 clsqh = uhci_alloc_sqh(sc); 523 if (clsqh == NULL) 524 goto fail4; 525 clsqh->hlink = chsqh; 526 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 527 clsqh->elink = NULL; 528 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 529 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 530 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 533 /* 534 * Make all (virtual) frame list pointers point to the interrupt 535 * queue heads and the interrupt queue heads at the control 536 * queue head and point the physical frame list to the virtual. 537 */ 538 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 539 std = uhci_alloc_std(sc); 540 sqh = uhci_alloc_sqh(sc); 541 if (std == NULL || sqh == NULL) 542 return USBD_NOMEM; 543 std->link.sqh = sqh; 544 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 545 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 546 std->td.td_token = htole32(0); 547 std->td.td_buffer = htole32(0); 548 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 sqh->hlink = clsqh; 551 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 552 sqh->elink = NULL; 553 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 554 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 556 sc->sc_vframes[i].htd = std; 557 sc->sc_vframes[i].etd = std; 558 sc->sc_vframes[i].hqh = sqh; 559 sc->sc_vframes[i].eqh = sqh; 560 for (j = i; 561 j < UHCI_FRAMELIST_COUNT; 562 j += UHCI_VFRAMELIST_COUNT) 563 sc->sc_pframes[j] = htole32(std->physaddr); 564 } 565 usb_syncmem(&sc->sc_dma, 0, 566 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 567 BUS_DMASYNC_PREWRITE); 568 569 570 TAILQ_INIT(&sc->sc_intrhead); 571 572 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 573 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 574 575 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 576 577 /* Set up the bus struct. */ 578 sc->sc_bus.ub_methods = &uhci_bus_methods; 579 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 580 sc->sc_bus.ub_usedma = true; 581 582 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 583 584 DPRINTF("Enabling...", 0, 0, 0, 0); 585 586 err = uhci_run(sc, 1, 0); /* and here we go... */ 587 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 588 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 589 return err; 590 591 fail4: 592 uhci_free_sqh(sc, chsqh); 593 fail3: 594 uhci_free_sqh(sc, lsqh); 595 fail2: 596 uhci_free_sqh(sc, lsqh); 597 fail1: 598 uhci_free_std(sc, std); 599 600 return ENOMEM; 601 } 602 603 int 604 uhci_activate(device_t self, enum devact act) 605 { 606 struct uhci_softc *sc = device_private(self); 607 608 switch (act) { 609 case DVACT_DEACTIVATE: 610 sc->sc_dying = 1; 611 return 0; 612 default: 613 return EOPNOTSUPP; 614 } 615 } 616 617 void 618 uhci_childdet(device_t self, device_t child) 619 { 620 struct uhci_softc *sc = device_private(self); 621 622 KASSERT(sc->sc_child == child); 623 sc->sc_child = NULL; 624 } 625 626 int 627 uhci_detach(struct uhci_softc *sc, int flags) 628 { 629 int rv = 0; 630 631 if (sc->sc_child != NULL) 632 rv = config_detach(sc->sc_child, flags); 633 634 if (rv != 0) 635 return rv; 636 637 callout_halt(&sc->sc_poll_handle, NULL); 638 callout_destroy(&sc->sc_poll_handle); 639 640 mutex_destroy(&sc->sc_lock); 641 mutex_destroy(&sc->sc_intr_lock); 642 643 pool_cache_destroy(sc->sc_xferpool); 644 645 /* XXX free other data structures XXX */ 646 647 return rv; 648 } 649 650 struct usbd_xfer * 651 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 652 { 653 struct uhci_softc *sc = UHCI_BUS2SC(bus); 654 struct usbd_xfer *xfer; 655 656 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 657 if (xfer != NULL) { 658 memset(xfer, 0, sizeof(struct uhci_xfer)); 659 660 #ifdef DIAGNOSTIC 661 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 662 uxfer->ux_isdone = true; 663 xfer->ux_state = XFER_BUSY; 664 #endif 665 } 666 return xfer; 667 } 668 669 void 670 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 671 { 672 struct uhci_softc *sc = UHCI_BUS2SC(bus); 673 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 674 675 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 676 xfer->ux_state); 677 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 678 #ifdef DIAGNOSTIC 679 xfer->ux_state = XFER_FREE; 680 #endif 681 pool_cache_put(sc->sc_xferpool, xfer); 682 } 683 684 Static void 685 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 686 { 687 struct uhci_softc *sc = UHCI_BUS2SC(bus); 688 689 *lock = &sc->sc_lock; 690 } 691 692 693 /* 694 * Handle suspend/resume. 695 * 696 * We need to switch to polling mode here, because this routine is 697 * called from an interrupt context. This is all right since we 698 * are almost suspended anyway. 699 */ 700 bool 701 uhci_resume(device_t dv, const pmf_qual_t *qual) 702 { 703 uhci_softc_t *sc = device_private(dv); 704 int cmd; 705 706 mutex_spin_enter(&sc->sc_intr_lock); 707 708 cmd = UREAD2(sc, UHCI_CMD); 709 sc->sc_bus.ub_usepolling++; 710 UWRITE2(sc, UHCI_INTR, 0); 711 uhci_globalreset(sc); 712 uhci_reset(sc); 713 if (cmd & UHCI_CMD_RS) 714 uhci_run(sc, 0, 1); 715 716 /* restore saved state */ 717 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 718 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 719 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 720 721 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 722 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 723 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 724 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 725 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 726 UHCICMD(sc, UHCI_CMD_MAXP); 727 uhci_run(sc, 1, 1); /* and start traffic again */ 728 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 729 sc->sc_bus.ub_usepolling--; 730 if (sc->sc_intr_xfer != NULL) 731 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 732 sc->sc_intr_xfer); 733 #ifdef UHCI_DEBUG 734 if (uhcidebug >= 2) 735 uhci_dumpregs(sc); 736 #endif 737 738 sc->sc_suspend = PWR_RESUME; 739 mutex_spin_exit(&sc->sc_intr_lock); 740 741 return true; 742 } 743 744 bool 745 uhci_suspend(device_t dv, const pmf_qual_t *qual) 746 { 747 uhci_softc_t *sc = device_private(dv); 748 int cmd; 749 750 mutex_spin_enter(&sc->sc_intr_lock); 751 752 cmd = UREAD2(sc, UHCI_CMD); 753 754 #ifdef UHCI_DEBUG 755 if (uhcidebug >= 2) 756 uhci_dumpregs(sc); 757 #endif 758 if (sc->sc_intr_xfer != NULL) 759 callout_stop(&sc->sc_poll_handle); 760 sc->sc_suspend = PWR_SUSPEND; 761 sc->sc_bus.ub_usepolling++; 762 763 uhci_run(sc, 0, 1); /* stop the controller */ 764 cmd &= ~UHCI_CMD_RS; 765 766 /* save some state if BIOS doesn't */ 767 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 768 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 769 770 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 771 772 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 773 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 774 sc->sc_bus.ub_usepolling--; 775 776 mutex_spin_exit(&sc->sc_intr_lock); 777 778 return true; 779 } 780 781 #ifdef UHCI_DEBUG 782 Static void 783 uhci_dumpregs(uhci_softc_t *sc) 784 { 785 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 786 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 787 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 788 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 789 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 790 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 791 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 792 } 793 794 void 795 uhci_dump_td(uhci_soft_td_t *p) 796 { 797 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 798 799 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 800 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 801 802 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 803 DPRINTF(" link=0x%08x status=0x%08x " 804 "token=0x%08x buffer=0x%08x", 805 le32toh(p->td.td_link), 806 le32toh(p->td.td_status), 807 le32toh(p->td.td_token), 808 le32toh(p->td.td_buffer)); 809 810 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 811 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 812 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 813 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 814 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 815 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 816 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 817 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 818 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 819 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 820 DPRINTF("ios =%d ls =%d spd =%d", 821 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 822 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 823 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 824 DPRINTF("errcnt =%d actlen =%d pid=%02x", 825 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 826 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 827 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 828 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 829 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 830 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 831 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 832 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 833 } 834 835 void 836 uhci_dump_qh(uhci_soft_qh_t *sqh) 837 { 838 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 839 840 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 841 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 842 843 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 844 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 845 le32toh(sqh->qh.qh_elink)); 846 847 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 848 } 849 850 851 #if 1 852 void 853 uhci_dump(void) 854 { 855 uhci_dump_all(thesc); 856 } 857 #endif 858 859 void 860 uhci_dump_all(uhci_softc_t *sc) 861 { 862 uhci_dumpregs(sc); 863 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 864 uhci_dump_qhs(sc->sc_lctl_start); 865 } 866 867 868 void 869 uhci_dump_qhs(uhci_soft_qh_t *sqh) 870 { 871 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 872 873 uhci_dump_qh(sqh); 874 875 /* 876 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 877 * Traverses sideways first, then down. 878 * 879 * QH1 880 * QH2 881 * No QH 882 * TD2.1 883 * TD2.2 884 * TD1.1 885 * etc. 886 * 887 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 888 */ 889 890 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 892 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 893 uhci_dump_qhs(sqh->hlink); 894 else 895 DPRINTF("No QH", 0, 0, 0, 0); 896 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 897 898 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 899 uhci_dump_tds(sqh->elink); 900 else 901 DPRINTF("No QH", 0, 0, 0, 0); 902 } 903 904 void 905 uhci_dump_tds(uhci_soft_td_t *std) 906 { 907 uhci_soft_td_t *td; 908 int stop; 909 910 for (td = std; td != NULL; td = td->link.std) { 911 uhci_dump_td(td); 912 913 /* 914 * Check whether the link pointer in this TD marks 915 * the link pointer as end of queue. This avoids 916 * printing the free list in case the queue/TD has 917 * already been moved there (seatbelt). 918 */ 919 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 920 sizeof(td->td.td_link), 921 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 922 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 923 le32toh(td->td.td_link) == 0); 924 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 925 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 926 if (stop) 927 break; 928 } 929 } 930 931 Static void 932 uhci_dump_ii(struct uhci_xfer *ux) 933 { 934 struct usbd_pipe *pipe; 935 usb_endpoint_descriptor_t *ed; 936 struct usbd_device *dev; 937 938 if (ux == NULL) { 939 printf("ux NULL\n"); 940 return; 941 } 942 pipe = ux->ux_xfer.ux_pipe; 943 if (pipe == NULL) { 944 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 945 return; 946 } 947 if (pipe->up_endpoint == NULL) { 948 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 949 ux, ux->ux_isdone, pipe); 950 return; 951 } 952 if (pipe->up_dev == NULL) { 953 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 954 ux, ux->ux_isdone, pipe); 955 return; 956 } 957 ed = pipe->up_endpoint->ue_edesc; 958 dev = pipe->up_dev; 959 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 960 ux, ux->ux_isdone, dev, 961 UGETW(dev->ud_ddesc.idVendor), 962 UGETW(dev->ud_ddesc.idProduct), 963 dev->ud_addr, pipe, 964 ed->bEndpointAddress, ed->bmAttributes); 965 } 966 967 void uhci_dump_iis(struct uhci_softc *sc); 968 void 969 uhci_dump_iis(struct uhci_softc *sc) 970 { 971 struct uhci_xfer *ux; 972 973 printf("interrupt list:\n"); 974 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 975 uhci_dump_ii(ux); 976 } 977 978 void iidump(void); 979 void iidump(void) { uhci_dump_iis(thesc); } 980 981 #endif 982 983 /* 984 * This routine is executed periodically and simulates interrupts 985 * from the root controller interrupt pipe for port status change. 986 */ 987 void 988 uhci_poll_hub(void *addr) 989 { 990 struct usbd_xfer *xfer = addr; 991 struct usbd_pipe *pipe = xfer->ux_pipe; 992 uhci_softc_t *sc; 993 u_char *p; 994 995 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 996 997 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 998 return; /* device has detached */ 999 sc = UHCI_PIPE2SC(pipe); 1000 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1001 1002 p = xfer->ux_buf; 1003 p[0] = 0; 1004 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1005 p[0] |= 1<<1; 1006 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<2; 1008 if (p[0] == 0) 1009 /* No change, try again in a while */ 1010 return; 1011 1012 xfer->ux_actlen = 1; 1013 xfer->ux_status = USBD_NORMAL_COMPLETION; 1014 mutex_enter(&sc->sc_lock); 1015 usb_transfer_complete(xfer); 1016 mutex_exit(&sc->sc_lock); 1017 } 1018 1019 void 1020 uhci_root_intr_done(struct usbd_xfer *xfer) 1021 { 1022 } 1023 1024 /* 1025 * Let the last QH loop back to the high speed control transfer QH. 1026 * This is what intel calls "bandwidth reclamation" and improves 1027 * USB performance a lot for some devices. 1028 * If we are already looping, just count it. 1029 */ 1030 void 1031 uhci_add_loop(uhci_softc_t *sc) 1032 { 1033 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1034 1035 #ifdef UHCI_DEBUG 1036 if (uhcinoloop) 1037 return; 1038 #endif 1039 if (++sc->sc_loops == 1) { 1040 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1041 /* Note, we don't loop back the soft pointer. */ 1042 sc->sc_last_qh->qh.qh_hlink = 1043 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1044 usb_syncmem(&sc->sc_last_qh->dma, 1045 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1046 sizeof(sc->sc_last_qh->qh.qh_hlink), 1047 BUS_DMASYNC_PREWRITE); 1048 } 1049 } 1050 1051 void 1052 uhci_rem_loop(uhci_softc_t *sc) 1053 { 1054 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1055 1056 #ifdef UHCI_DEBUG 1057 if (uhcinoloop) 1058 return; 1059 #endif 1060 if (--sc->sc_loops == 0) { 1061 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1062 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1063 usb_syncmem(&sc->sc_last_qh->dma, 1064 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1065 sizeof(sc->sc_last_qh->qh.qh_hlink), 1066 BUS_DMASYNC_PREWRITE); 1067 } 1068 } 1069 1070 /* Add high speed control QH, called with lock held. */ 1071 void 1072 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1073 { 1074 uhci_soft_qh_t *eqh; 1075 1076 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1077 1078 KASSERT(mutex_owned(&sc->sc_lock)); 1079 1080 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1081 eqh = sc->sc_hctl_end; 1082 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1083 sizeof(eqh->qh.qh_hlink), 1084 BUS_DMASYNC_POSTWRITE); 1085 sqh->hlink = eqh->hlink; 1086 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1087 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1088 BUS_DMASYNC_PREWRITE); 1089 eqh->hlink = sqh; 1090 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1091 sc->sc_hctl_end = sqh; 1092 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1093 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1094 #ifdef UHCI_CTL_LOOP 1095 uhci_add_loop(sc); 1096 #endif 1097 } 1098 1099 /* Remove high speed control QH, called with lock held. */ 1100 void 1101 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1102 { 1103 uhci_soft_qh_t *pqh; 1104 uint32_t elink; 1105 1106 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1107 1108 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1109 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1110 #ifdef UHCI_CTL_LOOP 1111 uhci_rem_loop(sc); 1112 #endif 1113 /* 1114 * The T bit should be set in the elink of the QH so that the HC 1115 * doesn't follow the pointer. This condition may fail if the 1116 * the transferred packet was short so that the QH still points 1117 * at the last used TD. 1118 * In this case we set the T bit and wait a little for the HC 1119 * to stop looking at the TD. 1120 * Note that if the TD chain is large enough, the controller 1121 * may still be looking at the chain at the end of this function. 1122 * uhci_free_std_chain() will make sure the controller stops 1123 * looking at it quickly, but until then we should not change 1124 * sqh->hlink. 1125 */ 1126 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1127 sizeof(sqh->qh.qh_elink), 1128 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1129 elink = le32toh(sqh->qh.qh_elink); 1130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1131 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1132 if (!(elink & UHCI_PTR_T)) { 1133 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1134 usb_syncmem(&sqh->dma, 1135 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1136 sizeof(sqh->qh.qh_elink), 1137 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1138 delay(UHCI_QH_REMOVE_DELAY); 1139 } 1140 1141 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1142 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1143 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1144 pqh->hlink = sqh->hlink; 1145 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1146 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1147 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1148 delay(UHCI_QH_REMOVE_DELAY); 1149 if (sc->sc_hctl_end == sqh) 1150 sc->sc_hctl_end = pqh; 1151 } 1152 1153 /* Add low speed control QH, called with lock held. */ 1154 void 1155 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1156 { 1157 uhci_soft_qh_t *eqh; 1158 1159 KASSERT(mutex_owned(&sc->sc_lock)); 1160 1161 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1162 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1163 1164 eqh = sc->sc_lctl_end; 1165 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1166 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1167 sqh->hlink = eqh->hlink; 1168 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1169 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1170 BUS_DMASYNC_PREWRITE); 1171 eqh->hlink = sqh; 1172 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1173 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1174 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1175 sc->sc_lctl_end = sqh; 1176 } 1177 1178 /* Remove low speed control QH, called with lock held. */ 1179 void 1180 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1181 { 1182 uhci_soft_qh_t *pqh; 1183 uint32_t elink; 1184 1185 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1186 1187 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1188 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1189 1190 /* See comment in uhci_remove_hs_ctrl() */ 1191 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1192 sizeof(sqh->qh.qh_elink), 1193 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1194 elink = le32toh(sqh->qh.qh_elink); 1195 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1196 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1197 if (!(elink & UHCI_PTR_T)) { 1198 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1199 usb_syncmem(&sqh->dma, 1200 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1201 sizeof(sqh->qh.qh_elink), 1202 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1203 delay(UHCI_QH_REMOVE_DELAY); 1204 } 1205 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1206 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1207 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1208 pqh->hlink = sqh->hlink; 1209 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1210 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1211 sizeof(pqh->qh.qh_hlink), 1212 BUS_DMASYNC_PREWRITE); 1213 delay(UHCI_QH_REMOVE_DELAY); 1214 if (sc->sc_lctl_end == sqh) 1215 sc->sc_lctl_end = pqh; 1216 } 1217 1218 /* Add bulk QH, called with lock held. */ 1219 void 1220 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1221 { 1222 uhci_soft_qh_t *eqh; 1223 1224 KASSERT(mutex_owned(&sc->sc_lock)); 1225 1226 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1227 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1228 1229 eqh = sc->sc_bulk_end; 1230 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1231 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1232 sqh->hlink = eqh->hlink; 1233 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1234 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1235 BUS_DMASYNC_PREWRITE); 1236 eqh->hlink = sqh; 1237 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1238 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1239 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1240 sc->sc_bulk_end = sqh; 1241 uhci_add_loop(sc); 1242 } 1243 1244 /* Remove bulk QH, called with lock held. */ 1245 void 1246 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1247 { 1248 uhci_soft_qh_t *pqh; 1249 1250 KASSERT(mutex_owned(&sc->sc_lock)); 1251 1252 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1253 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1254 1255 uhci_rem_loop(sc); 1256 /* See comment in uhci_remove_hs_ctrl() */ 1257 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1258 sizeof(sqh->qh.qh_elink), 1259 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1260 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1261 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1262 usb_syncmem(&sqh->dma, 1263 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1264 sizeof(sqh->qh.qh_elink), 1265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1266 delay(UHCI_QH_REMOVE_DELAY); 1267 } 1268 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1269 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1270 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1271 pqh->hlink = sqh->hlink; 1272 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1273 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1274 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1275 delay(UHCI_QH_REMOVE_DELAY); 1276 if (sc->sc_bulk_end == sqh) 1277 sc->sc_bulk_end = pqh; 1278 } 1279 1280 Static int uhci_intr1(uhci_softc_t *); 1281 1282 int 1283 uhci_intr(void *arg) 1284 { 1285 uhci_softc_t *sc = arg; 1286 int ret = 0; 1287 1288 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1289 1290 mutex_spin_enter(&sc->sc_intr_lock); 1291 1292 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1293 goto done; 1294 1295 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1296 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1297 goto done; 1298 } 1299 1300 ret = uhci_intr1(sc); 1301 1302 done: 1303 mutex_spin_exit(&sc->sc_intr_lock); 1304 return ret; 1305 } 1306 1307 int 1308 uhci_intr1(uhci_softc_t *sc) 1309 { 1310 int status; 1311 int ack; 1312 1313 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1314 1315 #ifdef UHCI_DEBUG 1316 if (uhcidebug >= 15) { 1317 DPRINTF("sc %p", sc, 0, 0, 0); 1318 uhci_dumpregs(sc); 1319 } 1320 #endif 1321 1322 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1323 1324 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1325 /* Check if the interrupt was for us. */ 1326 if (status == 0) 1327 return 0; 1328 1329 if (sc->sc_suspend != PWR_RESUME) { 1330 #ifdef DIAGNOSTIC 1331 printf("%s: interrupt while not operating ignored\n", 1332 device_xname(sc->sc_dev)); 1333 #endif 1334 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1335 return 0; 1336 } 1337 1338 ack = 0; 1339 if (status & UHCI_STS_USBINT) 1340 ack |= UHCI_STS_USBINT; 1341 if (status & UHCI_STS_USBEI) 1342 ack |= UHCI_STS_USBEI; 1343 if (status & UHCI_STS_RD) { 1344 ack |= UHCI_STS_RD; 1345 #ifdef UHCI_DEBUG 1346 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1347 #endif 1348 } 1349 if (status & UHCI_STS_HSE) { 1350 ack |= UHCI_STS_HSE; 1351 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1352 } 1353 if (status & UHCI_STS_HCPE) { 1354 ack |= UHCI_STS_HCPE; 1355 printf("%s: host controller process error\n", 1356 device_xname(sc->sc_dev)); 1357 } 1358 1359 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1360 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1361 /* no acknowledge needed */ 1362 if (!sc->sc_dying) { 1363 printf("%s: host controller halted\n", 1364 device_xname(sc->sc_dev)); 1365 #ifdef UHCI_DEBUG 1366 uhci_dump_all(sc); 1367 #endif 1368 } 1369 sc->sc_dying = 1; 1370 } 1371 1372 if (!ack) 1373 return 0; /* nothing to acknowledge */ 1374 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1375 1376 usb_schedsoftintr(&sc->sc_bus); 1377 1378 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1379 1380 return 1; 1381 } 1382 1383 void 1384 uhci_softintr(void *v) 1385 { 1386 struct usbd_bus *bus = v; 1387 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1388 struct uhci_xfer *ux, *nextux; 1389 ux_completeq_t cq; 1390 1391 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1392 DPRINTF("sc %p", sc, 0, 0, 0); 1393 1394 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1395 1396 TAILQ_INIT(&cq); 1397 /* 1398 * Interrupts on UHCI really suck. When the host controller 1399 * interrupts because a transfer is completed there is no 1400 * way of knowing which transfer it was. You can scan down 1401 * the TDs and QHs of the previous frame to limit the search, 1402 * but that assumes that the interrupt was not delayed by more 1403 * than 1 ms, which may not always be true (e.g. after debug 1404 * output on a slow console). 1405 * We scan all interrupt descriptors to see if any have 1406 * completed. 1407 */ 1408 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1409 uhci_check_intr(sc, ux, &cq); 1410 } 1411 1412 /* 1413 * We abuse ux_list for the interrupt and complete lists and 1414 * interrupt transfers will get re-added here so use 1415 * the _SAFE version of TAILQ_FOREACH. 1416 */ 1417 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1418 DPRINTF("ux %p", ux, 0, 0, 0); 1419 usb_transfer_complete(&ux->ux_xfer); 1420 } 1421 } 1422 1423 /* Check for an interrupt. */ 1424 void 1425 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1426 { 1427 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1428 uint32_t status; 1429 1430 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1431 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1432 1433 KASSERT(ux != NULL); 1434 1435 struct usbd_xfer *xfer = &ux->ux_xfer; 1436 if (xfer->ux_status == USBD_CANCELLED || 1437 xfer->ux_status == USBD_TIMEOUT) { 1438 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1439 return; 1440 } 1441 1442 switch (ux->ux_type) { 1443 case UX_CTRL: 1444 fstd = ux->ux_setup; 1445 lstd = ux->ux_stat; 1446 break; 1447 case UX_BULK: 1448 case UX_INTR: 1449 case UX_ISOC: 1450 fstd = ux->ux_stdstart; 1451 lstd = ux->ux_stdend; 1452 break; 1453 default: 1454 KASSERT(false); 1455 break; 1456 } 1457 if (fstd == NULL) 1458 return; 1459 1460 KASSERT(lstd != NULL); 1461 1462 usb_syncmem(&lstd->dma, 1463 lstd->offs + offsetof(uhci_td_t, td_status), 1464 sizeof(lstd->td.td_status), 1465 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1466 status = le32toh(lstd->td.td_status); 1467 usb_syncmem(&lstd->dma, 1468 lstd->offs + offsetof(uhci_td_t, td_status), 1469 sizeof(lstd->td.td_status), 1470 BUS_DMASYNC_PREREAD); 1471 1472 /* If the last TD is not marked active we can complete */ 1473 if (!(status & UHCI_TD_ACTIVE)) { 1474 done: 1475 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1476 uhci_idone(ux, cqp); 1477 return; 1478 } 1479 1480 /* 1481 * If the last TD is still active we need to check whether there 1482 * is an error somewhere in the middle, or whether there was a 1483 * short packet (SPD and not ACTIVE). 1484 */ 1485 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1486 for (std = fstd; std != lstd; std = std->link.std) { 1487 usb_syncmem(&std->dma, 1488 std->offs + offsetof(uhci_td_t, td_status), 1489 sizeof(std->td.td_status), 1490 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1491 status = le32toh(std->td.td_status); 1492 usb_syncmem(&std->dma, 1493 std->offs + offsetof(uhci_td_t, td_status), 1494 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1495 1496 /* If there's an active TD the xfer isn't done. */ 1497 if (status & UHCI_TD_ACTIVE) { 1498 DPRINTFN(12, "ux=%p std=%p still active", 1499 ux, std, 0, 0); 1500 return; 1501 } 1502 1503 /* Any kind of error makes the xfer done. */ 1504 if (status & UHCI_TD_STALLED) 1505 goto done; 1506 1507 /* 1508 * If the data phase of a control transfer is short, we need 1509 * to complete the status stage 1510 */ 1511 1512 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1513 struct uhci_pipe *upipe = 1514 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1515 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1516 uhci_soft_td_t *stat = upipe->ctrl.stat; 1517 1518 DPRINTFN(12, "ux=%p std=%p control status" 1519 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1520 1521 sqh->qh.qh_elink = 1522 htole32(stat->physaddr | UHCI_PTR_TD); 1523 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1524 BUS_DMASYNC_PREWRITE); 1525 break; 1526 } 1527 1528 /* We want short packets, and it is short: it's done */ 1529 usb_syncmem(&std->dma, 1530 std->offs + offsetof(uhci_td_t, td_token), 1531 sizeof(std->td.td_token), 1532 BUS_DMASYNC_POSTWRITE); 1533 1534 if ((status & UHCI_TD_SPD) && 1535 UHCI_TD_GET_ACTLEN(status) < 1536 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1537 goto done; 1538 } 1539 } 1540 } 1541 1542 /* Called with USB lock held. */ 1543 void 1544 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1545 { 1546 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1547 struct usbd_xfer *xfer = &ux->ux_xfer; 1548 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1549 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1550 uhci_soft_td_t *std; 1551 uint32_t status = 0, nstatus; 1552 bool polling = sc->sc_bus.ub_usepolling; 1553 int actlen; 1554 1555 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1556 1557 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1558 1559 /* 1560 * Make sure the timeout handler didn't run or ran to the end 1561 * and set the transfer status. 1562 */ 1563 callout_halt(&xfer->ux_callout, polling ? NULL : &sc->sc_lock); 1564 if (xfer->ux_status == USBD_CANCELLED || 1565 xfer->ux_status == USBD_TIMEOUT) { 1566 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1567 return; 1568 } 1569 1570 #ifdef DIAGNOSTIC 1571 #ifdef UHCI_DEBUG 1572 if (ux->ux_isdone) { 1573 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1574 uhci_dump_ii(ux); 1575 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1576 } 1577 #endif 1578 KASSERT(!ux->ux_isdone); 1579 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1580 ux->ux_type, xfer->ux_status); 1581 ux->ux_isdone = true; 1582 #endif 1583 1584 if (xfer->ux_nframes != 0) { 1585 /* Isoc transfer, do things differently. */ 1586 uhci_soft_td_t **stds = upipe->isoc.stds; 1587 int i, n, nframes, len; 1588 1589 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1590 1591 nframes = xfer->ux_nframes; 1592 actlen = 0; 1593 n = ux->ux_curframe; 1594 for (i = 0; i < nframes; i++) { 1595 std = stds[n]; 1596 #ifdef UHCI_DEBUG 1597 if (uhcidebug >= 5) { 1598 DPRINTF("isoc TD %d", i, 0, 0, 0); 1599 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1600 uhci_dump_td(std); 1601 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1602 } 1603 #endif 1604 if (++n >= UHCI_VFRAMELIST_COUNT) 1605 n = 0; 1606 usb_syncmem(&std->dma, 1607 std->offs + offsetof(uhci_td_t, td_status), 1608 sizeof(std->td.td_status), 1609 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1610 status = le32toh(std->td.td_status); 1611 len = UHCI_TD_GET_ACTLEN(status); 1612 xfer->ux_frlengths[i] = len; 1613 actlen += len; 1614 } 1615 upipe->isoc.inuse -= nframes; 1616 xfer->ux_actlen = actlen; 1617 xfer->ux_status = USBD_NORMAL_COMPLETION; 1618 goto end; 1619 } 1620 1621 #ifdef UHCI_DEBUG 1622 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1623 if (uhcidebug >= 10) { 1624 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1625 uhci_dump_tds(ux->ux_stdstart); 1626 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1627 } 1628 #endif 1629 1630 /* The transfer is done, compute actual length and status. */ 1631 actlen = 0; 1632 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1633 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1634 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1635 nstatus = le32toh(std->td.td_status); 1636 if (nstatus & UHCI_TD_ACTIVE) 1637 break; 1638 1639 status = nstatus; 1640 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1641 UHCI_TD_PID_SETUP) 1642 actlen += UHCI_TD_GET_ACTLEN(status); 1643 else { 1644 /* 1645 * UHCI will report CRCTO in addition to a STALL or NAK 1646 * for a SETUP transaction. See section 3.2.2, "TD 1647 * CONTROL AND STATUS". 1648 */ 1649 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1650 status &= ~UHCI_TD_CRCTO; 1651 } 1652 } 1653 /* If there are left over TDs we need to update the toggle. */ 1654 if (std != NULL) 1655 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1656 1657 status &= UHCI_TD_ERROR; 1658 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1659 xfer->ux_actlen = actlen; 1660 if (status != 0) { 1661 1662 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1663 "error, addr=%d, endpt=0x%02x", 1664 xfer->ux_pipe->up_dev->ud_addr, 1665 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1666 0, 0); 1667 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1668 "bitstuff=%d crcto =%d nak =%d babble =%d", 1669 !!(status & UHCI_TD_BITSTUFF), 1670 !!(status & UHCI_TD_CRCTO), 1671 !!(status & UHCI_TD_NAK), 1672 !!(status & UHCI_TD_BABBLE)); 1673 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1674 "dbuffer =%d stalled =%d active =%d", 1675 !!(status & UHCI_TD_DBUFFER), 1676 !!(status & UHCI_TD_STALLED), 1677 !!(status & UHCI_TD_ACTIVE), 1678 0); 1679 1680 if (status == UHCI_TD_STALLED) 1681 xfer->ux_status = USBD_STALLED; 1682 else 1683 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1684 } else { 1685 xfer->ux_status = USBD_NORMAL_COMPLETION; 1686 } 1687 1688 end: 1689 uhci_del_intr_list(sc, ux); 1690 if (cqp) 1691 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1692 1693 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1694 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1695 } 1696 1697 /* 1698 * Called when a request does not complete. 1699 */ 1700 void 1701 uhci_timeout(void *addr) 1702 { 1703 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1704 struct usbd_xfer *xfer = addr; 1705 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1706 bool timeout = false; 1707 1708 DPRINTF("xfer %p", xfer, 0, 0, 0); 1709 1710 mutex_enter(&sc->sc_lock); 1711 if (sc->sc_dying) { 1712 mutex_exit(&sc->sc_lock); 1713 return; 1714 } 1715 if (xfer->ux_status != USBD_CANCELLED) { 1716 xfer->ux_status = USBD_TIMEOUT; 1717 timeout = true; 1718 } 1719 mutex_exit(&sc->sc_lock); 1720 1721 if (timeout) { 1722 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1723 1724 /* Execute the abort in a process context. */ 1725 usb_init_task(&xfer->ux_aborttask, uhci_timeout_task, xfer, 1726 USB_TASKQ_MPSAFE); 1727 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 1728 } 1729 } 1730 1731 void 1732 uhci_timeout_task(void *addr) 1733 { 1734 struct usbd_xfer *xfer = addr; 1735 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1736 1737 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1738 1739 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1740 1741 mutex_enter(&sc->sc_lock); 1742 KASSERT(xfer->ux_status == USBD_TIMEOUT); 1743 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1744 mutex_exit(&sc->sc_lock); 1745 } 1746 1747 void 1748 uhci_poll(struct usbd_bus *bus) 1749 { 1750 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1751 1752 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1753 mutex_spin_enter(&sc->sc_intr_lock); 1754 uhci_intr1(sc); 1755 mutex_spin_exit(&sc->sc_intr_lock); 1756 } 1757 } 1758 1759 void 1760 uhci_reset(uhci_softc_t *sc) 1761 { 1762 int n; 1763 1764 UHCICMD(sc, UHCI_CMD_HCRESET); 1765 /* The reset bit goes low when the controller is done. */ 1766 for (n = 0; n < UHCI_RESET_TIMEOUT && 1767 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1768 usb_delay_ms(&sc->sc_bus, 1); 1769 if (n >= UHCI_RESET_TIMEOUT) 1770 printf("%s: controller did not reset\n", 1771 device_xname(sc->sc_dev)); 1772 } 1773 1774 usbd_status 1775 uhci_run(uhci_softc_t *sc, int run, int locked) 1776 { 1777 int n, running; 1778 uint16_t cmd; 1779 1780 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1781 1782 run = run != 0; 1783 if (!locked) 1784 mutex_spin_enter(&sc->sc_intr_lock); 1785 1786 DPRINTF("setting run=%d", run, 0, 0, 0); 1787 cmd = UREAD2(sc, UHCI_CMD); 1788 if (run) 1789 cmd |= UHCI_CMD_RS; 1790 else 1791 cmd &= ~UHCI_CMD_RS; 1792 UHCICMD(sc, cmd); 1793 for (n = 0; n < 10; n++) { 1794 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1795 /* return when we've entered the state we want */ 1796 if (run == running) { 1797 if (!locked) 1798 mutex_spin_exit(&sc->sc_intr_lock); 1799 DPRINTF("done cmd=0x%x sts=0x%x", 1800 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1801 return USBD_NORMAL_COMPLETION; 1802 } 1803 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1804 } 1805 if (!locked) 1806 mutex_spin_exit(&sc->sc_intr_lock); 1807 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1808 run ? "start" : "stop"); 1809 return USBD_IOERROR; 1810 } 1811 1812 /* 1813 * Memory management routines. 1814 * uhci_alloc_std allocates TDs 1815 * uhci_alloc_sqh allocates QHs 1816 * These two routines do their own free list management, 1817 * partly for speed, partly because allocating DMAable memory 1818 * has page size granularity so much memory would be wasted if 1819 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1820 */ 1821 1822 uhci_soft_td_t * 1823 uhci_alloc_std(uhci_softc_t *sc) 1824 { 1825 uhci_soft_td_t *std; 1826 usbd_status err; 1827 int i, offs; 1828 usb_dma_t dma; 1829 1830 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1831 1832 mutex_enter(&sc->sc_lock); 1833 if (sc->sc_freetds == NULL) { 1834 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1835 mutex_exit(&sc->sc_lock); 1836 1837 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1838 UHCI_TD_ALIGN, &dma); 1839 if (err) 1840 return NULL; 1841 1842 mutex_enter(&sc->sc_lock); 1843 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1844 offs = i * UHCI_STD_SIZE; 1845 std = KERNADDR(&dma, offs); 1846 std->physaddr = DMAADDR(&dma, offs); 1847 std->dma = dma; 1848 std->offs = offs; 1849 std->link.std = sc->sc_freetds; 1850 sc->sc_freetds = std; 1851 } 1852 } 1853 std = sc->sc_freetds; 1854 sc->sc_freetds = std->link.std; 1855 mutex_exit(&sc->sc_lock); 1856 1857 memset(&std->td, 0, sizeof(uhci_td_t)); 1858 1859 return std; 1860 } 1861 1862 #define TD_IS_FREE 0x12345678 1863 1864 void 1865 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1866 { 1867 KASSERT(mutex_owned(&sc->sc_lock)); 1868 1869 #ifdef DIAGNOSTIC 1870 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1871 printf("%s: freeing free TD %p\n", __func__, std); 1872 return; 1873 } 1874 std->td.td_token = htole32(TD_IS_FREE); 1875 #endif 1876 1877 std->link.std = sc->sc_freetds; 1878 sc->sc_freetds = std; 1879 } 1880 1881 void 1882 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1883 { 1884 mutex_enter(&sc->sc_lock); 1885 uhci_free_std_locked(sc, std); 1886 mutex_exit(&sc->sc_lock); 1887 } 1888 1889 uhci_soft_qh_t * 1890 uhci_alloc_sqh(uhci_softc_t *sc) 1891 { 1892 uhci_soft_qh_t *sqh; 1893 usbd_status err; 1894 int i, offs; 1895 usb_dma_t dma; 1896 1897 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1898 1899 mutex_enter(&sc->sc_lock); 1900 if (sc->sc_freeqhs == NULL) { 1901 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1902 mutex_exit(&sc->sc_lock); 1903 1904 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1905 UHCI_QH_ALIGN, &dma); 1906 if (err) 1907 return NULL; 1908 1909 mutex_enter(&sc->sc_lock); 1910 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1911 offs = i * UHCI_SQH_SIZE; 1912 sqh = KERNADDR(&dma, offs); 1913 sqh->physaddr = DMAADDR(&dma, offs); 1914 sqh->dma = dma; 1915 sqh->offs = offs; 1916 sqh->hlink = sc->sc_freeqhs; 1917 sc->sc_freeqhs = sqh; 1918 } 1919 } 1920 sqh = sc->sc_freeqhs; 1921 sc->sc_freeqhs = sqh->hlink; 1922 mutex_exit(&sc->sc_lock); 1923 1924 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1925 1926 return sqh; 1927 } 1928 1929 void 1930 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1931 { 1932 KASSERT(mutex_owned(&sc->sc_lock)); 1933 1934 sqh->hlink = sc->sc_freeqhs; 1935 sc->sc_freeqhs = sqh; 1936 } 1937 1938 #if 0 1939 void 1940 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1941 uhci_soft_td_t *stdend) 1942 { 1943 uhci_soft_td_t *p; 1944 uint32_t td_link; 1945 1946 /* 1947 * to avoid race condition with the controller which may be looking 1948 * at this chain, we need to first invalidate all links, and 1949 * then wait for the controller to move to another queue 1950 */ 1951 for (p = std; p != stdend; p = p->link.std) { 1952 usb_syncmem(&p->dma, 1953 p->offs + offsetof(uhci_td_t, td_link), 1954 sizeof(p->td.td_link), 1955 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1956 td_link = le32toh(p->td.td_link); 1957 usb_syncmem(&p->dma, 1958 p->offs + offsetof(uhci_td_t, td_link), 1959 sizeof(p->td.td_link), 1960 BUS_DMASYNC_PREREAD); 1961 if ((td_link & UHCI_PTR_T) == 0) { 1962 p->td.td_link = htole32(UHCI_PTR_T); 1963 usb_syncmem(&p->dma, 1964 p->offs + offsetof(uhci_td_t, td_link), 1965 sizeof(p->td.td_link), 1966 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1967 } 1968 } 1969 delay(UHCI_QH_REMOVE_DELAY); 1970 1971 for (; std != stdend; std = p) { 1972 p = std->link.std; 1973 uhci_free_std(sc, std); 1974 } 1975 } 1976 #endif 1977 1978 int 1979 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len, 1980 int rd, uhci_soft_td_t **sp) 1981 { 1982 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1983 uint16_t flags = xfer->ux_flags; 1984 uhci_soft_td_t *p; 1985 1986 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1987 1988 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 1989 1990 ASSERT_SLEEPABLE(); 1991 KASSERT(sp); 1992 1993 int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 1994 if (maxp == 0) { 1995 printf("%s: maxp=0\n", __func__); 1996 return EINVAL; 1997 } 1998 size_t ntd = (len + maxp - 1) / maxp; 1999 if (!rd && (flags & USBD_FORCE_SHORT_XFER)) { 2000 ntd++; 2001 } 2002 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 2003 2004 uxfer->ux_stds = NULL; 2005 uxfer->ux_nstd = ntd; 2006 if (ntd == 0) { 2007 *sp = NULL; 2008 DPRINTF("ntd=0", 0, 0, 0, 0); 2009 return 0; 2010 } 2011 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2012 KM_SLEEP); 2013 2014 for (int i = 0; i < ntd; i++) { 2015 p = uhci_alloc_std(sc); 2016 if (p == NULL) { 2017 if (i != 0) { 2018 uxfer->ux_nstd = i; 2019 uhci_free_stds(sc, uxfer); 2020 } 2021 kmem_free(uxfer->ux_stds, 2022 sizeof(uhci_soft_td_t *) * ntd); 2023 return ENOMEM; 2024 } 2025 uxfer->ux_stds[i] = p; 2026 } 2027 2028 *sp = uxfer->ux_stds[0]; 2029 2030 return 0; 2031 } 2032 2033 Static void 2034 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2035 { 2036 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2037 2038 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2039 2040 mutex_enter(&sc->sc_lock); 2041 for (size_t i = 0; i < ux->ux_nstd; i++) { 2042 uhci_soft_td_t *std = ux->ux_stds[i]; 2043 #ifdef DIAGNOSTIC 2044 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2045 printf("%s: freeing free TD %p\n", __func__, std); 2046 return; 2047 } 2048 std->td.td_token = htole32(TD_IS_FREE); 2049 #endif 2050 ux->ux_stds[i]->link.std = sc->sc_freetds; 2051 sc->sc_freetds = std; 2052 } 2053 mutex_exit(&sc->sc_lock); 2054 } 2055 2056 2057 Static void 2058 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2059 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2060 { 2061 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2062 struct usbd_pipe *pipe = xfer->ux_pipe; 2063 usb_dma_t *dma = &xfer->ux_dmabuf; 2064 uint16_t flags = xfer->ux_flags; 2065 uhci_soft_td_t *std, *prev; 2066 int len = length; 2067 int tog = *toggle; 2068 int maxp; 2069 uint32_t status; 2070 size_t i; 2071 2072 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2073 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2074 len, isread, *toggle); 2075 2076 KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2077 2078 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2079 KASSERT(maxp != 0); 2080 2081 int addr = xfer->ux_pipe->up_dev->ud_addr; 2082 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2083 2084 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2085 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2086 status |= UHCI_TD_LS; 2087 if (flags & USBD_SHORT_XFER_OK) 2088 status |= UHCI_TD_SPD; 2089 usb_syncmem(dma, 0, len, 2090 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2091 std = prev = NULL; 2092 for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) { 2093 int l = len; 2094 std = uxfer->ux_stds[i]; 2095 if (l > maxp) 2096 l = maxp; 2097 2098 if (prev) { 2099 prev->link.std = std; 2100 prev->td.td_link = htole32( 2101 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2102 ); 2103 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2105 } 2106 2107 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2108 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2109 2110 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2111 std->td.td_status = htole32(status); 2112 std->td.td_token = htole32( 2113 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2114 UHCI_TD_SET_DEVADDR(addr) | 2115 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2116 UHCI_TD_SET_DT(tog) | 2117 UHCI_TD_SET_MAXLEN(l) 2118 ); 2119 std->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2120 2121 std->link.std = NULL; 2122 2123 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2124 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2125 tog ^= 1; 2126 2127 len -= l; 2128 } 2129 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2130 xfer, length, len, maxp, uxfer->ux_nstd, i); 2131 2132 if (!isread && 2133 (flags & USBD_FORCE_SHORT_XFER) && 2134 length % maxp == 0) { 2135 /* Force a 0 length transfer at the end. */ 2136 KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i, 2137 uxfer->ux_nstd); 2138 std = uxfer->ux_stds[i++]; 2139 2140 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2141 std->td.td_status = htole32(status); 2142 std->td.td_token = htole32( 2143 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2144 UHCI_TD_SET_DEVADDR(addr) | 2145 UHCI_TD_SET_PID(UHCI_TD_PID_OUT) | 2146 UHCI_TD_SET_DT(tog) | 2147 UHCI_TD_SET_MAXLEN(0) 2148 ); 2149 std->td.td_buffer = 0; 2150 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2151 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2152 2153 std->link.std = NULL; 2154 if (prev) { 2155 prev->link.std = std; 2156 prev->td.td_link = htole32( 2157 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2158 ); 2159 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2161 } 2162 tog ^= 1; 2163 } 2164 *lstd = std; 2165 *toggle = tog; 2166 } 2167 2168 void 2169 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2170 { 2171 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2172 upipe->nexttoggle = 0; 2173 } 2174 2175 void 2176 uhci_noop(struct usbd_pipe *pipe) 2177 { 2178 } 2179 2180 int 2181 uhci_device_bulk_init(struct usbd_xfer *xfer) 2182 { 2183 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2184 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2185 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2186 int endpt = ed->bEndpointAddress; 2187 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2188 int len = xfer->ux_bufsize; 2189 int err = 0; 2190 2191 2192 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2193 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2194 2195 if (sc->sc_dying) 2196 return USBD_IOERROR; 2197 2198 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2199 2200 uxfer->ux_type = UX_BULK; 2201 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart); 2202 if (err) 2203 return err; 2204 2205 #ifdef UHCI_DEBUG 2206 if (uhcidebug >= 10) { 2207 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2208 uhci_dump_tds(uxfer->ux_stdstart); 2209 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2210 } 2211 #endif 2212 2213 return 0; 2214 } 2215 2216 Static void 2217 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2218 { 2219 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2220 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2221 2222 KASSERT(ux->ux_type == UX_BULK); 2223 2224 if (ux->ux_nstd) { 2225 uhci_free_stds(sc, ux); 2226 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2227 } 2228 } 2229 2230 usbd_status 2231 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2232 { 2233 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2234 usbd_status err; 2235 2236 /* Insert last in queue. */ 2237 mutex_enter(&sc->sc_lock); 2238 err = usb_insert_transfer(xfer); 2239 mutex_exit(&sc->sc_lock); 2240 if (err) 2241 return err; 2242 2243 /* 2244 * Pipe isn't running (otherwise err would be USBD_INPROG), 2245 * so start it first. 2246 */ 2247 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2248 } 2249 2250 usbd_status 2251 uhci_device_bulk_start(struct usbd_xfer *xfer) 2252 { 2253 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2254 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2255 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2256 uhci_soft_td_t *data, *dataend; 2257 uhci_soft_qh_t *sqh; 2258 int len; 2259 int endpt; 2260 int isread; 2261 2262 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2263 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2264 xfer->ux_flags, 0); 2265 2266 if (sc->sc_dying) 2267 return USBD_IOERROR; 2268 2269 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2270 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2271 2272 len = xfer->ux_length; 2273 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2274 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2275 sqh = upipe->bulk.sqh; 2276 2277 /* Take lock here to protect nexttoggle */ 2278 mutex_enter(&sc->sc_lock); 2279 2280 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2281 &dataend); 2282 2283 data = ux->ux_stdstart; 2284 ux->ux_stdend = dataend; 2285 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2286 usb_syncmem(&dataend->dma, 2287 dataend->offs + offsetof(uhci_td_t, td_status), 2288 sizeof(dataend->td.td_status), 2289 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2290 2291 #ifdef UHCI_DEBUG 2292 if (uhcidebug >= 10) { 2293 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2294 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2295 uhci_dump_tds(data); 2296 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2297 } 2298 #endif 2299 2300 KASSERT(ux->ux_isdone); 2301 #ifdef DIAGNOSTIC 2302 ux->ux_isdone = false; 2303 #endif 2304 2305 sqh->elink = data; 2306 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2307 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2308 2309 uhci_add_bulk(sc, sqh); 2310 uhci_add_intr_list(sc, ux); 2311 2312 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2313 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2314 uhci_timeout, xfer); 2315 } 2316 xfer->ux_status = USBD_IN_PROGRESS; 2317 mutex_exit(&sc->sc_lock); 2318 2319 return USBD_IN_PROGRESS; 2320 } 2321 2322 /* Abort a device bulk request. */ 2323 void 2324 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2325 { 2326 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2327 2328 KASSERT(mutex_owned(&sc->sc_lock)); 2329 2330 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2331 2332 uhci_abort_xfer(xfer, USBD_CANCELLED); 2333 } 2334 2335 /* 2336 * Cancel or timeout a device request. We have two cases to deal with 2337 * 2338 * 1) A driver wants to stop scheduled or inflight transfers 2339 * 2) A transfer has timed out 2340 * 2341 * It's impossible to guarantee that the requested transfer will not 2342 * have (partially) happened since the hardware runs concurrently. 2343 * 2344 * Transfer state is protected by the bus lock and we set the transfer status 2345 * as soon as either of the above happens (with bus lock held). 2346 * 2347 * To allow the hardware time to notice we simply wait. 2348 */ 2349 void 2350 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2351 { 2352 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2353 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2354 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2355 uhci_soft_td_t *std; 2356 int wake; 2357 2358 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2359 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2360 2361 KASSERT(mutex_owned(&sc->sc_lock)); 2362 ASSERT_SLEEPABLE(); 2363 2364 if (sc->sc_dying) { 2365 /* If we're dying, just do the software part. */ 2366 xfer->ux_status = status; /* make software ignore it */ 2367 callout_stop(&xfer->ux_callout); 2368 usb_transfer_complete(xfer); 2369 return; 2370 } 2371 2372 /* 2373 * If an abort is already in progress then just wait for it to 2374 * complete and return. 2375 */ 2376 if (xfer->ux_hcflags & UXFER_ABORTING) { 2377 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2378 #ifdef DIAGNOSTIC 2379 if (status == USBD_TIMEOUT) 2380 printf("%s: TIMEOUT while aborting\n", __func__); 2381 #endif 2382 /* Override the status which might be USBD_TIMEOUT. */ 2383 xfer->ux_status = status; 2384 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2385 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2386 while (xfer->ux_hcflags & UXFER_ABORTING) 2387 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2388 goto done; 2389 } 2390 xfer->ux_hcflags |= UXFER_ABORTING; 2391 2392 /* 2393 * Step 1: When cancelling a transfer make sure the timeout handler 2394 * didn't run or ran to the end and saw the USBD_CANCELLED status. 2395 * Otherwise we must have got here via a timeout. 2396 */ 2397 if (status == USBD_CANCELLED) { 2398 xfer->ux_status = status; 2399 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2400 } else { 2401 KASSERT(xfer->ux_status == USBD_TIMEOUT); 2402 } 2403 2404 /* 2405 * Step 2: Make interrupt routine and hardware ignore xfer. 2406 */ 2407 uhci_del_intr_list(sc, ux); 2408 2409 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2410 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2411 usb_syncmem(&std->dma, 2412 std->offs + offsetof(uhci_td_t, td_status), 2413 sizeof(std->td.td_status), 2414 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2415 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2416 usb_syncmem(&std->dma, 2417 std->offs + offsetof(uhci_td_t, td_status), 2418 sizeof(std->td.td_status), 2419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2420 } 2421 2422 /* 2423 * Step 3: Wait until we know hardware has finished any possible 2424 * use of the xfer. Also make sure the soft interrupt routine 2425 * has run. 2426 */ 2427 /* Hardware finishes in 1ms */ 2428 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2429 2430 /* 2431 * Step 4: Execute callback. 2432 */ 2433 DPRINTF("callback", 0, 0, 0, 0); 2434 #ifdef DIAGNOSTIC 2435 ux->ux_isdone = true; 2436 #endif 2437 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2438 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2439 usb_transfer_complete(xfer); 2440 if (wake) 2441 cv_broadcast(&xfer->ux_hccv); 2442 done: 2443 KASSERT(mutex_owned(&sc->sc_lock)); 2444 } 2445 2446 /* Close a device bulk pipe. */ 2447 void 2448 uhci_device_bulk_close(struct usbd_pipe *pipe) 2449 { 2450 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2451 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2452 2453 KASSERT(mutex_owned(&sc->sc_lock)); 2454 2455 uhci_free_sqh(sc, upipe->bulk.sqh); 2456 2457 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2458 } 2459 2460 int 2461 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2462 { 2463 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2464 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2465 usb_device_request_t *req = &xfer->ux_request; 2466 struct usbd_device *dev = upipe->pipe.up_dev; 2467 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2468 uhci_soft_td_t *data = NULL; 2469 int len; 2470 usbd_status err; 2471 int isread; 2472 2473 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2474 DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize, 2475 dev->ud_addr, upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2476 2477 isread = req->bmRequestType & UT_READ; 2478 len = xfer->ux_bufsize; 2479 2480 uxfer->ux_type = UX_CTRL; 2481 /* Set up data transaction */ 2482 if (len != 0) { 2483 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data); 2484 if (err) 2485 return err; 2486 } 2487 /* Set up interrupt info. */ 2488 uxfer->ux_setup = upipe->ctrl.setup; 2489 uxfer->ux_stat = upipe->ctrl.stat; 2490 uxfer->ux_data = data; 2491 2492 return 0; 2493 } 2494 2495 Static void 2496 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2497 { 2498 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2499 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2500 2501 KASSERT(ux->ux_type == UX_CTRL); 2502 2503 if (ux->ux_nstd) { 2504 uhci_free_stds(sc, ux); 2505 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2506 } 2507 } 2508 2509 usbd_status 2510 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2511 { 2512 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2513 usbd_status err; 2514 2515 /* Insert last in queue. */ 2516 mutex_enter(&sc->sc_lock); 2517 err = usb_insert_transfer(xfer); 2518 mutex_exit(&sc->sc_lock); 2519 if (err) 2520 return err; 2521 2522 /* 2523 * Pipe isn't running (otherwise err would be USBD_INPROG), 2524 * so start it first. 2525 */ 2526 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2527 } 2528 2529 usbd_status 2530 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2531 { 2532 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2533 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2534 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2535 usb_device_request_t *req = &xfer->ux_request; 2536 struct usbd_device *dev = upipe->pipe.up_dev; 2537 int addr = dev->ud_addr; 2538 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2539 uhci_soft_td_t *setup, *stat, *next, *dataend; 2540 uhci_soft_qh_t *sqh; 2541 int len; 2542 int isread; 2543 2544 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2545 2546 if (sc->sc_dying) 2547 return USBD_IOERROR; 2548 2549 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2550 2551 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2552 "wValue=0x%04x, wIndex=0x%04x", 2553 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2554 UGETW(req->wIndex)); 2555 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2556 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2557 2558 isread = req->bmRequestType & UT_READ; 2559 len = UGETW(req->wLength); 2560 2561 setup = upipe->ctrl.setup; 2562 stat = upipe->ctrl.stat; 2563 sqh = upipe->ctrl.sqh; 2564 2565 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2566 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2567 2568 mutex_enter(&sc->sc_lock); 2569 2570 /* Set up data transaction */ 2571 if (len != 0) { 2572 upipe->nexttoggle = 1; 2573 next = uxfer->ux_data; 2574 uhci_reset_std_chain(sc, xfer, len, isread, 2575 &upipe->nexttoggle, &dataend); 2576 dataend->link.std = stat; 2577 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2578 usb_syncmem(&dataend->dma, 2579 dataend->offs + offsetof(uhci_td_t, td_link), 2580 sizeof(dataend->td.td_link), 2581 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2582 } else { 2583 next = stat; 2584 } 2585 2586 const uint32_t status = UHCI_TD_ZERO_ACTLEN( 2587 UHCI_TD_SET_ERRCNT(3) | 2588 UHCI_TD_ACTIVE | 2589 (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0) 2590 ); 2591 setup->link.std = next; 2592 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2593 setup->td.td_status = htole32(status); 2594 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2595 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2596 2597 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2598 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2599 2600 stat->link.std = NULL; 2601 stat->td.td_link = htole32(UHCI_PTR_T); 2602 stat->td.td_status = htole32(status | UHCI_TD_IOC); 2603 stat->td.td_token = 2604 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2605 UHCI_TD_IN (0, endpt, addr, 1)); 2606 stat->td.td_buffer = htole32(0); 2607 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2608 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2609 2610 #ifdef UHCI_DEBUG 2611 if (uhcidebug >= 10) { 2612 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2613 DPRINTF("before transfer", 0, 0, 0, 0); 2614 uhci_dump_tds(setup); 2615 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2616 } 2617 #endif 2618 2619 /* Set up interrupt info. */ 2620 uxfer->ux_setup = setup; 2621 uxfer->ux_stat = stat; 2622 KASSERT(uxfer->ux_isdone); 2623 #ifdef DIAGNOSTIC 2624 uxfer->ux_isdone = false; 2625 #endif 2626 2627 sqh->elink = setup; 2628 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2629 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2630 2631 if (dev->ud_speed == USB_SPEED_LOW) 2632 uhci_add_ls_ctrl(sc, sqh); 2633 else 2634 uhci_add_hs_ctrl(sc, sqh); 2635 uhci_add_intr_list(sc, uxfer); 2636 #ifdef UHCI_DEBUG 2637 if (uhcidebug >= 12) { 2638 uhci_soft_td_t *std; 2639 uhci_soft_qh_t *xqh; 2640 uhci_soft_qh_t *sxqh; 2641 int maxqh = 0; 2642 uhci_physaddr_t link; 2643 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2644 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2645 for (std = sc->sc_vframes[0].htd, link = 0; 2646 (link & UHCI_PTR_QH) == 0; 2647 std = std->link.std) { 2648 link = le32toh(std->td.td_link); 2649 uhci_dump_td(std); 2650 } 2651 sxqh = (uhci_soft_qh_t *)std; 2652 uhci_dump_qh(sxqh); 2653 for (xqh = sxqh; 2654 xqh != NULL; 2655 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2656 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2657 uhci_dump_qh(xqh); 2658 } 2659 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2660 uhci_dump_qh(sqh); 2661 uhci_dump_tds(sqh->elink); 2662 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2663 } 2664 #endif 2665 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2666 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2667 uhci_timeout, xfer); 2668 } 2669 xfer->ux_status = USBD_IN_PROGRESS; 2670 mutex_exit(&sc->sc_lock); 2671 2672 return USBD_IN_PROGRESS; 2673 } 2674 2675 int 2676 uhci_device_intr_init(struct usbd_xfer *xfer) 2677 { 2678 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2679 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2680 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2681 int endpt = ed->bEndpointAddress; 2682 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2683 int len = xfer->ux_bufsize; 2684 int err; 2685 2686 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2687 2688 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2689 xfer->ux_flags, 0); 2690 2691 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2692 KASSERT(len != 0); 2693 2694 ux->ux_type = UX_INTR; 2695 ux->ux_nstd = 0; 2696 err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart); 2697 2698 return err; 2699 } 2700 2701 Static void 2702 uhci_device_intr_fini(struct usbd_xfer *xfer) 2703 { 2704 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2705 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2706 2707 KASSERT(ux->ux_type == UX_INTR); 2708 2709 if (ux->ux_nstd) { 2710 uhci_free_stds(sc, ux); 2711 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2712 } 2713 } 2714 2715 usbd_status 2716 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2717 { 2718 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2719 usbd_status err; 2720 2721 /* Insert last in queue. */ 2722 mutex_enter(&sc->sc_lock); 2723 err = usb_insert_transfer(xfer); 2724 mutex_exit(&sc->sc_lock); 2725 if (err) 2726 return err; 2727 2728 /* 2729 * Pipe isn't running (otherwise err would be USBD_INPROG), 2730 * so start it first. 2731 */ 2732 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2733 } 2734 2735 usbd_status 2736 uhci_device_intr_start(struct usbd_xfer *xfer) 2737 { 2738 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2739 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2740 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2741 uhci_soft_td_t *data, *dataend; 2742 uhci_soft_qh_t *sqh; 2743 int isread, endpt; 2744 int i; 2745 2746 if (sc->sc_dying) 2747 return USBD_IOERROR; 2748 2749 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2750 2751 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2752 xfer->ux_flags, 0); 2753 2754 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2755 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2756 2757 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2758 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2759 2760 data = ux->ux_stdstart; 2761 2762 KASSERT(ux->ux_isdone); 2763 #ifdef DIAGNOSTIC 2764 ux->ux_isdone = false; 2765 #endif 2766 2767 /* Take lock to protect nexttoggle */ 2768 mutex_enter(&sc->sc_lock); 2769 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2770 &upipe->nexttoggle, &dataend); 2771 2772 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2773 usb_syncmem(&dataend->dma, 2774 dataend->offs + offsetof(uhci_td_t, td_status), 2775 sizeof(dataend->td.td_status), 2776 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2777 ux->ux_stdend = dataend; 2778 2779 #ifdef UHCI_DEBUG 2780 if (uhcidebug >= 10) { 2781 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2782 uhci_dump_tds(data); 2783 uhci_dump_qh(upipe->intr.qhs[0]); 2784 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2785 } 2786 #endif 2787 2788 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2789 for (i = 0; i < upipe->intr.npoll; i++) { 2790 sqh = upipe->intr.qhs[i]; 2791 sqh->elink = data; 2792 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2793 usb_syncmem(&sqh->dma, 2794 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2795 sizeof(sqh->qh.qh_elink), 2796 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2797 } 2798 uhci_add_intr_list(sc, ux); 2799 xfer->ux_status = USBD_IN_PROGRESS; 2800 mutex_exit(&sc->sc_lock); 2801 2802 #ifdef UHCI_DEBUG 2803 if (uhcidebug >= 10) { 2804 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2805 uhci_dump_tds(data); 2806 uhci_dump_qh(upipe->intr.qhs[0]); 2807 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2808 } 2809 #endif 2810 2811 return USBD_IN_PROGRESS; 2812 } 2813 2814 /* Abort a device control request. */ 2815 void 2816 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2817 { 2818 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2819 2820 KASSERT(mutex_owned(&sc->sc_lock)); 2821 2822 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2823 uhci_abort_xfer(xfer, USBD_CANCELLED); 2824 } 2825 2826 /* Close a device control pipe. */ 2827 void 2828 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2829 { 2830 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2831 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2832 2833 uhci_free_sqh(sc, upipe->ctrl.sqh); 2834 uhci_free_std_locked(sc, upipe->ctrl.setup); 2835 uhci_free_std_locked(sc, upipe->ctrl.stat); 2836 2837 } 2838 2839 /* Abort a device interrupt request. */ 2840 void 2841 uhci_device_intr_abort(struct usbd_xfer *xfer) 2842 { 2843 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2844 2845 KASSERT(mutex_owned(&sc->sc_lock)); 2846 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2847 2848 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2849 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2850 2851 uhci_abort_xfer(xfer, USBD_CANCELLED); 2852 } 2853 2854 /* Close a device interrupt pipe. */ 2855 void 2856 uhci_device_intr_close(struct usbd_pipe *pipe) 2857 { 2858 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2859 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2860 int i, npoll; 2861 2862 KASSERT(mutex_owned(&sc->sc_lock)); 2863 2864 /* Unlink descriptors from controller data structures. */ 2865 npoll = upipe->intr.npoll; 2866 for (i = 0; i < npoll; i++) 2867 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2868 2869 /* 2870 * We now have to wait for any activity on the physical 2871 * descriptors to stop. 2872 */ 2873 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2874 2875 for (i = 0; i < npoll; i++) 2876 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2877 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2878 } 2879 2880 int 2881 uhci_device_isoc_init(struct usbd_xfer *xfer) 2882 { 2883 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2884 2885 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2886 KASSERT(xfer->ux_nframes != 0); 2887 KASSERT(ux->ux_isdone); 2888 2889 ux->ux_type = UX_ISOC; 2890 return 0; 2891 } 2892 2893 Static void 2894 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2895 { 2896 struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer); 2897 2898 KASSERT(ux->ux_type == UX_ISOC); 2899 } 2900 2901 usbd_status 2902 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2903 { 2904 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2905 usbd_status err __diagused; 2906 2907 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2908 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2909 2910 /* Put it on our queue, */ 2911 mutex_enter(&sc->sc_lock); 2912 err = usb_insert_transfer(xfer); 2913 mutex_exit(&sc->sc_lock); 2914 2915 KASSERT(err == USBD_NORMAL_COMPLETION); 2916 2917 /* insert into schedule, */ 2918 2919 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2920 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2921 struct isoc *isoc = &upipe->isoc; 2922 uhci_soft_td_t *std = NULL; 2923 uint32_t buf, len, status, offs; 2924 int i, next, nframes; 2925 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2926 2927 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2928 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2929 2930 if (sc->sc_dying) 2931 return USBD_IOERROR; 2932 2933 if (xfer->ux_status == USBD_IN_PROGRESS) { 2934 /* This request has already been entered into the frame list */ 2935 printf("%s: xfer=%p in frame list\n", __func__, xfer); 2936 /* XXX */ 2937 } 2938 2939 #ifdef DIAGNOSTIC 2940 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2941 printf("%s: overflow!\n", __func__); 2942 #endif 2943 2944 KASSERT(xfer->ux_nframes != 0); 2945 2946 mutex_enter(&sc->sc_lock); 2947 next = isoc->next; 2948 if (next == -1) { 2949 /* Not in use yet, schedule it a few frames ahead. */ 2950 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2951 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2952 } 2953 2954 xfer->ux_status = USBD_IN_PROGRESS; 2955 ux->ux_curframe = next; 2956 2957 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2958 offs = 0; 2959 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2960 UHCI_TD_ACTIVE | 2961 UHCI_TD_IOS); 2962 nframes = xfer->ux_nframes; 2963 for (i = 0; i < nframes; i++) { 2964 std = isoc->stds[next]; 2965 if (++next >= UHCI_VFRAMELIST_COUNT) 2966 next = 0; 2967 len = xfer->ux_frlengths[i]; 2968 std->td.td_buffer = htole32(buf); 2969 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2970 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2971 if (i == nframes - 1) 2972 status |= UHCI_TD_IOC; 2973 std->td.td_status = htole32(status); 2974 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2975 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2976 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2978 #ifdef UHCI_DEBUG 2979 if (uhcidebug >= 5) { 2980 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2981 DPRINTF("TD %d", i, 0, 0, 0); 2982 uhci_dump_td(std); 2983 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2984 } 2985 #endif 2986 buf += len; 2987 offs += len; 2988 } 2989 isoc->next = next; 2990 isoc->inuse += xfer->ux_nframes; 2991 2992 /* Set up interrupt info. */ 2993 ux->ux_stdstart = std; 2994 ux->ux_stdend = std; 2995 2996 KASSERT(ux->ux_isdone); 2997 #ifdef DIAGNOSTIC 2998 ux->ux_isdone = false; 2999 #endif 3000 uhci_add_intr_list(sc, ux); 3001 3002 mutex_exit(&sc->sc_lock); 3003 3004 return USBD_IN_PROGRESS; 3005 } 3006 3007 void 3008 uhci_device_isoc_abort(struct usbd_xfer *xfer) 3009 { 3010 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3011 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3012 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3013 uhci_soft_td_t **stds = upipe->isoc.stds; 3014 uhci_soft_td_t *std; 3015 int i, n, nframes, maxlen, len; 3016 3017 KASSERT(mutex_owned(&sc->sc_lock)); 3018 3019 /* Transfer is already done. */ 3020 if (xfer->ux_status != USBD_NOT_STARTED && 3021 xfer->ux_status != USBD_IN_PROGRESS) { 3022 return; 3023 } 3024 3025 /* Give xfer the requested abort code. */ 3026 xfer->ux_status = USBD_CANCELLED; 3027 3028 /* make hardware ignore it, */ 3029 nframes = xfer->ux_nframes; 3030 n = ux->ux_curframe; 3031 maxlen = 0; 3032 for (i = 0; i < nframes; i++) { 3033 std = stds[n]; 3034 usb_syncmem(&std->dma, 3035 std->offs + offsetof(uhci_td_t, td_status), 3036 sizeof(std->td.td_status), 3037 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3038 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3039 usb_syncmem(&std->dma, 3040 std->offs + offsetof(uhci_td_t, td_status), 3041 sizeof(std->td.td_status), 3042 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3043 usb_syncmem(&std->dma, 3044 std->offs + offsetof(uhci_td_t, td_token), 3045 sizeof(std->td.td_token), 3046 BUS_DMASYNC_POSTWRITE); 3047 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3048 if (len > maxlen) 3049 maxlen = len; 3050 if (++n >= UHCI_VFRAMELIST_COUNT) 3051 n = 0; 3052 } 3053 3054 /* and wait until we are sure the hardware has finished. */ 3055 delay(maxlen); 3056 3057 #ifdef DIAGNOSTIC 3058 ux->ux_isdone = true; 3059 #endif 3060 /* Remove from interrupt list. */ 3061 uhci_del_intr_list(sc, ux); 3062 3063 /* Run callback. */ 3064 usb_transfer_complete(xfer); 3065 3066 KASSERT(mutex_owned(&sc->sc_lock)); 3067 } 3068 3069 void 3070 uhci_device_isoc_close(struct usbd_pipe *pipe) 3071 { 3072 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3073 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3074 uhci_soft_td_t *std, *vstd; 3075 struct isoc *isoc; 3076 int i; 3077 3078 KASSERT(mutex_owned(&sc->sc_lock)); 3079 3080 /* 3081 * Make sure all TDs are marked as inactive. 3082 * Wait for completion. 3083 * Unschedule. 3084 * Deallocate. 3085 */ 3086 isoc = &upipe->isoc; 3087 3088 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3089 std = isoc->stds[i]; 3090 usb_syncmem(&std->dma, 3091 std->offs + offsetof(uhci_td_t, td_status), 3092 sizeof(std->td.td_status), 3093 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3094 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3095 usb_syncmem(&std->dma, 3096 std->offs + offsetof(uhci_td_t, td_status), 3097 sizeof(std->td.td_status), 3098 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3099 } 3100 /* wait for completion */ 3101 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3102 3103 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3104 std = isoc->stds[i]; 3105 for (vstd = sc->sc_vframes[i].htd; 3106 vstd != NULL && vstd->link.std != std; 3107 vstd = vstd->link.std) 3108 ; 3109 if (vstd == NULL) { 3110 /*panic*/ 3111 printf("%s: %p not found\n", __func__, std); 3112 mutex_exit(&sc->sc_lock); 3113 return; 3114 } 3115 vstd->link = std->link; 3116 usb_syncmem(&std->dma, 3117 std->offs + offsetof(uhci_td_t, td_link), 3118 sizeof(std->td.td_link), 3119 BUS_DMASYNC_POSTWRITE); 3120 vstd->td.td_link = std->td.td_link; 3121 usb_syncmem(&vstd->dma, 3122 vstd->offs + offsetof(uhci_td_t, td_link), 3123 sizeof(vstd->td.td_link), 3124 BUS_DMASYNC_PREWRITE); 3125 uhci_free_std_locked(sc, std); 3126 } 3127 3128 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3129 } 3130 3131 usbd_status 3132 uhci_setup_isoc(struct usbd_pipe *pipe) 3133 { 3134 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3135 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3136 int addr = upipe->pipe.up_dev->ud_addr; 3137 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3138 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3139 uhci_soft_td_t *std, *vstd; 3140 uint32_t token; 3141 struct isoc *isoc; 3142 int i; 3143 3144 isoc = &upipe->isoc; 3145 3146 isoc->stds = kmem_alloc( 3147 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3148 if (isoc->stds == NULL) 3149 return USBD_NOMEM; 3150 3151 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3152 UHCI_TD_OUT(0, endpt, addr, 0); 3153 3154 /* Allocate the TDs and mark as inactive; */ 3155 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3156 std = uhci_alloc_std(sc); 3157 if (std == 0) 3158 goto bad; 3159 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3160 std->td.td_token = htole32(token); 3161 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3163 isoc->stds[i] = std; 3164 } 3165 3166 mutex_enter(&sc->sc_lock); 3167 3168 /* Insert TDs into schedule. */ 3169 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3170 std = isoc->stds[i]; 3171 vstd = sc->sc_vframes[i].htd; 3172 usb_syncmem(&vstd->dma, 3173 vstd->offs + offsetof(uhci_td_t, td_link), 3174 sizeof(vstd->td.td_link), 3175 BUS_DMASYNC_POSTWRITE); 3176 std->link = vstd->link; 3177 std->td.td_link = vstd->td.td_link; 3178 usb_syncmem(&std->dma, 3179 std->offs + offsetof(uhci_td_t, td_link), 3180 sizeof(std->td.td_link), 3181 BUS_DMASYNC_PREWRITE); 3182 vstd->link.std = std; 3183 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3184 usb_syncmem(&vstd->dma, 3185 vstd->offs + offsetof(uhci_td_t, td_link), 3186 sizeof(vstd->td.td_link), 3187 BUS_DMASYNC_PREWRITE); 3188 } 3189 mutex_exit(&sc->sc_lock); 3190 3191 isoc->next = -1; 3192 isoc->inuse = 0; 3193 3194 return USBD_NORMAL_COMPLETION; 3195 3196 bad: 3197 while (--i >= 0) 3198 uhci_free_std(sc, isoc->stds[i]); 3199 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3200 return USBD_NOMEM; 3201 } 3202 3203 void 3204 uhci_device_isoc_done(struct usbd_xfer *xfer) 3205 { 3206 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3207 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3208 int i, offs; 3209 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3210 3211 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3212 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3213 xfer->ux_actlen, xfer->ux_state, 0, 0); 3214 3215 #ifdef DIAGNOSTIC 3216 if (ux->ux_stdend == NULL) { 3217 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3218 #ifdef UHCI_DEBUG 3219 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3220 uhci_dump_ii(ux); 3221 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3222 #endif 3223 return; 3224 } 3225 #endif 3226 3227 /* Turn off the interrupt since it is active even if the TD is not. */ 3228 usb_syncmem(&ux->ux_stdend->dma, 3229 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3230 sizeof(ux->ux_stdend->td.td_status), 3231 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3232 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3233 usb_syncmem(&ux->ux_stdend->dma, 3234 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3235 sizeof(ux->ux_stdend->td.td_status), 3236 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3237 3238 offs = 0; 3239 for (i = 0; i < xfer->ux_nframes; i++) { 3240 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3241 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3242 offs += xfer->ux_frlengths[i]; 3243 } 3244 } 3245 3246 void 3247 uhci_device_intr_done(struct usbd_xfer *xfer) 3248 { 3249 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 3250 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3251 uhci_soft_qh_t *sqh; 3252 int i, npoll; 3253 3254 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3255 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3256 3257 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3258 3259 npoll = upipe->intr.npoll; 3260 for (i = 0; i < npoll; i++) { 3261 sqh = upipe->intr.qhs[i]; 3262 sqh->elink = NULL; 3263 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3264 usb_syncmem(&sqh->dma, 3265 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3266 sizeof(sqh->qh.qh_elink), 3267 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3268 } 3269 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3270 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3271 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3272 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3273 } 3274 3275 /* Deallocate request data structures */ 3276 void 3277 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3278 { 3279 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3280 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3281 int len = UGETW(xfer->ux_request.wLength); 3282 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3283 3284 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3285 3286 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3287 3288 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3289 3290 /* XXXNH move to uhci_idone??? */ 3291 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3292 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3293 else 3294 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3295 3296 if (len) { 3297 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3298 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3299 } 3300 usb_syncmem(&upipe->ctrl.reqdma, 0, 3301 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3302 3303 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3304 } 3305 3306 /* Deallocate request data structures */ 3307 void 3308 uhci_device_bulk_done(struct usbd_xfer *xfer) 3309 { 3310 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3311 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3312 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3313 int endpt = ed->bEndpointAddress; 3314 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3315 3316 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3317 DPRINTFN(5, "xfer=%p sc=%p upipe=%p", xfer, sc, upipe, 0); 3318 3319 KASSERT(mutex_owned(&sc->sc_lock)); 3320 3321 uhci_remove_bulk(sc, upipe->bulk.sqh); 3322 3323 if (xfer->ux_length) { 3324 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3325 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3326 } 3327 3328 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3329 } 3330 3331 /* Add interrupt QH, called with vflock. */ 3332 void 3333 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3334 { 3335 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3336 uhci_soft_qh_t *eqh; 3337 3338 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3339 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3340 3341 eqh = vf->eqh; 3342 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3343 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 3344 sqh->hlink = eqh->hlink; 3345 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3346 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3347 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 3348 eqh->hlink = sqh; 3349 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3350 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3351 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 3352 vf->eqh = sqh; 3353 vf->bandwidth++; 3354 } 3355 3356 /* Remove interrupt QH. */ 3357 void 3358 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3359 { 3360 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3361 uhci_soft_qh_t *pqh; 3362 3363 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3364 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3365 3366 /* See comment in uhci_remove_ctrl() */ 3367 3368 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3369 sizeof(sqh->qh.qh_elink), 3370 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3371 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3372 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3373 usb_syncmem(&sqh->dma, 3374 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3375 sizeof(sqh->qh.qh_elink), 3376 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3377 delay(UHCI_QH_REMOVE_DELAY); 3378 } 3379 3380 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3381 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3382 sizeof(sqh->qh.qh_hlink), 3383 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3384 pqh->hlink = sqh->hlink; 3385 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3386 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3387 sizeof(pqh->qh.qh_hlink), 3388 BUS_DMASYNC_PREWRITE); 3389 delay(UHCI_QH_REMOVE_DELAY); 3390 if (vf->eqh == sqh) 3391 vf->eqh = pqh; 3392 vf->bandwidth--; 3393 } 3394 3395 usbd_status 3396 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3397 { 3398 uhci_soft_qh_t *sqh; 3399 int i, npoll; 3400 u_int bestbw, bw, bestoffs, offs; 3401 3402 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3403 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3404 if (ival == 0) { 3405 printf("%s: 0 interval\n", __func__); 3406 return USBD_INVAL; 3407 } 3408 3409 if (ival > UHCI_VFRAMELIST_COUNT) 3410 ival = UHCI_VFRAMELIST_COUNT; 3411 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3412 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3413 3414 upipe->intr.npoll = npoll; 3415 upipe->intr.qhs = 3416 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3417 3418 /* 3419 * Figure out which offset in the schedule that has most 3420 * bandwidth left over. 3421 */ 3422 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3423 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3424 for (bw = i = 0; i < npoll; i++) 3425 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3426 if (bw < bestbw) { 3427 bestbw = bw; 3428 bestoffs = offs; 3429 } 3430 } 3431 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3432 for (i = 0; i < npoll; i++) { 3433 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3434 sqh->elink = NULL; 3435 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3436 usb_syncmem(&sqh->dma, 3437 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3438 sizeof(sqh->qh.qh_elink), 3439 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3440 sqh->pos = MOD(i * ival + bestoffs); 3441 } 3442 #undef MOD 3443 3444 mutex_enter(&sc->sc_lock); 3445 /* Enter QHs into the controller data structures. */ 3446 for (i = 0; i < npoll; i++) 3447 uhci_add_intr(sc, upipe->intr.qhs[i]); 3448 mutex_exit(&sc->sc_lock); 3449 3450 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3451 3452 return USBD_NORMAL_COMPLETION; 3453 } 3454 3455 /* Open a new pipe. */ 3456 usbd_status 3457 uhci_open(struct usbd_pipe *pipe) 3458 { 3459 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3460 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3461 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3462 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3463 usbd_status err = USBD_NOMEM; 3464 int ival; 3465 3466 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3467 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3468 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3469 3470 if (sc->sc_dying) 3471 return USBD_IOERROR; 3472 3473 upipe->aborting = 0; 3474 /* toggle state needed for bulk endpoints */ 3475 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3476 3477 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3478 switch (ed->bEndpointAddress) { 3479 case USB_CONTROL_ENDPOINT: 3480 pipe->up_methods = &roothub_ctrl_methods; 3481 break; 3482 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3483 pipe->up_methods = &uhci_root_intr_methods; 3484 break; 3485 default: 3486 return USBD_INVAL; 3487 } 3488 } else { 3489 switch (ed->bmAttributes & UE_XFERTYPE) { 3490 case UE_CONTROL: 3491 pipe->up_methods = &uhci_device_ctrl_methods; 3492 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3493 if (upipe->ctrl.sqh == NULL) 3494 goto bad; 3495 upipe->ctrl.setup = uhci_alloc_std(sc); 3496 if (upipe->ctrl.setup == NULL) { 3497 uhci_free_sqh(sc, upipe->ctrl.sqh); 3498 goto bad; 3499 } 3500 upipe->ctrl.stat = uhci_alloc_std(sc); 3501 if (upipe->ctrl.stat == NULL) { 3502 uhci_free_sqh(sc, upipe->ctrl.sqh); 3503 uhci_free_std(sc, upipe->ctrl.setup); 3504 goto bad; 3505 } 3506 err = usb_allocmem(&sc->sc_bus, 3507 sizeof(usb_device_request_t), 3508 0, &upipe->ctrl.reqdma); 3509 if (err) { 3510 uhci_free_sqh(sc, upipe->ctrl.sqh); 3511 uhci_free_std(sc, upipe->ctrl.setup); 3512 uhci_free_std(sc, upipe->ctrl.stat); 3513 goto bad; 3514 } 3515 break; 3516 case UE_INTERRUPT: 3517 pipe->up_methods = &uhci_device_intr_methods; 3518 ival = pipe->up_interval; 3519 if (ival == USBD_DEFAULT_INTERVAL) 3520 ival = ed->bInterval; 3521 return uhci_device_setintr(sc, upipe, ival); 3522 case UE_ISOCHRONOUS: 3523 pipe->up_serialise = false; 3524 pipe->up_methods = &uhci_device_isoc_methods; 3525 return uhci_setup_isoc(pipe); 3526 case UE_BULK: 3527 pipe->up_methods = &uhci_device_bulk_methods; 3528 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3529 if (upipe->bulk.sqh == NULL) 3530 goto bad; 3531 break; 3532 } 3533 } 3534 return USBD_NORMAL_COMPLETION; 3535 3536 bad: 3537 return USBD_NOMEM; 3538 } 3539 3540 /* 3541 * Data structures and routines to emulate the root hub. 3542 */ 3543 /* 3544 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3545 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3546 * should not be used by the USB subsystem. As we cannot issue a 3547 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3548 * will be enabled as part of the reset. 3549 * 3550 * On the VT83C572, the port cannot be successfully enabled until the 3551 * outstanding "port enable change" and "connection status change" 3552 * events have been reset. 3553 */ 3554 Static usbd_status 3555 uhci_portreset(uhci_softc_t *sc, int index) 3556 { 3557 int lim, port, x; 3558 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3559 3560 if (index == 1) 3561 port = UHCI_PORTSC1; 3562 else if (index == 2) 3563 port = UHCI_PORTSC2; 3564 else 3565 return USBD_IOERROR; 3566 3567 x = URWMASK(UREAD2(sc, port)); 3568 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3569 3570 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3571 3572 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3573 UREAD2(sc, port), 0, 0); 3574 3575 x = URWMASK(UREAD2(sc, port)); 3576 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3577 3578 delay(100); 3579 3580 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3581 UREAD2(sc, port), 0, 0); 3582 3583 x = URWMASK(UREAD2(sc, port)); 3584 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3585 3586 for (lim = 10; --lim > 0;) { 3587 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3588 3589 x = UREAD2(sc, port); 3590 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3591 lim, x, 0); 3592 3593 if (!(x & UHCI_PORTSC_CCS)) { 3594 /* 3595 * No device is connected (or was disconnected 3596 * during reset). Consider the port reset. 3597 * The delay must be long enough to ensure on 3598 * the initial iteration that the device 3599 * connection will have been registered. 50ms 3600 * appears to be sufficient, but 20ms is not. 3601 */ 3602 DPRINTFN(3, "uhci port %d loop %u, device detached", 3603 index, lim, 0, 0); 3604 break; 3605 } 3606 3607 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3608 /* 3609 * Port enabled changed and/or connection 3610 * status changed were set. Reset either or 3611 * both raised flags (by writing a 1 to that 3612 * bit), and wait again for state to settle. 3613 */ 3614 UWRITE2(sc, port, URWMASK(x) | 3615 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3616 continue; 3617 } 3618 3619 if (x & UHCI_PORTSC_PE) 3620 /* Port is enabled */ 3621 break; 3622 3623 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3624 } 3625 3626 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3627 UREAD2(sc, port), 0, 0); 3628 3629 if (lim <= 0) { 3630 DPRINTF("uhci port %d reset timed out", index, 3631 0, 0, 0); 3632 return USBD_TIMEOUT; 3633 } 3634 3635 sc->sc_isreset = 1; 3636 return USBD_NORMAL_COMPLETION; 3637 } 3638 3639 Static int 3640 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3641 void *buf, int buflen) 3642 { 3643 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3644 int port, x; 3645 int status, change, totlen = 0; 3646 uint16_t len, value, index; 3647 usb_port_status_t ps; 3648 usbd_status err; 3649 3650 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3651 3652 if (sc->sc_dying) 3653 return -1; 3654 3655 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3656 req->bRequest, 0, 0); 3657 3658 len = UGETW(req->wLength); 3659 value = UGETW(req->wValue); 3660 index = UGETW(req->wIndex); 3661 3662 #define C(x,y) ((x) | ((y) << 8)) 3663 switch (C(req->bRequest, req->bmRequestType)) { 3664 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3665 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3666 if (len == 0) 3667 break; 3668 switch (value) { 3669 case C(0, UDESC_DEVICE): { 3670 usb_device_descriptor_t devd; 3671 3672 totlen = min(buflen, sizeof(devd)); 3673 memcpy(&devd, buf, totlen); 3674 USETW(devd.idVendor, sc->sc_id_vendor); 3675 memcpy(buf, &devd, totlen); 3676 break; 3677 } 3678 case C(1, UDESC_STRING): 3679 #define sd ((usb_string_descriptor_t *)buf) 3680 /* Vendor */ 3681 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3682 break; 3683 case C(2, UDESC_STRING): 3684 /* Product */ 3685 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3686 break; 3687 #undef sd 3688 default: 3689 /* default from usbroothub */ 3690 return buflen; 3691 } 3692 break; 3693 3694 /* Hub requests */ 3695 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3696 break; 3697 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3698 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3699 value, 0, 0); 3700 if (index == 1) 3701 port = UHCI_PORTSC1; 3702 else if (index == 2) 3703 port = UHCI_PORTSC2; 3704 else { 3705 return -1; 3706 } 3707 switch(value) { 3708 case UHF_PORT_ENABLE: 3709 x = URWMASK(UREAD2(sc, port)); 3710 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3711 break; 3712 case UHF_PORT_SUSPEND: 3713 x = URWMASK(UREAD2(sc, port)); 3714 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3715 break; 3716 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3717 /* see USB2 spec ch. 7.1.7.7 */ 3718 usb_delay_ms(&sc->sc_bus, 20); 3719 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3720 /* 10ms resume delay must be provided by caller */ 3721 break; 3722 case UHF_PORT_RESET: 3723 x = URWMASK(UREAD2(sc, port)); 3724 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3725 break; 3726 case UHF_C_PORT_CONNECTION: 3727 x = URWMASK(UREAD2(sc, port)); 3728 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3729 break; 3730 case UHF_C_PORT_ENABLE: 3731 x = URWMASK(UREAD2(sc, port)); 3732 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3733 break; 3734 case UHF_C_PORT_OVER_CURRENT: 3735 x = URWMASK(UREAD2(sc, port)); 3736 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3737 break; 3738 case UHF_C_PORT_RESET: 3739 sc->sc_isreset = 0; 3740 break; 3741 case UHF_PORT_CONNECTION: 3742 case UHF_PORT_OVER_CURRENT: 3743 case UHF_PORT_POWER: 3744 case UHF_PORT_LOW_SPEED: 3745 case UHF_C_PORT_SUSPEND: 3746 default: 3747 return -1; 3748 } 3749 break; 3750 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3751 if (index == 1) 3752 port = UHCI_PORTSC1; 3753 else if (index == 2) 3754 port = UHCI_PORTSC2; 3755 else { 3756 return -1; 3757 } 3758 if (len > 0) { 3759 *(uint8_t *)buf = 3760 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3761 totlen = 1; 3762 } 3763 break; 3764 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3765 if (len == 0) 3766 break; 3767 if ((value & 0xff) != 0) { 3768 return -1; 3769 } 3770 usb_hub_descriptor_t hubd; 3771 3772 totlen = min(buflen, sizeof(hubd)); 3773 memcpy(&hubd, buf, totlen); 3774 hubd.bNbrPorts = 2; 3775 memcpy(buf, &hubd, totlen); 3776 break; 3777 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3778 if (len != 4) { 3779 return -1; 3780 } 3781 memset(buf, 0, len); 3782 totlen = len; 3783 break; 3784 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3785 if (index == 1) 3786 port = UHCI_PORTSC1; 3787 else if (index == 2) 3788 port = UHCI_PORTSC2; 3789 else { 3790 return -1; 3791 } 3792 if (len != 4) { 3793 return -1; 3794 } 3795 x = UREAD2(sc, port); 3796 status = change = 0; 3797 if (x & UHCI_PORTSC_CCS) 3798 status |= UPS_CURRENT_CONNECT_STATUS; 3799 if (x & UHCI_PORTSC_CSC) 3800 change |= UPS_C_CONNECT_STATUS; 3801 if (x & UHCI_PORTSC_PE) 3802 status |= UPS_PORT_ENABLED; 3803 if (x & UHCI_PORTSC_POEDC) 3804 change |= UPS_C_PORT_ENABLED; 3805 if (x & UHCI_PORTSC_OCI) 3806 status |= UPS_OVERCURRENT_INDICATOR; 3807 if (x & UHCI_PORTSC_OCIC) 3808 change |= UPS_C_OVERCURRENT_INDICATOR; 3809 if (x & UHCI_PORTSC_SUSP) 3810 status |= UPS_SUSPEND; 3811 if (x & UHCI_PORTSC_LSDA) 3812 status |= UPS_LOW_SPEED; 3813 status |= UPS_PORT_POWER; 3814 if (sc->sc_isreset) 3815 change |= UPS_C_PORT_RESET; 3816 USETW(ps.wPortStatus, status); 3817 USETW(ps.wPortChange, change); 3818 totlen = min(len, sizeof(ps)); 3819 memcpy(buf, &ps, totlen); 3820 break; 3821 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3822 return -1; 3823 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3824 break; 3825 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3826 if (index == 1) 3827 port = UHCI_PORTSC1; 3828 else if (index == 2) 3829 port = UHCI_PORTSC2; 3830 else { 3831 return -1; 3832 } 3833 switch(value) { 3834 case UHF_PORT_ENABLE: 3835 x = URWMASK(UREAD2(sc, port)); 3836 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3837 break; 3838 case UHF_PORT_SUSPEND: 3839 x = URWMASK(UREAD2(sc, port)); 3840 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3841 break; 3842 case UHF_PORT_RESET: 3843 err = uhci_portreset(sc, index); 3844 if (err != USBD_NORMAL_COMPLETION) 3845 return -1; 3846 return 0; 3847 case UHF_PORT_POWER: 3848 /* Pretend we turned on power */ 3849 return 0; 3850 case UHF_C_PORT_CONNECTION: 3851 case UHF_C_PORT_ENABLE: 3852 case UHF_C_PORT_OVER_CURRENT: 3853 case UHF_PORT_CONNECTION: 3854 case UHF_PORT_OVER_CURRENT: 3855 case UHF_PORT_LOW_SPEED: 3856 case UHF_C_PORT_SUSPEND: 3857 case UHF_C_PORT_RESET: 3858 default: 3859 return -1; 3860 } 3861 break; 3862 default: 3863 /* default from usbroothub */ 3864 DPRINTF("returning %d (usbroothub default)", 3865 buflen, 0, 0, 0); 3866 return buflen; 3867 } 3868 3869 DPRINTF("returning %d", totlen, 0, 0, 0); 3870 3871 return totlen; 3872 } 3873 3874 /* Abort a root interrupt request. */ 3875 void 3876 uhci_root_intr_abort(struct usbd_xfer *xfer) 3877 { 3878 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3879 3880 KASSERT(mutex_owned(&sc->sc_lock)); 3881 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3882 3883 callout_stop(&sc->sc_poll_handle); 3884 sc->sc_intr_xfer = NULL; 3885 3886 xfer->ux_status = USBD_CANCELLED; 3887 #ifdef DIAGNOSTIC 3888 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3889 #endif 3890 usb_transfer_complete(xfer); 3891 } 3892 3893 usbd_status 3894 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3895 { 3896 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3897 usbd_status err; 3898 3899 /* Insert last in queue. */ 3900 mutex_enter(&sc->sc_lock); 3901 err = usb_insert_transfer(xfer); 3902 mutex_exit(&sc->sc_lock); 3903 if (err) 3904 return err; 3905 3906 /* 3907 * Pipe isn't running (otherwise err would be USBD_INPROG), 3908 * start first 3909 */ 3910 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3911 } 3912 3913 /* Start a transfer on the root interrupt pipe */ 3914 usbd_status 3915 uhci_root_intr_start(struct usbd_xfer *xfer) 3916 { 3917 struct usbd_pipe *pipe = xfer->ux_pipe; 3918 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3919 unsigned int ival; 3920 3921 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3922 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3923 xfer->ux_flags, 0); 3924 3925 if (sc->sc_dying) 3926 return USBD_IOERROR; 3927 3928 /* XXX temporary variable needed to avoid gcc3 warning */ 3929 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3930 sc->sc_ival = mstohz(ival); 3931 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3932 sc->sc_intr_xfer = xfer; 3933 return USBD_IN_PROGRESS; 3934 } 3935 3936 /* Close the root interrupt pipe. */ 3937 void 3938 uhci_root_intr_close(struct usbd_pipe *pipe) 3939 { 3940 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3941 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3942 3943 KASSERT(mutex_owned(&sc->sc_lock)); 3944 3945 callout_stop(&sc->sc_poll_handle); 3946 sc->sc_intr_xfer = NULL; 3947 } 3948
Indexes created Tue Sep 30 17:09:57 GMT 2025