uhci.c revision 1.271
1 /* $NetBSD: uhci.c,v 1.271 2016/05/06 13:03:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.271 2016/05/06 13:03:06 skrll Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/mutex.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/uhcireg.h> 71 #include <dev/usb/uhcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 76 /*#define UHCI_CTL_LOOP */ 77 78 #ifdef UHCI_DEBUG 79 uhci_softc_t *thesc; 80 int uhcinoloop = 0; 81 #endif 82 83 #ifdef USB_DEBUG 84 #ifndef UHCI_DEBUG 85 #define uhcidebug 0 86 #else 87 static int uhcidebug = 0; 88 89 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 90 { 91 int err; 92 const struct sysctlnode *rnode; 93 const struct sysctlnode *cnode; 94 95 err = sysctl_createv(clog, 0, NULL, &rnode, 96 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 97 SYSCTL_DESCR("uhci global controls"), 98 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 99 100 if (err) 101 goto fail; 102 103 /* control debugging printfs */ 104 err = sysctl_createv(clog, 0, &rnode, &cnode, 105 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 106 "debug", SYSCTL_DESCR("Enable debugging output"), 107 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 108 if (err) 109 goto fail; 110 111 return; 112 fail: 113 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 114 } 115 116 #endif /* UHCI_DEBUG */ 117 #endif /* USB_DEBUG */ 118 119 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 120 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 121 #define UHCIHIST_FUNC() USBHIST_FUNC() 122 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 123 124 /* 125 * The UHCI controller is little endian, so on big endian machines 126 * the data stored in memory needs to be swapped. 127 */ 128 129 struct uhci_pipe { 130 struct usbd_pipe pipe; 131 int nexttoggle; 132 133 u_char aborting; 134 struct usbd_xfer *abortstart, abortend; 135 136 /* Info needed for different pipe kinds. */ 137 union { 138 /* Control pipe */ 139 struct { 140 uhci_soft_qh_t *sqh; 141 usb_dma_t reqdma; 142 uhci_soft_td_t *setup; 143 uhci_soft_td_t *stat; 144 } ctrl; 145 /* Interrupt pipe */ 146 struct { 147 int npoll; 148 uhci_soft_qh_t **qhs; 149 } intr; 150 /* Bulk pipe */ 151 struct { 152 uhci_soft_qh_t *sqh; 153 } bulk; 154 /* Isochronous pipe */ 155 struct isoc { 156 uhci_soft_td_t **stds; 157 int next, inuse; 158 } isoc; 159 }; 160 }; 161 162 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 163 164 Static void uhci_globalreset(uhci_softc_t *); 165 Static usbd_status uhci_portreset(uhci_softc_t*, int); 166 Static void uhci_reset(uhci_softc_t *); 167 Static usbd_status uhci_run(uhci_softc_t *, int, int); 168 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 169 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 170 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 171 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 172 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 173 #if 0 174 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 175 uhci_intr_info_t *); 176 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 177 #endif 178 179 #if 0 180 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 181 uhci_soft_td_t *); 182 #endif 183 Static int uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 184 int, int, uhci_soft_td_t **); 185 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 186 187 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 188 int, int, int *, uhci_soft_td_t **); 189 190 Static void uhci_poll_hub(void *); 191 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 192 ux_completeq_t *); 193 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 194 195 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 196 197 Static void uhci_timeout(void *); 198 Static void uhci_timeout_task(void *); 199 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 200 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 201 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 202 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 203 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 204 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 205 Static void uhci_add_loop(uhci_softc_t *); 206 Static void uhci_rem_loop(uhci_softc_t *); 207 208 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 209 210 Static struct usbd_xfer * 211 uhci_allocx(struct usbd_bus *, unsigned int); 212 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 213 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 214 Static int uhci_roothub_ctrl(struct usbd_bus *, 215 usb_device_request_t *, void *, int); 216 217 Static int uhci_device_ctrl_init(struct usbd_xfer *); 218 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 219 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 220 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 221 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 222 Static void uhci_device_ctrl_close(struct usbd_pipe *); 223 Static void uhci_device_ctrl_done(struct usbd_xfer *); 224 225 Static int uhci_device_intr_init(struct usbd_xfer *); 226 Static void uhci_device_intr_fini(struct usbd_xfer *); 227 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 228 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 229 Static void uhci_device_intr_abort(struct usbd_xfer *); 230 Static void uhci_device_intr_close(struct usbd_pipe *); 231 Static void uhci_device_intr_done(struct usbd_xfer *); 232 233 Static int uhci_device_bulk_init(struct usbd_xfer *); 234 Static void uhci_device_bulk_fini(struct usbd_xfer *); 235 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 236 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 237 Static void uhci_device_bulk_abort(struct usbd_xfer *); 238 Static void uhci_device_bulk_close(struct usbd_pipe *); 239 Static void uhci_device_bulk_done(struct usbd_xfer *); 240 241 Static int uhci_device_isoc_init(struct usbd_xfer *); 242 Static void uhci_device_isoc_fini(struct usbd_xfer *); 243 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 244 Static void uhci_device_isoc_abort(struct usbd_xfer *); 245 Static void uhci_device_isoc_close(struct usbd_pipe *); 246 Static void uhci_device_isoc_done(struct usbd_xfer *); 247 248 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 249 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 250 Static void uhci_root_intr_abort(struct usbd_xfer *); 251 Static void uhci_root_intr_close(struct usbd_pipe *); 252 Static void uhci_root_intr_done(struct usbd_xfer *); 253 254 Static usbd_status uhci_open(struct usbd_pipe *); 255 Static void uhci_poll(struct usbd_bus *); 256 Static void uhci_softintr(void *); 257 258 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 259 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 260 Static usbd_status uhci_device_setintr(uhci_softc_t *, 261 struct uhci_pipe *, int); 262 263 Static void uhci_device_clear_toggle(struct usbd_pipe *); 264 Static void uhci_noop(struct usbd_pipe *); 265 266 static inline uhci_soft_qh_t * 267 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 268 269 #ifdef UHCI_DEBUG 270 Static void uhci_dump_all(uhci_softc_t *); 271 Static void uhci_dumpregs(uhci_softc_t *); 272 Static void uhci_dump_qhs(uhci_soft_qh_t *); 273 Static void uhci_dump_qh(uhci_soft_qh_t *); 274 Static void uhci_dump_tds(uhci_soft_td_t *); 275 Static void uhci_dump_td(uhci_soft_td_t *); 276 Static void uhci_dump_ii(struct uhci_xfer *); 277 void uhci_dump(void); 278 #endif 279 280 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 281 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 282 #define UWRITE1(sc, r, x) \ 283 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 284 } while (/*CONSTCOND*/0) 285 #define UWRITE2(sc, r, x) \ 286 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 287 } while (/*CONSTCOND*/0) 288 #define UWRITE4(sc, r, x) \ 289 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 290 } while (/*CONSTCOND*/0) 291 292 static __inline uint8_t 293 UREAD1(uhci_softc_t *sc, bus_size_t r) 294 { 295 296 UBARR(sc); 297 return bus_space_read_1(sc->iot, sc->ioh, r); 298 } 299 300 static __inline uint16_t 301 UREAD2(uhci_softc_t *sc, bus_size_t r) 302 { 303 304 UBARR(sc); 305 return bus_space_read_2(sc->iot, sc->ioh, r); 306 } 307 308 #ifdef UHCI_DEBUG 309 static __inline uint32_t 310 UREAD4(uhci_softc_t *sc, bus_size_t r) 311 { 312 313 UBARR(sc); 314 return bus_space_read_4(sc->iot, sc->ioh, r); 315 } 316 #endif 317 318 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 319 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 320 321 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 322 323 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 324 325 const struct usbd_bus_methods uhci_bus_methods = { 326 .ubm_open = uhci_open, 327 .ubm_softint = uhci_softintr, 328 .ubm_dopoll = uhci_poll, 329 .ubm_allocx = uhci_allocx, 330 .ubm_freex = uhci_freex, 331 .ubm_getlock = uhci_get_lock, 332 .ubm_rhctrl = uhci_roothub_ctrl, 333 }; 334 335 const struct usbd_pipe_methods uhci_root_intr_methods = { 336 .upm_transfer = uhci_root_intr_transfer, 337 .upm_start = uhci_root_intr_start, 338 .upm_abort = uhci_root_intr_abort, 339 .upm_close = uhci_root_intr_close, 340 .upm_cleartoggle = uhci_noop, 341 .upm_done = uhci_root_intr_done, 342 }; 343 344 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 345 .upm_init = uhci_device_ctrl_init, 346 .upm_fini = uhci_device_ctrl_fini, 347 .upm_transfer = uhci_device_ctrl_transfer, 348 .upm_start = uhci_device_ctrl_start, 349 .upm_abort = uhci_device_ctrl_abort, 350 .upm_close = uhci_device_ctrl_close, 351 .upm_cleartoggle = uhci_noop, 352 .upm_done = uhci_device_ctrl_done, 353 }; 354 355 const struct usbd_pipe_methods uhci_device_intr_methods = { 356 .upm_init = uhci_device_intr_init, 357 .upm_fini = uhci_device_intr_fini, 358 .upm_transfer = uhci_device_intr_transfer, 359 .upm_start = uhci_device_intr_start, 360 .upm_abort = uhci_device_intr_abort, 361 .upm_close = uhci_device_intr_close, 362 .upm_cleartoggle = uhci_device_clear_toggle, 363 .upm_done = uhci_device_intr_done, 364 }; 365 366 const struct usbd_pipe_methods uhci_device_bulk_methods = { 367 .upm_init = uhci_device_bulk_init, 368 .upm_fini = uhci_device_bulk_fini, 369 .upm_transfer = uhci_device_bulk_transfer, 370 .upm_start = uhci_device_bulk_start, 371 .upm_abort = uhci_device_bulk_abort, 372 .upm_close = uhci_device_bulk_close, 373 .upm_cleartoggle = uhci_device_clear_toggle, 374 .upm_done = uhci_device_bulk_done, 375 }; 376 377 const struct usbd_pipe_methods uhci_device_isoc_methods = { 378 .upm_init = uhci_device_isoc_init, 379 .upm_fini = uhci_device_isoc_fini, 380 .upm_transfer = uhci_device_isoc_transfer, 381 .upm_abort = uhci_device_isoc_abort, 382 .upm_close = uhci_device_isoc_close, 383 .upm_cleartoggle = uhci_noop, 384 .upm_done = uhci_device_isoc_done, 385 }; 386 387 static inline void 388 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 389 { 390 391 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 392 } 393 394 static inline void 395 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 396 { 397 398 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 399 } 400 401 static inline uhci_soft_qh_t * 402 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 403 { 404 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 405 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 406 407 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 408 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 409 usb_syncmem(&pqh->dma, 410 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 411 sizeof(pqh->qh.qh_hlink), 412 BUS_DMASYNC_POSTWRITE); 413 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 414 printf("%s: QH not found\n", __func__); 415 return NULL; 416 } 417 #endif 418 } 419 return pqh; 420 } 421 422 void 423 uhci_globalreset(uhci_softc_t *sc) 424 { 425 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 426 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 427 UHCICMD(sc, 0); /* do nothing */ 428 } 429 430 int 431 uhci_init(uhci_softc_t *sc) 432 { 433 usbd_status err; 434 int i, j; 435 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 436 uhci_soft_td_t *std; 437 438 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 439 440 #ifdef UHCI_DEBUG 441 thesc = sc; 442 443 if (uhcidebug >= 2) 444 uhci_dumpregs(sc); 445 #endif 446 447 sc->sc_suspend = PWR_RESUME; 448 449 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 450 uhci_globalreset(sc); /* reset the controller */ 451 uhci_reset(sc); 452 453 /* Allocate and initialize real frame array. */ 454 err = usb_allocmem(&sc->sc_bus, 455 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 456 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 457 if (err) 458 return err; 459 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 460 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 461 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 462 463 /* Initialise mutex early for uhci_alloc_* */ 464 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 465 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 466 467 /* 468 * Allocate a TD, inactive, that hangs from the last QH. 469 * This is to avoid a bug in the PIIX that makes it run berserk 470 * otherwise. 471 */ 472 std = uhci_alloc_std(sc); 473 if (std == NULL) 474 return ENOMEM; 475 std->link.std = NULL; 476 std->td.td_link = htole32(UHCI_PTR_T); 477 std->td.td_status = htole32(0); /* inactive */ 478 std->td.td_token = htole32(0); 479 std->td.td_buffer = htole32(0); 480 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 482 483 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 484 lsqh = uhci_alloc_sqh(sc); 485 if (lsqh == NULL) 486 goto fail1; 487 lsqh->hlink = NULL; 488 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 489 lsqh->elink = std; 490 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 491 sc->sc_last_qh = lsqh; 492 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 494 495 /* Allocate the dummy QH where bulk traffic will be queued. */ 496 bsqh = uhci_alloc_sqh(sc); 497 if (bsqh == NULL) 498 goto fail2; 499 bsqh->hlink = lsqh; 500 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 501 bsqh->elink = NULL; 502 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 503 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 504 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 506 507 /* Allocate dummy QH where high speed control traffic will be queued. */ 508 chsqh = uhci_alloc_sqh(sc); 509 if (chsqh == NULL) 510 goto fail3; 511 chsqh->hlink = bsqh; 512 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 513 chsqh->elink = NULL; 514 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 515 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 516 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 517 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 518 519 /* Allocate dummy QH where control traffic will be queued. */ 520 clsqh = uhci_alloc_sqh(sc); 521 if (clsqh == NULL) 522 goto fail4; 523 clsqh->hlink = chsqh; 524 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 525 clsqh->elink = NULL; 526 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 527 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 528 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 530 531 /* 532 * Make all (virtual) frame list pointers point to the interrupt 533 * queue heads and the interrupt queue heads at the control 534 * queue head and point the physical frame list to the virtual. 535 */ 536 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 537 std = uhci_alloc_std(sc); 538 sqh = uhci_alloc_sqh(sc); 539 if (std == NULL || sqh == NULL) 540 return USBD_NOMEM; 541 std->link.sqh = sqh; 542 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 543 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 544 std->td.td_token = htole32(0); 545 std->td.td_buffer = htole32(0); 546 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 548 sqh->hlink = clsqh; 549 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 550 sqh->elink = NULL; 551 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 552 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 553 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 554 sc->sc_vframes[i].htd = std; 555 sc->sc_vframes[i].etd = std; 556 sc->sc_vframes[i].hqh = sqh; 557 sc->sc_vframes[i].eqh = sqh; 558 for (j = i; 559 j < UHCI_FRAMELIST_COUNT; 560 j += UHCI_VFRAMELIST_COUNT) 561 sc->sc_pframes[j] = htole32(std->physaddr); 562 } 563 usb_syncmem(&sc->sc_dma, 0, 564 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 565 BUS_DMASYNC_PREWRITE); 566 567 568 TAILQ_INIT(&sc->sc_intrhead); 569 570 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 571 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 572 573 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 574 575 cv_init(&sc->sc_softwake_cv, "uhciab"); 576 577 /* Set up the bus struct. */ 578 sc->sc_bus.ub_methods = &uhci_bus_methods; 579 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 580 sc->sc_bus.ub_usedma = true; 581 582 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 583 584 DPRINTF("Enabling...", 0, 0, 0, 0); 585 586 err = uhci_run(sc, 1, 0); /* and here we go... */ 587 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 588 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 589 return err; 590 591 fail4: 592 uhci_free_sqh(sc, chsqh); 593 fail3: 594 uhci_free_sqh(sc, lsqh); 595 fail2: 596 uhci_free_sqh(sc, lsqh); 597 fail1: 598 uhci_free_std(sc, std); 599 600 return ENOMEM; 601 } 602 603 int 604 uhci_activate(device_t self, enum devact act) 605 { 606 struct uhci_softc *sc = device_private(self); 607 608 switch (act) { 609 case DVACT_DEACTIVATE: 610 sc->sc_dying = 1; 611 return 0; 612 default: 613 return EOPNOTSUPP; 614 } 615 } 616 617 void 618 uhci_childdet(device_t self, device_t child) 619 { 620 struct uhci_softc *sc = device_private(self); 621 622 KASSERT(sc->sc_child == child); 623 sc->sc_child = NULL; 624 } 625 626 int 627 uhci_detach(struct uhci_softc *sc, int flags) 628 { 629 int rv = 0; 630 631 if (sc->sc_child != NULL) 632 rv = config_detach(sc->sc_child, flags); 633 634 if (rv != 0) 635 return rv; 636 637 callout_halt(&sc->sc_poll_handle, NULL); 638 callout_destroy(&sc->sc_poll_handle); 639 640 cv_destroy(&sc->sc_softwake_cv); 641 642 mutex_destroy(&sc->sc_lock); 643 mutex_destroy(&sc->sc_intr_lock); 644 645 pool_cache_destroy(sc->sc_xferpool); 646 647 /* XXX free other data structures XXX */ 648 649 return rv; 650 } 651 652 struct usbd_xfer * 653 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 654 { 655 struct uhci_softc *sc = UHCI_BUS2SC(bus); 656 struct usbd_xfer *xfer; 657 658 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 659 if (xfer != NULL) { 660 memset(xfer, 0, sizeof(struct uhci_xfer)); 661 662 #ifdef DIAGNOSTIC 663 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 664 uxfer->ux_isdone = true; 665 xfer->ux_state = XFER_BUSY; 666 #endif 667 } 668 return xfer; 669 } 670 671 void 672 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 673 { 674 struct uhci_softc *sc = UHCI_BUS2SC(bus); 675 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 676 677 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 678 xfer->ux_state); 679 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 680 #ifdef DIAGNOSTIC 681 xfer->ux_state = XFER_FREE; 682 #endif 683 pool_cache_put(sc->sc_xferpool, xfer); 684 } 685 686 Static void 687 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 688 { 689 struct uhci_softc *sc = UHCI_BUS2SC(bus); 690 691 *lock = &sc->sc_lock; 692 } 693 694 695 /* 696 * Handle suspend/resume. 697 * 698 * We need to switch to polling mode here, because this routine is 699 * called from an interrupt context. This is all right since we 700 * are almost suspended anyway. 701 */ 702 bool 703 uhci_resume(device_t dv, const pmf_qual_t *qual) 704 { 705 uhci_softc_t *sc = device_private(dv); 706 int cmd; 707 708 mutex_spin_enter(&sc->sc_intr_lock); 709 710 cmd = UREAD2(sc, UHCI_CMD); 711 sc->sc_bus.ub_usepolling++; 712 UWRITE2(sc, UHCI_INTR, 0); 713 uhci_globalreset(sc); 714 uhci_reset(sc); 715 if (cmd & UHCI_CMD_RS) 716 uhci_run(sc, 0, 1); 717 718 /* restore saved state */ 719 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 720 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 721 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 722 723 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 724 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 725 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 726 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 727 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 728 UHCICMD(sc, UHCI_CMD_MAXP); 729 uhci_run(sc, 1, 1); /* and start traffic again */ 730 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 731 sc->sc_bus.ub_usepolling--; 732 if (sc->sc_intr_xfer != NULL) 733 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 734 sc->sc_intr_xfer); 735 #ifdef UHCI_DEBUG 736 if (uhcidebug >= 2) 737 uhci_dumpregs(sc); 738 #endif 739 740 sc->sc_suspend = PWR_RESUME; 741 mutex_spin_exit(&sc->sc_intr_lock); 742 743 return true; 744 } 745 746 bool 747 uhci_suspend(device_t dv, const pmf_qual_t *qual) 748 { 749 uhci_softc_t *sc = device_private(dv); 750 int cmd; 751 752 mutex_spin_enter(&sc->sc_intr_lock); 753 754 cmd = UREAD2(sc, UHCI_CMD); 755 756 #ifdef UHCI_DEBUG 757 if (uhcidebug >= 2) 758 uhci_dumpregs(sc); 759 #endif 760 if (sc->sc_intr_xfer != NULL) 761 callout_stop(&sc->sc_poll_handle); 762 sc->sc_suspend = PWR_SUSPEND; 763 sc->sc_bus.ub_usepolling++; 764 765 uhci_run(sc, 0, 1); /* stop the controller */ 766 cmd &= ~UHCI_CMD_RS; 767 768 /* save some state if BIOS doesn't */ 769 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 770 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 771 772 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 773 774 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 775 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 776 sc->sc_bus.ub_usepolling--; 777 778 mutex_spin_exit(&sc->sc_intr_lock); 779 780 return true; 781 } 782 783 #ifdef UHCI_DEBUG 784 Static void 785 uhci_dumpregs(uhci_softc_t *sc) 786 { 787 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 788 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 789 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 790 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 791 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 792 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 793 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 794 } 795 796 void 797 uhci_dump_td(uhci_soft_td_t *p) 798 { 799 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 800 801 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 802 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 803 804 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 805 DPRINTF(" link=0x%08x status=0x%08x " 806 "token=0x%08x buffer=0x%08x", 807 le32toh(p->td.td_link), 808 le32toh(p->td.td_status), 809 le32toh(p->td.td_token), 810 le32toh(p->td.td_buffer)); 811 812 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 813 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 814 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 815 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 816 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 817 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 818 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 819 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 820 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 821 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 822 DPRINTF("ios =%d ls =%d spd =%d", 823 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 824 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 825 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 826 DPRINTF("errcnt =%d actlen =%d pid=%02x", 827 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 828 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 829 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 830 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 831 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 832 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 833 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 834 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 835 } 836 837 void 838 uhci_dump_qh(uhci_soft_qh_t *sqh) 839 { 840 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 841 842 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 844 845 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 846 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 847 le32toh(sqh->qh.qh_elink)); 848 849 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 850 } 851 852 853 #if 1 854 void 855 uhci_dump(void) 856 { 857 uhci_dump_all(thesc); 858 } 859 #endif 860 861 void 862 uhci_dump_all(uhci_softc_t *sc) 863 { 864 uhci_dumpregs(sc); 865 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 866 uhci_dump_qhs(sc->sc_lctl_start); 867 } 868 869 870 void 871 uhci_dump_qhs(uhci_soft_qh_t *sqh) 872 { 873 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 874 875 uhci_dump_qh(sqh); 876 877 /* 878 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 879 * Traverses sideways first, then down. 880 * 881 * QH1 882 * QH2 883 * No QH 884 * TD2.1 885 * TD2.2 886 * TD1.1 887 * etc. 888 * 889 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 890 */ 891 892 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 893 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 894 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 895 uhci_dump_qhs(sqh->hlink); 896 else 897 DPRINTF("No QH", 0, 0, 0, 0); 898 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 899 900 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 901 uhci_dump_tds(sqh->elink); 902 else 903 DPRINTF("No QH", 0, 0, 0, 0); 904 } 905 906 void 907 uhci_dump_tds(uhci_soft_td_t *std) 908 { 909 uhci_soft_td_t *td; 910 int stop; 911 912 for (td = std; td != NULL; td = td->link.std) { 913 uhci_dump_td(td); 914 915 /* 916 * Check whether the link pointer in this TD marks 917 * the link pointer as end of queue. This avoids 918 * printing the free list in case the queue/TD has 919 * already been moved there (seatbelt). 920 */ 921 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 922 sizeof(td->td.td_link), 923 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 924 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 925 le32toh(td->td.td_link) == 0); 926 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 927 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 928 if (stop) 929 break; 930 } 931 } 932 933 Static void 934 uhci_dump_ii(struct uhci_xfer *ux) 935 { 936 struct usbd_pipe *pipe; 937 usb_endpoint_descriptor_t *ed; 938 struct usbd_device *dev; 939 940 if (ux == NULL) { 941 printf("ux NULL\n"); 942 return; 943 } 944 pipe = ux->ux_xfer.ux_pipe; 945 if (pipe == NULL) { 946 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 947 return; 948 } 949 if (pipe->up_endpoint == NULL) { 950 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 951 ux, ux->ux_isdone, pipe); 952 return; 953 } 954 if (pipe->up_dev == NULL) { 955 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 956 ux, ux->ux_isdone, pipe); 957 return; 958 } 959 ed = pipe->up_endpoint->ue_edesc; 960 dev = pipe->up_dev; 961 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 962 ux, ux->ux_isdone, dev, 963 UGETW(dev->ud_ddesc.idVendor), 964 UGETW(dev->ud_ddesc.idProduct), 965 dev->ud_addr, pipe, 966 ed->bEndpointAddress, ed->bmAttributes); 967 } 968 969 void uhci_dump_iis(struct uhci_softc *sc); 970 void 971 uhci_dump_iis(struct uhci_softc *sc) 972 { 973 struct uhci_xfer *ux; 974 975 printf("interrupt list:\n"); 976 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 977 uhci_dump_ii(ux); 978 } 979 980 void iidump(void); 981 void iidump(void) { uhci_dump_iis(thesc); } 982 983 #endif 984 985 /* 986 * This routine is executed periodically and simulates interrupts 987 * from the root controller interrupt pipe for port status change. 988 */ 989 void 990 uhci_poll_hub(void *addr) 991 { 992 struct usbd_xfer *xfer = addr; 993 struct usbd_pipe *pipe = xfer->ux_pipe; 994 uhci_softc_t *sc; 995 u_char *p; 996 997 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 998 999 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1000 return; /* device has detached */ 1001 sc = UHCI_PIPE2SC(pipe); 1002 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1003 1004 p = xfer->ux_buf; 1005 p[0] = 0; 1006 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1007 p[0] |= 1<<1; 1008 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<2; 1010 if (p[0] == 0) 1011 /* No change, try again in a while */ 1012 return; 1013 1014 xfer->ux_actlen = 1; 1015 xfer->ux_status = USBD_NORMAL_COMPLETION; 1016 mutex_enter(&sc->sc_lock); 1017 usb_transfer_complete(xfer); 1018 mutex_exit(&sc->sc_lock); 1019 } 1020 1021 void 1022 uhci_root_intr_done(struct usbd_xfer *xfer) 1023 { 1024 } 1025 1026 /* 1027 * Let the last QH loop back to the high speed control transfer QH. 1028 * This is what intel calls "bandwidth reclamation" and improves 1029 * USB performance a lot for some devices. 1030 * If we are already looping, just count it. 1031 */ 1032 void 1033 uhci_add_loop(uhci_softc_t *sc) 1034 { 1035 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1036 1037 #ifdef UHCI_DEBUG 1038 if (uhcinoloop) 1039 return; 1040 #endif 1041 if (++sc->sc_loops == 1) { 1042 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1043 /* Note, we don't loop back the soft pointer. */ 1044 sc->sc_last_qh->qh.qh_hlink = 1045 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1046 usb_syncmem(&sc->sc_last_qh->dma, 1047 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1048 sizeof(sc->sc_last_qh->qh.qh_hlink), 1049 BUS_DMASYNC_PREWRITE); 1050 } 1051 } 1052 1053 void 1054 uhci_rem_loop(uhci_softc_t *sc) 1055 { 1056 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1057 1058 #ifdef UHCI_DEBUG 1059 if (uhcinoloop) 1060 return; 1061 #endif 1062 if (--sc->sc_loops == 0) { 1063 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1064 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1065 usb_syncmem(&sc->sc_last_qh->dma, 1066 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1067 sizeof(sc->sc_last_qh->qh.qh_hlink), 1068 BUS_DMASYNC_PREWRITE); 1069 } 1070 } 1071 1072 /* Add high speed control QH, called with lock held. */ 1073 void 1074 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1075 { 1076 uhci_soft_qh_t *eqh; 1077 1078 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1079 1080 KASSERT(mutex_owned(&sc->sc_lock)); 1081 1082 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1083 eqh = sc->sc_hctl_end; 1084 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1085 sizeof(eqh->qh.qh_hlink), 1086 BUS_DMASYNC_POSTWRITE); 1087 sqh->hlink = eqh->hlink; 1088 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1089 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1090 BUS_DMASYNC_PREWRITE); 1091 eqh->hlink = sqh; 1092 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1093 sc->sc_hctl_end = sqh; 1094 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1095 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1096 #ifdef UHCI_CTL_LOOP 1097 uhci_add_loop(sc); 1098 #endif 1099 } 1100 1101 /* Remove high speed control QH, called with lock held. */ 1102 void 1103 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1104 { 1105 uhci_soft_qh_t *pqh; 1106 uint32_t elink; 1107 1108 KASSERT(mutex_owned(&sc->sc_lock)); 1109 1110 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1111 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1112 #ifdef UHCI_CTL_LOOP 1113 uhci_rem_loop(sc); 1114 #endif 1115 /* 1116 * The T bit should be set in the elink of the QH so that the HC 1117 * doesn't follow the pointer. This condition may fail if the 1118 * the transferred packet was short so that the QH still points 1119 * at the last used TD. 1120 * In this case we set the T bit and wait a little for the HC 1121 * to stop looking at the TD. 1122 * Note that if the TD chain is large enough, the controller 1123 * may still be looking at the chain at the end of this function. 1124 * uhci_free_std_chain() will make sure the controller stops 1125 * looking at it quickly, but until then we should not change 1126 * sqh->hlink. 1127 */ 1128 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1129 sizeof(sqh->qh.qh_elink), 1130 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1131 elink = le32toh(sqh->qh.qh_elink); 1132 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1133 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1134 if (!(elink & UHCI_PTR_T)) { 1135 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1136 usb_syncmem(&sqh->dma, 1137 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1138 sizeof(sqh->qh.qh_elink), 1139 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1140 delay(UHCI_QH_REMOVE_DELAY); 1141 } 1142 1143 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1144 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1145 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1146 pqh->hlink = sqh->hlink; 1147 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1148 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1149 sizeof(pqh->qh.qh_hlink), 1150 BUS_DMASYNC_PREWRITE); 1151 delay(UHCI_QH_REMOVE_DELAY); 1152 if (sc->sc_hctl_end == sqh) 1153 sc->sc_hctl_end = pqh; 1154 } 1155 1156 /* Add low speed control QH, called with lock held. */ 1157 void 1158 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1159 { 1160 uhci_soft_qh_t *eqh; 1161 1162 KASSERT(mutex_owned(&sc->sc_lock)); 1163 1164 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1165 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1166 1167 eqh = sc->sc_lctl_end; 1168 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1169 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1170 sqh->hlink = eqh->hlink; 1171 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1172 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1173 BUS_DMASYNC_PREWRITE); 1174 eqh->hlink = sqh; 1175 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1176 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1177 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1178 sc->sc_lctl_end = sqh; 1179 } 1180 1181 /* Remove low speed control QH, called with lock held. */ 1182 void 1183 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1184 { 1185 uhci_soft_qh_t *pqh; 1186 uint32_t elink; 1187 1188 KASSERT(mutex_owned(&sc->sc_lock)); 1189 1190 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1191 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1192 1193 /* See comment in uhci_remove_hs_ctrl() */ 1194 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1195 sizeof(sqh->qh.qh_elink), 1196 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1197 elink = le32toh(sqh->qh.qh_elink); 1198 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1199 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1200 if (!(elink & UHCI_PTR_T)) { 1201 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1202 usb_syncmem(&sqh->dma, 1203 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1204 sizeof(sqh->qh.qh_elink), 1205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1206 delay(UHCI_QH_REMOVE_DELAY); 1207 } 1208 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1209 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1210 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1211 pqh->hlink = sqh->hlink; 1212 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1213 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1214 sizeof(pqh->qh.qh_hlink), 1215 BUS_DMASYNC_PREWRITE); 1216 delay(UHCI_QH_REMOVE_DELAY); 1217 if (sc->sc_lctl_end == sqh) 1218 sc->sc_lctl_end = pqh; 1219 } 1220 1221 /* Add bulk QH, called with lock held. */ 1222 void 1223 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1224 { 1225 uhci_soft_qh_t *eqh; 1226 1227 KASSERT(mutex_owned(&sc->sc_lock)); 1228 1229 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1230 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1231 1232 eqh = sc->sc_bulk_end; 1233 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1234 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1235 sqh->hlink = eqh->hlink; 1236 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1237 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1238 BUS_DMASYNC_PREWRITE); 1239 eqh->hlink = sqh; 1240 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1241 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1242 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1243 sc->sc_bulk_end = sqh; 1244 uhci_add_loop(sc); 1245 } 1246 1247 /* Remove bulk QH, called with lock held. */ 1248 void 1249 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1250 { 1251 uhci_soft_qh_t *pqh; 1252 1253 KASSERT(mutex_owned(&sc->sc_lock)); 1254 1255 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1256 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1257 1258 uhci_rem_loop(sc); 1259 /* See comment in uhci_remove_hs_ctrl() */ 1260 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1261 sizeof(sqh->qh.qh_elink), 1262 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1263 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1264 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1265 usb_syncmem(&sqh->dma, 1266 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1267 sizeof(sqh->qh.qh_elink), 1268 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269 delay(UHCI_QH_REMOVE_DELAY); 1270 } 1271 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1272 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1273 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1274 pqh->hlink = sqh->hlink; 1275 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1276 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1277 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1278 delay(UHCI_QH_REMOVE_DELAY); 1279 if (sc->sc_bulk_end == sqh) 1280 sc->sc_bulk_end = pqh; 1281 } 1282 1283 Static int uhci_intr1(uhci_softc_t *); 1284 1285 int 1286 uhci_intr(void *arg) 1287 { 1288 uhci_softc_t *sc = arg; 1289 int ret = 0; 1290 1291 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1292 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 1295 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1296 goto done; 1297 1298 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1299 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1300 goto done; 1301 } 1302 1303 ret = uhci_intr1(sc); 1304 1305 done: 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 return ret; 1308 } 1309 1310 int 1311 uhci_intr1(uhci_softc_t *sc) 1312 { 1313 int status; 1314 int ack; 1315 1316 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1317 1318 #ifdef UHCI_DEBUG 1319 if (uhcidebug >= 15) { 1320 DPRINTF("sc %p", sc, 0, 0, 0); 1321 uhci_dumpregs(sc); 1322 } 1323 #endif 1324 1325 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1326 1327 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1328 /* Check if the interrupt was for us. */ 1329 if (status == 0) 1330 return 0; 1331 1332 if (sc->sc_suspend != PWR_RESUME) { 1333 #ifdef DIAGNOSTIC 1334 printf("%s: interrupt while not operating ignored\n", 1335 device_xname(sc->sc_dev)); 1336 #endif 1337 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1338 return 0; 1339 } 1340 1341 ack = 0; 1342 if (status & UHCI_STS_USBINT) 1343 ack |= UHCI_STS_USBINT; 1344 if (status & UHCI_STS_USBEI) 1345 ack |= UHCI_STS_USBEI; 1346 if (status & UHCI_STS_RD) { 1347 ack |= UHCI_STS_RD; 1348 #ifdef UHCI_DEBUG 1349 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1350 #endif 1351 } 1352 if (status & UHCI_STS_HSE) { 1353 ack |= UHCI_STS_HSE; 1354 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1355 } 1356 if (status & UHCI_STS_HCPE) { 1357 ack |= UHCI_STS_HCPE; 1358 printf("%s: host controller process error\n", 1359 device_xname(sc->sc_dev)); 1360 } 1361 1362 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1363 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1364 /* no acknowledge needed */ 1365 if (!sc->sc_dying) { 1366 printf("%s: host controller halted\n", 1367 device_xname(sc->sc_dev)); 1368 #ifdef UHCI_DEBUG 1369 uhci_dump_all(sc); 1370 #endif 1371 } 1372 sc->sc_dying = 1; 1373 } 1374 1375 if (!ack) 1376 return 0; /* nothing to acknowledge */ 1377 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1378 1379 usb_schedsoftintr(&sc->sc_bus); 1380 1381 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1382 1383 return 1; 1384 } 1385 1386 void 1387 uhci_softintr(void *v) 1388 { 1389 struct usbd_bus *bus = v; 1390 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1391 struct uhci_xfer *ux, *nextux; 1392 ux_completeq_t cq; 1393 1394 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1395 DPRINTF("sc %p", sc, 0, 0, 0); 1396 1397 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1398 1399 TAILQ_INIT(&cq); 1400 /* 1401 * Interrupts on UHCI really suck. When the host controller 1402 * interrupts because a transfer is completed there is no 1403 * way of knowing which transfer it was. You can scan down 1404 * the TDs and QHs of the previous frame to limit the search, 1405 * but that assumes that the interrupt was not delayed by more 1406 * than 1 ms, which may not always be true (e.g. after debug 1407 * output on a slow console). 1408 * We scan all interrupt descriptors to see if any have 1409 * completed. 1410 */ 1411 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1412 uhci_check_intr(sc, ux, &cq); 1413 } 1414 1415 /* 1416 * We abuse ux_list for the interrupt and complete lists and 1417 * interrupt transfers will get re-added here so use 1418 * the _SAFE version of TAILQ_FOREACH. 1419 */ 1420 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1421 DPRINTF("ux %p", ux, 0, 0, 0); 1422 usb_transfer_complete(&ux->ux_xfer); 1423 } 1424 1425 if (sc->sc_softwake) { 1426 sc->sc_softwake = 0; 1427 cv_broadcast(&sc->sc_softwake_cv); 1428 } 1429 } 1430 1431 /* Check for an interrupt. */ 1432 void 1433 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1434 { 1435 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1436 uint32_t status; 1437 1438 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1439 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1440 1441 KASSERT(ux != NULL); 1442 1443 struct usbd_xfer *xfer = &ux->ux_xfer; 1444 if (xfer->ux_status == USBD_CANCELLED || 1445 xfer->ux_status == USBD_TIMEOUT) { 1446 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1447 return; 1448 } 1449 1450 switch (ux->ux_type) { 1451 case UX_CTRL: 1452 fstd = ux->ux_setup; 1453 lstd = ux->ux_stat; 1454 break; 1455 case UX_BULK: 1456 case UX_INTR: 1457 case UX_ISOC: 1458 fstd = ux->ux_stdstart; 1459 lstd = ux->ux_stdend; 1460 break; 1461 default: 1462 KASSERT(false); 1463 break; 1464 } 1465 if (fstd == NULL) 1466 return; 1467 1468 KASSERT(lstd != NULL); 1469 1470 usb_syncmem(&lstd->dma, 1471 lstd->offs + offsetof(uhci_td_t, td_status), 1472 sizeof(lstd->td.td_status), 1473 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1474 status = le32toh(lstd->td.td_status); 1475 usb_syncmem(&lstd->dma, 1476 lstd->offs + offsetof(uhci_td_t, td_status), 1477 sizeof(lstd->td.td_status), 1478 BUS_DMASYNC_PREREAD); 1479 1480 /* If the last TD is not marked active we can complete */ 1481 if (!(status & UHCI_TD_ACTIVE)) { 1482 done: 1483 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1484 1485 callout_stop(&xfer->ux_callout); 1486 uhci_idone(ux, cqp); 1487 return; 1488 } 1489 1490 /* 1491 * If the last TD is still active we need to check whether there 1492 * is an error somewhere in the middle, or whether there was a 1493 * short packet (SPD and not ACTIVE). 1494 */ 1495 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1496 for (std = fstd; std != lstd; std = std->link.std) { 1497 usb_syncmem(&std->dma, 1498 std->offs + offsetof(uhci_td_t, td_status), 1499 sizeof(std->td.td_status), 1500 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1501 status = le32toh(std->td.td_status); 1502 usb_syncmem(&std->dma, 1503 std->offs + offsetof(uhci_td_t, td_status), 1504 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1505 1506 /* If there's an active TD the xfer isn't done. */ 1507 if (status & UHCI_TD_ACTIVE) { 1508 DPRINTFN(12, "ux=%p std=%p still active", 1509 ux, std, 0, 0); 1510 return; 1511 } 1512 1513 /* Any kind of error makes the xfer done. */ 1514 if (status & UHCI_TD_STALLED) 1515 goto done; 1516 1517 /* 1518 * If the data phase of a control transfer is short, we need 1519 * to complete the status stage 1520 */ 1521 1522 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1523 struct uhci_pipe *upipe = 1524 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1525 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1526 uhci_soft_td_t *stat = upipe->ctrl.stat; 1527 1528 DPRINTFN(12, "ux=%p std=%p control status" 1529 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1530 1531 sqh->qh.qh_elink = 1532 htole32(stat->physaddr | UHCI_PTR_TD); 1533 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1534 BUS_DMASYNC_PREWRITE); 1535 break; 1536 } 1537 1538 /* We want short packets, and it is short: it's done */ 1539 usb_syncmem(&std->dma, 1540 std->offs + offsetof(uhci_td_t, td_token), 1541 sizeof(std->td.td_token), 1542 BUS_DMASYNC_POSTWRITE); 1543 1544 if ((status & UHCI_TD_SPD) && 1545 UHCI_TD_GET_ACTLEN(status) < 1546 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1547 goto done; 1548 } 1549 } 1550 } 1551 1552 /* Called with USB lock held. */ 1553 void 1554 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1555 { 1556 struct usbd_xfer *xfer = &ux->ux_xfer; 1557 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1558 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1559 uhci_soft_td_t *std; 1560 uint32_t status = 0, nstatus; 1561 int actlen; 1562 1563 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1564 1565 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1566 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1567 1568 #ifdef DIAGNOSTIC 1569 #ifdef UHCI_DEBUG 1570 if (ux->ux_isdone) { 1571 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1572 uhci_dump_ii(ux); 1573 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1574 } 1575 #endif 1576 KASSERT(!ux->ux_isdone); 1577 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1578 ux->ux_type, xfer->ux_status); 1579 ux->ux_isdone = true; 1580 #endif 1581 1582 if (xfer->ux_nframes != 0) { 1583 /* Isoc transfer, do things differently. */ 1584 uhci_soft_td_t **stds = upipe->isoc.stds; 1585 int i, n, nframes, len; 1586 1587 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1588 1589 nframes = xfer->ux_nframes; 1590 actlen = 0; 1591 n = ux->ux_curframe; 1592 for (i = 0; i < nframes; i++) { 1593 std = stds[n]; 1594 #ifdef UHCI_DEBUG 1595 if (uhcidebug >= 5) { 1596 DPRINTF("isoc TD %d", i, 0, 0, 0); 1597 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1598 uhci_dump_td(std); 1599 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1600 } 1601 #endif 1602 if (++n >= UHCI_VFRAMELIST_COUNT) 1603 n = 0; 1604 usb_syncmem(&std->dma, 1605 std->offs + offsetof(uhci_td_t, td_status), 1606 sizeof(std->td.td_status), 1607 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1608 status = le32toh(std->td.td_status); 1609 len = UHCI_TD_GET_ACTLEN(status); 1610 xfer->ux_frlengths[i] = len; 1611 actlen += len; 1612 } 1613 upipe->isoc.inuse -= nframes; 1614 xfer->ux_actlen = actlen; 1615 xfer->ux_status = USBD_NORMAL_COMPLETION; 1616 goto end; 1617 } 1618 1619 #ifdef UHCI_DEBUG 1620 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1621 if (uhcidebug >= 10) { 1622 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1623 uhci_dump_tds(ux->ux_stdstart); 1624 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1625 } 1626 #endif 1627 1628 /* The transfer is done, compute actual length and status. */ 1629 actlen = 0; 1630 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1631 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1632 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1633 nstatus = le32toh(std->td.td_status); 1634 if (nstatus & UHCI_TD_ACTIVE) 1635 break; 1636 1637 status = nstatus; 1638 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1639 UHCI_TD_PID_SETUP) 1640 actlen += UHCI_TD_GET_ACTLEN(status); 1641 else { 1642 /* 1643 * UHCI will report CRCTO in addition to a STALL or NAK 1644 * for a SETUP transaction. See section 3.2.2, "TD 1645 * CONTROL AND STATUS". 1646 */ 1647 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1648 status &= ~UHCI_TD_CRCTO; 1649 } 1650 } 1651 /* If there are left over TDs we need to update the toggle. */ 1652 if (std != NULL) 1653 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1654 1655 status &= UHCI_TD_ERROR; 1656 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1657 xfer->ux_actlen = actlen; 1658 if (status != 0) { 1659 1660 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1661 "error, addr=%d, endpt=0x%02x", 1662 xfer->ux_pipe->up_dev->ud_addr, 1663 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1664 0, 0); 1665 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1666 "bitstuff=%d crcto =%d nak =%d babble =%d", 1667 !!(status & UHCI_TD_BITSTUFF), 1668 !!(status & UHCI_TD_CRCTO), 1669 !!(status & UHCI_TD_NAK), 1670 !!(status & UHCI_TD_BABBLE)); 1671 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1672 "dbuffer =%d stalled =%d active =%d", 1673 !!(status & UHCI_TD_DBUFFER), 1674 !!(status & UHCI_TD_STALLED), 1675 !!(status & UHCI_TD_ACTIVE), 1676 0); 1677 1678 if (status == UHCI_TD_STALLED) 1679 xfer->ux_status = USBD_STALLED; 1680 else 1681 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1682 } else { 1683 xfer->ux_status = USBD_NORMAL_COMPLETION; 1684 } 1685 1686 end: 1687 uhci_del_intr_list(sc, ux); 1688 if (cqp) 1689 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1690 1691 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1692 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1693 } 1694 1695 /* 1696 * Called when a request does not complete. 1697 */ 1698 void 1699 uhci_timeout(void *addr) 1700 { 1701 struct usbd_xfer *xfer = addr; 1702 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1703 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1704 1705 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1706 1707 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1708 1709 if (sc->sc_dying) { 1710 mutex_enter(&sc->sc_lock); 1711 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1712 mutex_exit(&sc->sc_lock); 1713 return; 1714 } 1715 1716 /* Execute the abort in a process context. */ 1717 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1718 USB_TASKQ_MPSAFE); 1719 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1720 USB_TASKQ_HC); 1721 } 1722 1723 void 1724 uhci_timeout_task(void *addr) 1725 { 1726 struct usbd_xfer *xfer = addr; 1727 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1728 1729 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1730 1731 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1732 1733 mutex_enter(&sc->sc_lock); 1734 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1735 mutex_exit(&sc->sc_lock); 1736 } 1737 1738 void 1739 uhci_poll(struct usbd_bus *bus) 1740 { 1741 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1742 1743 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1744 mutex_spin_enter(&sc->sc_intr_lock); 1745 uhci_intr1(sc); 1746 mutex_spin_exit(&sc->sc_intr_lock); 1747 } 1748 } 1749 1750 void 1751 uhci_reset(uhci_softc_t *sc) 1752 { 1753 int n; 1754 1755 UHCICMD(sc, UHCI_CMD_HCRESET); 1756 /* The reset bit goes low when the controller is done. */ 1757 for (n = 0; n < UHCI_RESET_TIMEOUT && 1758 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1759 usb_delay_ms(&sc->sc_bus, 1); 1760 if (n >= UHCI_RESET_TIMEOUT) 1761 printf("%s: controller did not reset\n", 1762 device_xname(sc->sc_dev)); 1763 } 1764 1765 usbd_status 1766 uhci_run(uhci_softc_t *sc, int run, int locked) 1767 { 1768 int n, running; 1769 uint16_t cmd; 1770 1771 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1772 1773 run = run != 0; 1774 if (!locked) 1775 mutex_spin_enter(&sc->sc_intr_lock); 1776 1777 DPRINTF("setting run=%d", run, 0, 0, 0); 1778 cmd = UREAD2(sc, UHCI_CMD); 1779 if (run) 1780 cmd |= UHCI_CMD_RS; 1781 else 1782 cmd &= ~UHCI_CMD_RS; 1783 UHCICMD(sc, cmd); 1784 for (n = 0; n < 10; n++) { 1785 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1786 /* return when we've entered the state we want */ 1787 if (run == running) { 1788 if (!locked) 1789 mutex_spin_exit(&sc->sc_intr_lock); 1790 DPRINTF("done cmd=0x%x sts=0x%x", 1791 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1792 return USBD_NORMAL_COMPLETION; 1793 } 1794 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1795 } 1796 if (!locked) 1797 mutex_spin_exit(&sc->sc_intr_lock); 1798 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1799 run ? "start" : "stop"); 1800 return USBD_IOERROR; 1801 } 1802 1803 /* 1804 * Memory management routines. 1805 * uhci_alloc_std allocates TDs 1806 * uhci_alloc_sqh allocates QHs 1807 * These two routines do their own free list management, 1808 * partly for speed, partly because allocating DMAable memory 1809 * has page size granularity so much memory would be wasted if 1810 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1811 */ 1812 1813 uhci_soft_td_t * 1814 uhci_alloc_std(uhci_softc_t *sc) 1815 { 1816 uhci_soft_td_t *std; 1817 usbd_status err; 1818 int i, offs; 1819 usb_dma_t dma; 1820 1821 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1822 1823 mutex_enter(&sc->sc_lock); 1824 if (sc->sc_freetds == NULL) { 1825 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1826 mutex_exit(&sc->sc_lock); 1827 1828 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1829 UHCI_TD_ALIGN, &dma); 1830 if (err) 1831 return NULL; 1832 1833 mutex_enter(&sc->sc_lock); 1834 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1835 offs = i * UHCI_STD_SIZE; 1836 std = KERNADDR(&dma, offs); 1837 std->physaddr = DMAADDR(&dma, offs); 1838 std->dma = dma; 1839 std->offs = offs; 1840 std->link.std = sc->sc_freetds; 1841 sc->sc_freetds = std; 1842 } 1843 } 1844 std = sc->sc_freetds; 1845 sc->sc_freetds = std->link.std; 1846 mutex_exit(&sc->sc_lock); 1847 1848 memset(&std->td, 0, sizeof(uhci_td_t)); 1849 1850 return std; 1851 } 1852 1853 #define TD_IS_FREE 0x12345678 1854 1855 void 1856 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1857 { 1858 KASSERT(mutex_owned(&sc->sc_lock)); 1859 1860 #ifdef DIAGNOSTIC 1861 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1862 printf("%s: freeing free TD %p\n", __func__, std); 1863 return; 1864 } 1865 std->td.td_token = htole32(TD_IS_FREE); 1866 #endif 1867 1868 std->link.std = sc->sc_freetds; 1869 sc->sc_freetds = std; 1870 } 1871 1872 void 1873 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1874 { 1875 mutex_enter(&sc->sc_lock); 1876 uhci_free_std_locked(sc, std); 1877 mutex_exit(&sc->sc_lock); 1878 } 1879 1880 uhci_soft_qh_t * 1881 uhci_alloc_sqh(uhci_softc_t *sc) 1882 { 1883 uhci_soft_qh_t *sqh; 1884 usbd_status err; 1885 int i, offs; 1886 usb_dma_t dma; 1887 1888 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1889 1890 mutex_enter(&sc->sc_lock); 1891 if (sc->sc_freeqhs == NULL) { 1892 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1893 mutex_exit(&sc->sc_lock); 1894 1895 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1896 UHCI_QH_ALIGN, &dma); 1897 if (err) 1898 return NULL; 1899 1900 mutex_enter(&sc->sc_lock); 1901 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1902 offs = i * UHCI_SQH_SIZE; 1903 sqh = KERNADDR(&dma, offs); 1904 sqh->physaddr = DMAADDR(&dma, offs); 1905 sqh->dma = dma; 1906 sqh->offs = offs; 1907 sqh->hlink = sc->sc_freeqhs; 1908 sc->sc_freeqhs = sqh; 1909 } 1910 } 1911 sqh = sc->sc_freeqhs; 1912 sc->sc_freeqhs = sqh->hlink; 1913 mutex_exit(&sc->sc_lock); 1914 1915 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1916 1917 return sqh; 1918 } 1919 1920 void 1921 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1922 { 1923 KASSERT(mutex_owned(&sc->sc_lock)); 1924 1925 sqh->hlink = sc->sc_freeqhs; 1926 sc->sc_freeqhs = sqh; 1927 } 1928 1929 #if 0 1930 void 1931 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1932 uhci_soft_td_t *stdend) 1933 { 1934 uhci_soft_td_t *p; 1935 uint32_t td_link; 1936 1937 /* 1938 * to avoid race condition with the controller which may be looking 1939 * at this chain, we need to first invalidate all links, and 1940 * then wait for the controller to move to another queue 1941 */ 1942 for (p = std; p != stdend; p = p->link.std) { 1943 usb_syncmem(&p->dma, 1944 p->offs + offsetof(uhci_td_t, td_link), 1945 sizeof(p->td.td_link), 1946 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1947 td_link = le32toh(p->td.td_link); 1948 usb_syncmem(&p->dma, 1949 p->offs + offsetof(uhci_td_t, td_link), 1950 sizeof(p->td.td_link), 1951 BUS_DMASYNC_PREREAD); 1952 if ((td_link & UHCI_PTR_T) == 0) { 1953 p->td.td_link = htole32(UHCI_PTR_T); 1954 usb_syncmem(&p->dma, 1955 p->offs + offsetof(uhci_td_t, td_link), 1956 sizeof(p->td.td_link), 1957 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1958 } 1959 } 1960 delay(UHCI_QH_REMOVE_DELAY); 1961 1962 for (; std != stdend; std = p) { 1963 p = std->link.std; 1964 uhci_free_std(sc, std); 1965 } 1966 } 1967 #endif 1968 1969 int 1970 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len, 1971 int rd, uhci_soft_td_t **sp) 1972 { 1973 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1974 uint16_t flags = xfer->ux_flags; 1975 uhci_soft_td_t *p; 1976 1977 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1978 1979 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 1980 1981 ASSERT_SLEEPABLE(); 1982 KASSERT(sp); 1983 1984 int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 1985 if (maxp == 0) { 1986 printf("%s: maxp=0\n", __func__); 1987 return EINVAL; 1988 } 1989 size_t ntd = (len + maxp - 1) / maxp; 1990 if (!rd && (flags & USBD_FORCE_SHORT_XFER)) { 1991 ntd++; 1992 } 1993 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 1994 1995 uxfer->ux_stds = NULL; 1996 uxfer->ux_nstd = ntd; 1997 p = NULL; 1998 if (ntd == 0) { 1999 *sp = NULL; 2000 DPRINTF("ntd=0", 0, 0, 0, 0); 2001 return 0; 2002 } 2003 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2004 KM_SLEEP); 2005 2006 ntd--; 2007 for (int i = ntd; i >= 0; i--) { 2008 p = uhci_alloc_std(sc); 2009 if (p == NULL) { 2010 uhci_free_stds(sc, uxfer); 2011 kmem_free(uxfer->ux_stds, 2012 sizeof(uhci_soft_td_t *) * ntd); 2013 return ENOMEM; 2014 } 2015 uxfer->ux_stds[i] = p; 2016 } 2017 2018 *sp = uxfer->ux_stds[0]; 2019 2020 return 0; 2021 } 2022 2023 Static void 2024 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2025 { 2026 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2027 2028 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2029 2030 mutex_enter(&sc->sc_lock); 2031 for (size_t i = 0; i < ux->ux_nstd; i++) { 2032 uhci_soft_td_t *std = ux->ux_stds[i]; 2033 #ifdef DIAGNOSTIC 2034 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2035 printf("%s: freeing free TD %p\n", __func__, std); 2036 return; 2037 } 2038 std->td.td_token = htole32(TD_IS_FREE); 2039 #endif 2040 ux->ux_stds[i]->link.std = sc->sc_freetds; 2041 sc->sc_freetds = std; 2042 } 2043 mutex_exit(&sc->sc_lock); 2044 } 2045 2046 2047 Static void 2048 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2049 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2050 { 2051 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2052 struct usbd_pipe *pipe = xfer->ux_pipe; 2053 usb_dma_t *dma = &xfer->ux_dmabuf; 2054 uint16_t flags = xfer->ux_flags; 2055 uhci_soft_td_t *std, *prev; 2056 int len = length; 2057 int tog = *toggle; 2058 int maxp; 2059 uint32_t status; 2060 size_t i; 2061 2062 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2063 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2064 len, isread, *toggle); 2065 2066 KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2067 2068 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2069 KASSERT(maxp != 0); 2070 2071 int addr = xfer->ux_pipe->up_dev->ud_addr; 2072 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2073 2074 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2075 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2076 status |= UHCI_TD_LS; 2077 if (flags & USBD_SHORT_XFER_OK) 2078 status |= UHCI_TD_SPD; 2079 usb_syncmem(dma, 0, len, 2080 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2081 std = prev = NULL; 2082 for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) { 2083 int l = len; 2084 std = uxfer->ux_stds[i]; 2085 if (l > maxp) 2086 l = maxp; 2087 2088 if (prev) { 2089 prev->link.std = std; 2090 prev->td.td_link = htole32( 2091 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2092 ); 2093 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2095 } 2096 2097 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2098 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2099 2100 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2101 std->td.td_status = htole32(status); 2102 std->td.td_token = htole32( 2103 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2104 UHCI_TD_SET_DEVADDR(addr) | 2105 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2106 UHCI_TD_SET_DT(tog) | 2107 UHCI_TD_SET_MAXLEN(l) 2108 ); 2109 std->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2110 2111 std->link.std = NULL; 2112 2113 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2114 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2115 tog ^= 1; 2116 2117 len -= l; 2118 } 2119 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2120 xfer, length, len, maxp, uxfer->ux_nstd, i); 2121 2122 if (!isread && 2123 (flags & USBD_FORCE_SHORT_XFER) && 2124 length % maxp == 0) { 2125 /* Force a 0 length transfer at the end. */ 2126 KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i, 2127 uxfer->ux_nstd); 2128 std = uxfer->ux_stds[i++]; 2129 2130 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2131 std->td.td_status = htole32(status); 2132 std->td.td_token = htole32( 2133 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2134 UHCI_TD_SET_DEVADDR(addr) | 2135 UHCI_TD_SET_PID(UHCI_TD_PID_OUT) | 2136 UHCI_TD_SET_DT(tog) | 2137 UHCI_TD_SET_MAXLEN(0) 2138 ); 2139 std->td.td_buffer = 0; 2140 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2142 2143 std->link.std = NULL; 2144 if (prev) { 2145 prev->link.std = std; 2146 prev->td.td_link = htole32( 2147 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2148 ); 2149 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2150 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2151 } 2152 tog ^= 1; 2153 } 2154 *lstd = std; 2155 *toggle = tog; 2156 } 2157 2158 void 2159 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2160 { 2161 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2162 upipe->nexttoggle = 0; 2163 } 2164 2165 void 2166 uhci_noop(struct usbd_pipe *pipe) 2167 { 2168 } 2169 2170 int 2171 uhci_device_bulk_init(struct usbd_xfer *xfer) 2172 { 2173 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2174 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2175 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2176 int endpt = ed->bEndpointAddress; 2177 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2178 int len = xfer->ux_bufsize; 2179 int err = 0; 2180 2181 2182 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2183 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2184 2185 if (sc->sc_dying) 2186 return USBD_IOERROR; 2187 2188 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2189 2190 uxfer->ux_type = UX_BULK; 2191 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart); 2192 if (err) 2193 return err; 2194 2195 #ifdef UHCI_DEBUG 2196 if (uhcidebug >= 10) { 2197 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2198 uhci_dump_tds(uxfer->ux_stdstart); 2199 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2200 } 2201 #endif 2202 2203 return 0; 2204 } 2205 2206 Static void 2207 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2208 { 2209 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2210 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2211 2212 KASSERT(ux->ux_type == UX_BULK); 2213 2214 uhci_free_stds(sc, ux); 2215 if (ux->ux_nstd) 2216 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2217 } 2218 2219 usbd_status 2220 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2221 { 2222 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2223 usbd_status err; 2224 2225 /* Insert last in queue. */ 2226 mutex_enter(&sc->sc_lock); 2227 err = usb_insert_transfer(xfer); 2228 mutex_exit(&sc->sc_lock); 2229 if (err) 2230 return err; 2231 2232 /* 2233 * Pipe isn't running (otherwise err would be USBD_INPROG), 2234 * so start it first. 2235 */ 2236 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2237 } 2238 2239 usbd_status 2240 uhci_device_bulk_start(struct usbd_xfer *xfer) 2241 { 2242 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2243 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2244 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2245 uhci_soft_td_t *data, *dataend; 2246 uhci_soft_qh_t *sqh; 2247 int len; 2248 int endpt; 2249 int isread; 2250 2251 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2252 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2253 xfer->ux_flags, 0); 2254 2255 if (sc->sc_dying) 2256 return USBD_IOERROR; 2257 2258 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2259 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2260 2261 len = xfer->ux_length; 2262 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2263 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2264 sqh = upipe->bulk.sqh; 2265 2266 /* Take lock here to protect nexttoggle */ 2267 mutex_enter(&sc->sc_lock); 2268 2269 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2270 &dataend); 2271 2272 data = ux->ux_stdstart; 2273 ux->ux_stdend = dataend; 2274 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2275 usb_syncmem(&dataend->dma, 2276 dataend->offs + offsetof(uhci_td_t, td_status), 2277 sizeof(dataend->td.td_status), 2278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2279 2280 #ifdef UHCI_DEBUG 2281 if (uhcidebug >= 10) { 2282 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2283 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2284 uhci_dump_tds(data); 2285 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2286 } 2287 #endif 2288 2289 KASSERT(ux->ux_isdone); 2290 #ifdef DIAGNOSTIC 2291 ux->ux_isdone = false; 2292 #endif 2293 2294 sqh->elink = data; 2295 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2296 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2297 2298 uhci_add_bulk(sc, sqh); 2299 uhci_add_intr_list(sc, ux); 2300 2301 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2302 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2303 uhci_timeout, xfer); 2304 } 2305 xfer->ux_status = USBD_IN_PROGRESS; 2306 mutex_exit(&sc->sc_lock); 2307 2308 return USBD_IN_PROGRESS; 2309 } 2310 2311 /* Abort a device bulk request. */ 2312 void 2313 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2314 { 2315 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2316 2317 KASSERT(mutex_owned(&sc->sc_lock)); 2318 2319 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2320 2321 uhci_abort_xfer(xfer, USBD_CANCELLED); 2322 } 2323 2324 /* 2325 * Abort a device request. 2326 * If this routine is called at splusb() it guarantees that the request 2327 * will be removed from the hardware scheduling and that the callback 2328 * for it will be called with USBD_CANCELLED status. 2329 * It's impossible to guarantee that the requested transfer will not 2330 * have happened since the hardware runs concurrently. 2331 * If the transaction has already happened we rely on the ordinary 2332 * interrupt processing to process it. 2333 * XXX This is most probably wrong. 2334 * XXXMRG this doesn't make sense anymore. 2335 */ 2336 void 2337 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2338 { 2339 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2340 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2341 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2342 uhci_soft_td_t *std; 2343 int wake; 2344 2345 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2346 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2347 2348 KASSERT(mutex_owned(&sc->sc_lock)); 2349 ASSERT_SLEEPABLE(); 2350 2351 if (sc->sc_dying) { 2352 /* If we're dying, just do the software part. */ 2353 xfer->ux_status = status; /* make software ignore it */ 2354 callout_stop(&xfer->ux_callout); 2355 usb_transfer_complete(xfer); 2356 return; 2357 } 2358 2359 /* 2360 * If an abort is already in progress then just wait for it to 2361 * complete and return. 2362 */ 2363 if (xfer->ux_hcflags & UXFER_ABORTING) { 2364 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2365 #ifdef DIAGNOSTIC 2366 if (status == USBD_TIMEOUT) 2367 printf("%s: TIMEOUT while aborting\n", __func__); 2368 #endif 2369 /* Override the status which might be USBD_TIMEOUT. */ 2370 xfer->ux_status = status; 2371 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2372 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2373 while (xfer->ux_hcflags & UXFER_ABORTING) 2374 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2375 goto done; 2376 } 2377 xfer->ux_hcflags |= UXFER_ABORTING; 2378 2379 /* 2380 * Step 1: Make interrupt routine and hardware ignore xfer. 2381 */ 2382 xfer->ux_status = status; /* make software ignore it */ 2383 callout_stop(&xfer->ux_callout); 2384 uhci_del_intr_list(sc, ux); 2385 2386 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2387 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2388 usb_syncmem(&std->dma, 2389 std->offs + offsetof(uhci_td_t, td_status), 2390 sizeof(std->td.td_status), 2391 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2392 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2393 usb_syncmem(&std->dma, 2394 std->offs + offsetof(uhci_td_t, td_status), 2395 sizeof(std->td.td_status), 2396 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2397 } 2398 2399 /* 2400 * Step 2: Wait until we know hardware has finished any possible 2401 * use of the xfer. Also make sure the soft interrupt routine 2402 * has run. 2403 */ 2404 /* Hardware finishes in 1ms */ 2405 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2406 sc->sc_softwake = 1; 2407 usb_schedsoftintr(&sc->sc_bus); 2408 DPRINTF("cv_wait", 0, 0, 0, 0); 2409 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2410 2411 /* 2412 * Step 3: Execute callback. 2413 */ 2414 DPRINTF("callback", 0, 0, 0, 0); 2415 #ifdef DIAGNOSTIC 2416 ux->ux_isdone = true; 2417 #endif 2418 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2419 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2420 usb_transfer_complete(xfer); 2421 if (wake) 2422 cv_broadcast(&xfer->ux_hccv); 2423 done: 2424 KASSERT(mutex_owned(&sc->sc_lock)); 2425 } 2426 2427 /* Close a device bulk pipe. */ 2428 void 2429 uhci_device_bulk_close(struct usbd_pipe *pipe) 2430 { 2431 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2432 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2433 2434 KASSERT(mutex_owned(&sc->sc_lock)); 2435 2436 uhci_free_sqh(sc, upipe->bulk.sqh); 2437 2438 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2439 } 2440 2441 int 2442 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2443 { 2444 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2445 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2446 usb_device_request_t *req = &xfer->ux_request; 2447 struct usbd_device *dev = upipe->pipe.up_dev; 2448 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2449 uhci_soft_td_t *data = NULL; 2450 int len; 2451 usbd_status err; 2452 int isread; 2453 2454 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2455 DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize, 2456 dev->ud_addr, upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2457 2458 isread = req->bmRequestType & UT_READ; 2459 len = xfer->ux_bufsize; 2460 2461 uxfer->ux_type = UX_CTRL; 2462 /* Set up data transaction */ 2463 if (len != 0) { 2464 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data); 2465 if (err) 2466 return err; 2467 } 2468 /* Set up interrupt info. */ 2469 uxfer->ux_setup = upipe->ctrl.setup; 2470 uxfer->ux_stat = upipe->ctrl.stat; 2471 uxfer->ux_data = data; 2472 2473 return 0; 2474 } 2475 2476 Static void 2477 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2478 { 2479 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2480 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2481 2482 KASSERT(ux->ux_type == UX_CTRL); 2483 2484 uhci_free_stds(sc, ux); 2485 if (ux->ux_nstd) 2486 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2487 } 2488 2489 usbd_status 2490 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2491 { 2492 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2493 usbd_status err; 2494 2495 /* Insert last in queue. */ 2496 mutex_enter(&sc->sc_lock); 2497 err = usb_insert_transfer(xfer); 2498 mutex_exit(&sc->sc_lock); 2499 if (err) 2500 return err; 2501 2502 /* 2503 * Pipe isn't running (otherwise err would be USBD_INPROG), 2504 * so start it first. 2505 */ 2506 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2507 } 2508 2509 usbd_status 2510 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2511 { 2512 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2513 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2514 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2515 usb_device_request_t *req = &xfer->ux_request; 2516 struct usbd_device *dev = upipe->pipe.up_dev; 2517 int addr = dev->ud_addr; 2518 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2519 uhci_soft_td_t *setup, *stat, *next, *dataend; 2520 uhci_soft_qh_t *sqh; 2521 int len; 2522 int isread; 2523 2524 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2525 2526 if (sc->sc_dying) 2527 return USBD_IOERROR; 2528 2529 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2530 2531 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2532 "wValue=0x%04x, wIndex=0x%04x", 2533 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2534 UGETW(req->wIndex)); 2535 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2536 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2537 2538 isread = req->bmRequestType & UT_READ; 2539 len = UGETW(req->wLength); 2540 2541 setup = upipe->ctrl.setup; 2542 stat = upipe->ctrl.stat; 2543 sqh = upipe->ctrl.sqh; 2544 2545 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2546 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2547 2548 mutex_enter(&sc->sc_lock); 2549 2550 /* Set up data transaction */ 2551 if (len != 0) { 2552 upipe->nexttoggle = 1; 2553 next = uxfer->ux_data; 2554 uhci_reset_std_chain(sc, xfer, len, isread, 2555 &upipe->nexttoggle, &dataend); 2556 dataend->link.std = stat; 2557 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2558 usb_syncmem(&dataend->dma, 2559 dataend->offs + offsetof(uhci_td_t, td_link), 2560 sizeof(dataend->td.td_link), 2561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2562 } else { 2563 next = stat; 2564 } 2565 2566 const uint32_t status = UHCI_TD_ZERO_ACTLEN( 2567 UHCI_TD_SET_ERRCNT(3) | 2568 UHCI_TD_ACTIVE | 2569 (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0) 2570 ); 2571 setup->link.std = next; 2572 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2573 setup->td.td_status = htole32(status); 2574 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2575 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2576 2577 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2579 2580 stat->link.std = NULL; 2581 stat->td.td_link = htole32(UHCI_PTR_T); 2582 stat->td.td_status = htole32(status | UHCI_TD_IOC); 2583 stat->td.td_token = 2584 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2585 UHCI_TD_IN (0, endpt, addr, 1)); 2586 stat->td.td_buffer = htole32(0); 2587 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2588 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2589 2590 #ifdef UHCI_DEBUG 2591 if (uhcidebug >= 10) { 2592 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2593 DPRINTF("before transfer", 0, 0, 0, 0); 2594 uhci_dump_tds(setup); 2595 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2596 } 2597 #endif 2598 2599 /* Set up interrupt info. */ 2600 uxfer->ux_setup = setup; 2601 uxfer->ux_stat = stat; 2602 KASSERT(uxfer->ux_isdone); 2603 #ifdef DIAGNOSTIC 2604 uxfer->ux_isdone = false; 2605 #endif 2606 2607 sqh->elink = setup; 2608 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2609 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2610 2611 if (dev->ud_speed == USB_SPEED_LOW) 2612 uhci_add_ls_ctrl(sc, sqh); 2613 else 2614 uhci_add_hs_ctrl(sc, sqh); 2615 uhci_add_intr_list(sc, uxfer); 2616 #ifdef UHCI_DEBUG 2617 if (uhcidebug >= 12) { 2618 uhci_soft_td_t *std; 2619 uhci_soft_qh_t *xqh; 2620 uhci_soft_qh_t *sxqh; 2621 int maxqh = 0; 2622 uhci_physaddr_t link; 2623 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2624 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2625 for (std = sc->sc_vframes[0].htd, link = 0; 2626 (link & UHCI_PTR_QH) == 0; 2627 std = std->link.std) { 2628 link = le32toh(std->td.td_link); 2629 uhci_dump_td(std); 2630 } 2631 sxqh = (uhci_soft_qh_t *)std; 2632 uhci_dump_qh(sxqh); 2633 for (xqh = sxqh; 2634 xqh != NULL; 2635 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2636 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2637 uhci_dump_qh(xqh); 2638 } 2639 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2640 uhci_dump_qh(sqh); 2641 uhci_dump_tds(sqh->elink); 2642 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2643 } 2644 #endif 2645 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2646 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2647 uhci_timeout, xfer); 2648 } 2649 xfer->ux_status = USBD_IN_PROGRESS; 2650 mutex_exit(&sc->sc_lock); 2651 2652 return USBD_IN_PROGRESS; 2653 } 2654 2655 int 2656 uhci_device_intr_init(struct usbd_xfer *xfer) 2657 { 2658 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2659 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2660 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2661 int endpt = ed->bEndpointAddress; 2662 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2663 int len = xfer->ux_bufsize; 2664 int err; 2665 2666 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2667 2668 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2669 xfer->ux_flags, 0); 2670 2671 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2672 KASSERT(len != 0); 2673 2674 ux->ux_type = UX_INTR; 2675 ux->ux_nstd = 0; 2676 err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart); 2677 2678 return err; 2679 } 2680 2681 Static void 2682 uhci_device_intr_fini(struct usbd_xfer *xfer) 2683 { 2684 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2685 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2686 2687 KASSERT(ux->ux_type == UX_INTR); 2688 2689 uhci_free_stds(sc, ux); 2690 if (ux->ux_nstd) 2691 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2692 } 2693 2694 usbd_status 2695 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2696 { 2697 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2698 usbd_status err; 2699 2700 /* Insert last in queue. */ 2701 mutex_enter(&sc->sc_lock); 2702 err = usb_insert_transfer(xfer); 2703 mutex_exit(&sc->sc_lock); 2704 if (err) 2705 return err; 2706 2707 /* 2708 * Pipe isn't running (otherwise err would be USBD_INPROG), 2709 * so start it first. 2710 */ 2711 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2712 } 2713 2714 usbd_status 2715 uhci_device_intr_start(struct usbd_xfer *xfer) 2716 { 2717 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2718 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2719 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2720 uhci_soft_td_t *data, *dataend; 2721 uhci_soft_qh_t *sqh; 2722 int isread, endpt; 2723 int i; 2724 2725 if (sc->sc_dying) 2726 return USBD_IOERROR; 2727 2728 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2729 2730 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2731 xfer->ux_flags, 0); 2732 2733 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2734 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2735 2736 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2737 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2738 2739 data = ux->ux_stdstart; 2740 2741 KASSERT(ux->ux_isdone); 2742 #ifdef DIAGNOSTIC 2743 ux->ux_isdone = false; 2744 #endif 2745 2746 /* Take lock to protect nexttoggle */ 2747 mutex_enter(&sc->sc_lock); 2748 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2749 &upipe->nexttoggle, &dataend); 2750 2751 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2752 usb_syncmem(&dataend->dma, 2753 dataend->offs + offsetof(uhci_td_t, td_status), 2754 sizeof(dataend->td.td_status), 2755 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2756 ux->ux_stdend = dataend; 2757 2758 #ifdef UHCI_DEBUG 2759 if (uhcidebug >= 10) { 2760 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2761 uhci_dump_tds(data); 2762 uhci_dump_qh(upipe->intr.qhs[0]); 2763 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2764 } 2765 #endif 2766 2767 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2768 for (i = 0; i < upipe->intr.npoll; i++) { 2769 sqh = upipe->intr.qhs[i]; 2770 sqh->elink = data; 2771 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2772 usb_syncmem(&sqh->dma, 2773 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2774 sizeof(sqh->qh.qh_elink), 2775 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2776 } 2777 uhci_add_intr_list(sc, ux); 2778 xfer->ux_status = USBD_IN_PROGRESS; 2779 mutex_exit(&sc->sc_lock); 2780 2781 #ifdef UHCI_DEBUG 2782 if (uhcidebug >= 10) { 2783 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2784 uhci_dump_tds(data); 2785 uhci_dump_qh(upipe->intr.qhs[0]); 2786 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2787 } 2788 #endif 2789 2790 return USBD_IN_PROGRESS; 2791 } 2792 2793 /* Abort a device control request. */ 2794 void 2795 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2796 { 2797 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2798 2799 KASSERT(mutex_owned(&sc->sc_lock)); 2800 2801 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2802 uhci_abort_xfer(xfer, USBD_CANCELLED); 2803 } 2804 2805 /* Close a device control pipe. */ 2806 void 2807 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2808 { 2809 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2810 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2811 2812 uhci_free_sqh(sc, upipe->ctrl.sqh); 2813 uhci_free_std_locked(sc, upipe->ctrl.setup); 2814 uhci_free_std_locked(sc, upipe->ctrl.stat); 2815 2816 } 2817 2818 /* Abort a device interrupt request. */ 2819 void 2820 uhci_device_intr_abort(struct usbd_xfer *xfer) 2821 { 2822 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2823 2824 KASSERT(mutex_owned(&sc->sc_lock)); 2825 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2826 2827 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2828 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2829 2830 uhci_abort_xfer(xfer, USBD_CANCELLED); 2831 } 2832 2833 /* Close a device interrupt pipe. */ 2834 void 2835 uhci_device_intr_close(struct usbd_pipe *pipe) 2836 { 2837 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2838 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2839 int i, npoll; 2840 2841 KASSERT(mutex_owned(&sc->sc_lock)); 2842 2843 /* Unlink descriptors from controller data structures. */ 2844 npoll = upipe->intr.npoll; 2845 for (i = 0; i < npoll; i++) 2846 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2847 2848 /* 2849 * We now have to wait for any activity on the physical 2850 * descriptors to stop. 2851 */ 2852 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2853 2854 for (i = 0; i < npoll; i++) 2855 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2856 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2857 } 2858 2859 int 2860 uhci_device_isoc_init(struct usbd_xfer *xfer) 2861 { 2862 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2863 2864 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2865 KASSERT(xfer->ux_nframes != 0); 2866 KASSERT(ux->ux_isdone); 2867 2868 ux->ux_type = UX_ISOC; 2869 return 0; 2870 } 2871 2872 Static void 2873 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2874 { 2875 struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer); 2876 2877 KASSERT(ux->ux_type == UX_ISOC); 2878 } 2879 2880 usbd_status 2881 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2882 { 2883 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2884 usbd_status err __diagused; 2885 2886 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2887 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2888 2889 /* Put it on our queue, */ 2890 mutex_enter(&sc->sc_lock); 2891 err = usb_insert_transfer(xfer); 2892 mutex_exit(&sc->sc_lock); 2893 2894 KASSERT(err == USBD_NORMAL_COMPLETION); 2895 2896 /* insert into schedule, */ 2897 2898 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2899 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2900 struct isoc *isoc = &upipe->isoc; 2901 uhci_soft_td_t *std = NULL; 2902 uint32_t buf, len, status, offs; 2903 int i, next, nframes; 2904 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2905 2906 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2907 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2908 2909 if (sc->sc_dying) 2910 return USBD_IOERROR; 2911 2912 if (xfer->ux_status == USBD_IN_PROGRESS) { 2913 /* This request has already been entered into the frame list */ 2914 printf("%s: xfer=%p in frame list\n", __func__, xfer); 2915 /* XXX */ 2916 } 2917 2918 #ifdef DIAGNOSTIC 2919 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2920 printf("%s: overflow!\n", __func__); 2921 #endif 2922 2923 KASSERT(xfer->ux_nframes != 0); 2924 2925 mutex_enter(&sc->sc_lock); 2926 next = isoc->next; 2927 if (next == -1) { 2928 /* Not in use yet, schedule it a few frames ahead. */ 2929 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2930 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2931 } 2932 2933 xfer->ux_status = USBD_IN_PROGRESS; 2934 ux->ux_curframe = next; 2935 2936 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2937 offs = 0; 2938 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2939 UHCI_TD_ACTIVE | 2940 UHCI_TD_IOS); 2941 nframes = xfer->ux_nframes; 2942 for (i = 0; i < nframes; i++) { 2943 std = isoc->stds[next]; 2944 if (++next >= UHCI_VFRAMELIST_COUNT) 2945 next = 0; 2946 len = xfer->ux_frlengths[i]; 2947 std->td.td_buffer = htole32(buf); 2948 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2949 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2950 if (i == nframes - 1) 2951 status |= UHCI_TD_IOC; 2952 std->td.td_status = htole32(status); 2953 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2954 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2955 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2956 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2957 #ifdef UHCI_DEBUG 2958 if (uhcidebug >= 5) { 2959 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2960 DPRINTF("TD %d", i, 0, 0, 0); 2961 uhci_dump_td(std); 2962 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2963 } 2964 #endif 2965 buf += len; 2966 offs += len; 2967 } 2968 isoc->next = next; 2969 isoc->inuse += xfer->ux_nframes; 2970 2971 /* Set up interrupt info. */ 2972 ux->ux_stdstart = std; 2973 ux->ux_stdend = std; 2974 2975 KASSERT(ux->ux_isdone); 2976 #ifdef DIAGNOSTIC 2977 ux->ux_isdone = false; 2978 #endif 2979 uhci_add_intr_list(sc, ux); 2980 2981 mutex_exit(&sc->sc_lock); 2982 2983 return USBD_IN_PROGRESS; 2984 } 2985 2986 void 2987 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2988 { 2989 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2990 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2991 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2992 uhci_soft_td_t **stds = upipe->isoc.stds; 2993 uhci_soft_td_t *std; 2994 int i, n, nframes, maxlen, len; 2995 2996 KASSERT(mutex_owned(&sc->sc_lock)); 2997 2998 /* Transfer is already done. */ 2999 if (xfer->ux_status != USBD_NOT_STARTED && 3000 xfer->ux_status != USBD_IN_PROGRESS) { 3001 return; 3002 } 3003 3004 /* Give xfer the requested abort code. */ 3005 xfer->ux_status = USBD_CANCELLED; 3006 3007 /* make hardware ignore it, */ 3008 nframes = xfer->ux_nframes; 3009 n = ux->ux_curframe; 3010 maxlen = 0; 3011 for (i = 0; i < nframes; i++) { 3012 std = stds[n]; 3013 usb_syncmem(&std->dma, 3014 std->offs + offsetof(uhci_td_t, td_status), 3015 sizeof(std->td.td_status), 3016 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3017 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3018 usb_syncmem(&std->dma, 3019 std->offs + offsetof(uhci_td_t, td_status), 3020 sizeof(std->td.td_status), 3021 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3022 usb_syncmem(&std->dma, 3023 std->offs + offsetof(uhci_td_t, td_token), 3024 sizeof(std->td.td_token), 3025 BUS_DMASYNC_POSTWRITE); 3026 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3027 if (len > maxlen) 3028 maxlen = len; 3029 if (++n >= UHCI_VFRAMELIST_COUNT) 3030 n = 0; 3031 } 3032 3033 /* and wait until we are sure the hardware has finished. */ 3034 delay(maxlen); 3035 3036 #ifdef DIAGNOSTIC 3037 ux->ux_isdone = true; 3038 #endif 3039 /* Remove from interrupt list. */ 3040 uhci_del_intr_list(sc, ux); 3041 3042 /* Run callback. */ 3043 usb_transfer_complete(xfer); 3044 3045 KASSERT(mutex_owned(&sc->sc_lock)); 3046 } 3047 3048 void 3049 uhci_device_isoc_close(struct usbd_pipe *pipe) 3050 { 3051 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3052 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3053 uhci_soft_td_t *std, *vstd; 3054 struct isoc *isoc; 3055 int i; 3056 3057 KASSERT(mutex_owned(&sc->sc_lock)); 3058 3059 /* 3060 * Make sure all TDs are marked as inactive. 3061 * Wait for completion. 3062 * Unschedule. 3063 * Deallocate. 3064 */ 3065 isoc = &upipe->isoc; 3066 3067 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3068 std = isoc->stds[i]; 3069 usb_syncmem(&std->dma, 3070 std->offs + offsetof(uhci_td_t, td_status), 3071 sizeof(std->td.td_status), 3072 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3073 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3074 usb_syncmem(&std->dma, 3075 std->offs + offsetof(uhci_td_t, td_status), 3076 sizeof(std->td.td_status), 3077 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3078 } 3079 /* wait for completion */ 3080 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3081 3082 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3083 std = isoc->stds[i]; 3084 for (vstd = sc->sc_vframes[i].htd; 3085 vstd != NULL && vstd->link.std != std; 3086 vstd = vstd->link.std) 3087 ; 3088 if (vstd == NULL) { 3089 /*panic*/ 3090 printf("%s: %p not found\n", __func__, std); 3091 mutex_exit(&sc->sc_lock); 3092 return; 3093 } 3094 vstd->link = std->link; 3095 usb_syncmem(&std->dma, 3096 std->offs + offsetof(uhci_td_t, td_link), 3097 sizeof(std->td.td_link), 3098 BUS_DMASYNC_POSTWRITE); 3099 vstd->td.td_link = std->td.td_link; 3100 usb_syncmem(&vstd->dma, 3101 vstd->offs + offsetof(uhci_td_t, td_link), 3102 sizeof(vstd->td.td_link), 3103 BUS_DMASYNC_PREWRITE); 3104 uhci_free_std_locked(sc, std); 3105 } 3106 3107 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3108 } 3109 3110 usbd_status 3111 uhci_setup_isoc(struct usbd_pipe *pipe) 3112 { 3113 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3114 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3115 int addr = upipe->pipe.up_dev->ud_addr; 3116 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3117 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3118 uhci_soft_td_t *std, *vstd; 3119 uint32_t token; 3120 struct isoc *isoc; 3121 int i; 3122 3123 isoc = &upipe->isoc; 3124 3125 isoc->stds = kmem_alloc( 3126 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3127 if (isoc->stds == NULL) 3128 return USBD_NOMEM; 3129 3130 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3131 UHCI_TD_OUT(0, endpt, addr, 0); 3132 3133 /* Allocate the TDs and mark as inactive; */ 3134 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3135 std = uhci_alloc_std(sc); 3136 if (std == 0) 3137 goto bad; 3138 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3139 std->td.td_token = htole32(token); 3140 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3142 isoc->stds[i] = std; 3143 } 3144 3145 mutex_enter(&sc->sc_lock); 3146 3147 /* Insert TDs into schedule. */ 3148 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3149 std = isoc->stds[i]; 3150 vstd = sc->sc_vframes[i].htd; 3151 usb_syncmem(&vstd->dma, 3152 vstd->offs + offsetof(uhci_td_t, td_link), 3153 sizeof(vstd->td.td_link), 3154 BUS_DMASYNC_POSTWRITE); 3155 std->link = vstd->link; 3156 std->td.td_link = vstd->td.td_link; 3157 usb_syncmem(&std->dma, 3158 std->offs + offsetof(uhci_td_t, td_link), 3159 sizeof(std->td.td_link), 3160 BUS_DMASYNC_PREWRITE); 3161 vstd->link.std = std; 3162 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3163 usb_syncmem(&vstd->dma, 3164 vstd->offs + offsetof(uhci_td_t, td_link), 3165 sizeof(vstd->td.td_link), 3166 BUS_DMASYNC_PREWRITE); 3167 } 3168 mutex_exit(&sc->sc_lock); 3169 3170 isoc->next = -1; 3171 isoc->inuse = 0; 3172 3173 return USBD_NORMAL_COMPLETION; 3174 3175 bad: 3176 while (--i >= 0) 3177 uhci_free_std(sc, isoc->stds[i]); 3178 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3179 return USBD_NOMEM; 3180 } 3181 3182 void 3183 uhci_device_isoc_done(struct usbd_xfer *xfer) 3184 { 3185 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3186 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3187 int i, offs; 3188 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3189 3190 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3191 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3192 xfer->ux_actlen, xfer->ux_state, 0, 0); 3193 3194 #ifdef DIAGNOSTIC 3195 if (ux->ux_stdend == NULL) { 3196 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3197 #ifdef UHCI_DEBUG 3198 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3199 uhci_dump_ii(ux); 3200 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3201 #endif 3202 return; 3203 } 3204 #endif 3205 3206 /* Turn off the interrupt since it is active even if the TD is not. */ 3207 usb_syncmem(&ux->ux_stdend->dma, 3208 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3209 sizeof(ux->ux_stdend->td.td_status), 3210 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3211 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3212 usb_syncmem(&ux->ux_stdend->dma, 3213 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3214 sizeof(ux->ux_stdend->td.td_status), 3215 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3216 3217 offs = 0; 3218 for (i = 0; i < xfer->ux_nframes; i++) { 3219 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3220 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3221 offs += xfer->ux_frlengths[i]; 3222 } 3223 } 3224 3225 void 3226 uhci_device_intr_done(struct usbd_xfer *xfer) 3227 { 3228 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 3229 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3230 uhci_soft_qh_t *sqh; 3231 int i, npoll; 3232 3233 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3234 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3235 3236 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3237 3238 npoll = upipe->intr.npoll; 3239 for (i = 0; i < npoll; i++) { 3240 sqh = upipe->intr.qhs[i]; 3241 sqh->elink = NULL; 3242 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3243 usb_syncmem(&sqh->dma, 3244 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3245 sizeof(sqh->qh.qh_elink), 3246 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3247 } 3248 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3249 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3250 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3251 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3252 } 3253 3254 /* Deallocate request data structures */ 3255 void 3256 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3257 { 3258 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3259 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3260 int len = UGETW(xfer->ux_request.wLength); 3261 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3262 3263 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3264 3265 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3266 3267 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3268 3269 /* XXXNH move to uhci_idone??? */ 3270 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3271 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3272 else 3273 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3274 3275 if (len) { 3276 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3277 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3278 } 3279 usb_syncmem(&upipe->ctrl.reqdma, 0, 3280 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3281 3282 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3283 } 3284 3285 /* Deallocate request data structures */ 3286 void 3287 uhci_device_bulk_done(struct usbd_xfer *xfer) 3288 { 3289 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3290 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3291 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3292 int endpt = ed->bEndpointAddress; 3293 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3294 3295 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3296 DPRINTFN(5, "xfer=%p sc=%p upipe=%p", xfer, sc, upipe, 0); 3297 3298 KASSERT(mutex_owned(&sc->sc_lock)); 3299 3300 uhci_remove_bulk(sc, upipe->bulk.sqh); 3301 3302 if (xfer->ux_length) { 3303 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3304 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3305 } 3306 3307 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3308 } 3309 3310 /* Add interrupt QH, called with vflock. */ 3311 void 3312 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3313 { 3314 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3315 uhci_soft_qh_t *eqh; 3316 3317 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3318 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3319 3320 eqh = vf->eqh; 3321 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3322 sizeof(eqh->qh.qh_hlink), 3323 BUS_DMASYNC_POSTWRITE); 3324 sqh->hlink = eqh->hlink; 3325 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3326 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3327 sizeof(sqh->qh.qh_hlink), 3328 BUS_DMASYNC_PREWRITE); 3329 eqh->hlink = sqh; 3330 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3331 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3332 sizeof(eqh->qh.qh_hlink), 3333 BUS_DMASYNC_PREWRITE); 3334 vf->eqh = sqh; 3335 vf->bandwidth++; 3336 } 3337 3338 /* Remove interrupt QH. */ 3339 void 3340 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3341 { 3342 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3343 uhci_soft_qh_t *pqh; 3344 3345 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3346 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3347 3348 /* See comment in uhci_remove_ctrl() */ 3349 3350 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3351 sizeof(sqh->qh.qh_elink), 3352 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3353 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3354 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3355 usb_syncmem(&sqh->dma, 3356 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3357 sizeof(sqh->qh.qh_elink), 3358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3359 delay(UHCI_QH_REMOVE_DELAY); 3360 } 3361 3362 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3363 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3364 sizeof(sqh->qh.qh_hlink), 3365 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3366 pqh->hlink = sqh->hlink; 3367 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3368 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3369 sizeof(pqh->qh.qh_hlink), 3370 BUS_DMASYNC_PREWRITE); 3371 delay(UHCI_QH_REMOVE_DELAY); 3372 if (vf->eqh == sqh) 3373 vf->eqh = pqh; 3374 vf->bandwidth--; 3375 } 3376 3377 usbd_status 3378 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3379 { 3380 uhci_soft_qh_t *sqh; 3381 int i, npoll; 3382 u_int bestbw, bw, bestoffs, offs; 3383 3384 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3385 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3386 if (ival == 0) { 3387 printf("%s: 0 interval\n", __func__); 3388 return USBD_INVAL; 3389 } 3390 3391 if (ival > UHCI_VFRAMELIST_COUNT) 3392 ival = UHCI_VFRAMELIST_COUNT; 3393 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3394 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3395 3396 upipe->intr.npoll = npoll; 3397 upipe->intr.qhs = 3398 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3399 if (upipe->intr.qhs == NULL) 3400 return USBD_NOMEM; 3401 3402 /* 3403 * Figure out which offset in the schedule that has most 3404 * bandwidth left over. 3405 */ 3406 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3407 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3408 for (bw = i = 0; i < npoll; i++) 3409 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3410 if (bw < bestbw) { 3411 bestbw = bw; 3412 bestoffs = offs; 3413 } 3414 } 3415 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3416 for (i = 0; i < npoll; i++) { 3417 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3418 sqh->elink = NULL; 3419 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3420 usb_syncmem(&sqh->dma, 3421 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3422 sizeof(sqh->qh.qh_elink), 3423 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3424 sqh->pos = MOD(i * ival + bestoffs); 3425 } 3426 #undef MOD 3427 3428 mutex_enter(&sc->sc_lock); 3429 /* Enter QHs into the controller data structures. */ 3430 for (i = 0; i < npoll; i++) 3431 uhci_add_intr(sc, upipe->intr.qhs[i]); 3432 mutex_exit(&sc->sc_lock); 3433 3434 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3435 3436 return USBD_NORMAL_COMPLETION; 3437 } 3438 3439 /* Open a new pipe. */ 3440 usbd_status 3441 uhci_open(struct usbd_pipe *pipe) 3442 { 3443 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3444 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3445 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3446 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3447 usbd_status err = USBD_NOMEM; 3448 int ival; 3449 3450 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3451 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3452 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3453 3454 if (sc->sc_dying) 3455 return USBD_IOERROR; 3456 3457 upipe->aborting = 0; 3458 /* toggle state needed for bulk endpoints */ 3459 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3460 3461 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3462 switch (ed->bEndpointAddress) { 3463 case USB_CONTROL_ENDPOINT: 3464 pipe->up_methods = &roothub_ctrl_methods; 3465 break; 3466 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3467 pipe->up_methods = &uhci_root_intr_methods; 3468 break; 3469 default: 3470 return USBD_INVAL; 3471 } 3472 } else { 3473 switch (ed->bmAttributes & UE_XFERTYPE) { 3474 case UE_CONTROL: 3475 pipe->up_methods = &uhci_device_ctrl_methods; 3476 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3477 if (upipe->ctrl.sqh == NULL) 3478 goto bad; 3479 upipe->ctrl.setup = uhci_alloc_std(sc); 3480 if (upipe->ctrl.setup == NULL) { 3481 uhci_free_sqh(sc, upipe->ctrl.sqh); 3482 goto bad; 3483 } 3484 upipe->ctrl.stat = uhci_alloc_std(sc); 3485 if (upipe->ctrl.stat == NULL) { 3486 uhci_free_sqh(sc, upipe->ctrl.sqh); 3487 uhci_free_std(sc, upipe->ctrl.setup); 3488 goto bad; 3489 } 3490 err = usb_allocmem(&sc->sc_bus, 3491 sizeof(usb_device_request_t), 3492 0, &upipe->ctrl.reqdma); 3493 if (err) { 3494 uhci_free_sqh(sc, upipe->ctrl.sqh); 3495 uhci_free_std(sc, upipe->ctrl.setup); 3496 uhci_free_std(sc, upipe->ctrl.stat); 3497 goto bad; 3498 } 3499 break; 3500 case UE_INTERRUPT: 3501 pipe->up_methods = &uhci_device_intr_methods; 3502 ival = pipe->up_interval; 3503 if (ival == USBD_DEFAULT_INTERVAL) 3504 ival = ed->bInterval; 3505 return uhci_device_setintr(sc, upipe, ival); 3506 case UE_ISOCHRONOUS: 3507 pipe->up_serialise = false; 3508 pipe->up_methods = &uhci_device_isoc_methods; 3509 return uhci_setup_isoc(pipe); 3510 case UE_BULK: 3511 pipe->up_methods = &uhci_device_bulk_methods; 3512 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3513 if (upipe->bulk.sqh == NULL) 3514 goto bad; 3515 break; 3516 } 3517 } 3518 return USBD_NORMAL_COMPLETION; 3519 3520 bad: 3521 return USBD_NOMEM; 3522 } 3523 3524 /* 3525 * Data structures and routines to emulate the root hub. 3526 */ 3527 /* 3528 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3529 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3530 * should not be used by the USB subsystem. As we cannot issue a 3531 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3532 * will be enabled as part of the reset. 3533 * 3534 * On the VT83C572, the port cannot be successfully enabled until the 3535 * outstanding "port enable change" and "connection status change" 3536 * events have been reset. 3537 */ 3538 Static usbd_status 3539 uhci_portreset(uhci_softc_t *sc, int index) 3540 { 3541 int lim, port, x; 3542 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3543 3544 if (index == 1) 3545 port = UHCI_PORTSC1; 3546 else if (index == 2) 3547 port = UHCI_PORTSC2; 3548 else 3549 return USBD_IOERROR; 3550 3551 x = URWMASK(UREAD2(sc, port)); 3552 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3553 3554 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3555 3556 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3557 UREAD2(sc, port), 0, 0); 3558 3559 x = URWMASK(UREAD2(sc, port)); 3560 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3561 3562 delay(100); 3563 3564 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3565 UREAD2(sc, port), 0, 0); 3566 3567 x = URWMASK(UREAD2(sc, port)); 3568 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3569 3570 for (lim = 10; --lim > 0;) { 3571 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3572 3573 x = UREAD2(sc, port); 3574 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3575 lim, x, 0); 3576 3577 if (!(x & UHCI_PORTSC_CCS)) { 3578 /* 3579 * No device is connected (or was disconnected 3580 * during reset). Consider the port reset. 3581 * The delay must be long enough to ensure on 3582 * the initial iteration that the device 3583 * connection will have been registered. 50ms 3584 * appears to be sufficient, but 20ms is not. 3585 */ 3586 DPRINTFN(3, "uhci port %d loop %u, device detached", 3587 index, lim, 0, 0); 3588 break; 3589 } 3590 3591 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3592 /* 3593 * Port enabled changed and/or connection 3594 * status changed were set. Reset either or 3595 * both raised flags (by writing a 1 to that 3596 * bit), and wait again for state to settle. 3597 */ 3598 UWRITE2(sc, port, URWMASK(x) | 3599 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3600 continue; 3601 } 3602 3603 if (x & UHCI_PORTSC_PE) 3604 /* Port is enabled */ 3605 break; 3606 3607 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3608 } 3609 3610 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3611 UREAD2(sc, port), 0, 0); 3612 3613 if (lim <= 0) { 3614 DPRINTF("uhci port %d reset timed out", index, 3615 0, 0, 0); 3616 return USBD_TIMEOUT; 3617 } 3618 3619 sc->sc_isreset = 1; 3620 return USBD_NORMAL_COMPLETION; 3621 } 3622 3623 Static int 3624 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3625 void *buf, int buflen) 3626 { 3627 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3628 int port, x; 3629 int status, change, totlen = 0; 3630 uint16_t len, value, index; 3631 usb_port_status_t ps; 3632 usbd_status err; 3633 3634 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3635 3636 if (sc->sc_dying) 3637 return -1; 3638 3639 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3640 req->bRequest, 0, 0); 3641 3642 len = UGETW(req->wLength); 3643 value = UGETW(req->wValue); 3644 index = UGETW(req->wIndex); 3645 3646 #define C(x,y) ((x) | ((y) << 8)) 3647 switch (C(req->bRequest, req->bmRequestType)) { 3648 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3649 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3650 if (len == 0) 3651 break; 3652 switch (value) { 3653 case C(0, UDESC_DEVICE): { 3654 usb_device_descriptor_t devd; 3655 3656 totlen = min(buflen, sizeof(devd)); 3657 memcpy(&devd, buf, totlen); 3658 USETW(devd.idVendor, sc->sc_id_vendor); 3659 memcpy(buf, &devd, totlen); 3660 break; 3661 } 3662 case C(1, UDESC_STRING): 3663 #define sd ((usb_string_descriptor_t *)buf) 3664 /* Vendor */ 3665 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3666 break; 3667 case C(2, UDESC_STRING): 3668 /* Product */ 3669 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3670 break; 3671 #undef sd 3672 default: 3673 /* default from usbroothub */ 3674 return buflen; 3675 } 3676 break; 3677 3678 /* Hub requests */ 3679 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3680 break; 3681 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3682 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3683 value, 0, 0); 3684 if (index == 1) 3685 port = UHCI_PORTSC1; 3686 else if (index == 2) 3687 port = UHCI_PORTSC2; 3688 else { 3689 return -1; 3690 } 3691 switch(value) { 3692 case UHF_PORT_ENABLE: 3693 x = URWMASK(UREAD2(sc, port)); 3694 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3695 break; 3696 case UHF_PORT_SUSPEND: 3697 x = URWMASK(UREAD2(sc, port)); 3698 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3699 break; 3700 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3701 /* see USB2 spec ch. 7.1.7.7 */ 3702 usb_delay_ms(&sc->sc_bus, 20); 3703 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3704 /* 10ms resume delay must be provided by caller */ 3705 break; 3706 case UHF_PORT_RESET: 3707 x = URWMASK(UREAD2(sc, port)); 3708 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3709 break; 3710 case UHF_C_PORT_CONNECTION: 3711 x = URWMASK(UREAD2(sc, port)); 3712 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3713 break; 3714 case UHF_C_PORT_ENABLE: 3715 x = URWMASK(UREAD2(sc, port)); 3716 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3717 break; 3718 case UHF_C_PORT_OVER_CURRENT: 3719 x = URWMASK(UREAD2(sc, port)); 3720 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3721 break; 3722 case UHF_C_PORT_RESET: 3723 sc->sc_isreset = 0; 3724 break; 3725 case UHF_PORT_CONNECTION: 3726 case UHF_PORT_OVER_CURRENT: 3727 case UHF_PORT_POWER: 3728 case UHF_PORT_LOW_SPEED: 3729 case UHF_C_PORT_SUSPEND: 3730 default: 3731 return -1; 3732 } 3733 break; 3734 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3735 if (index == 1) 3736 port = UHCI_PORTSC1; 3737 else if (index == 2) 3738 port = UHCI_PORTSC2; 3739 else { 3740 return -1; 3741 } 3742 if (len > 0) { 3743 *(uint8_t *)buf = 3744 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3745 totlen = 1; 3746 } 3747 break; 3748 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3749 if (len == 0) 3750 break; 3751 if ((value & 0xff) != 0) { 3752 return -1; 3753 } 3754 usb_hub_descriptor_t hubd; 3755 3756 totlen = min(buflen, sizeof(hubd)); 3757 memcpy(&hubd, buf, totlen); 3758 hubd.bNbrPorts = 2; 3759 memcpy(buf, &hubd, totlen); 3760 break; 3761 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3762 if (len != 4) { 3763 return -1; 3764 } 3765 memset(buf, 0, len); 3766 totlen = len; 3767 break; 3768 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3769 if (index == 1) 3770 port = UHCI_PORTSC1; 3771 else if (index == 2) 3772 port = UHCI_PORTSC2; 3773 else { 3774 return -1; 3775 } 3776 if (len != 4) { 3777 return -1; 3778 } 3779 x = UREAD2(sc, port); 3780 status = change = 0; 3781 if (x & UHCI_PORTSC_CCS) 3782 status |= UPS_CURRENT_CONNECT_STATUS; 3783 if (x & UHCI_PORTSC_CSC) 3784 change |= UPS_C_CONNECT_STATUS; 3785 if (x & UHCI_PORTSC_PE) 3786 status |= UPS_PORT_ENABLED; 3787 if (x & UHCI_PORTSC_POEDC) 3788 change |= UPS_C_PORT_ENABLED; 3789 if (x & UHCI_PORTSC_OCI) 3790 status |= UPS_OVERCURRENT_INDICATOR; 3791 if (x & UHCI_PORTSC_OCIC) 3792 change |= UPS_C_OVERCURRENT_INDICATOR; 3793 if (x & UHCI_PORTSC_SUSP) 3794 status |= UPS_SUSPEND; 3795 if (x & UHCI_PORTSC_LSDA) 3796 status |= UPS_LOW_SPEED; 3797 status |= UPS_PORT_POWER; 3798 if (sc->sc_isreset) 3799 change |= UPS_C_PORT_RESET; 3800 USETW(ps.wPortStatus, status); 3801 USETW(ps.wPortChange, change); 3802 totlen = min(len, sizeof(ps)); 3803 memcpy(buf, &ps, totlen); 3804 break; 3805 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3806 return -1; 3807 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3808 break; 3809 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3810 if (index == 1) 3811 port = UHCI_PORTSC1; 3812 else if (index == 2) 3813 port = UHCI_PORTSC2; 3814 else { 3815 return -1; 3816 } 3817 switch(value) { 3818 case UHF_PORT_ENABLE: 3819 x = URWMASK(UREAD2(sc, port)); 3820 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3821 break; 3822 case UHF_PORT_SUSPEND: 3823 x = URWMASK(UREAD2(sc, port)); 3824 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3825 break; 3826 case UHF_PORT_RESET: 3827 err = uhci_portreset(sc, index); 3828 if (err != USBD_NORMAL_COMPLETION) 3829 return -1; 3830 return 0; 3831 case UHF_PORT_POWER: 3832 /* Pretend we turned on power */ 3833 return 0; 3834 case UHF_C_PORT_CONNECTION: 3835 case UHF_C_PORT_ENABLE: 3836 case UHF_C_PORT_OVER_CURRENT: 3837 case UHF_PORT_CONNECTION: 3838 case UHF_PORT_OVER_CURRENT: 3839 case UHF_PORT_LOW_SPEED: 3840 case UHF_C_PORT_SUSPEND: 3841 case UHF_C_PORT_RESET: 3842 default: 3843 return -1; 3844 } 3845 break; 3846 default: 3847 /* default from usbroothub */ 3848 DPRINTF("returning %d (usbroothub default)", 3849 buflen, 0, 0, 0); 3850 return buflen; 3851 } 3852 3853 DPRINTF("returning %d", totlen, 0, 0, 0); 3854 3855 return totlen; 3856 } 3857 3858 /* Abort a root interrupt request. */ 3859 void 3860 uhci_root_intr_abort(struct usbd_xfer *xfer) 3861 { 3862 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3863 3864 KASSERT(mutex_owned(&sc->sc_lock)); 3865 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3866 3867 callout_stop(&sc->sc_poll_handle); 3868 sc->sc_intr_xfer = NULL; 3869 3870 xfer->ux_status = USBD_CANCELLED; 3871 #ifdef DIAGNOSTIC 3872 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3873 #endif 3874 usb_transfer_complete(xfer); 3875 } 3876 3877 usbd_status 3878 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3879 { 3880 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3881 usbd_status err; 3882 3883 /* Insert last in queue. */ 3884 mutex_enter(&sc->sc_lock); 3885 err = usb_insert_transfer(xfer); 3886 mutex_exit(&sc->sc_lock); 3887 if (err) 3888 return err; 3889 3890 /* 3891 * Pipe isn't running (otherwise err would be USBD_INPROG), 3892 * start first 3893 */ 3894 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3895 } 3896 3897 /* Start a transfer on the root interrupt pipe */ 3898 usbd_status 3899 uhci_root_intr_start(struct usbd_xfer *xfer) 3900 { 3901 struct usbd_pipe *pipe = xfer->ux_pipe; 3902 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3903 unsigned int ival; 3904 3905 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3906 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3907 xfer->ux_flags, 0); 3908 3909 if (sc->sc_dying) 3910 return USBD_IOERROR; 3911 3912 /* XXX temporary variable needed to avoid gcc3 warning */ 3913 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3914 sc->sc_ival = mstohz(ival); 3915 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3916 sc->sc_intr_xfer = xfer; 3917 return USBD_IN_PROGRESS; 3918 } 3919 3920 /* Close the root interrupt pipe. */ 3921 void 3922 uhci_root_intr_close(struct usbd_pipe *pipe) 3923 { 3924 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3925 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3926 3927 KASSERT(mutex_owned(&sc->sc_lock)); 3928 3929 callout_stop(&sc->sc_poll_handle); 3930 sc->sc_intr_xfer = NULL; 3931 } 3932
Indexes created Tue Sep 30 17:09:57 GMT 2025