uhci.c revision 1.275.2.1
1 /* $NetBSD: uhci.c,v 1.275.2.1 2017/07/25 01:39:41 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.275.2.1 2017/07/25 01:39:41 snj Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/device.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/mutex.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/select.h> 62 #include <sys/sysctl.h> 63 #include <sys/systm.h> 64 65 #include <machine/endian.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usb_mem.h> 71 72 #include <dev/usb/uhcireg.h> 73 #include <dev/usb/uhcivar.h> 74 #include <dev/usb/usbroothub.h> 75 #include <dev/usb/usbhist.h> 76 77 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 78 /*#define UHCI_CTL_LOOP */ 79 80 #ifdef UHCI_DEBUG 81 uhci_softc_t *thesc; 82 int uhcinoloop = 0; 83 #endif 84 85 #ifdef USB_DEBUG 86 #ifndef UHCI_DEBUG 87 #define uhcidebug 0 88 #else 89 static int uhcidebug = 0; 90 91 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 92 { 93 int err; 94 const struct sysctlnode *rnode; 95 const struct sysctlnode *cnode; 96 97 err = sysctl_createv(clog, 0, NULL, &rnode, 98 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 99 SYSCTL_DESCR("uhci global controls"), 100 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 101 102 if (err) 103 goto fail; 104 105 /* control debugging printfs */ 106 err = sysctl_createv(clog, 0, &rnode, &cnode, 107 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 108 "debug", SYSCTL_DESCR("Enable debugging output"), 109 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 110 if (err) 111 goto fail; 112 113 return; 114 fail: 115 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 116 } 117 118 #endif /* UHCI_DEBUG */ 119 #endif /* USB_DEBUG */ 120 121 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 122 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 123 #define UHCIHIST_FUNC() USBHIST_FUNC() 124 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 125 126 /* 127 * The UHCI controller is little endian, so on big endian machines 128 * the data stored in memory needs to be swapped. 129 */ 130 131 struct uhci_pipe { 132 struct usbd_pipe pipe; 133 int nexttoggle; 134 135 u_char aborting; 136 struct usbd_xfer *abortstart, abortend; 137 138 /* Info needed for different pipe kinds. */ 139 union { 140 /* Control pipe */ 141 struct { 142 uhci_soft_qh_t *sqh; 143 usb_dma_t reqdma; 144 uhci_soft_td_t *setup; 145 uhci_soft_td_t *stat; 146 } ctrl; 147 /* Interrupt pipe */ 148 struct { 149 int npoll; 150 uhci_soft_qh_t **qhs; 151 } intr; 152 /* Bulk pipe */ 153 struct { 154 uhci_soft_qh_t *sqh; 155 } bulk; 156 /* Isochronous pipe */ 157 struct isoc { 158 uhci_soft_td_t **stds; 159 int next, inuse; 160 } isoc; 161 }; 162 }; 163 164 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 165 166 Static void uhci_globalreset(uhci_softc_t *); 167 Static usbd_status uhci_portreset(uhci_softc_t*, int); 168 Static void uhci_reset(uhci_softc_t *); 169 Static usbd_status uhci_run(uhci_softc_t *, int, int); 170 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 171 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 172 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 173 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 174 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 175 #if 0 176 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 177 uhci_intr_info_t *); 178 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 179 #endif 180 181 #if 0 182 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 183 uhci_soft_td_t *); 184 #endif 185 Static int uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, uhci_soft_td_t **); 187 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 188 189 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 190 int, int, int *, uhci_soft_td_t **); 191 192 Static void uhci_poll_hub(void *); 193 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 194 ux_completeq_t *); 195 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 196 197 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 198 199 Static void uhci_timeout(void *); 200 Static void uhci_timeout_task(void *); 201 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 202 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 203 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 204 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 205 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 206 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 207 Static void uhci_add_loop(uhci_softc_t *); 208 Static void uhci_rem_loop(uhci_softc_t *); 209 210 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 211 212 Static struct usbd_xfer * 213 uhci_allocx(struct usbd_bus *, unsigned int); 214 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 215 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 216 Static int uhci_roothub_ctrl(struct usbd_bus *, 217 usb_device_request_t *, void *, int); 218 219 Static int uhci_device_ctrl_init(struct usbd_xfer *); 220 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 221 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 222 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 223 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 224 Static void uhci_device_ctrl_close(struct usbd_pipe *); 225 Static void uhci_device_ctrl_done(struct usbd_xfer *); 226 227 Static int uhci_device_intr_init(struct usbd_xfer *); 228 Static void uhci_device_intr_fini(struct usbd_xfer *); 229 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 230 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 231 Static void uhci_device_intr_abort(struct usbd_xfer *); 232 Static void uhci_device_intr_close(struct usbd_pipe *); 233 Static void uhci_device_intr_done(struct usbd_xfer *); 234 235 Static int uhci_device_bulk_init(struct usbd_xfer *); 236 Static void uhci_device_bulk_fini(struct usbd_xfer *); 237 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 238 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 239 Static void uhci_device_bulk_abort(struct usbd_xfer *); 240 Static void uhci_device_bulk_close(struct usbd_pipe *); 241 Static void uhci_device_bulk_done(struct usbd_xfer *); 242 243 Static int uhci_device_isoc_init(struct usbd_xfer *); 244 Static void uhci_device_isoc_fini(struct usbd_xfer *); 245 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 246 Static void uhci_device_isoc_abort(struct usbd_xfer *); 247 Static void uhci_device_isoc_close(struct usbd_pipe *); 248 Static void uhci_device_isoc_done(struct usbd_xfer *); 249 250 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 251 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 252 Static void uhci_root_intr_abort(struct usbd_xfer *); 253 Static void uhci_root_intr_close(struct usbd_pipe *); 254 Static void uhci_root_intr_done(struct usbd_xfer *); 255 256 Static usbd_status uhci_open(struct usbd_pipe *); 257 Static void uhci_poll(struct usbd_bus *); 258 Static void uhci_softintr(void *); 259 260 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 261 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 262 Static usbd_status uhci_device_setintr(uhci_softc_t *, 263 struct uhci_pipe *, int); 264 265 Static void uhci_device_clear_toggle(struct usbd_pipe *); 266 Static void uhci_noop(struct usbd_pipe *); 267 268 static inline uhci_soft_qh_t * 269 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 270 271 #ifdef UHCI_DEBUG 272 Static void uhci_dump_all(uhci_softc_t *); 273 Static void uhci_dumpregs(uhci_softc_t *); 274 Static void uhci_dump_qhs(uhci_soft_qh_t *); 275 Static void uhci_dump_qh(uhci_soft_qh_t *); 276 Static void uhci_dump_tds(uhci_soft_td_t *); 277 Static void uhci_dump_td(uhci_soft_td_t *); 278 Static void uhci_dump_ii(struct uhci_xfer *); 279 void uhci_dump(void); 280 #endif 281 282 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 283 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 284 #define UWRITE1(sc, r, x) \ 285 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 286 } while (/*CONSTCOND*/0) 287 #define UWRITE2(sc, r, x) \ 288 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 289 } while (/*CONSTCOND*/0) 290 #define UWRITE4(sc, r, x) \ 291 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 292 } while (/*CONSTCOND*/0) 293 294 static __inline uint8_t 295 UREAD1(uhci_softc_t *sc, bus_size_t r) 296 { 297 298 UBARR(sc); 299 return bus_space_read_1(sc->iot, sc->ioh, r); 300 } 301 302 static __inline uint16_t 303 UREAD2(uhci_softc_t *sc, bus_size_t r) 304 { 305 306 UBARR(sc); 307 return bus_space_read_2(sc->iot, sc->ioh, r); 308 } 309 310 #ifdef UHCI_DEBUG 311 static __inline uint32_t 312 UREAD4(uhci_softc_t *sc, bus_size_t r) 313 { 314 315 UBARR(sc); 316 return bus_space_read_4(sc->iot, sc->ioh, r); 317 } 318 #endif 319 320 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 321 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 322 323 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 324 325 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 326 327 const struct usbd_bus_methods uhci_bus_methods = { 328 .ubm_open = uhci_open, 329 .ubm_softint = uhci_softintr, 330 .ubm_dopoll = uhci_poll, 331 .ubm_allocx = uhci_allocx, 332 .ubm_freex = uhci_freex, 333 .ubm_getlock = uhci_get_lock, 334 .ubm_rhctrl = uhci_roothub_ctrl, 335 }; 336 337 const struct usbd_pipe_methods uhci_root_intr_methods = { 338 .upm_transfer = uhci_root_intr_transfer, 339 .upm_start = uhci_root_intr_start, 340 .upm_abort = uhci_root_intr_abort, 341 .upm_close = uhci_root_intr_close, 342 .upm_cleartoggle = uhci_noop, 343 .upm_done = uhci_root_intr_done, 344 }; 345 346 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 347 .upm_init = uhci_device_ctrl_init, 348 .upm_fini = uhci_device_ctrl_fini, 349 .upm_transfer = uhci_device_ctrl_transfer, 350 .upm_start = uhci_device_ctrl_start, 351 .upm_abort = uhci_device_ctrl_abort, 352 .upm_close = uhci_device_ctrl_close, 353 .upm_cleartoggle = uhci_noop, 354 .upm_done = uhci_device_ctrl_done, 355 }; 356 357 const struct usbd_pipe_methods uhci_device_intr_methods = { 358 .upm_init = uhci_device_intr_init, 359 .upm_fini = uhci_device_intr_fini, 360 .upm_transfer = uhci_device_intr_transfer, 361 .upm_start = uhci_device_intr_start, 362 .upm_abort = uhci_device_intr_abort, 363 .upm_close = uhci_device_intr_close, 364 .upm_cleartoggle = uhci_device_clear_toggle, 365 .upm_done = uhci_device_intr_done, 366 }; 367 368 const struct usbd_pipe_methods uhci_device_bulk_methods = { 369 .upm_init = uhci_device_bulk_init, 370 .upm_fini = uhci_device_bulk_fini, 371 .upm_transfer = uhci_device_bulk_transfer, 372 .upm_start = uhci_device_bulk_start, 373 .upm_abort = uhci_device_bulk_abort, 374 .upm_close = uhci_device_bulk_close, 375 .upm_cleartoggle = uhci_device_clear_toggle, 376 .upm_done = uhci_device_bulk_done, 377 }; 378 379 const struct usbd_pipe_methods uhci_device_isoc_methods = { 380 .upm_init = uhci_device_isoc_init, 381 .upm_fini = uhci_device_isoc_fini, 382 .upm_transfer = uhci_device_isoc_transfer, 383 .upm_abort = uhci_device_isoc_abort, 384 .upm_close = uhci_device_isoc_close, 385 .upm_cleartoggle = uhci_noop, 386 .upm_done = uhci_device_isoc_done, 387 }; 388 389 static inline void 390 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 391 { 392 393 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 394 } 395 396 static inline void 397 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 398 { 399 400 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 401 } 402 403 static inline uhci_soft_qh_t * 404 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 405 { 406 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 407 DPRINTFN(15, "pqh=%p sqh=%p", pqh, sqh, 0, 0); 408 409 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 410 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 411 usb_syncmem(&pqh->dma, 412 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 413 sizeof(pqh->qh.qh_hlink), 414 BUS_DMASYNC_POSTWRITE); 415 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 416 printf("%s: QH not found\n", __func__); 417 return NULL; 418 } 419 #endif 420 } 421 return pqh; 422 } 423 424 void 425 uhci_globalreset(uhci_softc_t *sc) 426 { 427 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 428 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 429 UHCICMD(sc, 0); /* do nothing */ 430 } 431 432 int 433 uhci_init(uhci_softc_t *sc) 434 { 435 usbd_status err; 436 int i, j; 437 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 438 uhci_soft_td_t *std; 439 440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 441 442 #ifdef UHCI_DEBUG 443 thesc = sc; 444 445 if (uhcidebug >= 2) 446 uhci_dumpregs(sc); 447 #endif 448 449 sc->sc_suspend = PWR_RESUME; 450 451 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 452 uhci_globalreset(sc); /* reset the controller */ 453 uhci_reset(sc); 454 455 /* Allocate and initialize real frame array. */ 456 err = usb_allocmem(&sc->sc_bus, 457 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 458 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 459 if (err) 460 return err; 461 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 462 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 463 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 464 465 /* Initialise mutex early for uhci_alloc_* */ 466 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 467 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 468 469 /* 470 * Allocate a TD, inactive, that hangs from the last QH. 471 * This is to avoid a bug in the PIIX that makes it run berserk 472 * otherwise. 473 */ 474 std = uhci_alloc_std(sc); 475 if (std == NULL) 476 return ENOMEM; 477 std->link.std = NULL; 478 std->td.td_link = htole32(UHCI_PTR_T); 479 std->td.td_status = htole32(0); /* inactive */ 480 std->td.td_token = htole32(0); 481 std->td.td_buffer = htole32(0); 482 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 486 lsqh = uhci_alloc_sqh(sc); 487 if (lsqh == NULL) 488 goto fail1; 489 lsqh->hlink = NULL; 490 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 491 lsqh->elink = std; 492 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 493 sc->sc_last_qh = lsqh; 494 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 495 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 496 497 /* Allocate the dummy QH where bulk traffic will be queued. */ 498 bsqh = uhci_alloc_sqh(sc); 499 if (bsqh == NULL) 500 goto fail2; 501 bsqh->hlink = lsqh; 502 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 503 bsqh->elink = NULL; 504 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 506 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 509 /* Allocate dummy QH where high speed control traffic will be queued. */ 510 chsqh = uhci_alloc_sqh(sc); 511 if (chsqh == NULL) 512 goto fail3; 513 chsqh->hlink = bsqh; 514 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 515 chsqh->elink = NULL; 516 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 517 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 518 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 521 /* Allocate dummy QH where control traffic will be queued. */ 522 clsqh = uhci_alloc_sqh(sc); 523 if (clsqh == NULL) 524 goto fail4; 525 clsqh->hlink = chsqh; 526 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 527 clsqh->elink = NULL; 528 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 529 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 530 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 533 /* 534 * Make all (virtual) frame list pointers point to the interrupt 535 * queue heads and the interrupt queue heads at the control 536 * queue head and point the physical frame list to the virtual. 537 */ 538 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 539 std = uhci_alloc_std(sc); 540 sqh = uhci_alloc_sqh(sc); 541 if (std == NULL || sqh == NULL) 542 return USBD_NOMEM; 543 std->link.sqh = sqh; 544 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 545 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 546 std->td.td_token = htole32(0); 547 std->td.td_buffer = htole32(0); 548 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 sqh->hlink = clsqh; 551 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 552 sqh->elink = NULL; 553 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 554 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 556 sc->sc_vframes[i].htd = std; 557 sc->sc_vframes[i].etd = std; 558 sc->sc_vframes[i].hqh = sqh; 559 sc->sc_vframes[i].eqh = sqh; 560 for (j = i; 561 j < UHCI_FRAMELIST_COUNT; 562 j += UHCI_VFRAMELIST_COUNT) 563 sc->sc_pframes[j] = htole32(std->physaddr); 564 } 565 usb_syncmem(&sc->sc_dma, 0, 566 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 567 BUS_DMASYNC_PREWRITE); 568 569 570 TAILQ_INIT(&sc->sc_intrhead); 571 572 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 573 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 574 575 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 576 577 cv_init(&sc->sc_softwake_cv, "uhciab"); 578 579 /* Set up the bus struct. */ 580 sc->sc_bus.ub_methods = &uhci_bus_methods; 581 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 582 sc->sc_bus.ub_usedma = true; 583 584 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 585 586 DPRINTF("Enabling...", 0, 0, 0, 0); 587 588 err = uhci_run(sc, 1, 0); /* and here we go... */ 589 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 590 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 591 return err; 592 593 fail4: 594 uhci_free_sqh(sc, chsqh); 595 fail3: 596 uhci_free_sqh(sc, lsqh); 597 fail2: 598 uhci_free_sqh(sc, lsqh); 599 fail1: 600 uhci_free_std(sc, std); 601 602 return ENOMEM; 603 } 604 605 int 606 uhci_activate(device_t self, enum devact act) 607 { 608 struct uhci_softc *sc = device_private(self); 609 610 switch (act) { 611 case DVACT_DEACTIVATE: 612 sc->sc_dying = 1; 613 return 0; 614 default: 615 return EOPNOTSUPP; 616 } 617 } 618 619 void 620 uhci_childdet(device_t self, device_t child) 621 { 622 struct uhci_softc *sc = device_private(self); 623 624 KASSERT(sc->sc_child == child); 625 sc->sc_child = NULL; 626 } 627 628 int 629 uhci_detach(struct uhci_softc *sc, int flags) 630 { 631 int rv = 0; 632 633 if (sc->sc_child != NULL) 634 rv = config_detach(sc->sc_child, flags); 635 636 if (rv != 0) 637 return rv; 638 639 callout_halt(&sc->sc_poll_handle, NULL); 640 callout_destroy(&sc->sc_poll_handle); 641 642 cv_destroy(&sc->sc_softwake_cv); 643 644 mutex_destroy(&sc->sc_lock); 645 mutex_destroy(&sc->sc_intr_lock); 646 647 pool_cache_destroy(sc->sc_xferpool); 648 649 /* XXX free other data structures XXX */ 650 651 return rv; 652 } 653 654 struct usbd_xfer * 655 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 656 { 657 struct uhci_softc *sc = UHCI_BUS2SC(bus); 658 struct usbd_xfer *xfer; 659 660 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 661 if (xfer != NULL) { 662 memset(xfer, 0, sizeof(struct uhci_xfer)); 663 664 #ifdef DIAGNOSTIC 665 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 666 uxfer->ux_isdone = true; 667 xfer->ux_state = XFER_BUSY; 668 #endif 669 } 670 return xfer; 671 } 672 673 void 674 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 675 { 676 struct uhci_softc *sc = UHCI_BUS2SC(bus); 677 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 678 679 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 680 xfer->ux_state); 681 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 682 #ifdef DIAGNOSTIC 683 xfer->ux_state = XFER_FREE; 684 #endif 685 pool_cache_put(sc->sc_xferpool, xfer); 686 } 687 688 Static void 689 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 690 { 691 struct uhci_softc *sc = UHCI_BUS2SC(bus); 692 693 *lock = &sc->sc_lock; 694 } 695 696 697 /* 698 * Handle suspend/resume. 699 * 700 * We need to switch to polling mode here, because this routine is 701 * called from an interrupt context. This is all right since we 702 * are almost suspended anyway. 703 */ 704 bool 705 uhci_resume(device_t dv, const pmf_qual_t *qual) 706 { 707 uhci_softc_t *sc = device_private(dv); 708 int cmd; 709 710 mutex_spin_enter(&sc->sc_intr_lock); 711 712 cmd = UREAD2(sc, UHCI_CMD); 713 sc->sc_bus.ub_usepolling++; 714 UWRITE2(sc, UHCI_INTR, 0); 715 uhci_globalreset(sc); 716 uhci_reset(sc); 717 if (cmd & UHCI_CMD_RS) 718 uhci_run(sc, 0, 1); 719 720 /* restore saved state */ 721 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 722 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 723 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 724 725 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 726 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 727 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 728 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 729 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 730 UHCICMD(sc, UHCI_CMD_MAXP); 731 uhci_run(sc, 1, 1); /* and start traffic again */ 732 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 733 sc->sc_bus.ub_usepolling--; 734 if (sc->sc_intr_xfer != NULL) 735 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 736 sc->sc_intr_xfer); 737 #ifdef UHCI_DEBUG 738 if (uhcidebug >= 2) 739 uhci_dumpregs(sc); 740 #endif 741 742 sc->sc_suspend = PWR_RESUME; 743 mutex_spin_exit(&sc->sc_intr_lock); 744 745 return true; 746 } 747 748 bool 749 uhci_suspend(device_t dv, const pmf_qual_t *qual) 750 { 751 uhci_softc_t *sc = device_private(dv); 752 int cmd; 753 754 mutex_spin_enter(&sc->sc_intr_lock); 755 756 cmd = UREAD2(sc, UHCI_CMD); 757 758 #ifdef UHCI_DEBUG 759 if (uhcidebug >= 2) 760 uhci_dumpregs(sc); 761 #endif 762 if (sc->sc_intr_xfer != NULL) 763 callout_stop(&sc->sc_poll_handle); 764 sc->sc_suspend = PWR_SUSPEND; 765 sc->sc_bus.ub_usepolling++; 766 767 uhci_run(sc, 0, 1); /* stop the controller */ 768 cmd &= ~UHCI_CMD_RS; 769 770 /* save some state if BIOS doesn't */ 771 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 772 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 773 774 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 775 776 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 777 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 778 sc->sc_bus.ub_usepolling--; 779 780 mutex_spin_exit(&sc->sc_intr_lock); 781 782 return true; 783 } 784 785 #ifdef UHCI_DEBUG 786 Static void 787 uhci_dumpregs(uhci_softc_t *sc) 788 { 789 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 790 DPRINTF("cmd =%04x sts =%04x intr =%04x frnum =%04x", 791 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 792 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 793 DPRINTF("sof =%04x portsc1=%04x portsc2=%04x flbase=%08x", 794 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 795 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 796 } 797 798 void 799 uhci_dump_td(uhci_soft_td_t *p) 800 { 801 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 802 803 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 805 806 DPRINTF("TD(%p) at 0x%08x", p, p->physaddr, 0, 0); 807 DPRINTF(" link=0x%08x status=0x%08x " 808 "token=0x%08x buffer=0x%08x", 809 le32toh(p->td.td_link), 810 le32toh(p->td.td_status), 811 le32toh(p->td.td_token), 812 le32toh(p->td.td_buffer)); 813 814 DPRINTF("bitstuff=%d crcto =%d nak =%d babble =%d", 815 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 816 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 817 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 818 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 819 DPRINTF("dbuffer =%d stalled =%d active =%d ioc =%d", 820 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 821 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 822 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 823 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 824 DPRINTF("ios =%d ls =%d spd =%d", 825 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 826 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 827 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 828 DPRINTF("errcnt =%d actlen =%d pid=%02x", 829 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 830 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 831 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 832 DPRINTF("addr=%d endpt=%d D=%d maxlen=%d,", 833 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 834 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 835 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 836 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 837 } 838 839 void 840 uhci_dump_qh(uhci_soft_qh_t *sqh) 841 { 842 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 843 844 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 845 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 846 847 DPRINTF("QH(%p) at 0x%08x: hlink=%08x elink=%08x", sqh, 848 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 849 le32toh(sqh->qh.qh_elink)); 850 851 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 852 } 853 854 855 #if 1 856 void 857 uhci_dump(void) 858 { 859 uhci_dump_all(thesc); 860 } 861 #endif 862 863 void 864 uhci_dump_all(uhci_softc_t *sc) 865 { 866 uhci_dumpregs(sc); 867 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 868 uhci_dump_qhs(sc->sc_lctl_start); 869 } 870 871 872 void 873 uhci_dump_qhs(uhci_soft_qh_t *sqh) 874 { 875 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 876 877 uhci_dump_qh(sqh); 878 879 /* 880 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 881 * Traverses sideways first, then down. 882 * 883 * QH1 884 * QH2 885 * No QH 886 * TD2.1 887 * TD2.2 888 * TD1.1 889 * etc. 890 * 891 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 892 */ 893 894 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 895 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 896 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 897 uhci_dump_qhs(sqh->hlink); 898 else 899 DPRINTF("No QH", 0, 0, 0, 0); 900 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 901 902 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 903 uhci_dump_tds(sqh->elink); 904 else 905 DPRINTF("No QH", 0, 0, 0, 0); 906 } 907 908 void 909 uhci_dump_tds(uhci_soft_td_t *std) 910 { 911 uhci_soft_td_t *td; 912 int stop; 913 914 for (td = std; td != NULL; td = td->link.std) { 915 uhci_dump_td(td); 916 917 /* 918 * Check whether the link pointer in this TD marks 919 * the link pointer as end of queue. This avoids 920 * printing the free list in case the queue/TD has 921 * already been moved there (seatbelt). 922 */ 923 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 924 sizeof(td->td.td_link), 925 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 926 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 927 le32toh(td->td.td_link) == 0); 928 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 929 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 930 if (stop) 931 break; 932 } 933 } 934 935 Static void 936 uhci_dump_ii(struct uhci_xfer *ux) 937 { 938 struct usbd_pipe *pipe; 939 usb_endpoint_descriptor_t *ed; 940 struct usbd_device *dev; 941 942 if (ux == NULL) { 943 printf("ux NULL\n"); 944 return; 945 } 946 pipe = ux->ux_xfer.ux_pipe; 947 if (pipe == NULL) { 948 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 949 return; 950 } 951 if (pipe->up_endpoint == NULL) { 952 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 953 ux, ux->ux_isdone, pipe); 954 return; 955 } 956 if (pipe->up_dev == NULL) { 957 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 958 ux, ux->ux_isdone, pipe); 959 return; 960 } 961 ed = pipe->up_endpoint->ue_edesc; 962 dev = pipe->up_dev; 963 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 964 ux, ux->ux_isdone, dev, 965 UGETW(dev->ud_ddesc.idVendor), 966 UGETW(dev->ud_ddesc.idProduct), 967 dev->ud_addr, pipe, 968 ed->bEndpointAddress, ed->bmAttributes); 969 } 970 971 void uhci_dump_iis(struct uhci_softc *sc); 972 void 973 uhci_dump_iis(struct uhci_softc *sc) 974 { 975 struct uhci_xfer *ux; 976 977 printf("interrupt list:\n"); 978 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 979 uhci_dump_ii(ux); 980 } 981 982 void iidump(void); 983 void iidump(void) { uhci_dump_iis(thesc); } 984 985 #endif 986 987 /* 988 * This routine is executed periodically and simulates interrupts 989 * from the root controller interrupt pipe for port status change. 990 */ 991 void 992 uhci_poll_hub(void *addr) 993 { 994 struct usbd_xfer *xfer = addr; 995 struct usbd_pipe *pipe = xfer->ux_pipe; 996 uhci_softc_t *sc; 997 u_char *p; 998 999 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1000 1001 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1002 return; /* device has detached */ 1003 sc = UHCI_PIPE2SC(pipe); 1004 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1005 1006 p = xfer->ux_buf; 1007 p[0] = 0; 1008 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1009 p[0] |= 1<<1; 1010 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1011 p[0] |= 1<<2; 1012 if (p[0] == 0) 1013 /* No change, try again in a while */ 1014 return; 1015 1016 xfer->ux_actlen = 1; 1017 xfer->ux_status = USBD_NORMAL_COMPLETION; 1018 mutex_enter(&sc->sc_lock); 1019 usb_transfer_complete(xfer); 1020 mutex_exit(&sc->sc_lock); 1021 } 1022 1023 void 1024 uhci_root_intr_done(struct usbd_xfer *xfer) 1025 { 1026 } 1027 1028 /* 1029 * Let the last QH loop back to the high speed control transfer QH. 1030 * This is what intel calls "bandwidth reclamation" and improves 1031 * USB performance a lot for some devices. 1032 * If we are already looping, just count it. 1033 */ 1034 void 1035 uhci_add_loop(uhci_softc_t *sc) 1036 { 1037 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1038 1039 #ifdef UHCI_DEBUG 1040 if (uhcinoloop) 1041 return; 1042 #endif 1043 if (++sc->sc_loops == 1) { 1044 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1045 /* Note, we don't loop back the soft pointer. */ 1046 sc->sc_last_qh->qh.qh_hlink = 1047 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1048 usb_syncmem(&sc->sc_last_qh->dma, 1049 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1050 sizeof(sc->sc_last_qh->qh.qh_hlink), 1051 BUS_DMASYNC_PREWRITE); 1052 } 1053 } 1054 1055 void 1056 uhci_rem_loop(uhci_softc_t *sc) 1057 { 1058 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1059 1060 #ifdef UHCI_DEBUG 1061 if (uhcinoloop) 1062 return; 1063 #endif 1064 if (--sc->sc_loops == 0) { 1065 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1066 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1067 usb_syncmem(&sc->sc_last_qh->dma, 1068 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1069 sizeof(sc->sc_last_qh->qh.qh_hlink), 1070 BUS_DMASYNC_PREWRITE); 1071 } 1072 } 1073 1074 /* Add high speed control QH, called with lock held. */ 1075 void 1076 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1077 { 1078 uhci_soft_qh_t *eqh; 1079 1080 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1081 1082 KASSERT(mutex_owned(&sc->sc_lock)); 1083 1084 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1085 eqh = sc->sc_hctl_end; 1086 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1087 sizeof(eqh->qh.qh_hlink), 1088 BUS_DMASYNC_POSTWRITE); 1089 sqh->hlink = eqh->hlink; 1090 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1091 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1092 BUS_DMASYNC_PREWRITE); 1093 eqh->hlink = sqh; 1094 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1095 sc->sc_hctl_end = sqh; 1096 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1097 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1098 #ifdef UHCI_CTL_LOOP 1099 uhci_add_loop(sc); 1100 #endif 1101 } 1102 1103 /* Remove high speed control QH, called with lock held. */ 1104 void 1105 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1106 { 1107 uhci_soft_qh_t *pqh; 1108 uint32_t elink; 1109 1110 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1111 1112 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1113 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1114 #ifdef UHCI_CTL_LOOP 1115 uhci_rem_loop(sc); 1116 #endif 1117 /* 1118 * The T bit should be set in the elink of the QH so that the HC 1119 * doesn't follow the pointer. This condition may fail if the 1120 * the transferred packet was short so that the QH still points 1121 * at the last used TD. 1122 * In this case we set the T bit and wait a little for the HC 1123 * to stop looking at the TD. 1124 * Note that if the TD chain is large enough, the controller 1125 * may still be looking at the chain at the end of this function. 1126 * uhci_free_std_chain() will make sure the controller stops 1127 * looking at it quickly, but until then we should not change 1128 * sqh->hlink. 1129 */ 1130 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1131 sizeof(sqh->qh.qh_elink), 1132 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1133 elink = le32toh(sqh->qh.qh_elink); 1134 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1135 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1136 if (!(elink & UHCI_PTR_T)) { 1137 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1138 usb_syncmem(&sqh->dma, 1139 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1140 sizeof(sqh->qh.qh_elink), 1141 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1142 delay(UHCI_QH_REMOVE_DELAY); 1143 } 1144 1145 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1146 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1147 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1148 pqh->hlink = sqh->hlink; 1149 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1150 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1151 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1152 delay(UHCI_QH_REMOVE_DELAY); 1153 if (sc->sc_hctl_end == sqh) 1154 sc->sc_hctl_end = pqh; 1155 } 1156 1157 /* Add low speed control QH, called with lock held. */ 1158 void 1159 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1160 { 1161 uhci_soft_qh_t *eqh; 1162 1163 KASSERT(mutex_owned(&sc->sc_lock)); 1164 1165 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1166 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1167 1168 eqh = sc->sc_lctl_end; 1169 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1170 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1171 sqh->hlink = eqh->hlink; 1172 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1173 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1174 BUS_DMASYNC_PREWRITE); 1175 eqh->hlink = sqh; 1176 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1177 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1178 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1179 sc->sc_lctl_end = sqh; 1180 } 1181 1182 /* Remove low speed control QH, called with lock held. */ 1183 void 1184 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1185 { 1186 uhci_soft_qh_t *pqh; 1187 uint32_t elink; 1188 1189 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1190 1191 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1192 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1193 1194 /* See comment in uhci_remove_hs_ctrl() */ 1195 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1196 sizeof(sqh->qh.qh_elink), 1197 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1198 elink = le32toh(sqh->qh.qh_elink); 1199 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1200 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1201 if (!(elink & UHCI_PTR_T)) { 1202 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1203 usb_syncmem(&sqh->dma, 1204 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1205 sizeof(sqh->qh.qh_elink), 1206 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1207 delay(UHCI_QH_REMOVE_DELAY); 1208 } 1209 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1210 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1211 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1212 pqh->hlink = sqh->hlink; 1213 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1214 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1215 sizeof(pqh->qh.qh_hlink), 1216 BUS_DMASYNC_PREWRITE); 1217 delay(UHCI_QH_REMOVE_DELAY); 1218 if (sc->sc_lctl_end == sqh) 1219 sc->sc_lctl_end = pqh; 1220 } 1221 1222 /* Add bulk QH, called with lock held. */ 1223 void 1224 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1225 { 1226 uhci_soft_qh_t *eqh; 1227 1228 KASSERT(mutex_owned(&sc->sc_lock)); 1229 1230 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1231 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1232 1233 eqh = sc->sc_bulk_end; 1234 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1235 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1236 sqh->hlink = eqh->hlink; 1237 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1238 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1239 BUS_DMASYNC_PREWRITE); 1240 eqh->hlink = sqh; 1241 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1242 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1243 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1244 sc->sc_bulk_end = sqh; 1245 uhci_add_loop(sc); 1246 } 1247 1248 /* Remove bulk QH, called with lock held. */ 1249 void 1250 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1251 { 1252 uhci_soft_qh_t *pqh; 1253 1254 KASSERT(mutex_owned(&sc->sc_lock)); 1255 1256 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1257 DPRINTFN(10, "sqh %p", sqh, 0, 0, 0); 1258 1259 uhci_rem_loop(sc); 1260 /* See comment in uhci_remove_hs_ctrl() */ 1261 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1262 sizeof(sqh->qh.qh_elink), 1263 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1264 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1265 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1266 usb_syncmem(&sqh->dma, 1267 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1268 sizeof(sqh->qh.qh_elink), 1269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1270 delay(UHCI_QH_REMOVE_DELAY); 1271 } 1272 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1273 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1274 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1275 pqh->hlink = sqh->hlink; 1276 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1277 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1278 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1279 delay(UHCI_QH_REMOVE_DELAY); 1280 if (sc->sc_bulk_end == sqh) 1281 sc->sc_bulk_end = pqh; 1282 } 1283 1284 Static int uhci_intr1(uhci_softc_t *); 1285 1286 int 1287 uhci_intr(void *arg) 1288 { 1289 uhci_softc_t *sc = arg; 1290 int ret = 0; 1291 1292 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1293 1294 mutex_spin_enter(&sc->sc_intr_lock); 1295 1296 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1297 goto done; 1298 1299 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1300 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1301 goto done; 1302 } 1303 1304 ret = uhci_intr1(sc); 1305 1306 done: 1307 mutex_spin_exit(&sc->sc_intr_lock); 1308 return ret; 1309 } 1310 1311 int 1312 uhci_intr1(uhci_softc_t *sc) 1313 { 1314 int status; 1315 int ack; 1316 1317 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1318 1319 #ifdef UHCI_DEBUG 1320 if (uhcidebug >= 15) { 1321 DPRINTF("sc %p", sc, 0, 0, 0); 1322 uhci_dumpregs(sc); 1323 } 1324 #endif 1325 1326 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1327 1328 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1329 /* Check if the interrupt was for us. */ 1330 if (status == 0) 1331 return 0; 1332 1333 if (sc->sc_suspend != PWR_RESUME) { 1334 #ifdef DIAGNOSTIC 1335 printf("%s: interrupt while not operating ignored\n", 1336 device_xname(sc->sc_dev)); 1337 #endif 1338 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1339 return 0; 1340 } 1341 1342 ack = 0; 1343 if (status & UHCI_STS_USBINT) 1344 ack |= UHCI_STS_USBINT; 1345 if (status & UHCI_STS_USBEI) 1346 ack |= UHCI_STS_USBEI; 1347 if (status & UHCI_STS_RD) { 1348 ack |= UHCI_STS_RD; 1349 #ifdef UHCI_DEBUG 1350 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1351 #endif 1352 } 1353 if (status & UHCI_STS_HSE) { 1354 ack |= UHCI_STS_HSE; 1355 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1356 } 1357 if (status & UHCI_STS_HCPE) { 1358 ack |= UHCI_STS_HCPE; 1359 printf("%s: host controller process error\n", 1360 device_xname(sc->sc_dev)); 1361 } 1362 1363 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1364 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1365 /* no acknowledge needed */ 1366 if (!sc->sc_dying) { 1367 printf("%s: host controller halted\n", 1368 device_xname(sc->sc_dev)); 1369 #ifdef UHCI_DEBUG 1370 uhci_dump_all(sc); 1371 #endif 1372 } 1373 sc->sc_dying = 1; 1374 } 1375 1376 if (!ack) 1377 return 0; /* nothing to acknowledge */ 1378 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1379 1380 usb_schedsoftintr(&sc->sc_bus); 1381 1382 DPRINTFN(15, "sc %p done", sc, 0, 0, 0); 1383 1384 return 1; 1385 } 1386 1387 void 1388 uhci_softintr(void *v) 1389 { 1390 struct usbd_bus *bus = v; 1391 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1392 struct uhci_xfer *ux, *nextux; 1393 ux_completeq_t cq; 1394 1395 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1396 DPRINTF("sc %p", sc, 0, 0, 0); 1397 1398 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1399 1400 TAILQ_INIT(&cq); 1401 /* 1402 * Interrupts on UHCI really suck. When the host controller 1403 * interrupts because a transfer is completed there is no 1404 * way of knowing which transfer it was. You can scan down 1405 * the TDs and QHs of the previous frame to limit the search, 1406 * but that assumes that the interrupt was not delayed by more 1407 * than 1 ms, which may not always be true (e.g. after debug 1408 * output on a slow console). 1409 * We scan all interrupt descriptors to see if any have 1410 * completed. 1411 */ 1412 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1413 uhci_check_intr(sc, ux, &cq); 1414 } 1415 1416 /* 1417 * We abuse ux_list for the interrupt and complete lists and 1418 * interrupt transfers will get re-added here so use 1419 * the _SAFE version of TAILQ_FOREACH. 1420 */ 1421 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1422 DPRINTF("ux %p", ux, 0, 0, 0); 1423 usb_transfer_complete(&ux->ux_xfer); 1424 } 1425 1426 if (sc->sc_softwake) { 1427 sc->sc_softwake = 0; 1428 cv_broadcast(&sc->sc_softwake_cv); 1429 } 1430 } 1431 1432 /* Check for an interrupt. */ 1433 void 1434 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1435 { 1436 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1437 uint32_t status; 1438 1439 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1440 DPRINTFN(15, "ux %p", ux, 0, 0, 0); 1441 1442 KASSERT(ux != NULL); 1443 1444 struct usbd_xfer *xfer = &ux->ux_xfer; 1445 if (xfer->ux_status == USBD_CANCELLED || 1446 xfer->ux_status == USBD_TIMEOUT) { 1447 DPRINTF("aborted xfer %p", xfer, 0, 0, 0); 1448 return; 1449 } 1450 1451 switch (ux->ux_type) { 1452 case UX_CTRL: 1453 fstd = ux->ux_setup; 1454 lstd = ux->ux_stat; 1455 break; 1456 case UX_BULK: 1457 case UX_INTR: 1458 case UX_ISOC: 1459 fstd = ux->ux_stdstart; 1460 lstd = ux->ux_stdend; 1461 break; 1462 default: 1463 KASSERT(false); 1464 break; 1465 } 1466 if (fstd == NULL) 1467 return; 1468 1469 KASSERT(lstd != NULL); 1470 1471 usb_syncmem(&lstd->dma, 1472 lstd->offs + offsetof(uhci_td_t, td_status), 1473 sizeof(lstd->td.td_status), 1474 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1475 status = le32toh(lstd->td.td_status); 1476 usb_syncmem(&lstd->dma, 1477 lstd->offs + offsetof(uhci_td_t, td_status), 1478 sizeof(lstd->td.td_status), 1479 BUS_DMASYNC_PREREAD); 1480 1481 /* If the last TD is not marked active we can complete */ 1482 if (!(status & UHCI_TD_ACTIVE)) { 1483 done: 1484 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1485 1486 callout_stop(&xfer->ux_callout); 1487 uhci_idone(ux, cqp); 1488 return; 1489 } 1490 1491 /* 1492 * If the last TD is still active we need to check whether there 1493 * is an error somewhere in the middle, or whether there was a 1494 * short packet (SPD and not ACTIVE). 1495 */ 1496 DPRINTFN(12, "active ux=%p", ux, 0, 0, 0); 1497 for (std = fstd; std != lstd; std = std->link.std) { 1498 usb_syncmem(&std->dma, 1499 std->offs + offsetof(uhci_td_t, td_status), 1500 sizeof(std->td.td_status), 1501 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1502 status = le32toh(std->td.td_status); 1503 usb_syncmem(&std->dma, 1504 std->offs + offsetof(uhci_td_t, td_status), 1505 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1506 1507 /* If there's an active TD the xfer isn't done. */ 1508 if (status & UHCI_TD_ACTIVE) { 1509 DPRINTFN(12, "ux=%p std=%p still active", 1510 ux, std, 0, 0); 1511 return; 1512 } 1513 1514 /* Any kind of error makes the xfer done. */ 1515 if (status & UHCI_TD_STALLED) 1516 goto done; 1517 1518 /* 1519 * If the data phase of a control transfer is short, we need 1520 * to complete the status stage 1521 */ 1522 1523 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1524 struct uhci_pipe *upipe = 1525 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1526 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1527 uhci_soft_td_t *stat = upipe->ctrl.stat; 1528 1529 DPRINTFN(12, "ux=%p std=%p control status" 1530 "phase needs completion", ux, ux->ux_stdstart, 0, 0); 1531 1532 sqh->qh.qh_elink = 1533 htole32(stat->physaddr | UHCI_PTR_TD); 1534 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1535 BUS_DMASYNC_PREWRITE); 1536 break; 1537 } 1538 1539 /* We want short packets, and it is short: it's done */ 1540 usb_syncmem(&std->dma, 1541 std->offs + offsetof(uhci_td_t, td_token), 1542 sizeof(std->td.td_token), 1543 BUS_DMASYNC_POSTWRITE); 1544 1545 if ((status & UHCI_TD_SPD) && 1546 UHCI_TD_GET_ACTLEN(status) < 1547 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1548 goto done; 1549 } 1550 } 1551 } 1552 1553 /* Called with USB lock held. */ 1554 void 1555 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1556 { 1557 struct usbd_xfer *xfer = &ux->ux_xfer; 1558 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1559 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1560 uhci_soft_td_t *std; 1561 uint32_t status = 0, nstatus; 1562 int actlen; 1563 1564 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1565 1566 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1567 DPRINTFN(12, "ux=%p", ux, 0, 0, 0); 1568 1569 #ifdef DIAGNOSTIC 1570 #ifdef UHCI_DEBUG 1571 if (ux->ux_isdone) { 1572 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1573 uhci_dump_ii(ux); 1574 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1575 } 1576 #endif 1577 KASSERT(!ux->ux_isdone); 1578 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1579 ux->ux_type, xfer->ux_status); 1580 ux->ux_isdone = true; 1581 #endif 1582 1583 if (xfer->ux_nframes != 0) { 1584 /* Isoc transfer, do things differently. */ 1585 uhci_soft_td_t **stds = upipe->isoc.stds; 1586 int i, n, nframes, len; 1587 1588 DPRINTFN(5, "ux=%p isoc ready", ux, 0, 0, 0); 1589 1590 nframes = xfer->ux_nframes; 1591 actlen = 0; 1592 n = ux->ux_curframe; 1593 for (i = 0; i < nframes; i++) { 1594 std = stds[n]; 1595 #ifdef UHCI_DEBUG 1596 if (uhcidebug >= 5) { 1597 DPRINTF("isoc TD %d", i, 0, 0, 0); 1598 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1599 uhci_dump_td(std); 1600 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1601 } 1602 #endif 1603 if (++n >= UHCI_VFRAMELIST_COUNT) 1604 n = 0; 1605 usb_syncmem(&std->dma, 1606 std->offs + offsetof(uhci_td_t, td_status), 1607 sizeof(std->td.td_status), 1608 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1609 status = le32toh(std->td.td_status); 1610 len = UHCI_TD_GET_ACTLEN(status); 1611 xfer->ux_frlengths[i] = len; 1612 actlen += len; 1613 } 1614 upipe->isoc.inuse -= nframes; 1615 xfer->ux_actlen = actlen; 1616 xfer->ux_status = USBD_NORMAL_COMPLETION; 1617 goto end; 1618 } 1619 1620 #ifdef UHCI_DEBUG 1621 DPRINTFN(10, "ux=%p, xfer=%p, pipe=%p ready", ux, xfer, upipe, 0); 1622 if (uhcidebug >= 10) { 1623 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1624 uhci_dump_tds(ux->ux_stdstart); 1625 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1626 } 1627 #endif 1628 1629 /* The transfer is done, compute actual length and status. */ 1630 actlen = 0; 1631 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1632 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1633 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1634 nstatus = le32toh(std->td.td_status); 1635 if (nstatus & UHCI_TD_ACTIVE) 1636 break; 1637 1638 status = nstatus; 1639 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1640 UHCI_TD_PID_SETUP) 1641 actlen += UHCI_TD_GET_ACTLEN(status); 1642 else { 1643 /* 1644 * UHCI will report CRCTO in addition to a STALL or NAK 1645 * for a SETUP transaction. See section 3.2.2, "TD 1646 * CONTROL AND STATUS". 1647 */ 1648 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1649 status &= ~UHCI_TD_CRCTO; 1650 } 1651 } 1652 /* If there are left over TDs we need to update the toggle. */ 1653 if (std != NULL) 1654 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1655 1656 status &= UHCI_TD_ERROR; 1657 DPRINTFN(10, "actlen=%d, status=0x%x", actlen, status, 0, 0); 1658 xfer->ux_actlen = actlen; 1659 if (status != 0) { 1660 1661 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1662 "error, addr=%d, endpt=0x%02x", 1663 xfer->ux_pipe->up_dev->ud_addr, 1664 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1665 0, 0); 1666 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1667 "bitstuff=%d crcto =%d nak =%d babble =%d", 1668 !!(status & UHCI_TD_BITSTUFF), 1669 !!(status & UHCI_TD_CRCTO), 1670 !!(status & UHCI_TD_NAK), 1671 !!(status & UHCI_TD_BABBLE)); 1672 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1673 "dbuffer =%d stalled =%d active =%d", 1674 !!(status & UHCI_TD_DBUFFER), 1675 !!(status & UHCI_TD_STALLED), 1676 !!(status & UHCI_TD_ACTIVE), 1677 0); 1678 1679 if (status == UHCI_TD_STALLED) 1680 xfer->ux_status = USBD_STALLED; 1681 else 1682 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1683 } else { 1684 xfer->ux_status = USBD_NORMAL_COMPLETION; 1685 } 1686 1687 end: 1688 uhci_del_intr_list(sc, ux); 1689 if (cqp) 1690 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1691 1692 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1693 DPRINTFN(12, "ux=%p done", ux, 0, 0, 0); 1694 } 1695 1696 /* 1697 * Called when a request does not complete. 1698 */ 1699 void 1700 uhci_timeout(void *addr) 1701 { 1702 struct usbd_xfer *xfer = addr; 1703 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1704 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1705 1706 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1707 1708 DPRINTF("uxfer %p", uxfer, 0, 0, 0); 1709 1710 if (sc->sc_dying) { 1711 mutex_enter(&sc->sc_lock); 1712 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1713 mutex_exit(&sc->sc_lock); 1714 return; 1715 } 1716 1717 /* Execute the abort in a process context. */ 1718 usb_init_task(&uxfer->ux_aborttask, uhci_timeout_task, xfer, 1719 USB_TASKQ_MPSAFE); 1720 usb_add_task(uxfer->ux_xfer.ux_pipe->up_dev, &uxfer->ux_aborttask, 1721 USB_TASKQ_HC); 1722 } 1723 1724 void 1725 uhci_timeout_task(void *addr) 1726 { 1727 struct usbd_xfer *xfer = addr; 1728 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1729 1730 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1731 1732 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1733 1734 mutex_enter(&sc->sc_lock); 1735 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1736 mutex_exit(&sc->sc_lock); 1737 } 1738 1739 void 1740 uhci_poll(struct usbd_bus *bus) 1741 { 1742 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1743 1744 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1745 mutex_spin_enter(&sc->sc_intr_lock); 1746 uhci_intr1(sc); 1747 mutex_spin_exit(&sc->sc_intr_lock); 1748 } 1749 } 1750 1751 void 1752 uhci_reset(uhci_softc_t *sc) 1753 { 1754 int n; 1755 1756 UHCICMD(sc, UHCI_CMD_HCRESET); 1757 /* The reset bit goes low when the controller is done. */ 1758 for (n = 0; n < UHCI_RESET_TIMEOUT && 1759 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1760 usb_delay_ms(&sc->sc_bus, 1); 1761 if (n >= UHCI_RESET_TIMEOUT) 1762 printf("%s: controller did not reset\n", 1763 device_xname(sc->sc_dev)); 1764 } 1765 1766 usbd_status 1767 uhci_run(uhci_softc_t *sc, int run, int locked) 1768 { 1769 int n, running; 1770 uint16_t cmd; 1771 1772 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1773 1774 run = run != 0; 1775 if (!locked) 1776 mutex_spin_enter(&sc->sc_intr_lock); 1777 1778 DPRINTF("setting run=%d", run, 0, 0, 0); 1779 cmd = UREAD2(sc, UHCI_CMD); 1780 if (run) 1781 cmd |= UHCI_CMD_RS; 1782 else 1783 cmd &= ~UHCI_CMD_RS; 1784 UHCICMD(sc, cmd); 1785 for (n = 0; n < 10; n++) { 1786 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1787 /* return when we've entered the state we want */ 1788 if (run == running) { 1789 if (!locked) 1790 mutex_spin_exit(&sc->sc_intr_lock); 1791 DPRINTF("done cmd=0x%x sts=0x%x", 1792 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1793 return USBD_NORMAL_COMPLETION; 1794 } 1795 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1796 } 1797 if (!locked) 1798 mutex_spin_exit(&sc->sc_intr_lock); 1799 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1800 run ? "start" : "stop"); 1801 return USBD_IOERROR; 1802 } 1803 1804 /* 1805 * Memory management routines. 1806 * uhci_alloc_std allocates TDs 1807 * uhci_alloc_sqh allocates QHs 1808 * These two routines do their own free list management, 1809 * partly for speed, partly because allocating DMAable memory 1810 * has page size granularity so much memory would be wasted if 1811 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1812 */ 1813 1814 uhci_soft_td_t * 1815 uhci_alloc_std(uhci_softc_t *sc) 1816 { 1817 uhci_soft_td_t *std; 1818 usbd_status err; 1819 int i, offs; 1820 usb_dma_t dma; 1821 1822 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1823 1824 mutex_enter(&sc->sc_lock); 1825 if (sc->sc_freetds == NULL) { 1826 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1827 mutex_exit(&sc->sc_lock); 1828 1829 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1830 UHCI_TD_ALIGN, &dma); 1831 if (err) 1832 return NULL; 1833 1834 mutex_enter(&sc->sc_lock); 1835 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1836 offs = i * UHCI_STD_SIZE; 1837 std = KERNADDR(&dma, offs); 1838 std->physaddr = DMAADDR(&dma, offs); 1839 std->dma = dma; 1840 std->offs = offs; 1841 std->link.std = sc->sc_freetds; 1842 sc->sc_freetds = std; 1843 } 1844 } 1845 std = sc->sc_freetds; 1846 sc->sc_freetds = std->link.std; 1847 mutex_exit(&sc->sc_lock); 1848 1849 memset(&std->td, 0, sizeof(uhci_td_t)); 1850 1851 return std; 1852 } 1853 1854 #define TD_IS_FREE 0x12345678 1855 1856 void 1857 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1858 { 1859 KASSERT(mutex_owned(&sc->sc_lock)); 1860 1861 #ifdef DIAGNOSTIC 1862 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1863 printf("%s: freeing free TD %p\n", __func__, std); 1864 return; 1865 } 1866 std->td.td_token = htole32(TD_IS_FREE); 1867 #endif 1868 1869 std->link.std = sc->sc_freetds; 1870 sc->sc_freetds = std; 1871 } 1872 1873 void 1874 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1875 { 1876 mutex_enter(&sc->sc_lock); 1877 uhci_free_std_locked(sc, std); 1878 mutex_exit(&sc->sc_lock); 1879 } 1880 1881 uhci_soft_qh_t * 1882 uhci_alloc_sqh(uhci_softc_t *sc) 1883 { 1884 uhci_soft_qh_t *sqh; 1885 usbd_status err; 1886 int i, offs; 1887 usb_dma_t dma; 1888 1889 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1890 1891 mutex_enter(&sc->sc_lock); 1892 if (sc->sc_freeqhs == NULL) { 1893 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1894 mutex_exit(&sc->sc_lock); 1895 1896 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1897 UHCI_QH_ALIGN, &dma); 1898 if (err) 1899 return NULL; 1900 1901 mutex_enter(&sc->sc_lock); 1902 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1903 offs = i * UHCI_SQH_SIZE; 1904 sqh = KERNADDR(&dma, offs); 1905 sqh->physaddr = DMAADDR(&dma, offs); 1906 sqh->dma = dma; 1907 sqh->offs = offs; 1908 sqh->hlink = sc->sc_freeqhs; 1909 sc->sc_freeqhs = sqh; 1910 } 1911 } 1912 sqh = sc->sc_freeqhs; 1913 sc->sc_freeqhs = sqh->hlink; 1914 mutex_exit(&sc->sc_lock); 1915 1916 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1917 1918 return sqh; 1919 } 1920 1921 void 1922 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1923 { 1924 KASSERT(mutex_owned(&sc->sc_lock)); 1925 1926 sqh->hlink = sc->sc_freeqhs; 1927 sc->sc_freeqhs = sqh; 1928 } 1929 1930 #if 0 1931 void 1932 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1933 uhci_soft_td_t *stdend) 1934 { 1935 uhci_soft_td_t *p; 1936 uint32_t td_link; 1937 1938 /* 1939 * to avoid race condition with the controller which may be looking 1940 * at this chain, we need to first invalidate all links, and 1941 * then wait for the controller to move to another queue 1942 */ 1943 for (p = std; p != stdend; p = p->link.std) { 1944 usb_syncmem(&p->dma, 1945 p->offs + offsetof(uhci_td_t, td_link), 1946 sizeof(p->td.td_link), 1947 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1948 td_link = le32toh(p->td.td_link); 1949 usb_syncmem(&p->dma, 1950 p->offs + offsetof(uhci_td_t, td_link), 1951 sizeof(p->td.td_link), 1952 BUS_DMASYNC_PREREAD); 1953 if ((td_link & UHCI_PTR_T) == 0) { 1954 p->td.td_link = htole32(UHCI_PTR_T); 1955 usb_syncmem(&p->dma, 1956 p->offs + offsetof(uhci_td_t, td_link), 1957 sizeof(p->td.td_link), 1958 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1959 } 1960 } 1961 delay(UHCI_QH_REMOVE_DELAY); 1962 1963 for (; std != stdend; std = p) { 1964 p = std->link.std; 1965 uhci_free_std(sc, std); 1966 } 1967 } 1968 #endif 1969 1970 int 1971 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len, 1972 int rd, uhci_soft_td_t **sp) 1973 { 1974 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1975 uint16_t flags = xfer->ux_flags; 1976 uhci_soft_td_t *p; 1977 1978 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1979 1980 DPRINTFN(8, "xfer=%p pipe=%p", xfer, xfer->ux_pipe, 0, 0); 1981 1982 ASSERT_SLEEPABLE(); 1983 KASSERT(sp); 1984 1985 int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 1986 if (maxp == 0) { 1987 printf("%s: maxp=0\n", __func__); 1988 return EINVAL; 1989 } 1990 size_t ntd = (len + maxp - 1) / maxp; 1991 if (!rd && (flags & USBD_FORCE_SHORT_XFER)) { 1992 ntd++; 1993 } 1994 DPRINTFN(10, "maxp=%d ntd=%d", maxp, ntd, 0, 0); 1995 1996 uxfer->ux_stds = NULL; 1997 uxfer->ux_nstd = ntd; 1998 if (ntd == 0) { 1999 *sp = NULL; 2000 DPRINTF("ntd=0", 0, 0, 0, 0); 2001 return 0; 2002 } 2003 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2004 KM_SLEEP); 2005 2006 for (int i = 0; i < ntd; i++) { 2007 p = uhci_alloc_std(sc); 2008 if (p == NULL) { 2009 if (i != 0) { 2010 uxfer->ux_nstd = i; 2011 uhci_free_stds(sc, uxfer); 2012 } 2013 kmem_free(uxfer->ux_stds, 2014 sizeof(uhci_soft_td_t *) * ntd); 2015 return ENOMEM; 2016 } 2017 uxfer->ux_stds[i] = p; 2018 } 2019 2020 *sp = uxfer->ux_stds[0]; 2021 2022 return 0; 2023 } 2024 2025 Static void 2026 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2027 { 2028 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2029 2030 DPRINTFN(8, "ux=%p", ux, 0, 0, 0); 2031 2032 mutex_enter(&sc->sc_lock); 2033 for (size_t i = 0; i < ux->ux_nstd; i++) { 2034 uhci_soft_td_t *std = ux->ux_stds[i]; 2035 #ifdef DIAGNOSTIC 2036 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2037 printf("%s: freeing free TD %p\n", __func__, std); 2038 return; 2039 } 2040 std->td.td_token = htole32(TD_IS_FREE); 2041 #endif 2042 ux->ux_stds[i]->link.std = sc->sc_freetds; 2043 sc->sc_freetds = std; 2044 } 2045 mutex_exit(&sc->sc_lock); 2046 } 2047 2048 2049 Static void 2050 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2051 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2052 { 2053 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2054 struct usbd_pipe *pipe = xfer->ux_pipe; 2055 usb_dma_t *dma = &xfer->ux_dmabuf; 2056 uint16_t flags = xfer->ux_flags; 2057 uhci_soft_td_t *std, *prev; 2058 int len = length; 2059 int tog = *toggle; 2060 int maxp; 2061 uint32_t status; 2062 size_t i; 2063 2064 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2065 DPRINTFN(8, "xfer=%p len %d isread %d toggle %d", xfer, 2066 len, isread, *toggle); 2067 2068 KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2069 2070 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2071 KASSERT(maxp != 0); 2072 2073 int addr = xfer->ux_pipe->up_dev->ud_addr; 2074 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2075 2076 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2077 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2078 status |= UHCI_TD_LS; 2079 if (flags & USBD_SHORT_XFER_OK) 2080 status |= UHCI_TD_SPD; 2081 usb_syncmem(dma, 0, len, 2082 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2083 std = prev = NULL; 2084 for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) { 2085 int l = len; 2086 std = uxfer->ux_stds[i]; 2087 if (l > maxp) 2088 l = maxp; 2089 2090 if (prev) { 2091 prev->link.std = std; 2092 prev->td.td_link = htole32( 2093 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2094 ); 2095 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2096 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2097 } 2098 2099 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2100 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2101 2102 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2103 std->td.td_status = htole32(status); 2104 std->td.td_token = htole32( 2105 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2106 UHCI_TD_SET_DEVADDR(addr) | 2107 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2108 UHCI_TD_SET_DT(tog) | 2109 UHCI_TD_SET_MAXLEN(l) 2110 ); 2111 std->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2112 2113 std->link.std = NULL; 2114 2115 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2116 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2117 tog ^= 1; 2118 2119 len -= l; 2120 } 2121 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2122 xfer, length, len, maxp, uxfer->ux_nstd, i); 2123 2124 if (!isread && 2125 (flags & USBD_FORCE_SHORT_XFER) && 2126 length % maxp == 0) { 2127 /* Force a 0 length transfer at the end. */ 2128 KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i, 2129 uxfer->ux_nstd); 2130 std = uxfer->ux_stds[i++]; 2131 2132 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2133 std->td.td_status = htole32(status); 2134 std->td.td_token = htole32( 2135 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2136 UHCI_TD_SET_DEVADDR(addr) | 2137 UHCI_TD_SET_PID(UHCI_TD_PID_OUT) | 2138 UHCI_TD_SET_DT(tog) | 2139 UHCI_TD_SET_MAXLEN(0) 2140 ); 2141 std->td.td_buffer = 0; 2142 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2143 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2144 2145 std->link.std = NULL; 2146 if (prev) { 2147 prev->link.std = std; 2148 prev->td.td_link = htole32( 2149 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2150 ); 2151 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2152 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2153 } 2154 tog ^= 1; 2155 } 2156 *lstd = std; 2157 *toggle = tog; 2158 } 2159 2160 void 2161 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2162 { 2163 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2164 upipe->nexttoggle = 0; 2165 } 2166 2167 void 2168 uhci_noop(struct usbd_pipe *pipe) 2169 { 2170 } 2171 2172 int 2173 uhci_device_bulk_init(struct usbd_xfer *xfer) 2174 { 2175 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2176 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2177 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2178 int endpt = ed->bEndpointAddress; 2179 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2180 int len = xfer->ux_bufsize; 2181 int err = 0; 2182 2183 2184 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2185 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, len, xfer->ux_flags, 0); 2186 2187 if (sc->sc_dying) 2188 return USBD_IOERROR; 2189 2190 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2191 2192 uxfer->ux_type = UX_BULK; 2193 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart); 2194 if (err) 2195 return err; 2196 2197 #ifdef UHCI_DEBUG 2198 if (uhcidebug >= 10) { 2199 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2200 uhci_dump_tds(uxfer->ux_stdstart); 2201 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2202 } 2203 #endif 2204 2205 return 0; 2206 } 2207 2208 Static void 2209 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2210 { 2211 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2212 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2213 2214 KASSERT(ux->ux_type == UX_BULK); 2215 2216 if (ux->ux_nstd) { 2217 uhci_free_stds(sc, ux); 2218 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2219 } 2220 } 2221 2222 usbd_status 2223 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2224 { 2225 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2226 usbd_status err; 2227 2228 /* Insert last in queue. */ 2229 mutex_enter(&sc->sc_lock); 2230 err = usb_insert_transfer(xfer); 2231 mutex_exit(&sc->sc_lock); 2232 if (err) 2233 return err; 2234 2235 /* 2236 * Pipe isn't running (otherwise err would be USBD_INPROG), 2237 * so start it first. 2238 */ 2239 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2240 } 2241 2242 usbd_status 2243 uhci_device_bulk_start(struct usbd_xfer *xfer) 2244 { 2245 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2246 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2247 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2248 uhci_soft_td_t *data, *dataend; 2249 uhci_soft_qh_t *sqh; 2250 int len; 2251 int endpt; 2252 int isread; 2253 2254 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2255 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2256 xfer->ux_flags, 0); 2257 2258 if (sc->sc_dying) 2259 return USBD_IOERROR; 2260 2261 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2262 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2263 2264 len = xfer->ux_length; 2265 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2266 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2267 sqh = upipe->bulk.sqh; 2268 2269 /* Take lock here to protect nexttoggle */ 2270 mutex_enter(&sc->sc_lock); 2271 2272 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2273 &dataend); 2274 2275 data = ux->ux_stdstart; 2276 ux->ux_stdend = dataend; 2277 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2278 usb_syncmem(&dataend->dma, 2279 dataend->offs + offsetof(uhci_td_t, td_status), 2280 sizeof(dataend->td.td_status), 2281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2282 2283 #ifdef UHCI_DEBUG 2284 if (uhcidebug >= 10) { 2285 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2286 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2287 uhci_dump_tds(data); 2288 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2289 } 2290 #endif 2291 2292 KASSERT(ux->ux_isdone); 2293 #ifdef DIAGNOSTIC 2294 ux->ux_isdone = false; 2295 #endif 2296 2297 sqh->elink = data; 2298 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2299 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2300 2301 uhci_add_bulk(sc, sqh); 2302 uhci_add_intr_list(sc, ux); 2303 2304 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2305 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2306 uhci_timeout, xfer); 2307 } 2308 xfer->ux_status = USBD_IN_PROGRESS; 2309 mutex_exit(&sc->sc_lock); 2310 2311 return USBD_IN_PROGRESS; 2312 } 2313 2314 /* Abort a device bulk request. */ 2315 void 2316 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2317 { 2318 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2319 2320 KASSERT(mutex_owned(&sc->sc_lock)); 2321 2322 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2323 2324 uhci_abort_xfer(xfer, USBD_CANCELLED); 2325 } 2326 2327 /* 2328 * Abort a device request. 2329 * If this routine is called at splusb() it guarantees that the request 2330 * will be removed from the hardware scheduling and that the callback 2331 * for it will be called with USBD_CANCELLED status. 2332 * It's impossible to guarantee that the requested transfer will not 2333 * have happened since the hardware runs concurrently. 2334 * If the transaction has already happened we rely on the ordinary 2335 * interrupt processing to process it. 2336 * XXX This is most probably wrong. 2337 * XXXMRG this doesn't make sense anymore. 2338 */ 2339 void 2340 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2341 { 2342 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2343 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2344 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2345 uhci_soft_td_t *std; 2346 int wake; 2347 2348 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2349 DPRINTFN(1,"xfer=%p, status=%d", xfer, status, 0, 0); 2350 2351 KASSERT(mutex_owned(&sc->sc_lock)); 2352 ASSERT_SLEEPABLE(); 2353 2354 if (sc->sc_dying) { 2355 /* If we're dying, just do the software part. */ 2356 xfer->ux_status = status; /* make software ignore it */ 2357 callout_stop(&xfer->ux_callout); 2358 usb_transfer_complete(xfer); 2359 return; 2360 } 2361 2362 /* 2363 * If an abort is already in progress then just wait for it to 2364 * complete and return. 2365 */ 2366 if (xfer->ux_hcflags & UXFER_ABORTING) { 2367 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2368 #ifdef DIAGNOSTIC 2369 if (status == USBD_TIMEOUT) 2370 printf("%s: TIMEOUT while aborting\n", __func__); 2371 #endif 2372 /* Override the status which might be USBD_TIMEOUT. */ 2373 xfer->ux_status = status; 2374 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2375 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2376 while (xfer->ux_hcflags & UXFER_ABORTING) 2377 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2378 goto done; 2379 } 2380 xfer->ux_hcflags |= UXFER_ABORTING; 2381 2382 /* 2383 * Step 1: Make interrupt routine and hardware ignore xfer. 2384 */ 2385 xfer->ux_status = status; /* make software ignore it */ 2386 callout_stop(&xfer->ux_callout); 2387 uhci_del_intr_list(sc, ux); 2388 2389 DPRINTF("stop ux=%p", ux, 0, 0, 0); 2390 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2391 usb_syncmem(&std->dma, 2392 std->offs + offsetof(uhci_td_t, td_status), 2393 sizeof(std->td.td_status), 2394 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2395 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2396 usb_syncmem(&std->dma, 2397 std->offs + offsetof(uhci_td_t, td_status), 2398 sizeof(std->td.td_status), 2399 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2400 } 2401 2402 /* 2403 * Step 2: Wait until we know hardware has finished any possible 2404 * use of the xfer. Also make sure the soft interrupt routine 2405 * has run. 2406 */ 2407 /* Hardware finishes in 1ms */ 2408 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2409 sc->sc_softwake = 1; 2410 usb_schedsoftintr(&sc->sc_bus); 2411 DPRINTF("cv_wait", 0, 0, 0, 0); 2412 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2413 2414 /* 2415 * Step 3: Execute callback. 2416 */ 2417 DPRINTF("callback", 0, 0, 0, 0); 2418 #ifdef DIAGNOSTIC 2419 ux->ux_isdone = true; 2420 #endif 2421 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2422 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2423 usb_transfer_complete(xfer); 2424 if (wake) 2425 cv_broadcast(&xfer->ux_hccv); 2426 done: 2427 KASSERT(mutex_owned(&sc->sc_lock)); 2428 } 2429 2430 /* Close a device bulk pipe. */ 2431 void 2432 uhci_device_bulk_close(struct usbd_pipe *pipe) 2433 { 2434 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2435 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2436 2437 KASSERT(mutex_owned(&sc->sc_lock)); 2438 2439 uhci_free_sqh(sc, upipe->bulk.sqh); 2440 2441 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2442 } 2443 2444 int 2445 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2446 { 2447 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2448 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2449 usb_device_request_t *req = &xfer->ux_request; 2450 struct usbd_device *dev = upipe->pipe.up_dev; 2451 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2452 uhci_soft_td_t *data = NULL; 2453 int len; 2454 usbd_status err; 2455 int isread; 2456 2457 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2458 DPRINTFN(3, "xfer=%p len=%d, addr=%d, endpt=%d", xfer, xfer->ux_bufsize, 2459 dev->ud_addr, upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2460 2461 isread = req->bmRequestType & UT_READ; 2462 len = xfer->ux_bufsize; 2463 2464 uxfer->ux_type = UX_CTRL; 2465 /* Set up data transaction */ 2466 if (len != 0) { 2467 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data); 2468 if (err) 2469 return err; 2470 } 2471 /* Set up interrupt info. */ 2472 uxfer->ux_setup = upipe->ctrl.setup; 2473 uxfer->ux_stat = upipe->ctrl.stat; 2474 uxfer->ux_data = data; 2475 2476 return 0; 2477 } 2478 2479 Static void 2480 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2481 { 2482 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2483 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2484 2485 KASSERT(ux->ux_type == UX_CTRL); 2486 2487 if (ux->ux_nstd) { 2488 uhci_free_stds(sc, ux); 2489 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2490 } 2491 } 2492 2493 usbd_status 2494 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2495 { 2496 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2497 usbd_status err; 2498 2499 /* Insert last in queue. */ 2500 mutex_enter(&sc->sc_lock); 2501 err = usb_insert_transfer(xfer); 2502 mutex_exit(&sc->sc_lock); 2503 if (err) 2504 return err; 2505 2506 /* 2507 * Pipe isn't running (otherwise err would be USBD_INPROG), 2508 * so start it first. 2509 */ 2510 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2511 } 2512 2513 usbd_status 2514 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2515 { 2516 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2517 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2518 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2519 usb_device_request_t *req = &xfer->ux_request; 2520 struct usbd_device *dev = upipe->pipe.up_dev; 2521 int addr = dev->ud_addr; 2522 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2523 uhci_soft_td_t *setup, *stat, *next, *dataend; 2524 uhci_soft_qh_t *sqh; 2525 int len; 2526 int isread; 2527 2528 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2529 2530 if (sc->sc_dying) 2531 return USBD_IOERROR; 2532 2533 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2534 2535 DPRINTFN(3, "type=0x%02x, request=0x%02x, " 2536 "wValue=0x%04x, wIndex=0x%04x", 2537 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2538 UGETW(req->wIndex)); 2539 DPRINTFN(3, "len=%d, addr=%d, endpt=%d", 2540 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2541 2542 isread = req->bmRequestType & UT_READ; 2543 len = UGETW(req->wLength); 2544 2545 setup = upipe->ctrl.setup; 2546 stat = upipe->ctrl.stat; 2547 sqh = upipe->ctrl.sqh; 2548 2549 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2550 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2551 2552 mutex_enter(&sc->sc_lock); 2553 2554 /* Set up data transaction */ 2555 if (len != 0) { 2556 upipe->nexttoggle = 1; 2557 next = uxfer->ux_data; 2558 uhci_reset_std_chain(sc, xfer, len, isread, 2559 &upipe->nexttoggle, &dataend); 2560 dataend->link.std = stat; 2561 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2562 usb_syncmem(&dataend->dma, 2563 dataend->offs + offsetof(uhci_td_t, td_link), 2564 sizeof(dataend->td.td_link), 2565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2566 } else { 2567 next = stat; 2568 } 2569 2570 const uint32_t status = UHCI_TD_ZERO_ACTLEN( 2571 UHCI_TD_SET_ERRCNT(3) | 2572 UHCI_TD_ACTIVE | 2573 (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0) 2574 ); 2575 setup->link.std = next; 2576 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2577 setup->td.td_status = htole32(status); 2578 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2579 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2580 2581 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2582 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2583 2584 stat->link.std = NULL; 2585 stat->td.td_link = htole32(UHCI_PTR_T); 2586 stat->td.td_status = htole32(status | UHCI_TD_IOC); 2587 stat->td.td_token = 2588 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2589 UHCI_TD_IN (0, endpt, addr, 1)); 2590 stat->td.td_buffer = htole32(0); 2591 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2593 2594 #ifdef UHCI_DEBUG 2595 if (uhcidebug >= 10) { 2596 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2597 DPRINTF("before transfer", 0, 0, 0, 0); 2598 uhci_dump_tds(setup); 2599 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2600 } 2601 #endif 2602 2603 /* Set up interrupt info. */ 2604 uxfer->ux_setup = setup; 2605 uxfer->ux_stat = stat; 2606 KASSERT(uxfer->ux_isdone); 2607 #ifdef DIAGNOSTIC 2608 uxfer->ux_isdone = false; 2609 #endif 2610 2611 sqh->elink = setup; 2612 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2613 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2614 2615 if (dev->ud_speed == USB_SPEED_LOW) 2616 uhci_add_ls_ctrl(sc, sqh); 2617 else 2618 uhci_add_hs_ctrl(sc, sqh); 2619 uhci_add_intr_list(sc, uxfer); 2620 #ifdef UHCI_DEBUG 2621 if (uhcidebug >= 12) { 2622 uhci_soft_td_t *std; 2623 uhci_soft_qh_t *xqh; 2624 uhci_soft_qh_t *sxqh; 2625 int maxqh = 0; 2626 uhci_physaddr_t link; 2627 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2628 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2629 for (std = sc->sc_vframes[0].htd, link = 0; 2630 (link & UHCI_PTR_QH) == 0; 2631 std = std->link.std) { 2632 link = le32toh(std->td.td_link); 2633 uhci_dump_td(std); 2634 } 2635 sxqh = (uhci_soft_qh_t *)std; 2636 uhci_dump_qh(sxqh); 2637 for (xqh = sxqh; 2638 xqh != NULL; 2639 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2640 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2641 uhci_dump_qh(xqh); 2642 } 2643 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2644 uhci_dump_qh(sqh); 2645 uhci_dump_tds(sqh->elink); 2646 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2647 } 2648 #endif 2649 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2650 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2651 uhci_timeout, xfer); 2652 } 2653 xfer->ux_status = USBD_IN_PROGRESS; 2654 mutex_exit(&sc->sc_lock); 2655 2656 return USBD_IN_PROGRESS; 2657 } 2658 2659 int 2660 uhci_device_intr_init(struct usbd_xfer *xfer) 2661 { 2662 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2663 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2664 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2665 int endpt = ed->bEndpointAddress; 2666 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2667 int len = xfer->ux_bufsize; 2668 int err; 2669 2670 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2671 2672 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2673 xfer->ux_flags, 0); 2674 2675 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2676 KASSERT(len != 0); 2677 2678 ux->ux_type = UX_INTR; 2679 ux->ux_nstd = 0; 2680 err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart); 2681 2682 return err; 2683 } 2684 2685 Static void 2686 uhci_device_intr_fini(struct usbd_xfer *xfer) 2687 { 2688 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2689 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2690 2691 KASSERT(ux->ux_type == UX_INTR); 2692 2693 if (ux->ux_nstd) { 2694 uhci_free_stds(sc, ux); 2695 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2696 } 2697 } 2698 2699 usbd_status 2700 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2701 { 2702 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2703 usbd_status err; 2704 2705 /* Insert last in queue. */ 2706 mutex_enter(&sc->sc_lock); 2707 err = usb_insert_transfer(xfer); 2708 mutex_exit(&sc->sc_lock); 2709 if (err) 2710 return err; 2711 2712 /* 2713 * Pipe isn't running (otherwise err would be USBD_INPROG), 2714 * so start it first. 2715 */ 2716 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2717 } 2718 2719 usbd_status 2720 uhci_device_intr_start(struct usbd_xfer *xfer) 2721 { 2722 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2723 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2724 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2725 uhci_soft_td_t *data, *dataend; 2726 uhci_soft_qh_t *sqh; 2727 int isread, endpt; 2728 int i; 2729 2730 if (sc->sc_dying) 2731 return USBD_IOERROR; 2732 2733 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2734 2735 DPRINTFN(3, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 2736 xfer->ux_flags, 0); 2737 2738 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2739 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2740 2741 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2742 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2743 2744 data = ux->ux_stdstart; 2745 2746 KASSERT(ux->ux_isdone); 2747 #ifdef DIAGNOSTIC 2748 ux->ux_isdone = false; 2749 #endif 2750 2751 /* Take lock to protect nexttoggle */ 2752 mutex_enter(&sc->sc_lock); 2753 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2754 &upipe->nexttoggle, &dataend); 2755 2756 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2757 usb_syncmem(&dataend->dma, 2758 dataend->offs + offsetof(uhci_td_t, td_status), 2759 sizeof(dataend->td.td_status), 2760 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2761 ux->ux_stdend = dataend; 2762 2763 #ifdef UHCI_DEBUG 2764 if (uhcidebug >= 10) { 2765 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2766 uhci_dump_tds(data); 2767 uhci_dump_qh(upipe->intr.qhs[0]); 2768 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2769 } 2770 #endif 2771 2772 DPRINTFN(10, "qhs[0]=%p", upipe->intr.qhs[0], 0, 0, 0); 2773 for (i = 0; i < upipe->intr.npoll; i++) { 2774 sqh = upipe->intr.qhs[i]; 2775 sqh->elink = data; 2776 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2777 usb_syncmem(&sqh->dma, 2778 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2779 sizeof(sqh->qh.qh_elink), 2780 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2781 } 2782 uhci_add_intr_list(sc, ux); 2783 xfer->ux_status = USBD_IN_PROGRESS; 2784 mutex_exit(&sc->sc_lock); 2785 2786 #ifdef UHCI_DEBUG 2787 if (uhcidebug >= 10) { 2788 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2789 uhci_dump_tds(data); 2790 uhci_dump_qh(upipe->intr.qhs[0]); 2791 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2792 } 2793 #endif 2794 2795 return USBD_IN_PROGRESS; 2796 } 2797 2798 /* Abort a device control request. */ 2799 void 2800 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2801 { 2802 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2803 2804 KASSERT(mutex_owned(&sc->sc_lock)); 2805 2806 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2807 uhci_abort_xfer(xfer, USBD_CANCELLED); 2808 } 2809 2810 /* Close a device control pipe. */ 2811 void 2812 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2813 { 2814 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2815 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2816 2817 uhci_free_sqh(sc, upipe->ctrl.sqh); 2818 uhci_free_std_locked(sc, upipe->ctrl.setup); 2819 uhci_free_std_locked(sc, upipe->ctrl.stat); 2820 2821 } 2822 2823 /* Abort a device interrupt request. */ 2824 void 2825 uhci_device_intr_abort(struct usbd_xfer *xfer) 2826 { 2827 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2828 2829 KASSERT(mutex_owned(&sc->sc_lock)); 2830 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2831 2832 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2833 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2834 2835 uhci_abort_xfer(xfer, USBD_CANCELLED); 2836 } 2837 2838 /* Close a device interrupt pipe. */ 2839 void 2840 uhci_device_intr_close(struct usbd_pipe *pipe) 2841 { 2842 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2843 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2844 int i, npoll; 2845 2846 KASSERT(mutex_owned(&sc->sc_lock)); 2847 2848 /* Unlink descriptors from controller data structures. */ 2849 npoll = upipe->intr.npoll; 2850 for (i = 0; i < npoll; i++) 2851 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2852 2853 /* 2854 * We now have to wait for any activity on the physical 2855 * descriptors to stop. 2856 */ 2857 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2858 2859 for (i = 0; i < npoll; i++) 2860 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2861 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2862 } 2863 2864 int 2865 uhci_device_isoc_init(struct usbd_xfer *xfer) 2866 { 2867 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2868 2869 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2870 KASSERT(xfer->ux_nframes != 0); 2871 KASSERT(ux->ux_isdone); 2872 2873 ux->ux_type = UX_ISOC; 2874 return 0; 2875 } 2876 2877 Static void 2878 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2879 { 2880 struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer); 2881 2882 KASSERT(ux->ux_type == UX_ISOC); 2883 } 2884 2885 usbd_status 2886 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2887 { 2888 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2889 usbd_status err __diagused; 2890 2891 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2892 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 2893 2894 /* Put it on our queue, */ 2895 mutex_enter(&sc->sc_lock); 2896 err = usb_insert_transfer(xfer); 2897 mutex_exit(&sc->sc_lock); 2898 2899 KASSERT(err == USBD_NORMAL_COMPLETION); 2900 2901 /* insert into schedule, */ 2902 2903 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2904 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2905 struct isoc *isoc = &upipe->isoc; 2906 uhci_soft_td_t *std = NULL; 2907 uint32_t buf, len, status, offs; 2908 int i, next, nframes; 2909 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2910 2911 DPRINTFN(5, "used=%d next=%d xfer=%p nframes=%d", 2912 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 2913 2914 if (sc->sc_dying) 2915 return USBD_IOERROR; 2916 2917 if (xfer->ux_status == USBD_IN_PROGRESS) { 2918 /* This request has already been entered into the frame list */ 2919 printf("%s: xfer=%p in frame list\n", __func__, xfer); 2920 /* XXX */ 2921 } 2922 2923 #ifdef DIAGNOSTIC 2924 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2925 printf("%s: overflow!\n", __func__); 2926 #endif 2927 2928 KASSERT(xfer->ux_nframes != 0); 2929 2930 mutex_enter(&sc->sc_lock); 2931 next = isoc->next; 2932 if (next == -1) { 2933 /* Not in use yet, schedule it a few frames ahead. */ 2934 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2935 DPRINTFN(2, "start next=%d", next, 0, 0, 0); 2936 } 2937 2938 xfer->ux_status = USBD_IN_PROGRESS; 2939 ux->ux_curframe = next; 2940 2941 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2942 offs = 0; 2943 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2944 UHCI_TD_ACTIVE | 2945 UHCI_TD_IOS); 2946 nframes = xfer->ux_nframes; 2947 for (i = 0; i < nframes; i++) { 2948 std = isoc->stds[next]; 2949 if (++next >= UHCI_VFRAMELIST_COUNT) 2950 next = 0; 2951 len = xfer->ux_frlengths[i]; 2952 std->td.td_buffer = htole32(buf); 2953 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2954 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2955 if (i == nframes - 1) 2956 status |= UHCI_TD_IOC; 2957 std->td.td_status = htole32(status); 2958 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2959 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2960 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2961 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2962 #ifdef UHCI_DEBUG 2963 if (uhcidebug >= 5) { 2964 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2965 DPRINTF("TD %d", i, 0, 0, 0); 2966 uhci_dump_td(std); 2967 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2968 } 2969 #endif 2970 buf += len; 2971 offs += len; 2972 } 2973 isoc->next = next; 2974 isoc->inuse += xfer->ux_nframes; 2975 2976 /* Set up interrupt info. */ 2977 ux->ux_stdstart = std; 2978 ux->ux_stdend = std; 2979 2980 KASSERT(ux->ux_isdone); 2981 #ifdef DIAGNOSTIC 2982 ux->ux_isdone = false; 2983 #endif 2984 uhci_add_intr_list(sc, ux); 2985 2986 mutex_exit(&sc->sc_lock); 2987 2988 return USBD_IN_PROGRESS; 2989 } 2990 2991 void 2992 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2993 { 2994 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2995 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2996 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2997 uhci_soft_td_t **stds = upipe->isoc.stds; 2998 uhci_soft_td_t *std; 2999 int i, n, nframes, maxlen, len; 3000 3001 KASSERT(mutex_owned(&sc->sc_lock)); 3002 3003 /* Transfer is already done. */ 3004 if (xfer->ux_status != USBD_NOT_STARTED && 3005 xfer->ux_status != USBD_IN_PROGRESS) { 3006 return; 3007 } 3008 3009 /* Give xfer the requested abort code. */ 3010 xfer->ux_status = USBD_CANCELLED; 3011 3012 /* make hardware ignore it, */ 3013 nframes = xfer->ux_nframes; 3014 n = ux->ux_curframe; 3015 maxlen = 0; 3016 for (i = 0; i < nframes; i++) { 3017 std = stds[n]; 3018 usb_syncmem(&std->dma, 3019 std->offs + offsetof(uhci_td_t, td_status), 3020 sizeof(std->td.td_status), 3021 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3022 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3023 usb_syncmem(&std->dma, 3024 std->offs + offsetof(uhci_td_t, td_status), 3025 sizeof(std->td.td_status), 3026 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3027 usb_syncmem(&std->dma, 3028 std->offs + offsetof(uhci_td_t, td_token), 3029 sizeof(std->td.td_token), 3030 BUS_DMASYNC_POSTWRITE); 3031 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3032 if (len > maxlen) 3033 maxlen = len; 3034 if (++n >= UHCI_VFRAMELIST_COUNT) 3035 n = 0; 3036 } 3037 3038 /* and wait until we are sure the hardware has finished. */ 3039 delay(maxlen); 3040 3041 #ifdef DIAGNOSTIC 3042 ux->ux_isdone = true; 3043 #endif 3044 /* Remove from interrupt list. */ 3045 uhci_del_intr_list(sc, ux); 3046 3047 /* Run callback. */ 3048 usb_transfer_complete(xfer); 3049 3050 KASSERT(mutex_owned(&sc->sc_lock)); 3051 } 3052 3053 void 3054 uhci_device_isoc_close(struct usbd_pipe *pipe) 3055 { 3056 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3057 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3058 uhci_soft_td_t *std, *vstd; 3059 struct isoc *isoc; 3060 int i; 3061 3062 KASSERT(mutex_owned(&sc->sc_lock)); 3063 3064 /* 3065 * Make sure all TDs are marked as inactive. 3066 * Wait for completion. 3067 * Unschedule. 3068 * Deallocate. 3069 */ 3070 isoc = &upipe->isoc; 3071 3072 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3073 std = isoc->stds[i]; 3074 usb_syncmem(&std->dma, 3075 std->offs + offsetof(uhci_td_t, td_status), 3076 sizeof(std->td.td_status), 3077 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3078 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3079 usb_syncmem(&std->dma, 3080 std->offs + offsetof(uhci_td_t, td_status), 3081 sizeof(std->td.td_status), 3082 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3083 } 3084 /* wait for completion */ 3085 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3086 3087 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3088 std = isoc->stds[i]; 3089 for (vstd = sc->sc_vframes[i].htd; 3090 vstd != NULL && vstd->link.std != std; 3091 vstd = vstd->link.std) 3092 ; 3093 if (vstd == NULL) { 3094 /*panic*/ 3095 printf("%s: %p not found\n", __func__, std); 3096 mutex_exit(&sc->sc_lock); 3097 return; 3098 } 3099 vstd->link = std->link; 3100 usb_syncmem(&std->dma, 3101 std->offs + offsetof(uhci_td_t, td_link), 3102 sizeof(std->td.td_link), 3103 BUS_DMASYNC_POSTWRITE); 3104 vstd->td.td_link = std->td.td_link; 3105 usb_syncmem(&vstd->dma, 3106 vstd->offs + offsetof(uhci_td_t, td_link), 3107 sizeof(vstd->td.td_link), 3108 BUS_DMASYNC_PREWRITE); 3109 uhci_free_std_locked(sc, std); 3110 } 3111 3112 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3113 } 3114 3115 usbd_status 3116 uhci_setup_isoc(struct usbd_pipe *pipe) 3117 { 3118 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3119 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3120 int addr = upipe->pipe.up_dev->ud_addr; 3121 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3122 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3123 uhci_soft_td_t *std, *vstd; 3124 uint32_t token; 3125 struct isoc *isoc; 3126 int i; 3127 3128 isoc = &upipe->isoc; 3129 3130 isoc->stds = kmem_alloc( 3131 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3132 if (isoc->stds == NULL) 3133 return USBD_NOMEM; 3134 3135 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3136 UHCI_TD_OUT(0, endpt, addr, 0); 3137 3138 /* Allocate the TDs and mark as inactive; */ 3139 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3140 std = uhci_alloc_std(sc); 3141 if (std == 0) 3142 goto bad; 3143 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3144 std->td.td_token = htole32(token); 3145 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3146 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3147 isoc->stds[i] = std; 3148 } 3149 3150 mutex_enter(&sc->sc_lock); 3151 3152 /* Insert TDs into schedule. */ 3153 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3154 std = isoc->stds[i]; 3155 vstd = sc->sc_vframes[i].htd; 3156 usb_syncmem(&vstd->dma, 3157 vstd->offs + offsetof(uhci_td_t, td_link), 3158 sizeof(vstd->td.td_link), 3159 BUS_DMASYNC_POSTWRITE); 3160 std->link = vstd->link; 3161 std->td.td_link = vstd->td.td_link; 3162 usb_syncmem(&std->dma, 3163 std->offs + offsetof(uhci_td_t, td_link), 3164 sizeof(std->td.td_link), 3165 BUS_DMASYNC_PREWRITE); 3166 vstd->link.std = std; 3167 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3168 usb_syncmem(&vstd->dma, 3169 vstd->offs + offsetof(uhci_td_t, td_link), 3170 sizeof(vstd->td.td_link), 3171 BUS_DMASYNC_PREWRITE); 3172 } 3173 mutex_exit(&sc->sc_lock); 3174 3175 isoc->next = -1; 3176 isoc->inuse = 0; 3177 3178 return USBD_NORMAL_COMPLETION; 3179 3180 bad: 3181 while (--i >= 0) 3182 uhci_free_std(sc, isoc->stds[i]); 3183 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3184 return USBD_NOMEM; 3185 } 3186 3187 void 3188 uhci_device_isoc_done(struct usbd_xfer *xfer) 3189 { 3190 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3191 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3192 int i, offs; 3193 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3194 3195 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3196 DPRINTFN(4, "length=%d, ux_state=0x%08x", 3197 xfer->ux_actlen, xfer->ux_state, 0, 0); 3198 3199 #ifdef DIAGNOSTIC 3200 if (ux->ux_stdend == NULL) { 3201 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3202 #ifdef UHCI_DEBUG 3203 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3204 uhci_dump_ii(ux); 3205 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3206 #endif 3207 return; 3208 } 3209 #endif 3210 3211 /* Turn off the interrupt since it is active even if the TD is not. */ 3212 usb_syncmem(&ux->ux_stdend->dma, 3213 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3214 sizeof(ux->ux_stdend->td.td_status), 3215 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3216 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3217 usb_syncmem(&ux->ux_stdend->dma, 3218 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3219 sizeof(ux->ux_stdend->td.td_status), 3220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3221 3222 offs = 0; 3223 for (i = 0; i < xfer->ux_nframes; i++) { 3224 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3225 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3226 offs += xfer->ux_frlengths[i]; 3227 } 3228 } 3229 3230 void 3231 uhci_device_intr_done(struct usbd_xfer *xfer) 3232 { 3233 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 3234 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3235 uhci_soft_qh_t *sqh; 3236 int i, npoll; 3237 3238 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3239 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3240 3241 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3242 3243 npoll = upipe->intr.npoll; 3244 for (i = 0; i < npoll; i++) { 3245 sqh = upipe->intr.qhs[i]; 3246 sqh->elink = NULL; 3247 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3248 usb_syncmem(&sqh->dma, 3249 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3250 sizeof(sqh->qh.qh_elink), 3251 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3252 } 3253 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3254 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3255 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3256 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3257 } 3258 3259 /* Deallocate request data structures */ 3260 void 3261 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3262 { 3263 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3264 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3265 int len = UGETW(xfer->ux_request.wLength); 3266 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3267 3268 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3269 3270 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3271 3272 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3273 3274 /* XXXNH move to uhci_idone??? */ 3275 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3276 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3277 else 3278 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3279 3280 if (len) { 3281 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3282 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3283 } 3284 usb_syncmem(&upipe->ctrl.reqdma, 0, 3285 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3286 3287 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3288 } 3289 3290 /* Deallocate request data structures */ 3291 void 3292 uhci_device_bulk_done(struct usbd_xfer *xfer) 3293 { 3294 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3295 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3296 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3297 int endpt = ed->bEndpointAddress; 3298 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3299 3300 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3301 DPRINTFN(5, "xfer=%p sc=%p upipe=%p", xfer, sc, upipe, 0); 3302 3303 KASSERT(mutex_owned(&sc->sc_lock)); 3304 3305 uhci_remove_bulk(sc, upipe->bulk.sqh); 3306 3307 if (xfer->ux_length) { 3308 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3309 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3310 } 3311 3312 DPRINTFN(5, "length=%d", xfer->ux_actlen, 0, 0, 0); 3313 } 3314 3315 /* Add interrupt QH, called with vflock. */ 3316 void 3317 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3318 { 3319 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3320 uhci_soft_qh_t *eqh; 3321 3322 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3323 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3324 3325 eqh = vf->eqh; 3326 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3327 sizeof(eqh->qh.qh_hlink), 3328 BUS_DMASYNC_POSTWRITE); 3329 sqh->hlink = eqh->hlink; 3330 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3331 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3332 sizeof(sqh->qh.qh_hlink), 3333 BUS_DMASYNC_PREWRITE); 3334 eqh->hlink = sqh; 3335 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3336 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3337 sizeof(eqh->qh.qh_hlink), 3338 BUS_DMASYNC_PREWRITE); 3339 vf->eqh = sqh; 3340 vf->bandwidth++; 3341 } 3342 3343 /* Remove interrupt QH. */ 3344 void 3345 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3346 { 3347 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3348 uhci_soft_qh_t *pqh; 3349 3350 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3351 DPRINTFN(4, "n=%d sqh=%p", sqh->pos, sqh, 0, 0); 3352 3353 /* See comment in uhci_remove_ctrl() */ 3354 3355 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3356 sizeof(sqh->qh.qh_elink), 3357 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3358 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3359 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3360 usb_syncmem(&sqh->dma, 3361 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3362 sizeof(sqh->qh.qh_elink), 3363 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3364 delay(UHCI_QH_REMOVE_DELAY); 3365 } 3366 3367 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3368 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3369 sizeof(sqh->qh.qh_hlink), 3370 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3371 pqh->hlink = sqh->hlink; 3372 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3373 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3374 sizeof(pqh->qh.qh_hlink), 3375 BUS_DMASYNC_PREWRITE); 3376 delay(UHCI_QH_REMOVE_DELAY); 3377 if (vf->eqh == sqh) 3378 vf->eqh = pqh; 3379 vf->bandwidth--; 3380 } 3381 3382 usbd_status 3383 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3384 { 3385 uhci_soft_qh_t *sqh; 3386 int i, npoll; 3387 u_int bestbw, bw, bestoffs, offs; 3388 3389 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3390 DPRINTFN(2, "pipe=%p", upipe, 0, 0, 0); 3391 if (ival == 0) { 3392 printf("%s: 0 interval\n", __func__); 3393 return USBD_INVAL; 3394 } 3395 3396 if (ival > UHCI_VFRAMELIST_COUNT) 3397 ival = UHCI_VFRAMELIST_COUNT; 3398 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3399 DPRINTF("ival=%d npoll=%d", ival, npoll, 0, 0); 3400 3401 upipe->intr.npoll = npoll; 3402 upipe->intr.qhs = 3403 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3404 3405 /* 3406 * Figure out which offset in the schedule that has most 3407 * bandwidth left over. 3408 */ 3409 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3410 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3411 for (bw = i = 0; i < npoll; i++) 3412 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3413 if (bw < bestbw) { 3414 bestbw = bw; 3415 bestoffs = offs; 3416 } 3417 } 3418 DPRINTF("bw=%d offs=%d", bestbw, bestoffs, 0, 0); 3419 for (i = 0; i < npoll; i++) { 3420 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3421 sqh->elink = NULL; 3422 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3423 usb_syncmem(&sqh->dma, 3424 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3425 sizeof(sqh->qh.qh_elink), 3426 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3427 sqh->pos = MOD(i * ival + bestoffs); 3428 } 3429 #undef MOD 3430 3431 mutex_enter(&sc->sc_lock); 3432 /* Enter QHs into the controller data structures. */ 3433 for (i = 0; i < npoll; i++) 3434 uhci_add_intr(sc, upipe->intr.qhs[i]); 3435 mutex_exit(&sc->sc_lock); 3436 3437 DPRINTFN(5, "returns %p", upipe, 0, 0, 0); 3438 3439 return USBD_NORMAL_COMPLETION; 3440 } 3441 3442 /* Open a new pipe. */ 3443 usbd_status 3444 uhci_open(struct usbd_pipe *pipe) 3445 { 3446 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3447 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3448 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3449 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3450 usbd_status err = USBD_NOMEM; 3451 int ival; 3452 3453 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3454 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", 3455 pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, bus->ub_rhaddr); 3456 3457 if (sc->sc_dying) 3458 return USBD_IOERROR; 3459 3460 upipe->aborting = 0; 3461 /* toggle state needed for bulk endpoints */ 3462 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3463 3464 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3465 switch (ed->bEndpointAddress) { 3466 case USB_CONTROL_ENDPOINT: 3467 pipe->up_methods = &roothub_ctrl_methods; 3468 break; 3469 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3470 pipe->up_methods = &uhci_root_intr_methods; 3471 break; 3472 default: 3473 return USBD_INVAL; 3474 } 3475 } else { 3476 switch (ed->bmAttributes & UE_XFERTYPE) { 3477 case UE_CONTROL: 3478 pipe->up_methods = &uhci_device_ctrl_methods; 3479 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3480 if (upipe->ctrl.sqh == NULL) 3481 goto bad; 3482 upipe->ctrl.setup = uhci_alloc_std(sc); 3483 if (upipe->ctrl.setup == NULL) { 3484 uhci_free_sqh(sc, upipe->ctrl.sqh); 3485 goto bad; 3486 } 3487 upipe->ctrl.stat = uhci_alloc_std(sc); 3488 if (upipe->ctrl.stat == NULL) { 3489 uhci_free_sqh(sc, upipe->ctrl.sqh); 3490 uhci_free_std(sc, upipe->ctrl.setup); 3491 goto bad; 3492 } 3493 err = usb_allocmem(&sc->sc_bus, 3494 sizeof(usb_device_request_t), 3495 0, &upipe->ctrl.reqdma); 3496 if (err) { 3497 uhci_free_sqh(sc, upipe->ctrl.sqh); 3498 uhci_free_std(sc, upipe->ctrl.setup); 3499 uhci_free_std(sc, upipe->ctrl.stat); 3500 goto bad; 3501 } 3502 break; 3503 case UE_INTERRUPT: 3504 pipe->up_methods = &uhci_device_intr_methods; 3505 ival = pipe->up_interval; 3506 if (ival == USBD_DEFAULT_INTERVAL) 3507 ival = ed->bInterval; 3508 return uhci_device_setintr(sc, upipe, ival); 3509 case UE_ISOCHRONOUS: 3510 pipe->up_serialise = false; 3511 pipe->up_methods = &uhci_device_isoc_methods; 3512 return uhci_setup_isoc(pipe); 3513 case UE_BULK: 3514 pipe->up_methods = &uhci_device_bulk_methods; 3515 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3516 if (upipe->bulk.sqh == NULL) 3517 goto bad; 3518 break; 3519 } 3520 } 3521 return USBD_NORMAL_COMPLETION; 3522 3523 bad: 3524 return USBD_NOMEM; 3525 } 3526 3527 /* 3528 * Data structures and routines to emulate the root hub. 3529 */ 3530 /* 3531 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3532 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3533 * should not be used by the USB subsystem. As we cannot issue a 3534 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3535 * will be enabled as part of the reset. 3536 * 3537 * On the VT83C572, the port cannot be successfully enabled until the 3538 * outstanding "port enable change" and "connection status change" 3539 * events have been reset. 3540 */ 3541 Static usbd_status 3542 uhci_portreset(uhci_softc_t *sc, int index) 3543 { 3544 int lim, port, x; 3545 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3546 3547 if (index == 1) 3548 port = UHCI_PORTSC1; 3549 else if (index == 2) 3550 port = UHCI_PORTSC2; 3551 else 3552 return USBD_IOERROR; 3553 3554 x = URWMASK(UREAD2(sc, port)); 3555 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3556 3557 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3558 3559 DPRINTF("uhci port %d reset, status0 = 0x%04x", index, 3560 UREAD2(sc, port), 0, 0); 3561 3562 x = URWMASK(UREAD2(sc, port)); 3563 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3564 3565 delay(100); 3566 3567 DPRINTF("uhci port %d reset, status1 = 0x%04x", index, 3568 UREAD2(sc, port), 0, 0); 3569 3570 x = URWMASK(UREAD2(sc, port)); 3571 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3572 3573 for (lim = 10; --lim > 0;) { 3574 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3575 3576 x = UREAD2(sc, port); 3577 DPRINTF("uhci port %d iteration %u, status = 0x%04x", index, 3578 lim, x, 0); 3579 3580 if (!(x & UHCI_PORTSC_CCS)) { 3581 /* 3582 * No device is connected (or was disconnected 3583 * during reset). Consider the port reset. 3584 * The delay must be long enough to ensure on 3585 * the initial iteration that the device 3586 * connection will have been registered. 50ms 3587 * appears to be sufficient, but 20ms is not. 3588 */ 3589 DPRINTFN(3, "uhci port %d loop %u, device detached", 3590 index, lim, 0, 0); 3591 break; 3592 } 3593 3594 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3595 /* 3596 * Port enabled changed and/or connection 3597 * status changed were set. Reset either or 3598 * both raised flags (by writing a 1 to that 3599 * bit), and wait again for state to settle. 3600 */ 3601 UWRITE2(sc, port, URWMASK(x) | 3602 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3603 continue; 3604 } 3605 3606 if (x & UHCI_PORTSC_PE) 3607 /* Port is enabled */ 3608 break; 3609 3610 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3611 } 3612 3613 DPRINTFN(3, "uhci port %d reset, status2 = 0x%04x", index, 3614 UREAD2(sc, port), 0, 0); 3615 3616 if (lim <= 0) { 3617 DPRINTF("uhci port %d reset timed out", index, 3618 0, 0, 0); 3619 return USBD_TIMEOUT; 3620 } 3621 3622 sc->sc_isreset = 1; 3623 return USBD_NORMAL_COMPLETION; 3624 } 3625 3626 Static int 3627 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3628 void *buf, int buflen) 3629 { 3630 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3631 int port, x; 3632 int status, change, totlen = 0; 3633 uint16_t len, value, index; 3634 usb_port_status_t ps; 3635 usbd_status err; 3636 3637 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3638 3639 if (sc->sc_dying) 3640 return -1; 3641 3642 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, 3643 req->bRequest, 0, 0); 3644 3645 len = UGETW(req->wLength); 3646 value = UGETW(req->wValue); 3647 index = UGETW(req->wIndex); 3648 3649 #define C(x,y) ((x) | ((y) << 8)) 3650 switch (C(req->bRequest, req->bmRequestType)) { 3651 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3652 DPRINTF("wValue=0x%04x", value, 0, 0, 0); 3653 if (len == 0) 3654 break; 3655 switch (value) { 3656 case C(0, UDESC_DEVICE): { 3657 usb_device_descriptor_t devd; 3658 3659 totlen = min(buflen, sizeof(devd)); 3660 memcpy(&devd, buf, totlen); 3661 USETW(devd.idVendor, sc->sc_id_vendor); 3662 memcpy(buf, &devd, totlen); 3663 break; 3664 } 3665 case C(1, UDESC_STRING): 3666 #define sd ((usb_string_descriptor_t *)buf) 3667 /* Vendor */ 3668 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3669 break; 3670 case C(2, UDESC_STRING): 3671 /* Product */ 3672 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3673 break; 3674 #undef sd 3675 default: 3676 /* default from usbroothub */ 3677 return buflen; 3678 } 3679 break; 3680 3681 /* Hub requests */ 3682 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3683 break; 3684 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3685 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 3686 value, 0, 0); 3687 if (index == 1) 3688 port = UHCI_PORTSC1; 3689 else if (index == 2) 3690 port = UHCI_PORTSC2; 3691 else { 3692 return -1; 3693 } 3694 switch(value) { 3695 case UHF_PORT_ENABLE: 3696 x = URWMASK(UREAD2(sc, port)); 3697 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3698 break; 3699 case UHF_PORT_SUSPEND: 3700 x = URWMASK(UREAD2(sc, port)); 3701 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3702 break; 3703 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3704 /* see USB2 spec ch. 7.1.7.7 */ 3705 usb_delay_ms(&sc->sc_bus, 20); 3706 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3707 /* 10ms resume delay must be provided by caller */ 3708 break; 3709 case UHF_PORT_RESET: 3710 x = URWMASK(UREAD2(sc, port)); 3711 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3712 break; 3713 case UHF_C_PORT_CONNECTION: 3714 x = URWMASK(UREAD2(sc, port)); 3715 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3716 break; 3717 case UHF_C_PORT_ENABLE: 3718 x = URWMASK(UREAD2(sc, port)); 3719 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3720 break; 3721 case UHF_C_PORT_OVER_CURRENT: 3722 x = URWMASK(UREAD2(sc, port)); 3723 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3724 break; 3725 case UHF_C_PORT_RESET: 3726 sc->sc_isreset = 0; 3727 break; 3728 case UHF_PORT_CONNECTION: 3729 case UHF_PORT_OVER_CURRENT: 3730 case UHF_PORT_POWER: 3731 case UHF_PORT_LOW_SPEED: 3732 case UHF_C_PORT_SUSPEND: 3733 default: 3734 return -1; 3735 } 3736 break; 3737 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3738 if (index == 1) 3739 port = UHCI_PORTSC1; 3740 else if (index == 2) 3741 port = UHCI_PORTSC2; 3742 else { 3743 return -1; 3744 } 3745 if (len > 0) { 3746 *(uint8_t *)buf = 3747 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3748 totlen = 1; 3749 } 3750 break; 3751 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3752 if (len == 0) 3753 break; 3754 if ((value & 0xff) != 0) { 3755 return -1; 3756 } 3757 usb_hub_descriptor_t hubd; 3758 3759 totlen = min(buflen, sizeof(hubd)); 3760 memcpy(&hubd, buf, totlen); 3761 hubd.bNbrPorts = 2; 3762 memcpy(buf, &hubd, totlen); 3763 break; 3764 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3765 if (len != 4) { 3766 return -1; 3767 } 3768 memset(buf, 0, len); 3769 totlen = len; 3770 break; 3771 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3772 if (index == 1) 3773 port = UHCI_PORTSC1; 3774 else if (index == 2) 3775 port = UHCI_PORTSC2; 3776 else { 3777 return -1; 3778 } 3779 if (len != 4) { 3780 return -1; 3781 } 3782 x = UREAD2(sc, port); 3783 status = change = 0; 3784 if (x & UHCI_PORTSC_CCS) 3785 status |= UPS_CURRENT_CONNECT_STATUS; 3786 if (x & UHCI_PORTSC_CSC) 3787 change |= UPS_C_CONNECT_STATUS; 3788 if (x & UHCI_PORTSC_PE) 3789 status |= UPS_PORT_ENABLED; 3790 if (x & UHCI_PORTSC_POEDC) 3791 change |= UPS_C_PORT_ENABLED; 3792 if (x & UHCI_PORTSC_OCI) 3793 status |= UPS_OVERCURRENT_INDICATOR; 3794 if (x & UHCI_PORTSC_OCIC) 3795 change |= UPS_C_OVERCURRENT_INDICATOR; 3796 if (x & UHCI_PORTSC_SUSP) 3797 status |= UPS_SUSPEND; 3798 if (x & UHCI_PORTSC_LSDA) 3799 status |= UPS_LOW_SPEED; 3800 status |= UPS_PORT_POWER; 3801 if (sc->sc_isreset) 3802 change |= UPS_C_PORT_RESET; 3803 USETW(ps.wPortStatus, status); 3804 USETW(ps.wPortChange, change); 3805 totlen = min(len, sizeof(ps)); 3806 memcpy(buf, &ps, totlen); 3807 break; 3808 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3809 return -1; 3810 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3811 break; 3812 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3813 if (index == 1) 3814 port = UHCI_PORTSC1; 3815 else if (index == 2) 3816 port = UHCI_PORTSC2; 3817 else { 3818 return -1; 3819 } 3820 switch(value) { 3821 case UHF_PORT_ENABLE: 3822 x = URWMASK(UREAD2(sc, port)); 3823 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3824 break; 3825 case UHF_PORT_SUSPEND: 3826 x = URWMASK(UREAD2(sc, port)); 3827 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3828 break; 3829 case UHF_PORT_RESET: 3830 err = uhci_portreset(sc, index); 3831 if (err != USBD_NORMAL_COMPLETION) 3832 return -1; 3833 return 0; 3834 case UHF_PORT_POWER: 3835 /* Pretend we turned on power */ 3836 return 0; 3837 case UHF_C_PORT_CONNECTION: 3838 case UHF_C_PORT_ENABLE: 3839 case UHF_C_PORT_OVER_CURRENT: 3840 case UHF_PORT_CONNECTION: 3841 case UHF_PORT_OVER_CURRENT: 3842 case UHF_PORT_LOW_SPEED: 3843 case UHF_C_PORT_SUSPEND: 3844 case UHF_C_PORT_RESET: 3845 default: 3846 return -1; 3847 } 3848 break; 3849 default: 3850 /* default from usbroothub */ 3851 DPRINTF("returning %d (usbroothub default)", 3852 buflen, 0, 0, 0); 3853 return buflen; 3854 } 3855 3856 DPRINTF("returning %d", totlen, 0, 0, 0); 3857 3858 return totlen; 3859 } 3860 3861 /* Abort a root interrupt request. */ 3862 void 3863 uhci_root_intr_abort(struct usbd_xfer *xfer) 3864 { 3865 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3866 3867 KASSERT(mutex_owned(&sc->sc_lock)); 3868 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3869 3870 callout_stop(&sc->sc_poll_handle); 3871 sc->sc_intr_xfer = NULL; 3872 3873 xfer->ux_status = USBD_CANCELLED; 3874 #ifdef DIAGNOSTIC 3875 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3876 #endif 3877 usb_transfer_complete(xfer); 3878 } 3879 3880 usbd_status 3881 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3882 { 3883 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3884 usbd_status err; 3885 3886 /* Insert last in queue. */ 3887 mutex_enter(&sc->sc_lock); 3888 err = usb_insert_transfer(xfer); 3889 mutex_exit(&sc->sc_lock); 3890 if (err) 3891 return err; 3892 3893 /* 3894 * Pipe isn't running (otherwise err would be USBD_INPROG), 3895 * start first 3896 */ 3897 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3898 } 3899 3900 /* Start a transfer on the root interrupt pipe */ 3901 usbd_status 3902 uhci_root_intr_start(struct usbd_xfer *xfer) 3903 { 3904 struct usbd_pipe *pipe = xfer->ux_pipe; 3905 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3906 unsigned int ival; 3907 3908 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3909 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3910 xfer->ux_flags, 0); 3911 3912 if (sc->sc_dying) 3913 return USBD_IOERROR; 3914 3915 /* XXX temporary variable needed to avoid gcc3 warning */ 3916 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3917 sc->sc_ival = mstohz(ival); 3918 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3919 sc->sc_intr_xfer = xfer; 3920 return USBD_IN_PROGRESS; 3921 } 3922 3923 /* Close the root interrupt pipe. */ 3924 void 3925 uhci_root_intr_close(struct usbd_pipe *pipe) 3926 { 3927 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3928 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3929 3930 KASSERT(mutex_owned(&sc->sc_lock)); 3931 3932 callout_stop(&sc->sc_poll_handle); 3933 sc->sc_intr_xfer = NULL; 3934 } 3935
Indexes created Tue Sep 30 17:09:57 GMT 2025