uhci.c revision 1.275.2.4
1 /* $NetBSD: uhci.c,v 1.275.2.4 2018/08/25 11:29:52 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.275.2.4 2018/08/25 11:29:52 martin Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/device.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/mutex.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/select.h> 62 #include <sys/sysctl.h> 63 #include <sys/systm.h> 64 65 #include <machine/endian.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usb_mem.h> 71 72 #include <dev/usb/uhcireg.h> 73 #include <dev/usb/uhcivar.h> 74 #include <dev/usb/usbroothub.h> 75 #include <dev/usb/usbhist.h> 76 77 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 78 /*#define UHCI_CTL_LOOP */ 79 80 #ifdef UHCI_DEBUG 81 uhci_softc_t *thesc; 82 int uhcinoloop = 0; 83 #endif 84 85 #ifdef USB_DEBUG 86 #ifndef UHCI_DEBUG 87 #define uhcidebug 0 88 #else 89 static int uhcidebug = 0; 90 91 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 92 { 93 int err; 94 const struct sysctlnode *rnode; 95 const struct sysctlnode *cnode; 96 97 err = sysctl_createv(clog, 0, NULL, &rnode, 98 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 99 SYSCTL_DESCR("uhci global controls"), 100 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 101 102 if (err) 103 goto fail; 104 105 /* control debugging printfs */ 106 err = sysctl_createv(clog, 0, &rnode, &cnode, 107 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 108 "debug", SYSCTL_DESCR("Enable debugging output"), 109 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 110 if (err) 111 goto fail; 112 113 return; 114 fail: 115 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 116 } 117 118 #endif /* UHCI_DEBUG */ 119 #endif /* USB_DEBUG */ 120 121 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 122 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 123 #define UHCIHIST_FUNC() USBHIST_FUNC() 124 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 125 126 /* 127 * The UHCI controller is little endian, so on big endian machines 128 * the data stored in memory needs to be swapped. 129 */ 130 131 struct uhci_pipe { 132 struct usbd_pipe pipe; 133 int nexttoggle; 134 135 u_char aborting; 136 struct usbd_xfer *abortstart, abortend; 137 138 /* Info needed for different pipe kinds. */ 139 union { 140 /* Control pipe */ 141 struct { 142 uhci_soft_qh_t *sqh; 143 usb_dma_t reqdma; 144 uhci_soft_td_t *setup; 145 uhci_soft_td_t *stat; 146 } ctrl; 147 /* Interrupt pipe */ 148 struct { 149 int npoll; 150 uhci_soft_qh_t **qhs; 151 } intr; 152 /* Bulk pipe */ 153 struct { 154 uhci_soft_qh_t *sqh; 155 } bulk; 156 /* Isochronous pipe */ 157 struct isoc { 158 uhci_soft_td_t **stds; 159 int next, inuse; 160 } isoc; 161 }; 162 }; 163 164 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 165 166 Static void uhci_globalreset(uhci_softc_t *); 167 Static usbd_status uhci_portreset(uhci_softc_t*, int); 168 Static void uhci_reset(uhci_softc_t *); 169 Static usbd_status uhci_run(uhci_softc_t *, int, int); 170 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 171 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 172 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 173 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 174 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 175 #if 0 176 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 177 uhci_intr_info_t *); 178 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 179 #endif 180 181 #if 0 182 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 183 uhci_soft_td_t *); 184 #endif 185 Static int uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, uhci_soft_td_t **); 187 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 188 189 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 190 int, int, int *, uhci_soft_td_t **); 191 192 Static void uhci_poll_hub(void *); 193 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 194 ux_completeq_t *); 195 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 196 197 Static void uhci_abort_xfer(struct usbd_xfer *, usbd_status); 198 199 Static void uhci_timeout(void *); 200 Static void uhci_timeout_task(void *); 201 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 202 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 203 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 204 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 205 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 206 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 207 Static void uhci_add_loop(uhci_softc_t *); 208 Static void uhci_rem_loop(uhci_softc_t *); 209 210 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 211 212 Static struct usbd_xfer * 213 uhci_allocx(struct usbd_bus *, unsigned int); 214 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 215 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 216 Static int uhci_roothub_ctrl(struct usbd_bus *, 217 usb_device_request_t *, void *, int); 218 219 Static int uhci_device_ctrl_init(struct usbd_xfer *); 220 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 221 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 222 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 223 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 224 Static void uhci_device_ctrl_close(struct usbd_pipe *); 225 Static void uhci_device_ctrl_done(struct usbd_xfer *); 226 227 Static int uhci_device_intr_init(struct usbd_xfer *); 228 Static void uhci_device_intr_fini(struct usbd_xfer *); 229 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 230 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 231 Static void uhci_device_intr_abort(struct usbd_xfer *); 232 Static void uhci_device_intr_close(struct usbd_pipe *); 233 Static void uhci_device_intr_done(struct usbd_xfer *); 234 235 Static int uhci_device_bulk_init(struct usbd_xfer *); 236 Static void uhci_device_bulk_fini(struct usbd_xfer *); 237 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 238 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 239 Static void uhci_device_bulk_abort(struct usbd_xfer *); 240 Static void uhci_device_bulk_close(struct usbd_pipe *); 241 Static void uhci_device_bulk_done(struct usbd_xfer *); 242 243 Static int uhci_device_isoc_init(struct usbd_xfer *); 244 Static void uhci_device_isoc_fini(struct usbd_xfer *); 245 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 246 Static void uhci_device_isoc_abort(struct usbd_xfer *); 247 Static void uhci_device_isoc_close(struct usbd_pipe *); 248 Static void uhci_device_isoc_done(struct usbd_xfer *); 249 250 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 251 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 252 Static void uhci_root_intr_abort(struct usbd_xfer *); 253 Static void uhci_root_intr_close(struct usbd_pipe *); 254 Static void uhci_root_intr_done(struct usbd_xfer *); 255 256 Static usbd_status uhci_open(struct usbd_pipe *); 257 Static void uhci_poll(struct usbd_bus *); 258 Static void uhci_softintr(void *); 259 260 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 261 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 262 Static usbd_status uhci_device_setintr(uhci_softc_t *, 263 struct uhci_pipe *, int); 264 265 Static void uhci_device_clear_toggle(struct usbd_pipe *); 266 Static void uhci_noop(struct usbd_pipe *); 267 268 static inline uhci_soft_qh_t * 269 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 270 271 #ifdef UHCI_DEBUG 272 Static void uhci_dump_all(uhci_softc_t *); 273 Static void uhci_dumpregs(uhci_softc_t *); 274 Static void uhci_dump_qhs(uhci_soft_qh_t *); 275 Static void uhci_dump_qh(uhci_soft_qh_t *); 276 Static void uhci_dump_tds(uhci_soft_td_t *); 277 Static void uhci_dump_td(uhci_soft_td_t *); 278 Static void uhci_dump_ii(struct uhci_xfer *); 279 void uhci_dump(void); 280 #endif 281 282 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 283 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 284 #define UWRITE1(sc, r, x) \ 285 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 286 } while (/*CONSTCOND*/0) 287 #define UWRITE2(sc, r, x) \ 288 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 289 } while (/*CONSTCOND*/0) 290 #define UWRITE4(sc, r, x) \ 291 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 292 } while (/*CONSTCOND*/0) 293 294 static __inline uint8_t 295 UREAD1(uhci_softc_t *sc, bus_size_t r) 296 { 297 298 UBARR(sc); 299 return bus_space_read_1(sc->iot, sc->ioh, r); 300 } 301 302 static __inline uint16_t 303 UREAD2(uhci_softc_t *sc, bus_size_t r) 304 { 305 306 UBARR(sc); 307 return bus_space_read_2(sc->iot, sc->ioh, r); 308 } 309 310 #ifdef UHCI_DEBUG 311 static __inline uint32_t 312 UREAD4(uhci_softc_t *sc, bus_size_t r) 313 { 314 315 UBARR(sc); 316 return bus_space_read_4(sc->iot, sc->ioh, r); 317 } 318 #endif 319 320 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 321 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 322 323 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 324 325 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 326 327 const struct usbd_bus_methods uhci_bus_methods = { 328 .ubm_open = uhci_open, 329 .ubm_softint = uhci_softintr, 330 .ubm_dopoll = uhci_poll, 331 .ubm_allocx = uhci_allocx, 332 .ubm_freex = uhci_freex, 333 .ubm_getlock = uhci_get_lock, 334 .ubm_rhctrl = uhci_roothub_ctrl, 335 }; 336 337 const struct usbd_pipe_methods uhci_root_intr_methods = { 338 .upm_transfer = uhci_root_intr_transfer, 339 .upm_start = uhci_root_intr_start, 340 .upm_abort = uhci_root_intr_abort, 341 .upm_close = uhci_root_intr_close, 342 .upm_cleartoggle = uhci_noop, 343 .upm_done = uhci_root_intr_done, 344 }; 345 346 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 347 .upm_init = uhci_device_ctrl_init, 348 .upm_fini = uhci_device_ctrl_fini, 349 .upm_transfer = uhci_device_ctrl_transfer, 350 .upm_start = uhci_device_ctrl_start, 351 .upm_abort = uhci_device_ctrl_abort, 352 .upm_close = uhci_device_ctrl_close, 353 .upm_cleartoggle = uhci_noop, 354 .upm_done = uhci_device_ctrl_done, 355 }; 356 357 const struct usbd_pipe_methods uhci_device_intr_methods = { 358 .upm_init = uhci_device_intr_init, 359 .upm_fini = uhci_device_intr_fini, 360 .upm_transfer = uhci_device_intr_transfer, 361 .upm_start = uhci_device_intr_start, 362 .upm_abort = uhci_device_intr_abort, 363 .upm_close = uhci_device_intr_close, 364 .upm_cleartoggle = uhci_device_clear_toggle, 365 .upm_done = uhci_device_intr_done, 366 }; 367 368 const struct usbd_pipe_methods uhci_device_bulk_methods = { 369 .upm_init = uhci_device_bulk_init, 370 .upm_fini = uhci_device_bulk_fini, 371 .upm_transfer = uhci_device_bulk_transfer, 372 .upm_start = uhci_device_bulk_start, 373 .upm_abort = uhci_device_bulk_abort, 374 .upm_close = uhci_device_bulk_close, 375 .upm_cleartoggle = uhci_device_clear_toggle, 376 .upm_done = uhci_device_bulk_done, 377 }; 378 379 const struct usbd_pipe_methods uhci_device_isoc_methods = { 380 .upm_init = uhci_device_isoc_init, 381 .upm_fini = uhci_device_isoc_fini, 382 .upm_transfer = uhci_device_isoc_transfer, 383 .upm_abort = uhci_device_isoc_abort, 384 .upm_close = uhci_device_isoc_close, 385 .upm_cleartoggle = uhci_noop, 386 .upm_done = uhci_device_isoc_done, 387 }; 388 389 static inline void 390 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 391 { 392 393 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 394 } 395 396 static inline void 397 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 398 { 399 400 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 401 } 402 403 static inline uhci_soft_qh_t * 404 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 405 { 406 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 407 DPRINTFN(15, "pqh=%#jx sqh=%#jx", (uintptr_t)pqh, (uintptr_t)sqh, 0, 0); 408 409 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 410 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 411 usb_syncmem(&pqh->dma, 412 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 413 sizeof(pqh->qh.qh_hlink), 414 BUS_DMASYNC_POSTWRITE); 415 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 416 printf("%s: QH not found\n", __func__); 417 return NULL; 418 } 419 #endif 420 } 421 return pqh; 422 } 423 424 void 425 uhci_globalreset(uhci_softc_t *sc) 426 { 427 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 428 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 429 UHCICMD(sc, 0); /* do nothing */ 430 } 431 432 int 433 uhci_init(uhci_softc_t *sc) 434 { 435 usbd_status err; 436 int i, j; 437 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 438 uhci_soft_td_t *std; 439 440 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 441 442 #ifdef UHCI_DEBUG 443 thesc = sc; 444 445 if (uhcidebug >= 2) 446 uhci_dumpregs(sc); 447 #endif 448 449 sc->sc_suspend = PWR_RESUME; 450 451 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 452 uhci_globalreset(sc); /* reset the controller */ 453 uhci_reset(sc); 454 455 /* Allocate and initialize real frame array. */ 456 err = usb_allocmem(&sc->sc_bus, 457 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 458 UHCI_FRAMELIST_ALIGN, &sc->sc_dma); 459 if (err) 460 return err; 461 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 462 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 463 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); /* set frame list*/ 464 465 /* Initialise mutex early for uhci_alloc_* */ 466 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 467 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 468 469 /* 470 * Allocate a TD, inactive, that hangs from the last QH. 471 * This is to avoid a bug in the PIIX that makes it run berserk 472 * otherwise. 473 */ 474 std = uhci_alloc_std(sc); 475 if (std == NULL) 476 return ENOMEM; 477 std->link.std = NULL; 478 std->td.td_link = htole32(UHCI_PTR_T); 479 std->td.td_status = htole32(0); /* inactive */ 480 std->td.td_token = htole32(0); 481 std->td.td_buffer = htole32(0); 482 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 484 485 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 486 lsqh = uhci_alloc_sqh(sc); 487 if (lsqh == NULL) 488 goto fail1; 489 lsqh->hlink = NULL; 490 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 491 lsqh->elink = std; 492 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 493 sc->sc_last_qh = lsqh; 494 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 495 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 496 497 /* Allocate the dummy QH where bulk traffic will be queued. */ 498 bsqh = uhci_alloc_sqh(sc); 499 if (bsqh == NULL) 500 goto fail2; 501 bsqh->hlink = lsqh; 502 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 503 bsqh->elink = NULL; 504 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 505 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 506 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 507 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 508 509 /* Allocate dummy QH where high speed control traffic will be queued. */ 510 chsqh = uhci_alloc_sqh(sc); 511 if (chsqh == NULL) 512 goto fail3; 513 chsqh->hlink = bsqh; 514 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 515 chsqh->elink = NULL; 516 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 517 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 518 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 521 /* Allocate dummy QH where control traffic will be queued. */ 522 clsqh = uhci_alloc_sqh(sc); 523 if (clsqh == NULL) 524 goto fail4; 525 clsqh->hlink = chsqh; 526 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 527 clsqh->elink = NULL; 528 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 529 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 530 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 533 /* 534 * Make all (virtual) frame list pointers point to the interrupt 535 * queue heads and the interrupt queue heads at the control 536 * queue head and point the physical frame list to the virtual. 537 */ 538 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 539 std = uhci_alloc_std(sc); 540 sqh = uhci_alloc_sqh(sc); 541 if (std == NULL || sqh == NULL) 542 return USBD_NOMEM; 543 std->link.sqh = sqh; 544 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 545 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 546 std->td.td_token = htole32(0); 547 std->td.td_buffer = htole32(0); 548 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 549 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 550 sqh->hlink = clsqh; 551 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 552 sqh->elink = NULL; 553 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 554 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 556 sc->sc_vframes[i].htd = std; 557 sc->sc_vframes[i].etd = std; 558 sc->sc_vframes[i].hqh = sqh; 559 sc->sc_vframes[i].eqh = sqh; 560 for (j = i; 561 j < UHCI_FRAMELIST_COUNT; 562 j += UHCI_VFRAMELIST_COUNT) 563 sc->sc_pframes[j] = htole32(std->physaddr); 564 } 565 usb_syncmem(&sc->sc_dma, 0, 566 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 567 BUS_DMASYNC_PREWRITE); 568 569 570 TAILQ_INIT(&sc->sc_intrhead); 571 572 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 573 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 574 575 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 576 577 /* Set up the bus struct. */ 578 sc->sc_bus.ub_methods = &uhci_bus_methods; 579 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 580 sc->sc_bus.ub_usedma = true; 581 582 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 583 584 DPRINTF("Enabling...", 0, 0, 0, 0); 585 586 err = uhci_run(sc, 1, 0); /* and here we go... */ 587 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 588 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 589 return err; 590 591 fail4: 592 uhci_free_sqh(sc, chsqh); 593 fail3: 594 uhci_free_sqh(sc, lsqh); 595 fail2: 596 uhci_free_sqh(sc, lsqh); 597 fail1: 598 uhci_free_std(sc, std); 599 600 return ENOMEM; 601 } 602 603 int 604 uhci_activate(device_t self, enum devact act) 605 { 606 struct uhci_softc *sc = device_private(self); 607 608 switch (act) { 609 case DVACT_DEACTIVATE: 610 sc->sc_dying = 1; 611 return 0; 612 default: 613 return EOPNOTSUPP; 614 } 615 } 616 617 void 618 uhci_childdet(device_t self, device_t child) 619 { 620 struct uhci_softc *sc = device_private(self); 621 622 KASSERT(sc->sc_child == child); 623 sc->sc_child = NULL; 624 } 625 626 int 627 uhci_detach(struct uhci_softc *sc, int flags) 628 { 629 int rv = 0; 630 631 if (sc->sc_child != NULL) 632 rv = config_detach(sc->sc_child, flags); 633 634 if (rv != 0) 635 return rv; 636 637 callout_halt(&sc->sc_poll_handle, NULL); 638 callout_destroy(&sc->sc_poll_handle); 639 640 mutex_destroy(&sc->sc_lock); 641 mutex_destroy(&sc->sc_intr_lock); 642 643 pool_cache_destroy(sc->sc_xferpool); 644 645 /* XXX free other data structures XXX */ 646 647 return rv; 648 } 649 650 struct usbd_xfer * 651 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 652 { 653 struct uhci_softc *sc = UHCI_BUS2SC(bus); 654 struct usbd_xfer *xfer; 655 656 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 657 if (xfer != NULL) { 658 memset(xfer, 0, sizeof(struct uhci_xfer)); 659 660 /* Initialise this always so we can call remove on it. */ 661 usb_init_task(&xfer->ux_aborttask, uhci_timeout_task, xfer, 662 USB_TASKQ_MPSAFE); 663 #ifdef DIAGNOSTIC 664 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 665 uxfer->ux_isdone = true; 666 xfer->ux_state = XFER_BUSY; 667 #endif 668 } 669 return xfer; 670 } 671 672 void 673 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 674 { 675 struct uhci_softc *sc = UHCI_BUS2SC(bus); 676 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 677 678 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 679 xfer->ux_state); 680 KASSERTMSG(uxfer->ux_isdone, "xfer %p not done\n", xfer); 681 #ifdef DIAGNOSTIC 682 xfer->ux_state = XFER_FREE; 683 #endif 684 pool_cache_put(sc->sc_xferpool, xfer); 685 } 686 687 Static void 688 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 689 { 690 struct uhci_softc *sc = UHCI_BUS2SC(bus); 691 692 *lock = &sc->sc_lock; 693 } 694 695 696 /* 697 * Handle suspend/resume. 698 * 699 * We need to switch to polling mode here, because this routine is 700 * called from an interrupt context. This is all right since we 701 * are almost suspended anyway. 702 */ 703 bool 704 uhci_resume(device_t dv, const pmf_qual_t *qual) 705 { 706 uhci_softc_t *sc = device_private(dv); 707 int cmd; 708 709 mutex_spin_enter(&sc->sc_intr_lock); 710 711 cmd = UREAD2(sc, UHCI_CMD); 712 sc->sc_bus.ub_usepolling++; 713 UWRITE2(sc, UHCI_INTR, 0); 714 uhci_globalreset(sc); 715 uhci_reset(sc); 716 if (cmd & UHCI_CMD_RS) 717 uhci_run(sc, 0, 1); 718 719 /* restore saved state */ 720 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 721 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 722 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 723 724 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 725 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 726 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 727 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 728 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 729 UHCICMD(sc, UHCI_CMD_MAXP); 730 uhci_run(sc, 1, 1); /* and start traffic again */ 731 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 732 sc->sc_bus.ub_usepolling--; 733 if (sc->sc_intr_xfer != NULL) 734 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, 735 sc->sc_intr_xfer); 736 #ifdef UHCI_DEBUG 737 if (uhcidebug >= 2) 738 uhci_dumpregs(sc); 739 #endif 740 741 sc->sc_suspend = PWR_RESUME; 742 mutex_spin_exit(&sc->sc_intr_lock); 743 744 return true; 745 } 746 747 bool 748 uhci_suspend(device_t dv, const pmf_qual_t *qual) 749 { 750 uhci_softc_t *sc = device_private(dv); 751 int cmd; 752 753 mutex_spin_enter(&sc->sc_intr_lock); 754 755 cmd = UREAD2(sc, UHCI_CMD); 756 757 #ifdef UHCI_DEBUG 758 if (uhcidebug >= 2) 759 uhci_dumpregs(sc); 760 #endif 761 if (sc->sc_intr_xfer != NULL) 762 callout_stop(&sc->sc_poll_handle); 763 sc->sc_suspend = PWR_SUSPEND; 764 sc->sc_bus.ub_usepolling++; 765 766 uhci_run(sc, 0, 1); /* stop the controller */ 767 cmd &= ~UHCI_CMD_RS; 768 769 /* save some state if BIOS doesn't */ 770 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 771 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 772 773 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 774 775 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 776 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 777 sc->sc_bus.ub_usepolling--; 778 779 mutex_spin_exit(&sc->sc_intr_lock); 780 781 return true; 782 } 783 784 #ifdef UHCI_DEBUG 785 Static void 786 uhci_dumpregs(uhci_softc_t *sc) 787 { 788 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 789 DPRINTF("cmd =%04jx sts =%04jx intr =%04jx frnum =%04jx", 790 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 791 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 792 DPRINTF("sof =%04jx portsc1=%04jx portsc2=%04jx flbase=%08jx", 793 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 794 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 795 } 796 797 void 798 uhci_dump_td(uhci_soft_td_t *p) 799 { 800 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 801 802 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 803 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 804 805 DPRINTF("TD(%#jx) at 0x%08jx", (uintptr_t)p, p->physaddr, 0, 0); 806 DPRINTF(" link=0x%08jx status=0x%08jx " 807 "token=0x%08x buffer=0x%08x", 808 le32toh(p->td.td_link), 809 le32toh(p->td.td_status), 810 le32toh(p->td.td_token), 811 le32toh(p->td.td_buffer)); 812 813 DPRINTF("bitstuff=%jd crcto =%jd nak =%jd babble =%jd", 814 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 815 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 816 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 817 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 818 DPRINTF("dbuffer =%jd stalled =%jd active =%jd ioc =%jd", 819 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 820 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 821 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 822 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 823 DPRINTF("ios =%jd ls =%jd spd =%jd", 824 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 825 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 826 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 827 DPRINTF("errcnt =%d actlen =%d pid=%02x", 828 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 829 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 830 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 831 DPRINTF("addr=%jd endpt=%jd D=%jd maxlen=%jd,", 832 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 833 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 834 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 835 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 836 } 837 838 void 839 uhci_dump_qh(uhci_soft_qh_t *sqh) 840 { 841 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 842 843 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 844 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 845 846 DPRINTF("QH(%#jx) at 0x%08jx: hlink=%08jx elink=%08jx", (uintptr_t)sqh, 847 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 848 le32toh(sqh->qh.qh_elink)); 849 850 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 851 } 852 853 854 #if 1 855 void 856 uhci_dump(void) 857 { 858 uhci_dump_all(thesc); 859 } 860 #endif 861 862 void 863 uhci_dump_all(uhci_softc_t *sc) 864 { 865 uhci_dumpregs(sc); 866 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 867 uhci_dump_qhs(sc->sc_lctl_start); 868 } 869 870 871 void 872 uhci_dump_qhs(uhci_soft_qh_t *sqh) 873 { 874 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 875 876 uhci_dump_qh(sqh); 877 878 /* 879 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 880 * Traverses sideways first, then down. 881 * 882 * QH1 883 * QH2 884 * No QH 885 * TD2.1 886 * TD2.2 887 * TD1.1 888 * etc. 889 * 890 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 891 */ 892 893 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 894 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 895 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 896 uhci_dump_qhs(sqh->hlink); 897 else 898 DPRINTF("No QH", 0, 0, 0, 0); 899 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 900 901 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 902 uhci_dump_tds(sqh->elink); 903 else 904 DPRINTF("No QH", 0, 0, 0, 0); 905 } 906 907 void 908 uhci_dump_tds(uhci_soft_td_t *std) 909 { 910 uhci_soft_td_t *td; 911 int stop; 912 913 for (td = std; td != NULL; td = td->link.std) { 914 uhci_dump_td(td); 915 916 /* 917 * Check whether the link pointer in this TD marks 918 * the link pointer as end of queue. This avoids 919 * printing the free list in case the queue/TD has 920 * already been moved there (seatbelt). 921 */ 922 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 923 sizeof(td->td.td_link), 924 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 925 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 926 le32toh(td->td.td_link) == 0); 927 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 928 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 929 if (stop) 930 break; 931 } 932 } 933 934 Static void 935 uhci_dump_ii(struct uhci_xfer *ux) 936 { 937 struct usbd_pipe *pipe; 938 usb_endpoint_descriptor_t *ed; 939 struct usbd_device *dev; 940 941 if (ux == NULL) { 942 printf("ux NULL\n"); 943 return; 944 } 945 pipe = ux->ux_xfer.ux_pipe; 946 if (pipe == NULL) { 947 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 948 return; 949 } 950 if (pipe->up_endpoint == NULL) { 951 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 952 ux, ux->ux_isdone, pipe); 953 return; 954 } 955 if (pipe->up_dev == NULL) { 956 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 957 ux, ux->ux_isdone, pipe); 958 return; 959 } 960 ed = pipe->up_endpoint->ue_edesc; 961 dev = pipe->up_dev; 962 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 963 ux, ux->ux_isdone, dev, 964 UGETW(dev->ud_ddesc.idVendor), 965 UGETW(dev->ud_ddesc.idProduct), 966 dev->ud_addr, pipe, 967 ed->bEndpointAddress, ed->bmAttributes); 968 } 969 970 void uhci_dump_iis(struct uhci_softc *sc); 971 void 972 uhci_dump_iis(struct uhci_softc *sc) 973 { 974 struct uhci_xfer *ux; 975 976 printf("interrupt list:\n"); 977 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 978 uhci_dump_ii(ux); 979 } 980 981 void iidump(void); 982 void iidump(void) { uhci_dump_iis(thesc); } 983 984 #endif 985 986 /* 987 * This routine is executed periodically and simulates interrupts 988 * from the root controller interrupt pipe for port status change. 989 */ 990 void 991 uhci_poll_hub(void *addr) 992 { 993 struct usbd_xfer *xfer = addr; 994 struct usbd_pipe *pipe = xfer->ux_pipe; 995 uhci_softc_t *sc; 996 u_char *p; 997 998 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 999 1000 if (__predict_false(pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL)) 1001 return; /* device has detached */ 1002 sc = UHCI_PIPE2SC(pipe); 1003 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 1004 1005 p = xfer->ux_buf; 1006 p[0] = 0; 1007 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1008 p[0] |= 1<<1; 1009 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1010 p[0] |= 1<<2; 1011 if (p[0] == 0) 1012 /* No change, try again in a while */ 1013 return; 1014 1015 xfer->ux_actlen = 1; 1016 xfer->ux_status = USBD_NORMAL_COMPLETION; 1017 mutex_enter(&sc->sc_lock); 1018 usb_transfer_complete(xfer); 1019 mutex_exit(&sc->sc_lock); 1020 } 1021 1022 void 1023 uhci_root_intr_done(struct usbd_xfer *xfer) 1024 { 1025 } 1026 1027 /* 1028 * Let the last QH loop back to the high speed control transfer QH. 1029 * This is what intel calls "bandwidth reclamation" and improves 1030 * USB performance a lot for some devices. 1031 * If we are already looping, just count it. 1032 */ 1033 void 1034 uhci_add_loop(uhci_softc_t *sc) 1035 { 1036 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1037 1038 #ifdef UHCI_DEBUG 1039 if (uhcinoloop) 1040 return; 1041 #endif 1042 if (++sc->sc_loops == 1) { 1043 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1044 /* Note, we don't loop back the soft pointer. */ 1045 sc->sc_last_qh->qh.qh_hlink = 1046 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1047 usb_syncmem(&sc->sc_last_qh->dma, 1048 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1049 sizeof(sc->sc_last_qh->qh.qh_hlink), 1050 BUS_DMASYNC_PREWRITE); 1051 } 1052 } 1053 1054 void 1055 uhci_rem_loop(uhci_softc_t *sc) 1056 { 1057 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1058 1059 #ifdef UHCI_DEBUG 1060 if (uhcinoloop) 1061 return; 1062 #endif 1063 if (--sc->sc_loops == 0) { 1064 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1065 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1066 usb_syncmem(&sc->sc_last_qh->dma, 1067 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1068 sizeof(sc->sc_last_qh->qh.qh_hlink), 1069 BUS_DMASYNC_PREWRITE); 1070 } 1071 } 1072 1073 /* Add high speed control QH, called with lock held. */ 1074 void 1075 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1076 { 1077 uhci_soft_qh_t *eqh; 1078 1079 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1080 1081 KASSERT(mutex_owned(&sc->sc_lock)); 1082 1083 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1084 eqh = sc->sc_hctl_end; 1085 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1086 sizeof(eqh->qh.qh_hlink), 1087 BUS_DMASYNC_POSTWRITE); 1088 sqh->hlink = eqh->hlink; 1089 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1090 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1091 BUS_DMASYNC_PREWRITE); 1092 eqh->hlink = sqh; 1093 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1094 sc->sc_hctl_end = sqh; 1095 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1096 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1097 #ifdef UHCI_CTL_LOOP 1098 uhci_add_loop(sc); 1099 #endif 1100 } 1101 1102 /* Remove high speed control QH, called with lock held. */ 1103 void 1104 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1105 { 1106 uhci_soft_qh_t *pqh; 1107 uint32_t elink; 1108 1109 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1110 1111 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1112 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1113 #ifdef UHCI_CTL_LOOP 1114 uhci_rem_loop(sc); 1115 #endif 1116 /* 1117 * The T bit should be set in the elink of the QH so that the HC 1118 * doesn't follow the pointer. This condition may fail if the 1119 * the transferred packet was short so that the QH still points 1120 * at the last used TD. 1121 * In this case we set the T bit and wait a little for the HC 1122 * to stop looking at the TD. 1123 * Note that if the TD chain is large enough, the controller 1124 * may still be looking at the chain at the end of this function. 1125 * uhci_free_std_chain() will make sure the controller stops 1126 * looking at it quickly, but until then we should not change 1127 * sqh->hlink. 1128 */ 1129 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1130 sizeof(sqh->qh.qh_elink), 1131 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1132 elink = le32toh(sqh->qh.qh_elink); 1133 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1134 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1135 if (!(elink & UHCI_PTR_T)) { 1136 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1137 usb_syncmem(&sqh->dma, 1138 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1139 sizeof(sqh->qh.qh_elink), 1140 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1141 delay(UHCI_QH_REMOVE_DELAY); 1142 } 1143 1144 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1145 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1146 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1147 pqh->hlink = sqh->hlink; 1148 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1149 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1150 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1151 delay(UHCI_QH_REMOVE_DELAY); 1152 if (sc->sc_hctl_end == sqh) 1153 sc->sc_hctl_end = pqh; 1154 } 1155 1156 /* Add low speed control QH, called with lock held. */ 1157 void 1158 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1159 { 1160 uhci_soft_qh_t *eqh; 1161 1162 KASSERT(mutex_owned(&sc->sc_lock)); 1163 1164 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1165 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1166 1167 eqh = sc->sc_lctl_end; 1168 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1169 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1170 sqh->hlink = eqh->hlink; 1171 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1172 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1173 BUS_DMASYNC_PREWRITE); 1174 eqh->hlink = sqh; 1175 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1176 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1177 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1178 sc->sc_lctl_end = sqh; 1179 } 1180 1181 /* Remove low speed control QH, called with lock held. */ 1182 void 1183 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1184 { 1185 uhci_soft_qh_t *pqh; 1186 uint32_t elink; 1187 1188 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1189 1190 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1191 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1192 1193 /* See comment in uhci_remove_hs_ctrl() */ 1194 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1195 sizeof(sqh->qh.qh_elink), 1196 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1197 elink = le32toh(sqh->qh.qh_elink); 1198 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1199 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1200 if (!(elink & UHCI_PTR_T)) { 1201 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1202 usb_syncmem(&sqh->dma, 1203 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1204 sizeof(sqh->qh.qh_elink), 1205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1206 delay(UHCI_QH_REMOVE_DELAY); 1207 } 1208 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1209 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1210 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1211 pqh->hlink = sqh->hlink; 1212 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1213 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1214 sizeof(pqh->qh.qh_hlink), 1215 BUS_DMASYNC_PREWRITE); 1216 delay(UHCI_QH_REMOVE_DELAY); 1217 if (sc->sc_lctl_end == sqh) 1218 sc->sc_lctl_end = pqh; 1219 } 1220 1221 /* Add bulk QH, called with lock held. */ 1222 void 1223 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1224 { 1225 uhci_soft_qh_t *eqh; 1226 1227 KASSERT(mutex_owned(&sc->sc_lock)); 1228 1229 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1230 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1231 1232 eqh = sc->sc_bulk_end; 1233 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1234 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1235 sqh->hlink = eqh->hlink; 1236 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1237 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1238 BUS_DMASYNC_PREWRITE); 1239 eqh->hlink = sqh; 1240 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1241 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1242 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1243 sc->sc_bulk_end = sqh; 1244 uhci_add_loop(sc); 1245 } 1246 1247 /* Remove bulk QH, called with lock held. */ 1248 void 1249 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1250 { 1251 uhci_soft_qh_t *pqh; 1252 1253 KASSERT(mutex_owned(&sc->sc_lock)); 1254 1255 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1256 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1257 1258 uhci_rem_loop(sc); 1259 /* See comment in uhci_remove_hs_ctrl() */ 1260 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1261 sizeof(sqh->qh.qh_elink), 1262 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1263 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1264 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1265 usb_syncmem(&sqh->dma, 1266 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1267 sizeof(sqh->qh.qh_elink), 1268 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269 delay(UHCI_QH_REMOVE_DELAY); 1270 } 1271 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1272 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1273 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1274 pqh->hlink = sqh->hlink; 1275 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1276 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1277 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1278 delay(UHCI_QH_REMOVE_DELAY); 1279 if (sc->sc_bulk_end == sqh) 1280 sc->sc_bulk_end = pqh; 1281 } 1282 1283 Static int uhci_intr1(uhci_softc_t *); 1284 1285 int 1286 uhci_intr(void *arg) 1287 { 1288 uhci_softc_t *sc = arg; 1289 int ret = 0; 1290 1291 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1292 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 1295 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1296 goto done; 1297 1298 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1299 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1300 goto done; 1301 } 1302 1303 ret = uhci_intr1(sc); 1304 1305 done: 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 return ret; 1308 } 1309 1310 int 1311 uhci_intr1(uhci_softc_t *sc) 1312 { 1313 int status; 1314 int ack; 1315 1316 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1317 1318 #ifdef UHCI_DEBUG 1319 if (uhcidebug >= 15) { 1320 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1321 uhci_dumpregs(sc); 1322 } 1323 #endif 1324 1325 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1326 1327 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1328 /* Check if the interrupt was for us. */ 1329 if (status == 0) 1330 return 0; 1331 1332 if (sc->sc_suspend != PWR_RESUME) { 1333 #ifdef DIAGNOSTIC 1334 printf("%s: interrupt while not operating ignored\n", 1335 device_xname(sc->sc_dev)); 1336 #endif 1337 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1338 return 0; 1339 } 1340 1341 ack = 0; 1342 if (status & UHCI_STS_USBINT) 1343 ack |= UHCI_STS_USBINT; 1344 if (status & UHCI_STS_USBEI) 1345 ack |= UHCI_STS_USBEI; 1346 if (status & UHCI_STS_RD) { 1347 ack |= UHCI_STS_RD; 1348 #ifdef UHCI_DEBUG 1349 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1350 #endif 1351 } 1352 if (status & UHCI_STS_HSE) { 1353 ack |= UHCI_STS_HSE; 1354 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1355 } 1356 if (status & UHCI_STS_HCPE) { 1357 ack |= UHCI_STS_HCPE; 1358 printf("%s: host controller process error\n", 1359 device_xname(sc->sc_dev)); 1360 } 1361 1362 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1363 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1364 /* no acknowledge needed */ 1365 if (!sc->sc_dying) { 1366 printf("%s: host controller halted\n", 1367 device_xname(sc->sc_dev)); 1368 #ifdef UHCI_DEBUG 1369 uhci_dump_all(sc); 1370 #endif 1371 } 1372 sc->sc_dying = 1; 1373 } 1374 1375 if (!ack) 1376 return 0; /* nothing to acknowledge */ 1377 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1378 1379 usb_schedsoftintr(&sc->sc_bus); 1380 1381 DPRINTFN(15, "sc %#jx done", (uintptr_t)sc, 0, 0, 0); 1382 1383 return 1; 1384 } 1385 1386 void 1387 uhci_softintr(void *v) 1388 { 1389 struct usbd_bus *bus = v; 1390 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1391 struct uhci_xfer *ux, *nextux; 1392 ux_completeq_t cq; 1393 1394 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1395 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1396 1397 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1398 1399 TAILQ_INIT(&cq); 1400 /* 1401 * Interrupts on UHCI really suck. When the host controller 1402 * interrupts because a transfer is completed there is no 1403 * way of knowing which transfer it was. You can scan down 1404 * the TDs and QHs of the previous frame to limit the search, 1405 * but that assumes that the interrupt was not delayed by more 1406 * than 1 ms, which may not always be true (e.g. after debug 1407 * output on a slow console). 1408 * We scan all interrupt descriptors to see if any have 1409 * completed. 1410 */ 1411 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1412 uhci_check_intr(sc, ux, &cq); 1413 } 1414 1415 /* 1416 * We abuse ux_list for the interrupt and complete lists and 1417 * interrupt transfers will get re-added here so use 1418 * the _SAFE version of TAILQ_FOREACH. 1419 */ 1420 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1421 DPRINTF("ux %#jx", (uintptr_t)ux, 0, 0, 0); 1422 usb_transfer_complete(&ux->ux_xfer); 1423 } 1424 1425 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1426 } 1427 1428 /* Check for an interrupt. */ 1429 void 1430 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1431 { 1432 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1433 uint32_t status; 1434 1435 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1436 DPRINTFN(15, "ux %#jx", (uintptr_t)ux, 0, 0, 0); 1437 1438 KASSERT(ux != NULL); 1439 1440 struct usbd_xfer *xfer = &ux->ux_xfer; 1441 if (xfer->ux_status == USBD_CANCELLED || 1442 xfer->ux_status == USBD_TIMEOUT) { 1443 DPRINTF("aborted xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1444 return; 1445 } 1446 1447 switch (ux->ux_type) { 1448 case UX_CTRL: 1449 fstd = ux->ux_setup; 1450 lstd = ux->ux_stat; 1451 break; 1452 case UX_BULK: 1453 case UX_INTR: 1454 case UX_ISOC: 1455 fstd = ux->ux_stdstart; 1456 lstd = ux->ux_stdend; 1457 break; 1458 default: 1459 KASSERT(false); 1460 break; 1461 } 1462 if (fstd == NULL) 1463 return; 1464 1465 KASSERT(lstd != NULL); 1466 1467 usb_syncmem(&lstd->dma, 1468 lstd->offs + offsetof(uhci_td_t, td_status), 1469 sizeof(lstd->td.td_status), 1470 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1471 status = le32toh(lstd->td.td_status); 1472 usb_syncmem(&lstd->dma, 1473 lstd->offs + offsetof(uhci_td_t, td_status), 1474 sizeof(lstd->td.td_status), 1475 BUS_DMASYNC_PREREAD); 1476 1477 /* If the last TD is not marked active we can complete */ 1478 if (!(status & UHCI_TD_ACTIVE)) { 1479 done: 1480 DPRINTFN(12, "ux=%#jx done", (uintptr_t)ux, 0, 0, 0); 1481 uhci_idone(ux, cqp); 1482 return; 1483 } 1484 1485 /* 1486 * If the last TD is still active we need to check whether there 1487 * is an error somewhere in the middle, or whether there was a 1488 * short packet (SPD and not ACTIVE). 1489 */ 1490 DPRINTFN(12, "active ux=%#jx", (uintptr_t)ux, 0, 0, 0); 1491 for (std = fstd; std != lstd; std = std->link.std) { 1492 usb_syncmem(&std->dma, 1493 std->offs + offsetof(uhci_td_t, td_status), 1494 sizeof(std->td.td_status), 1495 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1496 status = le32toh(std->td.td_status); 1497 usb_syncmem(&std->dma, 1498 std->offs + offsetof(uhci_td_t, td_status), 1499 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1500 1501 /* If there's an active TD the xfer isn't done. */ 1502 if (status & UHCI_TD_ACTIVE) { 1503 DPRINTFN(12, "ux=%#jx std=%#jx still active", 1504 (uintptr_t)ux, (uintptr_t)std, 0, 0); 1505 return; 1506 } 1507 1508 /* Any kind of error makes the xfer done. */ 1509 if (status & UHCI_TD_STALLED) 1510 goto done; 1511 1512 /* 1513 * If the data phase of a control transfer is short, we need 1514 * to complete the status stage 1515 */ 1516 1517 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1518 struct uhci_pipe *upipe = 1519 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1520 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1521 uhci_soft_td_t *stat = upipe->ctrl.stat; 1522 1523 DPRINTFN(12, "ux=%#jx std=%#jx control status" 1524 "phase needs completion", (uintptr_t)ux, 1525 (uintptr_t)ux->ux_stdstart, 0, 0); 1526 1527 sqh->qh.qh_elink = 1528 htole32(stat->physaddr | UHCI_PTR_TD); 1529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1530 BUS_DMASYNC_PREWRITE); 1531 break; 1532 } 1533 1534 /* We want short packets, and it is short: it's done */ 1535 usb_syncmem(&std->dma, 1536 std->offs + offsetof(uhci_td_t, td_token), 1537 sizeof(std->td.td_token), 1538 BUS_DMASYNC_POSTWRITE); 1539 1540 if ((status & UHCI_TD_SPD) && 1541 UHCI_TD_GET_ACTLEN(status) < 1542 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1543 goto done; 1544 } 1545 } 1546 } 1547 1548 /* Called with USB lock held. */ 1549 void 1550 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1551 { 1552 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1553 struct usbd_xfer *xfer = &ux->ux_xfer; 1554 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1555 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1556 uhci_soft_td_t *std; 1557 uint32_t status = 0, nstatus; 1558 int actlen; 1559 1560 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1561 1562 DPRINTFN(12, "ux=%#jx", (uintptr_t)ux, 0, 0, 0); 1563 1564 /* 1565 * If software has completed it, either by cancellation 1566 * or timeout, drop it on the floor. 1567 */ 1568 if (xfer->ux_status != USBD_IN_PROGRESS) { 1569 KASSERT(xfer->ux_status == USBD_CANCELLED || 1570 xfer->ux_status == USBD_TIMEOUT); 1571 DPRINTF("aborted xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1572 return; 1573 } 1574 1575 /* 1576 * Cancel the timeout and the task, which have not yet 1577 * run. If they have already fired, at worst they are 1578 * waiting for the lock. They will see that the xfer 1579 * is no longer in progress and give up. 1580 */ 1581 callout_stop(&xfer->ux_callout); 1582 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 1583 1584 #ifdef DIAGNOSTIC 1585 #ifdef UHCI_DEBUG 1586 if (ux->ux_isdone) { 1587 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1588 uhci_dump_ii(ux); 1589 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1590 } 1591 #endif 1592 KASSERT(!ux->ux_isdone); 1593 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1594 ux->ux_type, xfer->ux_status); 1595 ux->ux_isdone = true; 1596 #endif 1597 1598 if (xfer->ux_nframes != 0) { 1599 /* Isoc transfer, do things differently. */ 1600 uhci_soft_td_t **stds = upipe->isoc.stds; 1601 int i, n, nframes, len; 1602 1603 DPRINTFN(5, "ux=%#jx isoc ready", (uintptr_t)ux, 0, 0, 0); 1604 1605 nframes = xfer->ux_nframes; 1606 actlen = 0; 1607 n = ux->ux_curframe; 1608 for (i = 0; i < nframes; i++) { 1609 std = stds[n]; 1610 #ifdef UHCI_DEBUG 1611 if (uhcidebug >= 5) { 1612 DPRINTF("isoc TD %jd", i, 0, 0, 0); 1613 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1614 uhci_dump_td(std); 1615 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1616 } 1617 #endif 1618 if (++n >= UHCI_VFRAMELIST_COUNT) 1619 n = 0; 1620 usb_syncmem(&std->dma, 1621 std->offs + offsetof(uhci_td_t, td_status), 1622 sizeof(std->td.td_status), 1623 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1624 status = le32toh(std->td.td_status); 1625 len = UHCI_TD_GET_ACTLEN(status); 1626 xfer->ux_frlengths[i] = len; 1627 actlen += len; 1628 } 1629 upipe->isoc.inuse -= nframes; 1630 xfer->ux_actlen = actlen; 1631 xfer->ux_status = USBD_NORMAL_COMPLETION; 1632 goto end; 1633 } 1634 1635 #ifdef UHCI_DEBUG 1636 DPRINTFN(10, "ux=%#jx, xfer=%#jx, pipe=%#jx ready", (uintptr_t)ux, 1637 (uintptr_t)xfer, (uintptr_t)upipe, 0); 1638 if (uhcidebug >= 10) { 1639 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1640 uhci_dump_tds(ux->ux_stdstart); 1641 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1642 } 1643 #endif 1644 1645 /* The transfer is done, compute actual length and status. */ 1646 actlen = 0; 1647 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1648 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1649 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1650 nstatus = le32toh(std->td.td_status); 1651 if (nstatus & UHCI_TD_ACTIVE) 1652 break; 1653 1654 status = nstatus; 1655 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1656 UHCI_TD_PID_SETUP) 1657 actlen += UHCI_TD_GET_ACTLEN(status); 1658 else { 1659 /* 1660 * UHCI will report CRCTO in addition to a STALL or NAK 1661 * for a SETUP transaction. See section 3.2.2, "TD 1662 * CONTROL AND STATUS". 1663 */ 1664 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1665 status &= ~UHCI_TD_CRCTO; 1666 } 1667 } 1668 /* If there are left over TDs we need to update the toggle. */ 1669 if (std != NULL) 1670 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1671 1672 status &= UHCI_TD_ERROR; 1673 DPRINTFN(10, "actlen=%jd, status=0x%jx", actlen, status, 0, 0); 1674 xfer->ux_actlen = actlen; 1675 if (status != 0) { 1676 1677 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1678 "error, addr=%jd, endpt=0x%02jx", 1679 xfer->ux_pipe->up_dev->ud_addr, 1680 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1681 0, 0); 1682 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1683 "bitstuff=%jd crcto =%jd nak =%jd babble =%jd", 1684 !!(status & UHCI_TD_BITSTUFF), 1685 !!(status & UHCI_TD_CRCTO), 1686 !!(status & UHCI_TD_NAK), 1687 !!(status & UHCI_TD_BABBLE)); 1688 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1689 "dbuffer =%jd stalled =%jd active =%jd", 1690 !!(status & UHCI_TD_DBUFFER), 1691 !!(status & UHCI_TD_STALLED), 1692 !!(status & UHCI_TD_ACTIVE), 1693 0); 1694 1695 if (status == UHCI_TD_STALLED) 1696 xfer->ux_status = USBD_STALLED; 1697 else 1698 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1699 } else { 1700 xfer->ux_status = USBD_NORMAL_COMPLETION; 1701 } 1702 1703 end: 1704 uhci_del_intr_list(sc, ux); 1705 if (cqp) 1706 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1707 1708 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1709 DPRINTFN(12, "ux=%#jx done", (uintptr_t)ux, 0, 0, 0); 1710 } 1711 1712 /* 1713 * Called when a request does not complete. 1714 */ 1715 void 1716 uhci_timeout(void *addr) 1717 { 1718 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1719 struct usbd_xfer *xfer = addr; 1720 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1721 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1722 1723 DPRINTF("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1724 1725 mutex_enter(&sc->sc_lock); 1726 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 1727 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 1728 mutex_exit(&sc->sc_lock); 1729 } 1730 1731 void 1732 uhci_timeout_task(void *addr) 1733 { 1734 struct usbd_xfer *xfer = addr; 1735 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 1736 1737 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1738 1739 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1740 1741 mutex_enter(&sc->sc_lock); 1742 uhci_abort_xfer(xfer, USBD_TIMEOUT); 1743 mutex_exit(&sc->sc_lock); 1744 } 1745 1746 void 1747 uhci_poll(struct usbd_bus *bus) 1748 { 1749 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1750 1751 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1752 mutex_spin_enter(&sc->sc_intr_lock); 1753 uhci_intr1(sc); 1754 mutex_spin_exit(&sc->sc_intr_lock); 1755 } 1756 } 1757 1758 void 1759 uhci_reset(uhci_softc_t *sc) 1760 { 1761 int n; 1762 1763 UHCICMD(sc, UHCI_CMD_HCRESET); 1764 /* The reset bit goes low when the controller is done. */ 1765 for (n = 0; n < UHCI_RESET_TIMEOUT && 1766 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1767 usb_delay_ms(&sc->sc_bus, 1); 1768 if (n >= UHCI_RESET_TIMEOUT) 1769 printf("%s: controller did not reset\n", 1770 device_xname(sc->sc_dev)); 1771 } 1772 1773 usbd_status 1774 uhci_run(uhci_softc_t *sc, int run, int locked) 1775 { 1776 int n, running; 1777 uint16_t cmd; 1778 1779 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1780 1781 run = run != 0; 1782 if (!locked) 1783 mutex_spin_enter(&sc->sc_intr_lock); 1784 1785 DPRINTF("setting run=%jd", run, 0, 0, 0); 1786 cmd = UREAD2(sc, UHCI_CMD); 1787 if (run) 1788 cmd |= UHCI_CMD_RS; 1789 else 1790 cmd &= ~UHCI_CMD_RS; 1791 UHCICMD(sc, cmd); 1792 for (n = 0; n < 10; n++) { 1793 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1794 /* return when we've entered the state we want */ 1795 if (run == running) { 1796 if (!locked) 1797 mutex_spin_exit(&sc->sc_intr_lock); 1798 DPRINTF("done cmd=0x%jx sts=0x%jx", 1799 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1800 return USBD_NORMAL_COMPLETION; 1801 } 1802 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1803 } 1804 if (!locked) 1805 mutex_spin_exit(&sc->sc_intr_lock); 1806 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1807 run ? "start" : "stop"); 1808 return USBD_IOERROR; 1809 } 1810 1811 /* 1812 * Memory management routines. 1813 * uhci_alloc_std allocates TDs 1814 * uhci_alloc_sqh allocates QHs 1815 * These two routines do their own free list management, 1816 * partly for speed, partly because allocating DMAable memory 1817 * has page size granularity so much memory would be wasted if 1818 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1819 */ 1820 1821 uhci_soft_td_t * 1822 uhci_alloc_std(uhci_softc_t *sc) 1823 { 1824 uhci_soft_td_t *std; 1825 usbd_status err; 1826 int i, offs; 1827 usb_dma_t dma; 1828 1829 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1830 1831 mutex_enter(&sc->sc_lock); 1832 if (sc->sc_freetds == NULL) { 1833 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1834 mutex_exit(&sc->sc_lock); 1835 1836 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1837 UHCI_TD_ALIGN, &dma); 1838 if (err) 1839 return NULL; 1840 1841 mutex_enter(&sc->sc_lock); 1842 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1843 offs = i * UHCI_STD_SIZE; 1844 std = KERNADDR(&dma, offs); 1845 std->physaddr = DMAADDR(&dma, offs); 1846 std->dma = dma; 1847 std->offs = offs; 1848 std->link.std = sc->sc_freetds; 1849 sc->sc_freetds = std; 1850 } 1851 } 1852 std = sc->sc_freetds; 1853 sc->sc_freetds = std->link.std; 1854 mutex_exit(&sc->sc_lock); 1855 1856 memset(&std->td, 0, sizeof(uhci_td_t)); 1857 1858 return std; 1859 } 1860 1861 #define TD_IS_FREE 0x12345678 1862 1863 void 1864 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1865 { 1866 KASSERT(mutex_owned(&sc->sc_lock)); 1867 1868 #ifdef DIAGNOSTIC 1869 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1870 printf("%s: freeing free TD %p\n", __func__, std); 1871 return; 1872 } 1873 std->td.td_token = htole32(TD_IS_FREE); 1874 #endif 1875 1876 std->link.std = sc->sc_freetds; 1877 sc->sc_freetds = std; 1878 } 1879 1880 void 1881 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1882 { 1883 mutex_enter(&sc->sc_lock); 1884 uhci_free_std_locked(sc, std); 1885 mutex_exit(&sc->sc_lock); 1886 } 1887 1888 uhci_soft_qh_t * 1889 uhci_alloc_sqh(uhci_softc_t *sc) 1890 { 1891 uhci_soft_qh_t *sqh; 1892 usbd_status err; 1893 int i, offs; 1894 usb_dma_t dma; 1895 1896 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1897 1898 mutex_enter(&sc->sc_lock); 1899 if (sc->sc_freeqhs == NULL) { 1900 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1901 mutex_exit(&sc->sc_lock); 1902 1903 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1904 UHCI_QH_ALIGN, &dma); 1905 if (err) 1906 return NULL; 1907 1908 mutex_enter(&sc->sc_lock); 1909 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1910 offs = i * UHCI_SQH_SIZE; 1911 sqh = KERNADDR(&dma, offs); 1912 sqh->physaddr = DMAADDR(&dma, offs); 1913 sqh->dma = dma; 1914 sqh->offs = offs; 1915 sqh->hlink = sc->sc_freeqhs; 1916 sc->sc_freeqhs = sqh; 1917 } 1918 } 1919 sqh = sc->sc_freeqhs; 1920 sc->sc_freeqhs = sqh->hlink; 1921 mutex_exit(&sc->sc_lock); 1922 1923 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1924 1925 return sqh; 1926 } 1927 1928 void 1929 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1930 { 1931 KASSERT(mutex_owned(&sc->sc_lock)); 1932 1933 sqh->hlink = sc->sc_freeqhs; 1934 sc->sc_freeqhs = sqh; 1935 } 1936 1937 #if 0 1938 void 1939 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1940 uhci_soft_td_t *stdend) 1941 { 1942 uhci_soft_td_t *p; 1943 uint32_t td_link; 1944 1945 /* 1946 * to avoid race condition with the controller which may be looking 1947 * at this chain, we need to first invalidate all links, and 1948 * then wait for the controller to move to another queue 1949 */ 1950 for (p = std; p != stdend; p = p->link.std) { 1951 usb_syncmem(&p->dma, 1952 p->offs + offsetof(uhci_td_t, td_link), 1953 sizeof(p->td.td_link), 1954 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1955 td_link = le32toh(p->td.td_link); 1956 usb_syncmem(&p->dma, 1957 p->offs + offsetof(uhci_td_t, td_link), 1958 sizeof(p->td.td_link), 1959 BUS_DMASYNC_PREREAD); 1960 if ((td_link & UHCI_PTR_T) == 0) { 1961 p->td.td_link = htole32(UHCI_PTR_T); 1962 usb_syncmem(&p->dma, 1963 p->offs + offsetof(uhci_td_t, td_link), 1964 sizeof(p->td.td_link), 1965 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1966 } 1967 } 1968 delay(UHCI_QH_REMOVE_DELAY); 1969 1970 for (; std != stdend; std = p) { 1971 p = std->link.std; 1972 uhci_free_std(sc, std); 1973 } 1974 } 1975 #endif 1976 1977 int 1978 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len, 1979 int rd, uhci_soft_td_t **sp) 1980 { 1981 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1982 uint16_t flags = xfer->ux_flags; 1983 uhci_soft_td_t *p; 1984 1985 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1986 1987 DPRINTFN(8, "xfer=%#jx pipe=%#jx", (uintptr_t)xfer, 1988 (uintptr_t)xfer->ux_pipe, 0, 0); 1989 1990 ASSERT_SLEEPABLE(); 1991 KASSERT(sp); 1992 1993 int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 1994 if (maxp == 0) { 1995 printf("%s: maxp=0\n", __func__); 1996 return EINVAL; 1997 } 1998 size_t ntd = (len + maxp - 1) / maxp; 1999 if (!rd && (flags & USBD_FORCE_SHORT_XFER)) { 2000 ntd++; 2001 } 2002 DPRINTFN(10, "maxp=%jd ntd=%jd", maxp, ntd, 0, 0); 2003 2004 uxfer->ux_stds = NULL; 2005 uxfer->ux_nstd = ntd; 2006 if (ntd == 0) { 2007 *sp = NULL; 2008 DPRINTF("ntd=0", 0, 0, 0, 0); 2009 return 0; 2010 } 2011 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2012 KM_SLEEP); 2013 2014 for (int i = 0; i < ntd; i++) { 2015 p = uhci_alloc_std(sc); 2016 if (p == NULL) { 2017 if (i != 0) { 2018 uxfer->ux_nstd = i; 2019 uhci_free_stds(sc, uxfer); 2020 } 2021 kmem_free(uxfer->ux_stds, 2022 sizeof(uhci_soft_td_t *) * ntd); 2023 return ENOMEM; 2024 } 2025 uxfer->ux_stds[i] = p; 2026 } 2027 2028 *sp = uxfer->ux_stds[0]; 2029 2030 return 0; 2031 } 2032 2033 Static void 2034 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2035 { 2036 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2037 2038 DPRINTFN(8, "ux=%#jx", (uintptr_t)ux, 0, 0, 0); 2039 2040 mutex_enter(&sc->sc_lock); 2041 for (size_t i = 0; i < ux->ux_nstd; i++) { 2042 uhci_soft_td_t *std = ux->ux_stds[i]; 2043 #ifdef DIAGNOSTIC 2044 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2045 printf("%s: freeing free TD %p\n", __func__, std); 2046 return; 2047 } 2048 std->td.td_token = htole32(TD_IS_FREE); 2049 #endif 2050 ux->ux_stds[i]->link.std = sc->sc_freetds; 2051 sc->sc_freetds = std; 2052 } 2053 mutex_exit(&sc->sc_lock); 2054 } 2055 2056 2057 Static void 2058 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2059 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2060 { 2061 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2062 struct usbd_pipe *pipe = xfer->ux_pipe; 2063 usb_dma_t *dma = &xfer->ux_dmabuf; 2064 uint16_t flags = xfer->ux_flags; 2065 uhci_soft_td_t *std, *prev; 2066 int len = length; 2067 int tog = *toggle; 2068 int maxp; 2069 uint32_t status; 2070 size_t i; 2071 2072 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2073 DPRINTFN(8, "xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2074 len, isread, *toggle); 2075 2076 KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2077 2078 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2079 KASSERT(maxp != 0); 2080 2081 int addr = xfer->ux_pipe->up_dev->ud_addr; 2082 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2083 2084 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2085 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2086 status |= UHCI_TD_LS; 2087 if (flags & USBD_SHORT_XFER_OK) 2088 status |= UHCI_TD_SPD; 2089 usb_syncmem(dma, 0, len, 2090 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2091 std = prev = NULL; 2092 for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) { 2093 int l = len; 2094 std = uxfer->ux_stds[i]; 2095 if (l > maxp) 2096 l = maxp; 2097 2098 if (prev) { 2099 prev->link.std = std; 2100 prev->td.td_link = htole32( 2101 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2102 ); 2103 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2105 } 2106 2107 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2108 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2109 2110 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2111 std->td.td_status = htole32(status); 2112 std->td.td_token = htole32( 2113 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2114 UHCI_TD_SET_DEVADDR(addr) | 2115 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2116 UHCI_TD_SET_DT(tog) | 2117 UHCI_TD_SET_MAXLEN(l) 2118 ); 2119 std->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2120 2121 std->link.std = NULL; 2122 2123 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2124 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2125 tog ^= 1; 2126 2127 len -= l; 2128 } 2129 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2130 xfer, length, len, maxp, uxfer->ux_nstd, i); 2131 2132 if (!isread && 2133 (flags & USBD_FORCE_SHORT_XFER) && 2134 length % maxp == 0) { 2135 /* Force a 0 length transfer at the end. */ 2136 KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i, 2137 uxfer->ux_nstd); 2138 std = uxfer->ux_stds[i++]; 2139 2140 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2141 std->td.td_status = htole32(status); 2142 std->td.td_token = htole32( 2143 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2144 UHCI_TD_SET_DEVADDR(addr) | 2145 UHCI_TD_SET_PID(UHCI_TD_PID_OUT) | 2146 UHCI_TD_SET_DT(tog) | 2147 UHCI_TD_SET_MAXLEN(0) 2148 ); 2149 std->td.td_buffer = 0; 2150 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2151 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2152 2153 std->link.std = NULL; 2154 if (prev) { 2155 prev->link.std = std; 2156 prev->td.td_link = htole32( 2157 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2158 ); 2159 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2161 } 2162 tog ^= 1; 2163 } 2164 *lstd = std; 2165 *toggle = tog; 2166 } 2167 2168 void 2169 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2170 { 2171 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2172 upipe->nexttoggle = 0; 2173 } 2174 2175 void 2176 uhci_noop(struct usbd_pipe *pipe) 2177 { 2178 } 2179 2180 int 2181 uhci_device_bulk_init(struct usbd_xfer *xfer) 2182 { 2183 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2184 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2185 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2186 int endpt = ed->bEndpointAddress; 2187 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2188 int len = xfer->ux_bufsize; 2189 int err = 0; 2190 2191 2192 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2193 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, len, 2194 xfer->ux_flags, 0); 2195 2196 if (sc->sc_dying) 2197 return USBD_IOERROR; 2198 2199 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2200 2201 uxfer->ux_type = UX_BULK; 2202 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart); 2203 if (err) 2204 return err; 2205 2206 #ifdef UHCI_DEBUG 2207 if (uhcidebug >= 10) { 2208 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2209 uhci_dump_tds(uxfer->ux_stdstart); 2210 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2211 } 2212 #endif 2213 2214 return 0; 2215 } 2216 2217 Static void 2218 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2219 { 2220 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2221 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2222 2223 KASSERT(ux->ux_type == UX_BULK); 2224 2225 if (ux->ux_nstd) { 2226 uhci_free_stds(sc, ux); 2227 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2228 } 2229 } 2230 2231 usbd_status 2232 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2233 { 2234 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2235 usbd_status err; 2236 2237 /* Insert last in queue. */ 2238 mutex_enter(&sc->sc_lock); 2239 err = usb_insert_transfer(xfer); 2240 mutex_exit(&sc->sc_lock); 2241 if (err) 2242 return err; 2243 2244 /* 2245 * Pipe isn't running (otherwise err would be USBD_INPROG), 2246 * so start it first. 2247 */ 2248 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2249 } 2250 2251 usbd_status 2252 uhci_device_bulk_start(struct usbd_xfer *xfer) 2253 { 2254 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2255 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2256 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2257 uhci_soft_td_t *data, *dataend; 2258 uhci_soft_qh_t *sqh; 2259 int len; 2260 int endpt; 2261 int isread; 2262 2263 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2264 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 2265 xfer->ux_length, xfer->ux_flags, 0); 2266 2267 if (sc->sc_dying) 2268 return USBD_IOERROR; 2269 2270 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2271 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2272 2273 len = xfer->ux_length; 2274 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2275 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2276 sqh = upipe->bulk.sqh; 2277 2278 /* Take lock here to protect nexttoggle */ 2279 mutex_enter(&sc->sc_lock); 2280 2281 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2282 &dataend); 2283 2284 data = ux->ux_stdstart; 2285 ux->ux_stdend = dataend; 2286 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2287 usb_syncmem(&dataend->dma, 2288 dataend->offs + offsetof(uhci_td_t, td_status), 2289 sizeof(dataend->td.td_status), 2290 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2291 2292 #ifdef UHCI_DEBUG 2293 if (uhcidebug >= 10) { 2294 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2295 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2296 uhci_dump_tds(data); 2297 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2298 } 2299 #endif 2300 2301 KASSERT(ux->ux_isdone); 2302 #ifdef DIAGNOSTIC 2303 ux->ux_isdone = false; 2304 #endif 2305 2306 sqh->elink = data; 2307 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2308 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2309 2310 uhci_add_bulk(sc, sqh); 2311 uhci_add_intr_list(sc, ux); 2312 2313 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2314 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2315 uhci_timeout, xfer); 2316 } 2317 xfer->ux_status = USBD_IN_PROGRESS; 2318 mutex_exit(&sc->sc_lock); 2319 2320 return USBD_IN_PROGRESS; 2321 } 2322 2323 /* Abort a device bulk request. */ 2324 void 2325 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2326 { 2327 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2328 2329 KASSERT(mutex_owned(&sc->sc_lock)); 2330 2331 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2332 2333 uhci_abort_xfer(xfer, USBD_CANCELLED); 2334 } 2335 2336 /* 2337 * Cancel or timeout a device request. We have two cases to deal with 2338 * 2339 * 1) A driver wants to stop scheduled or inflight transfers 2340 * 2) A transfer has timed out 2341 * 2342 * It's impossible to guarantee that the requested transfer will not 2343 * have (partially) happened since the hardware runs concurrently. 2344 * 2345 * Transfer state is protected by the bus lock and we set the transfer status 2346 * as soon as either of the above happens (with bus lock held). 2347 * 2348 * To allow the hardware time to notice we simply wait. 2349 */ 2350 void 2351 uhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2352 { 2353 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2354 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2355 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2356 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2357 uhci_soft_td_t *std; 2358 2359 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 2360 "invalid status for abort: %d", (int)status); 2361 2362 DPRINTFN(1,"xfer=%#jx, status=%jd", (uintptr_t)xfer, status, 0, 0); 2363 2364 KASSERT(mutex_owned(&sc->sc_lock)); 2365 ASSERT_SLEEPABLE(); 2366 2367 if (status == USBD_CANCELLED) { 2368 /* 2369 * We are synchronously aborting. Try to stop the 2370 * callout and task, but if we can't, wait for them to 2371 * complete. 2372 */ 2373 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2374 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 2375 USB_TASKQ_HC, &sc->sc_lock); 2376 } else { 2377 /* Otherwise, we are timing out. */ 2378 KASSERT(status == USBD_TIMEOUT); 2379 } 2380 2381 /* 2382 * The xfer cannot have been cancelled already. It is the 2383 * responsibility of the caller of usbd_abort_pipe not to try 2384 * to abort a pipe multiple times, whether concurrently or 2385 * sequentially. 2386 */ 2387 KASSERT(xfer->ux_status != USBD_CANCELLED); 2388 2389 /* Only the timeout, which runs only once, can time it out. */ 2390 KASSERT(xfer->ux_status != USBD_TIMEOUT); 2391 2392 /* If anyone else beat us, we're done. */ 2393 if (xfer->ux_status != USBD_IN_PROGRESS) 2394 return; 2395 2396 /* We beat everyone else. Claim the status. */ 2397 xfer->ux_status = status; 2398 2399 /* 2400 * If we're dying, skip the hardware action and just notify the 2401 * software that we're done. 2402 */ 2403 if (sc->sc_dying) { 2404 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2405 xfer->ux_status, 0, 0); 2406 goto dying; 2407 } 2408 2409 /* 2410 * HC Step 1: Make interrupt routine and hardware ignore xfer. 2411 */ 2412 uhci_del_intr_list(sc, ux); 2413 2414 DPRINTF("stop ux=%#jx", (uintptr_t)ux, 0, 0, 0); 2415 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2416 usb_syncmem(&std->dma, 2417 std->offs + offsetof(uhci_td_t, td_status), 2418 sizeof(std->td.td_status), 2419 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2420 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2421 usb_syncmem(&std->dma, 2422 std->offs + offsetof(uhci_td_t, td_status), 2423 sizeof(std->td.td_status), 2424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2425 } 2426 2427 /* 2428 * HC Step 2: Wait until we know hardware has finished any possible 2429 * use of the xfer. 2430 */ 2431 /* Hardware finishes in 1ms */ 2432 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2433 2434 /* 2435 * HC Step 3: Notify completion to waiting xfers. 2436 */ 2437 dying: 2438 #ifdef DIAGNOSTIC 2439 ux->ux_isdone = true; 2440 #endif 2441 usb_transfer_complete(xfer); 2442 DPRINTFN(14, "end", 0, 0, 0, 0); 2443 2444 KASSERT(mutex_owned(&sc->sc_lock)); 2445 } 2446 2447 /* Close a device bulk pipe. */ 2448 void 2449 uhci_device_bulk_close(struct usbd_pipe *pipe) 2450 { 2451 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2452 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2453 2454 KASSERT(mutex_owned(&sc->sc_lock)); 2455 2456 uhci_free_sqh(sc, upipe->bulk.sqh); 2457 2458 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2459 } 2460 2461 int 2462 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2463 { 2464 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2465 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2466 usb_device_request_t *req = &xfer->ux_request; 2467 struct usbd_device *dev = upipe->pipe.up_dev; 2468 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2469 uhci_soft_td_t *data = NULL; 2470 int len; 2471 usbd_status err; 2472 int isread; 2473 2474 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2475 DPRINTFN(3, "xfer=%#jx len=%jd, addr=%jd, endpt=%jd", 2476 (uintptr_t)xfer, xfer->ux_bufsize, dev->ud_addr, 2477 upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2478 2479 isread = req->bmRequestType & UT_READ; 2480 len = xfer->ux_bufsize; 2481 2482 uxfer->ux_type = UX_CTRL; 2483 /* Set up data transaction */ 2484 if (len != 0) { 2485 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data); 2486 if (err) 2487 return err; 2488 } 2489 /* Set up interrupt info. */ 2490 uxfer->ux_setup = upipe->ctrl.setup; 2491 uxfer->ux_stat = upipe->ctrl.stat; 2492 uxfer->ux_data = data; 2493 2494 return 0; 2495 } 2496 2497 Static void 2498 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2499 { 2500 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2501 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2502 2503 KASSERT(ux->ux_type == UX_CTRL); 2504 2505 if (ux->ux_nstd) { 2506 uhci_free_stds(sc, ux); 2507 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2508 } 2509 } 2510 2511 usbd_status 2512 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2513 { 2514 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2515 usbd_status err; 2516 2517 /* Insert last in queue. */ 2518 mutex_enter(&sc->sc_lock); 2519 err = usb_insert_transfer(xfer); 2520 mutex_exit(&sc->sc_lock); 2521 if (err) 2522 return err; 2523 2524 /* 2525 * Pipe isn't running (otherwise err would be USBD_INPROG), 2526 * so start it first. 2527 */ 2528 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2529 } 2530 2531 usbd_status 2532 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2533 { 2534 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2535 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2536 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2537 usb_device_request_t *req = &xfer->ux_request; 2538 struct usbd_device *dev = upipe->pipe.up_dev; 2539 int addr = dev->ud_addr; 2540 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2541 uhci_soft_td_t *setup, *stat, *next, *dataend; 2542 uhci_soft_qh_t *sqh; 2543 int len; 2544 int isread; 2545 2546 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2547 2548 if (sc->sc_dying) 2549 return USBD_IOERROR; 2550 2551 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2552 2553 DPRINTFN(3, "type=0x%02jx, request=0x%02jx, " 2554 "wValue=0x%04jx, wIndex=0x%04jx", 2555 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2556 UGETW(req->wIndex)); 2557 DPRINTFN(3, "len=%jd, addr=%jd, endpt=%jd", 2558 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2559 2560 isread = req->bmRequestType & UT_READ; 2561 len = UGETW(req->wLength); 2562 2563 setup = upipe->ctrl.setup; 2564 stat = upipe->ctrl.stat; 2565 sqh = upipe->ctrl.sqh; 2566 2567 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2568 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2569 2570 mutex_enter(&sc->sc_lock); 2571 2572 /* Set up data transaction */ 2573 if (len != 0) { 2574 upipe->nexttoggle = 1; 2575 next = uxfer->ux_data; 2576 uhci_reset_std_chain(sc, xfer, len, isread, 2577 &upipe->nexttoggle, &dataend); 2578 dataend->link.std = stat; 2579 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2580 usb_syncmem(&dataend->dma, 2581 dataend->offs + offsetof(uhci_td_t, td_link), 2582 sizeof(dataend->td.td_link), 2583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2584 } else { 2585 next = stat; 2586 } 2587 2588 const uint32_t status = UHCI_TD_ZERO_ACTLEN( 2589 UHCI_TD_SET_ERRCNT(3) | 2590 UHCI_TD_ACTIVE | 2591 (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0) 2592 ); 2593 setup->link.std = next; 2594 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2595 setup->td.td_status = htole32(status); 2596 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2597 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2598 2599 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2600 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2601 2602 stat->link.std = NULL; 2603 stat->td.td_link = htole32(UHCI_PTR_T); 2604 stat->td.td_status = htole32(status | UHCI_TD_IOC); 2605 stat->td.td_token = 2606 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2607 UHCI_TD_IN (0, endpt, addr, 1)); 2608 stat->td.td_buffer = htole32(0); 2609 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2611 2612 #ifdef UHCI_DEBUG 2613 if (uhcidebug >= 10) { 2614 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2615 DPRINTF("before transfer", 0, 0, 0, 0); 2616 uhci_dump_tds(setup); 2617 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2618 } 2619 #endif 2620 2621 /* Set up interrupt info. */ 2622 uxfer->ux_setup = setup; 2623 uxfer->ux_stat = stat; 2624 KASSERT(uxfer->ux_isdone); 2625 #ifdef DIAGNOSTIC 2626 uxfer->ux_isdone = false; 2627 #endif 2628 2629 sqh->elink = setup; 2630 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2631 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2632 2633 if (dev->ud_speed == USB_SPEED_LOW) 2634 uhci_add_ls_ctrl(sc, sqh); 2635 else 2636 uhci_add_hs_ctrl(sc, sqh); 2637 uhci_add_intr_list(sc, uxfer); 2638 #ifdef UHCI_DEBUG 2639 if (uhcidebug >= 12) { 2640 uhci_soft_td_t *std; 2641 uhci_soft_qh_t *xqh; 2642 uhci_soft_qh_t *sxqh; 2643 int maxqh = 0; 2644 uhci_physaddr_t link; 2645 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2646 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2647 for (std = sc->sc_vframes[0].htd, link = 0; 2648 (link & UHCI_PTR_QH) == 0; 2649 std = std->link.std) { 2650 link = le32toh(std->td.td_link); 2651 uhci_dump_td(std); 2652 } 2653 sxqh = (uhci_soft_qh_t *)std; 2654 uhci_dump_qh(sxqh); 2655 for (xqh = sxqh; 2656 xqh != NULL; 2657 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2658 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2659 uhci_dump_qh(xqh); 2660 } 2661 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2662 uhci_dump_qh(sqh); 2663 uhci_dump_tds(sqh->elink); 2664 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2665 } 2666 #endif 2667 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2668 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2669 uhci_timeout, xfer); 2670 } 2671 xfer->ux_status = USBD_IN_PROGRESS; 2672 mutex_exit(&sc->sc_lock); 2673 2674 return USBD_IN_PROGRESS; 2675 } 2676 2677 int 2678 uhci_device_intr_init(struct usbd_xfer *xfer) 2679 { 2680 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2681 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2682 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2683 int endpt = ed->bEndpointAddress; 2684 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2685 int len = xfer->ux_bufsize; 2686 int err; 2687 2688 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2689 2690 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 2691 xfer->ux_length, xfer->ux_flags, 0); 2692 2693 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2694 KASSERT(len != 0); 2695 2696 ux->ux_type = UX_INTR; 2697 ux->ux_nstd = 0; 2698 err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart); 2699 2700 return err; 2701 } 2702 2703 Static void 2704 uhci_device_intr_fini(struct usbd_xfer *xfer) 2705 { 2706 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2707 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2708 2709 KASSERT(ux->ux_type == UX_INTR); 2710 2711 if (ux->ux_nstd) { 2712 uhci_free_stds(sc, ux); 2713 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2714 } 2715 } 2716 2717 usbd_status 2718 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2719 { 2720 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2721 usbd_status err; 2722 2723 /* Insert last in queue. */ 2724 mutex_enter(&sc->sc_lock); 2725 err = usb_insert_transfer(xfer); 2726 mutex_exit(&sc->sc_lock); 2727 if (err) 2728 return err; 2729 2730 /* 2731 * Pipe isn't running (otherwise err would be USBD_INPROG), 2732 * so start it first. 2733 */ 2734 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2735 } 2736 2737 usbd_status 2738 uhci_device_intr_start(struct usbd_xfer *xfer) 2739 { 2740 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2741 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2742 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2743 uhci_soft_td_t *data, *dataend; 2744 uhci_soft_qh_t *sqh; 2745 int isread, endpt; 2746 int i; 2747 2748 if (sc->sc_dying) 2749 return USBD_IOERROR; 2750 2751 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2752 2753 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 2754 xfer->ux_length, xfer->ux_flags, 0); 2755 2756 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2757 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2758 2759 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2760 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2761 2762 data = ux->ux_stdstart; 2763 2764 KASSERT(ux->ux_isdone); 2765 #ifdef DIAGNOSTIC 2766 ux->ux_isdone = false; 2767 #endif 2768 2769 /* Take lock to protect nexttoggle */ 2770 mutex_enter(&sc->sc_lock); 2771 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2772 &upipe->nexttoggle, &dataend); 2773 2774 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2775 usb_syncmem(&dataend->dma, 2776 dataend->offs + offsetof(uhci_td_t, td_status), 2777 sizeof(dataend->td.td_status), 2778 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2779 ux->ux_stdend = dataend; 2780 2781 #ifdef UHCI_DEBUG 2782 if (uhcidebug >= 10) { 2783 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2784 uhci_dump_tds(data); 2785 uhci_dump_qh(upipe->intr.qhs[0]); 2786 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2787 } 2788 #endif 2789 2790 DPRINTFN(10, "qhs[0]=%#jx", (uintptr_t)upipe->intr.qhs[0], 0, 0, 0); 2791 for (i = 0; i < upipe->intr.npoll; i++) { 2792 sqh = upipe->intr.qhs[i]; 2793 sqh->elink = data; 2794 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2795 usb_syncmem(&sqh->dma, 2796 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2797 sizeof(sqh->qh.qh_elink), 2798 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2799 } 2800 uhci_add_intr_list(sc, ux); 2801 xfer->ux_status = USBD_IN_PROGRESS; 2802 mutex_exit(&sc->sc_lock); 2803 2804 #ifdef UHCI_DEBUG 2805 if (uhcidebug >= 10) { 2806 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2807 uhci_dump_tds(data); 2808 uhci_dump_qh(upipe->intr.qhs[0]); 2809 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2810 } 2811 #endif 2812 2813 return USBD_IN_PROGRESS; 2814 } 2815 2816 /* Abort a device control request. */ 2817 void 2818 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2819 { 2820 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2821 2822 KASSERT(mutex_owned(&sc->sc_lock)); 2823 2824 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2825 uhci_abort_xfer(xfer, USBD_CANCELLED); 2826 } 2827 2828 /* Close a device control pipe. */ 2829 void 2830 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2831 { 2832 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2833 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2834 2835 uhci_free_sqh(sc, upipe->ctrl.sqh); 2836 uhci_free_std_locked(sc, upipe->ctrl.setup); 2837 uhci_free_std_locked(sc, upipe->ctrl.stat); 2838 2839 } 2840 2841 /* Abort a device interrupt request. */ 2842 void 2843 uhci_device_intr_abort(struct usbd_xfer *xfer) 2844 { 2845 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2846 2847 KASSERT(mutex_owned(&sc->sc_lock)); 2848 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2849 2850 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2851 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2852 2853 uhci_abort_xfer(xfer, USBD_CANCELLED); 2854 } 2855 2856 /* Close a device interrupt pipe. */ 2857 void 2858 uhci_device_intr_close(struct usbd_pipe *pipe) 2859 { 2860 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2861 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2862 int i, npoll; 2863 2864 KASSERT(mutex_owned(&sc->sc_lock)); 2865 2866 /* Unlink descriptors from controller data structures. */ 2867 npoll = upipe->intr.npoll; 2868 for (i = 0; i < npoll; i++) 2869 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2870 2871 /* 2872 * We now have to wait for any activity on the physical 2873 * descriptors to stop. 2874 */ 2875 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2876 2877 for (i = 0; i < npoll; i++) 2878 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2879 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2880 } 2881 2882 int 2883 uhci_device_isoc_init(struct usbd_xfer *xfer) 2884 { 2885 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2886 2887 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2888 KASSERT(xfer->ux_nframes != 0); 2889 KASSERT(ux->ux_isdone); 2890 2891 ux->ux_type = UX_ISOC; 2892 return 0; 2893 } 2894 2895 Static void 2896 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2897 { 2898 struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer); 2899 2900 KASSERT(ux->ux_type == UX_ISOC); 2901 } 2902 2903 usbd_status 2904 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2905 { 2906 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2907 usbd_status err __diagused; 2908 2909 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2910 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2911 2912 /* Put it on our queue, */ 2913 mutex_enter(&sc->sc_lock); 2914 err = usb_insert_transfer(xfer); 2915 mutex_exit(&sc->sc_lock); 2916 2917 KASSERT(err == USBD_NORMAL_COMPLETION); 2918 2919 /* insert into schedule, */ 2920 2921 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2922 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2923 struct isoc *isoc = &upipe->isoc; 2924 uhci_soft_td_t *std = NULL; 2925 uint32_t buf, len, status, offs; 2926 int i, next, nframes; 2927 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2928 2929 DPRINTFN(5, "used=%jd next=%jd xfer=%#jx nframes=%jd", 2930 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 2931 2932 if (sc->sc_dying) 2933 return USBD_IOERROR; 2934 2935 if (xfer->ux_status == USBD_IN_PROGRESS) { 2936 /* This request has already been entered into the frame list */ 2937 printf("%s: xfer=%p in frame list\n", __func__, xfer); 2938 /* XXX */ 2939 } 2940 2941 #ifdef DIAGNOSTIC 2942 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2943 printf("%s: overflow!\n", __func__); 2944 #endif 2945 2946 KASSERT(xfer->ux_nframes != 0); 2947 2948 mutex_enter(&sc->sc_lock); 2949 next = isoc->next; 2950 if (next == -1) { 2951 /* Not in use yet, schedule it a few frames ahead. */ 2952 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2953 DPRINTFN(2, "start next=%jd", next, 0, 0, 0); 2954 } 2955 2956 xfer->ux_status = USBD_IN_PROGRESS; 2957 ux->ux_curframe = next; 2958 2959 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2960 offs = 0; 2961 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2962 UHCI_TD_ACTIVE | 2963 UHCI_TD_IOS); 2964 nframes = xfer->ux_nframes; 2965 for (i = 0; i < nframes; i++) { 2966 std = isoc->stds[next]; 2967 if (++next >= UHCI_VFRAMELIST_COUNT) 2968 next = 0; 2969 len = xfer->ux_frlengths[i]; 2970 std->td.td_buffer = htole32(buf); 2971 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2972 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2973 if (i == nframes - 1) 2974 status |= UHCI_TD_IOC; 2975 std->td.td_status = htole32(status); 2976 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2977 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2978 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2980 #ifdef UHCI_DEBUG 2981 if (uhcidebug >= 5) { 2982 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2983 DPRINTF("TD %jd", i, 0, 0, 0); 2984 uhci_dump_td(std); 2985 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2986 } 2987 #endif 2988 buf += len; 2989 offs += len; 2990 } 2991 isoc->next = next; 2992 isoc->inuse += xfer->ux_nframes; 2993 2994 /* Set up interrupt info. */ 2995 ux->ux_stdstart = std; 2996 ux->ux_stdend = std; 2997 2998 KASSERT(ux->ux_isdone); 2999 #ifdef DIAGNOSTIC 3000 ux->ux_isdone = false; 3001 #endif 3002 uhci_add_intr_list(sc, ux); 3003 3004 mutex_exit(&sc->sc_lock); 3005 3006 return USBD_IN_PROGRESS; 3007 } 3008 3009 void 3010 uhci_device_isoc_abort(struct usbd_xfer *xfer) 3011 { 3012 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3013 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3014 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3015 uhci_soft_td_t **stds = upipe->isoc.stds; 3016 uhci_soft_td_t *std; 3017 int i, n, nframes, maxlen, len; 3018 3019 KASSERT(mutex_owned(&sc->sc_lock)); 3020 3021 /* Transfer is already done. */ 3022 if (xfer->ux_status != USBD_NOT_STARTED && 3023 xfer->ux_status != USBD_IN_PROGRESS) { 3024 return; 3025 } 3026 3027 /* Give xfer the requested abort code. */ 3028 xfer->ux_status = USBD_CANCELLED; 3029 3030 /* make hardware ignore it, */ 3031 nframes = xfer->ux_nframes; 3032 n = ux->ux_curframe; 3033 maxlen = 0; 3034 for (i = 0; i < nframes; i++) { 3035 std = stds[n]; 3036 usb_syncmem(&std->dma, 3037 std->offs + offsetof(uhci_td_t, td_status), 3038 sizeof(std->td.td_status), 3039 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3040 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3041 usb_syncmem(&std->dma, 3042 std->offs + offsetof(uhci_td_t, td_status), 3043 sizeof(std->td.td_status), 3044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3045 usb_syncmem(&std->dma, 3046 std->offs + offsetof(uhci_td_t, td_token), 3047 sizeof(std->td.td_token), 3048 BUS_DMASYNC_POSTWRITE); 3049 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3050 if (len > maxlen) 3051 maxlen = len; 3052 if (++n >= UHCI_VFRAMELIST_COUNT) 3053 n = 0; 3054 } 3055 3056 /* and wait until we are sure the hardware has finished. */ 3057 delay(maxlen); 3058 3059 #ifdef DIAGNOSTIC 3060 ux->ux_isdone = true; 3061 #endif 3062 /* Remove from interrupt list. */ 3063 uhci_del_intr_list(sc, ux); 3064 3065 /* Run callback. */ 3066 usb_transfer_complete(xfer); 3067 3068 KASSERT(mutex_owned(&sc->sc_lock)); 3069 } 3070 3071 void 3072 uhci_device_isoc_close(struct usbd_pipe *pipe) 3073 { 3074 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3075 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3076 uhci_soft_td_t *std, *vstd; 3077 struct isoc *isoc; 3078 int i; 3079 3080 KASSERT(mutex_owned(&sc->sc_lock)); 3081 3082 /* 3083 * Make sure all TDs are marked as inactive. 3084 * Wait for completion. 3085 * Unschedule. 3086 * Deallocate. 3087 */ 3088 isoc = &upipe->isoc; 3089 3090 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3091 std = isoc->stds[i]; 3092 usb_syncmem(&std->dma, 3093 std->offs + offsetof(uhci_td_t, td_status), 3094 sizeof(std->td.td_status), 3095 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3096 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3097 usb_syncmem(&std->dma, 3098 std->offs + offsetof(uhci_td_t, td_status), 3099 sizeof(std->td.td_status), 3100 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3101 } 3102 /* wait for completion */ 3103 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3104 3105 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3106 std = isoc->stds[i]; 3107 for (vstd = sc->sc_vframes[i].htd; 3108 vstd != NULL && vstd->link.std != std; 3109 vstd = vstd->link.std) 3110 ; 3111 if (vstd == NULL) { 3112 /*panic*/ 3113 printf("%s: %p not found\n", __func__, std); 3114 mutex_exit(&sc->sc_lock); 3115 return; 3116 } 3117 vstd->link = std->link; 3118 usb_syncmem(&std->dma, 3119 std->offs + offsetof(uhci_td_t, td_link), 3120 sizeof(std->td.td_link), 3121 BUS_DMASYNC_POSTWRITE); 3122 vstd->td.td_link = std->td.td_link; 3123 usb_syncmem(&vstd->dma, 3124 vstd->offs + offsetof(uhci_td_t, td_link), 3125 sizeof(vstd->td.td_link), 3126 BUS_DMASYNC_PREWRITE); 3127 uhci_free_std_locked(sc, std); 3128 } 3129 3130 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3131 } 3132 3133 usbd_status 3134 uhci_setup_isoc(struct usbd_pipe *pipe) 3135 { 3136 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3137 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3138 int addr = upipe->pipe.up_dev->ud_addr; 3139 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3140 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3141 uhci_soft_td_t *std, *vstd; 3142 uint32_t token; 3143 struct isoc *isoc; 3144 int i; 3145 3146 isoc = &upipe->isoc; 3147 3148 isoc->stds = kmem_alloc( 3149 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3150 if (isoc->stds == NULL) 3151 return USBD_NOMEM; 3152 3153 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3154 UHCI_TD_OUT(0, endpt, addr, 0); 3155 3156 /* Allocate the TDs and mark as inactive; */ 3157 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3158 std = uhci_alloc_std(sc); 3159 if (std == 0) 3160 goto bad; 3161 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3162 std->td.td_token = htole32(token); 3163 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3164 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3165 isoc->stds[i] = std; 3166 } 3167 3168 mutex_enter(&sc->sc_lock); 3169 3170 /* Insert TDs into schedule. */ 3171 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3172 std = isoc->stds[i]; 3173 vstd = sc->sc_vframes[i].htd; 3174 usb_syncmem(&vstd->dma, 3175 vstd->offs + offsetof(uhci_td_t, td_link), 3176 sizeof(vstd->td.td_link), 3177 BUS_DMASYNC_POSTWRITE); 3178 std->link = vstd->link; 3179 std->td.td_link = vstd->td.td_link; 3180 usb_syncmem(&std->dma, 3181 std->offs + offsetof(uhci_td_t, td_link), 3182 sizeof(std->td.td_link), 3183 BUS_DMASYNC_PREWRITE); 3184 vstd->link.std = std; 3185 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3186 usb_syncmem(&vstd->dma, 3187 vstd->offs + offsetof(uhci_td_t, td_link), 3188 sizeof(vstd->td.td_link), 3189 BUS_DMASYNC_PREWRITE); 3190 } 3191 mutex_exit(&sc->sc_lock); 3192 3193 isoc->next = -1; 3194 isoc->inuse = 0; 3195 3196 return USBD_NORMAL_COMPLETION; 3197 3198 bad: 3199 while (--i >= 0) 3200 uhci_free_std(sc, isoc->stds[i]); 3201 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3202 return USBD_NOMEM; 3203 } 3204 3205 void 3206 uhci_device_isoc_done(struct usbd_xfer *xfer) 3207 { 3208 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3209 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3210 int i, offs; 3211 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3212 3213 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3214 DPRINTFN(4, "length=%jd, ux_state=0x%08jx", 3215 xfer->ux_actlen, xfer->ux_state, 0, 0); 3216 3217 #ifdef DIAGNOSTIC 3218 if (ux->ux_stdend == NULL) { 3219 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3220 #ifdef UHCI_DEBUG 3221 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3222 uhci_dump_ii(ux); 3223 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3224 #endif 3225 return; 3226 } 3227 #endif 3228 3229 /* Turn off the interrupt since it is active even if the TD is not. */ 3230 usb_syncmem(&ux->ux_stdend->dma, 3231 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3232 sizeof(ux->ux_stdend->td.td_status), 3233 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3234 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3235 usb_syncmem(&ux->ux_stdend->dma, 3236 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3237 sizeof(ux->ux_stdend->td.td_status), 3238 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3239 3240 offs = 0; 3241 for (i = 0; i < xfer->ux_nframes; i++) { 3242 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3243 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3244 offs += xfer->ux_frlengths[i]; 3245 } 3246 } 3247 3248 void 3249 uhci_device_intr_done(struct usbd_xfer *xfer) 3250 { 3251 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 3252 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3253 uhci_soft_qh_t *sqh; 3254 int i, npoll; 3255 3256 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3257 DPRINTFN(5, "length=%jd", xfer->ux_actlen, 0, 0, 0); 3258 3259 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3260 3261 npoll = upipe->intr.npoll; 3262 for (i = 0; i < npoll; i++) { 3263 sqh = upipe->intr.qhs[i]; 3264 sqh->elink = NULL; 3265 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3266 usb_syncmem(&sqh->dma, 3267 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3268 sizeof(sqh->qh.qh_elink), 3269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3270 } 3271 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3272 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3273 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3274 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3275 } 3276 3277 /* Deallocate request data structures */ 3278 void 3279 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3280 { 3281 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3282 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3283 int len = UGETW(xfer->ux_request.wLength); 3284 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3285 3286 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3287 3288 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3289 3290 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3291 3292 /* XXXNH move to uhci_idone??? */ 3293 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3294 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3295 else 3296 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3297 3298 if (len) { 3299 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3300 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3301 } 3302 usb_syncmem(&upipe->ctrl.reqdma, 0, 3303 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3304 3305 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3306 } 3307 3308 /* Deallocate request data structures */ 3309 void 3310 uhci_device_bulk_done(struct usbd_xfer *xfer) 3311 { 3312 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3313 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3314 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3315 int endpt = ed->bEndpointAddress; 3316 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3317 3318 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3319 DPRINTFN(5, "xfer=%#jx sc=%#jx upipe=%#jx", (uintptr_t)xfer, 3320 (uintptr_t)sc, (uintptr_t)upipe, 0); 3321 3322 KASSERT(mutex_owned(&sc->sc_lock)); 3323 3324 uhci_remove_bulk(sc, upipe->bulk.sqh); 3325 3326 if (xfer->ux_length) { 3327 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3328 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3329 } 3330 3331 DPRINTFN(5, "length=%jd", xfer->ux_actlen, 0, 0, 0); 3332 } 3333 3334 /* Add interrupt QH, called with vflock. */ 3335 void 3336 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3337 { 3338 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3339 uhci_soft_qh_t *eqh; 3340 3341 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3342 DPRINTFN(4, "n=%jd sqh=%#jx", sqh->pos, (uintptr_t)sqh, 0, 0); 3343 3344 eqh = vf->eqh; 3345 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3346 sizeof(eqh->qh.qh_hlink), 3347 BUS_DMASYNC_POSTWRITE); 3348 sqh->hlink = eqh->hlink; 3349 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3350 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3351 sizeof(sqh->qh.qh_hlink), 3352 BUS_DMASYNC_PREWRITE); 3353 eqh->hlink = sqh; 3354 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3355 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3356 sizeof(eqh->qh.qh_hlink), 3357 BUS_DMASYNC_PREWRITE); 3358 vf->eqh = sqh; 3359 vf->bandwidth++; 3360 } 3361 3362 /* Remove interrupt QH. */ 3363 void 3364 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3365 { 3366 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3367 uhci_soft_qh_t *pqh; 3368 3369 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3370 DPRINTFN(4, "n=%jd sqh=%#jx", sqh->pos, (uintptr_t)sqh, 0, 0); 3371 3372 /* See comment in uhci_remove_ctrl() */ 3373 3374 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3375 sizeof(sqh->qh.qh_elink), 3376 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3377 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3378 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3379 usb_syncmem(&sqh->dma, 3380 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3381 sizeof(sqh->qh.qh_elink), 3382 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3383 delay(UHCI_QH_REMOVE_DELAY); 3384 } 3385 3386 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3387 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3388 sizeof(sqh->qh.qh_hlink), 3389 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3390 pqh->hlink = sqh->hlink; 3391 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3392 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3393 sizeof(pqh->qh.qh_hlink), 3394 BUS_DMASYNC_PREWRITE); 3395 delay(UHCI_QH_REMOVE_DELAY); 3396 if (vf->eqh == sqh) 3397 vf->eqh = pqh; 3398 vf->bandwidth--; 3399 } 3400 3401 usbd_status 3402 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3403 { 3404 uhci_soft_qh_t *sqh; 3405 int i, npoll; 3406 u_int bestbw, bw, bestoffs, offs; 3407 3408 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3409 DPRINTFN(2, "pipe=%#jx", (uintptr_t)upipe, 0, 0, 0); 3410 if (ival == 0) { 3411 printf("%s: 0 interval\n", __func__); 3412 return USBD_INVAL; 3413 } 3414 3415 if (ival > UHCI_VFRAMELIST_COUNT) 3416 ival = UHCI_VFRAMELIST_COUNT; 3417 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 3418 DPRINTF("ival=%jd npoll=%jd", ival, npoll, 0, 0); 3419 3420 upipe->intr.npoll = npoll; 3421 upipe->intr.qhs = 3422 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3423 3424 /* 3425 * Figure out which offset in the schedule that has most 3426 * bandwidth left over. 3427 */ 3428 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3429 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3430 for (bw = i = 0; i < npoll; i++) 3431 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3432 if (bw < bestbw) { 3433 bestbw = bw; 3434 bestoffs = offs; 3435 } 3436 } 3437 DPRINTF("bw=%jd offs=%jd", bestbw, bestoffs, 0, 0); 3438 for (i = 0; i < npoll; i++) { 3439 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3440 sqh->elink = NULL; 3441 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3442 usb_syncmem(&sqh->dma, 3443 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3444 sizeof(sqh->qh.qh_elink), 3445 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3446 sqh->pos = MOD(i * ival + bestoffs); 3447 } 3448 #undef MOD 3449 3450 mutex_enter(&sc->sc_lock); 3451 /* Enter QHs into the controller data structures. */ 3452 for (i = 0; i < npoll; i++) 3453 uhci_add_intr(sc, upipe->intr.qhs[i]); 3454 mutex_exit(&sc->sc_lock); 3455 3456 DPRINTFN(5, "returns %#jx", (uintptr_t)upipe, 0, 0, 0); 3457 3458 return USBD_NORMAL_COMPLETION; 3459 } 3460 3461 /* Open a new pipe. */ 3462 usbd_status 3463 uhci_open(struct usbd_pipe *pipe) 3464 { 3465 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3466 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3467 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3468 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3469 usbd_status err = USBD_NOMEM; 3470 int ival; 3471 3472 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3473 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", 3474 (uintptr_t)pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, 3475 bus->ub_rhaddr); 3476 3477 if (sc->sc_dying) 3478 return USBD_IOERROR; 3479 3480 upipe->aborting = 0; 3481 /* toggle state needed for bulk endpoints */ 3482 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3483 3484 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3485 switch (ed->bEndpointAddress) { 3486 case USB_CONTROL_ENDPOINT: 3487 pipe->up_methods = &roothub_ctrl_methods; 3488 break; 3489 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3490 pipe->up_methods = &uhci_root_intr_methods; 3491 break; 3492 default: 3493 return USBD_INVAL; 3494 } 3495 } else { 3496 switch (ed->bmAttributes & UE_XFERTYPE) { 3497 case UE_CONTROL: 3498 pipe->up_methods = &uhci_device_ctrl_methods; 3499 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3500 if (upipe->ctrl.sqh == NULL) 3501 goto bad; 3502 upipe->ctrl.setup = uhci_alloc_std(sc); 3503 if (upipe->ctrl.setup == NULL) { 3504 uhci_free_sqh(sc, upipe->ctrl.sqh); 3505 goto bad; 3506 } 3507 upipe->ctrl.stat = uhci_alloc_std(sc); 3508 if (upipe->ctrl.stat == NULL) { 3509 uhci_free_sqh(sc, upipe->ctrl.sqh); 3510 uhci_free_std(sc, upipe->ctrl.setup); 3511 goto bad; 3512 } 3513 err = usb_allocmem(&sc->sc_bus, 3514 sizeof(usb_device_request_t), 3515 0, &upipe->ctrl.reqdma); 3516 if (err) { 3517 uhci_free_sqh(sc, upipe->ctrl.sqh); 3518 uhci_free_std(sc, upipe->ctrl.setup); 3519 uhci_free_std(sc, upipe->ctrl.stat); 3520 goto bad; 3521 } 3522 break; 3523 case UE_INTERRUPT: 3524 pipe->up_methods = &uhci_device_intr_methods; 3525 ival = pipe->up_interval; 3526 if (ival == USBD_DEFAULT_INTERVAL) 3527 ival = ed->bInterval; 3528 return uhci_device_setintr(sc, upipe, ival); 3529 case UE_ISOCHRONOUS: 3530 pipe->up_serialise = false; 3531 pipe->up_methods = &uhci_device_isoc_methods; 3532 return uhci_setup_isoc(pipe); 3533 case UE_BULK: 3534 pipe->up_methods = &uhci_device_bulk_methods; 3535 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3536 if (upipe->bulk.sqh == NULL) 3537 goto bad; 3538 break; 3539 } 3540 } 3541 return USBD_NORMAL_COMPLETION; 3542 3543 bad: 3544 return USBD_NOMEM; 3545 } 3546 3547 /* 3548 * Data structures and routines to emulate the root hub. 3549 */ 3550 /* 3551 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3552 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3553 * should not be used by the USB subsystem. As we cannot issue a 3554 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3555 * will be enabled as part of the reset. 3556 * 3557 * On the VT83C572, the port cannot be successfully enabled until the 3558 * outstanding "port enable change" and "connection status change" 3559 * events have been reset. 3560 */ 3561 Static usbd_status 3562 uhci_portreset(uhci_softc_t *sc, int index) 3563 { 3564 int lim, port, x; 3565 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3566 3567 if (index == 1) 3568 port = UHCI_PORTSC1; 3569 else if (index == 2) 3570 port = UHCI_PORTSC2; 3571 else 3572 return USBD_IOERROR; 3573 3574 x = URWMASK(UREAD2(sc, port)); 3575 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3576 3577 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3578 3579 DPRINTF("uhci port %jd reset, status0 = 0x%04jx", index, 3580 UREAD2(sc, port), 0, 0); 3581 3582 x = URWMASK(UREAD2(sc, port)); 3583 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3584 3585 delay(100); 3586 3587 DPRINTF("uhci port %jd reset, status1 = 0x%04jx", index, 3588 UREAD2(sc, port), 0, 0); 3589 3590 x = URWMASK(UREAD2(sc, port)); 3591 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3592 3593 for (lim = 10; --lim > 0;) { 3594 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3595 3596 x = UREAD2(sc, port); 3597 DPRINTF("uhci port %jd iteration %ju, status = 0x%04jx", index, 3598 lim, x, 0); 3599 3600 if (!(x & UHCI_PORTSC_CCS)) { 3601 /* 3602 * No device is connected (or was disconnected 3603 * during reset). Consider the port reset. 3604 * The delay must be long enough to ensure on 3605 * the initial iteration that the device 3606 * connection will have been registered. 50ms 3607 * appears to be sufficient, but 20ms is not. 3608 */ 3609 DPRINTFN(3, "uhci port %jd loop %ju, device detached", 3610 index, lim, 0, 0); 3611 break; 3612 } 3613 3614 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3615 /* 3616 * Port enabled changed and/or connection 3617 * status changed were set. Reset either or 3618 * both raised flags (by writing a 1 to that 3619 * bit), and wait again for state to settle. 3620 */ 3621 UWRITE2(sc, port, URWMASK(x) | 3622 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3623 continue; 3624 } 3625 3626 if (x & UHCI_PORTSC_PE) 3627 /* Port is enabled */ 3628 break; 3629 3630 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3631 } 3632 3633 DPRINTFN(3, "uhci port %jd reset, status2 = 0x%04jx", index, 3634 UREAD2(sc, port), 0, 0); 3635 3636 if (lim <= 0) { 3637 DPRINTF("uhci port %jd reset timed out", index, 3638 0, 0, 0); 3639 return USBD_TIMEOUT; 3640 } 3641 3642 sc->sc_isreset = 1; 3643 return USBD_NORMAL_COMPLETION; 3644 } 3645 3646 Static int 3647 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3648 void *buf, int buflen) 3649 { 3650 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3651 int port, x; 3652 int status, change, totlen = 0; 3653 uint16_t len, value, index; 3654 usb_port_status_t ps; 3655 usbd_status err; 3656 3657 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3658 3659 if (sc->sc_dying) 3660 return -1; 3661 3662 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, 3663 req->bRequest, 0, 0); 3664 3665 len = UGETW(req->wLength); 3666 value = UGETW(req->wValue); 3667 index = UGETW(req->wIndex); 3668 3669 #define C(x,y) ((x) | ((y) << 8)) 3670 switch (C(req->bRequest, req->bmRequestType)) { 3671 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3672 DPRINTF("wValue=0x%04jx", value, 0, 0, 0); 3673 if (len == 0) 3674 break; 3675 switch (value) { 3676 case C(0, UDESC_DEVICE): { 3677 usb_device_descriptor_t devd; 3678 3679 totlen = min(buflen, sizeof(devd)); 3680 memcpy(&devd, buf, totlen); 3681 USETW(devd.idVendor, sc->sc_id_vendor); 3682 memcpy(buf, &devd, totlen); 3683 break; 3684 } 3685 case C(1, UDESC_STRING): 3686 #define sd ((usb_string_descriptor_t *)buf) 3687 /* Vendor */ 3688 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3689 break; 3690 case C(2, UDESC_STRING): 3691 /* Product */ 3692 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3693 break; 3694 #undef sd 3695 default: 3696 /* default from usbroothub */ 3697 return buflen; 3698 } 3699 break; 3700 3701 /* Hub requests */ 3702 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3703 break; 3704 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3705 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 3706 value, 0, 0); 3707 if (index == 1) 3708 port = UHCI_PORTSC1; 3709 else if (index == 2) 3710 port = UHCI_PORTSC2; 3711 else { 3712 return -1; 3713 } 3714 switch(value) { 3715 case UHF_PORT_ENABLE: 3716 x = URWMASK(UREAD2(sc, port)); 3717 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3718 break; 3719 case UHF_PORT_SUSPEND: 3720 x = URWMASK(UREAD2(sc, port)); 3721 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3722 break; 3723 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3724 /* see USB2 spec ch. 7.1.7.7 */ 3725 usb_delay_ms(&sc->sc_bus, 20); 3726 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3727 /* 10ms resume delay must be provided by caller */ 3728 break; 3729 case UHF_PORT_RESET: 3730 x = URWMASK(UREAD2(sc, port)); 3731 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3732 break; 3733 case UHF_C_PORT_CONNECTION: 3734 x = URWMASK(UREAD2(sc, port)); 3735 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3736 break; 3737 case UHF_C_PORT_ENABLE: 3738 x = URWMASK(UREAD2(sc, port)); 3739 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3740 break; 3741 case UHF_C_PORT_OVER_CURRENT: 3742 x = URWMASK(UREAD2(sc, port)); 3743 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3744 break; 3745 case UHF_C_PORT_RESET: 3746 sc->sc_isreset = 0; 3747 break; 3748 case UHF_PORT_CONNECTION: 3749 case UHF_PORT_OVER_CURRENT: 3750 case UHF_PORT_POWER: 3751 case UHF_PORT_LOW_SPEED: 3752 case UHF_C_PORT_SUSPEND: 3753 default: 3754 return -1; 3755 } 3756 break; 3757 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3758 if (index == 1) 3759 port = UHCI_PORTSC1; 3760 else if (index == 2) 3761 port = UHCI_PORTSC2; 3762 else { 3763 return -1; 3764 } 3765 if (len > 0) { 3766 *(uint8_t *)buf = 3767 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3768 totlen = 1; 3769 } 3770 break; 3771 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3772 if (len == 0) 3773 break; 3774 if ((value & 0xff) != 0) { 3775 return -1; 3776 } 3777 usb_hub_descriptor_t hubd; 3778 3779 totlen = min(buflen, sizeof(hubd)); 3780 memcpy(&hubd, buf, totlen); 3781 hubd.bNbrPorts = 2; 3782 memcpy(buf, &hubd, totlen); 3783 break; 3784 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3785 if (len != 4) { 3786 return -1; 3787 } 3788 memset(buf, 0, len); 3789 totlen = len; 3790 break; 3791 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3792 if (index == 1) 3793 port = UHCI_PORTSC1; 3794 else if (index == 2) 3795 port = UHCI_PORTSC2; 3796 else { 3797 return -1; 3798 } 3799 if (len != 4) { 3800 return -1; 3801 } 3802 x = UREAD2(sc, port); 3803 status = change = 0; 3804 if (x & UHCI_PORTSC_CCS) 3805 status |= UPS_CURRENT_CONNECT_STATUS; 3806 if (x & UHCI_PORTSC_CSC) 3807 change |= UPS_C_CONNECT_STATUS; 3808 if (x & UHCI_PORTSC_PE) 3809 status |= UPS_PORT_ENABLED; 3810 if (x & UHCI_PORTSC_POEDC) 3811 change |= UPS_C_PORT_ENABLED; 3812 if (x & UHCI_PORTSC_OCI) 3813 status |= UPS_OVERCURRENT_INDICATOR; 3814 if (x & UHCI_PORTSC_OCIC) 3815 change |= UPS_C_OVERCURRENT_INDICATOR; 3816 if (x & UHCI_PORTSC_SUSP) 3817 status |= UPS_SUSPEND; 3818 if (x & UHCI_PORTSC_LSDA) 3819 status |= UPS_LOW_SPEED; 3820 status |= UPS_PORT_POWER; 3821 if (sc->sc_isreset) 3822 change |= UPS_C_PORT_RESET; 3823 USETW(ps.wPortStatus, status); 3824 USETW(ps.wPortChange, change); 3825 totlen = min(len, sizeof(ps)); 3826 memcpy(buf, &ps, totlen); 3827 break; 3828 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3829 return -1; 3830 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3831 break; 3832 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3833 if (index == 1) 3834 port = UHCI_PORTSC1; 3835 else if (index == 2) 3836 port = UHCI_PORTSC2; 3837 else { 3838 return -1; 3839 } 3840 switch(value) { 3841 case UHF_PORT_ENABLE: 3842 x = URWMASK(UREAD2(sc, port)); 3843 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3844 break; 3845 case UHF_PORT_SUSPEND: 3846 x = URWMASK(UREAD2(sc, port)); 3847 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3848 break; 3849 case UHF_PORT_RESET: 3850 err = uhci_portreset(sc, index); 3851 if (err != USBD_NORMAL_COMPLETION) 3852 return -1; 3853 return 0; 3854 case UHF_PORT_POWER: 3855 /* Pretend we turned on power */ 3856 return 0; 3857 case UHF_C_PORT_CONNECTION: 3858 case UHF_C_PORT_ENABLE: 3859 case UHF_C_PORT_OVER_CURRENT: 3860 case UHF_PORT_CONNECTION: 3861 case UHF_PORT_OVER_CURRENT: 3862 case UHF_PORT_LOW_SPEED: 3863 case UHF_C_PORT_SUSPEND: 3864 case UHF_C_PORT_RESET: 3865 default: 3866 return -1; 3867 } 3868 break; 3869 default: 3870 /* default from usbroothub */ 3871 DPRINTF("returning %jd (usbroothub default)", 3872 buflen, 0, 0, 0); 3873 return buflen; 3874 } 3875 3876 DPRINTF("returning %jd", totlen, 0, 0, 0); 3877 3878 return totlen; 3879 } 3880 3881 /* Abort a root interrupt request. */ 3882 void 3883 uhci_root_intr_abort(struct usbd_xfer *xfer) 3884 { 3885 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3886 3887 KASSERT(mutex_owned(&sc->sc_lock)); 3888 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3889 3890 callout_stop(&sc->sc_poll_handle); 3891 sc->sc_intr_xfer = NULL; 3892 3893 xfer->ux_status = USBD_CANCELLED; 3894 #ifdef DIAGNOSTIC 3895 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3896 #endif 3897 usb_transfer_complete(xfer); 3898 } 3899 3900 usbd_status 3901 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3902 { 3903 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3904 usbd_status err; 3905 3906 /* Insert last in queue. */ 3907 mutex_enter(&sc->sc_lock); 3908 err = usb_insert_transfer(xfer); 3909 mutex_exit(&sc->sc_lock); 3910 if (err) 3911 return err; 3912 3913 /* 3914 * Pipe isn't running (otherwise err would be USBD_INPROG), 3915 * start first 3916 */ 3917 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3918 } 3919 3920 /* Start a transfer on the root interrupt pipe */ 3921 usbd_status 3922 uhci_root_intr_start(struct usbd_xfer *xfer) 3923 { 3924 struct usbd_pipe *pipe = xfer->ux_pipe; 3925 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3926 unsigned int ival; 3927 3928 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3929 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3930 xfer->ux_flags, 0); 3931 3932 if (sc->sc_dying) 3933 return USBD_IOERROR; 3934 3935 /* XXX temporary variable needed to avoid gcc3 warning */ 3936 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3937 sc->sc_ival = mstohz(ival); 3938 callout_reset(&sc->sc_poll_handle, sc->sc_ival, uhci_poll_hub, xfer); 3939 sc->sc_intr_xfer = xfer; 3940 return USBD_IN_PROGRESS; 3941 } 3942 3943 /* Close the root interrupt pipe. */ 3944 void 3945 uhci_root_intr_close(struct usbd_pipe *pipe) 3946 { 3947 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3948 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3949 3950 KASSERT(mutex_owned(&sc->sc_lock)); 3951 3952 callout_stop(&sc->sc_poll_handle); 3953 sc->sc_intr_xfer = NULL; 3954 } 3955
Indexes created Tue Sep 30 17:09:57 GMT 2025