uhci.c revision 1.3
1 /* $NetBSD: uhci.c,v 1.3 1998/07/23 00:27:36 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Author: Lennart Augustsson <augustss (at) carlstedt.se> 8 * Carlstedt Research & Technology 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Universal Host Controller driver. 41 * Handles PIIX3 and PIIX4. 42 * 43 * Data sheets: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 44 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 45 * UHCI spec: http://www.intel.com/design/usb/uhci11d.pdf 46 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 58 #include <dev/usb/usb.h> 59 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 63 #include <dev/usb/usb_quirks.h> 64 65 #include <machine/bus.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 70 #define MS_TO_TICKS(ms) ((ms) * hz / 1000) 71 72 struct uhci_pipe { 73 struct usbd_pipe pipe; 74 uhci_intr_info_t *iinfo; 75 int newtoggle; 76 /* Info needed for different pipe kinds. */ 77 union { 78 /* Control pipe */ 79 struct { 80 uhci_soft_qh_t *sqh; 81 uhci_dma_t reqdma; 82 uhci_dma_t datadma; 83 uhci_soft_td_t *setup, *stat, *xferend; 84 u_int length; 85 } ctl; 86 /* Interrupt pipe */ 87 struct { 88 uhci_dma_t datadma; 89 int npoll; 90 uhci_soft_qh_t **qhs; 91 } intr; 92 /* Bulk pipe */ 93 struct { 94 uhci_soft_qh_t *sqh; 95 uhci_dma_t datadma; 96 u_int length; 97 int isread; 98 } bulk; 99 } u; 100 }; 101 102 /* 103 * The uhci_intr_info free list can be global since they contain 104 * no dma specific data. The other free lists do. 105 */ 106 int uhci_global_init_done = 0; 107 LIST_HEAD(, uhci_intr_info) uhci_ii_free; 108 109 void uhci_busreset __P((uhci_softc_t *)); 110 usbd_status uhci_allocmem __P((uhci_softc_t *,size_t,size_t,uhci_dma_t *)); 111 void uhci_freemem __P((uhci_softc_t *, uhci_dma_t *)); 112 void uhci_run __P((uhci_softc_t *, int run)); 113 uhci_soft_td_t *uhci_alloc_std __P((uhci_softc_t *)); 114 void uhci_free_std __P((uhci_softc_t *, uhci_soft_td_t *)); 115 uhci_soft_qh_t *uhci_alloc_sqh __P((uhci_softc_t *)); 116 void uhci_free_sqh __P((uhci_softc_t *, uhci_soft_qh_t *)); 117 uhci_intr_info_t *uhci_alloc_intr_info __P((uhci_softc_t *)); 118 void uhci_free_intr_info __P((uhci_intr_info_t *ii)); 119 void uhci_enter_ctl_q __P((uhci_softc_t *, uhci_soft_qh_t *, 120 uhci_intr_info_t *)); 121 void uhci_exit_ctl_q __P((uhci_softc_t *, uhci_soft_qh_t *)); 122 123 void uhci_free_std_chain __P((uhci_softc_t *, 124 uhci_soft_td_t *, uhci_soft_td_t *)); 125 usbd_status uhci_alloc_std_chain __P((struct uhci_pipe *, uhci_softc_t *, 126 int, int, uhci_dma_t *, 127 uhci_soft_td_t **, 128 uhci_soft_td_t **)); 129 void uhci_timo __P((void *)); 130 void uhci_waitintr __P((uhci_softc_t *, usbd_request_handle)); 131 void uhci_check_intr __P((uhci_softc_t *, uhci_intr_info_t *)); 132 void uhci_ii_done __P((uhci_intr_info_t *, int)); 133 void uhci_timeout __P((void *)); 134 void uhci_wakeup_ctrl __P((void *, int, int, void *, int)); 135 void uhci_lock_frames __P((uhci_softc_t *)); 136 void uhci_unlock_frames __P((uhci_softc_t *)); 137 void uhci_add_ctrl __P((uhci_softc_t *, uhci_soft_qh_t *)); 138 void uhci_add_bulk __P((uhci_softc_t *, uhci_soft_qh_t *)); 139 void uhci_remove_ctrl __P((uhci_softc_t *, uhci_soft_qh_t *)); 140 void uhci_remove_bulk __P((uhci_softc_t *, uhci_soft_qh_t *)); 141 int uhci_str __P((usb_string_descriptor_t *, int, char *)); 142 143 void uhci_device_close __P((struct uhci_pipe *)); 144 145 void uhci_wakeup_cb __P((usbd_request_handle reqh)); 146 147 usbd_status uhci_device_ctrl_transfer __P((usbd_request_handle)); 148 void uhci_device_ctrl_abort __P((usbd_request_handle)); 149 void uhci_device_ctrl_close __P((usbd_pipe_handle)); 150 usbd_status uhci_device_intr_transfer __P((usbd_request_handle)); 151 void uhci_device_intr_abort __P((usbd_request_handle)); 152 void uhci_device_intr_close __P((usbd_pipe_handle)); 153 usbd_status uhci_device_bulk_transfer __P((usbd_request_handle)); 154 void uhci_device_bulk_abort __P((usbd_request_handle)); 155 void uhci_device_bulk_close __P((usbd_pipe_handle)); 156 157 usbd_status uhci_root_ctrl_transfer __P((usbd_request_handle)); 158 void uhci_root_ctrl_abort __P((usbd_request_handle)); 159 void uhci_root_ctrl_close __P((usbd_pipe_handle)); 160 usbd_status uhci_root_intr_transfer __P((usbd_request_handle)); 161 void uhci_root_intr_abort __P((usbd_request_handle)); 162 void uhci_root_intr_close __P((usbd_pipe_handle)); 163 164 usbd_status uhci_open __P((usbd_pipe_handle)); 165 166 usbd_status uhci_device_request __P((usbd_request_handle reqh)); 167 void uhci_ctrl_done __P((uhci_intr_info_t *ii)); 168 void uhci_bulk_done __P((uhci_intr_info_t *ii)); 169 170 void uhci_add_intr __P((uhci_softc_t *, int, uhci_soft_qh_t *)); 171 void uhci_remove_intr __P((uhci_softc_t *, int, uhci_soft_qh_t *)); 172 usbd_status uhci_device_setintr __P((uhci_softc_t *sc, 173 struct uhci_pipe *pipe, int ival)); 174 void uhci_intr_done __P((uhci_intr_info_t *ii)); 175 176 #ifdef USB_DEBUG 177 static void uhci_dumpregs __P((uhci_softc_t *)); 178 void uhci_dump_tds __P((uhci_soft_td_t *)); 179 void uhci_dump_qh __P((uhci_soft_qh_t *)); 180 void uhci_dump __P((void)); 181 void uhci_dump_td __P((uhci_soft_td_t *)); 182 #endif 183 184 #define UWRITE2(sc, r, x) bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)) 185 #define UWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 186 #define UREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 187 #define UREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 188 189 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 190 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 191 192 #define UHCI_RESET_TIMEOUT 100 /* reset timeout */ 193 #define UHCI_CTRL_TIMEOUT 500 /* control transaction timeout */ 194 #define UHCI_ISO_DELAY 50 /* delay of start of iso */ 195 196 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 197 198 #define UHCI_INTR_ENDPT 1 199 200 struct usbd_methods uhci_root_ctrl_methods = { 201 uhci_root_ctrl_transfer, 202 uhci_root_ctrl_abort, 203 uhci_root_ctrl_close, 204 }; 205 206 struct usbd_methods uhci_root_intr_methods = { 207 uhci_root_intr_transfer, 208 uhci_root_intr_abort, 209 uhci_root_intr_close, 210 }; 211 212 struct usbd_methods uhci_device_ctrl_methods = { 213 uhci_device_ctrl_transfer, 214 uhci_device_ctrl_abort, 215 uhci_device_ctrl_close, 216 }; 217 218 struct usbd_methods uhci_device_intr_methods = { 219 uhci_device_intr_transfer, 220 uhci_device_intr_abort, 221 uhci_device_intr_close, 222 }; 223 224 struct usbd_methods uhci_device_bulk_methods = { 225 uhci_device_bulk_transfer, 226 uhci_device_bulk_abort, 227 uhci_device_bulk_close, 228 }; 229 230 void 231 uhci_busreset(sc) 232 uhci_softc_t *sc; 233 { 234 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 235 usbd_delay_ms(USB_RESET_DELAY); /* wait at least 10ms */ 236 UHCICMD(sc, 0); /* do nothing */ 237 } 238 239 usbd_status 240 uhci_init(sc) 241 uhci_softc_t *sc; 242 { 243 usbd_status r; 244 int i, j; 245 uhci_soft_qh_t *csqh, *bsqh, *sqh; 246 uhci_soft_td_t *std; 247 uhci_dma_t dma; 248 249 DPRINTFN(1,("uhci_init: start\n")); 250 251 if (!uhci_global_init_done) { 252 uhci_global_init_done = 1; 253 LIST_INIT(&uhci_ii_free); 254 } 255 256 #if defined(USB_DEBUG) 257 if (uhcidebug > 2) 258 uhci_dumpregs(sc); 259 #endif 260 261 uhci_run(sc, 0); /* stop the controller */ 262 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 263 264 /* Allocate and initialize real frame array. */ 265 r = uhci_allocmem(sc, UHCI_FRAMELIST_COUNT * 266 sizeof(uhci_physaddr_t), 267 UHCI_FRAMELIST_ALIGN, &dma); 268 if (r != USBD_NORMAL_COMPLETION) 269 return (r); 270 sc->sc_pframes = KERNADDR(&dma); 271 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 272 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&dma)); /* set frame list */ 273 274 uhci_busreset(sc); 275 276 /* Allocate the dummy QH where bulk traffic will be queued. */ 277 bsqh = uhci_alloc_sqh(sc); 278 if (!bsqh) 279 return (USBD_NOMEM); 280 bsqh->qh->qh_hlink = UHCI_PTR_T; /* end of QH chain */ 281 bsqh->qh->qh_elink = UHCI_PTR_T; 282 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 283 284 /* Allocate the dummy QH where control traffic will be queued. */ 285 csqh = uhci_alloc_sqh(sc); 286 if (!csqh) 287 return (USBD_NOMEM); 288 csqh->qh->hlink = bsqh; 289 csqh->qh->qh_hlink = bsqh->physaddr | UHCI_PTR_Q; 290 csqh->qh->qh_elink = UHCI_PTR_T; 291 sc->sc_ctl_start = sc->sc_ctl_end = csqh; 292 293 /* 294 * Make all (virtual) frame list pointers point to the interrupt 295 * queue heads and the interrupt queue heads at the control 296 * queue head and point the physical frame list to the virtual. 297 */ 298 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 299 std = uhci_alloc_std(sc); 300 sqh = uhci_alloc_sqh(sc); 301 if (!std || !sqh) 302 return (ENOMEM); 303 std->td->link.sqh = sqh; 304 std->td->td_link = sqh->physaddr | UHCI_PTR_Q; 305 std->td->td_status = UHCI_TD_IOS; /* iso, inactive */ 306 std->td->td_token = 0; 307 std->td->td_buffer = 0; 308 sqh->qh->hlink = csqh; 309 sqh->qh->qh_hlink = csqh->physaddr | UHCI_PTR_Q; 310 sqh->qh->elink = 0; 311 sqh->qh->qh_elink = UHCI_PTR_T; 312 sc->sc_vframes[i].htd = std; 313 sc->sc_vframes[i].etd = std; 314 sc->sc_vframes[i].hqh = sqh; 315 sc->sc_vframes[i].eqh = sqh; 316 for (j = i; 317 j < UHCI_FRAMELIST_COUNT; 318 j += UHCI_VFRAMELIST_COUNT) 319 sc->sc_pframes[j] = std->physaddr; 320 } 321 322 LIST_INIT(&sc->sc_intrhead); 323 324 /* Set up the bus struct. */ 325 sc->sc_bus.open_pipe = uhci_open; 326 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 327 328 DPRINTFN(1,("uhci_init: enabling\n")); 329 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 330 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 331 332 uhci_run(sc, 1); /* and here we go... */ 333 return (USBD_NORMAL_COMPLETION); 334 } 335 336 #ifdef USB_DEBUG 337 static void 338 uhci_dumpregs(sc) 339 uhci_softc_t *sc; 340 { 341 printf("%s: regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 342 sc->sc_bus.bdev.dv_xname, 343 UREAD2(sc, UHCI_CMD), 344 UREAD2(sc, UHCI_STS), 345 UREAD2(sc, UHCI_INTR), 346 UREAD2(sc, UHCI_FRNUM), 347 UREAD2(sc, UHCI_FLBASEADDR), 348 UREAD2(sc, UHCI_SOF), 349 UREAD2(sc, UHCI_PORTSC1), 350 UREAD2(sc, UHCI_PORTSC2)); 351 } 352 353 int uhci_longtd = 1; 354 355 void 356 uhci_dump_td(p) 357 uhci_soft_td_t *p; 358 { 359 printf("TD(%p) at %08lx = 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", 360 p, (long)p->physaddr, 361 (long)p->td->td_link, 362 (long)p->td->td_status, 363 (long)p->td->td_token, 364 (long)p->td->td_buffer); 365 if (uhci_longtd) 366 printf(" %b %b,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d,D=%d,maxlen=%d\n", 367 (long)p->td->td_link, 368 "\20\1T\2Q\3VF", 369 (long)p->td->td_status, 370 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 371 UHCI_TD_GET_ERRCNT(p->td->td_status), 372 UHCI_TD_GET_ACTLEN(p->td->td_status), 373 UHCI_TD_GET_PID(p->td->td_token), 374 UHCI_TD_GET_DEVADDR(p->td->td_token), 375 UHCI_TD_GET_ENDPT(p->td->td_token), 376 UHCI_TD_GET_DT(p->td->td_token), 377 UHCI_TD_GET_MAXLEN(p->td->td_token)); 378 379 } 380 381 void 382 uhci_dump_qh(p) 383 uhci_soft_qh_t *p; 384 { 385 printf("QH(%p) at %08x: hlink=%08x elink=%08x\n", p, (int)p->physaddr, 386 p->qh->qh_hlink, p->qh->qh_elink); 387 } 388 389 #if 0 390 void 391 uhci_dump() 392 { 393 uhci_softc_t *sc = uhci; 394 395 uhci_dumpregs(sc); 396 printf("intrs=%d\n", sc->sc_intrs); 397 printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link); 398 uhci_dump_qh(sc->sc_ctl_start->qh->hlink); 399 } 400 #endif 401 402 void 403 uhci_dump_tds(std) 404 uhci_soft_td_t *std; 405 { 406 uhci_soft_td_t *p; 407 408 for(p = std; p; p = p->td->link.std) 409 uhci_dump_td(p); 410 } 411 #endif 412 413 /* 414 * This routine is executed periodically and simulates interrupts 415 * from the root controller interrupt pipe for port status change. 416 */ 417 void 418 uhci_timo(addr) 419 void *addr; 420 { 421 usbd_request_handle reqh = addr; 422 usbd_pipe_handle pipe = reqh->pipe; 423 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 424 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 425 int s; 426 u_char *p; 427 428 DPRINTFN(15, ("uhci_timo\n")); 429 430 p = KERNADDR(&upipe->u.intr.datadma); 431 p[0] = 0; 432 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 433 p[0] |= 1<<1; 434 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 435 p[0] |= 1<<2; 436 if (p[0] != 0) { 437 reqh->actlen = 1; 438 reqh->status = USBD_NORMAL_COMPLETION; 439 s = splusb(); 440 reqh->xfercb(reqh); 441 splx(s); 442 } 443 if (reqh->pipe->intrreqh == reqh) { 444 timeout(uhci_timo, addr, sc->sc_ival); 445 } else { 446 uhci_freemem(sc, &upipe->u.intr.datadma); 447 } 448 } 449 450 451 void 452 uhci_lock_frames(sc) 453 uhci_softc_t *sc; 454 { 455 int s = splusb(); 456 while (sc->sc_vflock) { 457 sc->sc_vflock |= UHCI_WANT_LOCK; 458 tsleep(&sc->sc_vflock, PRIBIO, "uhcqhl", 0); 459 } 460 sc->sc_vflock = UHCI_HAS_LOCK; 461 splx(s); 462 } 463 464 void 465 uhci_unlock_frames(sc) 466 uhci_softc_t *sc; 467 { 468 int s = splusb(); 469 sc->sc_vflock &= ~UHCI_HAS_LOCK; 470 if (sc->sc_vflock & UHCI_WANT_LOCK) 471 wakeup(&sc->sc_vflock); 472 splx(s); 473 } 474 475 /* 476 * Allocate an interrupt information struct. A free list is kept 477 * for fast allocation. 478 */ 479 uhci_intr_info_t * 480 uhci_alloc_intr_info(sc) 481 uhci_softc_t *sc; 482 { 483 uhci_intr_info_t *ii; 484 485 ii = LIST_FIRST(&uhci_ii_free); 486 if (ii) 487 LIST_REMOVE(ii, list); 488 else { 489 ii = malloc(sizeof(uhci_intr_info_t), M_USBDEV, M_NOWAIT); 490 } 491 ii->sc = sc; 492 return ii; 493 } 494 495 void 496 uhci_free_intr_info(ii) 497 uhci_intr_info_t *ii; 498 { 499 LIST_INSERT_HEAD(&uhci_ii_free, ii, list); /* and put on free list */ 500 } 501 502 /* Add control QH, called at splusb(). */ 503 void 504 uhci_add_ctrl(sc, sqh) 505 uhci_softc_t *sc; 506 uhci_soft_qh_t *sqh; 507 { 508 uhci_qh_t *eqh; 509 510 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 511 eqh = sc->sc_ctl_end->qh; 512 sqh->qh->hlink = eqh->hlink; 513 sqh->qh->qh_hlink = eqh->qh_hlink; 514 eqh->hlink = sqh; 515 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 516 sc->sc_ctl_end = sqh; 517 } 518 519 /* Remove control QH, called at splusb(). */ 520 void 521 uhci_remove_ctrl(sc, sqh) 522 uhci_softc_t *sc; 523 uhci_soft_qh_t *sqh; 524 { 525 uhci_soft_qh_t *pqh; 526 527 DPRINTFN(10, ("uhci_remove_ctrl: sqh=%p\n", sqh)); 528 for (pqh = sc->sc_ctl_start; pqh->qh->hlink != sqh; pqh=pqh->qh->hlink) 529 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 530 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 531 printf("uhci_remove_ctrl: QH not found\n"); 532 return; 533 } 534 #else 535 ; 536 #endif 537 pqh->qh->hlink = sqh->qh->hlink; 538 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 539 if (sc->sc_ctl_end == sqh) 540 sc->sc_ctl_end = pqh; 541 } 542 543 /* Add bulk QH, called at splusb(). */ 544 void 545 uhci_add_bulk(sc, sqh) 546 uhci_softc_t *sc; 547 uhci_soft_qh_t *sqh; 548 { 549 uhci_qh_t *eqh; 550 551 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 552 eqh = sc->sc_bulk_end->qh; 553 sqh->qh->hlink = eqh->hlink; 554 sqh->qh->qh_hlink = eqh->qh_hlink; 555 eqh->hlink = sqh; 556 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 557 sc->sc_bulk_end = sqh; 558 } 559 560 /* Remove bulk QH, called at splusb(). */ 561 void 562 uhci_remove_bulk(sc, sqh) 563 uhci_softc_t *sc; 564 uhci_soft_qh_t *sqh; 565 { 566 uhci_soft_qh_t *pqh; 567 568 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 569 for (pqh = sc->sc_bulk_start; pqh->qh->hlink != sqh; pqh=pqh->qh->hlink) 570 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 571 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 572 printf("uhci_remove_bulk: QH not found\n"); 573 return; 574 } 575 #else 576 ; 577 #endif 578 pqh->qh->hlink = sqh->qh->hlink; 579 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 580 if (sc->sc_bulk_end == sqh) 581 sc->sc_bulk_end = pqh; 582 } 583 584 int 585 uhci_intr(p) 586 void *p; 587 { 588 uhci_softc_t *sc = p; 589 int status, ret; 590 uhci_intr_info_t *ii; 591 592 sc->sc_intrs++; 593 #if defined(USB_DEBUG) 594 if (uhcidebug > 9) { 595 DPRINTF(("uhci_intr %s, %p\n", sc->sc_bus.bdev.dv_xname, sc)); 596 uhci_dumpregs(sc); 597 } 598 #endif 599 status = UREAD2(sc, UHCI_STS); 600 ret = 0; 601 if (status & UHCI_STS_USBINT) { 602 UWRITE2(sc, UHCI_STS, UHCI_STS_USBINT); /* acknowledge */ 603 ret = 1; 604 } 605 if (status & UHCI_STS_USBEI) { 606 UWRITE2(sc, UHCI_STS, UHCI_STS_USBEI); /* acknowledge */ 607 ret = 1; 608 } 609 if (status & UHCI_STS_RD) { 610 UWRITE2(sc, UHCI_STS, UHCI_STS_RD); /* acknowledge */ 611 printf("%s: resume detect\n", sc->sc_bus.bdev.dv_xname); 612 ret = 1; 613 } 614 if (status & UHCI_STS_HSE) { 615 UWRITE2(sc, UHCI_STS, UHCI_STS_HSE); /* acknowledge */ 616 printf("%s: Host System Error\n", sc->sc_bus.bdev.dv_xname); 617 ret = 1; 618 } 619 if (status & UHCI_STS_HCPE) { 620 UWRITE2(sc, UHCI_STS, UHCI_STS_HCPE); /* acknowledge */ 621 printf("%s: Host System Error\n", sc->sc_bus.bdev.dv_xname); 622 ret = 1; 623 } 624 if (status & UHCI_STS_HCH) { 625 printf("%s: controller halted\n", sc->sc_bus.bdev.dv_xname); 626 } 627 if (!ret) 628 return 0; 629 630 /* 631 * Interrupts on UHCI really suck. When the host controller 632 * interrupts because a transfer is completed there is no 633 * way of knowing which transfer it was. You can scan down 634 * the TDs and QHs of the previous frame to limit the search, 635 * but that assumes that the interrupt was not delayed by more 636 * than 1 ms, which may not always be true (e.g. after debug 637 * output on a slow console). 638 * We scan all interrupt descriptors to see if any have 639 * completed. 640 */ 641 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 642 uhci_check_intr(sc, ii); 643 644 DPRINTFN(10, ("uhci_intr: exit\n")); 645 return 1; 646 } 647 648 /* Check for an interrupt. */ 649 void 650 uhci_check_intr(sc, ii) 651 uhci_softc_t *sc; 652 uhci_intr_info_t *ii; 653 { 654 struct uhci_pipe *upipe; 655 uhci_soft_td_t *std, *lstd; 656 657 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 658 #ifdef DIAGNOSTIC 659 if (!ii) { 660 printf("uhci_check_intr: no ii? %p\n", ii); 661 return; 662 } 663 #endif 664 if (!ii->stdstart) 665 return; 666 lstd = ii->stdend; 667 #ifdef DIAGNOSTIC 668 if (!lstd) { 669 printf("uhci_check_intr: std==0\n"); 670 return; 671 } 672 #endif 673 /* If the last TD is still active the whole transfer probably is. */ 674 if (lstd->td->td_status & UHCI_TD_ACTIVE) { 675 DPRINTFN(15, ("uhci_check_intr: active ii=%p\n", ii)); 676 for (std = ii->stdstart; std != lstd; std = std->td->link.std) 677 if (std->td->td_status & UHCI_TD_STALLED) 678 goto done; 679 DPRINTFN(15, ("uhci_check_intr: ii=%p still active\n", ii)); 680 return; 681 } 682 done: 683 upipe = (struct uhci_pipe *)ii->reqh->pipe; 684 upipe->pipe.endpoint->toggle = upipe->newtoggle; 685 uhci_ii_done(ii, 0); 686 untimeout(uhci_timeout, ii); 687 } 688 689 void 690 uhci_ii_done(ii, timo) 691 uhci_intr_info_t *ii; 692 int timo; 693 { 694 usbd_request_handle reqh = ii->reqh; 695 uhci_soft_td_t *std; 696 u_int32_t tst; 697 int len, status; 698 699 DPRINTFN(10, ("uhci_check_intr: ii=%p ready\n", ii)); 700 701 /* The transfer is done, compute length and status. */ 702 for (len = status = 0, std = ii->stdstart; 703 std != 0; 704 std = std->td->link.std) { 705 tst = std->td->td_status;; 706 status |= tst; 707 #ifdef USB_DEBUG 708 if ((tst & UHCI_TD_ERROR) && uhcidebug) { 709 printf("uhci_intr: intr error TD:\n"); 710 uhci_dump_td(std); 711 } 712 #endif 713 if (UHCI_TD_GET_PID(std->td->td_token) != UHCI_TD_PID_SETUP) 714 len += UHCI_TD_GET_ACTLEN(tst); 715 } 716 status &= UHCI_TD_ERROR; 717 DPRINTFN(10, ("uhci_check_intr: len=%d, status=0x%x\n", len, status)); 718 if (status != 0) { 719 DPRINTFN(-1+(status==UHCI_TD_STALLED), 720 ("uhci_intr: error, status 0x%b\n", (long)status, 721 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27STALLED\30ACTIVE")); 722 if (status == UHCI_TD_STALLED) 723 reqh->status = USBD_STALLED; 724 else 725 reqh->status = USBD_IOERROR; /* more info XXX */ 726 reqh->actlen = 0; 727 } else { 728 reqh->status = USBD_NORMAL_COMPLETION; 729 reqh->actlen = len; 730 } 731 if (timo) { 732 /* We got a timeout. Make sure transaction is not active. */ 733 reqh->status = USBD_TIMEOUT; 734 for (std = ii->stdstart; std != 0; std = std->td->link.std) 735 std->td->td_status &= ~UHCI_TD_ACTIVE; 736 /* XXX should we wait 1 ms */ 737 } 738 DPRINTFN(5, ("uhci_intr: calling handler ii=%p\n", ii)); 739 740 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 741 case UE_CONTROL: 742 uhci_ctrl_done(ii); 743 break; 744 case UE_ISOCHRONOUS: 745 printf("uhci_ii_done: ISO??\n"); 746 case UE_BULK: 747 uhci_bulk_done(ii); 748 break; 749 case UE_INTERRUPT: 750 uhci_intr_done(ii); 751 break; 752 } 753 754 /* And finally execute callback. */ 755 reqh->xfercb(reqh); 756 } 757 758 void 759 uhci_timeout(addr) 760 void *addr; 761 { 762 uhci_intr_info_t *ii = addr; 763 int s; 764 765 DPRINTF(("uhci_timeout: ii=%p\n", ii)); 766 s = splusb(); 767 uhci_ii_done(ii, 1); 768 splx(s); 769 } 770 771 /* 772 * Wait here until controller claims to have an interrupt. 773 * Then call uhci_intr and return. Use timeout to avoid waiting 774 * too long. 775 */ 776 void 777 uhci_waitintr(sc, reqh) 778 uhci_softc_t *sc; 779 usbd_request_handle reqh; 780 { 781 int timo = reqh->timeout; 782 int usecs; 783 784 reqh->status = USBD_IN_PROGRESS; 785 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 786 delay(1000); 787 DPRINTFN(10,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 788 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 789 uhci_intr(sc); 790 if (reqh->status != USBD_IN_PROGRESS) 791 return; 792 } 793 } 794 reqh->status = USBD_TIMEOUT; 795 reqh->xfercb(reqh); 796 } 797 798 #if 0 799 void 800 uhci_reset(p) 801 void *p; 802 { 803 uhci_softc_t *sc = p; 804 int n; 805 806 UHCICMD(sc, UHCI_CMD_HCRESET); 807 /* The reset bit goes low when the controller is done. */ 808 for (n = 0; n < UHCI_RESET_TIMEOUT && 809 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 810 delay(100); 811 if (n >= UHCI_RESET_TIMEOUT) 812 printf("%s: controller did not reset\n", sc->sc_bus.bdev.dv_xname); 813 } 814 #endif 815 816 void 817 uhci_run(sc, run) 818 uhci_softc_t *sc; 819 int run; 820 { 821 int s, n, running; 822 823 run = run != 0; 824 s = splusb(); /* XXX really? */ 825 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 826 if (run == running) { 827 splx(s); 828 return; 829 } 830 UWRITE2(sc, UHCI_CMD, run ? UHCI_CMD_RS : 0); 831 for(n = 0; n < 100; n++) { 832 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 833 /* return when we've entered the state we want */ 834 if (run == running) { 835 splx(s); 836 return; 837 } 838 } 839 splx(s); 840 printf("%s: cannot %s\n", sc->sc_bus.bdev.dv_xname, run ? "start" : "stop"); 841 } 842 843 /* 844 * Memory management routines. 845 * uhci_allocmem allocates DMAable memory. 846 * uhci_alloc_std allocates TDs 847 * uhci_alloc_sqh allocates QHs 848 * uhci_alloc_buffer allocates transfer buffers. 849 * The latter three routines do their own free list management, 850 * partly for speed, partly because allocating DMAable memory 851 * has page size granularaity so much memory would be wasted if 852 * only one TD/QH (32 bytes) was placed in each alloacted chunk. 853 */ 854 855 usbd_status 856 uhci_allocmem(sc, size, align, p) 857 uhci_softc_t *sc; 858 size_t size; 859 size_t align; 860 uhci_dma_t *p; 861 { 862 int error; 863 864 DPRINTFN(5, ("uhci_allocmem: size=%d align=%d\n", size, align)); 865 p->size = size; 866 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 867 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 868 &p->nsegs, BUS_DMA_NOWAIT); 869 if (error) 870 return (USBD_NOMEM); 871 872 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 873 &p->kaddr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 874 if (error) 875 goto free; 876 877 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 878 0, BUS_DMA_NOWAIT, &p->map); 879 if (error) 880 goto unmap; 881 882 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->kaddr,p->size, NULL, 883 BUS_DMA_NOWAIT); 884 if (error) 885 goto destroy; 886 return 0; 887 888 destroy: 889 bus_dmamap_destroy(sc->sc_dmatag, p->map); 890 unmap: 891 bus_dmamem_unmap(sc->sc_dmatag, p->kaddr, p->size); 892 free: 893 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 894 return (USBD_NOMEM); 895 } 896 897 void 898 uhci_freemem(sc, p) 899 uhci_softc_t *sc; 900 uhci_dma_t *p; 901 { 902 bus_dmamap_unload(sc->sc_dmatag, p->map); 903 bus_dmamap_destroy(sc->sc_dmatag, p->map); 904 bus_dmamem_unmap(sc->sc_dmatag, p->kaddr, p->size); 905 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 906 } 907 908 uhci_soft_td_t * 909 uhci_alloc_std(sc) 910 uhci_softc_t *sc; 911 { 912 uhci_soft_td_t *std; 913 usbd_status r; 914 int i; 915 uhci_dma_t dma; 916 917 if (!sc->sc_freetds) { 918 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 919 std = malloc(sizeof(uhci_soft_td_t) * UHCI_TD_CHUNK, 920 M_USBDEV, M_NOWAIT); 921 if (!std) 922 return 0; 923 r = uhci_allocmem(sc, UHCI_TD_SIZE * UHCI_TD_CHUNK, 924 UHCI_TD_ALIGN, &dma); 925 if (r != USBD_NORMAL_COMPLETION) { 926 free(std, M_USBDEV); 927 return 0; 928 } 929 for(i = 0; i < UHCI_TD_CHUNK; i++, std++) { 930 std->physaddr = DMAADDR(&dma) + 931 i * UHCI_TD_SIZE; 932 std->td = (uhci_td_t *) 933 ((char *)KERNADDR(&dma) + i * UHCI_TD_SIZE); 934 std->td->link.std = sc->sc_freetds; 935 sc->sc_freetds = std; 936 } 937 } 938 std = sc->sc_freetds; 939 sc->sc_freetds = std->td->link.std; 940 memset(std->td, 0, UHCI_TD_SIZE); 941 return std; 942 } 943 944 void 945 uhci_free_std(sc, std) 946 uhci_softc_t *sc; 947 uhci_soft_td_t *std; 948 { 949 std->td->link.std = sc->sc_freetds; 950 sc->sc_freetds = std; 951 } 952 953 uhci_soft_qh_t * 954 uhci_alloc_sqh(sc) 955 uhci_softc_t *sc; 956 { 957 uhci_soft_qh_t *sqh; 958 usbd_status r; 959 int i, offs; 960 uhci_dma_t dma; 961 962 if (!sc->sc_freeqhs) { 963 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 964 sqh = malloc(sizeof(uhci_soft_qh_t) * UHCI_QH_CHUNK, 965 M_USBDEV, M_NOWAIT); 966 if (!sqh) 967 return 0; 968 r = uhci_allocmem(sc, UHCI_QH_SIZE * UHCI_QH_CHUNK, 969 UHCI_QH_ALIGN, &dma); 970 if (r != USBD_NORMAL_COMPLETION) { 971 free(sqh, M_USBDEV); 972 return 0; 973 } 974 for(i = 0; i < UHCI_QH_CHUNK; i++, sqh++) { 975 offs = i * UHCI_QH_SIZE; 976 sqh->physaddr = DMAADDR(&dma) + offs; 977 sqh->qh = (uhci_qh_t *) 978 ((char *)KERNADDR(&dma) + offs); 979 sqh->qh->hlink = sc->sc_freeqhs; 980 sc->sc_freeqhs = sqh; 981 } 982 } 983 sqh = sc->sc_freeqhs; 984 sc->sc_freeqhs = sqh->qh->hlink; 985 memset(sqh->qh, 0, UHCI_QH_SIZE); 986 return sqh; 987 } 988 989 void 990 uhci_free_sqh(sc, sqh) 991 uhci_softc_t *sc; 992 uhci_soft_qh_t *sqh; 993 { 994 sqh->qh->hlink = sc->sc_freeqhs; 995 sc->sc_freeqhs = sqh; 996 } 997 998 #if 0 999 void * 1000 uhci_alloc_buffer(sc, size) 1001 uhci_softc_t *sc; 1002 size_t size; 1003 { 1004 struct uhci_buffer *buf; 1005 usbd_status r; 1006 int i, offs; 1007 uhci_dma_t dma; 1008 1009 if (!sc->sc_freebuffers) { 1010 DPRINTFN(2, ("uhci_alloc_buffer: allocating chunk\n")); 1011 r = uhci_allocmem(sc, UHCI_BUFFER_SIZE * BUFFER_CHUNK, 1012 0, &dma); 1013 if (r != USBD_NORMAL_COMPLETION) 1014 return 0; 1015 for(i = 0; i < BUFFER_CHUNK; i++, sqh++) { 1016 offs = i * UHCI_BUFFER_SIZE; 1017 sqh->physaddr = DMAADDR(&dma) + offs; 1018 sqh->qh = (uhci_qh_t *) 1019 ((char *)KERNADDR(&dma) + offs); 1020 sqh->qh->hlink = sc->sc_freeqhs; 1021 sc->sc_freeqhs = sqh; 1022 } 1023 } 1024 sqh = sc->sc_freeqhs; 1025 sc->sc_freeqhs = sqh->qh->hlink; 1026 memset(sqh->qh, 0, UHCI_QH_SIZE); 1027 return sqh; 1028 } 1029 1030 void 1031 uhci_free_buffer(sc, p, size) 1032 uhci_softc_t *sc; 1033 void *p; 1034 size_t size; 1035 { 1036 } 1037 #endif 1038 1039 /* 1040 * Enter a list of transfers onto a control queue. 1041 * Called at splusb() 1042 */ 1043 void 1044 uhci_enter_ctl_q(sc, sqh, ii) 1045 uhci_softc_t *sc; 1046 uhci_soft_qh_t *sqh; 1047 uhci_intr_info_t *ii; 1048 { 1049 DPRINTFN(5, ("uhci_enter_ctl_q: sqh=%p\n", sqh)); 1050 1051 } 1052 1053 void 1054 uhci_free_std_chain(sc, std, stdend) 1055 uhci_softc_t *sc; 1056 uhci_soft_td_t *std; 1057 uhci_soft_td_t *stdend; 1058 { 1059 uhci_soft_td_t *p; 1060 1061 for (; std != stdend; std = p) { 1062 p = std->td->link.std; 1063 uhci_free_std(sc, std); 1064 } 1065 } 1066 1067 usbd_status 1068 uhci_alloc_std_chain(upipe, sc, len, rd, dma, sp, ep) 1069 struct uhci_pipe *upipe; 1070 uhci_softc_t *sc; 1071 int len, rd; 1072 uhci_dma_t *dma; 1073 uhci_soft_td_t **sp, **ep; 1074 { 1075 uhci_soft_td_t *p, *lastp; 1076 uhci_physaddr_t lastlink; 1077 u_int32_t ls; 1078 int i, ntd, l, tog, maxp; 1079 int addr = upipe->pipe.device->address; 1080 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1081 1082 DPRINTFN(15, ("uhci_alloc_std_chain: len=%d\n", len)); 1083 if (len == 0) { 1084 *sp = *ep = 0; 1085 printf("uhci_alloc_std_chain: len=0\n"); 1086 return (USBD_NORMAL_COMPLETION); 1087 } 1088 ls = upipe->pipe.device->lowspeed ? UHCI_TD_LS : 0; 1089 maxp = upipe->pipe.device->ddesc.bMaxPacketSize; 1090 if (maxp == 0) { 1091 printf("uhci_alloc_std_chain: maxp=0\n"); 1092 return (USBD_INVAL); 1093 } 1094 ntd = (len + maxp - 1) / maxp; 1095 tog = upipe->pipe.endpoint->toggle; 1096 if (ntd % 2 == 0) 1097 tog ^= 1; 1098 lastp = 0; 1099 lastlink = UHCI_PTR_T; 1100 ntd--; 1101 for (i = ntd; i >= 0; i--) { 1102 p = uhci_alloc_std(sc); 1103 if (!p) { 1104 uhci_free_std_chain(sc, lastp, 0); 1105 return (USBD_NOMEM); 1106 } 1107 p->td->link.std = lastp; 1108 p->td->td_link = lastlink; 1109 lastp = p; 1110 lastlink = p->physaddr; 1111 p->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | UHCI_TD_ACTIVE; 1112 if (i == ntd) { 1113 /* last TD */ 1114 l = len % maxp; 1115 if (l == 0) l = maxp; 1116 *ep = p; 1117 } else 1118 l = maxp; 1119 p->td->td_token = 1120 rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1121 UHCI_TD_OUT(l, endpt, addr, tog); 1122 p->td->td_buffer = DMAADDR(dma) + i * maxp; 1123 tog ^= 1; 1124 } 1125 *sp = lastp; 1126 /*upipe->pipe.endpoint->toggle = tog;*/ 1127 upipe->newtoggle = tog; 1128 return (USBD_NORMAL_COMPLETION); 1129 } 1130 1131 usbd_status 1132 uhci_device_bulk_transfer(reqh) 1133 usbd_request_handle reqh; 1134 { 1135 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1136 usbd_device_handle dev = upipe->pipe.device; 1137 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1138 uhci_intr_info_t *ii = upipe->iinfo; 1139 uhci_soft_td_t *xfer, *xferend; 1140 uhci_soft_qh_t *sqh; 1141 uhci_dma_t *dmap; 1142 usbd_status r; 1143 int len, isread; 1144 int s; 1145 1146 DPRINTFN(3, ("uhci_device_bulk_transfer: reqh=%p buf=%p len=%d flags=%d\n", 1147 reqh, reqh->buffer, reqh->length, reqh->flags)); 1148 1149 if (reqh->isreq) 1150 panic("uhci_device_bulk_transfer: a request\n"); 1151 1152 len = reqh->length; 1153 dmap = &upipe->u.bulk.datadma; 1154 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1155 sqh = upipe->u.bulk.sqh; 1156 1157 upipe->u.bulk.isread = isread; 1158 upipe->u.bulk.length = len; 1159 1160 r = uhci_allocmem(sc, len, 0, dmap); 1161 if (r != USBD_NORMAL_COMPLETION) 1162 goto ret1; 1163 r = uhci_alloc_std_chain(upipe, sc, len, isread, 1164 dmap, &xfer, &xferend); 1165 if (r != USBD_NORMAL_COMPLETION) 1166 goto ret2; 1167 xferend->td->td_status |= UHCI_TD_IOC; 1168 1169 if (!isread && len != 0) 1170 memcpy(KERNADDR(dmap), reqh->buffer, len); 1171 1172 #ifdef USB_DEBUG 1173 if (uhcidebug > 10) { 1174 printf("uhci_device_bulk_transfer: xfer(1)\n"); 1175 uhci_dump_tds(xfer); 1176 } 1177 #endif 1178 1179 /* Set up interrupt info. */ 1180 ii->reqh = reqh; 1181 ii->stdstart = xfer; 1182 ii->stdend = xferend; 1183 1184 sqh->qh->elink = xfer; 1185 sqh->qh->qh_elink = xfer->physaddr; 1186 sqh->intr_info = ii; 1187 1188 s = splusb(); 1189 uhci_add_bulk(sc, sqh); 1190 LIST_INSERT_HEAD(&sc->sc_intrhead, ii, list); 1191 1192 if (reqh->timeout && !usbd_use_polling) 1193 timeout(uhci_timeout, ii, MS_TO_TICKS(reqh->timeout)); 1194 splx(s); 1195 1196 #ifdef USB_DEBUG 1197 if (uhcidebug > 10) { 1198 printf("uhci_device_bulk_transfer: xfer(2)\n"); 1199 uhci_dump_tds(xfer); 1200 } 1201 #endif 1202 1203 return (USBD_IN_PROGRESS); 1204 1205 ret2: 1206 if (len != 0) 1207 uhci_freemem(sc, dmap); 1208 ret1: 1209 return (r); 1210 } 1211 1212 /* Abort a device bulk request. */ 1213 void 1214 uhci_device_bulk_abort(reqh) 1215 usbd_request_handle reqh; 1216 { 1217 /* XXX */ 1218 usbd_delay_ms(2); /* make sure it is finished */ 1219 } 1220 1221 /* Close a device bulk pipe. */ 1222 void 1223 uhci_device_bulk_close(pipe) 1224 usbd_pipe_handle pipe; 1225 { 1226 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1227 usbd_device_handle dev = upipe->pipe.device; 1228 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1229 1230 uhci_free_sqh(sc, upipe->u.bulk.sqh); 1231 uhci_free_intr_info(upipe->iinfo); 1232 /* XXX free other resources */ 1233 } 1234 1235 usbd_status 1236 uhci_device_ctrl_transfer(reqh) 1237 usbd_request_handle reqh; 1238 { 1239 usbd_status r; 1240 1241 if (!reqh->isreq) 1242 panic("uhci_device_ctrl_transfer: not a request\n"); 1243 1244 r = uhci_device_request(reqh); 1245 if (r != USBD_NORMAL_COMPLETION) 1246 return (r); 1247 1248 if (usbd_use_polling) 1249 uhci_waitintr((uhci_softc_t *)reqh->pipe->device->bus, reqh); 1250 return (USBD_IN_PROGRESS); 1251 } 1252 1253 usbd_status 1254 uhci_device_intr_transfer(reqh) 1255 usbd_request_handle reqh; 1256 { 1257 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1258 usbd_device_handle dev = upipe->pipe.device; 1259 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1260 uhci_intr_info_t *ii = upipe->iinfo; 1261 uhci_soft_td_t *xfer, *xferend; 1262 uhci_soft_qh_t *sqh; 1263 uhci_dma_t *dmap; 1264 usbd_status r; 1265 int len, i; 1266 int s; 1267 1268 DPRINTFN(3, ("uhci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d\n", 1269 reqh, reqh->buffer, reqh->length, reqh->flags)); 1270 1271 if (reqh->isreq) 1272 panic("uhci_device_intr_transfer: a request\n"); 1273 1274 len = reqh->length; 1275 dmap = &upipe->u.intr.datadma; 1276 if (len == 0) 1277 return (USBD_INVAL); /* XXX should it be? */ 1278 1279 r = uhci_allocmem(sc, len, 0, dmap); 1280 if (r != USBD_NORMAL_COMPLETION) 1281 goto ret1; 1282 r = uhci_alloc_std_chain(upipe, sc, len, 1, dmap, &xfer, &xferend); 1283 if (r != USBD_NORMAL_COMPLETION) 1284 goto ret2; 1285 xferend->td->td_status |= UHCI_TD_IOC; 1286 1287 #ifdef USB_DEBUG 1288 if (uhcidebug > 10) { 1289 printf("uhci_device_intr_transfer: xfer(1)\n"); 1290 uhci_dump_tds(xfer); 1291 uhci_dump_qh(upipe->u.intr.qhs[0]); 1292 } 1293 #endif 1294 1295 s = splusb(); 1296 /* Set up interrupt info. */ 1297 ii->reqh = reqh; 1298 ii->stdstart = xfer; 1299 ii->stdend = xferend; 1300 1301 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", upipe->u.intr.qhs[0])); 1302 for (i = 0; i < upipe->u.intr.npoll; i++) { 1303 sqh = upipe->u.intr.qhs[i]; 1304 sqh->qh->elink = xfer; 1305 sqh->qh->qh_elink = xfer->physaddr; 1306 } 1307 splx(s); 1308 1309 #ifdef USB_DEBUG 1310 if (uhcidebug > 10) { 1311 printf("uhci_device_intr_transfer: xfer(2)\n"); 1312 uhci_dump_tds(xfer); 1313 uhci_dump_qh(upipe->u.intr.qhs[0]); 1314 } 1315 #endif 1316 1317 return (USBD_IN_PROGRESS); 1318 1319 ret2: 1320 if (len != 0) 1321 uhci_freemem(sc, dmap); 1322 ret1: 1323 return (r); 1324 } 1325 1326 /* Abort a device control request. */ 1327 void 1328 uhci_device_ctrl_abort(reqh) 1329 usbd_request_handle reqh; 1330 { 1331 /* XXX */ 1332 usbd_delay_ms(2); /* make sure it is finished */ 1333 } 1334 1335 /* Close a device control pipe. */ 1336 void 1337 uhci_device_ctrl_close(pipe) 1338 usbd_pipe_handle pipe; 1339 { 1340 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1341 1342 uhci_free_intr_info(upipe->iinfo); 1343 /* XXX free other resources */ 1344 } 1345 1346 /* Abort a device interrupt request. */ 1347 void 1348 uhci_device_intr_abort(reqh) 1349 usbd_request_handle reqh; 1350 { 1351 struct uhci_pipe *upipe; 1352 1353 usbd_delay_ms(2); /* make sure it is finished */ 1354 if (reqh->pipe->intrreqh == reqh) { 1355 DPRINTF(("uhci_device_intr_abort: remove\n")); 1356 reqh->pipe->intrreqh = 0; 1357 upipe = (struct uhci_pipe *)reqh->pipe; 1358 uhci_intr_done(upipe->u.intr.qhs[0]->intr_info); 1359 } 1360 } 1361 1362 /* Close a device interrupt pipe. */ 1363 void 1364 uhci_device_intr_close(pipe) 1365 usbd_pipe_handle pipe; 1366 { 1367 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1368 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 1369 int i, s, npoll; 1370 1371 upipe->iinfo->stdstart = 0; /* inactive */ 1372 1373 /* Unlink descriptors from controller data structures. */ 1374 npoll = upipe->u.intr.npoll; 1375 uhci_lock_frames(sc); 1376 for (i = 0; i < npoll; i++) 1377 uhci_remove_intr(sc, upipe->u.intr.qhs[i]->pos, 1378 upipe->u.intr.qhs[i]); 1379 uhci_unlock_frames(sc); 1380 1381 /* 1382 * We now have to wait for any activity on the physical 1383 * descriptors to stop. 1384 */ 1385 usbd_delay_ms(2); 1386 1387 for(i = 0; i < npoll; i++) 1388 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 1389 free(upipe->u.intr.qhs, M_USB); 1390 1391 s = splusb(); 1392 LIST_REMOVE(upipe->iinfo, list); /* remove from active list */ 1393 splx(s); 1394 uhci_free_intr_info(upipe->iinfo); 1395 1396 /* XXX free other resources */ 1397 } 1398 1399 usbd_status 1400 uhci_device_request(reqh) 1401 usbd_request_handle reqh; 1402 { 1403 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1404 usb_device_request_t *req = &reqh->request; 1405 usbd_device_handle dev = upipe->pipe.device; 1406 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1407 int addr = dev->address; 1408 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1409 uhci_intr_info_t *ii = upipe->iinfo; 1410 uhci_soft_td_t *setup, *xfer, *stat, *next, *xferend; 1411 uhci_soft_qh_t *sqh; 1412 uhci_dma_t *dmap; 1413 int len; 1414 u_int32_t ls; 1415 usbd_status r; 1416 int isread; 1417 int s; 1418 1419 DPRINTFN(1,("uhci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1420 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1421 UGETW(req->wIndex), UGETW(req->wLength), 1422 addr, endpt)); 1423 1424 ls = dev->lowspeed ? UHCI_TD_LS : 0; 1425 isread = req->bmRequestType & UT_READ; 1426 len = UGETW(req->wLength); 1427 1428 setup = upipe->u.ctl.setup; 1429 stat = upipe->u.ctl.stat; 1430 sqh = upipe->u.ctl.sqh; 1431 dmap = &upipe->u.ctl.datadma; 1432 1433 /* Set up data transaction */ 1434 if (len != 0) { 1435 r = uhci_allocmem(sc, len, 0, dmap); 1436 if (r != USBD_NORMAL_COMPLETION) 1437 goto ret1; 1438 upipe->pipe.endpoint->toggle = 1; 1439 r = uhci_alloc_std_chain(upipe, sc, len, isread, 1440 dmap, &xfer, &xferend); 1441 if (r != USBD_NORMAL_COMPLETION) 1442 goto ret2; 1443 next = xfer; 1444 xferend->td->link.std = stat; 1445 xferend->td->td_link = stat->physaddr; 1446 } else { 1447 xfer = 0; 1448 next = stat; 1449 } 1450 upipe->u.ctl.length = len; 1451 upipe->u.ctl.xferend = xferend; 1452 1453 memcpy(KERNADDR(&upipe->u.ctl.reqdma), req, sizeof *req); 1454 if (!isread && len != 0) 1455 memcpy(KERNADDR(dmap), reqh->buffer, len); 1456 1457 setup->td->link.std = next; 1458 setup->td->td_link = next->physaddr; 1459 setup->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | UHCI_TD_ACTIVE; 1460 setup->td->td_token = UHCI_TD_SETUP(sizeof *req, endpt, addr); 1461 setup->td->td_buffer = DMAADDR(&upipe->u.ctl.reqdma); 1462 1463 stat->td->link.std = 0; 1464 stat->td->td_link = UHCI_PTR_T; 1465 stat->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | 1466 UHCI_TD_ACTIVE | UHCI_TD_IOC; 1467 stat->td->td_token = 1468 isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 1469 UHCI_TD_IN (0, endpt, addr, 1); 1470 stat->td->td_buffer = 0; 1471 1472 #ifdef USB_DEBUG 1473 if (uhcidebug > 20) { 1474 printf("uhci_device_request: setup\n"); 1475 uhci_dump_td(setup); 1476 printf("uhci_device_request: stat\n"); 1477 uhci_dump_td(stat); 1478 } 1479 #endif 1480 1481 /* Set up interrupt info. */ 1482 ii->reqh = reqh; 1483 ii->stdstart = setup; 1484 ii->stdend = stat; 1485 1486 sqh->qh->elink = setup; 1487 sqh->qh->qh_elink = setup->physaddr; 1488 sqh->intr_info = ii; 1489 1490 s = splusb(); 1491 uhci_add_ctrl(sc, sqh); 1492 LIST_INSERT_HEAD(&sc->sc_intrhead, ii, list); 1493 #ifdef USB_DEBUG 1494 if (uhcidebug > 12) { 1495 uhci_soft_td_t *std; 1496 uhci_soft_qh_t *xqh; 1497 uhci_physaddr_t link; 1498 printf("uhci_enter_ctl_q: follow from [0]\n"); 1499 for (std = sc->sc_vframes[0].htd, link = 0; 1500 (link & UHCI_PTR_Q) == 0; 1501 std = std->td->link.std) { 1502 link = std->td->td_link; 1503 uhci_dump_td(std); 1504 } 1505 for (xqh = (uhci_soft_qh_t *)std; 1506 xqh; 1507 xqh = xqh->qh->hlink) 1508 uhci_dump_qh(xqh); 1509 printf("Enqueued QH:\n"); 1510 uhci_dump_qh(sqh); 1511 uhci_dump_tds(sqh->qh->elink); 1512 } 1513 #endif 1514 if (reqh->timeout && !usbd_use_polling) 1515 timeout(uhci_timeout, ii, MS_TO_TICKS(reqh->timeout)); 1516 splx(s); 1517 1518 return (USBD_NORMAL_COMPLETION); 1519 1520 ret2: 1521 if (len != 0) 1522 uhci_freemem(sc, dmap); 1523 ret1: 1524 return (r); 1525 } 1526 1527 void 1528 uhci_intr_done(ii) 1529 uhci_intr_info_t *ii; 1530 { 1531 uhci_softc_t *sc = ii->sc; 1532 usbd_request_handle reqh = ii->reqh; 1533 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1534 uhci_dma_t *dma; 1535 uhci_soft_qh_t *sqh; 1536 int i, npoll; 1537 1538 DPRINTFN(5, ("uhci_intr_done: length=%d\n", reqh->actlen)); 1539 1540 dma = &upipe->u.intr.datadma; 1541 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 1542 npoll = upipe->u.intr.npoll; 1543 for(i = 0; i < npoll; i++) { 1544 sqh = upipe->u.intr.qhs[i]; 1545 sqh->qh->elink = 0; 1546 sqh->qh->qh_elink = UHCI_PTR_T; 1547 } 1548 uhci_free_std_chain(sc, ii->stdstart, 0); 1549 1550 /* XXX Wasteful. */ 1551 if (reqh->pipe->intrreqh == reqh) { 1552 uhci_soft_td_t *xfer, *xferend; 1553 1554 /* This alloc cannot fail since we freed the chain above. */ 1555 uhci_alloc_std_chain(upipe, sc, reqh->length, 1, dma, 1556 &xfer, &xferend); 1557 xferend->td->td_status |= UHCI_TD_IOC; 1558 1559 #ifdef USB_DEBUG 1560 if (uhcidebug > 10) { 1561 printf("uhci_device_intr_done: xfer(1)\n"); 1562 uhci_dump_tds(xfer); 1563 uhci_dump_qh(upipe->u.intr.qhs[0]); 1564 } 1565 #endif 1566 1567 ii->stdstart = xfer; 1568 ii->stdend = xferend; 1569 for (i = 0; i < npoll; i++) { 1570 sqh = upipe->u.intr.qhs[i]; 1571 sqh->qh->elink = xfer; 1572 sqh->qh->qh_elink = xfer->physaddr; 1573 } 1574 } else { 1575 uhci_freemem(sc, dma); 1576 ii->stdstart = 0; /* mark as inactive */ 1577 } 1578 } 1579 1580 /* Deallocate request data structures */ 1581 void 1582 uhci_ctrl_done(ii) 1583 uhci_intr_info_t *ii; 1584 { 1585 uhci_softc_t *sc = ii->sc; 1586 usbd_request_handle reqh = ii->reqh; 1587 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1588 u_int len = upipe->u.ctl.length; 1589 uhci_dma_t *dma; 1590 uhci_td_t *htd = ii->stdstart->td; 1591 1592 if (!reqh->isreq) 1593 panic("uhci_ctrl_done: not a request\n"); 1594 1595 LIST_REMOVE(ii, list); /* remove from active list */ 1596 1597 uhci_remove_ctrl(sc, upipe->u.ctl.sqh); 1598 1599 if (len != 0) { 1600 dma = &upipe->u.ctl.datadma; 1601 if (reqh->request.bmRequestType & UT_READ) 1602 memcpy(reqh->buffer, KERNADDR(dma), len); 1603 uhci_free_std_chain(sc, htd->link.std, ii->stdend); 1604 uhci_freemem(sc, dma); 1605 } 1606 DPRINTFN(5, ("uhci_ctrl_done: length=%d\n", reqh->actlen)); 1607 } 1608 1609 /* Deallocate request data structures */ 1610 void 1611 uhci_bulk_done(ii) 1612 uhci_intr_info_t *ii; 1613 { 1614 uhci_softc_t *sc = ii->sc; 1615 usbd_request_handle reqh = ii->reqh; 1616 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1617 u_int len = upipe->u.bulk.length; 1618 uhci_dma_t *dma; 1619 uhci_td_t *htd = ii->stdstart->td; 1620 1621 LIST_REMOVE(ii, list); /* remove from active list */ 1622 1623 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 1624 1625 if (len != 0) { 1626 dma = &upipe->u.bulk.datadma; 1627 if (upipe->u.bulk.isread && len != 0) 1628 memcpy(reqh->buffer, KERNADDR(dma), len); 1629 uhci_free_std_chain(sc, htd->link.std, 0); 1630 uhci_freemem(sc, dma); 1631 } 1632 DPRINTFN(4, ("uhci_bulk_done: length=%d\n", reqh->actlen)); 1633 } 1634 1635 /* Add interrupt QH, called with vflock. */ 1636 void 1637 uhci_add_intr(sc, n, sqh) 1638 uhci_softc_t *sc; 1639 int n; 1640 uhci_soft_qh_t *sqh; 1641 { 1642 struct uhci_vframe *vf = &sc->sc_vframes[n]; 1643 uhci_qh_t *eqh; 1644 1645 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", n, sqh)); 1646 eqh = vf->eqh->qh; 1647 sqh->qh->hlink = eqh->hlink; 1648 sqh->qh->qh_hlink = eqh->qh_hlink; 1649 eqh->hlink = sqh; 1650 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 1651 vf->eqh = sqh; 1652 vf->bandwidth++; 1653 } 1654 1655 /* Remove interrupt QH, called with vflock. */ 1656 void 1657 uhci_remove_intr(sc, n, sqh) 1658 uhci_softc_t *sc; 1659 int n; 1660 uhci_soft_qh_t *sqh; 1661 { 1662 struct uhci_vframe *vf = &sc->sc_vframes[n]; 1663 uhci_soft_qh_t *pqh; 1664 1665 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", n, sqh)); 1666 1667 for (pqh = vf->hqh; pqh->qh->hlink != sqh; pqh = pqh->qh->hlink) 1668 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 1669 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 1670 printf("uhci_remove_intr: QH not found\n"); 1671 return; 1672 } 1673 #else 1674 ; 1675 #endif 1676 pqh->qh->hlink = sqh->qh->hlink; 1677 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 1678 if (vf->eqh == sqh) 1679 vf->eqh = pqh; 1680 vf->bandwidth--; 1681 } 1682 1683 usbd_status 1684 uhci_device_setintr(sc, upipe, ival) 1685 uhci_softc_t *sc; 1686 struct uhci_pipe *upipe; 1687 int ival; 1688 { 1689 uhci_soft_qh_t *sqh; 1690 int i, npoll, s; 1691 u_int bestbw, bw, bestoffs, offs; 1692 1693 DPRINTFN(2, ("uhci_setintr: pipe=%p\n", upipe)); 1694 if (ival == 0) { 1695 printf("uhci_setintr: 0 interval\n"); 1696 return (USBD_INVAL); 1697 } 1698 1699 if (ival > UHCI_VFRAMELIST_COUNT) 1700 ival = UHCI_VFRAMELIST_COUNT; 1701 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 1702 DPRINTFN(2, ("uhci_setintr: ival=%d npoll=%d\n", ival, npoll)); 1703 1704 upipe->u.intr.npoll = npoll; 1705 upipe->u.intr.qhs = 1706 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USB, M_WAITOK); 1707 1708 /* 1709 * Figure out which offset in the schedule that has most 1710 * bandwidth left over. 1711 */ 1712 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 1713 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 1714 for (bw = i = 0; i < npoll; i++) 1715 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 1716 if (bw < bestbw) { 1717 bestbw = bw; 1718 bestoffs = offs; 1719 } 1720 } 1721 DPRINTFN(1, ("uhci_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 1722 1723 upipe->iinfo->stdstart = 0; 1724 for(i = 0; i < npoll; i++) { 1725 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 1726 sqh->qh->elink = 0; 1727 sqh->qh->qh_elink = UHCI_PTR_T; 1728 sqh->pos = MOD(i * ival + bestoffs); 1729 sqh->intr_info = upipe->iinfo; 1730 } 1731 #undef MOD 1732 1733 s = splusb(); 1734 LIST_INSERT_HEAD(&sc->sc_intrhead, upipe->iinfo, list); 1735 splx(s); 1736 1737 uhci_lock_frames(sc); 1738 /* Enter QHs into the controller data structures. */ 1739 for(i = 0; i < npoll; i++) 1740 uhci_add_intr(sc, upipe->u.intr.qhs[i]->pos, 1741 upipe->u.intr.qhs[i]); 1742 uhci_unlock_frames(sc); 1743 1744 DPRINTFN(5, ("uhci_setintr: returns %p\n", upipe)); 1745 return (USBD_NORMAL_COMPLETION); 1746 } 1747 1748 /* Open a new pipe. */ 1749 usbd_status 1750 uhci_open(pipe) 1751 usbd_pipe_handle pipe; 1752 { 1753 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 1754 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1755 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1756 usbd_status r; 1757 1758 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1759 pipe, pipe->device->address, 1760 ed->bEndpointAddress, sc->sc_addr)); 1761 if (pipe->device->address == sc->sc_addr) { 1762 switch (ed->bEndpointAddress) { 1763 case USB_CONTROL_ENDPOINT: 1764 pipe->methods = &uhci_root_ctrl_methods; 1765 break; 1766 case UE_IN | UHCI_INTR_ENDPT: 1767 pipe->methods = &uhci_root_intr_methods; 1768 break; 1769 default: 1770 return (USBD_INVAL); 1771 } 1772 } else { 1773 upipe->iinfo = uhci_alloc_intr_info(sc); 1774 if (upipe->iinfo == 0) 1775 return (USBD_NOMEM); 1776 switch (ed->bmAttributes & UE_XFERTYPE) { 1777 case UE_CONTROL: 1778 pipe->methods = &uhci_device_ctrl_methods; 1779 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 1780 if (upipe->u.ctl.sqh == 0) 1781 return (USBD_NOMEM); 1782 upipe->u.ctl.setup = uhci_alloc_std(sc); 1783 if (upipe->u.ctl.setup == 0) 1784 return (USBD_NOMEM); 1785 upipe->u.ctl.stat = uhci_alloc_std(sc); 1786 if (upipe->u.ctl.stat == 0) 1787 return (USBD_NOMEM); 1788 r = uhci_allocmem(sc, sizeof(uhci_dma_t), 0, 1789 &upipe->u.ctl.reqdma); 1790 if (r != USBD_NORMAL_COMPLETION) 1791 return (r); 1792 break; 1793 case UE_INTERRUPT: 1794 pipe->methods = &uhci_device_intr_methods; 1795 return (uhci_device_setintr(sc, upipe, ed->bInterval)); 1796 case UE_ISOCHRONOUS: 1797 printf("uhci_open: iso not implemented\n"); 1798 return (USBD_XXX); 1799 case UE_BULK: 1800 pipe->methods = &uhci_device_bulk_methods; 1801 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 1802 if (upipe->u.bulk.sqh == 0) 1803 return (USBD_NOMEM); 1804 break; 1805 } 1806 } 1807 return (USBD_NORMAL_COMPLETION); 1808 } 1809 1810 /* 1811 * Data structures and routines to emulate the root hub. 1812 */ 1813 usb_device_descriptor_t uhci_devd = { 1814 USB_DEVICE_DESCRIPTOR_SIZE, 1815 UDESC_DEVICE, /* type */ 1816 {0x00, 0x01}, /* USB version */ 1817 UCLASS_HUB, /* class */ 1818 USUBCLASS_HUB, /* subclass */ 1819 0, /* protocol */ 1820 64, /* max packet */ 1821 {0},{0},{0x00,0x01}, /* device id */ 1822 1,2,0, /* string indicies */ 1823 1 /* # of configurations */ 1824 }; 1825 1826 usb_config_descriptor_t uhci_confd = { 1827 USB_CONFIG_DESCRIPTOR_SIZE, 1828 UDESC_CONFIG, 1829 {USB_CONFIG_DESCRIPTOR_SIZE + 1830 USB_INTERFACE_DESCRIPTOR_SIZE + 1831 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1832 1, 1833 1, 1834 0, 1835 UC_SELF_POWERED, 1836 0 /* max power */ 1837 }; 1838 1839 usb_interface_descriptor_t uhci_ifcd = { 1840 USB_INTERFACE_DESCRIPTOR_SIZE, 1841 UDESC_INTERFACE, 1842 0, 1843 0, 1844 1, 1845 UCLASS_HUB, 1846 USUBCLASS_HUB, 1847 0, 1848 0 1849 }; 1850 1851 usb_endpoint_descriptor_t uhci_endpd = { 1852 USB_ENDPOINT_DESCRIPTOR_SIZE, 1853 UDESC_ENDPOINT, 1854 UE_IN | UHCI_INTR_ENDPT, 1855 UE_INTERRUPT, 1856 {8}, 1857 255 1858 }; 1859 1860 usb_hub_descriptor_t uhci_hubd_piix = { 1861 USB_HUB_DESCRIPTOR_SIZE, 1862 UDESC_HUB, 1863 2, 1864 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 1865 50, /* power on to power good */ 1866 0, 1867 { 0x00 }, /* both ports are removable */ 1868 { 0x00 }, /* no ports can power down individually */ 1869 }; 1870 1871 int 1872 uhci_str(p, l, s) 1873 usb_string_descriptor_t *p; 1874 int l; 1875 char *s; 1876 { 1877 int i; 1878 1879 if (l == 0) 1880 return (0); 1881 p->bLength = 2 * strlen(s) + 2; 1882 if (l == 1) 1883 return (1); 1884 p->bDescriptorType = UDESC_STRING; 1885 l -= 2; 1886 for (i = 0; s[i] && l > 1; i++, l -= 2) 1887 USETW2(p->bString[i], 0, s[i]); 1888 return (2*i+2); 1889 } 1890 1891 /* 1892 * Simulate a hardware hub by handling all the necessary requests. 1893 */ 1894 usbd_status 1895 uhci_root_ctrl_transfer(reqh) 1896 usbd_request_handle reqh; 1897 { 1898 uhci_softc_t *sc = (uhci_softc_t *)reqh->pipe->device->bus; 1899 usb_device_request_t *req; 1900 void *buf; 1901 int port, x; 1902 int len, value, index, status, change, l, totlen = 0; 1903 usb_port_status_t ps; 1904 usbd_status r; 1905 1906 if (!reqh->isreq) 1907 panic("uhci_root_ctrl_transfer: not a request\n"); 1908 req = &reqh->request; 1909 buf = reqh->buffer; 1910 1911 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 1912 req->bmRequestType, req->bRequest)); 1913 1914 len = UGETW(req->wLength); 1915 value = UGETW(req->wValue); 1916 index = UGETW(req->wIndex); 1917 #define C(x,y) ((x) | ((y) << 8)) 1918 switch(C(req->bRequest, req->bmRequestType)) { 1919 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1920 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1921 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1922 /* 1923 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops 1924 * for the integrated root hub. 1925 */ 1926 break; 1927 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1928 if (len > 0) { 1929 *(u_int8_t *)buf = sc->sc_conf; 1930 totlen = 1; 1931 } 1932 break; 1933 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1934 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 1935 switch(value >> 8) { 1936 case UDESC_DEVICE: 1937 if ((value & 0xff) != 0) { 1938 r = USBD_IOERROR; 1939 goto ret; 1940 } 1941 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1942 memcpy(buf, &uhci_devd, l); 1943 break; 1944 case UDESC_CONFIG: 1945 if ((value & 0xff) != 0) { 1946 r = USBD_IOERROR; 1947 goto ret; 1948 } 1949 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1950 memcpy(buf, &uhci_confd, l); 1951 buf = (char *)buf + l; 1952 len -= l; 1953 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1954 totlen += l; 1955 memcpy(buf, &uhci_ifcd, l); 1956 buf = (char *)buf + l; 1957 len -= l; 1958 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1959 totlen += l; 1960 memcpy(buf, &uhci_endpd, l); 1961 break; 1962 case UDESC_STRING: 1963 if (len == 0) 1964 break; 1965 *(u_int8_t *)buf = 0; 1966 totlen = 1; 1967 switch (value & 0xff) { 1968 case 1: /* Vendor */ 1969 if (sc->sc_model == UHCI_PIIX3 || 1970 sc->sc_model == UHCI_PIIX4) 1971 totlen = uhci_str(buf, len, "Intel"); 1972 break; 1973 case 2: /* Product */ 1974 if (sc->sc_model == UHCI_PIIX3) 1975 totlen = uhci_str(buf, len, 1976 "PIIX3 root hub"); 1977 if (sc->sc_model == UHCI_PIIX4) 1978 totlen = uhci_str(buf, len, 1979 "PIIX4 root hub"); 1980 break; 1981 } 1982 break; 1983 default: 1984 r = USBD_IOERROR; 1985 goto ret; 1986 } 1987 break; 1988 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1989 if (len > 0) { 1990 *(u_int8_t *)buf = 0; 1991 totlen = 1; 1992 } 1993 break; 1994 case C(UR_GET_STATUS, UT_READ_DEVICE): 1995 if (len > 1) { 1996 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1997 totlen = 2; 1998 } 1999 break; 2000 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2001 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2002 if (len > 1) { 2003 USETW(((usb_status_t *)buf)->wStatus, 0); 2004 totlen = 2; 2005 } 2006 break; 2007 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2008 if (value >= USB_MAX_DEVICES) { 2009 r = USBD_IOERROR; 2010 goto ret; 2011 } 2012 sc->sc_addr = value; 2013 break; 2014 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2015 if (value != 0 && value != 1) { 2016 r = USBD_IOERROR; 2017 goto ret; 2018 } 2019 sc->sc_conf = value; 2020 break; 2021 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2022 break; 2023 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2024 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2025 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2026 r = USBD_IOERROR; 2027 goto ret; 2028 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2029 break; 2030 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2031 break; 2032 /* Hub requests */ 2033 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2034 break; 2035 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2036 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n", 2037 index, value)); 2038 if (index == 1) 2039 port = UHCI_PORTSC1; 2040 else if (index == 2) 2041 port = UHCI_PORTSC2; 2042 else { 2043 r = USBD_IOERROR; 2044 goto ret; 2045 } 2046 switch(value) { 2047 case UHF_PORT_ENABLE: 2048 x = UREAD2(sc, port); 2049 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2050 break; 2051 case UHF_PORT_SUSPEND: 2052 x = UREAD2(sc, port); 2053 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 2054 break; 2055 case UHF_PORT_RESET: 2056 x = UREAD2(sc, port); 2057 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2058 break; 2059 case UHF_C_PORT_CONNECTION: 2060 x = UREAD2(sc, port); 2061 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2062 break; 2063 case UHF_C_PORT_ENABLE: 2064 x = UREAD2(sc, port); 2065 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2066 break; 2067 case UHF_C_PORT_OVER_CURRENT: 2068 x = UREAD2(sc, port); 2069 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2070 break; 2071 case UHF_C_PORT_RESET: 2072 sc->sc_isreset = 0; 2073 r = USBD_NORMAL_COMPLETION; 2074 goto ret; 2075 case UHF_PORT_CONNECTION: 2076 case UHF_PORT_OVER_CURRENT: 2077 case UHF_PORT_POWER: 2078 case UHF_PORT_LOW_SPEED: 2079 case UHF_C_PORT_SUSPEND: 2080 default: 2081 r = USBD_IOERROR; 2082 goto ret; 2083 } 2084 break; 2085 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2086 if (index == 1) 2087 port = UHCI_PORTSC1; 2088 else if (index == 2) 2089 port = UHCI_PORTSC2; 2090 else { 2091 r = USBD_IOERROR; 2092 goto ret; 2093 } 2094 if (len > 0) { 2095 *(u_int8_t *)buf = 2096 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2097 UHCI_PORTSC_LS_SHIFT; 2098 totlen = 1; 2099 } 2100 break; 2101 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2102 if (value != 0) { 2103 r = USBD_IOERROR; 2104 goto ret; 2105 } 2106 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 2107 totlen = l; 2108 memcpy(buf, &uhci_hubd_piix, l); 2109 break; 2110 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2111 if (len != 4) { 2112 r = USBD_IOERROR; 2113 goto ret; 2114 } 2115 memset(buf, 0, len); 2116 totlen = len; 2117 break; 2118 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2119 if (index == 1) 2120 port = UHCI_PORTSC1; 2121 else if (index == 2) 2122 port = UHCI_PORTSC2; 2123 else { 2124 r = USBD_IOERROR; 2125 goto ret; 2126 } 2127 if (len != 4) { 2128 r = USBD_IOERROR; 2129 goto ret; 2130 } 2131 x = UREAD2(sc, port); 2132 status = change = 0; 2133 if (x & UHCI_PORTSC_CCS ) 2134 status |= UPS_CURRENT_CONNECT_STATUS; 2135 if (x & UHCI_PORTSC_CSC ) 2136 change |= UPS_C_CONNECT_STATUS; 2137 if (x & UHCI_PORTSC_PE ) 2138 status |= UPS_PORT_ENABLED; 2139 if (x & UHCI_PORTSC_POEDC) 2140 change |= UPS_C_PORT_ENABLED; 2141 if (x & UHCI_PORTSC_OCI ) 2142 status |= UPS_OVERCURRENT_INDICATOR; 2143 if (x & UHCI_PORTSC_OCIC ) 2144 change |= UPS_C_OVERCURRENT_INDICATOR; 2145 if (x & UHCI_PORTSC_SUSP ) 2146 status |= UPS_SUSPEND; 2147 if (x & UHCI_PORTSC_LSDA ) 2148 status |= UPS_LOW_SPEED; 2149 status |= UPS_PORT_POWER; 2150 if (sc->sc_isreset) 2151 change |= UPS_C_PORT_RESET; 2152 USETW(ps.wPortStatus, status); 2153 USETW(ps.wPortChange, change); 2154 l = min(len, sizeof ps); 2155 memcpy(buf, &ps, l); 2156 totlen = l; 2157 break; 2158 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2159 r = USBD_IOERROR; 2160 goto ret; 2161 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2162 break; 2163 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2164 if (index == 1) 2165 port = UHCI_PORTSC1; 2166 else if (index == 2) 2167 port = UHCI_PORTSC2; 2168 else { 2169 r = USBD_IOERROR; 2170 goto ret; 2171 } 2172 switch(value) { 2173 case UHF_PORT_ENABLE: 2174 x = UREAD2(sc, port); 2175 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2176 break; 2177 case UHF_PORT_SUSPEND: 2178 x = UREAD2(sc, port); 2179 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2180 break; 2181 case UHF_PORT_RESET: 2182 x = UREAD2(sc, port); 2183 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2184 usbd_delay_ms(10); 2185 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2186 delay(100); 2187 x = UREAD2(sc, port); 2188 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2189 delay(100); 2190 DPRINTFN(3,("uhci port %d reset, status = 0x%04x\n", 2191 index, UREAD2(sc, port))); 2192 sc->sc_isreset = 1; 2193 break; 2194 case UHF_C_PORT_CONNECTION: 2195 case UHF_C_PORT_ENABLE: 2196 case UHF_C_PORT_OVER_CURRENT: 2197 case UHF_PORT_CONNECTION: 2198 case UHF_PORT_OVER_CURRENT: 2199 case UHF_PORT_POWER: 2200 case UHF_PORT_LOW_SPEED: 2201 case UHF_C_PORT_SUSPEND: 2202 case UHF_C_PORT_RESET: 2203 default: 2204 r = USBD_IOERROR; 2205 goto ret; 2206 } 2207 break; 2208 default: 2209 r = USBD_IOERROR; 2210 goto ret; 2211 } 2212 reqh->actlen = totlen; 2213 r = USBD_NORMAL_COMPLETION; 2214 ret: 2215 reqh->status = r; 2216 reqh->xfercb(reqh); 2217 return (USBD_IN_PROGRESS); 2218 } 2219 2220 /* Abort a root control request. */ 2221 void 2222 uhci_root_ctrl_abort(reqh) 2223 usbd_request_handle reqh; 2224 { 2225 } 2226 2227 /* Close the root pipe. */ 2228 void 2229 uhci_root_ctrl_close(pipe) 2230 usbd_pipe_handle pipe; 2231 { 2232 untimeout(uhci_timo, pipe->intrreqh); 2233 DPRINTF(("uhci_root_ctrl_close\n")); 2234 } 2235 2236 /* Abort a root interrupt request. */ 2237 void 2238 uhci_root_intr_abort(reqh) 2239 usbd_request_handle reqh; 2240 { 2241 untimeout(uhci_timo, reqh); 2242 } 2243 2244 /* Start a transfer on the root interrupt pipe */ 2245 usbd_status 2246 uhci_root_intr_transfer(reqh) 2247 usbd_request_handle reqh; 2248 { 2249 usbd_pipe_handle pipe = reqh->pipe; 2250 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 2251 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2252 uhci_dma_t *dmap; 2253 usbd_status r; 2254 int len; 2255 2256 DPRINTFN(3, ("uhci_root_intr_transfer: reqh=%p buf=%p len=%d flags=%d\n", 2257 reqh, reqh->buffer, reqh->length, reqh->flags)); 2258 2259 len = reqh->length; 2260 dmap = &upipe->u.intr.datadma; 2261 if (len == 0) 2262 return (USBD_INVAL); /* XXX should it be? */ 2263 2264 r = uhci_allocmem(sc, len, 0, dmap); 2265 if (r != USBD_NORMAL_COMPLETION) 2266 return (r); 2267 2268 sc->sc_ival = MS_TO_TICKS(reqh->pipe->endpoint->edesc->bInterval); 2269 timeout(uhci_timo, reqh, sc->sc_ival); 2270 return (USBD_IN_PROGRESS); 2271 } 2272 2273 /* Close the root interrupt pipe. */ 2274 void 2275 uhci_root_intr_close(pipe) 2276 usbd_pipe_handle pipe; 2277 { 2278 untimeout(uhci_timo, pipe->intrreqh); 2279 DPRINTF(("uhci_root_intr_close\n")); 2280 } 2281
Indexes created Tue Sep 30 20:09:53 GMT 2025