uhci.c revision 1.300
1 /* $NetBSD: uhci.c,v 1.300 2020/04/05 20:59:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Universal Host Controller driver. 36 * Handles e.g. PIIX3 and PIIX4. 37 * 38 * UHCI spec: http://www.intel.com/technology/usb/spec.htm 39 * USB spec: http://www.usb.org/developers/docs/ 40 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 41 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: uhci.c,v 1.300 2020/04/05 20:59:38 skrll Exp $"); 46 47 #ifdef _KERNEL_OPT 48 #include "opt_usb.h" 49 #endif 50 51 #include <sys/param.h> 52 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/device.h> 56 #include <sys/kernel.h> 57 #include <sys/kmem.h> 58 #include <sys/mutex.h> 59 #include <sys/proc.h> 60 #include <sys/queue.h> 61 #include <sys/select.h> 62 #include <sys/sysctl.h> 63 #include <sys/systm.h> 64 65 #include <machine/endian.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usb_mem.h> 71 72 #include <dev/usb/uhcireg.h> 73 #include <dev/usb/uhcivar.h> 74 #include <dev/usb/usbroothub.h> 75 #include <dev/usb/usbhist.h> 76 77 /* Use bandwidth reclamation for control transfers. Some devices choke on it. */ 78 /*#define UHCI_CTL_LOOP */ 79 80 #ifdef UHCI_DEBUG 81 uhci_softc_t *thesc; 82 int uhcinoloop = 0; 83 #endif 84 85 #ifdef USB_DEBUG 86 #ifndef UHCI_DEBUG 87 #define uhcidebug 0 88 #else 89 static int uhcidebug = 0; 90 91 SYSCTL_SETUP(sysctl_hw_uhci_setup, "sysctl hw.uhci setup") 92 { 93 int err; 94 const struct sysctlnode *rnode; 95 const struct sysctlnode *cnode; 96 97 err = sysctl_createv(clog, 0, NULL, &rnode, 98 CTLFLAG_PERMANENT, CTLTYPE_NODE, "uhci", 99 SYSCTL_DESCR("uhci global controls"), 100 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 101 102 if (err) 103 goto fail; 104 105 /* control debugging printfs */ 106 err = sysctl_createv(clog, 0, &rnode, &cnode, 107 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 108 "debug", SYSCTL_DESCR("Enable debugging output"), 109 NULL, 0, &uhcidebug, sizeof(uhcidebug), CTL_CREATE, CTL_EOL); 110 if (err) 111 goto fail; 112 113 return; 114 fail: 115 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 116 } 117 118 #endif /* UHCI_DEBUG */ 119 #endif /* USB_DEBUG */ 120 121 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,1,FMT,A,B,C,D) 122 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(uhcidebug,N,FMT,A,B,C,D) 123 #define UHCIHIST_FUNC() USBHIST_FUNC() 124 #define UHCIHIST_CALLED(name) USBHIST_CALLED(uhcidebug) 125 126 /* 127 * The UHCI controller is little endian, so on big endian machines 128 * the data stored in memory needs to be swapped. 129 */ 130 131 struct uhci_pipe { 132 struct usbd_pipe pipe; 133 int nexttoggle; 134 135 u_char aborting; 136 struct usbd_xfer *abortstart, abortend; 137 138 /* Info needed for different pipe kinds. */ 139 union { 140 /* Control pipe */ 141 struct { 142 uhci_soft_qh_t *sqh; 143 usb_dma_t reqdma; 144 uhci_soft_td_t *setup; 145 uhci_soft_td_t *stat; 146 } ctrl; 147 /* Interrupt pipe */ 148 struct { 149 int npoll; 150 uhci_soft_qh_t **qhs; 151 } intr; 152 /* Bulk pipe */ 153 struct { 154 uhci_soft_qh_t *sqh; 155 } bulk; 156 /* Isochronous pipe */ 157 struct isoc { 158 uhci_soft_td_t **stds; 159 int next, inuse; 160 } isoc; 161 }; 162 }; 163 164 typedef TAILQ_HEAD(ux_completeq, uhci_xfer) ux_completeq_t; 165 166 Static void uhci_globalreset(uhci_softc_t *); 167 Static usbd_status uhci_portreset(uhci_softc_t*, int); 168 Static void uhci_reset(uhci_softc_t *); 169 Static usbd_status uhci_run(uhci_softc_t *, int, int); 170 Static uhci_soft_td_t *uhci_alloc_std(uhci_softc_t *); 171 Static void uhci_free_std(uhci_softc_t *, uhci_soft_td_t *); 172 Static void uhci_free_std_locked(uhci_softc_t *, uhci_soft_td_t *); 173 Static uhci_soft_qh_t *uhci_alloc_sqh(uhci_softc_t *); 174 Static void uhci_free_sqh(uhci_softc_t *, uhci_soft_qh_t *); 175 #if 0 176 Static void uhci_enter_ctl_q(uhci_softc_t *, uhci_soft_qh_t *, 177 uhci_intr_info_t *); 178 Static void uhci_exit_ctl_q(uhci_softc_t *, uhci_soft_qh_t *); 179 #endif 180 181 #if 0 182 Static void uhci_free_std_chain(uhci_softc_t *, uhci_soft_td_t *, 183 uhci_soft_td_t *); 184 #endif 185 Static int uhci_alloc_std_chain(uhci_softc_t *, struct usbd_xfer *, 186 int, int, uhci_soft_td_t **); 187 Static void uhci_free_stds(uhci_softc_t *, struct uhci_xfer *); 188 189 Static void uhci_reset_std_chain(uhci_softc_t *, struct usbd_xfer *, 190 int, int, int *, uhci_soft_td_t **); 191 192 Static void uhci_poll_hub(void *); 193 Static void uhci_check_intr(uhci_softc_t *, struct uhci_xfer *, 194 ux_completeq_t *); 195 Static void uhci_idone(struct uhci_xfer *, ux_completeq_t *); 196 197 Static void uhci_abortx(struct usbd_xfer *); 198 199 Static void uhci_add_ls_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 200 Static void uhci_add_hs_ctrl(uhci_softc_t *, uhci_soft_qh_t *); 201 Static void uhci_add_bulk(uhci_softc_t *, uhci_soft_qh_t *); 202 Static void uhci_remove_ls_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 203 Static void uhci_remove_hs_ctrl(uhci_softc_t *,uhci_soft_qh_t *); 204 Static void uhci_remove_bulk(uhci_softc_t *,uhci_soft_qh_t *); 205 Static void uhci_add_loop(uhci_softc_t *); 206 Static void uhci_rem_loop(uhci_softc_t *); 207 208 Static usbd_status uhci_setup_isoc(struct usbd_pipe *); 209 210 Static struct usbd_xfer * 211 uhci_allocx(struct usbd_bus *, unsigned int); 212 Static void uhci_freex(struct usbd_bus *, struct usbd_xfer *); 213 Static bool uhci_dying(struct usbd_bus *); 214 Static void uhci_get_lock(struct usbd_bus *, kmutex_t **); 215 Static int uhci_roothub_ctrl(struct usbd_bus *, 216 usb_device_request_t *, void *, int); 217 218 Static int uhci_device_ctrl_init(struct usbd_xfer *); 219 Static void uhci_device_ctrl_fini(struct usbd_xfer *); 220 Static usbd_status uhci_device_ctrl_transfer(struct usbd_xfer *); 221 Static usbd_status uhci_device_ctrl_start(struct usbd_xfer *); 222 Static void uhci_device_ctrl_abort(struct usbd_xfer *); 223 Static void uhci_device_ctrl_close(struct usbd_pipe *); 224 Static void uhci_device_ctrl_done(struct usbd_xfer *); 225 226 Static int uhci_device_intr_init(struct usbd_xfer *); 227 Static void uhci_device_intr_fini(struct usbd_xfer *); 228 Static usbd_status uhci_device_intr_transfer(struct usbd_xfer *); 229 Static usbd_status uhci_device_intr_start(struct usbd_xfer *); 230 Static void uhci_device_intr_abort(struct usbd_xfer *); 231 Static void uhci_device_intr_close(struct usbd_pipe *); 232 Static void uhci_device_intr_done(struct usbd_xfer *); 233 234 Static int uhci_device_bulk_init(struct usbd_xfer *); 235 Static void uhci_device_bulk_fini(struct usbd_xfer *); 236 Static usbd_status uhci_device_bulk_transfer(struct usbd_xfer *); 237 Static usbd_status uhci_device_bulk_start(struct usbd_xfer *); 238 Static void uhci_device_bulk_abort(struct usbd_xfer *); 239 Static void uhci_device_bulk_close(struct usbd_pipe *); 240 Static void uhci_device_bulk_done(struct usbd_xfer *); 241 242 Static int uhci_device_isoc_init(struct usbd_xfer *); 243 Static void uhci_device_isoc_fini(struct usbd_xfer *); 244 Static usbd_status uhci_device_isoc_transfer(struct usbd_xfer *); 245 Static void uhci_device_isoc_abort(struct usbd_xfer *); 246 Static void uhci_device_isoc_close(struct usbd_pipe *); 247 Static void uhci_device_isoc_done(struct usbd_xfer *); 248 249 Static usbd_status uhci_root_intr_transfer(struct usbd_xfer *); 250 Static usbd_status uhci_root_intr_start(struct usbd_xfer *); 251 Static void uhci_root_intr_abort(struct usbd_xfer *); 252 Static void uhci_root_intr_close(struct usbd_pipe *); 253 Static void uhci_root_intr_done(struct usbd_xfer *); 254 255 Static usbd_status uhci_open(struct usbd_pipe *); 256 Static void uhci_poll(struct usbd_bus *); 257 Static void uhci_softintr(void *); 258 259 Static void uhci_add_intr(uhci_softc_t *, uhci_soft_qh_t *); 260 Static void uhci_remove_intr(uhci_softc_t *, uhci_soft_qh_t *); 261 Static usbd_status uhci_device_setintr(uhci_softc_t *, 262 struct uhci_pipe *, int); 263 264 Static void uhci_device_clear_toggle(struct usbd_pipe *); 265 Static void uhci_noop(struct usbd_pipe *); 266 267 static inline uhci_soft_qh_t * 268 uhci_find_prev_qh(uhci_soft_qh_t *, uhci_soft_qh_t *); 269 270 #ifdef UHCI_DEBUG 271 Static void uhci_dump_all(uhci_softc_t *); 272 Static void uhci_dumpregs(uhci_softc_t *); 273 Static void uhci_dump_qhs(uhci_soft_qh_t *); 274 Static void uhci_dump_qh(uhci_soft_qh_t *); 275 Static void uhci_dump_tds(uhci_soft_td_t *); 276 Static void uhci_dump_td(uhci_soft_td_t *); 277 Static void uhci_dump_ii(struct uhci_xfer *); 278 void uhci_dump(void); 279 #endif 280 281 #define UBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 282 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 283 #define UWRITE1(sc, r, x) \ 284 do { UBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); \ 285 } while (/*CONSTCOND*/0) 286 #define UWRITE2(sc, r, x) \ 287 do { UBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); \ 288 } while (/*CONSTCOND*/0) 289 #define UWRITE4(sc, r, x) \ 290 do { UBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); \ 291 } while (/*CONSTCOND*/0) 292 293 static __inline uint8_t 294 UREAD1(uhci_softc_t *sc, bus_size_t r) 295 { 296 297 UBARR(sc); 298 return bus_space_read_1(sc->iot, sc->ioh, r); 299 } 300 301 static __inline uint16_t 302 UREAD2(uhci_softc_t *sc, bus_size_t r) 303 { 304 305 UBARR(sc); 306 return bus_space_read_2(sc->iot, sc->ioh, r); 307 } 308 309 #ifdef UHCI_DEBUG 310 static __inline uint32_t 311 UREAD4(uhci_softc_t *sc, bus_size_t r) 312 { 313 314 UBARR(sc); 315 return bus_space_read_4(sc->iot, sc->ioh, r); 316 } 317 #endif 318 319 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 320 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 321 322 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 323 324 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 325 326 const struct usbd_bus_methods uhci_bus_methods = { 327 .ubm_open = uhci_open, 328 .ubm_softint = uhci_softintr, 329 .ubm_dopoll = uhci_poll, 330 .ubm_allocx = uhci_allocx, 331 .ubm_freex = uhci_freex, 332 .ubm_abortx = uhci_abortx, 333 .ubm_dying = uhci_dying, 334 .ubm_getlock = uhci_get_lock, 335 .ubm_rhctrl = uhci_roothub_ctrl, 336 }; 337 338 const struct usbd_pipe_methods uhci_root_intr_methods = { 339 .upm_transfer = uhci_root_intr_transfer, 340 .upm_start = uhci_root_intr_start, 341 .upm_abort = uhci_root_intr_abort, 342 .upm_close = uhci_root_intr_close, 343 .upm_cleartoggle = uhci_noop, 344 .upm_done = uhci_root_intr_done, 345 }; 346 347 const struct usbd_pipe_methods uhci_device_ctrl_methods = { 348 .upm_init = uhci_device_ctrl_init, 349 .upm_fini = uhci_device_ctrl_fini, 350 .upm_transfer = uhci_device_ctrl_transfer, 351 .upm_start = uhci_device_ctrl_start, 352 .upm_abort = uhci_device_ctrl_abort, 353 .upm_close = uhci_device_ctrl_close, 354 .upm_cleartoggle = uhci_noop, 355 .upm_done = uhci_device_ctrl_done, 356 }; 357 358 const struct usbd_pipe_methods uhci_device_intr_methods = { 359 .upm_init = uhci_device_intr_init, 360 .upm_fini = uhci_device_intr_fini, 361 .upm_transfer = uhci_device_intr_transfer, 362 .upm_start = uhci_device_intr_start, 363 .upm_abort = uhci_device_intr_abort, 364 .upm_close = uhci_device_intr_close, 365 .upm_cleartoggle = uhci_device_clear_toggle, 366 .upm_done = uhci_device_intr_done, 367 }; 368 369 const struct usbd_pipe_methods uhci_device_bulk_methods = { 370 .upm_init = uhci_device_bulk_init, 371 .upm_fini = uhci_device_bulk_fini, 372 .upm_transfer = uhci_device_bulk_transfer, 373 .upm_start = uhci_device_bulk_start, 374 .upm_abort = uhci_device_bulk_abort, 375 .upm_close = uhci_device_bulk_close, 376 .upm_cleartoggle = uhci_device_clear_toggle, 377 .upm_done = uhci_device_bulk_done, 378 }; 379 380 const struct usbd_pipe_methods uhci_device_isoc_methods = { 381 .upm_init = uhci_device_isoc_init, 382 .upm_fini = uhci_device_isoc_fini, 383 .upm_transfer = uhci_device_isoc_transfer, 384 .upm_abort = uhci_device_isoc_abort, 385 .upm_close = uhci_device_isoc_close, 386 .upm_cleartoggle = uhci_noop, 387 .upm_done = uhci_device_isoc_done, 388 }; 389 390 static inline void 391 uhci_add_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 392 { 393 394 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ux, ux_list); 395 } 396 397 static inline void 398 uhci_del_intr_list(uhci_softc_t *sc, struct uhci_xfer *ux) 399 { 400 401 TAILQ_REMOVE(&sc->sc_intrhead, ux, ux_list); 402 } 403 404 static inline uhci_soft_qh_t * 405 uhci_find_prev_qh(uhci_soft_qh_t *pqh, uhci_soft_qh_t *sqh) 406 { 407 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 408 DPRINTFN(15, "pqh=%#jx sqh=%#jx", (uintptr_t)pqh, (uintptr_t)sqh, 0, 0); 409 410 for (; pqh->hlink != sqh; pqh = pqh->hlink) { 411 #if defined(DIAGNOSTIC) || defined(UHCI_DEBUG) 412 usb_syncmem(&pqh->dma, 413 pqh->offs + offsetof(uhci_qh_t, qh_hlink), 414 sizeof(pqh->qh.qh_hlink), 415 BUS_DMASYNC_POSTWRITE); 416 if (le32toh(pqh->qh.qh_hlink) & UHCI_PTR_T) { 417 printf("%s: QH not found\n", __func__); 418 return NULL; 419 } 420 #endif 421 } 422 return pqh; 423 } 424 425 void 426 uhci_globalreset(uhci_softc_t *sc) 427 { 428 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 429 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); /* wait a little */ 430 UHCICMD(sc, 0); /* do nothing */ 431 } 432 433 int 434 uhci_init(uhci_softc_t *sc) 435 { 436 usbd_status err; 437 int i, j; 438 uhci_soft_qh_t *clsqh, *chsqh, *bsqh, *sqh, *lsqh; 439 uhci_soft_td_t *std; 440 441 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 442 443 #ifdef UHCI_DEBUG 444 thesc = sc; 445 446 if (uhcidebug >= 2) 447 uhci_dumpregs(sc); 448 #endif 449 450 sc->sc_suspend = PWR_RESUME; 451 452 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 453 uhci_globalreset(sc); /* reset the controller */ 454 uhci_reset(sc); 455 456 /* Allocate and initialize real frame array. */ 457 err = usb_allocmem(&sc->sc_bus, 458 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 459 UHCI_FRAMELIST_ALIGN, USBMALLOC_COHERENT, &sc->sc_dma); 460 if (err) 461 return err; 462 sc->sc_pframes = KERNADDR(&sc->sc_dma, 0); 463 /* set frame number to 0 */ 464 UWRITE2(sc, UHCI_FRNUM, 0); 465 /* set frame list */ 466 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 467 468 /* Initialise mutex early for uhci_alloc_* */ 469 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 470 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 471 472 /* 473 * Allocate a TD, inactive, that hangs from the last QH. 474 * This is to avoid a bug in the PIIX that makes it run berserk 475 * otherwise. 476 */ 477 std = uhci_alloc_std(sc); 478 if (std == NULL) 479 return ENOMEM; 480 std->link.std = NULL; 481 std->td.td_link = htole32(UHCI_PTR_T); 482 std->td.td_status = htole32(0); /* inactive */ 483 std->td.td_token = htole32(0); 484 std->td.td_buffer = htole32(0); 485 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 487 488 /* Allocate the dummy QH marking the end and used for looping the QHs.*/ 489 lsqh = uhci_alloc_sqh(sc); 490 if (lsqh == NULL) 491 goto fail1; 492 lsqh->hlink = NULL; 493 lsqh->qh.qh_hlink = htole32(UHCI_PTR_T); /* end of QH chain */ 494 lsqh->elink = std; 495 lsqh->qh.qh_elink = htole32(std->physaddr | UHCI_PTR_TD); 496 sc->sc_last_qh = lsqh; 497 usb_syncmem(&lsqh->dma, lsqh->offs, sizeof(lsqh->qh), 498 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 499 500 /* Allocate the dummy QH where bulk traffic will be queued. */ 501 bsqh = uhci_alloc_sqh(sc); 502 if (bsqh == NULL) 503 goto fail2; 504 bsqh->hlink = lsqh; 505 bsqh->qh.qh_hlink = htole32(lsqh->physaddr | UHCI_PTR_QH); 506 bsqh->elink = NULL; 507 bsqh->qh.qh_elink = htole32(UHCI_PTR_T); 508 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 509 usb_syncmem(&bsqh->dma, bsqh->offs, sizeof(bsqh->qh), 510 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 511 512 /* Allocate dummy QH where high speed control traffic will be queued. */ 513 chsqh = uhci_alloc_sqh(sc); 514 if (chsqh == NULL) 515 goto fail3; 516 chsqh->hlink = bsqh; 517 chsqh->qh.qh_hlink = htole32(bsqh->physaddr | UHCI_PTR_QH); 518 chsqh->elink = NULL; 519 chsqh->qh.qh_elink = htole32(UHCI_PTR_T); 520 sc->sc_hctl_start = sc->sc_hctl_end = chsqh; 521 usb_syncmem(&chsqh->dma, chsqh->offs, sizeof(chsqh->qh), 522 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 523 524 /* Allocate dummy QH where control traffic will be queued. */ 525 clsqh = uhci_alloc_sqh(sc); 526 if (clsqh == NULL) 527 goto fail4; 528 clsqh->hlink = chsqh; 529 clsqh->qh.qh_hlink = htole32(chsqh->physaddr | UHCI_PTR_QH); 530 clsqh->elink = NULL; 531 clsqh->qh.qh_elink = htole32(UHCI_PTR_T); 532 sc->sc_lctl_start = sc->sc_lctl_end = clsqh; 533 usb_syncmem(&clsqh->dma, clsqh->offs, sizeof(clsqh->qh), 534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 535 536 /* 537 * Make all (virtual) frame list pointers point to the interrupt 538 * queue heads and the interrupt queue heads at the control 539 * queue head and point the physical frame list to the virtual. 540 */ 541 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 542 std = uhci_alloc_std(sc); 543 sqh = uhci_alloc_sqh(sc); 544 if (std == NULL || sqh == NULL) 545 return USBD_NOMEM; 546 std->link.sqh = sqh; 547 std->td.td_link = htole32(sqh->physaddr | UHCI_PTR_QH); 548 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 549 std->td.td_token = htole32(0); 550 std->td.td_buffer = htole32(0); 551 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 552 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 553 sqh->hlink = clsqh; 554 sqh->qh.qh_hlink = htole32(clsqh->physaddr | UHCI_PTR_QH); 555 sqh->elink = NULL; 556 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 557 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 559 sc->sc_vframes[i].htd = std; 560 sc->sc_vframes[i].etd = std; 561 sc->sc_vframes[i].hqh = sqh; 562 sc->sc_vframes[i].eqh = sqh; 563 for (j = i; 564 j < UHCI_FRAMELIST_COUNT; 565 j += UHCI_VFRAMELIST_COUNT) 566 sc->sc_pframes[j] = htole32(std->physaddr); 567 } 568 usb_syncmem(&sc->sc_dma, 0, 569 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 570 BUS_DMASYNC_PREWRITE); 571 572 573 TAILQ_INIT(&sc->sc_intrhead); 574 575 sc->sc_xferpool = pool_cache_init(sizeof(struct uhci_xfer), 0, 0, 0, 576 "uhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 577 578 callout_init(&sc->sc_poll_handle, CALLOUT_MPSAFE); 579 callout_setfunc(&sc->sc_poll_handle, uhci_poll_hub, sc); 580 581 /* Set up the bus struct. */ 582 sc->sc_bus.ub_methods = &uhci_bus_methods; 583 sc->sc_bus.ub_pipesize = sizeof(struct uhci_pipe); 584 sc->sc_bus.ub_usedma = true; 585 586 UHCICMD(sc, UHCI_CMD_MAXP); /* Assume 64 byte packets at frame end */ 587 588 DPRINTF("Enabling...", 0, 0, 0, 0); 589 590 err = uhci_run(sc, 1, 0); /* and here we go... */ 591 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 592 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 593 return err; 594 595 fail4: 596 uhci_free_sqh(sc, chsqh); 597 fail3: 598 uhci_free_sqh(sc, lsqh); 599 fail2: 600 uhci_free_sqh(sc, lsqh); 601 fail1: 602 uhci_free_std(sc, std); 603 604 return ENOMEM; 605 } 606 607 int 608 uhci_activate(device_t self, enum devact act) 609 { 610 struct uhci_softc *sc = device_private(self); 611 612 switch (act) { 613 case DVACT_DEACTIVATE: 614 sc->sc_dying = 1; 615 return 0; 616 default: 617 return EOPNOTSUPP; 618 } 619 } 620 621 void 622 uhci_childdet(device_t self, device_t child) 623 { 624 struct uhci_softc *sc = device_private(self); 625 626 KASSERT(sc->sc_child == child); 627 sc->sc_child = NULL; 628 } 629 630 int 631 uhci_detach(struct uhci_softc *sc, int flags) 632 { 633 int rv = 0; 634 635 if (sc->sc_child != NULL) 636 rv = config_detach(sc->sc_child, flags); 637 638 if (rv != 0) 639 return rv; 640 641 callout_halt(&sc->sc_poll_handle, NULL); 642 callout_destroy(&sc->sc_poll_handle); 643 644 mutex_destroy(&sc->sc_lock); 645 mutex_destroy(&sc->sc_intr_lock); 646 647 pool_cache_destroy(sc->sc_xferpool); 648 649 /* XXX free other data structures XXX */ 650 651 return rv; 652 } 653 654 struct usbd_xfer * 655 uhci_allocx(struct usbd_bus *bus, unsigned int nframes) 656 { 657 struct uhci_softc *sc = UHCI_BUS2SC(bus); 658 struct usbd_xfer *xfer; 659 660 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 661 if (xfer != NULL) { 662 memset(xfer, 0, sizeof(struct uhci_xfer)); 663 664 #ifdef DIAGNOSTIC 665 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 666 uxfer->ux_isdone = true; 667 xfer->ux_state = XFER_BUSY; 668 #endif 669 } 670 return xfer; 671 } 672 673 void 674 uhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 675 { 676 struct uhci_softc *sc = UHCI_BUS2SC(bus); 677 struct uhci_xfer *uxfer __diagused = UHCI_XFER2UXFER(xfer); 678 679 KASSERTMSG(xfer->ux_state == XFER_BUSY || 680 xfer->ux_status == USBD_NOT_STARTED, 681 "xfer %p state %d\n", xfer, xfer->ux_state); 682 KASSERTMSG(uxfer->ux_isdone || xfer->ux_status == USBD_NOT_STARTED, 683 "xfer %p not done\n", xfer); 684 #ifdef DIAGNOSTIC 685 xfer->ux_state = XFER_FREE; 686 #endif 687 pool_cache_put(sc->sc_xferpool, xfer); 688 } 689 690 Static bool 691 uhci_dying(struct usbd_bus *bus) 692 { 693 struct uhci_softc *sc = UHCI_BUS2SC(bus); 694 695 return sc->sc_dying; 696 } 697 698 Static void 699 uhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 700 { 701 struct uhci_softc *sc = UHCI_BUS2SC(bus); 702 703 *lock = &sc->sc_lock; 704 } 705 706 707 /* 708 * Handle suspend/resume. 709 * 710 * We need to switch to polling mode here, because this routine is 711 * called from an interrupt context. This is all right since we 712 * are almost suspended anyway. 713 */ 714 bool 715 uhci_resume(device_t dv, const pmf_qual_t *qual) 716 { 717 uhci_softc_t *sc = device_private(dv); 718 int cmd; 719 720 mutex_spin_enter(&sc->sc_intr_lock); 721 722 cmd = UREAD2(sc, UHCI_CMD); 723 sc->sc_bus.ub_usepolling++; 724 UWRITE2(sc, UHCI_INTR, 0); 725 uhci_globalreset(sc); 726 uhci_reset(sc); 727 if (cmd & UHCI_CMD_RS) 728 uhci_run(sc, 0, 1); 729 730 /* restore saved state */ 731 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&sc->sc_dma, 0)); 732 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 733 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 734 735 UHCICMD(sc, cmd | UHCI_CMD_FGR); /* force resume */ 736 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_DELAY, &sc->sc_intr_lock); 737 UHCICMD(sc, cmd & ~UHCI_CMD_EGSM); /* back to normal */ 738 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | 739 UHCI_INTR_RIE | UHCI_INTR_IOCE | UHCI_INTR_SPIE); 740 UHCICMD(sc, UHCI_CMD_MAXP); 741 uhci_run(sc, 1, 1); /* and start traffic again */ 742 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_RECOVERY, &sc->sc_intr_lock); 743 sc->sc_bus.ub_usepolling--; 744 if (sc->sc_intr_xfer != NULL) 745 callout_schedule(&sc->sc_poll_handle, sc->sc_ival); 746 #ifdef UHCI_DEBUG 747 if (uhcidebug >= 2) 748 uhci_dumpregs(sc); 749 #endif 750 751 sc->sc_suspend = PWR_RESUME; 752 mutex_spin_exit(&sc->sc_intr_lock); 753 754 return true; 755 } 756 757 bool 758 uhci_suspend(device_t dv, const pmf_qual_t *qual) 759 { 760 uhci_softc_t *sc = device_private(dv); 761 int cmd; 762 763 mutex_spin_enter(&sc->sc_intr_lock); 764 765 cmd = UREAD2(sc, UHCI_CMD); 766 767 #ifdef UHCI_DEBUG 768 if (uhcidebug >= 2) 769 uhci_dumpregs(sc); 770 #endif 771 sc->sc_suspend = PWR_SUSPEND; 772 if (sc->sc_intr_xfer != NULL) 773 callout_halt(&sc->sc_poll_handle, &sc->sc_intr_lock); 774 sc->sc_bus.ub_usepolling++; 775 776 uhci_run(sc, 0, 1); /* stop the controller */ 777 cmd &= ~UHCI_CMD_RS; 778 779 /* save some state if BIOS doesn't */ 780 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 781 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 782 783 UWRITE2(sc, UHCI_INTR, 0); /* disable intrs */ 784 785 UHCICMD(sc, cmd | UHCI_CMD_EGSM); /* enter suspend */ 786 usb_delay_ms_locked(&sc->sc_bus, USB_RESUME_WAIT, &sc->sc_intr_lock); 787 sc->sc_bus.ub_usepolling--; 788 789 mutex_spin_exit(&sc->sc_intr_lock); 790 791 return true; 792 } 793 794 #ifdef UHCI_DEBUG 795 Static void 796 uhci_dumpregs(uhci_softc_t *sc) 797 { 798 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 799 DPRINTF("cmd =%04jx sts =%04jx intr =%04jx frnum =%04jx", 800 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 801 UREAD2(sc, UHCI_INTR), UREAD2(sc, UHCI_FRNUM)); 802 DPRINTF("sof =%04jx portsc1=%04jx portsc2=%04jx flbase=%08jx", 803 UREAD1(sc, UHCI_SOF), UREAD2(sc, UHCI_PORTSC1), 804 UREAD2(sc, UHCI_PORTSC2), UREAD4(sc, UHCI_FLBASEADDR)); 805 } 806 807 void 808 uhci_dump_td(uhci_soft_td_t *p) 809 { 810 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 811 812 usb_syncmem(&p->dma, p->offs, sizeof(p->td), 813 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 814 815 DPRINTF("TD(%#jx) at 0x%08jx", (uintptr_t)p, p->physaddr, 0, 0); 816 DPRINTF(" link=0x%08jx status=0x%08jx " 817 "token=0x%08x buffer=0x%08x", 818 le32toh(p->td.td_link), 819 le32toh(p->td.td_status), 820 le32toh(p->td.td_token), 821 le32toh(p->td.td_buffer)); 822 823 DPRINTF("bitstuff=%jd crcto =%jd nak =%jd babble =%jd", 824 !!(le32toh(p->td.td_status) & UHCI_TD_BITSTUFF), 825 !!(le32toh(p->td.td_status) & UHCI_TD_CRCTO), 826 !!(le32toh(p->td.td_status) & UHCI_TD_NAK), 827 !!(le32toh(p->td.td_status) & UHCI_TD_BABBLE)); 828 DPRINTF("dbuffer =%jd stalled =%jd active =%jd ioc =%jd", 829 !!(le32toh(p->td.td_status) & UHCI_TD_DBUFFER), 830 !!(le32toh(p->td.td_status) & UHCI_TD_STALLED), 831 !!(le32toh(p->td.td_status) & UHCI_TD_ACTIVE), 832 !!(le32toh(p->td.td_status) & UHCI_TD_IOC)); 833 DPRINTF("ios =%jd ls =%jd spd =%jd", 834 !!(le32toh(p->td.td_status) & UHCI_TD_IOS), 835 !!(le32toh(p->td.td_status) & UHCI_TD_LS), 836 !!(le32toh(p->td.td_status) & UHCI_TD_SPD), 0); 837 DPRINTF("errcnt =%d actlen =%d pid=%02x", 838 UHCI_TD_GET_ERRCNT(le32toh(p->td.td_status)), 839 UHCI_TD_GET_ACTLEN(le32toh(p->td.td_status)), 840 UHCI_TD_GET_PID(le32toh(p->td.td_token)), 0); 841 DPRINTF("addr=%jd endpt=%jd D=%jd maxlen=%jd,", 842 UHCI_TD_GET_DEVADDR(le32toh(p->td.td_token)), 843 UHCI_TD_GET_ENDPT(le32toh(p->td.td_token)), 844 UHCI_TD_GET_DT(le32toh(p->td.td_token)), 845 UHCI_TD_GET_MAXLEN(le32toh(p->td.td_token))); 846 } 847 848 void 849 uhci_dump_qh(uhci_soft_qh_t *sqh) 850 { 851 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 852 853 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 854 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 855 856 DPRINTF("QH(%#jx) at 0x%08jx: hlink=%08jx elink=%08jx", (uintptr_t)sqh, 857 (int)sqh->physaddr, le32toh(sqh->qh.qh_hlink), 858 le32toh(sqh->qh.qh_elink)); 859 860 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 861 } 862 863 864 #if 1 865 void 866 uhci_dump(void) 867 { 868 uhci_dump_all(thesc); 869 } 870 #endif 871 872 void 873 uhci_dump_all(uhci_softc_t *sc) 874 { 875 uhci_dumpregs(sc); 876 /*printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link);*/ 877 uhci_dump_qhs(sc->sc_lctl_start); 878 } 879 880 881 void 882 uhci_dump_qhs(uhci_soft_qh_t *sqh) 883 { 884 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 885 886 uhci_dump_qh(sqh); 887 888 /* 889 * uhci_dump_qhs displays all the QHs and TDs from the given QH onwards 890 * Traverses sideways first, then down. 891 * 892 * QH1 893 * QH2 894 * No QH 895 * TD2.1 896 * TD2.2 897 * TD1.1 898 * etc. 899 * 900 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 901 */ 902 903 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 904 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 905 if (sqh->hlink != NULL && !(le32toh(sqh->qh.qh_hlink) & UHCI_PTR_T)) 906 uhci_dump_qhs(sqh->hlink); 907 else 908 DPRINTF("No QH", 0, 0, 0, 0); 909 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 910 911 if (sqh->elink != NULL && !(le32toh(sqh->qh.qh_elink) & UHCI_PTR_T)) 912 uhci_dump_tds(sqh->elink); 913 else 914 DPRINTF("No QH", 0, 0, 0, 0); 915 } 916 917 void 918 uhci_dump_tds(uhci_soft_td_t *std) 919 { 920 uhci_soft_td_t *td; 921 int stop; 922 923 for (td = std; td != NULL; td = td->link.std) { 924 uhci_dump_td(td); 925 926 /* 927 * Check whether the link pointer in this TD marks 928 * the link pointer as end of queue. This avoids 929 * printing the free list in case the queue/TD has 930 * already been moved there (seatbelt). 931 */ 932 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 933 sizeof(td->td.td_link), 934 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 935 stop = (le32toh(td->td.td_link) & UHCI_PTR_T || 936 le32toh(td->td.td_link) == 0); 937 usb_syncmem(&td->dma, td->offs + offsetof(uhci_td_t, td_link), 938 sizeof(td->td.td_link), BUS_DMASYNC_PREREAD); 939 if (stop) 940 break; 941 } 942 } 943 944 Static void 945 uhci_dump_ii(struct uhci_xfer *ux) 946 { 947 struct usbd_pipe *pipe; 948 usb_endpoint_descriptor_t *ed; 949 struct usbd_device *dev; 950 951 if (ux == NULL) { 952 printf("ux NULL\n"); 953 return; 954 } 955 pipe = ux->ux_xfer.ux_pipe; 956 if (pipe == NULL) { 957 printf("ux %p: done=%d pipe=NULL\n", ux, ux->ux_isdone); 958 return; 959 } 960 if (pipe->up_endpoint == NULL) { 961 printf("ux %p: done=%d pipe=%p pipe->up_endpoint=NULL\n", 962 ux, ux->ux_isdone, pipe); 963 return; 964 } 965 if (pipe->up_dev == NULL) { 966 printf("ux %p: done=%d pipe=%p pipe->up_dev=NULL\n", 967 ux, ux->ux_isdone, pipe); 968 return; 969 } 970 ed = pipe->up_endpoint->ue_edesc; 971 dev = pipe->up_dev; 972 printf("ux %p: done=%d dev=%p vid=0x%04x pid=0x%04x addr=%d pipe=%p ep=0x%02x attr=0x%02x\n", 973 ux, ux->ux_isdone, dev, 974 UGETW(dev->ud_ddesc.idVendor), 975 UGETW(dev->ud_ddesc.idProduct), 976 dev->ud_addr, pipe, 977 ed->bEndpointAddress, ed->bmAttributes); 978 } 979 980 void uhci_dump_iis(struct uhci_softc *sc); 981 void 982 uhci_dump_iis(struct uhci_softc *sc) 983 { 984 struct uhci_xfer *ux; 985 986 printf("interrupt list:\n"); 987 TAILQ_FOREACH(ux, &sc->sc_intrhead, ux_list) 988 uhci_dump_ii(ux); 989 } 990 991 void iidump(void); 992 void iidump(void) { uhci_dump_iis(thesc); } 993 994 #endif 995 996 /* 997 * This routine is executed periodically and simulates interrupts 998 * from the root controller interrupt pipe for port status change. 999 */ 1000 void 1001 uhci_poll_hub(void *addr) 1002 { 1003 struct uhci_softc *sc = addr; 1004 struct usbd_xfer *xfer; 1005 u_char *p; 1006 1007 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1008 1009 mutex_enter(&sc->sc_lock); 1010 1011 /* 1012 * If the intr xfer has completed or been synchronously 1013 * aborted, we have nothing to do. 1014 */ 1015 xfer = sc->sc_intr_xfer; 1016 if (xfer == NULL) 1017 goto out; 1018 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1019 1020 /* 1021 * If the intr xfer for which we were scheduled is done, and 1022 * another intr xfer has been submitted, let that one be dealt 1023 * with when the callout fires again. 1024 * 1025 * The call to callout_pending is racy, but the the transition 1026 * from pending to invoking happens atomically. The 1027 * callout_ack ensures callout_invoking does not return true 1028 * due to this invocation of the callout; the lock ensures the 1029 * next invocation of the callout cannot callout_ack (unless it 1030 * had already run to completion and nulled sc->sc_intr_xfer, 1031 * in which case would have bailed out already). 1032 */ 1033 callout_ack(&sc->sc_poll_handle); 1034 if (callout_pending(&sc->sc_poll_handle) || 1035 callout_invoking(&sc->sc_poll_handle)) 1036 goto out; 1037 1038 /* 1039 * Check flags for the two interrupt ports, and set them in the 1040 * buffer if an interrupt arrived; otherwise arrange . 1041 */ 1042 p = xfer->ux_buf; 1043 p[0] = 0; 1044 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1045 p[0] |= 1<<1; 1046 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 1047 p[0] |= 1<<2; 1048 if (p[0] == 0) { 1049 /* 1050 * No change -- try again in a while, unless we're 1051 * suspending, in which case we'll try again after 1052 * resume. 1053 */ 1054 if (sc->sc_suspend != PWR_SUSPEND) 1055 callout_schedule(&sc->sc_poll_handle, sc->sc_ival); 1056 goto out; 1057 } 1058 1059 /* 1060 * Interrupt completed, and the xfer has not been completed or 1061 * synchronously aborted. Complete the xfer now. 1062 */ 1063 xfer->ux_actlen = 1; 1064 xfer->ux_status = USBD_NORMAL_COMPLETION; 1065 #ifdef DIAGNOSTIC 1066 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 1067 #endif 1068 usb_transfer_complete(xfer); 1069 1070 out: mutex_exit(&sc->sc_lock); 1071 } 1072 1073 void 1074 uhci_root_intr_done(struct usbd_xfer *xfer) 1075 { 1076 struct uhci_softc *sc = UHCI_XFER2SC(xfer); 1077 1078 KASSERT(mutex_owned(&sc->sc_lock)); 1079 1080 /* Claim the xfer so it doesn't get completed again. */ 1081 KASSERT(sc->sc_intr_xfer == xfer); 1082 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1083 sc->sc_intr_xfer = NULL; 1084 } 1085 1086 /* 1087 * Let the last QH loop back to the high speed control transfer QH. 1088 * This is what intel calls "bandwidth reclamation" and improves 1089 * USB performance a lot for some devices. 1090 * If we are already looping, just count it. 1091 */ 1092 void 1093 uhci_add_loop(uhci_softc_t *sc) 1094 { 1095 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1096 1097 #ifdef UHCI_DEBUG 1098 if (uhcinoloop) 1099 return; 1100 #endif 1101 if (++sc->sc_loops == 1) { 1102 DPRINTFN(5, "add loop", 0, 0, 0, 0); 1103 /* Note, we don't loop back the soft pointer. */ 1104 sc->sc_last_qh->qh.qh_hlink = 1105 htole32(sc->sc_hctl_start->physaddr | UHCI_PTR_QH); 1106 usb_syncmem(&sc->sc_last_qh->dma, 1107 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1108 sizeof(sc->sc_last_qh->qh.qh_hlink), 1109 BUS_DMASYNC_PREWRITE); 1110 } 1111 } 1112 1113 void 1114 uhci_rem_loop(uhci_softc_t *sc) 1115 { 1116 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1117 1118 #ifdef UHCI_DEBUG 1119 if (uhcinoloop) 1120 return; 1121 #endif 1122 if (--sc->sc_loops == 0) { 1123 DPRINTFN(5, "remove loop", 0, 0, 0, 0); 1124 sc->sc_last_qh->qh.qh_hlink = htole32(UHCI_PTR_T); 1125 usb_syncmem(&sc->sc_last_qh->dma, 1126 sc->sc_last_qh->offs + offsetof(uhci_qh_t, qh_hlink), 1127 sizeof(sc->sc_last_qh->qh.qh_hlink), 1128 BUS_DMASYNC_PREWRITE); 1129 } 1130 } 1131 1132 /* Add high speed control QH, called with lock held. */ 1133 void 1134 uhci_add_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1135 { 1136 uhci_soft_qh_t *eqh; 1137 1138 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1139 1140 KASSERT(mutex_owned(&sc->sc_lock)); 1141 1142 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1143 eqh = sc->sc_hctl_end; 1144 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1145 sizeof(eqh->qh.qh_hlink), 1146 BUS_DMASYNC_POSTWRITE); 1147 sqh->hlink = eqh->hlink; 1148 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1149 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1150 BUS_DMASYNC_PREWRITE); 1151 eqh->hlink = sqh; 1152 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1153 sc->sc_hctl_end = sqh; 1154 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1155 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1156 #ifdef UHCI_CTL_LOOP 1157 uhci_add_loop(sc); 1158 #endif 1159 } 1160 1161 /* Remove high speed control QH, called with lock held. */ 1162 void 1163 uhci_remove_hs_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1164 { 1165 uhci_soft_qh_t *pqh; 1166 uint32_t elink; 1167 1168 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1169 1170 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1171 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1172 #ifdef UHCI_CTL_LOOP 1173 uhci_rem_loop(sc); 1174 #endif 1175 /* 1176 * The T bit should be set in the elink of the QH so that the HC 1177 * doesn't follow the pointer. This condition may fail if the 1178 * the transferred packet was short so that the QH still points 1179 * at the last used TD. 1180 * In this case we set the T bit and wait a little for the HC 1181 * to stop looking at the TD. 1182 * Note that if the TD chain is large enough, the controller 1183 * may still be looking at the chain at the end of this function. 1184 * uhci_free_std_chain() will make sure the controller stops 1185 * looking at it quickly, but until then we should not change 1186 * sqh->hlink. 1187 */ 1188 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1189 sizeof(sqh->qh.qh_elink), 1190 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1191 elink = le32toh(sqh->qh.qh_elink); 1192 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1193 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1194 if (!(elink & UHCI_PTR_T)) { 1195 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1196 usb_syncmem(&sqh->dma, 1197 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1198 sizeof(sqh->qh.qh_elink), 1199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1200 delay(UHCI_QH_REMOVE_DELAY); 1201 } 1202 1203 pqh = uhci_find_prev_qh(sc->sc_hctl_start, sqh); 1204 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1205 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1206 pqh->hlink = sqh->hlink; 1207 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1208 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1209 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1210 delay(UHCI_QH_REMOVE_DELAY); 1211 if (sc->sc_hctl_end == sqh) 1212 sc->sc_hctl_end = pqh; 1213 } 1214 1215 /* Add low speed control QH, called with lock held. */ 1216 void 1217 uhci_add_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1218 { 1219 uhci_soft_qh_t *eqh; 1220 1221 KASSERT(mutex_owned(&sc->sc_lock)); 1222 1223 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1224 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1225 1226 eqh = sc->sc_lctl_end; 1227 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1228 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1229 sqh->hlink = eqh->hlink; 1230 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1231 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1232 BUS_DMASYNC_PREWRITE); 1233 eqh->hlink = sqh; 1234 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1235 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1236 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1237 sc->sc_lctl_end = sqh; 1238 } 1239 1240 /* Remove low speed control QH, called with lock held. */ 1241 void 1242 uhci_remove_ls_ctrl(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1243 { 1244 uhci_soft_qh_t *pqh; 1245 uint32_t elink; 1246 1247 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1248 1249 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1250 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1251 1252 /* See comment in uhci_remove_hs_ctrl() */ 1253 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1254 sizeof(sqh->qh.qh_elink), 1255 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1256 elink = le32toh(sqh->qh.qh_elink); 1257 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1258 sizeof(sqh->qh.qh_elink), BUS_DMASYNC_PREREAD); 1259 if (!(elink & UHCI_PTR_T)) { 1260 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1261 usb_syncmem(&sqh->dma, 1262 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1263 sizeof(sqh->qh.qh_elink), 1264 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1265 delay(UHCI_QH_REMOVE_DELAY); 1266 } 1267 pqh = uhci_find_prev_qh(sc->sc_lctl_start, sqh); 1268 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1269 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1270 pqh->hlink = sqh->hlink; 1271 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1272 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1273 sizeof(pqh->qh.qh_hlink), 1274 BUS_DMASYNC_PREWRITE); 1275 delay(UHCI_QH_REMOVE_DELAY); 1276 if (sc->sc_lctl_end == sqh) 1277 sc->sc_lctl_end = pqh; 1278 } 1279 1280 /* Add bulk QH, called with lock held. */ 1281 void 1282 uhci_add_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1283 { 1284 uhci_soft_qh_t *eqh; 1285 1286 KASSERT(mutex_owned(&sc->sc_lock)); 1287 1288 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1289 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1290 1291 eqh = sc->sc_bulk_end; 1292 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1293 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1294 sqh->hlink = eqh->hlink; 1295 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 1296 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1297 BUS_DMASYNC_PREWRITE); 1298 eqh->hlink = sqh; 1299 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 1300 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 1301 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1302 sc->sc_bulk_end = sqh; 1303 uhci_add_loop(sc); 1304 } 1305 1306 /* Remove bulk QH, called with lock held. */ 1307 void 1308 uhci_remove_bulk(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1309 { 1310 uhci_soft_qh_t *pqh; 1311 1312 KASSERT(mutex_owned(&sc->sc_lock)); 1313 1314 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1315 DPRINTFN(10, "sqh %#jx", (uintptr_t)sqh, 0, 0, 0); 1316 1317 uhci_rem_loop(sc); 1318 /* See comment in uhci_remove_hs_ctrl() */ 1319 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 1320 sizeof(sqh->qh.qh_elink), 1321 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1322 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 1323 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 1324 usb_syncmem(&sqh->dma, 1325 sqh->offs + offsetof(uhci_qh_t, qh_elink), 1326 sizeof(sqh->qh.qh_elink), 1327 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1328 delay(UHCI_QH_REMOVE_DELAY); 1329 } 1330 pqh = uhci_find_prev_qh(sc->sc_bulk_start, sqh); 1331 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 1332 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 1333 pqh->hlink = sqh->hlink; 1334 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 1335 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 1336 sizeof(pqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 1337 delay(UHCI_QH_REMOVE_DELAY); 1338 if (sc->sc_bulk_end == sqh) 1339 sc->sc_bulk_end = pqh; 1340 } 1341 1342 Static int uhci_intr1(uhci_softc_t *); 1343 1344 int 1345 uhci_intr(void *arg) 1346 { 1347 uhci_softc_t *sc = arg; 1348 int ret = 0; 1349 1350 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1351 1352 mutex_spin_enter(&sc->sc_intr_lock); 1353 1354 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1355 goto done; 1356 1357 if (sc->sc_bus.ub_usepolling || UREAD2(sc, UHCI_INTR) == 0) { 1358 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1359 goto done; 1360 } 1361 1362 ret = uhci_intr1(sc); 1363 1364 done: 1365 mutex_spin_exit(&sc->sc_intr_lock); 1366 return ret; 1367 } 1368 1369 int 1370 uhci_intr1(uhci_softc_t *sc) 1371 { 1372 int status; 1373 int ack; 1374 1375 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1376 1377 #ifdef UHCI_DEBUG 1378 if (uhcidebug >= 15) { 1379 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1380 uhci_dumpregs(sc); 1381 } 1382 #endif 1383 1384 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1385 1386 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1387 /* Check if the interrupt was for us. */ 1388 if (status == 0) 1389 return 0; 1390 1391 if (sc->sc_suspend != PWR_RESUME) { 1392 #ifdef DIAGNOSTIC 1393 printf("%s: interrupt while not operating ignored\n", 1394 device_xname(sc->sc_dev)); 1395 #endif 1396 UWRITE2(sc, UHCI_STS, status); /* acknowledge the ints */ 1397 return 0; 1398 } 1399 1400 ack = 0; 1401 if (status & UHCI_STS_USBINT) 1402 ack |= UHCI_STS_USBINT; 1403 if (status & UHCI_STS_USBEI) 1404 ack |= UHCI_STS_USBEI; 1405 if (status & UHCI_STS_RD) { 1406 ack |= UHCI_STS_RD; 1407 #ifdef UHCI_DEBUG 1408 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1409 #endif 1410 } 1411 if (status & UHCI_STS_HSE) { 1412 ack |= UHCI_STS_HSE; 1413 printf("%s: host system error\n", device_xname(sc->sc_dev)); 1414 } 1415 if (status & UHCI_STS_HCPE) { 1416 ack |= UHCI_STS_HCPE; 1417 printf("%s: host controller process error\n", 1418 device_xname(sc->sc_dev)); 1419 } 1420 1421 /* When HCHalted=1 and Run/Stop=0 , it is normal */ 1422 if ((status & UHCI_STS_HCH) && (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 1423 /* no acknowledge needed */ 1424 if (!sc->sc_dying) { 1425 printf("%s: host controller halted\n", 1426 device_xname(sc->sc_dev)); 1427 #ifdef UHCI_DEBUG 1428 uhci_dump_all(sc); 1429 #endif 1430 } 1431 sc->sc_dying = 1; 1432 } 1433 1434 if (!ack) 1435 return 0; /* nothing to acknowledge */ 1436 UWRITE2(sc, UHCI_STS, ack); /* acknowledge the ints */ 1437 1438 usb_schedsoftintr(&sc->sc_bus); 1439 1440 DPRINTFN(15, "sc %#jx done", (uintptr_t)sc, 0, 0, 0); 1441 1442 return 1; 1443 } 1444 1445 void 1446 uhci_softintr(void *v) 1447 { 1448 struct usbd_bus *bus = v; 1449 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1450 struct uhci_xfer *ux, *nextux; 1451 ux_completeq_t cq; 1452 1453 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1454 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1455 1456 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1457 1458 TAILQ_INIT(&cq); 1459 /* 1460 * Interrupts on UHCI really suck. When the host controller 1461 * interrupts because a transfer is completed there is no 1462 * way of knowing which transfer it was. You can scan down 1463 * the TDs and QHs of the previous frame to limit the search, 1464 * but that assumes that the interrupt was not delayed by more 1465 * than 1 ms, which may not always be true (e.g. after debug 1466 * output on a slow console). 1467 * We scan all interrupt descriptors to see if any have 1468 * completed. 1469 */ 1470 TAILQ_FOREACH_SAFE(ux, &sc->sc_intrhead, ux_list, nextux) { 1471 uhci_check_intr(sc, ux, &cq); 1472 } 1473 1474 /* 1475 * We abuse ux_list for the interrupt and complete lists and 1476 * interrupt transfers will get re-added here so use 1477 * the _SAFE version of TAILQ_FOREACH. 1478 */ 1479 TAILQ_FOREACH_SAFE(ux, &cq, ux_list, nextux) { 1480 DPRINTF("ux %#jx", (uintptr_t)ux, 0, 0, 0); 1481 usb_transfer_complete(&ux->ux_xfer); 1482 } 1483 1484 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1485 } 1486 1487 /* Check for an interrupt. */ 1488 void 1489 uhci_check_intr(uhci_softc_t *sc, struct uhci_xfer *ux, ux_completeq_t *cqp) 1490 { 1491 uhci_soft_td_t *std, *fstd = NULL, *lstd = NULL; 1492 uint32_t status; 1493 1494 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1495 DPRINTFN(15, "ux %#jx", (uintptr_t)ux, 0, 0, 0); 1496 1497 KASSERT(ux != NULL); 1498 1499 struct usbd_xfer *xfer = &ux->ux_xfer; 1500 if (xfer->ux_status == USBD_CANCELLED || 1501 xfer->ux_status == USBD_TIMEOUT) { 1502 DPRINTF("aborted xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1503 return; 1504 } 1505 1506 switch (ux->ux_type) { 1507 case UX_CTRL: 1508 fstd = ux->ux_setup; 1509 lstd = ux->ux_stat; 1510 break; 1511 case UX_BULK: 1512 case UX_INTR: 1513 case UX_ISOC: 1514 fstd = ux->ux_stdstart; 1515 lstd = ux->ux_stdend; 1516 break; 1517 default: 1518 KASSERT(false); 1519 break; 1520 } 1521 if (fstd == NULL) 1522 return; 1523 1524 KASSERT(lstd != NULL); 1525 1526 usb_syncmem(&lstd->dma, 1527 lstd->offs + offsetof(uhci_td_t, td_status), 1528 sizeof(lstd->td.td_status), 1529 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1530 status = le32toh(lstd->td.td_status); 1531 usb_syncmem(&lstd->dma, 1532 lstd->offs + offsetof(uhci_td_t, td_status), 1533 sizeof(lstd->td.td_status), 1534 BUS_DMASYNC_PREREAD); 1535 1536 /* If the last TD is not marked active we can complete */ 1537 if (!(status & UHCI_TD_ACTIVE)) { 1538 done: 1539 DPRINTFN(12, "ux=%#jx done", (uintptr_t)ux, 0, 0, 0); 1540 uhci_idone(ux, cqp); 1541 return; 1542 } 1543 1544 /* 1545 * If the last TD is still active we need to check whether there 1546 * is an error somewhere in the middle, or whether there was a 1547 * short packet (SPD and not ACTIVE). 1548 */ 1549 DPRINTFN(12, "active ux=%#jx", (uintptr_t)ux, 0, 0, 0); 1550 for (std = fstd; std != lstd; std = std->link.std) { 1551 usb_syncmem(&std->dma, 1552 std->offs + offsetof(uhci_td_t, td_status), 1553 sizeof(std->td.td_status), 1554 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1555 status = le32toh(std->td.td_status); 1556 usb_syncmem(&std->dma, 1557 std->offs + offsetof(uhci_td_t, td_status), 1558 sizeof(std->td.td_status), BUS_DMASYNC_PREREAD); 1559 1560 /* If there's an active TD the xfer isn't done. */ 1561 if (status & UHCI_TD_ACTIVE) { 1562 DPRINTFN(12, "ux=%#jx std=%#jx still active", 1563 (uintptr_t)ux, (uintptr_t)std, 0, 0); 1564 return; 1565 } 1566 1567 /* Any kind of error makes the xfer done. */ 1568 if (status & UHCI_TD_STALLED) 1569 goto done; 1570 1571 /* 1572 * If the data phase of a control transfer is short, we need 1573 * to complete the status stage 1574 */ 1575 1576 if ((status & UHCI_TD_SPD) && ux->ux_type == UX_CTRL) { 1577 struct uhci_pipe *upipe = 1578 UHCI_PIPE2UPIPE(xfer->ux_pipe); 1579 uhci_soft_qh_t *sqh = upipe->ctrl.sqh; 1580 uhci_soft_td_t *stat = upipe->ctrl.stat; 1581 1582 DPRINTFN(12, "ux=%#jx std=%#jx control status" 1583 "phase needs completion", (uintptr_t)ux, 1584 (uintptr_t)ux->ux_stdstart, 0, 0); 1585 1586 sqh->qh.qh_elink = 1587 htole32(stat->physaddr | UHCI_PTR_TD); 1588 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1589 BUS_DMASYNC_PREWRITE); 1590 break; 1591 } 1592 1593 /* We want short packets, and it is short: it's done */ 1594 usb_syncmem(&std->dma, 1595 std->offs + offsetof(uhci_td_t, td_token), 1596 sizeof(std->td.td_token), 1597 BUS_DMASYNC_POSTWRITE); 1598 1599 if ((status & UHCI_TD_SPD) && 1600 UHCI_TD_GET_ACTLEN(status) < 1601 UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token))) { 1602 goto done; 1603 } 1604 } 1605 } 1606 1607 /* Called with USB lock held. */ 1608 void 1609 uhci_idone(struct uhci_xfer *ux, ux_completeq_t *cqp) 1610 { 1611 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1612 struct usbd_xfer *xfer = &ux->ux_xfer; 1613 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 1614 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 1615 uhci_soft_td_t *std; 1616 uint32_t status = 0, nstatus; 1617 const bool polling __diagused = sc->sc_bus.ub_usepolling; 1618 int actlen; 1619 1620 KASSERT(polling || mutex_owned(&sc->sc_lock)); 1621 1622 DPRINTFN(12, "ux=%#jx", (uintptr_t)ux, 0, 0, 0); 1623 1624 /* 1625 * Try to claim this xfer for completion. If it has already 1626 * completed or aborted, drop it on the floor. 1627 */ 1628 if (!usbd_xfer_trycomplete(xfer)) 1629 return; 1630 1631 #ifdef DIAGNOSTIC 1632 #ifdef UHCI_DEBUG 1633 if (ux->ux_isdone) { 1634 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1635 uhci_dump_ii(ux); 1636 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1637 } 1638 #endif 1639 KASSERT(!ux->ux_isdone); 1640 KASSERTMSG(!ux->ux_isdone, "xfer %p type %d status %d", xfer, 1641 ux->ux_type, xfer->ux_status); 1642 ux->ux_isdone = true; 1643 #endif 1644 1645 if (xfer->ux_nframes != 0) { 1646 /* Isoc transfer, do things differently. */ 1647 uhci_soft_td_t **stds = upipe->isoc.stds; 1648 int i, n, nframes, len; 1649 1650 DPRINTFN(5, "ux=%#jx isoc ready", (uintptr_t)ux, 0, 0, 0); 1651 1652 nframes = xfer->ux_nframes; 1653 actlen = 0; 1654 n = ux->ux_curframe; 1655 for (i = 0; i < nframes; i++) { 1656 std = stds[n]; 1657 #ifdef UHCI_DEBUG 1658 if (uhcidebug >= 5) { 1659 DPRINTF("isoc TD %jd", i, 0, 0, 0); 1660 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1661 uhci_dump_td(std); 1662 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1663 } 1664 #endif 1665 if (++n >= UHCI_VFRAMELIST_COUNT) 1666 n = 0; 1667 usb_syncmem(&std->dma, 1668 std->offs + offsetof(uhci_td_t, td_status), 1669 sizeof(std->td.td_status), 1670 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1671 status = le32toh(std->td.td_status); 1672 len = UHCI_TD_GET_ACTLEN(status); 1673 xfer->ux_frlengths[i] = len; 1674 actlen += len; 1675 } 1676 upipe->isoc.inuse -= nframes; 1677 xfer->ux_actlen = actlen; 1678 xfer->ux_status = USBD_NORMAL_COMPLETION; 1679 goto end; 1680 } 1681 1682 #ifdef UHCI_DEBUG 1683 DPRINTFN(10, "ux=%#jx, xfer=%#jx, pipe=%#jx ready", (uintptr_t)ux, 1684 (uintptr_t)xfer, (uintptr_t)upipe, 0); 1685 if (uhcidebug >= 10) { 1686 DPRINTF("--- dump start ---", 0, 0, 0, 0); 1687 uhci_dump_tds(ux->ux_stdstart); 1688 DPRINTF("--- dump end ---", 0, 0, 0, 0); 1689 } 1690 #endif 1691 1692 /* The transfer is done, compute actual length and status. */ 1693 actlen = 0; 1694 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 1695 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1696 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1697 nstatus = le32toh(std->td.td_status); 1698 if (nstatus & UHCI_TD_ACTIVE) 1699 break; 1700 1701 status = nstatus; 1702 if (UHCI_TD_GET_PID(le32toh(std->td.td_token)) != 1703 UHCI_TD_PID_SETUP) 1704 actlen += UHCI_TD_GET_ACTLEN(status); 1705 else { 1706 /* 1707 * UHCI will report CRCTO in addition to a STALL or NAK 1708 * for a SETUP transaction. See section 3.2.2, "TD 1709 * CONTROL AND STATUS". 1710 */ 1711 if (status & (UHCI_TD_STALLED | UHCI_TD_NAK)) 1712 status &= ~UHCI_TD_CRCTO; 1713 } 1714 } 1715 /* If there are left over TDs we need to update the toggle. */ 1716 if (std != NULL) 1717 upipe->nexttoggle = UHCI_TD_GET_DT(le32toh(std->td.td_token)); 1718 1719 status &= UHCI_TD_ERROR; 1720 DPRINTFN(10, "actlen=%jd, status=%#jx", actlen, status, 0, 0); 1721 xfer->ux_actlen = actlen; 1722 if (status != 0) { 1723 1724 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1725 "error, addr=%jd, endpt=0x%02jx", 1726 xfer->ux_pipe->up_dev->ud_addr, 1727 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1728 0, 0); 1729 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1730 "bitstuff=%jd crcto =%jd nak =%jd babble =%jd", 1731 !!(status & UHCI_TD_BITSTUFF), 1732 !!(status & UHCI_TD_CRCTO), 1733 !!(status & UHCI_TD_NAK), 1734 !!(status & UHCI_TD_BABBLE)); 1735 DPRINTFN((status == UHCI_TD_STALLED) * 10, 1736 "dbuffer =%jd stalled =%jd active =%jd", 1737 !!(status & UHCI_TD_DBUFFER), 1738 !!(status & UHCI_TD_STALLED), 1739 !!(status & UHCI_TD_ACTIVE), 1740 0); 1741 1742 if (status == UHCI_TD_STALLED) 1743 xfer->ux_status = USBD_STALLED; 1744 else 1745 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1746 } else { 1747 xfer->ux_status = USBD_NORMAL_COMPLETION; 1748 } 1749 1750 end: 1751 uhci_del_intr_list(sc, ux); 1752 if (cqp) 1753 TAILQ_INSERT_TAIL(cqp, ux, ux_list); 1754 1755 KASSERT(polling || mutex_owned(&sc->sc_lock)); 1756 DPRINTFN(12, "ux=%#jx done", (uintptr_t)ux, 0, 0, 0); 1757 } 1758 1759 void 1760 uhci_poll(struct usbd_bus *bus) 1761 { 1762 uhci_softc_t *sc = UHCI_BUS2SC(bus); 1763 1764 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 1765 mutex_spin_enter(&sc->sc_intr_lock); 1766 uhci_intr1(sc); 1767 mutex_spin_exit(&sc->sc_intr_lock); 1768 } 1769 } 1770 1771 void 1772 uhci_reset(uhci_softc_t *sc) 1773 { 1774 int n; 1775 1776 UHCICMD(sc, UHCI_CMD_HCRESET); 1777 /* The reset bit goes low when the controller is done. */ 1778 for (n = 0; n < UHCI_RESET_TIMEOUT && 1779 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 1780 usb_delay_ms(&sc->sc_bus, 1); 1781 if (n >= UHCI_RESET_TIMEOUT) 1782 printf("%s: controller did not reset\n", 1783 device_xname(sc->sc_dev)); 1784 } 1785 1786 usbd_status 1787 uhci_run(uhci_softc_t *sc, int run, int locked) 1788 { 1789 int n, running; 1790 uint16_t cmd; 1791 1792 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1793 1794 run = run != 0; 1795 if (!locked) 1796 mutex_spin_enter(&sc->sc_intr_lock); 1797 1798 DPRINTF("setting run=%jd", run, 0, 0, 0); 1799 cmd = UREAD2(sc, UHCI_CMD); 1800 if (run) 1801 cmd |= UHCI_CMD_RS; 1802 else 1803 cmd &= ~UHCI_CMD_RS; 1804 UHCICMD(sc, cmd); 1805 for (n = 0; n < 10; n++) { 1806 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 1807 /* return when we've entered the state we want */ 1808 if (run == running) { 1809 if (!locked) 1810 mutex_spin_exit(&sc->sc_intr_lock); 1811 DPRINTF("done cmd=%#jx sts=%#jx", 1812 UREAD2(sc, UHCI_CMD), UREAD2(sc, UHCI_STS), 0, 0); 1813 return USBD_NORMAL_COMPLETION; 1814 } 1815 usb_delay_ms_locked(&sc->sc_bus, 1, &sc->sc_intr_lock); 1816 } 1817 if (!locked) 1818 mutex_spin_exit(&sc->sc_intr_lock); 1819 printf("%s: cannot %s\n", device_xname(sc->sc_dev), 1820 run ? "start" : "stop"); 1821 return USBD_IOERROR; 1822 } 1823 1824 /* 1825 * Memory management routines. 1826 * uhci_alloc_std allocates TDs 1827 * uhci_alloc_sqh allocates QHs 1828 * These two routines do their own free list management, 1829 * partly for speed, partly because allocating DMAable memory 1830 * has page size granularity so much memory would be wasted if 1831 * only one TD/QH (32 bytes) was placed in each allocated chunk. 1832 */ 1833 1834 uhci_soft_td_t * 1835 uhci_alloc_std(uhci_softc_t *sc) 1836 { 1837 uhci_soft_td_t *std; 1838 usbd_status err; 1839 int i, offs; 1840 usb_dma_t dma; 1841 1842 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1843 1844 mutex_enter(&sc->sc_lock); 1845 if (sc->sc_freetds == NULL) { 1846 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1847 mutex_exit(&sc->sc_lock); 1848 1849 err = usb_allocmem(&sc->sc_bus, UHCI_STD_SIZE * UHCI_STD_CHUNK, 1850 UHCI_TD_ALIGN, USBMALLOC_COHERENT, &dma); 1851 if (err) 1852 return NULL; 1853 1854 mutex_enter(&sc->sc_lock); 1855 for (i = 0; i < UHCI_STD_CHUNK; i++) { 1856 offs = i * UHCI_STD_SIZE; 1857 std = KERNADDR(&dma, offs); 1858 std->physaddr = DMAADDR(&dma, offs); 1859 std->dma = dma; 1860 std->offs = offs; 1861 std->link.std = sc->sc_freetds; 1862 sc->sc_freetds = std; 1863 } 1864 } 1865 std = sc->sc_freetds; 1866 sc->sc_freetds = std->link.std; 1867 mutex_exit(&sc->sc_lock); 1868 1869 memset(&std->td, 0, sizeof(uhci_td_t)); 1870 1871 return std; 1872 } 1873 1874 #define TD_IS_FREE 0x12345678 1875 1876 void 1877 uhci_free_std_locked(uhci_softc_t *sc, uhci_soft_td_t *std) 1878 { 1879 KASSERT(mutex_owned(&sc->sc_lock)); 1880 1881 #ifdef DIAGNOSTIC 1882 if (le32toh(std->td.td_token) == TD_IS_FREE) { 1883 printf("%s: freeing free TD %p\n", __func__, std); 1884 return; 1885 } 1886 std->td.td_token = htole32(TD_IS_FREE); 1887 #endif 1888 1889 std->link.std = sc->sc_freetds; 1890 sc->sc_freetds = std; 1891 } 1892 1893 void 1894 uhci_free_std(uhci_softc_t *sc, uhci_soft_td_t *std) 1895 { 1896 mutex_enter(&sc->sc_lock); 1897 uhci_free_std_locked(sc, std); 1898 mutex_exit(&sc->sc_lock); 1899 } 1900 1901 uhci_soft_qh_t * 1902 uhci_alloc_sqh(uhci_softc_t *sc) 1903 { 1904 uhci_soft_qh_t *sqh; 1905 usbd_status err; 1906 int i, offs; 1907 usb_dma_t dma; 1908 1909 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1910 1911 mutex_enter(&sc->sc_lock); 1912 if (sc->sc_freeqhs == NULL) { 1913 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 1914 mutex_exit(&sc->sc_lock); 1915 1916 err = usb_allocmem(&sc->sc_bus, UHCI_SQH_SIZE * UHCI_SQH_CHUNK, 1917 UHCI_QH_ALIGN, USBMALLOC_COHERENT, &dma); 1918 if (err) 1919 return NULL; 1920 1921 mutex_enter(&sc->sc_lock); 1922 for (i = 0; i < UHCI_SQH_CHUNK; i++) { 1923 offs = i * UHCI_SQH_SIZE; 1924 sqh = KERNADDR(&dma, offs); 1925 sqh->physaddr = DMAADDR(&dma, offs); 1926 sqh->dma = dma; 1927 sqh->offs = offs; 1928 sqh->hlink = sc->sc_freeqhs; 1929 sc->sc_freeqhs = sqh; 1930 } 1931 } 1932 sqh = sc->sc_freeqhs; 1933 sc->sc_freeqhs = sqh->hlink; 1934 mutex_exit(&sc->sc_lock); 1935 1936 memset(&sqh->qh, 0, sizeof(uhci_qh_t)); 1937 1938 return sqh; 1939 } 1940 1941 void 1942 uhci_free_sqh(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 1943 { 1944 KASSERT(mutex_owned(&sc->sc_lock)); 1945 1946 sqh->hlink = sc->sc_freeqhs; 1947 sc->sc_freeqhs = sqh; 1948 } 1949 1950 #if 0 1951 void 1952 uhci_free_std_chain(uhci_softc_t *sc, uhci_soft_td_t *std, 1953 uhci_soft_td_t *stdend) 1954 { 1955 uhci_soft_td_t *p; 1956 uint32_t td_link; 1957 1958 /* 1959 * to avoid race condition with the controller which may be looking 1960 * at this chain, we need to first invalidate all links, and 1961 * then wait for the controller to move to another queue 1962 */ 1963 for (p = std; p != stdend; p = p->link.std) { 1964 usb_syncmem(&p->dma, 1965 p->offs + offsetof(uhci_td_t, td_link), 1966 sizeof(p->td.td_link), 1967 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1968 td_link = le32toh(p->td.td_link); 1969 usb_syncmem(&p->dma, 1970 p->offs + offsetof(uhci_td_t, td_link), 1971 sizeof(p->td.td_link), 1972 BUS_DMASYNC_PREREAD); 1973 if ((td_link & UHCI_PTR_T) == 0) { 1974 p->td.td_link = htole32(UHCI_PTR_T); 1975 usb_syncmem(&p->dma, 1976 p->offs + offsetof(uhci_td_t, td_link), 1977 sizeof(p->td.td_link), 1978 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1979 } 1980 } 1981 delay(UHCI_QH_REMOVE_DELAY); 1982 1983 for (; std != stdend; std = p) { 1984 p = std->link.std; 1985 uhci_free_std(sc, std); 1986 } 1987 } 1988 #endif 1989 1990 int 1991 uhci_alloc_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, int len, 1992 int rd, uhci_soft_td_t **sp) 1993 { 1994 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 1995 uint16_t flags = xfer->ux_flags; 1996 uhci_soft_td_t *p; 1997 1998 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 1999 2000 DPRINTFN(8, "xfer=%#jx pipe=%#jx", (uintptr_t)xfer, 2001 (uintptr_t)xfer->ux_pipe, 0, 0); 2002 2003 ASSERT_SLEEPABLE(); 2004 KASSERT(sp); 2005 2006 int maxp = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2007 if (maxp == 0) { 2008 printf("%s: maxp=0\n", __func__); 2009 return EINVAL; 2010 } 2011 size_t ntd = howmany(len, maxp); 2012 if (!rd && (flags & USBD_FORCE_SHORT_XFER)) { 2013 ntd++; 2014 } 2015 DPRINTFN(10, "maxp=%jd ntd=%jd", maxp, ntd, 0, 0); 2016 2017 uxfer->ux_stds = NULL; 2018 uxfer->ux_nstd = ntd; 2019 if (ntd == 0) { 2020 *sp = NULL; 2021 DPRINTF("ntd=0", 0, 0, 0, 0); 2022 return 0; 2023 } 2024 uxfer->ux_stds = kmem_alloc(sizeof(uhci_soft_td_t *) * ntd, 2025 KM_SLEEP); 2026 2027 for (int i = 0; i < ntd; i++) { 2028 p = uhci_alloc_std(sc); 2029 if (p == NULL) { 2030 if (i != 0) { 2031 uxfer->ux_nstd = i; 2032 uhci_free_stds(sc, uxfer); 2033 } 2034 kmem_free(uxfer->ux_stds, 2035 sizeof(uhci_soft_td_t *) * ntd); 2036 return ENOMEM; 2037 } 2038 uxfer->ux_stds[i] = p; 2039 } 2040 2041 *sp = uxfer->ux_stds[0]; 2042 2043 return 0; 2044 } 2045 2046 Static void 2047 uhci_free_stds(uhci_softc_t *sc, struct uhci_xfer *ux) 2048 { 2049 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2050 2051 DPRINTFN(8, "ux=%#jx", (uintptr_t)ux, 0, 0, 0); 2052 2053 mutex_enter(&sc->sc_lock); 2054 for (size_t i = 0; i < ux->ux_nstd; i++) { 2055 uhci_soft_td_t *std = ux->ux_stds[i]; 2056 #ifdef DIAGNOSTIC 2057 if (le32toh(std->td.td_token) == TD_IS_FREE) { 2058 printf("%s: freeing free TD %p\n", __func__, std); 2059 return; 2060 } 2061 std->td.td_token = htole32(TD_IS_FREE); 2062 #endif 2063 ux->ux_stds[i]->link.std = sc->sc_freetds; 2064 sc->sc_freetds = std; 2065 } 2066 mutex_exit(&sc->sc_lock); 2067 } 2068 2069 2070 Static void 2071 uhci_reset_std_chain(uhci_softc_t *sc, struct usbd_xfer *xfer, 2072 int length, int isread, int *toggle, uhci_soft_td_t **lstd) 2073 { 2074 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2075 struct usbd_pipe *pipe = xfer->ux_pipe; 2076 usb_dma_t *dma = &xfer->ux_dmabuf; 2077 uint16_t flags = xfer->ux_flags; 2078 uhci_soft_td_t *std, *prev; 2079 int len = length; 2080 int tog = *toggle; 2081 int maxp; 2082 uint32_t status; 2083 size_t i; 2084 2085 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2086 DPRINTFN(8, "xfer=%#jx len %jd isread %jd toggle %jd", (uintptr_t)xfer, 2087 len, isread, *toggle); 2088 2089 KASSERT(len != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2090 2091 maxp = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2092 KASSERT(maxp != 0); 2093 2094 int addr = xfer->ux_pipe->up_dev->ud_addr; 2095 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2096 2097 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | UHCI_TD_ACTIVE); 2098 if (pipe->up_dev->ud_speed == USB_SPEED_LOW) 2099 status |= UHCI_TD_LS; 2100 if (flags & USBD_SHORT_XFER_OK) 2101 status |= UHCI_TD_SPD; 2102 usb_syncmem(dma, 0, len, 2103 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2104 std = prev = NULL; 2105 for (i = 0; len != 0 && i < uxfer->ux_nstd; i++, prev = std) { 2106 int l = len; 2107 std = uxfer->ux_stds[i]; 2108 if (l > maxp) 2109 l = maxp; 2110 2111 if (prev) { 2112 prev->link.std = std; 2113 prev->td.td_link = htole32( 2114 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2115 ); 2116 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2117 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2118 } 2119 2120 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2121 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2122 2123 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2124 std->td.td_status = htole32(status); 2125 std->td.td_token = htole32( 2126 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2127 UHCI_TD_SET_DEVADDR(addr) | 2128 UHCI_TD_SET_PID(isread ? UHCI_TD_PID_IN : UHCI_TD_PID_OUT) | 2129 UHCI_TD_SET_DT(tog) | 2130 UHCI_TD_SET_MAXLEN(l) 2131 ); 2132 std->td.td_buffer = htole32(DMAADDR(dma, i * maxp)); 2133 2134 std->link.std = NULL; 2135 2136 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2137 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2138 tog ^= 1; 2139 2140 len -= l; 2141 } 2142 KASSERTMSG(len == 0, "xfer %p alen %d len %d mps %d ux_nqtd %zu i %zu", 2143 xfer, length, len, maxp, uxfer->ux_nstd, i); 2144 2145 if (!isread && 2146 (flags & USBD_FORCE_SHORT_XFER) && 2147 length % maxp == 0) { 2148 /* Force a 0 length transfer at the end. */ 2149 KASSERTMSG(i < uxfer->ux_nstd, "i=%zu nstd=%zu", i, 2150 uxfer->ux_nstd); 2151 std = uxfer->ux_stds[i++]; 2152 2153 std->td.td_link = htole32(UHCI_PTR_T | UHCI_PTR_VF | UHCI_PTR_TD); 2154 std->td.td_status = htole32(status); 2155 std->td.td_token = htole32( 2156 UHCI_TD_SET_ENDPT(UE_GET_ADDR(endpt)) | 2157 UHCI_TD_SET_DEVADDR(addr) | 2158 UHCI_TD_SET_PID(UHCI_TD_PID_OUT) | 2159 UHCI_TD_SET_DT(tog) | 2160 UHCI_TD_SET_MAXLEN(0) 2161 ); 2162 std->td.td_buffer = 0; 2163 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2164 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2165 2166 std->link.std = NULL; 2167 if (prev) { 2168 prev->link.std = std; 2169 prev->td.td_link = htole32( 2170 std->physaddr | UHCI_PTR_VF | UHCI_PTR_TD 2171 ); 2172 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->td), 2173 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2174 } 2175 tog ^= 1; 2176 } 2177 *lstd = std; 2178 *toggle = tog; 2179 } 2180 2181 void 2182 uhci_device_clear_toggle(struct usbd_pipe *pipe) 2183 { 2184 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2185 upipe->nexttoggle = 0; 2186 } 2187 2188 void 2189 uhci_noop(struct usbd_pipe *pipe) 2190 { 2191 } 2192 2193 int 2194 uhci_device_bulk_init(struct usbd_xfer *xfer) 2195 { 2196 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2197 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2198 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2199 int endpt = ed->bEndpointAddress; 2200 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2201 int len = xfer->ux_bufsize; 2202 int err = 0; 2203 2204 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2205 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, len, 2206 xfer->ux_flags, 0); 2207 2208 if (sc->sc_dying) 2209 return USBD_IOERROR; 2210 2211 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2212 2213 uxfer->ux_type = UX_BULK; 2214 err = uhci_alloc_std_chain(sc, xfer, len, isread, &uxfer->ux_stdstart); 2215 if (err) 2216 return err; 2217 2218 #ifdef UHCI_DEBUG 2219 if (uhcidebug >= 10) { 2220 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2221 uhci_dump_tds(uxfer->ux_stdstart); 2222 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2223 } 2224 #endif 2225 2226 return 0; 2227 } 2228 2229 Static void 2230 uhci_device_bulk_fini(struct usbd_xfer *xfer) 2231 { 2232 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2233 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2234 2235 KASSERT(ux->ux_type == UX_BULK); 2236 2237 if (ux->ux_nstd) { 2238 uhci_free_stds(sc, ux); 2239 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2240 } 2241 } 2242 2243 usbd_status 2244 uhci_device_bulk_transfer(struct usbd_xfer *xfer) 2245 { 2246 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2247 usbd_status err; 2248 2249 /* Insert last in queue. */ 2250 mutex_enter(&sc->sc_lock); 2251 err = usb_insert_transfer(xfer); 2252 mutex_exit(&sc->sc_lock); 2253 if (err) 2254 return err; 2255 2256 /* 2257 * Pipe isn't running (otherwise err would be USBD_INPROG), 2258 * so start it first. 2259 */ 2260 return uhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2261 } 2262 2263 usbd_status 2264 uhci_device_bulk_start(struct usbd_xfer *xfer) 2265 { 2266 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2267 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2268 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2269 uhci_soft_td_t *data, *dataend; 2270 uhci_soft_qh_t *sqh; 2271 const bool polling = sc->sc_bus.ub_usepolling; 2272 int len; 2273 int endpt; 2274 int isread; 2275 2276 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2277 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 2278 xfer->ux_length, xfer->ux_flags, 0); 2279 2280 if (sc->sc_dying) 2281 return USBD_IOERROR; 2282 2283 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2284 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2285 2286 len = xfer->ux_length; 2287 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2288 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2289 sqh = upipe->bulk.sqh; 2290 2291 /* Take lock here to protect nexttoggle */ 2292 if (!polling) 2293 mutex_enter(&sc->sc_lock); 2294 2295 uhci_reset_std_chain(sc, xfer, len, isread, &upipe->nexttoggle, 2296 &dataend); 2297 2298 data = ux->ux_stdstart; 2299 ux->ux_stdend = dataend; 2300 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2301 usb_syncmem(&dataend->dma, 2302 dataend->offs + offsetof(uhci_td_t, td_status), 2303 sizeof(dataend->td.td_status), 2304 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2305 2306 #ifdef UHCI_DEBUG 2307 if (uhcidebug >= 10) { 2308 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2309 DPRINTFN(10, "before transfer", 0, 0, 0, 0); 2310 uhci_dump_tds(data); 2311 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2312 } 2313 #endif 2314 2315 KASSERT(ux->ux_isdone); 2316 #ifdef DIAGNOSTIC 2317 ux->ux_isdone = false; 2318 #endif 2319 2320 sqh->elink = data; 2321 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2322 /* uhci_add_bulk() will do usb_syncmem(sqh) */ 2323 2324 uhci_add_bulk(sc, sqh); 2325 uhci_add_intr_list(sc, ux); 2326 usbd_xfer_schedule_timeout(xfer); 2327 xfer->ux_status = USBD_IN_PROGRESS; 2328 if (!polling) 2329 mutex_exit(&sc->sc_lock); 2330 2331 return USBD_IN_PROGRESS; 2332 } 2333 2334 /* Abort a device bulk request. */ 2335 void 2336 uhci_device_bulk_abort(struct usbd_xfer *xfer) 2337 { 2338 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2339 2340 KASSERT(mutex_owned(&sc->sc_lock)); 2341 2342 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2343 2344 usbd_xfer_abort(xfer); 2345 } 2346 2347 /* 2348 * To allow the hardware time to notice we simply wait. 2349 */ 2350 Static void 2351 uhci_abortx(struct usbd_xfer *xfer) 2352 { 2353 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2354 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2355 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2356 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2357 uhci_soft_td_t *std; 2358 2359 DPRINTFN(1,"xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2360 2361 KASSERT(mutex_owned(&sc->sc_lock)); 2362 ASSERT_SLEEPABLE(); 2363 2364 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2365 xfer->ux_status == USBD_TIMEOUT), 2366 "bad abort status: %d", xfer->ux_status); 2367 2368 /* 2369 * If we're dying, skip the hardware action and just notify the 2370 * software that we're done. 2371 */ 2372 if (sc->sc_dying) { 2373 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2374 xfer->ux_status, 0, 0); 2375 goto dying; 2376 } 2377 2378 /* 2379 * HC Step 1: Make interrupt routine and hardware ignore xfer. 2380 */ 2381 uhci_del_intr_list(sc, ux); 2382 2383 DPRINTF("stop ux=%#jx", (uintptr_t)ux, 0, 0, 0); 2384 for (std = ux->ux_stdstart; std != NULL; std = std->link.std) { 2385 usb_syncmem(&std->dma, 2386 std->offs + offsetof(uhci_td_t, td_status), 2387 sizeof(std->td.td_status), 2388 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2389 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 2390 usb_syncmem(&std->dma, 2391 std->offs + offsetof(uhci_td_t, td_status), 2392 sizeof(std->td.td_status), 2393 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2394 } 2395 2396 /* 2397 * HC Step 2: Wait until we know hardware has finished any possible 2398 * use of the xfer. 2399 */ 2400 /* Hardware finishes in 1ms */ 2401 usb_delay_ms_locked(upipe->pipe.up_dev->ud_bus, 2, &sc->sc_lock); 2402 2403 /* 2404 * HC Step 3: Notify completion to waiting xfers. 2405 */ 2406 dying: 2407 #ifdef DIAGNOSTIC 2408 ux->ux_isdone = true; 2409 #endif 2410 usb_transfer_complete(xfer); 2411 DPRINTFN(14, "end", 0, 0, 0, 0); 2412 2413 KASSERT(mutex_owned(&sc->sc_lock)); 2414 } 2415 2416 /* Close a device bulk pipe. */ 2417 void 2418 uhci_device_bulk_close(struct usbd_pipe *pipe) 2419 { 2420 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2421 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2422 2423 KASSERT(mutex_owned(&sc->sc_lock)); 2424 2425 uhci_free_sqh(sc, upipe->bulk.sqh); 2426 2427 pipe->up_endpoint->ue_toggle = upipe->nexttoggle; 2428 } 2429 2430 int 2431 uhci_device_ctrl_init(struct usbd_xfer *xfer) 2432 { 2433 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2434 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2435 usb_device_request_t *req = &xfer->ux_request; 2436 struct usbd_device *dev = upipe->pipe.up_dev; 2437 uhci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2438 uhci_soft_td_t *data = NULL; 2439 int len; 2440 usbd_status err; 2441 int isread; 2442 2443 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2444 DPRINTFN(3, "xfer=%#jx len=%jd, addr=%jd, endpt=%jd", 2445 (uintptr_t)xfer, xfer->ux_bufsize, dev->ud_addr, 2446 upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2447 2448 isread = req->bmRequestType & UT_READ; 2449 len = xfer->ux_bufsize; 2450 2451 uxfer->ux_type = UX_CTRL; 2452 /* Set up data transaction */ 2453 if (len != 0) { 2454 err = uhci_alloc_std_chain(sc, xfer, len, isread, &data); 2455 if (err) 2456 return err; 2457 } 2458 /* Set up interrupt info. */ 2459 uxfer->ux_setup = upipe->ctrl.setup; 2460 uxfer->ux_stat = upipe->ctrl.stat; 2461 uxfer->ux_data = data; 2462 2463 return 0; 2464 } 2465 2466 Static void 2467 uhci_device_ctrl_fini(struct usbd_xfer *xfer) 2468 { 2469 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2470 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2471 2472 KASSERT(ux->ux_type == UX_CTRL); 2473 2474 if (ux->ux_nstd) { 2475 uhci_free_stds(sc, ux); 2476 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2477 } 2478 } 2479 2480 usbd_status 2481 uhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2482 { 2483 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2484 usbd_status err; 2485 2486 /* Insert last in queue. */ 2487 mutex_enter(&sc->sc_lock); 2488 err = usb_insert_transfer(xfer); 2489 mutex_exit(&sc->sc_lock); 2490 if (err) 2491 return err; 2492 2493 /* 2494 * Pipe isn't running (otherwise err would be USBD_INPROG), 2495 * so start it first. 2496 */ 2497 return uhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2498 } 2499 2500 usbd_status 2501 uhci_device_ctrl_start(struct usbd_xfer *xfer) 2502 { 2503 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2504 struct uhci_xfer *uxfer = UHCI_XFER2UXFER(xfer); 2505 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2506 usb_device_request_t *req = &xfer->ux_request; 2507 struct usbd_device *dev = upipe->pipe.up_dev; 2508 int addr = dev->ud_addr; 2509 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2510 uhci_soft_td_t *setup, *stat, *next, *dataend; 2511 uhci_soft_qh_t *sqh; 2512 const bool polling = sc->sc_bus.ub_usepolling; 2513 int len; 2514 int isread; 2515 2516 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2517 2518 if (sc->sc_dying) 2519 return USBD_IOERROR; 2520 2521 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2522 2523 DPRINTFN(3, "type=0x%02jx, request=0x%02jx, " 2524 "wValue=0x%04jx, wIndex=0x%04jx", 2525 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2526 UGETW(req->wIndex)); 2527 DPRINTFN(3, "len=%jd, addr=%jd, endpt=%jd", 2528 UGETW(req->wLength), dev->ud_addr, endpt, 0); 2529 2530 isread = req->bmRequestType & UT_READ; 2531 len = UGETW(req->wLength); 2532 2533 setup = upipe->ctrl.setup; 2534 stat = upipe->ctrl.stat; 2535 sqh = upipe->ctrl.sqh; 2536 2537 memcpy(KERNADDR(&upipe->ctrl.reqdma, 0), req, sizeof(*req)); 2538 usb_syncmem(&upipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2539 2540 if (!polling) 2541 mutex_enter(&sc->sc_lock); 2542 2543 /* Set up data transaction */ 2544 if (len != 0) { 2545 upipe->nexttoggle = 1; 2546 next = uxfer->ux_data; 2547 uhci_reset_std_chain(sc, xfer, len, isread, 2548 &upipe->nexttoggle, &dataend); 2549 dataend->link.std = stat; 2550 dataend->td.td_link = htole32(stat->physaddr | UHCI_PTR_TD); 2551 usb_syncmem(&dataend->dma, 2552 dataend->offs + offsetof(uhci_td_t, td_link), 2553 sizeof(dataend->td.td_link), 2554 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2555 } else { 2556 next = stat; 2557 } 2558 2559 const uint32_t status = UHCI_TD_ZERO_ACTLEN( 2560 UHCI_TD_SET_ERRCNT(3) | 2561 UHCI_TD_ACTIVE | 2562 (dev->ud_speed == USB_SPEED_LOW ? UHCI_TD_LS : 0) 2563 ); 2564 setup->link.std = next; 2565 setup->td.td_link = htole32(next->physaddr | UHCI_PTR_TD); 2566 setup->td.td_status = htole32(status); 2567 setup->td.td_token = htole32(UHCI_TD_SETUP(sizeof(*req), endpt, addr)); 2568 setup->td.td_buffer = htole32(DMAADDR(&upipe->ctrl.reqdma, 0)); 2569 2570 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2572 2573 stat->link.std = NULL; 2574 stat->td.td_link = htole32(UHCI_PTR_T); 2575 stat->td.td_status = htole32(status | UHCI_TD_IOC); 2576 stat->td.td_token = 2577 htole32(isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 2578 UHCI_TD_IN (0, endpt, addr, 1)); 2579 stat->td.td_buffer = htole32(0); 2580 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2581 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2582 2583 #ifdef UHCI_DEBUG 2584 if (uhcidebug >= 10) { 2585 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2586 DPRINTF("before transfer", 0, 0, 0, 0); 2587 uhci_dump_tds(setup); 2588 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2589 } 2590 #endif 2591 2592 /* Set up interrupt info. */ 2593 uxfer->ux_setup = setup; 2594 uxfer->ux_stat = stat; 2595 KASSERT(uxfer->ux_isdone); 2596 #ifdef DIAGNOSTIC 2597 uxfer->ux_isdone = false; 2598 #endif 2599 2600 sqh->elink = setup; 2601 sqh->qh.qh_elink = htole32(setup->physaddr | UHCI_PTR_TD); 2602 /* uhci_add_?s_ctrl() will do usb_syncmem(sqh) */ 2603 2604 if (dev->ud_speed == USB_SPEED_LOW) 2605 uhci_add_ls_ctrl(sc, sqh); 2606 else 2607 uhci_add_hs_ctrl(sc, sqh); 2608 uhci_add_intr_list(sc, uxfer); 2609 #ifdef UHCI_DEBUG 2610 if (uhcidebug >= 12) { 2611 uhci_soft_td_t *std; 2612 uhci_soft_qh_t *xqh; 2613 uhci_soft_qh_t *sxqh; 2614 int maxqh = 0; 2615 uhci_physaddr_t link; 2616 DPRINTFN(12, "--- dump start ---", 0, 0, 0, 0); 2617 DPRINTFN(12, "follow from [0]", 0, 0, 0, 0); 2618 for (std = sc->sc_vframes[0].htd, link = 0; 2619 (link & UHCI_PTR_QH) == 0; 2620 std = std->link.std) { 2621 link = le32toh(std->td.td_link); 2622 uhci_dump_td(std); 2623 } 2624 sxqh = (uhci_soft_qh_t *)std; 2625 uhci_dump_qh(sxqh); 2626 for (xqh = sxqh; 2627 xqh != NULL; 2628 xqh = (maxqh++ == 5 || xqh->hlink == sxqh || 2629 xqh->hlink == xqh ? NULL : xqh->hlink)) { 2630 uhci_dump_qh(xqh); 2631 } 2632 DPRINTFN(12, "Enqueued QH:", 0, 0, 0, 0); 2633 uhci_dump_qh(sqh); 2634 uhci_dump_tds(sqh->elink); 2635 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2636 } 2637 #endif 2638 usbd_xfer_schedule_timeout(xfer); 2639 xfer->ux_status = USBD_IN_PROGRESS; 2640 if (!polling) 2641 mutex_exit(&sc->sc_lock); 2642 2643 return USBD_IN_PROGRESS; 2644 } 2645 2646 int 2647 uhci_device_intr_init(struct usbd_xfer *xfer) 2648 { 2649 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2650 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2651 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 2652 int endpt = ed->bEndpointAddress; 2653 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2654 int len = xfer->ux_bufsize; 2655 int err; 2656 2657 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2658 2659 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 2660 xfer->ux_length, xfer->ux_flags, 0); 2661 2662 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2663 KASSERT(len != 0); 2664 2665 ux->ux_type = UX_INTR; 2666 ux->ux_nstd = 0; 2667 err = uhci_alloc_std_chain(sc, xfer, len, isread, &ux->ux_stdstart); 2668 2669 return err; 2670 } 2671 2672 Static void 2673 uhci_device_intr_fini(struct usbd_xfer *xfer) 2674 { 2675 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2676 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2677 2678 KASSERT(ux->ux_type == UX_INTR); 2679 2680 if (ux->ux_nstd) { 2681 uhci_free_stds(sc, ux); 2682 kmem_free(ux->ux_stds, sizeof(uhci_soft_td_t *) * ux->ux_nstd); 2683 } 2684 } 2685 2686 usbd_status 2687 uhci_device_intr_transfer(struct usbd_xfer *xfer) 2688 { 2689 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2690 usbd_status err; 2691 2692 /* Insert last in queue. */ 2693 mutex_enter(&sc->sc_lock); 2694 err = usb_insert_transfer(xfer); 2695 mutex_exit(&sc->sc_lock); 2696 if (err) 2697 return err; 2698 2699 /* 2700 * Pipe isn't running (otherwise err would be USBD_INPROG), 2701 * so start it first. 2702 */ 2703 return uhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2704 } 2705 2706 usbd_status 2707 uhci_device_intr_start(struct usbd_xfer *xfer) 2708 { 2709 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2710 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2711 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2712 uhci_soft_td_t *data, *dataend; 2713 uhci_soft_qh_t *sqh; 2714 const bool polling = sc->sc_bus.ub_usepolling; 2715 int isread, endpt; 2716 int i; 2717 2718 if (sc->sc_dying) 2719 return USBD_IOERROR; 2720 2721 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2722 2723 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 2724 xfer->ux_length, xfer->ux_flags, 0); 2725 2726 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2727 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 2728 2729 endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 2730 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2731 2732 data = ux->ux_stdstart; 2733 2734 KASSERT(ux->ux_isdone); 2735 #ifdef DIAGNOSTIC 2736 ux->ux_isdone = false; 2737 #endif 2738 2739 /* Take lock to protect nexttoggle */ 2740 if (!polling) 2741 mutex_enter(&sc->sc_lock); 2742 uhci_reset_std_chain(sc, xfer, xfer->ux_length, isread, 2743 &upipe->nexttoggle, &dataend); 2744 2745 dataend->td.td_status |= htole32(UHCI_TD_IOC); 2746 usb_syncmem(&dataend->dma, 2747 dataend->offs + offsetof(uhci_td_t, td_status), 2748 sizeof(dataend->td.td_status), 2749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2750 ux->ux_stdend = dataend; 2751 2752 #ifdef UHCI_DEBUG 2753 if (uhcidebug >= 10) { 2754 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2755 uhci_dump_tds(data); 2756 uhci_dump_qh(upipe->intr.qhs[0]); 2757 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2758 } 2759 #endif 2760 2761 DPRINTFN(10, "qhs[0]=%#jx", (uintptr_t)upipe->intr.qhs[0], 0, 0, 0); 2762 for (i = 0; i < upipe->intr.npoll; i++) { 2763 sqh = upipe->intr.qhs[i]; 2764 sqh->elink = data; 2765 sqh->qh.qh_elink = htole32(data->physaddr | UHCI_PTR_TD); 2766 usb_syncmem(&sqh->dma, 2767 sqh->offs + offsetof(uhci_qh_t, qh_elink), 2768 sizeof(sqh->qh.qh_elink), 2769 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2770 } 2771 uhci_add_intr_list(sc, ux); 2772 xfer->ux_status = USBD_IN_PROGRESS; 2773 if (!polling) 2774 mutex_exit(&sc->sc_lock); 2775 2776 #ifdef UHCI_DEBUG 2777 if (uhcidebug >= 10) { 2778 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2779 uhci_dump_tds(data); 2780 uhci_dump_qh(upipe->intr.qhs[0]); 2781 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2782 } 2783 #endif 2784 2785 return USBD_IN_PROGRESS; 2786 } 2787 2788 /* Abort a device control request. */ 2789 void 2790 uhci_device_ctrl_abort(struct usbd_xfer *xfer) 2791 { 2792 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2793 2794 KASSERT(mutex_owned(&sc->sc_lock)); 2795 2796 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2797 usbd_xfer_abort(xfer); 2798 } 2799 2800 /* Close a device control pipe. */ 2801 void 2802 uhci_device_ctrl_close(struct usbd_pipe *pipe) 2803 { 2804 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2805 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2806 2807 uhci_free_sqh(sc, upipe->ctrl.sqh); 2808 uhci_free_std_locked(sc, upipe->ctrl.setup); 2809 uhci_free_std_locked(sc, upipe->ctrl.stat); 2810 2811 usb_freemem(&sc->sc_bus, &upipe->ctrl.reqdma); 2812 } 2813 2814 /* Abort a device interrupt request. */ 2815 void 2816 uhci_device_intr_abort(struct usbd_xfer *xfer) 2817 { 2818 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 2819 2820 KASSERT(mutex_owned(&sc->sc_lock)); 2821 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2822 2823 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2824 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2825 2826 usbd_xfer_abort(xfer); 2827 } 2828 2829 /* Close a device interrupt pipe. */ 2830 void 2831 uhci_device_intr_close(struct usbd_pipe *pipe) 2832 { 2833 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 2834 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 2835 int i, npoll; 2836 2837 KASSERT(mutex_owned(&sc->sc_lock)); 2838 2839 /* Unlink descriptors from controller data structures. */ 2840 npoll = upipe->intr.npoll; 2841 for (i = 0; i < npoll; i++) 2842 uhci_remove_intr(sc, upipe->intr.qhs[i]); 2843 2844 /* 2845 * We now have to wait for any activity on the physical 2846 * descriptors to stop. 2847 */ 2848 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 2849 2850 for (i = 0; i < npoll; i++) 2851 uhci_free_sqh(sc, upipe->intr.qhs[i]); 2852 kmem_free(upipe->intr.qhs, npoll * sizeof(uhci_soft_qh_t *)); 2853 } 2854 2855 int 2856 uhci_device_isoc_init(struct usbd_xfer *xfer) 2857 { 2858 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2859 2860 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2861 KASSERT(xfer->ux_nframes != 0); 2862 KASSERT(ux->ux_isdone); 2863 2864 ux->ux_type = UX_ISOC; 2865 return 0; 2866 } 2867 2868 Static void 2869 uhci_device_isoc_fini(struct usbd_xfer *xfer) 2870 { 2871 struct uhci_xfer *ux __diagused = UHCI_XFER2UXFER(xfer); 2872 2873 KASSERT(ux->ux_type == UX_ISOC); 2874 } 2875 2876 usbd_status 2877 uhci_device_isoc_transfer(struct usbd_xfer *xfer) 2878 { 2879 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2880 usbd_status err __diagused; 2881 2882 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 2883 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2884 2885 /* Put it on our queue, */ 2886 mutex_enter(&sc->sc_lock); 2887 err = usb_insert_transfer(xfer); 2888 mutex_exit(&sc->sc_lock); 2889 2890 KASSERT(err == USBD_NORMAL_COMPLETION); 2891 2892 /* insert into schedule, */ 2893 2894 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2895 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2896 struct isoc *isoc = &upipe->isoc; 2897 uhci_soft_td_t *std = NULL; 2898 uint32_t buf, len, status, offs; 2899 int i, next, nframes; 2900 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 2901 2902 DPRINTFN(5, "used=%jd next=%jd xfer=%#jx nframes=%jd", 2903 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 2904 2905 if (sc->sc_dying) 2906 return USBD_IOERROR; 2907 2908 if (xfer->ux_status == USBD_IN_PROGRESS) { 2909 /* This request has already been entered into the frame list */ 2910 printf("%s: xfer=%p in frame list\n", __func__, xfer); 2911 /* XXX */ 2912 } 2913 2914 #ifdef DIAGNOSTIC 2915 if (isoc->inuse >= UHCI_VFRAMELIST_COUNT) 2916 printf("%s: overflow!\n", __func__); 2917 #endif 2918 2919 KASSERT(xfer->ux_nframes != 0); 2920 2921 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2922 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2923 2924 mutex_enter(&sc->sc_lock); 2925 next = isoc->next; 2926 if (next == -1) { 2927 /* Not in use yet, schedule it a few frames ahead. */ 2928 next = (UREAD2(sc, UHCI_FRNUM) + 3) % UHCI_VFRAMELIST_COUNT; 2929 DPRINTFN(2, "start next=%jd", next, 0, 0, 0); 2930 } 2931 2932 xfer->ux_status = USBD_IN_PROGRESS; 2933 ux->ux_curframe = next; 2934 2935 buf = DMAADDR(&xfer->ux_dmabuf, 0); 2936 offs = 0; 2937 status = UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(0) | 2938 UHCI_TD_ACTIVE | 2939 UHCI_TD_IOS); 2940 nframes = xfer->ux_nframes; 2941 for (i = 0; i < nframes; i++) { 2942 std = isoc->stds[next]; 2943 if (++next >= UHCI_VFRAMELIST_COUNT) 2944 next = 0; 2945 len = xfer->ux_frlengths[i]; 2946 std->td.td_buffer = htole32(buf); 2947 usb_syncmem(&xfer->ux_dmabuf, offs, len, 2948 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2949 if (i == nframes - 1) 2950 status |= UHCI_TD_IOC; 2951 std->td.td_status = htole32(status); 2952 std->td.td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2953 std->td.td_token |= htole32(UHCI_TD_SET_MAXLEN(len)); 2954 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2956 #ifdef UHCI_DEBUG 2957 if (uhcidebug >= 5) { 2958 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2959 DPRINTF("TD %jd", i, 0, 0, 0); 2960 uhci_dump_td(std); 2961 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2962 } 2963 #endif 2964 buf += len; 2965 offs += len; 2966 } 2967 isoc->next = next; 2968 isoc->inuse += xfer->ux_nframes; 2969 2970 /* Set up interrupt info. */ 2971 ux->ux_stdstart = std; 2972 ux->ux_stdend = std; 2973 2974 KASSERT(ux->ux_isdone); 2975 #ifdef DIAGNOSTIC 2976 ux->ux_isdone = false; 2977 #endif 2978 uhci_add_intr_list(sc, ux); 2979 2980 mutex_exit(&sc->sc_lock); 2981 2982 return USBD_IN_PROGRESS; 2983 } 2984 2985 void 2986 uhci_device_isoc_abort(struct usbd_xfer *xfer) 2987 { 2988 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 2989 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 2990 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 2991 uhci_soft_td_t **stds = upipe->isoc.stds; 2992 uhci_soft_td_t *std; 2993 int i, n, nframes, maxlen, len; 2994 2995 KASSERT(mutex_owned(&sc->sc_lock)); 2996 2997 /* Transfer is already done. */ 2998 if (xfer->ux_status != USBD_NOT_STARTED && 2999 xfer->ux_status != USBD_IN_PROGRESS) { 3000 return; 3001 } 3002 3003 /* Give xfer the requested abort code. */ 3004 xfer->ux_status = USBD_CANCELLED; 3005 3006 /* make hardware ignore it, */ 3007 nframes = xfer->ux_nframes; 3008 n = ux->ux_curframe; 3009 maxlen = 0; 3010 for (i = 0; i < nframes; i++) { 3011 std = stds[n]; 3012 usb_syncmem(&std->dma, 3013 std->offs + offsetof(uhci_td_t, td_status), 3014 sizeof(std->td.td_status), 3015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3016 std->td.td_status &= htole32(~(UHCI_TD_ACTIVE | UHCI_TD_IOC)); 3017 usb_syncmem(&std->dma, 3018 std->offs + offsetof(uhci_td_t, td_status), 3019 sizeof(std->td.td_status), 3020 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3021 usb_syncmem(&std->dma, 3022 std->offs + offsetof(uhci_td_t, td_token), 3023 sizeof(std->td.td_token), 3024 BUS_DMASYNC_POSTWRITE); 3025 len = UHCI_TD_GET_MAXLEN(le32toh(std->td.td_token)); 3026 if (len > maxlen) 3027 maxlen = len; 3028 if (++n >= UHCI_VFRAMELIST_COUNT) 3029 n = 0; 3030 } 3031 3032 /* and wait until we are sure the hardware has finished. */ 3033 delay(maxlen); 3034 3035 #ifdef DIAGNOSTIC 3036 ux->ux_isdone = true; 3037 #endif 3038 /* Remove from interrupt list. */ 3039 uhci_del_intr_list(sc, ux); 3040 3041 /* Run callback. */ 3042 usb_transfer_complete(xfer); 3043 3044 KASSERT(mutex_owned(&sc->sc_lock)); 3045 } 3046 3047 void 3048 uhci_device_isoc_close(struct usbd_pipe *pipe) 3049 { 3050 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3051 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3052 uhci_soft_td_t *std, *vstd; 3053 struct isoc *isoc; 3054 int i; 3055 3056 KASSERT(mutex_owned(&sc->sc_lock)); 3057 3058 /* 3059 * Make sure all TDs are marked as inactive. 3060 * Wait for completion. 3061 * Unschedule. 3062 * Deallocate. 3063 */ 3064 isoc = &upipe->isoc; 3065 3066 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3067 std = isoc->stds[i]; 3068 usb_syncmem(&std->dma, 3069 std->offs + offsetof(uhci_td_t, td_status), 3070 sizeof(std->td.td_status), 3071 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3072 std->td.td_status &= htole32(~UHCI_TD_ACTIVE); 3073 usb_syncmem(&std->dma, 3074 std->offs + offsetof(uhci_td_t, td_status), 3075 sizeof(std->td.td_status), 3076 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3077 } 3078 /* wait for completion */ 3079 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3080 3081 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3082 std = isoc->stds[i]; 3083 for (vstd = sc->sc_vframes[i].htd; 3084 vstd != NULL && vstd->link.std != std; 3085 vstd = vstd->link.std) 3086 ; 3087 if (vstd == NULL) { 3088 /*panic*/ 3089 printf("%s: %p not found\n", __func__, std); 3090 mutex_exit(&sc->sc_lock); 3091 return; 3092 } 3093 vstd->link = std->link; 3094 usb_syncmem(&std->dma, 3095 std->offs + offsetof(uhci_td_t, td_link), 3096 sizeof(std->td.td_link), 3097 BUS_DMASYNC_POSTWRITE); 3098 vstd->td.td_link = std->td.td_link; 3099 usb_syncmem(&vstd->dma, 3100 vstd->offs + offsetof(uhci_td_t, td_link), 3101 sizeof(vstd->td.td_link), 3102 BUS_DMASYNC_PREWRITE); 3103 uhci_free_std_locked(sc, std); 3104 } 3105 3106 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3107 } 3108 3109 usbd_status 3110 uhci_setup_isoc(struct usbd_pipe *pipe) 3111 { 3112 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3113 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3114 int addr = upipe->pipe.up_dev->ud_addr; 3115 int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3116 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3117 uhci_soft_td_t *std, *vstd; 3118 uint32_t token; 3119 struct isoc *isoc; 3120 int i; 3121 3122 isoc = &upipe->isoc; 3123 3124 isoc->stds = kmem_alloc( 3125 UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *), KM_SLEEP); 3126 if (isoc->stds == NULL) 3127 return USBD_NOMEM; 3128 3129 token = rd ? UHCI_TD_IN (0, endpt, addr, 0) : 3130 UHCI_TD_OUT(0, endpt, addr, 0); 3131 3132 /* Allocate the TDs and mark as inactive; */ 3133 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3134 std = uhci_alloc_std(sc); 3135 if (std == 0) 3136 goto bad; 3137 std->td.td_status = htole32(UHCI_TD_IOS); /* iso, inactive */ 3138 std->td.td_token = htole32(token); 3139 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 3140 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3141 isoc->stds[i] = std; 3142 } 3143 3144 mutex_enter(&sc->sc_lock); 3145 3146 /* Insert TDs into schedule. */ 3147 for (i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 3148 std = isoc->stds[i]; 3149 vstd = sc->sc_vframes[i].htd; 3150 usb_syncmem(&vstd->dma, 3151 vstd->offs + offsetof(uhci_td_t, td_link), 3152 sizeof(vstd->td.td_link), 3153 BUS_DMASYNC_POSTWRITE); 3154 std->link = vstd->link; 3155 std->td.td_link = vstd->td.td_link; 3156 usb_syncmem(&std->dma, 3157 std->offs + offsetof(uhci_td_t, td_link), 3158 sizeof(std->td.td_link), 3159 BUS_DMASYNC_PREWRITE); 3160 vstd->link.std = std; 3161 vstd->td.td_link = htole32(std->physaddr | UHCI_PTR_TD); 3162 usb_syncmem(&vstd->dma, 3163 vstd->offs + offsetof(uhci_td_t, td_link), 3164 sizeof(vstd->td.td_link), 3165 BUS_DMASYNC_PREWRITE); 3166 } 3167 mutex_exit(&sc->sc_lock); 3168 3169 isoc->next = -1; 3170 isoc->inuse = 0; 3171 3172 return USBD_NORMAL_COMPLETION; 3173 3174 bad: 3175 while (--i >= 0) 3176 uhci_free_std(sc, isoc->stds[i]); 3177 kmem_free(isoc->stds, UHCI_VFRAMELIST_COUNT * sizeof(uhci_soft_td_t *)); 3178 return USBD_NOMEM; 3179 } 3180 3181 void 3182 uhci_device_isoc_done(struct usbd_xfer *xfer) 3183 { 3184 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3185 struct uhci_xfer *ux = UHCI_XFER2UXFER(xfer); 3186 int i, offs; 3187 int rd = UE_GET_DIR(upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN; 3188 3189 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3190 DPRINTFN(4, "length=%jd, ux_state=0x%08jx", 3191 xfer->ux_actlen, xfer->ux_state, 0, 0); 3192 3193 #ifdef DIAGNOSTIC 3194 if (ux->ux_stdend == NULL) { 3195 printf("%s: xfer=%p stdend==NULL\n", __func__, xfer); 3196 #ifdef UHCI_DEBUG 3197 DPRINTF("--- dump start ---", 0, 0, 0, 0); 3198 uhci_dump_ii(ux); 3199 DPRINTF("--- dump end ---", 0, 0, 0, 0); 3200 #endif 3201 return; 3202 } 3203 #endif 3204 3205 /* Turn off the interrupt since it is active even if the TD is not. */ 3206 usb_syncmem(&ux->ux_stdend->dma, 3207 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3208 sizeof(ux->ux_stdend->td.td_status), 3209 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3210 ux->ux_stdend->td.td_status &= htole32(~UHCI_TD_IOC); 3211 usb_syncmem(&ux->ux_stdend->dma, 3212 ux->ux_stdend->offs + offsetof(uhci_td_t, td_status), 3213 sizeof(ux->ux_stdend->td.td_status), 3214 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3215 3216 offs = 0; 3217 for (i = 0; i < xfer->ux_nframes; i++) { 3218 usb_syncmem(&xfer->ux_dmabuf, offs, xfer->ux_frlengths[i], 3219 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3220 offs += xfer->ux_frlengths[i]; 3221 } 3222 } 3223 3224 void 3225 uhci_device_intr_done(struct usbd_xfer *xfer) 3226 { 3227 uhci_softc_t *sc __diagused = UHCI_XFER2SC(xfer); 3228 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3229 uhci_soft_qh_t *sqh; 3230 int i, npoll; 3231 3232 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3233 DPRINTFN(5, "length=%jd", xfer->ux_actlen, 0, 0, 0); 3234 3235 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3236 3237 npoll = upipe->intr.npoll; 3238 for (i = 0; i < npoll; i++) { 3239 sqh = upipe->intr.qhs[i]; 3240 sqh->elink = NULL; 3241 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3242 usb_syncmem(&sqh->dma, 3243 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3244 sizeof(sqh->qh.qh_elink), 3245 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3246 } 3247 const int endpt = upipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3248 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3249 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3250 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3251 } 3252 3253 /* Deallocate request data structures */ 3254 void 3255 uhci_device_ctrl_done(struct usbd_xfer *xfer) 3256 { 3257 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3258 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3259 int len = UGETW(xfer->ux_request.wLength); 3260 int isread = (xfer->ux_request.bmRequestType & UT_READ); 3261 3262 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3263 3264 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3265 3266 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3267 3268 /* XXXNH move to uhci_idone??? */ 3269 if (upipe->pipe.up_dev->ud_speed == USB_SPEED_LOW) 3270 uhci_remove_ls_ctrl(sc, upipe->ctrl.sqh); 3271 else 3272 uhci_remove_hs_ctrl(sc, upipe->ctrl.sqh); 3273 3274 if (len) { 3275 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3276 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3277 } 3278 usb_syncmem(&upipe->ctrl.reqdma, 0, 3279 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 3280 3281 DPRINTF("length=%jd", xfer->ux_actlen, 0, 0, 0); 3282 } 3283 3284 /* Deallocate request data structures */ 3285 void 3286 uhci_device_bulk_done(struct usbd_xfer *xfer) 3287 { 3288 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3289 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(xfer->ux_pipe); 3290 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3291 int endpt = ed->bEndpointAddress; 3292 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3293 3294 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3295 DPRINTFN(5, "xfer=%#jx sc=%#jx upipe=%#jx", (uintptr_t)xfer, 3296 (uintptr_t)sc, (uintptr_t)upipe, 0); 3297 3298 KASSERT(mutex_owned(&sc->sc_lock)); 3299 3300 uhci_remove_bulk(sc, upipe->bulk.sqh); 3301 3302 if (xfer->ux_length) { 3303 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3304 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3305 } 3306 3307 DPRINTFN(5, "length=%jd", xfer->ux_actlen, 0, 0, 0); 3308 } 3309 3310 /* Add interrupt QH, called with vflock. */ 3311 void 3312 uhci_add_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3313 { 3314 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3315 uhci_soft_qh_t *eqh; 3316 3317 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3318 DPRINTFN(4, "n=%jd sqh=%#jx", sqh->pos, (uintptr_t)sqh, 0, 0); 3319 3320 eqh = vf->eqh; 3321 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3322 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_POSTWRITE); 3323 sqh->hlink = eqh->hlink; 3324 sqh->qh.qh_hlink = eqh->qh.qh_hlink; 3325 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3326 sizeof(sqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 3327 eqh->hlink = sqh; 3328 eqh->qh.qh_hlink = htole32(sqh->physaddr | UHCI_PTR_QH); 3329 usb_syncmem(&eqh->dma, eqh->offs + offsetof(uhci_qh_t, qh_hlink), 3330 sizeof(eqh->qh.qh_hlink), BUS_DMASYNC_PREWRITE); 3331 vf->eqh = sqh; 3332 vf->bandwidth++; 3333 } 3334 3335 /* Remove interrupt QH. */ 3336 void 3337 uhci_remove_intr(uhci_softc_t *sc, uhci_soft_qh_t *sqh) 3338 { 3339 struct uhci_vframe *vf = &sc->sc_vframes[sqh->pos]; 3340 uhci_soft_qh_t *pqh; 3341 3342 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3343 DPRINTFN(4, "n=%jd sqh=%#jx", sqh->pos, (uintptr_t)sqh, 0, 0); 3344 3345 /* See comment in uhci_remove_ctrl() */ 3346 3347 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_elink), 3348 sizeof(sqh->qh.qh_elink), 3349 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3350 if (!(sqh->qh.qh_elink & htole32(UHCI_PTR_T))) { 3351 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3352 usb_syncmem(&sqh->dma, 3353 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3354 sizeof(sqh->qh.qh_elink), 3355 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3356 delay(UHCI_QH_REMOVE_DELAY); 3357 } 3358 3359 pqh = uhci_find_prev_qh(vf->hqh, sqh); 3360 usb_syncmem(&sqh->dma, sqh->offs + offsetof(uhci_qh_t, qh_hlink), 3361 sizeof(sqh->qh.qh_hlink), 3362 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3363 pqh->hlink = sqh->hlink; 3364 pqh->qh.qh_hlink = sqh->qh.qh_hlink; 3365 usb_syncmem(&pqh->dma, pqh->offs + offsetof(uhci_qh_t, qh_hlink), 3366 sizeof(pqh->qh.qh_hlink), 3367 BUS_DMASYNC_PREWRITE); 3368 delay(UHCI_QH_REMOVE_DELAY); 3369 if (vf->eqh == sqh) 3370 vf->eqh = pqh; 3371 vf->bandwidth--; 3372 } 3373 3374 usbd_status 3375 uhci_device_setintr(uhci_softc_t *sc, struct uhci_pipe *upipe, int ival) 3376 { 3377 uhci_soft_qh_t *sqh; 3378 int i, npoll; 3379 u_int bestbw, bw, bestoffs, offs; 3380 3381 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3382 DPRINTFN(2, "pipe=%#jx", (uintptr_t)upipe, 0, 0, 0); 3383 if (ival == 0) { 3384 printf("%s: 0 interval\n", __func__); 3385 return USBD_INVAL; 3386 } 3387 3388 if (ival > UHCI_VFRAMELIST_COUNT) 3389 ival = UHCI_VFRAMELIST_COUNT; 3390 npoll = howmany(UHCI_VFRAMELIST_COUNT, ival); 3391 DPRINTF("ival=%jd npoll=%jd", ival, npoll, 0, 0); 3392 3393 upipe->intr.npoll = npoll; 3394 upipe->intr.qhs = 3395 kmem_alloc(npoll * sizeof(uhci_soft_qh_t *), KM_SLEEP); 3396 3397 /* 3398 * Figure out which offset in the schedule that has most 3399 * bandwidth left over. 3400 */ 3401 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 3402 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 3403 for (bw = i = 0; i < npoll; i++) 3404 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 3405 if (bw < bestbw) { 3406 bestbw = bw; 3407 bestoffs = offs; 3408 } 3409 } 3410 DPRINTF("bw=%jd offs=%jd", bestbw, bestoffs, 0, 0); 3411 for (i = 0; i < npoll; i++) { 3412 upipe->intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 3413 sqh->elink = NULL; 3414 sqh->qh.qh_elink = htole32(UHCI_PTR_T); 3415 usb_syncmem(&sqh->dma, 3416 sqh->offs + offsetof(uhci_qh_t, qh_elink), 3417 sizeof(sqh->qh.qh_elink), 3418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3419 sqh->pos = MOD(i * ival + bestoffs); 3420 } 3421 #undef MOD 3422 3423 mutex_enter(&sc->sc_lock); 3424 /* Enter QHs into the controller data structures. */ 3425 for (i = 0; i < npoll; i++) 3426 uhci_add_intr(sc, upipe->intr.qhs[i]); 3427 mutex_exit(&sc->sc_lock); 3428 3429 DPRINTFN(5, "returns %#jx", (uintptr_t)upipe, 0, 0, 0); 3430 3431 return USBD_NORMAL_COMPLETION; 3432 } 3433 3434 /* Open a new pipe. */ 3435 usbd_status 3436 uhci_open(struct usbd_pipe *pipe) 3437 { 3438 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3439 struct usbd_bus *bus = pipe->up_dev->ud_bus; 3440 struct uhci_pipe *upipe = UHCI_PIPE2UPIPE(pipe); 3441 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 3442 usbd_status err = USBD_NOMEM; 3443 int ival; 3444 3445 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3446 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", 3447 (uintptr_t)pipe, pipe->up_dev->ud_addr, ed->bEndpointAddress, 3448 bus->ub_rhaddr); 3449 3450 if (sc->sc_dying) 3451 return USBD_IOERROR; 3452 3453 upipe->aborting = 0; 3454 /* toggle state needed for bulk endpoints */ 3455 upipe->nexttoggle = pipe->up_endpoint->ue_toggle; 3456 3457 if (pipe->up_dev->ud_addr == bus->ub_rhaddr) { 3458 switch (ed->bEndpointAddress) { 3459 case USB_CONTROL_ENDPOINT: 3460 pipe->up_methods = &roothub_ctrl_methods; 3461 break; 3462 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 3463 pipe->up_methods = &uhci_root_intr_methods; 3464 break; 3465 default: 3466 return USBD_INVAL; 3467 } 3468 } else { 3469 switch (ed->bmAttributes & UE_XFERTYPE) { 3470 case UE_CONTROL: 3471 pipe->up_methods = &uhci_device_ctrl_methods; 3472 upipe->ctrl.sqh = uhci_alloc_sqh(sc); 3473 if (upipe->ctrl.sqh == NULL) 3474 goto bad; 3475 upipe->ctrl.setup = uhci_alloc_std(sc); 3476 if (upipe->ctrl.setup == NULL) { 3477 uhci_free_sqh(sc, upipe->ctrl.sqh); 3478 goto bad; 3479 } 3480 upipe->ctrl.stat = uhci_alloc_std(sc); 3481 if (upipe->ctrl.stat == NULL) { 3482 uhci_free_sqh(sc, upipe->ctrl.sqh); 3483 uhci_free_std(sc, upipe->ctrl.setup); 3484 goto bad; 3485 } 3486 err = usb_allocmem(&sc->sc_bus, 3487 sizeof(usb_device_request_t), 0, 3488 USBMALLOC_COHERENT, &upipe->ctrl.reqdma); 3489 if (err) { 3490 uhci_free_sqh(sc, upipe->ctrl.sqh); 3491 uhci_free_std(sc, upipe->ctrl.setup); 3492 uhci_free_std(sc, upipe->ctrl.stat); 3493 goto bad; 3494 } 3495 break; 3496 case UE_INTERRUPT: 3497 pipe->up_methods = &uhci_device_intr_methods; 3498 ival = pipe->up_interval; 3499 if (ival == USBD_DEFAULT_INTERVAL) 3500 ival = ed->bInterval; 3501 return uhci_device_setintr(sc, upipe, ival); 3502 case UE_ISOCHRONOUS: 3503 pipe->up_serialise = false; 3504 pipe->up_methods = &uhci_device_isoc_methods; 3505 return uhci_setup_isoc(pipe); 3506 case UE_BULK: 3507 pipe->up_methods = &uhci_device_bulk_methods; 3508 upipe->bulk.sqh = uhci_alloc_sqh(sc); 3509 if (upipe->bulk.sqh == NULL) 3510 goto bad; 3511 break; 3512 } 3513 } 3514 return USBD_NORMAL_COMPLETION; 3515 3516 bad: 3517 return USBD_NOMEM; 3518 } 3519 3520 /* 3521 * Data structures and routines to emulate the root hub. 3522 */ 3523 /* 3524 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 3525 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 3526 * should not be used by the USB subsystem. As we cannot issue a 3527 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 3528 * will be enabled as part of the reset. 3529 * 3530 * On the VT83C572, the port cannot be successfully enabled until the 3531 * outstanding "port enable change" and "connection status change" 3532 * events have been reset. 3533 */ 3534 Static usbd_status 3535 uhci_portreset(uhci_softc_t *sc, int index) 3536 { 3537 int lim, port, x; 3538 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3539 3540 if (index == 1) 3541 port = UHCI_PORTSC1; 3542 else if (index == 2) 3543 port = UHCI_PORTSC2; 3544 else 3545 return USBD_IOERROR; 3546 3547 x = URWMASK(UREAD2(sc, port)); 3548 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 3549 3550 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3551 3552 DPRINTF("uhci port %jd reset, status0 = 0x%04jx", index, 3553 UREAD2(sc, port), 0, 0); 3554 3555 x = URWMASK(UREAD2(sc, port)); 3556 UWRITE2(sc, port, x & ~(UHCI_PORTSC_PR | UHCI_PORTSC_SUSP)); 3557 3558 delay(100); 3559 3560 DPRINTF("uhci port %jd reset, status1 = 0x%04jx", index, 3561 UREAD2(sc, port), 0, 0); 3562 3563 x = URWMASK(UREAD2(sc, port)); 3564 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3565 3566 for (lim = 10; --lim > 0;) { 3567 usb_delay_ms(&sc->sc_bus, USB_PORT_RESET_DELAY); 3568 3569 x = UREAD2(sc, port); 3570 DPRINTF("uhci port %jd iteration %ju, status = 0x%04jx", index, 3571 lim, x, 0); 3572 3573 if (!(x & UHCI_PORTSC_CCS)) { 3574 /* 3575 * No device is connected (or was disconnected 3576 * during reset). Consider the port reset. 3577 * The delay must be long enough to ensure on 3578 * the initial iteration that the device 3579 * connection will have been registered. 50ms 3580 * appears to be sufficient, but 20ms is not. 3581 */ 3582 DPRINTFN(3, "uhci port %jd loop %ju, device detached", 3583 index, lim, 0, 0); 3584 break; 3585 } 3586 3587 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 3588 /* 3589 * Port enabled changed and/or connection 3590 * status changed were set. Reset either or 3591 * both raised flags (by writing a 1 to that 3592 * bit), and wait again for state to settle. 3593 */ 3594 UWRITE2(sc, port, URWMASK(x) | 3595 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 3596 continue; 3597 } 3598 3599 if (x & UHCI_PORTSC_PE) 3600 /* Port is enabled */ 3601 break; 3602 3603 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 3604 } 3605 3606 DPRINTFN(3, "uhci port %jd reset, status2 = 0x%04jx", index, 3607 UREAD2(sc, port), 0, 0); 3608 3609 if (lim <= 0) { 3610 DPRINTF("uhci port %jd reset timed out", index, 3611 0, 0, 0); 3612 return USBD_TIMEOUT; 3613 } 3614 3615 sc->sc_isreset = 1; 3616 return USBD_NORMAL_COMPLETION; 3617 } 3618 3619 Static int 3620 uhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3621 void *buf, int buflen) 3622 { 3623 uhci_softc_t *sc = UHCI_BUS2SC(bus); 3624 int port, x; 3625 int status, change, totlen = 0; 3626 uint16_t len, value, index; 3627 usb_port_status_t ps; 3628 usbd_status err; 3629 3630 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3631 3632 if (sc->sc_dying) 3633 return -1; 3634 3635 DPRINTF("type=0x%02jx request=%02jx", req->bmRequestType, 3636 req->bRequest, 0, 0); 3637 3638 len = UGETW(req->wLength); 3639 value = UGETW(req->wValue); 3640 index = UGETW(req->wIndex); 3641 3642 #define C(x,y) ((x) | ((y) << 8)) 3643 switch (C(req->bRequest, req->bmRequestType)) { 3644 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3645 DPRINTF("wValue=0x%04jx", value, 0, 0, 0); 3646 if (len == 0) 3647 break; 3648 switch (value) { 3649 #define sd ((usb_string_descriptor_t *)buf) 3650 case C(2, UDESC_STRING): 3651 /* Product */ 3652 totlen = usb_makestrdesc(sd, len, "UHCI root hub"); 3653 break; 3654 #undef sd 3655 default: 3656 /* default from usbroothub */ 3657 return buflen; 3658 } 3659 break; 3660 3661 /* Hub requests */ 3662 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3663 break; 3664 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3665 DPRINTF("UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, 3666 value, 0, 0); 3667 if (index == 1) 3668 port = UHCI_PORTSC1; 3669 else if (index == 2) 3670 port = UHCI_PORTSC2; 3671 else { 3672 return -1; 3673 } 3674 switch(value) { 3675 case UHF_PORT_ENABLE: 3676 x = URWMASK(UREAD2(sc, port)); 3677 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 3678 break; 3679 case UHF_PORT_SUSPEND: 3680 x = URWMASK(UREAD2(sc, port)); 3681 if (!(x & UHCI_PORTSC_SUSP)) /* not suspended */ 3682 break; 3683 UWRITE2(sc, port, x | UHCI_PORTSC_RD); 3684 /* see USB2 spec ch. 7.1.7.7 */ 3685 usb_delay_ms(&sc->sc_bus, 20); 3686 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 3687 /* 10ms resume delay must be provided by caller */ 3688 break; 3689 case UHF_PORT_RESET: 3690 x = URWMASK(UREAD2(sc, port)); 3691 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 3692 break; 3693 case UHF_C_PORT_CONNECTION: 3694 x = URWMASK(UREAD2(sc, port)); 3695 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 3696 break; 3697 case UHF_C_PORT_ENABLE: 3698 x = URWMASK(UREAD2(sc, port)); 3699 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 3700 break; 3701 case UHF_C_PORT_OVER_CURRENT: 3702 x = URWMASK(UREAD2(sc, port)); 3703 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 3704 break; 3705 case UHF_C_PORT_RESET: 3706 sc->sc_isreset = 0; 3707 break; 3708 case UHF_PORT_CONNECTION: 3709 case UHF_PORT_OVER_CURRENT: 3710 case UHF_PORT_POWER: 3711 case UHF_PORT_LOW_SPEED: 3712 case UHF_C_PORT_SUSPEND: 3713 default: 3714 return -1; 3715 } 3716 break; 3717 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 3718 if (index == 1) 3719 port = UHCI_PORTSC1; 3720 else if (index == 2) 3721 port = UHCI_PORTSC2; 3722 else { 3723 return -1; 3724 } 3725 if (len > 0) { 3726 *(uint8_t *)buf = 3727 UHCI_PORTSC_GET_LS(UREAD2(sc, port)); 3728 totlen = 1; 3729 } 3730 break; 3731 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3732 if (len == 0) 3733 break; 3734 if ((value & 0xff) != 0) { 3735 return -1; 3736 } 3737 usb_hub_descriptor_t hubd; 3738 3739 totlen = uimin(buflen, sizeof(hubd)); 3740 memcpy(&hubd, buf, totlen); 3741 hubd.bNbrPorts = 2; 3742 memcpy(buf, &hubd, totlen); 3743 break; 3744 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3745 if (len != 4) { 3746 return -1; 3747 } 3748 memset(buf, 0, len); 3749 totlen = len; 3750 break; 3751 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3752 if (index == 1) 3753 port = UHCI_PORTSC1; 3754 else if (index == 2) 3755 port = UHCI_PORTSC2; 3756 else { 3757 return -1; 3758 } 3759 if (len != 4) { 3760 return -1; 3761 } 3762 x = UREAD2(sc, port); 3763 status = change = 0; 3764 if (x & UHCI_PORTSC_CCS) 3765 status |= UPS_CURRENT_CONNECT_STATUS; 3766 if (x & UHCI_PORTSC_CSC) 3767 change |= UPS_C_CONNECT_STATUS; 3768 if (x & UHCI_PORTSC_PE) 3769 status |= UPS_PORT_ENABLED; 3770 if (x & UHCI_PORTSC_POEDC) 3771 change |= UPS_C_PORT_ENABLED; 3772 if (x & UHCI_PORTSC_OCI) 3773 status |= UPS_OVERCURRENT_INDICATOR; 3774 if (x & UHCI_PORTSC_OCIC) 3775 change |= UPS_C_OVERCURRENT_INDICATOR; 3776 if (x & UHCI_PORTSC_SUSP) 3777 status |= UPS_SUSPEND; 3778 if (x & UHCI_PORTSC_LSDA) 3779 status |= UPS_LOW_SPEED; 3780 status |= UPS_PORT_POWER; 3781 if (sc->sc_isreset) 3782 change |= UPS_C_PORT_RESET; 3783 USETW(ps.wPortStatus, status); 3784 USETW(ps.wPortChange, change); 3785 totlen = uimin(len, sizeof(ps)); 3786 memcpy(buf, &ps, totlen); 3787 break; 3788 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3789 return -1; 3790 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3791 break; 3792 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3793 if (index == 1) 3794 port = UHCI_PORTSC1; 3795 else if (index == 2) 3796 port = UHCI_PORTSC2; 3797 else { 3798 return -1; 3799 } 3800 switch(value) { 3801 case UHF_PORT_ENABLE: 3802 x = URWMASK(UREAD2(sc, port)); 3803 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 3804 break; 3805 case UHF_PORT_SUSPEND: 3806 x = URWMASK(UREAD2(sc, port)); 3807 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 3808 break; 3809 case UHF_PORT_RESET: 3810 err = uhci_portreset(sc, index); 3811 if (err != USBD_NORMAL_COMPLETION) 3812 return -1; 3813 return 0; 3814 case UHF_PORT_POWER: 3815 /* Pretend we turned on power */ 3816 return 0; 3817 case UHF_C_PORT_CONNECTION: 3818 case UHF_C_PORT_ENABLE: 3819 case UHF_C_PORT_OVER_CURRENT: 3820 case UHF_PORT_CONNECTION: 3821 case UHF_PORT_OVER_CURRENT: 3822 case UHF_PORT_LOW_SPEED: 3823 case UHF_C_PORT_SUSPEND: 3824 case UHF_C_PORT_RESET: 3825 default: 3826 return -1; 3827 } 3828 break; 3829 default: 3830 /* default from usbroothub */ 3831 DPRINTF("returning %jd (usbroothub default)", 3832 buflen, 0, 0, 0); 3833 return buflen; 3834 } 3835 3836 DPRINTF("returning %jd", totlen, 0, 0, 0); 3837 3838 return totlen; 3839 } 3840 3841 /* Abort a root interrupt request. */ 3842 void 3843 uhci_root_intr_abort(struct usbd_xfer *xfer) 3844 { 3845 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3846 3847 KASSERT(mutex_owned(&sc->sc_lock)); 3848 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3849 3850 /* 3851 * Try to stop the callout before it starts. If we got in too 3852 * late, too bad; but if the callout had yet to run and time 3853 * out the xfer, cancel it ourselves. 3854 */ 3855 callout_stop(&sc->sc_poll_handle); 3856 if (sc->sc_intr_xfer == NULL) 3857 return; 3858 3859 KASSERT(sc->sc_intr_xfer == xfer); 3860 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 3861 xfer->ux_status = USBD_CANCELLED; 3862 #ifdef DIAGNOSTIC 3863 UHCI_XFER2UXFER(xfer)->ux_isdone = true; 3864 #endif 3865 usb_transfer_complete(xfer); 3866 } 3867 3868 usbd_status 3869 uhci_root_intr_transfer(struct usbd_xfer *xfer) 3870 { 3871 uhci_softc_t *sc = UHCI_XFER2SC(xfer); 3872 usbd_status err; 3873 3874 /* Insert last in queue. */ 3875 mutex_enter(&sc->sc_lock); 3876 err = usb_insert_transfer(xfer); 3877 mutex_exit(&sc->sc_lock); 3878 if (err) 3879 return err; 3880 3881 /* 3882 * Pipe isn't running (otherwise err would be USBD_INPROG), 3883 * start first 3884 */ 3885 return uhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3886 } 3887 3888 /* Start a transfer on the root interrupt pipe */ 3889 usbd_status 3890 uhci_root_intr_start(struct usbd_xfer *xfer) 3891 { 3892 struct usbd_pipe *pipe = xfer->ux_pipe; 3893 uhci_softc_t *sc = UHCI_PIPE2SC(pipe); 3894 unsigned int ival; 3895 const bool polling = sc->sc_bus.ub_usepolling; 3896 3897 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3898 DPRINTF("xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, xfer->ux_length, 3899 xfer->ux_flags, 0); 3900 3901 if (sc->sc_dying) 3902 return USBD_IOERROR; 3903 3904 if (!polling) 3905 mutex_enter(&sc->sc_lock); 3906 3907 KASSERT(sc->sc_intr_xfer == NULL); 3908 3909 /* XXX temporary variable needed to avoid gcc3 warning */ 3910 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 3911 sc->sc_ival = mstohz(ival); 3912 callout_schedule(&sc->sc_poll_handle, sc->sc_ival); 3913 sc->sc_intr_xfer = xfer; 3914 xfer->ux_status = USBD_IN_PROGRESS; 3915 3916 if (!polling) 3917 mutex_exit(&sc->sc_lock); 3918 3919 return USBD_IN_PROGRESS; 3920 } 3921 3922 /* Close the root interrupt pipe. */ 3923 void 3924 uhci_root_intr_close(struct usbd_pipe *pipe) 3925 { 3926 uhci_softc_t *sc __diagused = UHCI_PIPE2SC(pipe); 3927 UHCIHIST_FUNC(); UHCIHIST_CALLED(); 3928 3929 KASSERT(mutex_owned(&sc->sc_lock)); 3930 3931 /* 3932 * The caller must arrange to have aborted the pipe already, so 3933 * there can be no intr xfer in progress. The callout may 3934 * still be pending from a prior intr xfer -- if it has already 3935 * fired, it will see there is nothing to do, and do nothing. 3936 */ 3937 KASSERT(sc->sc_intr_xfer == NULL); 3938 KASSERT(!callout_pending(&sc->sc_poll_handle)); 3939 } 3940
Indexes created Tue Sep 30 20:09:53 GMT 2025