uhci.c revision 1.5
1 /* $NetBSD: uhci.c,v 1.5 1998/07/23 09:18:37 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Author: Lennart Augustsson <augustss (at) carlstedt.se> 8 * Carlstedt Research & Technology 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Universal Host Controller driver. 41 * Handles PIIX3 and PIIX4. 42 * 43 * Data sheets: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 44 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 45 * UHCI spec: http://www.intel.com/design/usb/uhci11d.pdf 46 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 58 #include <dev/usb/usb.h> 59 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 63 #include <dev/usb/usb_quirks.h> 64 65 #include <machine/bus.h> 66 67 #include <dev/usb/uhcireg.h> 68 #include <dev/usb/uhcivar.h> 69 70 #define MS_TO_TICKS(ms) ((ms) * hz / 1000) 71 72 struct uhci_pipe { 73 struct usbd_pipe pipe; 74 uhci_intr_info_t *iinfo; 75 int newtoggle; 76 /* Info needed for different pipe kinds. */ 77 union { 78 /* Control pipe */ 79 struct { 80 uhci_soft_qh_t *sqh; 81 uhci_dma_t reqdma; 82 uhci_dma_t datadma; 83 uhci_soft_td_t *setup, *stat, *xferend; 84 u_int length; 85 } ctl; 86 /* Interrupt pipe */ 87 struct { 88 uhci_dma_t datadma; 89 int npoll; 90 uhci_soft_qh_t **qhs; 91 } intr; 92 /* Bulk pipe */ 93 struct { 94 uhci_soft_qh_t *sqh; 95 uhci_dma_t datadma; 96 u_int length; 97 int isread; 98 } bulk; 99 } u; 100 }; 101 102 /* 103 * The uhci_intr_info free list can be global since they contain 104 * no dma specific data. The other free lists do. 105 */ 106 int uhci_global_init_done = 0; 107 LIST_HEAD(, uhci_intr_info) uhci_ii_free; 108 109 void uhci_busreset __P((uhci_softc_t *)); 110 usbd_status uhci_allocmem __P((uhci_softc_t *,size_t,size_t,uhci_dma_t *)); 111 void uhci_freemem __P((uhci_softc_t *, uhci_dma_t *)); 112 void uhci_run __P((uhci_softc_t *, int run)); 113 uhci_soft_td_t *uhci_alloc_std __P((uhci_softc_t *)); 114 void uhci_free_std __P((uhci_softc_t *, uhci_soft_td_t *)); 115 uhci_soft_qh_t *uhci_alloc_sqh __P((uhci_softc_t *)); 116 void uhci_free_sqh __P((uhci_softc_t *, uhci_soft_qh_t *)); 117 uhci_intr_info_t *uhci_alloc_intr_info __P((uhci_softc_t *)); 118 void uhci_free_intr_info __P((uhci_intr_info_t *ii)); 119 void uhci_enter_ctl_q __P((uhci_softc_t *, uhci_soft_qh_t *, 120 uhci_intr_info_t *)); 121 void uhci_exit_ctl_q __P((uhci_softc_t *, uhci_soft_qh_t *)); 122 123 void uhci_free_std_chain __P((uhci_softc_t *, 124 uhci_soft_td_t *, uhci_soft_td_t *)); 125 usbd_status uhci_alloc_std_chain __P((struct uhci_pipe *, uhci_softc_t *, 126 int, int, uhci_dma_t *, 127 uhci_soft_td_t **, 128 uhci_soft_td_t **)); 129 void uhci_timo __P((void *)); 130 void uhci_waitintr __P((uhci_softc_t *, usbd_request_handle)); 131 void uhci_check_intr __P((uhci_softc_t *, uhci_intr_info_t *)); 132 void uhci_ii_done __P((uhci_intr_info_t *, int)); 133 void uhci_timeout __P((void *)); 134 void uhci_wakeup_ctrl __P((void *, int, int, void *, int)); 135 void uhci_lock_frames __P((uhci_softc_t *)); 136 void uhci_unlock_frames __P((uhci_softc_t *)); 137 void uhci_add_ctrl __P((uhci_softc_t *, uhci_soft_qh_t *)); 138 void uhci_add_bulk __P((uhci_softc_t *, uhci_soft_qh_t *)); 139 void uhci_remove_ctrl __P((uhci_softc_t *, uhci_soft_qh_t *)); 140 void uhci_remove_bulk __P((uhci_softc_t *, uhci_soft_qh_t *)); 141 int uhci_str __P((usb_string_descriptor_t *, int, char *)); 142 143 void uhci_device_close __P((struct uhci_pipe *)); 144 145 void uhci_wakeup_cb __P((usbd_request_handle reqh)); 146 147 usbd_status uhci_device_ctrl_transfer __P((usbd_request_handle)); 148 void uhci_device_ctrl_abort __P((usbd_request_handle)); 149 void uhci_device_ctrl_close __P((usbd_pipe_handle)); 150 usbd_status uhci_device_intr_transfer __P((usbd_request_handle)); 151 void uhci_device_intr_abort __P((usbd_request_handle)); 152 void uhci_device_intr_close __P((usbd_pipe_handle)); 153 usbd_status uhci_device_bulk_transfer __P((usbd_request_handle)); 154 void uhci_device_bulk_abort __P((usbd_request_handle)); 155 void uhci_device_bulk_close __P((usbd_pipe_handle)); 156 157 usbd_status uhci_root_ctrl_transfer __P((usbd_request_handle)); 158 void uhci_root_ctrl_abort __P((usbd_request_handle)); 159 void uhci_root_ctrl_close __P((usbd_pipe_handle)); 160 usbd_status uhci_root_intr_transfer __P((usbd_request_handle)); 161 void uhci_root_intr_abort __P((usbd_request_handle)); 162 void uhci_root_intr_close __P((usbd_pipe_handle)); 163 164 usbd_status uhci_open __P((usbd_pipe_handle)); 165 166 usbd_status uhci_device_request __P((usbd_request_handle reqh)); 167 void uhci_ctrl_done __P((uhci_intr_info_t *ii)); 168 void uhci_bulk_done __P((uhci_intr_info_t *ii)); 169 170 void uhci_add_intr __P((uhci_softc_t *, int, uhci_soft_qh_t *)); 171 void uhci_remove_intr __P((uhci_softc_t *, int, uhci_soft_qh_t *)); 172 usbd_status uhci_device_setintr __P((uhci_softc_t *sc, 173 struct uhci_pipe *pipe, int ival)); 174 void uhci_intr_done __P((uhci_intr_info_t *ii)); 175 176 #ifdef USB_DEBUG 177 static void uhci_dumpregs __P((uhci_softc_t *)); 178 void uhci_dump_tds __P((uhci_soft_td_t *)); 179 void uhci_dump_qh __P((uhci_soft_qh_t *)); 180 void uhci_dump __P((void)); 181 void uhci_dump_td __P((uhci_soft_td_t *)); 182 #endif 183 184 #define UWRITE2(sc, r, x) bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)) 185 #define UWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 186 #define UREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 187 #define UREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 188 189 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 190 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 191 192 #define UHCI_RESET_TIMEOUT 100 /* reset timeout */ 193 #define UHCI_CTRL_TIMEOUT 500 /* control transaction timeout */ 194 #define UHCI_ISO_DELAY 50 /* delay of start of iso */ 195 196 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 197 198 #define UHCI_INTR_ENDPT 1 199 200 struct usbd_methods uhci_root_ctrl_methods = { 201 uhci_root_ctrl_transfer, 202 uhci_root_ctrl_abort, 203 uhci_root_ctrl_close, 204 }; 205 206 struct usbd_methods uhci_root_intr_methods = { 207 uhci_root_intr_transfer, 208 uhci_root_intr_abort, 209 uhci_root_intr_close, 210 }; 211 212 struct usbd_methods uhci_device_ctrl_methods = { 213 uhci_device_ctrl_transfer, 214 uhci_device_ctrl_abort, 215 uhci_device_ctrl_close, 216 }; 217 218 struct usbd_methods uhci_device_intr_methods = { 219 uhci_device_intr_transfer, 220 uhci_device_intr_abort, 221 uhci_device_intr_close, 222 }; 223 224 struct usbd_methods uhci_device_bulk_methods = { 225 uhci_device_bulk_transfer, 226 uhci_device_bulk_abort, 227 uhci_device_bulk_close, 228 }; 229 230 void 231 uhci_busreset(sc) 232 uhci_softc_t *sc; 233 { 234 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 235 usbd_delay_ms(USB_RESET_DELAY); /* wait at least 10ms */ 236 UHCICMD(sc, 0); /* do nothing */ 237 } 238 239 usbd_status 240 uhci_init(sc) 241 uhci_softc_t *sc; 242 { 243 usbd_status r; 244 int i, j; 245 uhci_soft_qh_t *csqh, *bsqh, *sqh; 246 uhci_soft_td_t *std; 247 uhci_dma_t dma; 248 249 DPRINTFN(1,("uhci_init: start\n")); 250 251 if (!uhci_global_init_done) { 252 uhci_global_init_done = 1; 253 LIST_INIT(&uhci_ii_free); 254 } 255 256 #if defined(USB_DEBUG) 257 if (uhcidebug > 2) 258 uhci_dumpregs(sc); 259 #endif 260 261 uhci_run(sc, 0); /* stop the controller */ 262 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 263 264 /* Allocate and initialize real frame array. */ 265 r = uhci_allocmem(sc, UHCI_FRAMELIST_COUNT * 266 sizeof(uhci_physaddr_t), 267 UHCI_FRAMELIST_ALIGN, &dma); 268 if (r != USBD_NORMAL_COMPLETION) 269 return (r); 270 sc->sc_pframes = KERNADDR(&dma); 271 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 272 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&dma)); /* set frame list */ 273 274 uhci_busreset(sc); 275 276 /* Allocate the dummy QH where bulk traffic will be queued. */ 277 bsqh = uhci_alloc_sqh(sc); 278 if (!bsqh) 279 return (USBD_NOMEM); 280 bsqh->qh->qh_hlink = UHCI_PTR_T; /* end of QH chain */ 281 bsqh->qh->qh_elink = UHCI_PTR_T; 282 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 283 284 /* Allocate the dummy QH where control traffic will be queued. */ 285 csqh = uhci_alloc_sqh(sc); 286 if (!csqh) 287 return (USBD_NOMEM); 288 csqh->qh->hlink = bsqh; 289 csqh->qh->qh_hlink = bsqh->physaddr | UHCI_PTR_Q; 290 csqh->qh->qh_elink = UHCI_PTR_T; 291 sc->sc_ctl_start = sc->sc_ctl_end = csqh; 292 293 /* 294 * Make all (virtual) frame list pointers point to the interrupt 295 * queue heads and the interrupt queue heads at the control 296 * queue head and point the physical frame list to the virtual. 297 */ 298 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 299 std = uhci_alloc_std(sc); 300 sqh = uhci_alloc_sqh(sc); 301 if (!std || !sqh) 302 return (ENOMEM); 303 std->td->link.sqh = sqh; 304 std->td->td_link = sqh->physaddr | UHCI_PTR_Q; 305 std->td->td_status = UHCI_TD_IOS; /* iso, inactive */ 306 std->td->td_token = 0; 307 std->td->td_buffer = 0; 308 sqh->qh->hlink = csqh; 309 sqh->qh->qh_hlink = csqh->physaddr | UHCI_PTR_Q; 310 sqh->qh->elink = 0; 311 sqh->qh->qh_elink = UHCI_PTR_T; 312 sc->sc_vframes[i].htd = std; 313 sc->sc_vframes[i].etd = std; 314 sc->sc_vframes[i].hqh = sqh; 315 sc->sc_vframes[i].eqh = sqh; 316 for (j = i; 317 j < UHCI_FRAMELIST_COUNT; 318 j += UHCI_VFRAMELIST_COUNT) 319 sc->sc_pframes[j] = std->physaddr; 320 } 321 322 LIST_INIT(&sc->sc_intrhead); 323 324 /* Set up the bus struct. */ 325 sc->sc_bus.open_pipe = uhci_open; 326 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 327 328 DPRINTFN(1,("uhci_init: enabling\n")); 329 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 330 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 331 332 uhci_run(sc, 1); /* and here we go... */ 333 return (USBD_NORMAL_COMPLETION); 334 } 335 336 #ifdef USB_DEBUG 337 static void 338 uhci_dumpregs(sc) 339 uhci_softc_t *sc; 340 { 341 printf("%s: regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 342 sc->sc_bus.bdev.dv_xname, 343 UREAD2(sc, UHCI_CMD), 344 UREAD2(sc, UHCI_STS), 345 UREAD2(sc, UHCI_INTR), 346 UREAD2(sc, UHCI_FRNUM), 347 UREAD2(sc, UHCI_FLBASEADDR), 348 UREAD2(sc, UHCI_SOF), 349 UREAD2(sc, UHCI_PORTSC1), 350 UREAD2(sc, UHCI_PORTSC2)); 351 } 352 353 int uhci_longtd = 1; 354 355 void 356 uhci_dump_td(p) 357 uhci_soft_td_t *p; 358 { 359 printf("TD(%p) at %08lx = 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", 360 p, (long)p->physaddr, 361 (long)p->td->td_link, 362 (long)p->td->td_status, 363 (long)p->td->td_token, 364 (long)p->td->td_buffer); 365 if (uhci_longtd) 366 printf(" %b %b,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d,D=%d,maxlen=%d\n", 367 (long)p->td->td_link, 368 "\20\1T\2Q\3VF", 369 (long)p->td->td_status, 370 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 371 UHCI_TD_GET_ERRCNT(p->td->td_status), 372 UHCI_TD_GET_ACTLEN(p->td->td_status), 373 UHCI_TD_GET_PID(p->td->td_token), 374 UHCI_TD_GET_DEVADDR(p->td->td_token), 375 UHCI_TD_GET_ENDPT(p->td->td_token), 376 UHCI_TD_GET_DT(p->td->td_token), 377 UHCI_TD_GET_MAXLEN(p->td->td_token)); 378 379 } 380 381 void 382 uhci_dump_qh(p) 383 uhci_soft_qh_t *p; 384 { 385 printf("QH(%p) at %08x: hlink=%08x elink=%08x\n", p, (int)p->physaddr, 386 p->qh->qh_hlink, p->qh->qh_elink); 387 } 388 389 #if 0 390 void 391 uhci_dump() 392 { 393 uhci_softc_t *sc = uhci; 394 395 uhci_dumpregs(sc); 396 printf("intrs=%d\n", sc->sc_intrs); 397 printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link); 398 uhci_dump_qh(sc->sc_ctl_start->qh->hlink); 399 } 400 #endif 401 402 void 403 uhci_dump_tds(std) 404 uhci_soft_td_t *std; 405 { 406 uhci_soft_td_t *p; 407 408 for(p = std; p; p = p->td->link.std) 409 uhci_dump_td(p); 410 } 411 #endif 412 413 /* 414 * This routine is executed periodically and simulates interrupts 415 * from the root controller interrupt pipe for port status change. 416 */ 417 void 418 uhci_timo(addr) 419 void *addr; 420 { 421 usbd_request_handle reqh = addr; 422 usbd_pipe_handle pipe = reqh->pipe; 423 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 424 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 425 int s; 426 u_char *p; 427 428 DPRINTFN(15, ("uhci_timo\n")); 429 430 p = KERNADDR(&upipe->u.intr.datadma); 431 p[0] = 0; 432 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 433 p[0] |= 1<<1; 434 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 435 p[0] |= 1<<2; 436 if (p[0] != 0) { 437 reqh->actlen = 1; 438 reqh->status = USBD_NORMAL_COMPLETION; 439 s = splusb(); 440 reqh->xfercb(reqh); 441 splx(s); 442 } 443 if (reqh->pipe->intrreqh == reqh) { 444 timeout(uhci_timo, addr, sc->sc_ival); 445 } else { 446 uhci_freemem(sc, &upipe->u.intr.datadma); 447 } 448 } 449 450 451 void 452 uhci_lock_frames(sc) 453 uhci_softc_t *sc; 454 { 455 int s = splusb(); 456 while (sc->sc_vflock) { 457 sc->sc_vflock |= UHCI_WANT_LOCK; 458 tsleep(&sc->sc_vflock, PRIBIO, "uhcqhl", 0); 459 } 460 sc->sc_vflock = UHCI_HAS_LOCK; 461 splx(s); 462 } 463 464 void 465 uhci_unlock_frames(sc) 466 uhci_softc_t *sc; 467 { 468 int s = splusb(); 469 sc->sc_vflock &= ~UHCI_HAS_LOCK; 470 if (sc->sc_vflock & UHCI_WANT_LOCK) 471 wakeup(&sc->sc_vflock); 472 splx(s); 473 } 474 475 /* 476 * Allocate an interrupt information struct. A free list is kept 477 * for fast allocation. 478 */ 479 uhci_intr_info_t * 480 uhci_alloc_intr_info(sc) 481 uhci_softc_t *sc; 482 { 483 uhci_intr_info_t *ii; 484 485 ii = LIST_FIRST(&uhci_ii_free); 486 if (ii) 487 LIST_REMOVE(ii, list); 488 else { 489 ii = malloc(sizeof(uhci_intr_info_t), M_USBDEV, M_NOWAIT); 490 } 491 ii->sc = sc; 492 return ii; 493 } 494 495 void 496 uhci_free_intr_info(ii) 497 uhci_intr_info_t *ii; 498 { 499 LIST_INSERT_HEAD(&uhci_ii_free, ii, list); /* and put on free list */ 500 } 501 502 /* Add control QH, called at splusb(). */ 503 void 504 uhci_add_ctrl(sc, sqh) 505 uhci_softc_t *sc; 506 uhci_soft_qh_t *sqh; 507 { 508 uhci_qh_t *eqh; 509 510 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 511 eqh = sc->sc_ctl_end->qh; 512 sqh->qh->hlink = eqh->hlink; 513 sqh->qh->qh_hlink = eqh->qh_hlink; 514 eqh->hlink = sqh; 515 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 516 sc->sc_ctl_end = sqh; 517 } 518 519 /* Remove control QH, called at splusb(). */ 520 void 521 uhci_remove_ctrl(sc, sqh) 522 uhci_softc_t *sc; 523 uhci_soft_qh_t *sqh; 524 { 525 uhci_soft_qh_t *pqh; 526 527 DPRINTFN(10, ("uhci_remove_ctrl: sqh=%p\n", sqh)); 528 for (pqh = sc->sc_ctl_start; pqh->qh->hlink != sqh; pqh=pqh->qh->hlink) 529 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 530 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 531 printf("uhci_remove_ctrl: QH not found\n"); 532 return; 533 } 534 #else 535 ; 536 #endif 537 pqh->qh->hlink = sqh->qh->hlink; 538 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 539 if (sc->sc_ctl_end == sqh) 540 sc->sc_ctl_end = pqh; 541 } 542 543 /* Add bulk QH, called at splusb(). */ 544 void 545 uhci_add_bulk(sc, sqh) 546 uhci_softc_t *sc; 547 uhci_soft_qh_t *sqh; 548 { 549 uhci_qh_t *eqh; 550 551 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 552 eqh = sc->sc_bulk_end->qh; 553 sqh->qh->hlink = eqh->hlink; 554 sqh->qh->qh_hlink = eqh->qh_hlink; 555 eqh->hlink = sqh; 556 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 557 sc->sc_bulk_end = sqh; 558 } 559 560 /* Remove bulk QH, called at splusb(). */ 561 void 562 uhci_remove_bulk(sc, sqh) 563 uhci_softc_t *sc; 564 uhci_soft_qh_t *sqh; 565 { 566 uhci_soft_qh_t *pqh; 567 568 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 569 for (pqh = sc->sc_bulk_start; pqh->qh->hlink != sqh; pqh=pqh->qh->hlink) 570 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 571 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 572 printf("uhci_remove_bulk: QH not found\n"); 573 return; 574 } 575 #else 576 ; 577 #endif 578 pqh->qh->hlink = sqh->qh->hlink; 579 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 580 if (sc->sc_bulk_end == sqh) 581 sc->sc_bulk_end = pqh; 582 } 583 584 int 585 uhci_intr(p) 586 void *p; 587 { 588 uhci_softc_t *sc = p; 589 int status, ret; 590 uhci_intr_info_t *ii; 591 592 sc->sc_intrs++; 593 #if defined(USB_DEBUG) 594 if (uhcidebug > 9) { 595 DPRINTF(("uhci_intr %s, %p\n", sc->sc_bus.bdev.dv_xname, sc)); 596 uhci_dumpregs(sc); 597 } 598 #endif 599 status = UREAD2(sc, UHCI_STS); 600 ret = 0; 601 if (status & UHCI_STS_USBINT) { 602 UWRITE2(sc, UHCI_STS, UHCI_STS_USBINT); /* acknowledge */ 603 ret = 1; 604 } 605 if (status & UHCI_STS_USBEI) { 606 UWRITE2(sc, UHCI_STS, UHCI_STS_USBEI); /* acknowledge */ 607 ret = 1; 608 } 609 if (status & UHCI_STS_RD) { 610 UWRITE2(sc, UHCI_STS, UHCI_STS_RD); /* acknowledge */ 611 printf("%s: resume detect\n", sc->sc_bus.bdev.dv_xname); 612 ret = 1; 613 } 614 if (status & UHCI_STS_HSE) { 615 UWRITE2(sc, UHCI_STS, UHCI_STS_HSE); /* acknowledge */ 616 printf("%s: Host System Error\n", sc->sc_bus.bdev.dv_xname); 617 ret = 1; 618 } 619 if (status & UHCI_STS_HCPE) { 620 UWRITE2(sc, UHCI_STS, UHCI_STS_HCPE); /* acknowledge */ 621 printf("%s: Host System Error\n", sc->sc_bus.bdev.dv_xname); 622 ret = 1; 623 } 624 if (status & UHCI_STS_HCH) { 625 printf("%s: controller halted\n", sc->sc_bus.bdev.dv_xname); 626 } 627 if (!ret) 628 return 0; 629 630 /* 631 * Interrupts on UHCI really suck. When the host controller 632 * interrupts because a transfer is completed there is no 633 * way of knowing which transfer it was. You can scan down 634 * the TDs and QHs of the previous frame to limit the search, 635 * but that assumes that the interrupt was not delayed by more 636 * than 1 ms, which may not always be true (e.g. after debug 637 * output on a slow console). 638 * We scan all interrupt descriptors to see if any have 639 * completed. 640 */ 641 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 642 uhci_check_intr(sc, ii); 643 644 DPRINTFN(10, ("uhci_intr: exit\n")); 645 return 1; 646 } 647 648 /* Check for an interrupt. */ 649 void 650 uhci_check_intr(sc, ii) 651 uhci_softc_t *sc; 652 uhci_intr_info_t *ii; 653 { 654 struct uhci_pipe *upipe; 655 uhci_soft_td_t *std, *lstd; 656 657 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 658 #ifdef DIAGNOSTIC 659 if (!ii) { 660 printf("uhci_check_intr: no ii? %p\n", ii); 661 return; 662 } 663 #endif 664 if (!ii->stdstart) 665 return; 666 lstd = ii->stdend; 667 #ifdef DIAGNOSTIC 668 if (!lstd) { 669 printf("uhci_check_intr: std==0\n"); 670 return; 671 } 672 #endif 673 /* If the last TD is still active the whole transfer probably is. */ 674 if (lstd->td->td_status & UHCI_TD_ACTIVE) { 675 DPRINTFN(15, ("uhci_check_intr: active ii=%p\n", ii)); 676 for (std = ii->stdstart; std != lstd; std = std->td->link.std) 677 if (std->td->td_status & UHCI_TD_STALLED) 678 goto done; 679 DPRINTFN(15, ("uhci_check_intr: ii=%p still active\n", ii)); 680 return; 681 } 682 done: 683 upipe = (struct uhci_pipe *)ii->reqh->pipe; 684 upipe->pipe.endpoint->toggle = upipe->newtoggle; 685 uhci_ii_done(ii, 0); 686 untimeout(uhci_timeout, ii); 687 } 688 689 void 690 uhci_ii_done(ii, timo) 691 uhci_intr_info_t *ii; 692 int timo; 693 { 694 usbd_request_handle reqh = ii->reqh; 695 uhci_soft_td_t *std; 696 u_int32_t tst; 697 int len, status; 698 699 DPRINTFN(10, ("uhci_check_intr: ii=%p ready\n", ii)); 700 701 /* The transfer is done, compute length and status. */ 702 for (len = status = 0, std = ii->stdstart; 703 std != 0; 704 std = std->td->link.std) { 705 tst = std->td->td_status;; 706 status |= tst; 707 #ifdef USB_DEBUG 708 if ((tst & UHCI_TD_ERROR) && uhcidebug) { 709 printf("uhci_intr: intr error TD:\n"); 710 uhci_dump_td(std); 711 } 712 #endif 713 if (UHCI_TD_GET_PID(std->td->td_token) != UHCI_TD_PID_SETUP) 714 len += UHCI_TD_GET_ACTLEN(tst); 715 } 716 status &= UHCI_TD_ERROR; 717 DPRINTFN(10, ("uhci_check_intr: len=%d, status=0x%x\n", len, status)); 718 if (status != 0) { 719 DPRINTFN(-1+(status==UHCI_TD_STALLED), 720 ("uhci_intr: error, status 0x%b\n", (long)status, 721 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27STALLED\30ACTIVE")); 722 if (status == UHCI_TD_STALLED) 723 reqh->status = USBD_STALLED; 724 else 725 reqh->status = USBD_IOERROR; /* more info XXX */ 726 reqh->actlen = 0; 727 } else { 728 reqh->status = USBD_NORMAL_COMPLETION; 729 reqh->actlen = len; 730 } 731 if (timo) { 732 /* We got a timeout. Make sure transaction is not active. */ 733 reqh->status = USBD_TIMEOUT; 734 for (std = ii->stdstart; std != 0; std = std->td->link.std) 735 std->td->td_status &= ~UHCI_TD_ACTIVE; 736 /* XXX should we wait 1 ms */ 737 } 738 DPRINTFN(5, ("uhci_intr: calling handler ii=%p\n", ii)); 739 740 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 741 case UE_CONTROL: 742 uhci_ctrl_done(ii); 743 break; 744 case UE_ISOCHRONOUS: 745 printf("uhci_ii_done: ISO??\n"); 746 case UE_BULK: 747 uhci_bulk_done(ii); 748 break; 749 case UE_INTERRUPT: 750 uhci_intr_done(ii); 751 break; 752 } 753 754 /* And finally execute callback. */ 755 reqh->xfercb(reqh); 756 } 757 758 void 759 uhci_timeout(addr) 760 void *addr; 761 { 762 uhci_intr_info_t *ii = addr; 763 int s; 764 765 DPRINTF(("uhci_timeout: ii=%p\n", ii)); 766 s = splusb(); 767 uhci_ii_done(ii, 1); 768 splx(s); 769 } 770 771 /* 772 * Wait here until controller claims to have an interrupt. 773 * Then call uhci_intr and return. Use timeout to avoid waiting 774 * too long. 775 */ 776 void 777 uhci_waitintr(sc, reqh) 778 uhci_softc_t *sc; 779 usbd_request_handle reqh; 780 { 781 int timo = reqh->timeout; 782 int usecs; 783 784 reqh->status = USBD_IN_PROGRESS; 785 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 786 delay(1000); 787 DPRINTFN(10,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 788 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 789 uhci_intr(sc); 790 if (reqh->status != USBD_IN_PROGRESS) 791 return; 792 } 793 } 794 reqh->status = USBD_TIMEOUT; 795 reqh->xfercb(reqh); 796 } 797 798 #if 0 799 void 800 uhci_reset(p) 801 void *p; 802 { 803 uhci_softc_t *sc = p; 804 int n; 805 806 UHCICMD(sc, UHCI_CMD_HCRESET); 807 /* The reset bit goes low when the controller is done. */ 808 for (n = 0; n < UHCI_RESET_TIMEOUT && 809 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 810 delay(100); 811 if (n >= UHCI_RESET_TIMEOUT) 812 printf("%s: controller did not reset\n", sc->sc_bus.bdev.dv_xname); 813 } 814 #endif 815 816 void 817 uhci_run(sc, run) 818 uhci_softc_t *sc; 819 int run; 820 { 821 int s, n, running; 822 823 run = run != 0; 824 s = splusb(); /* XXX really? */ 825 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 826 if (run == running) { 827 splx(s); 828 return; 829 } 830 UWRITE2(sc, UHCI_CMD, run ? UHCI_CMD_RS : 0); 831 for(n = 0; n < 100; n++) { 832 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 833 /* return when we've entered the state we want */ 834 if (run == running) { 835 splx(s); 836 return; 837 } 838 } 839 splx(s); 840 printf("%s: cannot %s\n", sc->sc_bus.bdev.dv_xname, run ? "start" : "stop"); 841 } 842 843 /* 844 * Memory management routines. 845 * uhci_allocmem allocates DMAable memory. 846 * uhci_alloc_std allocates TDs 847 * uhci_alloc_sqh allocates QHs 848 * uhci_alloc_buffer allocates transfer buffers. 849 * The latter three routines do their own free list management, 850 * partly for speed, partly because allocating DMAable memory 851 * has page size granularaity so much memory would be wasted if 852 * only one TD/QH (32 bytes) was placed in each alloacted chunk. 853 */ 854 855 usbd_status 856 uhci_allocmem(sc, size, align, p) 857 uhci_softc_t *sc; 858 size_t size; 859 size_t align; 860 uhci_dma_t *p; 861 { 862 int error; 863 864 DPRINTFN(5, ("uhci_allocmem: size=%d align=%d\n", size, align)); 865 p->size = size; 866 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 867 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 868 &p->nsegs, BUS_DMA_NOWAIT); 869 if (error) 870 return (USBD_NOMEM); 871 872 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 873 &p->kaddr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 874 if (error) 875 goto free; 876 877 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 878 0, BUS_DMA_NOWAIT, &p->map); 879 if (error) 880 goto unmap; 881 882 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->kaddr,p->size, NULL, 883 BUS_DMA_NOWAIT); 884 if (error) 885 goto destroy; 886 return 0; 887 888 destroy: 889 bus_dmamap_destroy(sc->sc_dmatag, p->map); 890 unmap: 891 bus_dmamem_unmap(sc->sc_dmatag, p->kaddr, p->size); 892 free: 893 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 894 return (USBD_NOMEM); 895 } 896 897 void 898 uhci_freemem(sc, p) 899 uhci_softc_t *sc; 900 uhci_dma_t *p; 901 { 902 bus_dmamap_unload(sc->sc_dmatag, p->map); 903 bus_dmamap_destroy(sc->sc_dmatag, p->map); 904 bus_dmamem_unmap(sc->sc_dmatag, p->kaddr, p->size); 905 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 906 } 907 908 uhci_soft_td_t * 909 uhci_alloc_std(sc) 910 uhci_softc_t *sc; 911 { 912 uhci_soft_td_t *std; 913 usbd_status r; 914 int i; 915 uhci_dma_t dma; 916 917 if (!sc->sc_freetds) { 918 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 919 std = malloc(sizeof(uhci_soft_td_t) * UHCI_TD_CHUNK, 920 M_USBDEV, M_NOWAIT); 921 if (!std) 922 return 0; 923 r = uhci_allocmem(sc, UHCI_TD_SIZE * UHCI_TD_CHUNK, 924 UHCI_TD_ALIGN, &dma); 925 if (r != USBD_NORMAL_COMPLETION) { 926 free(std, M_USBDEV); 927 return 0; 928 } 929 for(i = 0; i < UHCI_TD_CHUNK; i++, std++) { 930 std->physaddr = DMAADDR(&dma) + 931 i * UHCI_TD_SIZE; 932 std->td = (uhci_td_t *) 933 ((char *)KERNADDR(&dma) + i * UHCI_TD_SIZE); 934 std->td->link.std = sc->sc_freetds; 935 sc->sc_freetds = std; 936 } 937 } 938 std = sc->sc_freetds; 939 sc->sc_freetds = std->td->link.std; 940 memset(std->td, 0, UHCI_TD_SIZE); 941 return std; 942 } 943 944 void 945 uhci_free_std(sc, std) 946 uhci_softc_t *sc; 947 uhci_soft_td_t *std; 948 { 949 std->td->link.std = sc->sc_freetds; 950 sc->sc_freetds = std; 951 } 952 953 uhci_soft_qh_t * 954 uhci_alloc_sqh(sc) 955 uhci_softc_t *sc; 956 { 957 uhci_soft_qh_t *sqh; 958 usbd_status r; 959 int i, offs; 960 uhci_dma_t dma; 961 962 if (!sc->sc_freeqhs) { 963 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 964 sqh = malloc(sizeof(uhci_soft_qh_t) * UHCI_QH_CHUNK, 965 M_USBDEV, M_NOWAIT); 966 if (!sqh) 967 return 0; 968 r = uhci_allocmem(sc, UHCI_QH_SIZE * UHCI_QH_CHUNK, 969 UHCI_QH_ALIGN, &dma); 970 if (r != USBD_NORMAL_COMPLETION) { 971 free(sqh, M_USBDEV); 972 return 0; 973 } 974 for(i = 0; i < UHCI_QH_CHUNK; i++, sqh++) { 975 offs = i * UHCI_QH_SIZE; 976 sqh->physaddr = DMAADDR(&dma) + offs; 977 sqh->qh = (uhci_qh_t *) 978 ((char *)KERNADDR(&dma) + offs); 979 sqh->qh->hlink = sc->sc_freeqhs; 980 sc->sc_freeqhs = sqh; 981 } 982 } 983 sqh = sc->sc_freeqhs; 984 sc->sc_freeqhs = sqh->qh->hlink; 985 memset(sqh->qh, 0, UHCI_QH_SIZE); 986 return sqh; 987 } 988 989 void 990 uhci_free_sqh(sc, sqh) 991 uhci_softc_t *sc; 992 uhci_soft_qh_t *sqh; 993 { 994 sqh->qh->hlink = sc->sc_freeqhs; 995 sc->sc_freeqhs = sqh; 996 } 997 998 #if 0 999 void * 1000 uhci_alloc_buffer(sc, size) 1001 uhci_softc_t *sc; 1002 size_t size; 1003 { 1004 struct uhci_buffer *buf; 1005 usbd_status r; 1006 int i, offs; 1007 uhci_dma_t dma; 1008 1009 if (!sc->sc_freebuffers) { 1010 DPRINTFN(2, ("uhci_alloc_buffer: allocating chunk\n")); 1011 r = uhci_allocmem(sc, UHCI_BUFFER_SIZE * BUFFER_CHUNK, 1012 0, &dma); 1013 if (r != USBD_NORMAL_COMPLETION) 1014 return 0; 1015 for(i = 0; i < BUFFER_CHUNK; i++, sqh++) { 1016 offs = i * UHCI_BUFFER_SIZE; 1017 sqh->physaddr = DMAADDR(&dma) + offs; 1018 sqh->qh = (uhci_qh_t *) 1019 ((char *)KERNADDR(&dma) + offs); 1020 sqh->qh->hlink = sc->sc_freeqhs; 1021 sc->sc_freeqhs = sqh; 1022 } 1023 } 1024 sqh = sc->sc_freeqhs; 1025 sc->sc_freeqhs = sqh->qh->hlink; 1026 memset(sqh->qh, 0, UHCI_QH_SIZE); 1027 return sqh; 1028 } 1029 1030 void 1031 uhci_free_buffer(sc, p, size) 1032 uhci_softc_t *sc; 1033 void *p; 1034 size_t size; 1035 { 1036 } 1037 #endif 1038 1039 /* 1040 * Enter a list of transfers onto a control queue. 1041 * Called at splusb() 1042 */ 1043 void 1044 uhci_enter_ctl_q(sc, sqh, ii) 1045 uhci_softc_t *sc; 1046 uhci_soft_qh_t *sqh; 1047 uhci_intr_info_t *ii; 1048 { 1049 DPRINTFN(5, ("uhci_enter_ctl_q: sqh=%p\n", sqh)); 1050 1051 } 1052 1053 void 1054 uhci_free_std_chain(sc, std, stdend) 1055 uhci_softc_t *sc; 1056 uhci_soft_td_t *std; 1057 uhci_soft_td_t *stdend; 1058 { 1059 uhci_soft_td_t *p; 1060 1061 for (; std != stdend; std = p) { 1062 p = std->td->link.std; 1063 uhci_free_std(sc, std); 1064 } 1065 } 1066 1067 usbd_status 1068 uhci_alloc_std_chain(upipe, sc, len, rd, dma, sp, ep) 1069 struct uhci_pipe *upipe; 1070 uhci_softc_t *sc; 1071 int len, rd; 1072 uhci_dma_t *dma; 1073 uhci_soft_td_t **sp, **ep; 1074 { 1075 uhci_soft_td_t *p, *lastp; 1076 uhci_physaddr_t lastlink; 1077 u_int32_t ls; 1078 int i, ntd, l, tog, maxp; 1079 int addr = upipe->pipe.device->address; 1080 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1081 1082 DPRINTFN(15, ("uhci_alloc_std_chain: len=%d\n", len)); 1083 if (len == 0) { 1084 *sp = *ep = 0; 1085 printf("uhci_alloc_std_chain: len=0\n"); 1086 return (USBD_NORMAL_COMPLETION); 1087 } 1088 ls = upipe->pipe.device->lowspeed ? UHCI_TD_LS : 0; 1089 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1090 if (maxp == 0) { 1091 printf("uhci_alloc_std_chain: maxp=0\n"); 1092 return (USBD_INVAL); 1093 } 1094 ntd = (len + maxp - 1) / maxp; 1095 tog = upipe->pipe.endpoint->toggle; 1096 if (ntd % 2 == 0) 1097 tog ^= 1; 1098 upipe->newtoggle = tog ^ 1; 1099 lastp = 0; 1100 lastlink = UHCI_PTR_T; 1101 ntd--; 1102 for (i = ntd; i >= 0; i--) { 1103 p = uhci_alloc_std(sc); 1104 if (!p) { 1105 uhci_free_std_chain(sc, lastp, 0); 1106 return (USBD_NOMEM); 1107 } 1108 p->td->link.std = lastp; 1109 p->td->td_link = lastlink; 1110 lastp = p; 1111 lastlink = p->physaddr; 1112 p->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | UHCI_TD_ACTIVE; 1113 if (i == ntd) { 1114 /* last TD */ 1115 l = len % maxp; 1116 if (l == 0) l = maxp; 1117 *ep = p; 1118 } else 1119 l = maxp; 1120 p->td->td_token = 1121 rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1122 UHCI_TD_OUT(l, endpt, addr, tog); 1123 p->td->td_buffer = DMAADDR(dma) + i * maxp; 1124 tog ^= 1; 1125 } 1126 *sp = lastp; 1127 /*upipe->pipe.endpoint->toggle = tog;*/ 1128 DPRINTFN(10, ("uhci_alloc_std_chain: oldtog=%d newtog=%d\n", 1129 upipe->pipe.endpoint->toggle, upipe->newtoggle)); 1130 return (USBD_NORMAL_COMPLETION); 1131 } 1132 1133 usbd_status 1134 uhci_device_bulk_transfer(reqh) 1135 usbd_request_handle reqh; 1136 { 1137 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1138 usbd_device_handle dev = upipe->pipe.device; 1139 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1140 uhci_intr_info_t *ii = upipe->iinfo; 1141 uhci_soft_td_t *xfer, *xferend; 1142 uhci_soft_qh_t *sqh; 1143 uhci_dma_t *dmap; 1144 usbd_status r; 1145 int len, isread; 1146 int s; 1147 1148 DPRINTFN(3, ("uhci_device_bulk_transfer: reqh=%p buf=%p len=%d flags=%d\n", 1149 reqh, reqh->buffer, reqh->length, reqh->flags)); 1150 1151 if (reqh->isreq) 1152 panic("uhci_device_bulk_transfer: a request\n"); 1153 1154 len = reqh->length; 1155 dmap = &upipe->u.bulk.datadma; 1156 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1157 sqh = upipe->u.bulk.sqh; 1158 1159 upipe->u.bulk.isread = isread; 1160 upipe->u.bulk.length = len; 1161 1162 r = uhci_allocmem(sc, len, 0, dmap); 1163 if (r != USBD_NORMAL_COMPLETION) 1164 goto ret1; 1165 r = uhci_alloc_std_chain(upipe, sc, len, isread, 1166 dmap, &xfer, &xferend); 1167 if (r != USBD_NORMAL_COMPLETION) 1168 goto ret2; 1169 xferend->td->td_status |= UHCI_TD_IOC; 1170 1171 if (!isread && len != 0) 1172 memcpy(KERNADDR(dmap), reqh->buffer, len); 1173 1174 #ifdef USB_DEBUG 1175 if (uhcidebug > 10) { 1176 printf("uhci_device_bulk_transfer: xfer(1)\n"); 1177 uhci_dump_tds(xfer); 1178 } 1179 #endif 1180 1181 /* Set up interrupt info. */ 1182 ii->reqh = reqh; 1183 ii->stdstart = xfer; 1184 ii->stdend = xferend; 1185 1186 sqh->qh->elink = xfer; 1187 sqh->qh->qh_elink = xfer->physaddr; 1188 sqh->intr_info = ii; 1189 1190 s = splusb(); 1191 uhci_add_bulk(sc, sqh); 1192 LIST_INSERT_HEAD(&sc->sc_intrhead, ii, list); 1193 1194 if (reqh->timeout && !usbd_use_polling) 1195 timeout(uhci_timeout, ii, MS_TO_TICKS(reqh->timeout)); 1196 splx(s); 1197 1198 #ifdef USB_DEBUG 1199 if (uhcidebug > 10) { 1200 printf("uhci_device_bulk_transfer: xfer(2)\n"); 1201 uhci_dump_tds(xfer); 1202 } 1203 #endif 1204 1205 return (USBD_IN_PROGRESS); 1206 1207 ret2: 1208 if (len != 0) 1209 uhci_freemem(sc, dmap); 1210 ret1: 1211 return (r); 1212 } 1213 1214 /* Abort a device bulk request. */ 1215 void 1216 uhci_device_bulk_abort(reqh) 1217 usbd_request_handle reqh; 1218 { 1219 /* XXX */ 1220 usbd_delay_ms(2); /* make sure it is finished */ 1221 } 1222 1223 /* Close a device bulk pipe. */ 1224 void 1225 uhci_device_bulk_close(pipe) 1226 usbd_pipe_handle pipe; 1227 { 1228 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1229 usbd_device_handle dev = upipe->pipe.device; 1230 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1231 1232 uhci_free_sqh(sc, upipe->u.bulk.sqh); 1233 uhci_free_intr_info(upipe->iinfo); 1234 /* XXX free other resources */ 1235 } 1236 1237 usbd_status 1238 uhci_device_ctrl_transfer(reqh) 1239 usbd_request_handle reqh; 1240 { 1241 usbd_status r; 1242 1243 if (!reqh->isreq) 1244 panic("uhci_device_ctrl_transfer: not a request\n"); 1245 1246 r = uhci_device_request(reqh); 1247 if (r != USBD_NORMAL_COMPLETION) 1248 return (r); 1249 1250 if (usbd_use_polling) 1251 uhci_waitintr((uhci_softc_t *)reqh->pipe->device->bus, reqh); 1252 return (USBD_IN_PROGRESS); 1253 } 1254 1255 usbd_status 1256 uhci_device_intr_transfer(reqh) 1257 usbd_request_handle reqh; 1258 { 1259 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1260 usbd_device_handle dev = upipe->pipe.device; 1261 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1262 uhci_intr_info_t *ii = upipe->iinfo; 1263 uhci_soft_td_t *xfer, *xferend; 1264 uhci_soft_qh_t *sqh; 1265 uhci_dma_t *dmap; 1266 usbd_status r; 1267 int len, i; 1268 int s; 1269 1270 DPRINTFN(3, ("uhci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d\n", 1271 reqh, reqh->buffer, reqh->length, reqh->flags)); 1272 1273 if (reqh->isreq) 1274 panic("uhci_device_intr_transfer: a request\n"); 1275 1276 len = reqh->length; 1277 dmap = &upipe->u.intr.datadma; 1278 if (len == 0) 1279 return (USBD_INVAL); /* XXX should it be? */ 1280 1281 r = uhci_allocmem(sc, len, 0, dmap); 1282 if (r != USBD_NORMAL_COMPLETION) 1283 goto ret1; 1284 r = uhci_alloc_std_chain(upipe, sc, len, 1, dmap, &xfer, &xferend); 1285 if (r != USBD_NORMAL_COMPLETION) 1286 goto ret2; 1287 xferend->td->td_status |= UHCI_TD_IOC; 1288 1289 #ifdef USB_DEBUG 1290 if (uhcidebug > 10) { 1291 printf("uhci_device_intr_transfer: xfer(1)\n"); 1292 uhci_dump_tds(xfer); 1293 uhci_dump_qh(upipe->u.intr.qhs[0]); 1294 } 1295 #endif 1296 1297 s = splusb(); 1298 /* Set up interrupt info. */ 1299 ii->reqh = reqh; 1300 ii->stdstart = xfer; 1301 ii->stdend = xferend; 1302 1303 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", upipe->u.intr.qhs[0])); 1304 for (i = 0; i < upipe->u.intr.npoll; i++) { 1305 sqh = upipe->u.intr.qhs[i]; 1306 sqh->qh->elink = xfer; 1307 sqh->qh->qh_elink = xfer->physaddr; 1308 } 1309 splx(s); 1310 1311 #ifdef USB_DEBUG 1312 if (uhcidebug > 10) { 1313 printf("uhci_device_intr_transfer: xfer(2)\n"); 1314 uhci_dump_tds(xfer); 1315 uhci_dump_qh(upipe->u.intr.qhs[0]); 1316 } 1317 #endif 1318 1319 return (USBD_IN_PROGRESS); 1320 1321 ret2: 1322 if (len != 0) 1323 uhci_freemem(sc, dmap); 1324 ret1: 1325 return (r); 1326 } 1327 1328 /* Abort a device control request. */ 1329 void 1330 uhci_device_ctrl_abort(reqh) 1331 usbd_request_handle reqh; 1332 { 1333 /* XXX */ 1334 usbd_delay_ms(2); /* make sure it is finished */ 1335 } 1336 1337 /* Close a device control pipe. */ 1338 void 1339 uhci_device_ctrl_close(pipe) 1340 usbd_pipe_handle pipe; 1341 { 1342 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1343 1344 uhci_free_intr_info(upipe->iinfo); 1345 /* XXX free other resources */ 1346 } 1347 1348 /* Abort a device interrupt request. */ 1349 void 1350 uhci_device_intr_abort(reqh) 1351 usbd_request_handle reqh; 1352 { 1353 struct uhci_pipe *upipe; 1354 1355 usbd_delay_ms(2); /* make sure it is finished */ 1356 if (reqh->pipe->intrreqh == reqh) { 1357 DPRINTF(("uhci_device_intr_abort: remove\n")); 1358 reqh->pipe->intrreqh = 0; 1359 upipe = (struct uhci_pipe *)reqh->pipe; 1360 uhci_intr_done(upipe->u.intr.qhs[0]->intr_info); 1361 } 1362 } 1363 1364 /* Close a device interrupt pipe. */ 1365 void 1366 uhci_device_intr_close(pipe) 1367 usbd_pipe_handle pipe; 1368 { 1369 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1370 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 1371 int i, s, npoll; 1372 1373 upipe->iinfo->stdstart = 0; /* inactive */ 1374 1375 /* Unlink descriptors from controller data structures. */ 1376 npoll = upipe->u.intr.npoll; 1377 uhci_lock_frames(sc); 1378 for (i = 0; i < npoll; i++) 1379 uhci_remove_intr(sc, upipe->u.intr.qhs[i]->pos, 1380 upipe->u.intr.qhs[i]); 1381 uhci_unlock_frames(sc); 1382 1383 /* 1384 * We now have to wait for any activity on the physical 1385 * descriptors to stop. 1386 */ 1387 usbd_delay_ms(2); 1388 1389 for(i = 0; i < npoll; i++) 1390 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 1391 free(upipe->u.intr.qhs, M_USB); 1392 1393 s = splusb(); 1394 LIST_REMOVE(upipe->iinfo, list); /* remove from active list */ 1395 splx(s); 1396 uhci_free_intr_info(upipe->iinfo); 1397 1398 /* XXX free other resources */ 1399 } 1400 1401 usbd_status 1402 uhci_device_request(reqh) 1403 usbd_request_handle reqh; 1404 { 1405 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1406 usb_device_request_t *req = &reqh->request; 1407 usbd_device_handle dev = upipe->pipe.device; 1408 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1409 int addr = dev->address; 1410 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1411 uhci_intr_info_t *ii = upipe->iinfo; 1412 uhci_soft_td_t *setup, *xfer, *stat, *next, *xferend; 1413 uhci_soft_qh_t *sqh; 1414 uhci_dma_t *dmap; 1415 int len; 1416 u_int32_t ls; 1417 usbd_status r; 1418 int isread; 1419 int s; 1420 1421 DPRINTFN(1,("uhci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1422 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1423 UGETW(req->wIndex), UGETW(req->wLength), 1424 addr, endpt)); 1425 1426 ls = dev->lowspeed ? UHCI_TD_LS : 0; 1427 isread = req->bmRequestType & UT_READ; 1428 len = UGETW(req->wLength); 1429 1430 setup = upipe->u.ctl.setup; 1431 stat = upipe->u.ctl.stat; 1432 sqh = upipe->u.ctl.sqh; 1433 dmap = &upipe->u.ctl.datadma; 1434 1435 /* Set up data transaction */ 1436 if (len != 0) { 1437 r = uhci_allocmem(sc, len, 0, dmap); 1438 if (r != USBD_NORMAL_COMPLETION) 1439 goto ret1; 1440 upipe->pipe.endpoint->toggle = 1; 1441 r = uhci_alloc_std_chain(upipe, sc, len, isread, 1442 dmap, &xfer, &xferend); 1443 if (r != USBD_NORMAL_COMPLETION) 1444 goto ret2; 1445 next = xfer; 1446 xferend->td->link.std = stat; 1447 xferend->td->td_link = stat->physaddr; 1448 } else { 1449 xfer = 0; 1450 next = stat; 1451 } 1452 upipe->u.ctl.length = len; 1453 upipe->u.ctl.xferend = xferend; 1454 1455 memcpy(KERNADDR(&upipe->u.ctl.reqdma), req, sizeof *req); 1456 if (!isread && len != 0) 1457 memcpy(KERNADDR(dmap), reqh->buffer, len); 1458 1459 setup->td->link.std = next; 1460 setup->td->td_link = next->physaddr; 1461 setup->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | UHCI_TD_ACTIVE; 1462 setup->td->td_token = UHCI_TD_SETUP(sizeof *req, endpt, addr); 1463 setup->td->td_buffer = DMAADDR(&upipe->u.ctl.reqdma); 1464 1465 stat->td->link.std = 0; 1466 stat->td->td_link = UHCI_PTR_T; 1467 stat->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | 1468 UHCI_TD_ACTIVE | UHCI_TD_IOC; 1469 stat->td->td_token = 1470 isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 1471 UHCI_TD_IN (0, endpt, addr, 1); 1472 stat->td->td_buffer = 0; 1473 1474 #ifdef USB_DEBUG 1475 if (uhcidebug > 20) { 1476 printf("uhci_device_request: setup\n"); 1477 uhci_dump_td(setup); 1478 printf("uhci_device_request: stat\n"); 1479 uhci_dump_td(stat); 1480 } 1481 #endif 1482 1483 /* Set up interrupt info. */ 1484 ii->reqh = reqh; 1485 ii->stdstart = setup; 1486 ii->stdend = stat; 1487 1488 sqh->qh->elink = setup; 1489 sqh->qh->qh_elink = setup->physaddr; 1490 sqh->intr_info = ii; 1491 1492 s = splusb(); 1493 uhci_add_ctrl(sc, sqh); 1494 LIST_INSERT_HEAD(&sc->sc_intrhead, ii, list); 1495 #ifdef USB_DEBUG 1496 if (uhcidebug > 12) { 1497 uhci_soft_td_t *std; 1498 uhci_soft_qh_t *xqh; 1499 uhci_physaddr_t link; 1500 printf("uhci_enter_ctl_q: follow from [0]\n"); 1501 for (std = sc->sc_vframes[0].htd, link = 0; 1502 (link & UHCI_PTR_Q) == 0; 1503 std = std->td->link.std) { 1504 link = std->td->td_link; 1505 uhci_dump_td(std); 1506 } 1507 for (xqh = (uhci_soft_qh_t *)std; 1508 xqh; 1509 xqh = xqh->qh->hlink) 1510 uhci_dump_qh(xqh); 1511 printf("Enqueued QH:\n"); 1512 uhci_dump_qh(sqh); 1513 uhci_dump_tds(sqh->qh->elink); 1514 } 1515 #endif 1516 if (reqh->timeout && !usbd_use_polling) 1517 timeout(uhci_timeout, ii, MS_TO_TICKS(reqh->timeout)); 1518 splx(s); 1519 1520 return (USBD_NORMAL_COMPLETION); 1521 1522 ret2: 1523 if (len != 0) 1524 uhci_freemem(sc, dmap); 1525 ret1: 1526 return (r); 1527 } 1528 1529 void 1530 uhci_intr_done(ii) 1531 uhci_intr_info_t *ii; 1532 { 1533 uhci_softc_t *sc = ii->sc; 1534 usbd_request_handle reqh = ii->reqh; 1535 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1536 uhci_dma_t *dma; 1537 uhci_soft_qh_t *sqh; 1538 int i, npoll; 1539 1540 DPRINTFN(5, ("uhci_intr_done: length=%d\n", reqh->actlen)); 1541 1542 dma = &upipe->u.intr.datadma; 1543 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 1544 npoll = upipe->u.intr.npoll; 1545 for(i = 0; i < npoll; i++) { 1546 sqh = upipe->u.intr.qhs[i]; 1547 sqh->qh->elink = 0; 1548 sqh->qh->qh_elink = UHCI_PTR_T; 1549 } 1550 uhci_free_std_chain(sc, ii->stdstart, 0); 1551 1552 /* XXX Wasteful. */ 1553 if (reqh->pipe->intrreqh == reqh) { 1554 uhci_soft_td_t *xfer, *xferend; 1555 1556 /* This alloc cannot fail since we freed the chain above. */ 1557 uhci_alloc_std_chain(upipe, sc, reqh->length, 1, dma, 1558 &xfer, &xferend); 1559 xferend->td->td_status |= UHCI_TD_IOC; 1560 1561 #ifdef USB_DEBUG 1562 if (uhcidebug > 10) { 1563 printf("uhci_device_intr_done: xfer(1)\n"); 1564 uhci_dump_tds(xfer); 1565 uhci_dump_qh(upipe->u.intr.qhs[0]); 1566 } 1567 #endif 1568 1569 ii->stdstart = xfer; 1570 ii->stdend = xferend; 1571 for (i = 0; i < npoll; i++) { 1572 sqh = upipe->u.intr.qhs[i]; 1573 sqh->qh->elink = xfer; 1574 sqh->qh->qh_elink = xfer->physaddr; 1575 } 1576 } else { 1577 uhci_freemem(sc, dma); 1578 ii->stdstart = 0; /* mark as inactive */ 1579 } 1580 } 1581 1582 /* Deallocate request data structures */ 1583 void 1584 uhci_ctrl_done(ii) 1585 uhci_intr_info_t *ii; 1586 { 1587 uhci_softc_t *sc = ii->sc; 1588 usbd_request_handle reqh = ii->reqh; 1589 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1590 u_int len = upipe->u.ctl.length; 1591 uhci_dma_t *dma; 1592 uhci_td_t *htd = ii->stdstart->td; 1593 1594 if (!reqh->isreq) 1595 panic("uhci_ctrl_done: not a request\n"); 1596 1597 LIST_REMOVE(ii, list); /* remove from active list */ 1598 1599 uhci_remove_ctrl(sc, upipe->u.ctl.sqh); 1600 1601 if (len != 0) { 1602 dma = &upipe->u.ctl.datadma; 1603 if (reqh->request.bmRequestType & UT_READ) 1604 memcpy(reqh->buffer, KERNADDR(dma), len); 1605 uhci_free_std_chain(sc, htd->link.std, ii->stdend); 1606 uhci_freemem(sc, dma); 1607 } 1608 DPRINTFN(5, ("uhci_ctrl_done: length=%d\n", reqh->actlen)); 1609 } 1610 1611 /* Deallocate request data structures */ 1612 void 1613 uhci_bulk_done(ii) 1614 uhci_intr_info_t *ii; 1615 { 1616 uhci_softc_t *sc = ii->sc; 1617 usbd_request_handle reqh = ii->reqh; 1618 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1619 u_int len = upipe->u.bulk.length; 1620 uhci_dma_t *dma; 1621 uhci_td_t *htd = ii->stdstart->td; 1622 1623 LIST_REMOVE(ii, list); /* remove from active list */ 1624 1625 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 1626 1627 if (len != 0) { 1628 dma = &upipe->u.bulk.datadma; 1629 if (upipe->u.bulk.isread && len != 0) 1630 memcpy(reqh->buffer, KERNADDR(dma), len); 1631 uhci_free_std_chain(sc, htd->link.std, 0); 1632 uhci_freemem(sc, dma); 1633 } 1634 DPRINTFN(4, ("uhci_bulk_done: length=%d\n", reqh->actlen)); 1635 /* XXX compute new toggle */ 1636 } 1637 1638 /* Add interrupt QH, called with vflock. */ 1639 void 1640 uhci_add_intr(sc, n, sqh) 1641 uhci_softc_t *sc; 1642 int n; 1643 uhci_soft_qh_t *sqh; 1644 { 1645 struct uhci_vframe *vf = &sc->sc_vframes[n]; 1646 uhci_qh_t *eqh; 1647 1648 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", n, sqh)); 1649 eqh = vf->eqh->qh; 1650 sqh->qh->hlink = eqh->hlink; 1651 sqh->qh->qh_hlink = eqh->qh_hlink; 1652 eqh->hlink = sqh; 1653 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 1654 vf->eqh = sqh; 1655 vf->bandwidth++; 1656 } 1657 1658 /* Remove interrupt QH, called with vflock. */ 1659 void 1660 uhci_remove_intr(sc, n, sqh) 1661 uhci_softc_t *sc; 1662 int n; 1663 uhci_soft_qh_t *sqh; 1664 { 1665 struct uhci_vframe *vf = &sc->sc_vframes[n]; 1666 uhci_soft_qh_t *pqh; 1667 1668 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", n, sqh)); 1669 1670 for (pqh = vf->hqh; pqh->qh->hlink != sqh; pqh = pqh->qh->hlink) 1671 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 1672 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 1673 printf("uhci_remove_intr: QH not found\n"); 1674 return; 1675 } 1676 #else 1677 ; 1678 #endif 1679 pqh->qh->hlink = sqh->qh->hlink; 1680 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 1681 if (vf->eqh == sqh) 1682 vf->eqh = pqh; 1683 vf->bandwidth--; 1684 } 1685 1686 usbd_status 1687 uhci_device_setintr(sc, upipe, ival) 1688 uhci_softc_t *sc; 1689 struct uhci_pipe *upipe; 1690 int ival; 1691 { 1692 uhci_soft_qh_t *sqh; 1693 int i, npoll, s; 1694 u_int bestbw, bw, bestoffs, offs; 1695 1696 DPRINTFN(2, ("uhci_setintr: pipe=%p\n", upipe)); 1697 if (ival == 0) { 1698 printf("uhci_setintr: 0 interval\n"); 1699 return (USBD_INVAL); 1700 } 1701 1702 if (ival > UHCI_VFRAMELIST_COUNT) 1703 ival = UHCI_VFRAMELIST_COUNT; 1704 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 1705 DPRINTFN(2, ("uhci_setintr: ival=%d npoll=%d\n", ival, npoll)); 1706 1707 upipe->u.intr.npoll = npoll; 1708 upipe->u.intr.qhs = 1709 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USB, M_WAITOK); 1710 1711 /* 1712 * Figure out which offset in the schedule that has most 1713 * bandwidth left over. 1714 */ 1715 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 1716 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 1717 for (bw = i = 0; i < npoll; i++) 1718 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 1719 if (bw < bestbw) { 1720 bestbw = bw; 1721 bestoffs = offs; 1722 } 1723 } 1724 DPRINTFN(1, ("uhci_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 1725 1726 upipe->iinfo->stdstart = 0; 1727 for(i = 0; i < npoll; i++) { 1728 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 1729 sqh->qh->elink = 0; 1730 sqh->qh->qh_elink = UHCI_PTR_T; 1731 sqh->pos = MOD(i * ival + bestoffs); 1732 sqh->intr_info = upipe->iinfo; 1733 } 1734 #undef MOD 1735 1736 s = splusb(); 1737 LIST_INSERT_HEAD(&sc->sc_intrhead, upipe->iinfo, list); 1738 splx(s); 1739 1740 uhci_lock_frames(sc); 1741 /* Enter QHs into the controller data structures. */ 1742 for(i = 0; i < npoll; i++) 1743 uhci_add_intr(sc, upipe->u.intr.qhs[i]->pos, 1744 upipe->u.intr.qhs[i]); 1745 uhci_unlock_frames(sc); 1746 1747 DPRINTFN(5, ("uhci_setintr: returns %p\n", upipe)); 1748 return (USBD_NORMAL_COMPLETION); 1749 } 1750 1751 /* Open a new pipe. */ 1752 usbd_status 1753 uhci_open(pipe) 1754 usbd_pipe_handle pipe; 1755 { 1756 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 1757 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1758 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1759 usbd_status r; 1760 1761 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1762 pipe, pipe->device->address, 1763 ed->bEndpointAddress, sc->sc_addr)); 1764 if (pipe->device->address == sc->sc_addr) { 1765 switch (ed->bEndpointAddress) { 1766 case USB_CONTROL_ENDPOINT: 1767 pipe->methods = &uhci_root_ctrl_methods; 1768 break; 1769 case UE_IN | UHCI_INTR_ENDPT: 1770 pipe->methods = &uhci_root_intr_methods; 1771 break; 1772 default: 1773 return (USBD_INVAL); 1774 } 1775 } else { 1776 upipe->iinfo = uhci_alloc_intr_info(sc); 1777 if (upipe->iinfo == 0) 1778 return (USBD_NOMEM); 1779 switch (ed->bmAttributes & UE_XFERTYPE) { 1780 case UE_CONTROL: 1781 pipe->methods = &uhci_device_ctrl_methods; 1782 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 1783 if (upipe->u.ctl.sqh == 0) 1784 goto bad; 1785 upipe->u.ctl.setup = uhci_alloc_std(sc); 1786 if (upipe->u.ctl.setup == 0) { 1787 uhci_free_sqh(sc, upipe->u.ctl.sqh); 1788 goto bad; 1789 } 1790 upipe->u.ctl.stat = uhci_alloc_std(sc); 1791 if (upipe->u.ctl.stat == 0) { 1792 uhci_free_sqh(sc, upipe->u.ctl.sqh); 1793 uhci_free_std(sc, upipe->u.ctl.setup); 1794 goto bad; 1795 } 1796 r = uhci_allocmem(sc, sizeof(uhci_dma_t), 0, 1797 &upipe->u.ctl.reqdma); 1798 if (r != USBD_NORMAL_COMPLETION) { 1799 uhci_free_sqh(sc, upipe->u.ctl.sqh); 1800 uhci_free_std(sc, upipe->u.ctl.setup); 1801 uhci_free_std(sc, upipe->u.ctl.stat); 1802 goto bad; 1803 } 1804 break; 1805 case UE_INTERRUPT: 1806 pipe->methods = &uhci_device_intr_methods; 1807 return (uhci_device_setintr(sc, upipe, ed->bInterval)); 1808 case UE_ISOCHRONOUS: 1809 printf("uhci_open: iso not implemented\n"); 1810 return (USBD_XXX); 1811 case UE_BULK: 1812 pipe->methods = &uhci_device_bulk_methods; 1813 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 1814 if (upipe->u.bulk.sqh == 0) 1815 goto bad; 1816 break; 1817 } 1818 } 1819 return (USBD_NORMAL_COMPLETION); 1820 1821 bad: 1822 uhci_free_intr_info(upipe->iinfo); 1823 return (USBD_NOMEM); 1824 } 1825 1826 /* 1827 * Data structures and routines to emulate the root hub. 1828 */ 1829 usb_device_descriptor_t uhci_devd = { 1830 USB_DEVICE_DESCRIPTOR_SIZE, 1831 UDESC_DEVICE, /* type */ 1832 {0x00, 0x01}, /* USB version */ 1833 UCLASS_HUB, /* class */ 1834 USUBCLASS_HUB, /* subclass */ 1835 0, /* protocol */ 1836 64, /* max packet */ 1837 {0},{0},{0x00,0x01}, /* device id */ 1838 1,2,0, /* string indicies */ 1839 1 /* # of configurations */ 1840 }; 1841 1842 usb_config_descriptor_t uhci_confd = { 1843 USB_CONFIG_DESCRIPTOR_SIZE, 1844 UDESC_CONFIG, 1845 {USB_CONFIG_DESCRIPTOR_SIZE + 1846 USB_INTERFACE_DESCRIPTOR_SIZE + 1847 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1848 1, 1849 1, 1850 0, 1851 UC_SELF_POWERED, 1852 0 /* max power */ 1853 }; 1854 1855 usb_interface_descriptor_t uhci_ifcd = { 1856 USB_INTERFACE_DESCRIPTOR_SIZE, 1857 UDESC_INTERFACE, 1858 0, 1859 0, 1860 1, 1861 UCLASS_HUB, 1862 USUBCLASS_HUB, 1863 0, 1864 0 1865 }; 1866 1867 usb_endpoint_descriptor_t uhci_endpd = { 1868 USB_ENDPOINT_DESCRIPTOR_SIZE, 1869 UDESC_ENDPOINT, 1870 UE_IN | UHCI_INTR_ENDPT, 1871 UE_INTERRUPT, 1872 {8}, 1873 255 1874 }; 1875 1876 usb_hub_descriptor_t uhci_hubd_piix = { 1877 USB_HUB_DESCRIPTOR_SIZE, 1878 UDESC_HUB, 1879 2, 1880 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 1881 50, /* power on to power good */ 1882 0, 1883 { 0x00 }, /* both ports are removable */ 1884 { 0x00 }, /* no ports can power down individually */ 1885 }; 1886 1887 int 1888 uhci_str(p, l, s) 1889 usb_string_descriptor_t *p; 1890 int l; 1891 char *s; 1892 { 1893 int i; 1894 1895 if (l == 0) 1896 return (0); 1897 p->bLength = 2 * strlen(s) + 2; 1898 if (l == 1) 1899 return (1); 1900 p->bDescriptorType = UDESC_STRING; 1901 l -= 2; 1902 for (i = 0; s[i] && l > 1; i++, l -= 2) 1903 USETW2(p->bString[i], 0, s[i]); 1904 return (2*i+2); 1905 } 1906 1907 /* 1908 * Simulate a hardware hub by handling all the necessary requests. 1909 */ 1910 usbd_status 1911 uhci_root_ctrl_transfer(reqh) 1912 usbd_request_handle reqh; 1913 { 1914 uhci_softc_t *sc = (uhci_softc_t *)reqh->pipe->device->bus; 1915 usb_device_request_t *req; 1916 void *buf; 1917 int port, x; 1918 int len, value, index, status, change, l, totlen = 0; 1919 usb_port_status_t ps; 1920 usbd_status r; 1921 1922 if (!reqh->isreq) 1923 panic("uhci_root_ctrl_transfer: not a request\n"); 1924 req = &reqh->request; 1925 buf = reqh->buffer; 1926 1927 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 1928 req->bmRequestType, req->bRequest)); 1929 1930 len = UGETW(req->wLength); 1931 value = UGETW(req->wValue); 1932 index = UGETW(req->wIndex); 1933 #define C(x,y) ((x) | ((y) << 8)) 1934 switch(C(req->bRequest, req->bmRequestType)) { 1935 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1936 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1937 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1938 /* 1939 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops 1940 * for the integrated root hub. 1941 */ 1942 break; 1943 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1944 if (len > 0) { 1945 *(u_int8_t *)buf = sc->sc_conf; 1946 totlen = 1; 1947 } 1948 break; 1949 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1950 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 1951 switch(value >> 8) { 1952 case UDESC_DEVICE: 1953 if ((value & 0xff) != 0) { 1954 r = USBD_IOERROR; 1955 goto ret; 1956 } 1957 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1958 memcpy(buf, &uhci_devd, l); 1959 break; 1960 case UDESC_CONFIG: 1961 if ((value & 0xff) != 0) { 1962 r = USBD_IOERROR; 1963 goto ret; 1964 } 1965 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1966 memcpy(buf, &uhci_confd, l); 1967 buf = (char *)buf + l; 1968 len -= l; 1969 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1970 totlen += l; 1971 memcpy(buf, &uhci_ifcd, l); 1972 buf = (char *)buf + l; 1973 len -= l; 1974 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1975 totlen += l; 1976 memcpy(buf, &uhci_endpd, l); 1977 break; 1978 case UDESC_STRING: 1979 if (len == 0) 1980 break; 1981 *(u_int8_t *)buf = 0; 1982 totlen = 1; 1983 switch (value & 0xff) { 1984 case 1: /* Vendor */ 1985 if (sc->sc_model == UHCI_PIIX3 || 1986 sc->sc_model == UHCI_PIIX4) 1987 totlen = uhci_str(buf, len, "Intel"); 1988 break; 1989 case 2: /* Product */ 1990 if (sc->sc_model == UHCI_PIIX3) 1991 totlen = uhci_str(buf, len, 1992 "PIIX3 root hub"); 1993 if (sc->sc_model == UHCI_PIIX4) 1994 totlen = uhci_str(buf, len, 1995 "PIIX4 root hub"); 1996 break; 1997 } 1998 break; 1999 default: 2000 r = USBD_IOERROR; 2001 goto ret; 2002 } 2003 break; 2004 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2005 if (len > 0) { 2006 *(u_int8_t *)buf = 0; 2007 totlen = 1; 2008 } 2009 break; 2010 case C(UR_GET_STATUS, UT_READ_DEVICE): 2011 if (len > 1) { 2012 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2013 totlen = 2; 2014 } 2015 break; 2016 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2017 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2018 if (len > 1) { 2019 USETW(((usb_status_t *)buf)->wStatus, 0); 2020 totlen = 2; 2021 } 2022 break; 2023 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2024 if (value >= USB_MAX_DEVICES) { 2025 r = USBD_IOERROR; 2026 goto ret; 2027 } 2028 sc->sc_addr = value; 2029 break; 2030 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2031 if (value != 0 && value != 1) { 2032 r = USBD_IOERROR; 2033 goto ret; 2034 } 2035 sc->sc_conf = value; 2036 break; 2037 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2038 break; 2039 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2040 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2041 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2042 r = USBD_IOERROR; 2043 goto ret; 2044 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2045 break; 2046 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2047 break; 2048 /* Hub requests */ 2049 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2050 break; 2051 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2052 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n", 2053 index, value)); 2054 if (index == 1) 2055 port = UHCI_PORTSC1; 2056 else if (index == 2) 2057 port = UHCI_PORTSC2; 2058 else { 2059 r = USBD_IOERROR; 2060 goto ret; 2061 } 2062 switch(value) { 2063 case UHF_PORT_ENABLE: 2064 x = UREAD2(sc, port); 2065 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2066 break; 2067 case UHF_PORT_SUSPEND: 2068 x = UREAD2(sc, port); 2069 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 2070 break; 2071 case UHF_PORT_RESET: 2072 x = UREAD2(sc, port); 2073 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2074 break; 2075 case UHF_C_PORT_CONNECTION: 2076 x = UREAD2(sc, port); 2077 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2078 break; 2079 case UHF_C_PORT_ENABLE: 2080 x = UREAD2(sc, port); 2081 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2082 break; 2083 case UHF_C_PORT_OVER_CURRENT: 2084 x = UREAD2(sc, port); 2085 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2086 break; 2087 case UHF_C_PORT_RESET: 2088 sc->sc_isreset = 0; 2089 r = USBD_NORMAL_COMPLETION; 2090 goto ret; 2091 case UHF_PORT_CONNECTION: 2092 case UHF_PORT_OVER_CURRENT: 2093 case UHF_PORT_POWER: 2094 case UHF_PORT_LOW_SPEED: 2095 case UHF_C_PORT_SUSPEND: 2096 default: 2097 r = USBD_IOERROR; 2098 goto ret; 2099 } 2100 break; 2101 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2102 if (index == 1) 2103 port = UHCI_PORTSC1; 2104 else if (index == 2) 2105 port = UHCI_PORTSC2; 2106 else { 2107 r = USBD_IOERROR; 2108 goto ret; 2109 } 2110 if (len > 0) { 2111 *(u_int8_t *)buf = 2112 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2113 UHCI_PORTSC_LS_SHIFT; 2114 totlen = 1; 2115 } 2116 break; 2117 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2118 if (value != 0) { 2119 r = USBD_IOERROR; 2120 goto ret; 2121 } 2122 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 2123 totlen = l; 2124 memcpy(buf, &uhci_hubd_piix, l); 2125 break; 2126 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2127 if (len != 4) { 2128 r = USBD_IOERROR; 2129 goto ret; 2130 } 2131 memset(buf, 0, len); 2132 totlen = len; 2133 break; 2134 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2135 if (index == 1) 2136 port = UHCI_PORTSC1; 2137 else if (index == 2) 2138 port = UHCI_PORTSC2; 2139 else { 2140 r = USBD_IOERROR; 2141 goto ret; 2142 } 2143 if (len != 4) { 2144 r = USBD_IOERROR; 2145 goto ret; 2146 } 2147 x = UREAD2(sc, port); 2148 status = change = 0; 2149 if (x & UHCI_PORTSC_CCS ) 2150 status |= UPS_CURRENT_CONNECT_STATUS; 2151 if (x & UHCI_PORTSC_CSC ) 2152 change |= UPS_C_CONNECT_STATUS; 2153 if (x & UHCI_PORTSC_PE ) 2154 status |= UPS_PORT_ENABLED; 2155 if (x & UHCI_PORTSC_POEDC) 2156 change |= UPS_C_PORT_ENABLED; 2157 if (x & UHCI_PORTSC_OCI ) 2158 status |= UPS_OVERCURRENT_INDICATOR; 2159 if (x & UHCI_PORTSC_OCIC ) 2160 change |= UPS_C_OVERCURRENT_INDICATOR; 2161 if (x & UHCI_PORTSC_SUSP ) 2162 status |= UPS_SUSPEND; 2163 if (x & UHCI_PORTSC_LSDA ) 2164 status |= UPS_LOW_SPEED; 2165 status |= UPS_PORT_POWER; 2166 if (sc->sc_isreset) 2167 change |= UPS_C_PORT_RESET; 2168 USETW(ps.wPortStatus, status); 2169 USETW(ps.wPortChange, change); 2170 l = min(len, sizeof ps); 2171 memcpy(buf, &ps, l); 2172 totlen = l; 2173 break; 2174 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2175 r = USBD_IOERROR; 2176 goto ret; 2177 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2178 break; 2179 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2180 if (index == 1) 2181 port = UHCI_PORTSC1; 2182 else if (index == 2) 2183 port = UHCI_PORTSC2; 2184 else { 2185 r = USBD_IOERROR; 2186 goto ret; 2187 } 2188 switch(value) { 2189 case UHF_PORT_ENABLE: 2190 x = UREAD2(sc, port); 2191 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2192 break; 2193 case UHF_PORT_SUSPEND: 2194 x = UREAD2(sc, port); 2195 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2196 break; 2197 case UHF_PORT_RESET: 2198 x = UREAD2(sc, port); 2199 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2200 usbd_delay_ms(10); 2201 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2202 delay(100); 2203 x = UREAD2(sc, port); 2204 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2205 delay(100); 2206 DPRINTFN(3,("uhci port %d reset, status = 0x%04x\n", 2207 index, UREAD2(sc, port))); 2208 sc->sc_isreset = 1; 2209 break; 2210 case UHF_C_PORT_CONNECTION: 2211 case UHF_C_PORT_ENABLE: 2212 case UHF_C_PORT_OVER_CURRENT: 2213 case UHF_PORT_CONNECTION: 2214 case UHF_PORT_OVER_CURRENT: 2215 case UHF_PORT_POWER: 2216 case UHF_PORT_LOW_SPEED: 2217 case UHF_C_PORT_SUSPEND: 2218 case UHF_C_PORT_RESET: 2219 default: 2220 r = USBD_IOERROR; 2221 goto ret; 2222 } 2223 break; 2224 default: 2225 r = USBD_IOERROR; 2226 goto ret; 2227 } 2228 reqh->actlen = totlen; 2229 r = USBD_NORMAL_COMPLETION; 2230 ret: 2231 reqh->status = r; 2232 reqh->xfercb(reqh); 2233 return (USBD_IN_PROGRESS); 2234 } 2235 2236 /* Abort a root control request. */ 2237 void 2238 uhci_root_ctrl_abort(reqh) 2239 usbd_request_handle reqh; 2240 { 2241 } 2242 2243 /* Close the root pipe. */ 2244 void 2245 uhci_root_ctrl_close(pipe) 2246 usbd_pipe_handle pipe; 2247 { 2248 untimeout(uhci_timo, pipe->intrreqh); 2249 DPRINTF(("uhci_root_ctrl_close\n")); 2250 } 2251 2252 /* Abort a root interrupt request. */ 2253 void 2254 uhci_root_intr_abort(reqh) 2255 usbd_request_handle reqh; 2256 { 2257 untimeout(uhci_timo, reqh); 2258 } 2259 2260 /* Start a transfer on the root interrupt pipe */ 2261 usbd_status 2262 uhci_root_intr_transfer(reqh) 2263 usbd_request_handle reqh; 2264 { 2265 usbd_pipe_handle pipe = reqh->pipe; 2266 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 2267 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2268 uhci_dma_t *dmap; 2269 usbd_status r; 2270 int len; 2271 2272 DPRINTFN(3, ("uhci_root_intr_transfer: reqh=%p buf=%p len=%d flags=%d\n", 2273 reqh, reqh->buffer, reqh->length, reqh->flags)); 2274 2275 len = reqh->length; 2276 dmap = &upipe->u.intr.datadma; 2277 if (len == 0) 2278 return (USBD_INVAL); /* XXX should it be? */ 2279 2280 r = uhci_allocmem(sc, len, 0, dmap); 2281 if (r != USBD_NORMAL_COMPLETION) 2282 return (r); 2283 2284 sc->sc_ival = MS_TO_TICKS(reqh->pipe->endpoint->edesc->bInterval); 2285 timeout(uhci_timo, reqh, sc->sc_ival); 2286 return (USBD_IN_PROGRESS); 2287 } 2288 2289 /* Close the root interrupt pipe. */ 2290 void 2291 uhci_root_intr_close(pipe) 2292 usbd_pipe_handle pipe; 2293 { 2294 untimeout(uhci_timo, pipe->intrreqh); 2295 DPRINTF(("uhci_root_intr_close\n")); 2296 } 2297
Indexes created Tue Sep 23 07:09:52 GMT 2025