uhci.c revision 1.7
1 /* $NetBSD: uhci.c,v 1.7 1998/07/24 21:09:07 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Author: Lennart Augustsson <augustss (at) carlstedt.se> 8 * Carlstedt Research & Technology 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Universal Host Controller driver. 41 * Handles PIIX3 and PIIX4. 42 * 43 * Data sheets: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 44 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 45 * UHCI spec: http://www.intel.com/design/usb/uhci11d.pdf 46 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/device.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 58 #include <machine/bus.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usb_mem.h> 64 #include <dev/usb/usb_quirks.h> 65 66 #include <dev/usb/uhcireg.h> 67 #include <dev/usb/uhcivar.h> 68 69 #define MS_TO_TICKS(ms) ((ms) * hz / 1000) 70 71 struct uhci_pipe { 72 struct usbd_pipe pipe; 73 uhci_intr_info_t *iinfo; 74 int newtoggle; 75 /* Info needed for different pipe kinds. */ 76 union { 77 /* Control pipe */ 78 struct { 79 uhci_soft_qh_t *sqh; 80 usb_dma_t reqdma; 81 usb_dma_t datadma; 82 uhci_soft_td_t *setup, *stat, *xferend; 83 u_int length; 84 } ctl; 85 /* Interrupt pipe */ 86 struct { 87 usb_dma_t datadma; 88 int npoll; 89 uhci_soft_qh_t **qhs; 90 } intr; 91 /* Bulk pipe */ 92 struct { 93 uhci_soft_qh_t *sqh; 94 usb_dma_t datadma; 95 u_int length; 96 int isread; 97 } bulk; 98 } u; 99 }; 100 101 /* 102 * The uhci_intr_info free list can be global since they contain 103 * no dma specific data. The other free lists do. 104 */ 105 int uhci_global_init_done = 0; 106 LIST_HEAD(, uhci_intr_info) uhci_ii_free; 107 108 void uhci_busreset __P((uhci_softc_t *)); 109 void uhci_run __P((uhci_softc_t *, int run)); 110 uhci_soft_td_t *uhci_alloc_std __P((uhci_softc_t *)); 111 void uhci_free_std __P((uhci_softc_t *, uhci_soft_td_t *)); 112 uhci_soft_qh_t *uhci_alloc_sqh __P((uhci_softc_t *)); 113 void uhci_free_sqh __P((uhci_softc_t *, uhci_soft_qh_t *)); 114 uhci_intr_info_t *uhci_alloc_intr_info __P((uhci_softc_t *)); 115 void uhci_free_intr_info __P((uhci_intr_info_t *ii)); 116 void uhci_enter_ctl_q __P((uhci_softc_t *, uhci_soft_qh_t *, 117 uhci_intr_info_t *)); 118 void uhci_exit_ctl_q __P((uhci_softc_t *, uhci_soft_qh_t *)); 119 120 void uhci_free_std_chain __P((uhci_softc_t *, 121 uhci_soft_td_t *, uhci_soft_td_t *)); 122 usbd_status uhci_alloc_std_chain __P((struct uhci_pipe *, uhci_softc_t *, 123 int, int, usb_dma_t *, 124 uhci_soft_td_t **, 125 uhci_soft_td_t **)); 126 void uhci_timo __P((void *)); 127 void uhci_waitintr __P((uhci_softc_t *, usbd_request_handle)); 128 void uhci_check_intr __P((uhci_softc_t *, uhci_intr_info_t *)); 129 void uhci_ii_done __P((uhci_intr_info_t *, int)); 130 void uhci_timeout __P((void *)); 131 void uhci_wakeup_ctrl __P((void *, int, int, void *, int)); 132 void uhci_lock_frames __P((uhci_softc_t *)); 133 void uhci_unlock_frames __P((uhci_softc_t *)); 134 void uhci_add_ctrl __P((uhci_softc_t *, uhci_soft_qh_t *)); 135 void uhci_add_bulk __P((uhci_softc_t *, uhci_soft_qh_t *)); 136 void uhci_remove_ctrl __P((uhci_softc_t *, uhci_soft_qh_t *)); 137 void uhci_remove_bulk __P((uhci_softc_t *, uhci_soft_qh_t *)); 138 int uhci_str __P((usb_string_descriptor_t *, int, char *)); 139 140 void uhci_device_close __P((struct uhci_pipe *)); 141 142 void uhci_wakeup_cb __P((usbd_request_handle reqh)); 143 144 usbd_status uhci_device_ctrl_transfer __P((usbd_request_handle)); 145 void uhci_device_ctrl_abort __P((usbd_request_handle)); 146 void uhci_device_ctrl_close __P((usbd_pipe_handle)); 147 usbd_status uhci_device_intr_transfer __P((usbd_request_handle)); 148 void uhci_device_intr_abort __P((usbd_request_handle)); 149 void uhci_device_intr_close __P((usbd_pipe_handle)); 150 usbd_status uhci_device_bulk_transfer __P((usbd_request_handle)); 151 void uhci_device_bulk_abort __P((usbd_request_handle)); 152 void uhci_device_bulk_close __P((usbd_pipe_handle)); 153 154 usbd_status uhci_root_ctrl_transfer __P((usbd_request_handle)); 155 void uhci_root_ctrl_abort __P((usbd_request_handle)); 156 void uhci_root_ctrl_close __P((usbd_pipe_handle)); 157 usbd_status uhci_root_intr_transfer __P((usbd_request_handle)); 158 void uhci_root_intr_abort __P((usbd_request_handle)); 159 void uhci_root_intr_close __P((usbd_pipe_handle)); 160 161 usbd_status uhci_open __P((usbd_pipe_handle)); 162 163 usbd_status uhci_device_request __P((usbd_request_handle reqh)); 164 void uhci_ctrl_done __P((uhci_intr_info_t *ii)); 165 void uhci_bulk_done __P((uhci_intr_info_t *ii)); 166 167 void uhci_add_intr __P((uhci_softc_t *, int, uhci_soft_qh_t *)); 168 void uhci_remove_intr __P((uhci_softc_t *, int, uhci_soft_qh_t *)); 169 usbd_status uhci_device_setintr __P((uhci_softc_t *sc, 170 struct uhci_pipe *pipe, int ival)); 171 void uhci_intr_done __P((uhci_intr_info_t *ii)); 172 173 #ifdef USB_DEBUG 174 static void uhci_dumpregs __P((uhci_softc_t *)); 175 void uhci_dump_tds __P((uhci_soft_td_t *)); 176 void uhci_dump_qh __P((uhci_soft_qh_t *)); 177 void uhci_dump __P((void)); 178 void uhci_dump_td __P((uhci_soft_td_t *)); 179 #endif 180 181 #define UWRITE2(sc, r, x) bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)) 182 #define UWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 183 #define UREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 184 #define UREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 185 186 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 187 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 188 189 #define UHCI_RESET_TIMEOUT 100 /* reset timeout */ 190 #define UHCI_CTRL_TIMEOUT 500 /* control transaction timeout */ 191 #define UHCI_ISO_DELAY 50 /* delay of start of iso */ 192 193 #define UHCI_CURFRAME(sc) (UREAD2(sc, UHCI_FRNUM) & UHCI_FRNUM_MASK) 194 195 #define UHCI_INTR_ENDPT 1 196 197 struct usbd_methods uhci_root_ctrl_methods = { 198 uhci_root_ctrl_transfer, 199 uhci_root_ctrl_abort, 200 uhci_root_ctrl_close, 201 }; 202 203 struct usbd_methods uhci_root_intr_methods = { 204 uhci_root_intr_transfer, 205 uhci_root_intr_abort, 206 uhci_root_intr_close, 207 }; 208 209 struct usbd_methods uhci_device_ctrl_methods = { 210 uhci_device_ctrl_transfer, 211 uhci_device_ctrl_abort, 212 uhci_device_ctrl_close, 213 }; 214 215 struct usbd_methods uhci_device_intr_methods = { 216 uhci_device_intr_transfer, 217 uhci_device_intr_abort, 218 uhci_device_intr_close, 219 }; 220 221 struct usbd_methods uhci_device_bulk_methods = { 222 uhci_device_bulk_transfer, 223 uhci_device_bulk_abort, 224 uhci_device_bulk_close, 225 }; 226 227 void 228 uhci_busreset(sc) 229 uhci_softc_t *sc; 230 { 231 UHCICMD(sc, UHCI_CMD_GRESET); /* global reset */ 232 usbd_delay_ms(USB_RESET_DELAY); /* wait at least 10ms */ 233 UHCICMD(sc, 0); /* do nothing */ 234 } 235 236 usbd_status 237 uhci_init(sc) 238 uhci_softc_t *sc; 239 { 240 usbd_status r; 241 int i, j; 242 uhci_soft_qh_t *csqh, *bsqh, *sqh; 243 uhci_soft_td_t *std; 244 usb_dma_t dma; 245 246 DPRINTFN(1,("uhci_init: start\n")); 247 248 if (!uhci_global_init_done) { 249 uhci_global_init_done = 1; 250 LIST_INIT(&uhci_ii_free); 251 } 252 253 #if defined(USB_DEBUG) 254 if (uhcidebug > 2) 255 uhci_dumpregs(sc); 256 #endif 257 258 uhci_run(sc, 0); /* stop the controller */ 259 UWRITE2(sc, UHCI_INTR, 0); /* disable interrupts */ 260 261 /* Allocate and initialize real frame array. */ 262 r = usb_allocmem(sc->sc_dmatag, 263 UHCI_FRAMELIST_COUNT * sizeof(uhci_physaddr_t), 264 UHCI_FRAMELIST_ALIGN, &dma); 265 if (r != USBD_NORMAL_COMPLETION) 266 return (r); 267 sc->sc_pframes = KERNADDR(&dma); 268 UWRITE2(sc, UHCI_FRNUM, 0); /* set frame number to 0 */ 269 UWRITE4(sc, UHCI_FLBASEADDR, DMAADDR(&dma)); /* set frame list */ 270 271 uhci_busreset(sc); 272 273 /* Allocate the dummy QH where bulk traffic will be queued. */ 274 bsqh = uhci_alloc_sqh(sc); 275 if (!bsqh) 276 return (USBD_NOMEM); 277 bsqh->qh->qh_hlink = UHCI_PTR_T; /* end of QH chain */ 278 bsqh->qh->qh_elink = UHCI_PTR_T; 279 sc->sc_bulk_start = sc->sc_bulk_end = bsqh; 280 281 /* Allocate the dummy QH where control traffic will be queued. */ 282 csqh = uhci_alloc_sqh(sc); 283 if (!csqh) 284 return (USBD_NOMEM); 285 csqh->qh->hlink = bsqh; 286 csqh->qh->qh_hlink = bsqh->physaddr | UHCI_PTR_Q; 287 csqh->qh->qh_elink = UHCI_PTR_T; 288 sc->sc_ctl_start = sc->sc_ctl_end = csqh; 289 290 /* 291 * Make all (virtual) frame list pointers point to the interrupt 292 * queue heads and the interrupt queue heads at the control 293 * queue head and point the physical frame list to the virtual. 294 */ 295 for(i = 0; i < UHCI_VFRAMELIST_COUNT; i++) { 296 std = uhci_alloc_std(sc); 297 sqh = uhci_alloc_sqh(sc); 298 if (!std || !sqh) 299 return (ENOMEM); 300 std->td->link.sqh = sqh; 301 std->td->td_link = sqh->physaddr | UHCI_PTR_Q; 302 std->td->td_status = UHCI_TD_IOS; /* iso, inactive */ 303 std->td->td_token = 0; 304 std->td->td_buffer = 0; 305 sqh->qh->hlink = csqh; 306 sqh->qh->qh_hlink = csqh->physaddr | UHCI_PTR_Q; 307 sqh->qh->elink = 0; 308 sqh->qh->qh_elink = UHCI_PTR_T; 309 sc->sc_vframes[i].htd = std; 310 sc->sc_vframes[i].etd = std; 311 sc->sc_vframes[i].hqh = sqh; 312 sc->sc_vframes[i].eqh = sqh; 313 for (j = i; 314 j < UHCI_FRAMELIST_COUNT; 315 j += UHCI_VFRAMELIST_COUNT) 316 sc->sc_pframes[j] = std->physaddr; 317 } 318 319 LIST_INIT(&sc->sc_intrhead); 320 321 /* Set up the bus struct. */ 322 sc->sc_bus.open_pipe = uhci_open; 323 sc->sc_bus.pipe_size = sizeof(struct uhci_pipe); 324 325 DPRINTFN(1,("uhci_init: enabling\n")); 326 UWRITE2(sc, UHCI_INTR, UHCI_INTR_TOCRCIE | UHCI_INTR_RIE | 327 UHCI_INTR_IOCE | UHCI_INTR_SPIE); /* enable interrupts */ 328 329 uhci_run(sc, 1); /* and here we go... */ 330 return (USBD_NORMAL_COMPLETION); 331 } 332 333 #ifdef USB_DEBUG 334 static void 335 uhci_dumpregs(sc) 336 uhci_softc_t *sc; 337 { 338 printf("%s: regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 339 sc->sc_bus.bdev.dv_xname, 340 UREAD2(sc, UHCI_CMD), 341 UREAD2(sc, UHCI_STS), 342 UREAD2(sc, UHCI_INTR), 343 UREAD2(sc, UHCI_FRNUM), 344 UREAD2(sc, UHCI_FLBASEADDR), 345 UREAD2(sc, UHCI_SOF), 346 UREAD2(sc, UHCI_PORTSC1), 347 UREAD2(sc, UHCI_PORTSC2)); 348 } 349 350 int uhci_longtd = 1; 351 352 void 353 uhci_dump_td(p) 354 uhci_soft_td_t *p; 355 { 356 printf("TD(%p) at %08lx = 0x%08lx 0x%08lx 0x%08lx 0x%08lx\n", 357 p, (long)p->physaddr, 358 (long)p->td->td_link, 359 (long)p->td->td_status, 360 (long)p->td->td_token, 361 (long)p->td->td_buffer); 362 if (uhci_longtd) 363 printf(" %b %b,errcnt=%d,actlen=%d pid=%02x,addr=%d,endpt=%d,D=%d,maxlen=%d\n", 364 (long)p->td->td_link, 365 "\20\1T\2Q\3VF", 366 (long)p->td->td_status, 367 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27STALLED\30ACTIVE\31IOC\32ISO\33LS\36SPD", 368 UHCI_TD_GET_ERRCNT(p->td->td_status), 369 UHCI_TD_GET_ACTLEN(p->td->td_status), 370 UHCI_TD_GET_PID(p->td->td_token), 371 UHCI_TD_GET_DEVADDR(p->td->td_token), 372 UHCI_TD_GET_ENDPT(p->td->td_token), 373 UHCI_TD_GET_DT(p->td->td_token), 374 UHCI_TD_GET_MAXLEN(p->td->td_token)); 375 376 } 377 378 void 379 uhci_dump_qh(p) 380 uhci_soft_qh_t *p; 381 { 382 printf("QH(%p) at %08x: hlink=%08x elink=%08x\n", p, (int)p->physaddr, 383 p->qh->qh_hlink, p->qh->qh_elink); 384 } 385 386 #if 0 387 void 388 uhci_dump() 389 { 390 uhci_softc_t *sc = uhci; 391 392 uhci_dumpregs(sc); 393 printf("intrs=%d\n", sc->sc_intrs); 394 printf("framelist[i].link = %08x\n", sc->sc_framelist[0].link); 395 uhci_dump_qh(sc->sc_ctl_start->qh->hlink); 396 } 397 #endif 398 399 void 400 uhci_dump_tds(std) 401 uhci_soft_td_t *std; 402 { 403 uhci_soft_td_t *p; 404 405 for(p = std; p; p = p->td->link.std) 406 uhci_dump_td(p); 407 } 408 #endif 409 410 /* 411 * This routine is executed periodically and simulates interrupts 412 * from the root controller interrupt pipe for port status change. 413 */ 414 void 415 uhci_timo(addr) 416 void *addr; 417 { 418 usbd_request_handle reqh = addr; 419 usbd_pipe_handle pipe = reqh->pipe; 420 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 421 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 422 int s; 423 u_char *p; 424 425 DPRINTFN(15, ("uhci_timo\n")); 426 427 p = KERNADDR(&upipe->u.intr.datadma); 428 p[0] = 0; 429 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 430 p[0] |= 1<<1; 431 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC|UHCI_PORTSC_OCIC)) 432 p[0] |= 1<<2; 433 if (p[0] != 0) { 434 reqh->actlen = 1; 435 reqh->status = USBD_NORMAL_COMPLETION; 436 s = splusb(); 437 reqh->xfercb(reqh); 438 splx(s); 439 } 440 if (reqh->pipe->intrreqh == reqh) { 441 timeout(uhci_timo, addr, sc->sc_ival); 442 } else { 443 usb_freemem(sc->sc_dmatag, &upipe->u.intr.datadma); 444 } 445 } 446 447 448 void 449 uhci_lock_frames(sc) 450 uhci_softc_t *sc; 451 { 452 int s = splusb(); 453 while (sc->sc_vflock) { 454 sc->sc_vflock |= UHCI_WANT_LOCK; 455 tsleep(&sc->sc_vflock, PRIBIO, "uhcqhl", 0); 456 } 457 sc->sc_vflock = UHCI_HAS_LOCK; 458 splx(s); 459 } 460 461 void 462 uhci_unlock_frames(sc) 463 uhci_softc_t *sc; 464 { 465 int s = splusb(); 466 sc->sc_vflock &= ~UHCI_HAS_LOCK; 467 if (sc->sc_vflock & UHCI_WANT_LOCK) 468 wakeup(&sc->sc_vflock); 469 splx(s); 470 } 471 472 /* 473 * Allocate an interrupt information struct. A free list is kept 474 * for fast allocation. 475 */ 476 uhci_intr_info_t * 477 uhci_alloc_intr_info(sc) 478 uhci_softc_t *sc; 479 { 480 uhci_intr_info_t *ii; 481 482 ii = LIST_FIRST(&uhci_ii_free); 483 if (ii) 484 LIST_REMOVE(ii, list); 485 else { 486 ii = malloc(sizeof(uhci_intr_info_t), M_USBDEV, M_NOWAIT); 487 } 488 ii->sc = sc; 489 return ii; 490 } 491 492 void 493 uhci_free_intr_info(ii) 494 uhci_intr_info_t *ii; 495 { 496 LIST_INSERT_HEAD(&uhci_ii_free, ii, list); /* and put on free list */ 497 } 498 499 /* Add control QH, called at splusb(). */ 500 void 501 uhci_add_ctrl(sc, sqh) 502 uhci_softc_t *sc; 503 uhci_soft_qh_t *sqh; 504 { 505 uhci_qh_t *eqh; 506 507 DPRINTFN(10, ("uhci_add_ctrl: sqh=%p\n", sqh)); 508 eqh = sc->sc_ctl_end->qh; 509 sqh->qh->hlink = eqh->hlink; 510 sqh->qh->qh_hlink = eqh->qh_hlink; 511 eqh->hlink = sqh; 512 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 513 sc->sc_ctl_end = sqh; 514 } 515 516 /* Remove control QH, called at splusb(). */ 517 void 518 uhci_remove_ctrl(sc, sqh) 519 uhci_softc_t *sc; 520 uhci_soft_qh_t *sqh; 521 { 522 uhci_soft_qh_t *pqh; 523 524 DPRINTFN(10, ("uhci_remove_ctrl: sqh=%p\n", sqh)); 525 for (pqh = sc->sc_ctl_start; pqh->qh->hlink != sqh; pqh=pqh->qh->hlink) 526 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 527 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 528 printf("uhci_remove_ctrl: QH not found\n"); 529 return; 530 } 531 #else 532 ; 533 #endif 534 pqh->qh->hlink = sqh->qh->hlink; 535 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 536 if (sc->sc_ctl_end == sqh) 537 sc->sc_ctl_end = pqh; 538 } 539 540 /* Add bulk QH, called at splusb(). */ 541 void 542 uhci_add_bulk(sc, sqh) 543 uhci_softc_t *sc; 544 uhci_soft_qh_t *sqh; 545 { 546 uhci_qh_t *eqh; 547 548 DPRINTFN(10, ("uhci_add_bulk: sqh=%p\n", sqh)); 549 eqh = sc->sc_bulk_end->qh; 550 sqh->qh->hlink = eqh->hlink; 551 sqh->qh->qh_hlink = eqh->qh_hlink; 552 eqh->hlink = sqh; 553 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 554 sc->sc_bulk_end = sqh; 555 } 556 557 /* Remove bulk QH, called at splusb(). */ 558 void 559 uhci_remove_bulk(sc, sqh) 560 uhci_softc_t *sc; 561 uhci_soft_qh_t *sqh; 562 { 563 uhci_soft_qh_t *pqh; 564 565 DPRINTFN(10, ("uhci_remove_bulk: sqh=%p\n", sqh)); 566 for (pqh = sc->sc_bulk_start; pqh->qh->hlink != sqh; pqh=pqh->qh->hlink) 567 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 568 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 569 printf("uhci_remove_bulk: QH not found\n"); 570 return; 571 } 572 #else 573 ; 574 #endif 575 pqh->qh->hlink = sqh->qh->hlink; 576 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 577 if (sc->sc_bulk_end == sqh) 578 sc->sc_bulk_end = pqh; 579 } 580 581 int 582 uhci_intr(p) 583 void *p; 584 { 585 uhci_softc_t *sc = p; 586 int status, ret; 587 uhci_intr_info_t *ii; 588 589 sc->sc_intrs++; 590 #if defined(USB_DEBUG) 591 if (uhcidebug > 9) { 592 DPRINTF(("uhci_intr %s, %p\n", sc->sc_bus.bdev.dv_xname, sc)); 593 uhci_dumpregs(sc); 594 } 595 #endif 596 status = UREAD2(sc, UHCI_STS); 597 ret = 0; 598 if (status & UHCI_STS_USBINT) { 599 UWRITE2(sc, UHCI_STS, UHCI_STS_USBINT); /* acknowledge */ 600 ret = 1; 601 } 602 if (status & UHCI_STS_USBEI) { 603 UWRITE2(sc, UHCI_STS, UHCI_STS_USBEI); /* acknowledge */ 604 ret = 1; 605 } 606 if (status & UHCI_STS_RD) { 607 UWRITE2(sc, UHCI_STS, UHCI_STS_RD); /* acknowledge */ 608 printf("%s: resume detect\n", sc->sc_bus.bdev.dv_xname); 609 ret = 1; 610 } 611 if (status & UHCI_STS_HSE) { 612 UWRITE2(sc, UHCI_STS, UHCI_STS_HSE); /* acknowledge */ 613 printf("%s: Host System Error\n", sc->sc_bus.bdev.dv_xname); 614 ret = 1; 615 } 616 if (status & UHCI_STS_HCPE) { 617 UWRITE2(sc, UHCI_STS, UHCI_STS_HCPE); /* acknowledge */ 618 printf("%s: Host System Error\n", sc->sc_bus.bdev.dv_xname); 619 ret = 1; 620 } 621 if (status & UHCI_STS_HCH) { 622 printf("%s: controller halted\n", sc->sc_bus.bdev.dv_xname); 623 } 624 if (!ret) 625 return 0; 626 627 /* 628 * Interrupts on UHCI really suck. When the host controller 629 * interrupts because a transfer is completed there is no 630 * way of knowing which transfer it was. You can scan down 631 * the TDs and QHs of the previous frame to limit the search, 632 * but that assumes that the interrupt was not delayed by more 633 * than 1 ms, which may not always be true (e.g. after debug 634 * output on a slow console). 635 * We scan all interrupt descriptors to see if any have 636 * completed. 637 */ 638 for (ii = LIST_FIRST(&sc->sc_intrhead); ii; ii = LIST_NEXT(ii, list)) 639 uhci_check_intr(sc, ii); 640 641 DPRINTFN(10, ("uhci_intr: exit\n")); 642 return 1; 643 } 644 645 /* Check for an interrupt. */ 646 void 647 uhci_check_intr(sc, ii) 648 uhci_softc_t *sc; 649 uhci_intr_info_t *ii; 650 { 651 struct uhci_pipe *upipe; 652 uhci_soft_td_t *std, *lstd; 653 654 DPRINTFN(15, ("uhci_check_intr: ii=%p\n", ii)); 655 #ifdef DIAGNOSTIC 656 if (!ii) { 657 printf("uhci_check_intr: no ii? %p\n", ii); 658 return; 659 } 660 #endif 661 if (!ii->stdstart) 662 return; 663 lstd = ii->stdend; 664 #ifdef DIAGNOSTIC 665 if (!lstd) { 666 printf("uhci_check_intr: std==0\n"); 667 return; 668 } 669 #endif 670 /* If the last TD is still active the whole transfer probably is. */ 671 if (lstd->td->td_status & UHCI_TD_ACTIVE) { 672 DPRINTFN(15, ("uhci_check_intr: active ii=%p\n", ii)); 673 for (std = ii->stdstart; std != lstd; std = std->td->link.std) 674 if (std->td->td_status & UHCI_TD_STALLED) 675 goto done; 676 DPRINTFN(15, ("uhci_check_intr: ii=%p still active\n", ii)); 677 return; 678 } 679 done: 680 upipe = (struct uhci_pipe *)ii->reqh->pipe; 681 upipe->pipe.endpoint->toggle = upipe->newtoggle; 682 uhci_ii_done(ii, 0); 683 untimeout(uhci_timeout, ii); 684 } 685 686 void 687 uhci_ii_done(ii, timo) 688 uhci_intr_info_t *ii; 689 int timo; 690 { 691 usbd_request_handle reqh = ii->reqh; 692 uhci_soft_td_t *std; 693 u_int32_t tst; 694 int len, status; 695 696 DPRINTFN(10, ("uhci_ii_done: ii=%p ready %d\n", ii, timo)); 697 698 #ifdef DIAGNOSTIC 699 { 700 int s = splhigh(); 701 if (ii->isdone) { 702 printf("uhci_ii_done: is done!\n"); 703 splx(s); 704 return; 705 } 706 ii->isdone = 1; 707 splx(s); 708 } 709 #endif 710 711 /* The transfer is done, compute length and status. */ 712 for (len = status = 0, std = ii->stdstart; 713 std != 0; 714 std = std->td->link.std) { 715 tst = std->td->td_status; 716 status |= tst; 717 #ifdef USB_DEBUG 718 if ((tst & UHCI_TD_ERROR) && uhcidebug) { 719 printf("uhci_intr: intr error TD:\n"); 720 uhci_dump_td(std); 721 } 722 #endif 723 if (UHCI_TD_GET_PID(std->td->td_token) != UHCI_TD_PID_SETUP) 724 len += UHCI_TD_GET_ACTLEN(tst); 725 } 726 status &= UHCI_TD_ERROR; 727 DPRINTFN(10, ("uhci_check_intr: len=%d, status=0x%x\n", len, status)); 728 if (status != 0) { 729 DPRINTFN(-1+(status==UHCI_TD_STALLED), 730 ("uhci_intr: error, status 0x%b\n", (long)status, 731 "\20\22BITSTUFF\23CRCTO\24NAK\25BABBLE\26DBUFFER\27STALLED\30ACTIVE")); 732 if (status == UHCI_TD_STALLED) 733 reqh->status = USBD_STALLED; 734 else 735 reqh->status = USBD_IOERROR; /* more info XXX */ 736 reqh->actlen = 0; 737 } else { 738 reqh->status = USBD_NORMAL_COMPLETION; 739 reqh->actlen = len; 740 } 741 if (timo) { 742 /* We got a timeout. Make sure transaction is not active. */ 743 reqh->status = USBD_TIMEOUT; 744 for (std = ii->stdstart; std != 0; std = std->td->link.std) 745 std->td->td_status &= ~UHCI_TD_ACTIVE; 746 /* XXX should we wait 1 ms */ 747 } 748 DPRINTFN(5, ("uhci_intr: calling handler ii=%p\n", ii)); 749 750 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 751 case UE_CONTROL: 752 uhci_ctrl_done(ii); 753 break; 754 case UE_ISOCHRONOUS: 755 printf("uhci_ii_done: ISO??\n"); 756 break; 757 case UE_BULK: 758 uhci_bulk_done(ii); 759 break; 760 case UE_INTERRUPT: 761 uhci_intr_done(ii); 762 break; 763 } 764 765 /* And finally execute callback. */ 766 reqh->xfercb(reqh); 767 } 768 769 void 770 uhci_timeout(addr) 771 void *addr; 772 { 773 uhci_intr_info_t *ii = addr; 774 int s; 775 776 DPRINTF(("uhci_timeout: ii=%p\n", ii)); 777 s = splusb(); 778 uhci_ii_done(ii, 1); 779 splx(s); 780 } 781 782 /* 783 * Wait here until controller claims to have an interrupt. 784 * Then call uhci_intr and return. Use timeout to avoid waiting 785 * too long. 786 */ 787 void 788 uhci_waitintr(sc, reqh) 789 uhci_softc_t *sc; 790 usbd_request_handle reqh; 791 { 792 int timo = reqh->timeout; 793 int usecs; 794 795 reqh->status = USBD_IN_PROGRESS; 796 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 797 delay(1000); 798 DPRINTFN(10,("uhci_waitintr: 0x%04x\n", UREAD2(sc, UHCI_STS))); 799 if (UREAD2(sc, UHCI_STS) & UHCI_STS_USBINT) { 800 uhci_intr(sc); 801 if (reqh->status != USBD_IN_PROGRESS) 802 return; 803 } 804 } 805 reqh->status = USBD_TIMEOUT; 806 reqh->xfercb(reqh); 807 } 808 809 #if 0 810 void 811 uhci_reset(p) 812 void *p; 813 { 814 uhci_softc_t *sc = p; 815 int n; 816 817 UHCICMD(sc, UHCI_CMD_HCRESET); 818 /* The reset bit goes low when the controller is done. */ 819 for (n = 0; n < UHCI_RESET_TIMEOUT && 820 (UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET); n++) 821 delay(100); 822 if (n >= UHCI_RESET_TIMEOUT) 823 printf("%s: controller did not reset\n", sc->sc_bus.bdev.dv_xname); 824 } 825 #endif 826 827 void 828 uhci_run(sc, run) 829 uhci_softc_t *sc; 830 int run; 831 { 832 int s, n, running; 833 834 run = run != 0; 835 s = splusb(); /* XXX really? */ 836 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 837 if (run == running) { 838 splx(s); 839 return; 840 } 841 UWRITE2(sc, UHCI_CMD, run ? UHCI_CMD_RS : 0); 842 for(n = 0; n < 100; n++) { 843 running = !(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH); 844 /* return when we've entered the state we want */ 845 if (run == running) { 846 splx(s); 847 return; 848 } 849 } 850 splx(s); 851 printf("%s: cannot %s\n", sc->sc_bus.bdev.dv_xname, run ? "start" : "stop"); 852 } 853 854 /* 855 * Memory management routines. 856 * uhci_alloc_std allocates TDs 857 * uhci_alloc_sqh allocates QHs 858 * These two routines do their own free list management, 859 * partly for speed, partly because allocating DMAable memory 860 * has page size granularaity so much memory would be wasted if 861 * only one TD/QH (32 bytes) was placed in each alloacted chunk. 862 */ 863 864 uhci_soft_td_t * 865 uhci_alloc_std(sc) 866 uhci_softc_t *sc; 867 { 868 uhci_soft_td_t *std; 869 usbd_status r; 870 int i; 871 usb_dma_t dma; 872 873 if (!sc->sc_freetds) { 874 DPRINTFN(2,("uhci_alloc_std: allocating chunk\n")); 875 std = malloc(sizeof(uhci_soft_td_t) * UHCI_TD_CHUNK, 876 M_USBDEV, M_NOWAIT); 877 if (!std) 878 return 0; 879 r = usb_allocmem(sc->sc_dmatag, UHCI_TD_SIZE * UHCI_TD_CHUNK, 880 UHCI_TD_ALIGN, &dma); 881 if (r != USBD_NORMAL_COMPLETION) { 882 free(std, M_USBDEV); 883 return 0; 884 } 885 for(i = 0; i < UHCI_TD_CHUNK; i++, std++) { 886 std->physaddr = DMAADDR(&dma) + 887 i * UHCI_TD_SIZE; 888 std->td = (uhci_td_t *) 889 ((char *)KERNADDR(&dma) + i * UHCI_TD_SIZE); 890 std->td->link.std = sc->sc_freetds; 891 sc->sc_freetds = std; 892 } 893 } 894 std = sc->sc_freetds; 895 sc->sc_freetds = std->td->link.std; 896 memset(std->td, 0, UHCI_TD_SIZE); 897 return std; 898 } 899 900 void 901 uhci_free_std(sc, std) 902 uhci_softc_t *sc; 903 uhci_soft_td_t *std; 904 { 905 #ifdef DIAGNOSTIC 906 #define TD_IS_FREE 0x12345678 907 if (std->td->td_token == TD_IS_FREE) { 908 printf("uhci_free_std: freeing free TD %p\n", std); 909 return; 910 } 911 std->td->td_token = TD_IS_FREE; 912 #endif 913 std->td->link.std = sc->sc_freetds; 914 sc->sc_freetds = std; 915 } 916 917 uhci_soft_qh_t * 918 uhci_alloc_sqh(sc) 919 uhci_softc_t *sc; 920 { 921 uhci_soft_qh_t *sqh; 922 usbd_status r; 923 int i, offs; 924 usb_dma_t dma; 925 926 if (!sc->sc_freeqhs) { 927 DPRINTFN(2, ("uhci_alloc_sqh: allocating chunk\n")); 928 sqh = malloc(sizeof(uhci_soft_qh_t) * UHCI_QH_CHUNK, 929 M_USBDEV, M_NOWAIT); 930 if (!sqh) 931 return 0; 932 r = usb_allocmem(sc->sc_dmatag, UHCI_QH_SIZE * UHCI_QH_CHUNK, 933 UHCI_QH_ALIGN, &dma); 934 if (r != USBD_NORMAL_COMPLETION) { 935 free(sqh, M_USBDEV); 936 return 0; 937 } 938 for(i = 0; i < UHCI_QH_CHUNK; i++, sqh++) { 939 offs = i * UHCI_QH_SIZE; 940 sqh->physaddr = DMAADDR(&dma) + offs; 941 sqh->qh = (uhci_qh_t *) 942 ((char *)KERNADDR(&dma) + offs); 943 sqh->qh->hlink = sc->sc_freeqhs; 944 sc->sc_freeqhs = sqh; 945 } 946 } 947 sqh = sc->sc_freeqhs; 948 sc->sc_freeqhs = sqh->qh->hlink; 949 memset(sqh->qh, 0, UHCI_QH_SIZE); 950 return sqh; 951 } 952 953 void 954 uhci_free_sqh(sc, sqh) 955 uhci_softc_t *sc; 956 uhci_soft_qh_t *sqh; 957 { 958 sqh->qh->hlink = sc->sc_freeqhs; 959 sc->sc_freeqhs = sqh; 960 } 961 962 /* 963 * Enter a list of transfers onto a control queue. 964 * Called at splusb() 965 */ 966 void 967 uhci_enter_ctl_q(sc, sqh, ii) 968 uhci_softc_t *sc; 969 uhci_soft_qh_t *sqh; 970 uhci_intr_info_t *ii; 971 { 972 DPRINTFN(5, ("uhci_enter_ctl_q: sqh=%p\n", sqh)); 973 974 } 975 976 void 977 uhci_free_std_chain(sc, std, stdend) 978 uhci_softc_t *sc; 979 uhci_soft_td_t *std; 980 uhci_soft_td_t *stdend; 981 { 982 uhci_soft_td_t *p; 983 984 for (; std != stdend; std = p) { 985 p = std->td->link.std; 986 uhci_free_std(sc, std); 987 } 988 } 989 990 usbd_status 991 uhci_alloc_std_chain(upipe, sc, len, rd, dma, sp, ep) 992 struct uhci_pipe *upipe; 993 uhci_softc_t *sc; 994 int len, rd; 995 usb_dma_t *dma; 996 uhci_soft_td_t **sp, **ep; 997 { 998 uhci_soft_td_t *p, *lastp; 999 uhci_physaddr_t lastlink; 1000 u_int32_t ls; 1001 int i, ntd, l, tog, maxp; 1002 int addr = upipe->pipe.device->address; 1003 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1004 1005 DPRINTFN(15, ("uhci_alloc_std_chain: len=%d\n", len)); 1006 if (len == 0) { 1007 *sp = *ep = 0; 1008 printf("uhci_alloc_std_chain: len=0\n"); 1009 return (USBD_NORMAL_COMPLETION); 1010 } 1011 ls = upipe->pipe.device->lowspeed ? UHCI_TD_LS : 0; 1012 maxp = UGETW(upipe->pipe.endpoint->edesc->wMaxPacketSize); 1013 if (maxp == 0) { 1014 printf("uhci_alloc_std_chain: maxp=0\n"); 1015 return (USBD_INVAL); 1016 } 1017 ntd = (len + maxp - 1) / maxp; 1018 tog = upipe->pipe.endpoint->toggle; 1019 if (ntd % 2 == 0) 1020 tog ^= 1; 1021 upipe->newtoggle = tog ^ 1; 1022 lastp = 0; 1023 lastlink = UHCI_PTR_T; 1024 ntd--; 1025 for (i = ntd; i >= 0; i--) { 1026 p = uhci_alloc_std(sc); 1027 if (!p) { 1028 uhci_free_std_chain(sc, lastp, 0); 1029 return (USBD_NOMEM); 1030 } 1031 p->td->link.std = lastp; 1032 p->td->td_link = lastlink; 1033 lastp = p; 1034 lastlink = p->physaddr; 1035 p->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | UHCI_TD_ACTIVE; 1036 if (i == ntd) { 1037 /* last TD */ 1038 l = len % maxp; 1039 if (l == 0) l = maxp; 1040 *ep = p; 1041 } else 1042 l = maxp; 1043 p->td->td_token = 1044 rd ? UHCI_TD_IN (l, endpt, addr, tog) : 1045 UHCI_TD_OUT(l, endpt, addr, tog); 1046 p->td->td_buffer = DMAADDR(dma) + i * maxp; 1047 tog ^= 1; 1048 } 1049 *sp = lastp; 1050 /*upipe->pipe.endpoint->toggle = tog;*/ 1051 DPRINTFN(10, ("uhci_alloc_std_chain: oldtog=%d newtog=%d\n", 1052 upipe->pipe.endpoint->toggle, upipe->newtoggle)); 1053 return (USBD_NORMAL_COMPLETION); 1054 } 1055 1056 usbd_status 1057 uhci_device_bulk_transfer(reqh) 1058 usbd_request_handle reqh; 1059 { 1060 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1061 usbd_device_handle dev = upipe->pipe.device; 1062 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1063 uhci_intr_info_t *ii = upipe->iinfo; 1064 uhci_soft_td_t *xfer, *xferend; 1065 uhci_soft_qh_t *sqh; 1066 usb_dma_t *dmap; 1067 usbd_status r; 1068 int len, isread; 1069 int s; 1070 1071 DPRINTFN(3, ("uhci_device_bulk_transfer: reqh=%p buf=%p len=%d flags=%d\n", 1072 reqh, reqh->buffer, reqh->length, reqh->flags)); 1073 1074 if (reqh->isreq) 1075 panic("uhci_device_bulk_transfer: a request\n"); 1076 1077 len = reqh->length; 1078 dmap = &upipe->u.bulk.datadma; 1079 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1080 sqh = upipe->u.bulk.sqh; 1081 1082 upipe->u.bulk.isread = isread; 1083 upipe->u.bulk.length = len; 1084 1085 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1086 if (r != USBD_NORMAL_COMPLETION) 1087 goto ret1; 1088 r = uhci_alloc_std_chain(upipe, sc, len, isread, 1089 dmap, &xfer, &xferend); 1090 if (r != USBD_NORMAL_COMPLETION) 1091 goto ret2; 1092 xferend->td->td_status |= UHCI_TD_IOC; 1093 1094 if (!isread && len != 0) 1095 memcpy(KERNADDR(dmap), reqh->buffer, len); 1096 1097 #ifdef USB_DEBUG 1098 if (uhcidebug > 10) { 1099 printf("uhci_device_bulk_transfer: xfer(1)\n"); 1100 uhci_dump_tds(xfer); 1101 } 1102 #endif 1103 1104 /* Set up interrupt info. */ 1105 ii->reqh = reqh; 1106 ii->stdstart = xfer; 1107 ii->stdend = xferend; 1108 #ifdef DIAGNOSTIC 1109 ii->isdone = 0; 1110 #endif 1111 1112 sqh->qh->elink = xfer; 1113 sqh->qh->qh_elink = xfer->physaddr; 1114 sqh->intr_info = ii; 1115 1116 s = splusb(); 1117 uhci_add_bulk(sc, sqh); 1118 LIST_INSERT_HEAD(&sc->sc_intrhead, ii, list); 1119 1120 if (reqh->timeout && !usbd_use_polling) 1121 timeout(uhci_timeout, ii, MS_TO_TICKS(reqh->timeout)); 1122 splx(s); 1123 1124 #ifdef USB_DEBUG 1125 if (uhcidebug > 10) { 1126 printf("uhci_device_bulk_transfer: xfer(2)\n"); 1127 uhci_dump_tds(xfer); 1128 } 1129 #endif 1130 1131 return (USBD_IN_PROGRESS); 1132 1133 ret2: 1134 if (len != 0) 1135 usb_freemem(sc->sc_dmatag, dmap); 1136 ret1: 1137 return (r); 1138 } 1139 1140 /* Abort a device bulk request. */ 1141 void 1142 uhci_device_bulk_abort(reqh) 1143 usbd_request_handle reqh; 1144 { 1145 /* XXX inactivate */ 1146 usbd_delay_ms(1); /* make sure it is finished */ 1147 /* XXX call done */ 1148 } 1149 1150 /* Close a device bulk pipe. */ 1151 void 1152 uhci_device_bulk_close(pipe) 1153 usbd_pipe_handle pipe; 1154 { 1155 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1156 usbd_device_handle dev = upipe->pipe.device; 1157 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1158 1159 uhci_free_sqh(sc, upipe->u.bulk.sqh); 1160 uhci_free_intr_info(upipe->iinfo); 1161 /* XXX free other resources */ 1162 } 1163 1164 usbd_status 1165 uhci_device_ctrl_transfer(reqh) 1166 usbd_request_handle reqh; 1167 { 1168 usbd_status r; 1169 1170 if (!reqh->isreq) 1171 panic("uhci_device_ctrl_transfer: not a request\n"); 1172 1173 r = uhci_device_request(reqh); 1174 if (r != USBD_NORMAL_COMPLETION) 1175 return (r); 1176 1177 if (usbd_use_polling) 1178 uhci_waitintr((uhci_softc_t *)reqh->pipe->device->bus, reqh); 1179 return (USBD_IN_PROGRESS); 1180 } 1181 1182 usbd_status 1183 uhci_device_intr_transfer(reqh) 1184 usbd_request_handle reqh; 1185 { 1186 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1187 usbd_device_handle dev = upipe->pipe.device; 1188 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1189 uhci_intr_info_t *ii = upipe->iinfo; 1190 uhci_soft_td_t *xfer, *xferend; 1191 uhci_soft_qh_t *sqh; 1192 usb_dma_t *dmap; 1193 usbd_status r; 1194 int len, i; 1195 int s; 1196 1197 DPRINTFN(3, ("uhci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d\n", 1198 reqh, reqh->buffer, reqh->length, reqh->flags)); 1199 1200 if (reqh->isreq) 1201 panic("uhci_device_intr_transfer: a request\n"); 1202 1203 len = reqh->length; 1204 dmap = &upipe->u.intr.datadma; 1205 if (len == 0) 1206 return (USBD_INVAL); /* XXX should it be? */ 1207 1208 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1209 if (r != USBD_NORMAL_COMPLETION) 1210 goto ret1; 1211 r = uhci_alloc_std_chain(upipe, sc, len, 1, dmap, &xfer, &xferend); 1212 if (r != USBD_NORMAL_COMPLETION) 1213 goto ret2; 1214 xferend->td->td_status |= UHCI_TD_IOC; 1215 1216 #ifdef USB_DEBUG 1217 if (uhcidebug > 10) { 1218 printf("uhci_device_intr_transfer: xfer(1)\n"); 1219 uhci_dump_tds(xfer); 1220 uhci_dump_qh(upipe->u.intr.qhs[0]); 1221 } 1222 #endif 1223 1224 s = splusb(); 1225 /* Set up interrupt info. */ 1226 ii->reqh = reqh; 1227 ii->stdstart = xfer; 1228 ii->stdend = xferend; 1229 #ifdef DIAGNOSTIC 1230 ii->isdone = 0; 1231 #endif 1232 1233 DPRINTFN(10,("uhci_device_intr_transfer: qhs[0]=%p\n", upipe->u.intr.qhs[0])); 1234 for (i = 0; i < upipe->u.intr.npoll; i++) { 1235 sqh = upipe->u.intr.qhs[i]; 1236 sqh->qh->elink = xfer; 1237 sqh->qh->qh_elink = xfer->physaddr; 1238 } 1239 splx(s); 1240 1241 #ifdef USB_DEBUG 1242 if (uhcidebug > 10) { 1243 printf("uhci_device_intr_transfer: xfer(2)\n"); 1244 uhci_dump_tds(xfer); 1245 uhci_dump_qh(upipe->u.intr.qhs[0]); 1246 } 1247 #endif 1248 1249 return (USBD_IN_PROGRESS); 1250 1251 ret2: 1252 if (len != 0) 1253 usb_freemem(sc->sc_dmatag, dmap); 1254 ret1: 1255 return (r); 1256 } 1257 1258 /* Abort a device control request. */ 1259 void 1260 uhci_device_ctrl_abort(reqh) 1261 usbd_request_handle reqh; 1262 { 1263 /* XXX inactivate */ 1264 usbd_delay_ms(1); /* make sure it is finished */ 1265 /* XXX call done */ 1266 } 1267 1268 /* Close a device control pipe. */ 1269 void 1270 uhci_device_ctrl_close(pipe) 1271 usbd_pipe_handle pipe; 1272 { 1273 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1274 1275 uhci_free_intr_info(upipe->iinfo); 1276 /* XXX free other resources */ 1277 } 1278 1279 /* Abort a device interrupt request. */ 1280 void 1281 uhci_device_intr_abort(reqh) 1282 usbd_request_handle reqh; 1283 { 1284 struct uhci_pipe *upipe; 1285 1286 DPRINTFN(1, ("uhci_device_intr_abort: reqh=%p\n", reqh)); 1287 /* XXX inactivate */ 1288 usbd_delay_ms(2); /* make sure it is finished */ 1289 if (reqh->pipe->intrreqh == reqh) { 1290 DPRINTF(("uhci_device_intr_abort: remove\n")); 1291 reqh->pipe->intrreqh = 0; 1292 upipe = (struct uhci_pipe *)reqh->pipe; 1293 uhci_intr_done(upipe->u.intr.qhs[0]->intr_info); 1294 } 1295 } 1296 1297 /* Close a device interrupt pipe. */ 1298 void 1299 uhci_device_intr_close(pipe) 1300 usbd_pipe_handle pipe; 1301 { 1302 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1303 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 1304 int i, s, npoll; 1305 1306 upipe->iinfo->stdstart = 0; /* inactive */ 1307 1308 /* Unlink descriptors from controller data structures. */ 1309 npoll = upipe->u.intr.npoll; 1310 uhci_lock_frames(sc); 1311 for (i = 0; i < npoll; i++) 1312 uhci_remove_intr(sc, upipe->u.intr.qhs[i]->pos, 1313 upipe->u.intr.qhs[i]); 1314 uhci_unlock_frames(sc); 1315 1316 /* 1317 * We now have to wait for any activity on the physical 1318 * descriptors to stop. 1319 */ 1320 usbd_delay_ms(2); 1321 1322 for(i = 0; i < npoll; i++) 1323 uhci_free_sqh(sc, upipe->u.intr.qhs[i]); 1324 free(upipe->u.intr.qhs, M_USB); 1325 1326 s = splusb(); 1327 LIST_REMOVE(upipe->iinfo, list); /* remove from active list */ 1328 splx(s); 1329 uhci_free_intr_info(upipe->iinfo); 1330 1331 /* XXX free other resources */ 1332 } 1333 1334 usbd_status 1335 uhci_device_request(reqh) 1336 usbd_request_handle reqh; 1337 { 1338 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1339 usb_device_request_t *req = &reqh->request; 1340 usbd_device_handle dev = upipe->pipe.device; 1341 uhci_softc_t *sc = (uhci_softc_t *)dev->bus; 1342 int addr = dev->address; 1343 int endpt = upipe->pipe.endpoint->edesc->bEndpointAddress; 1344 uhci_intr_info_t *ii = upipe->iinfo; 1345 uhci_soft_td_t *setup, *xfer, *stat, *next, *xferend; 1346 uhci_soft_qh_t *sqh; 1347 usb_dma_t *dmap; 1348 int len; 1349 u_int32_t ls; 1350 usbd_status r; 1351 int isread; 1352 int s; 1353 1354 DPRINTFN(1,("uhci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1355 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1356 UGETW(req->wIndex), UGETW(req->wLength), 1357 addr, endpt)); 1358 1359 ls = dev->lowspeed ? UHCI_TD_LS : 0; 1360 isread = req->bmRequestType & UT_READ; 1361 len = UGETW(req->wLength); 1362 1363 setup = upipe->u.ctl.setup; 1364 stat = upipe->u.ctl.stat; 1365 sqh = upipe->u.ctl.sqh; 1366 dmap = &upipe->u.ctl.datadma; 1367 1368 /* Set up data transaction */ 1369 if (len != 0) { 1370 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1371 if (r != USBD_NORMAL_COMPLETION) 1372 goto ret1; 1373 upipe->pipe.endpoint->toggle = 1; 1374 r = uhci_alloc_std_chain(upipe, sc, len, isread, 1375 dmap, &xfer, &xferend); 1376 if (r != USBD_NORMAL_COMPLETION) 1377 goto ret2; 1378 next = xfer; 1379 xferend->td->link.std = stat; 1380 xferend->td->td_link = stat->physaddr; 1381 } else { 1382 xfer = 0; 1383 next = stat; 1384 } 1385 upipe->u.ctl.length = len; 1386 upipe->u.ctl.xferend = xferend; 1387 1388 memcpy(KERNADDR(&upipe->u.ctl.reqdma), req, sizeof *req); 1389 if (!isread && len != 0) 1390 memcpy(KERNADDR(dmap), reqh->buffer, len); 1391 1392 setup->td->link.std = next; 1393 setup->td->td_link = next->physaddr; 1394 setup->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | UHCI_TD_ACTIVE; 1395 setup->td->td_token = UHCI_TD_SETUP(sizeof *req, endpt, addr); 1396 setup->td->td_buffer = DMAADDR(&upipe->u.ctl.reqdma); 1397 1398 stat->td->link.std = 0; 1399 stat->td->td_link = UHCI_PTR_T; 1400 stat->td->td_status = UHCI_TD_SET_ERRCNT(2) | ls | 1401 UHCI_TD_ACTIVE | UHCI_TD_IOC; 1402 stat->td->td_token = 1403 isread ? UHCI_TD_OUT(0, endpt, addr, 1) : 1404 UHCI_TD_IN (0, endpt, addr, 1); 1405 stat->td->td_buffer = 0; 1406 1407 #ifdef USB_DEBUG 1408 if (uhcidebug > 20) { 1409 printf("uhci_device_request: setup\n"); 1410 uhci_dump_td(setup); 1411 printf("uhci_device_request: stat\n"); 1412 uhci_dump_td(stat); 1413 } 1414 #endif 1415 1416 /* Set up interrupt info. */ 1417 ii->reqh = reqh; 1418 ii->stdstart = setup; 1419 ii->stdend = stat; 1420 #ifdef DIAGNOSTIC 1421 ii->isdone = 0; 1422 #endif 1423 1424 sqh->qh->elink = setup; 1425 sqh->qh->qh_elink = setup->physaddr; 1426 sqh->intr_info = ii; 1427 1428 s = splusb(); 1429 uhci_add_ctrl(sc, sqh); 1430 LIST_INSERT_HEAD(&sc->sc_intrhead, ii, list); 1431 #ifdef USB_DEBUG 1432 if (uhcidebug > 12) { 1433 uhci_soft_td_t *std; 1434 uhci_soft_qh_t *xqh; 1435 uhci_physaddr_t link; 1436 printf("uhci_enter_ctl_q: follow from [0]\n"); 1437 for (std = sc->sc_vframes[0].htd, link = 0; 1438 (link & UHCI_PTR_Q) == 0; 1439 std = std->td->link.std) { 1440 link = std->td->td_link; 1441 uhci_dump_td(std); 1442 } 1443 for (xqh = (uhci_soft_qh_t *)std; 1444 xqh; 1445 xqh = xqh->qh->hlink) 1446 uhci_dump_qh(xqh); 1447 printf("Enqueued QH:\n"); 1448 uhci_dump_qh(sqh); 1449 uhci_dump_tds(sqh->qh->elink); 1450 } 1451 #endif 1452 if (reqh->timeout && !usbd_use_polling) 1453 timeout(uhci_timeout, ii, MS_TO_TICKS(reqh->timeout)); 1454 splx(s); 1455 1456 return (USBD_NORMAL_COMPLETION); 1457 1458 ret2: 1459 if (len != 0) 1460 usb_freemem(sc->sc_dmatag, dmap); 1461 ret1: 1462 return (r); 1463 } 1464 1465 void 1466 uhci_intr_done(ii) 1467 uhci_intr_info_t *ii; 1468 { 1469 uhci_softc_t *sc = ii->sc; 1470 usbd_request_handle reqh = ii->reqh; 1471 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1472 usb_dma_t *dma; 1473 uhci_soft_qh_t *sqh; 1474 int i, npoll; 1475 1476 DPRINTFN(5, ("uhci_intr_done: length=%d\n", reqh->actlen)); 1477 1478 dma = &upipe->u.intr.datadma; 1479 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 1480 npoll = upipe->u.intr.npoll; 1481 for(i = 0; i < npoll; i++) { 1482 sqh = upipe->u.intr.qhs[i]; 1483 sqh->qh->elink = 0; 1484 sqh->qh->qh_elink = UHCI_PTR_T; 1485 } 1486 uhci_free_std_chain(sc, ii->stdstart, 0); 1487 1488 /* XXX Wasteful. */ 1489 if (reqh->pipe->intrreqh == reqh) { 1490 uhci_soft_td_t *xfer, *xferend; 1491 1492 /* This alloc cannot fail since we freed the chain above. */ 1493 uhci_alloc_std_chain(upipe, sc, reqh->length, 1, dma, 1494 &xfer, &xferend); 1495 xferend->td->td_status |= UHCI_TD_IOC; 1496 1497 #ifdef USB_DEBUG 1498 if (uhcidebug > 10) { 1499 printf("uhci_device_intr_done: xfer(1)\n"); 1500 uhci_dump_tds(xfer); 1501 uhci_dump_qh(upipe->u.intr.qhs[0]); 1502 } 1503 #endif 1504 1505 ii->stdstart = xfer; 1506 ii->stdend = xferend; 1507 #ifdef DIAGNOSTIC 1508 ii->isdone = 0; 1509 #endif 1510 for (i = 0; i < npoll; i++) { 1511 sqh = upipe->u.intr.qhs[i]; 1512 sqh->qh->elink = xfer; 1513 sqh->qh->qh_elink = xfer->physaddr; 1514 } 1515 } else { 1516 usb_freemem(sc->sc_dmatag, dma); 1517 ii->stdstart = 0; /* mark as inactive */ 1518 } 1519 } 1520 1521 /* Deallocate request data structures */ 1522 void 1523 uhci_ctrl_done(ii) 1524 uhci_intr_info_t *ii; 1525 { 1526 uhci_softc_t *sc = ii->sc; 1527 usbd_request_handle reqh = ii->reqh; 1528 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1529 u_int len = upipe->u.ctl.length; 1530 usb_dma_t *dma; 1531 uhci_td_t *htd = ii->stdstart->td; 1532 1533 #ifdef DIAGNOSTIC 1534 if (!reqh->isreq) 1535 panic("uhci_ctrl_done: not a request\n"); 1536 #endif 1537 1538 LIST_REMOVE(ii, list); /* remove from active list */ 1539 1540 uhci_remove_ctrl(sc, upipe->u.ctl.sqh); 1541 1542 if (len != 0) { 1543 dma = &upipe->u.ctl.datadma; 1544 if (reqh->request.bmRequestType & UT_READ) 1545 memcpy(reqh->buffer, KERNADDR(dma), len); 1546 uhci_free_std_chain(sc, htd->link.std, ii->stdend); 1547 usb_freemem(sc->sc_dmatag, dma); 1548 } 1549 DPRINTFN(5, ("uhci_ctrl_done: length=%d\n", reqh->actlen)); 1550 } 1551 1552 /* Deallocate request data structures */ 1553 void 1554 uhci_bulk_done(ii) 1555 uhci_intr_info_t *ii; 1556 { 1557 uhci_softc_t *sc = ii->sc; 1558 usbd_request_handle reqh = ii->reqh; 1559 struct uhci_pipe *upipe = (struct uhci_pipe *)reqh->pipe; 1560 u_int len = upipe->u.bulk.length; 1561 usb_dma_t *dma; 1562 uhci_td_t *htd = ii->stdstart->td; 1563 1564 LIST_REMOVE(ii, list); /* remove from active list */ 1565 1566 uhci_remove_bulk(sc, upipe->u.bulk.sqh); 1567 1568 if (len != 0) { 1569 dma = &upipe->u.bulk.datadma; 1570 if (upipe->u.bulk.isread && len != 0) 1571 memcpy(reqh->buffer, KERNADDR(dma), len); 1572 uhci_free_std_chain(sc, htd->link.std, 0); 1573 usb_freemem(sc->sc_dmatag, dma); 1574 } 1575 DPRINTFN(4, ("uhci_bulk_done: length=%d\n", reqh->actlen)); 1576 /* XXX compute new toggle */ 1577 } 1578 1579 /* Add interrupt QH, called with vflock. */ 1580 void 1581 uhci_add_intr(sc, n, sqh) 1582 uhci_softc_t *sc; 1583 int n; 1584 uhci_soft_qh_t *sqh; 1585 { 1586 struct uhci_vframe *vf = &sc->sc_vframes[n]; 1587 uhci_qh_t *eqh; 1588 1589 DPRINTFN(4, ("uhci_add_intr: n=%d sqh=%p\n", n, sqh)); 1590 eqh = vf->eqh->qh; 1591 sqh->qh->hlink = eqh->hlink; 1592 sqh->qh->qh_hlink = eqh->qh_hlink; 1593 eqh->hlink = sqh; 1594 eqh->qh_hlink = sqh->physaddr | UHCI_PTR_Q; 1595 vf->eqh = sqh; 1596 vf->bandwidth++; 1597 } 1598 1599 /* Remove interrupt QH, called with vflock. */ 1600 void 1601 uhci_remove_intr(sc, n, sqh) 1602 uhci_softc_t *sc; 1603 int n; 1604 uhci_soft_qh_t *sqh; 1605 { 1606 struct uhci_vframe *vf = &sc->sc_vframes[n]; 1607 uhci_soft_qh_t *pqh; 1608 1609 DPRINTFN(4, ("uhci_remove_intr: n=%d sqh=%p\n", n, sqh)); 1610 1611 for (pqh = vf->hqh; pqh->qh->hlink != sqh; pqh = pqh->qh->hlink) 1612 #if defined(DIAGNOSTIC) || defined(USB_DEBUG) 1613 if (pqh->qh->qh_hlink & UHCI_PTR_T) { 1614 printf("uhci_remove_intr: QH not found\n"); 1615 return; 1616 } 1617 #else 1618 ; 1619 #endif 1620 pqh->qh->hlink = sqh->qh->hlink; 1621 pqh->qh->qh_hlink = sqh->qh->qh_hlink; 1622 if (vf->eqh == sqh) 1623 vf->eqh = pqh; 1624 vf->bandwidth--; 1625 } 1626 1627 usbd_status 1628 uhci_device_setintr(sc, upipe, ival) 1629 uhci_softc_t *sc; 1630 struct uhci_pipe *upipe; 1631 int ival; 1632 { 1633 uhci_soft_qh_t *sqh; 1634 int i, npoll, s; 1635 u_int bestbw, bw, bestoffs, offs; 1636 1637 DPRINTFN(2, ("uhci_setintr: pipe=%p\n", upipe)); 1638 if (ival == 0) { 1639 printf("uhci_setintr: 0 interval\n"); 1640 return (USBD_INVAL); 1641 } 1642 1643 if (ival > UHCI_VFRAMELIST_COUNT) 1644 ival = UHCI_VFRAMELIST_COUNT; 1645 npoll = (UHCI_VFRAMELIST_COUNT + ival - 1) / ival; 1646 DPRINTFN(2, ("uhci_setintr: ival=%d npoll=%d\n", ival, npoll)); 1647 1648 upipe->u.intr.npoll = npoll; 1649 upipe->u.intr.qhs = 1650 malloc(npoll * sizeof(uhci_soft_qh_t *), M_USB, M_WAITOK); 1651 1652 /* 1653 * Figure out which offset in the schedule that has most 1654 * bandwidth left over. 1655 */ 1656 #define MOD(i) ((i) & (UHCI_VFRAMELIST_COUNT-1)) 1657 for (bestoffs = offs = 0, bestbw = ~0; offs < ival; offs++) { 1658 for (bw = i = 0; i < npoll; i++) 1659 bw += sc->sc_vframes[MOD(i * ival + offs)].bandwidth; 1660 if (bw < bestbw) { 1661 bestbw = bw; 1662 bestoffs = offs; 1663 } 1664 } 1665 DPRINTFN(1, ("uhci_setintr: bw=%d offs=%d\n", bestbw, bestoffs)); 1666 1667 upipe->iinfo->stdstart = 0; 1668 for(i = 0; i < npoll; i++) { 1669 upipe->u.intr.qhs[i] = sqh = uhci_alloc_sqh(sc); 1670 sqh->qh->elink = 0; 1671 sqh->qh->qh_elink = UHCI_PTR_T; 1672 sqh->pos = MOD(i * ival + bestoffs); 1673 sqh->intr_info = upipe->iinfo; 1674 } 1675 #undef MOD 1676 1677 s = splusb(); 1678 LIST_INSERT_HEAD(&sc->sc_intrhead, upipe->iinfo, list); 1679 splx(s); 1680 1681 uhci_lock_frames(sc); 1682 /* Enter QHs into the controller data structures. */ 1683 for(i = 0; i < npoll; i++) 1684 uhci_add_intr(sc, upipe->u.intr.qhs[i]->pos, 1685 upipe->u.intr.qhs[i]); 1686 uhci_unlock_frames(sc); 1687 1688 DPRINTFN(5, ("uhci_setintr: returns %p\n", upipe)); 1689 return (USBD_NORMAL_COMPLETION); 1690 } 1691 1692 /* Open a new pipe. */ 1693 usbd_status 1694 uhci_open(pipe) 1695 usbd_pipe_handle pipe; 1696 { 1697 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 1698 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 1699 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1700 usbd_status r; 1701 1702 DPRINTFN(1, ("uhci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1703 pipe, pipe->device->address, 1704 ed->bEndpointAddress, sc->sc_addr)); 1705 if (pipe->device->address == sc->sc_addr) { 1706 switch (ed->bEndpointAddress) { 1707 case USB_CONTROL_ENDPOINT: 1708 pipe->methods = &uhci_root_ctrl_methods; 1709 break; 1710 case UE_IN | UHCI_INTR_ENDPT: 1711 pipe->methods = &uhci_root_intr_methods; 1712 break; 1713 default: 1714 return (USBD_INVAL); 1715 } 1716 } else { 1717 upipe->iinfo = uhci_alloc_intr_info(sc); 1718 if (upipe->iinfo == 0) 1719 return (USBD_NOMEM); 1720 switch (ed->bmAttributes & UE_XFERTYPE) { 1721 case UE_CONTROL: 1722 pipe->methods = &uhci_device_ctrl_methods; 1723 upipe->u.ctl.sqh = uhci_alloc_sqh(sc); 1724 if (upipe->u.ctl.sqh == 0) 1725 goto bad; 1726 upipe->u.ctl.setup = uhci_alloc_std(sc); 1727 if (upipe->u.ctl.setup == 0) { 1728 uhci_free_sqh(sc, upipe->u.ctl.sqh); 1729 goto bad; 1730 } 1731 upipe->u.ctl.stat = uhci_alloc_std(sc); 1732 if (upipe->u.ctl.stat == 0) { 1733 uhci_free_sqh(sc, upipe->u.ctl.sqh); 1734 uhci_free_std(sc, upipe->u.ctl.setup); 1735 goto bad; 1736 } 1737 r = usb_allocmem(sc->sc_dmatag, 1738 sizeof(usb_device_request_t), 1739 0, &upipe->u.ctl.reqdma); 1740 if (r != USBD_NORMAL_COMPLETION) { 1741 uhci_free_sqh(sc, upipe->u.ctl.sqh); 1742 uhci_free_std(sc, upipe->u.ctl.setup); 1743 uhci_free_std(sc, upipe->u.ctl.stat); 1744 goto bad; 1745 } 1746 break; 1747 case UE_INTERRUPT: 1748 pipe->methods = &uhci_device_intr_methods; 1749 return (uhci_device_setintr(sc, upipe, ed->bInterval)); 1750 case UE_ISOCHRONOUS: 1751 printf("uhci_open: iso not implemented\n"); 1752 return (USBD_XXX); 1753 case UE_BULK: 1754 pipe->methods = &uhci_device_bulk_methods; 1755 upipe->u.bulk.sqh = uhci_alloc_sqh(sc); 1756 if (upipe->u.bulk.sqh == 0) 1757 goto bad; 1758 break; 1759 } 1760 } 1761 return (USBD_NORMAL_COMPLETION); 1762 1763 bad: 1764 uhci_free_intr_info(upipe->iinfo); 1765 return (USBD_NOMEM); 1766 } 1767 1768 /* 1769 * Data structures and routines to emulate the root hub. 1770 */ 1771 usb_device_descriptor_t uhci_devd = { 1772 USB_DEVICE_DESCRIPTOR_SIZE, 1773 UDESC_DEVICE, /* type */ 1774 {0x00, 0x01}, /* USB version */ 1775 UCLASS_HUB, /* class */ 1776 USUBCLASS_HUB, /* subclass */ 1777 0, /* protocol */ 1778 64, /* max packet */ 1779 {0},{0},{0x00,0x01}, /* device id */ 1780 1,2,0, /* string indicies */ 1781 1 /* # of configurations */ 1782 }; 1783 1784 usb_config_descriptor_t uhci_confd = { 1785 USB_CONFIG_DESCRIPTOR_SIZE, 1786 UDESC_CONFIG, 1787 {USB_CONFIG_DESCRIPTOR_SIZE + 1788 USB_INTERFACE_DESCRIPTOR_SIZE + 1789 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1790 1, 1791 1, 1792 0, 1793 UC_SELF_POWERED, 1794 0 /* max power */ 1795 }; 1796 1797 usb_interface_descriptor_t uhci_ifcd = { 1798 USB_INTERFACE_DESCRIPTOR_SIZE, 1799 UDESC_INTERFACE, 1800 0, 1801 0, 1802 1, 1803 UCLASS_HUB, 1804 USUBCLASS_HUB, 1805 0, 1806 0 1807 }; 1808 1809 usb_endpoint_descriptor_t uhci_endpd = { 1810 USB_ENDPOINT_DESCRIPTOR_SIZE, 1811 UDESC_ENDPOINT, 1812 UE_IN | UHCI_INTR_ENDPT, 1813 UE_INTERRUPT, 1814 {8}, 1815 255 1816 }; 1817 1818 usb_hub_descriptor_t uhci_hubd_piix = { 1819 USB_HUB_DESCRIPTOR_SIZE, 1820 UDESC_HUB, 1821 2, 1822 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 1823 50, /* power on to power good */ 1824 0, 1825 { 0x00 }, /* both ports are removable */ 1826 { 0x00 }, /* no ports can power down individually */ 1827 }; 1828 1829 int 1830 uhci_str(p, l, s) 1831 usb_string_descriptor_t *p; 1832 int l; 1833 char *s; 1834 { 1835 int i; 1836 1837 if (l == 0) 1838 return (0); 1839 p->bLength = 2 * strlen(s) + 2; 1840 if (l == 1) 1841 return (1); 1842 p->bDescriptorType = UDESC_STRING; 1843 l -= 2; 1844 for (i = 0; s[i] && l > 1; i++, l -= 2) 1845 USETW2(p->bString[i], 0, s[i]); 1846 return (2*i+2); 1847 } 1848 1849 /* 1850 * Simulate a hardware hub by handling all the necessary requests. 1851 */ 1852 usbd_status 1853 uhci_root_ctrl_transfer(reqh) 1854 usbd_request_handle reqh; 1855 { 1856 uhci_softc_t *sc = (uhci_softc_t *)reqh->pipe->device->bus; 1857 usb_device_request_t *req; 1858 void *buf; 1859 int port, x; 1860 int len, value, index, status, change, l, totlen = 0; 1861 usb_port_status_t ps; 1862 usbd_status r; 1863 1864 if (!reqh->isreq) 1865 panic("uhci_root_ctrl_transfer: not a request\n"); 1866 req = &reqh->request; 1867 buf = reqh->buffer; 1868 1869 DPRINTFN(2,("uhci_root_ctrl_control type=0x%02x request=%02x\n", 1870 req->bmRequestType, req->bRequest)); 1871 1872 len = UGETW(req->wLength); 1873 value = UGETW(req->wValue); 1874 index = UGETW(req->wIndex); 1875 #define C(x,y) ((x) | ((y) << 8)) 1876 switch(C(req->bRequest, req->bmRequestType)) { 1877 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1878 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1879 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1880 /* 1881 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops 1882 * for the integrated root hub. 1883 */ 1884 break; 1885 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1886 if (len > 0) { 1887 *(u_int8_t *)buf = sc->sc_conf; 1888 totlen = 1; 1889 } 1890 break; 1891 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1892 DPRINTFN(2,("uhci_root_ctrl_control wValue=0x%04x\n", value)); 1893 switch(value >> 8) { 1894 case UDESC_DEVICE: 1895 if ((value & 0xff) != 0) { 1896 r = USBD_IOERROR; 1897 goto ret; 1898 } 1899 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1900 memcpy(buf, &uhci_devd, l); 1901 break; 1902 case UDESC_CONFIG: 1903 if ((value & 0xff) != 0) { 1904 r = USBD_IOERROR; 1905 goto ret; 1906 } 1907 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1908 memcpy(buf, &uhci_confd, l); 1909 buf = (char *)buf + l; 1910 len -= l; 1911 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1912 totlen += l; 1913 memcpy(buf, &uhci_ifcd, l); 1914 buf = (char *)buf + l; 1915 len -= l; 1916 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1917 totlen += l; 1918 memcpy(buf, &uhci_endpd, l); 1919 break; 1920 case UDESC_STRING: 1921 if (len == 0) 1922 break; 1923 *(u_int8_t *)buf = 0; 1924 totlen = 1; 1925 switch (value & 0xff) { 1926 case 1: /* Vendor */ 1927 if (sc->sc_model == UHCI_PIIX3 || 1928 sc->sc_model == UHCI_PIIX4) 1929 totlen = uhci_str(buf, len, "Intel"); 1930 break; 1931 case 2: /* Product */ 1932 if (sc->sc_model == UHCI_PIIX3) 1933 totlen = uhci_str(buf, len, 1934 "PIIX3 root hub"); 1935 if (sc->sc_model == UHCI_PIIX4) 1936 totlen = uhci_str(buf, len, 1937 "PIIX4 root hub"); 1938 break; 1939 } 1940 break; 1941 default: 1942 r = USBD_IOERROR; 1943 goto ret; 1944 } 1945 break; 1946 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1947 if (len > 0) { 1948 *(u_int8_t *)buf = 0; 1949 totlen = 1; 1950 } 1951 break; 1952 case C(UR_GET_STATUS, UT_READ_DEVICE): 1953 if (len > 1) { 1954 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1955 totlen = 2; 1956 } 1957 break; 1958 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1959 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1960 if (len > 1) { 1961 USETW(((usb_status_t *)buf)->wStatus, 0); 1962 totlen = 2; 1963 } 1964 break; 1965 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1966 if (value >= USB_MAX_DEVICES) { 1967 r = USBD_IOERROR; 1968 goto ret; 1969 } 1970 sc->sc_addr = value; 1971 break; 1972 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1973 if (value != 0 && value != 1) { 1974 r = USBD_IOERROR; 1975 goto ret; 1976 } 1977 sc->sc_conf = value; 1978 break; 1979 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1980 break; 1981 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1982 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1983 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1984 r = USBD_IOERROR; 1985 goto ret; 1986 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1987 break; 1988 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1989 break; 1990 /* Hub requests */ 1991 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1992 break; 1993 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1994 DPRINTFN(3, ("uhci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n", 1995 index, value)); 1996 if (index == 1) 1997 port = UHCI_PORTSC1; 1998 else if (index == 2) 1999 port = UHCI_PORTSC2; 2000 else { 2001 r = USBD_IOERROR; 2002 goto ret; 2003 } 2004 switch(value) { 2005 case UHF_PORT_ENABLE: 2006 x = UREAD2(sc, port); 2007 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2008 break; 2009 case UHF_PORT_SUSPEND: 2010 x = UREAD2(sc, port); 2011 UWRITE2(sc, port, x & ~UHCI_PORTSC_SUSP); 2012 break; 2013 case UHF_PORT_RESET: 2014 x = UREAD2(sc, port); 2015 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2016 break; 2017 case UHF_C_PORT_CONNECTION: 2018 x = UREAD2(sc, port); 2019 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2020 break; 2021 case UHF_C_PORT_ENABLE: 2022 x = UREAD2(sc, port); 2023 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2024 break; 2025 case UHF_C_PORT_OVER_CURRENT: 2026 x = UREAD2(sc, port); 2027 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2028 break; 2029 case UHF_C_PORT_RESET: 2030 sc->sc_isreset = 0; 2031 r = USBD_NORMAL_COMPLETION; 2032 goto ret; 2033 case UHF_PORT_CONNECTION: 2034 case UHF_PORT_OVER_CURRENT: 2035 case UHF_PORT_POWER: 2036 case UHF_PORT_LOW_SPEED: 2037 case UHF_C_PORT_SUSPEND: 2038 default: 2039 r = USBD_IOERROR; 2040 goto ret; 2041 } 2042 break; 2043 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2044 if (index == 1) 2045 port = UHCI_PORTSC1; 2046 else if (index == 2) 2047 port = UHCI_PORTSC2; 2048 else { 2049 r = USBD_IOERROR; 2050 goto ret; 2051 } 2052 if (len > 0) { 2053 *(u_int8_t *)buf = 2054 (UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2055 UHCI_PORTSC_LS_SHIFT; 2056 totlen = 1; 2057 } 2058 break; 2059 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2060 if (value != 0) { 2061 r = USBD_IOERROR; 2062 goto ret; 2063 } 2064 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 2065 totlen = l; 2066 memcpy(buf, &uhci_hubd_piix, l); 2067 break; 2068 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2069 if (len != 4) { 2070 r = USBD_IOERROR; 2071 goto ret; 2072 } 2073 memset(buf, 0, len); 2074 totlen = len; 2075 break; 2076 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2077 if (index == 1) 2078 port = UHCI_PORTSC1; 2079 else if (index == 2) 2080 port = UHCI_PORTSC2; 2081 else { 2082 r = USBD_IOERROR; 2083 goto ret; 2084 } 2085 if (len != 4) { 2086 r = USBD_IOERROR; 2087 goto ret; 2088 } 2089 x = UREAD2(sc, port); 2090 status = change = 0; 2091 if (x & UHCI_PORTSC_CCS ) 2092 status |= UPS_CURRENT_CONNECT_STATUS; 2093 if (x & UHCI_PORTSC_CSC ) 2094 change |= UPS_C_CONNECT_STATUS; 2095 if (x & UHCI_PORTSC_PE ) 2096 status |= UPS_PORT_ENABLED; 2097 if (x & UHCI_PORTSC_POEDC) 2098 change |= UPS_C_PORT_ENABLED; 2099 if (x & UHCI_PORTSC_OCI ) 2100 status |= UPS_OVERCURRENT_INDICATOR; 2101 if (x & UHCI_PORTSC_OCIC ) 2102 change |= UPS_C_OVERCURRENT_INDICATOR; 2103 if (x & UHCI_PORTSC_SUSP ) 2104 status |= UPS_SUSPEND; 2105 if (x & UHCI_PORTSC_LSDA ) 2106 status |= UPS_LOW_SPEED; 2107 status |= UPS_PORT_POWER; 2108 if (sc->sc_isreset) 2109 change |= UPS_C_PORT_RESET; 2110 USETW(ps.wPortStatus, status); 2111 USETW(ps.wPortChange, change); 2112 l = min(len, sizeof ps); 2113 memcpy(buf, &ps, l); 2114 totlen = l; 2115 break; 2116 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2117 r = USBD_IOERROR; 2118 goto ret; 2119 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2120 break; 2121 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2122 if (index == 1) 2123 port = UHCI_PORTSC1; 2124 else if (index == 2) 2125 port = UHCI_PORTSC2; 2126 else { 2127 r = USBD_IOERROR; 2128 goto ret; 2129 } 2130 switch(value) { 2131 case UHF_PORT_ENABLE: 2132 x = UREAD2(sc, port); 2133 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2134 break; 2135 case UHF_PORT_SUSPEND: 2136 x = UREAD2(sc, port); 2137 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2138 break; 2139 case UHF_PORT_RESET: 2140 x = UREAD2(sc, port); 2141 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2142 usbd_delay_ms(10); 2143 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2144 delay(100); 2145 x = UREAD2(sc, port); 2146 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2147 delay(100); 2148 DPRINTFN(3,("uhci port %d reset, status = 0x%04x\n", 2149 index, UREAD2(sc, port))); 2150 sc->sc_isreset = 1; 2151 break; 2152 case UHF_C_PORT_CONNECTION: 2153 case UHF_C_PORT_ENABLE: 2154 case UHF_C_PORT_OVER_CURRENT: 2155 case UHF_PORT_CONNECTION: 2156 case UHF_PORT_OVER_CURRENT: 2157 case UHF_PORT_POWER: 2158 case UHF_PORT_LOW_SPEED: 2159 case UHF_C_PORT_SUSPEND: 2160 case UHF_C_PORT_RESET: 2161 default: 2162 r = USBD_IOERROR; 2163 goto ret; 2164 } 2165 break; 2166 default: 2167 r = USBD_IOERROR; 2168 goto ret; 2169 } 2170 reqh->actlen = totlen; 2171 r = USBD_NORMAL_COMPLETION; 2172 ret: 2173 reqh->status = r; 2174 reqh->xfercb(reqh); 2175 return (USBD_IN_PROGRESS); 2176 } 2177 2178 /* Abort a root control request. */ 2179 void 2180 uhci_root_ctrl_abort(reqh) 2181 usbd_request_handle reqh; 2182 { 2183 /* Nothing to do, all transfers are syncronous. */ 2184 } 2185 2186 /* Close the root pipe. */ 2187 void 2188 uhci_root_ctrl_close(pipe) 2189 usbd_pipe_handle pipe; 2190 { 2191 untimeout(uhci_timo, pipe->intrreqh); 2192 DPRINTF(("uhci_root_ctrl_close\n")); 2193 } 2194 2195 /* Abort a root interrupt request. */ 2196 void 2197 uhci_root_intr_abort(reqh) 2198 usbd_request_handle reqh; 2199 { 2200 untimeout(uhci_timo, reqh); 2201 } 2202 2203 /* Start a transfer on the root interrupt pipe */ 2204 usbd_status 2205 uhci_root_intr_transfer(reqh) 2206 usbd_request_handle reqh; 2207 { 2208 usbd_pipe_handle pipe = reqh->pipe; 2209 uhci_softc_t *sc = (uhci_softc_t *)pipe->device->bus; 2210 struct uhci_pipe *upipe = (struct uhci_pipe *)pipe; 2211 usb_dma_t *dmap; 2212 usbd_status r; 2213 int len; 2214 2215 DPRINTFN(3, ("uhci_root_intr_transfer: reqh=%p buf=%p len=%d flags=%d\n", 2216 reqh, reqh->buffer, reqh->length, reqh->flags)); 2217 2218 len = reqh->length; 2219 dmap = &upipe->u.intr.datadma; 2220 if (len == 0) 2221 return (USBD_INVAL); /* XXX should it be? */ 2222 2223 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 2224 if (r != USBD_NORMAL_COMPLETION) 2225 return (r); 2226 2227 sc->sc_ival = MS_TO_TICKS(reqh->pipe->endpoint->edesc->bInterval); 2228 timeout(uhci_timo, reqh, sc->sc_ival); 2229 return (USBD_IN_PROGRESS); 2230 } 2231 2232 /* Close the root interrupt pipe. */ 2233 void 2234 uhci_root_intr_close(pipe) 2235 usbd_pipe_handle pipe; 2236 { 2237 untimeout(uhci_timo, pipe->intrreqh); 2238 DPRINTF(("uhci_root_intr_close\n")); 2239 } 2240
Indexes created Tue Sep 23 14:10:03 GMT 2025