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uhcivar.h revision 1.1 
      1 /*	$NetBSD: uhcivar.h,v 1.1 1998/07/12 19:51:59 augustss Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * Author: Lennart Augustsson <augustss (at) carlstedt.se>
      8  *         Carlstedt Research & Technology
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  * To avoid having 1024 TDs for each isochronous transfer we introduce
     41  * a virtual frame list.  Every UHCI_VFRAMELIST_COUNT entries in the real
     42  * frame list points to a non-active TD.  These, in turn, which form the
     43  * starts of the virtual frame list.  This also has the advantage that it
     44  * simplifies linking in/out TD/QH in the schedule.
     45  * Furthermore, initially each of the inactive TDs point to an inactive
     46  * QH that forms the start of the interrupt traffic for that slot.
     47  * Each of these QHs point to the same QH that is the start of control
     48  * traffic.
     49  *
     50  * UHCI_VFRAMELIST_COUNT should be a power of 2 and <= UHCI_FRAMELIST_COUNT.
     51  */
     52 #define UHCI_VFRAMELIST_COUNT 128
     53 
     54 typedef struct uhci_soft_qh uhci_soft_qh_t;
     55 typedef struct uhci_soft_td uhci_soft_td_t;
     56 
     57 typedef struct uhci_dma {
     58 	bus_dmamap_t map;
     59         caddr_t kaddr;
     60         bus_dma_segment_t segs[1];
     61         int nsegs;
     62         size_t size;
     63 	struct uhci_dma *next;
     64 } uhci_dma_t;
     65 #define DMAADDR(dma) ((dma)->segs[0].ds_addr)
     66 #define KERNADDR(dma) ((void *)((dma)->kaddr))
     67 
     68 /*
     69  * An interrupt info struct contains the information needed to
     70  * execute a requested routine when the controller generates an
     71  * interrupt.  Since we cannot know which transfer generated
     72  * the interrupt all structs are linked together so they can be
     73  * searched at interrupt time.
     74  */
     75 typedef struct uhci_intr_info {
     76 	struct uhci_softc *sc;
     77 	usbd_request_handle reqh;
     78 	uhci_soft_td_t *stdstart;
     79 	uhci_soft_td_t *stdend;
     80 	LIST_ENTRY(uhci_intr_info) list;
     81 } uhci_intr_info_t;
     82 
     83 /*
     84  * Extra information that we need for a TD.
     85  */
     86 struct uhci_soft_td {
     87 	uhci_td_t *td;			/* The real TD */
     88 	uhci_physaddr_t physaddr;	/* and its physical address. */
     89 };
     90 #define UHCI_TD_CHUNK 128 /*(PAGE_SIZE / UHCI_TD_SIZE)*/
     91 
     92 /*
     93  * Extra information that we need for a QH.
     94  */
     95 struct uhci_soft_qh {
     96 	uhci_qh_t *qh;			/* The real QH */
     97 	uhci_physaddr_t physaddr;	/* and its physical address. */
     98 	int pos;			/* Timeslot position */
     99 	uhci_intr_info_t *intr_info;	/* Who to call on completion. */
    100 };
    101 #define UHCI_QH_CHUNK 128 /*(PAGE_SIZE / UHCI_QH_SIZE)*/
    102 
    103 /* Only used for buffer free list. */
    104 struct uhci_buffer {
    105 	struct uhci_buffer *next;
    106 };
    107 #define UHCI_BUFFER_SIZE 64
    108 #define UHCI_BUFFER_CHUNK 64 	/*(PAGE_SIZE / UHCI_BUFFER_SIZE)*/
    109 
    110 /*
    111  * Information about an entry in the virtial frame list.
    112  */
    113 struct uhci_vframe {
    114 	uhci_soft_td_t *htd;		/* pointer to dummy TD */
    115 	uhci_soft_td_t *etd;		/* pointer to last TD */
    116 	uhci_soft_qh_t *hqh;		/* pointer to dummy QH */
    117 	uhci_soft_qh_t *eqh;		/* pointer to last QH */
    118 	u_int bandwidth;		/* max bandwidth used by this frame */
    119 };
    120 
    121 typedef struct uhci_softc {
    122 	struct usbd_bus sc_bus;		/* base device */
    123 	void *sc_ih;			/* interrupt vectoring */
    124 	bus_space_tag_t iot;
    125 	bus_space_handle_t ioh;
    126 
    127 	bus_dma_tag_t sc_dmatag;	/* DMA tag */
    128 	/* XXX should keep track of all DMA memory */
    129 
    130 	uhci_physaddr_t *sc_pframes;
    131 	struct uhci_vframe sc_vframes[UHCI_VFRAMELIST_COUNT];
    132 
    133 	uhci_soft_qh_t *sc_ctl_start;	/* dummy QH for control */
    134 	uhci_soft_qh_t *sc_ctl_end;	/* last control QH */
    135 	uhci_soft_qh_t *sc_bulk_start;	/* dummy QH for bulk */
    136 	uhci_soft_qh_t *sc_bulk_end;	/* last bulk transfer */
    137 
    138 	uhci_soft_td_t *sc_freetds;
    139 	uhci_soft_qh_t *sc_freeqhs;
    140 	struct uhci_buffer *sc_freebuffers;
    141 
    142 	u_int8_t sc_addr;		/* device address */
    143 	u_int8_t sc_conf;		/* device configuration */
    144 
    145 	int sc_model;
    146 #define UHCI_PIIX3 1
    147 #define UHCI_PIIX4 2
    148 
    149 	char sc_isreset;
    150 
    151 	int sc_intrs;
    152 	LIST_HEAD(, uhci_intr_info) sc_intrhead;
    153 
    154 	/* Info for the root hub interrupt channel. */
    155 	int sc_ival;
    156 
    157 	char sc_vflock;
    158 #define UHCI_HAS_LOCK 1
    159 #define UHCI_WANT_LOCK 2
    160 
    161 	uhci_dma_t *sc_mallocs;
    162 } uhci_softc_t;
    163 
    164 usbd_status	uhci_init __P((uhci_softc_t *));
    165 int		uhci_intr __P((void *));
    166 #if 0
    167 void		uhci_reset __P((void *));
    168 #endif
    169 
    170 #ifdef USB_DEBUG
    171 #define DPRINTF(x)	if (uhcidebug) printf x
    172 #define DPRINTFN(n,x)	if (uhcidebug>(n)) printf x
    173 extern int uhcidebug;
    174 #else
    175 #define DPRINTF(x)
    176 #define DPRINTFN(n,x)
    177 #endif
    178 
    179