umcpmio.c revision 1.1
1 /* $NetBSD: umcpmio.c,v 1.1 2024/12/16 16:37:38 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: umcpmio.c,v 1.1 2024/12/16 16:37:38 brad Exp $"); 21 22 /* 23 Driver for the Microchip MCP2221 / MCP2221A USB multi-io chip 24 */ 25 26 #ifdef _KERNEL_OPT 27 #include "opt_usb.h" 28 #endif 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/kmem.h> 35 #include <sys/device.h> 36 #include <sys/sysctl.h> 37 #include <sys/tty.h> 38 #include <sys/file.h> 39 #include <sys/vnode.h> 40 #include <sys/kauth.h> 41 #include <sys/lwp.h> 42 43 #include <sys/gpio.h> 44 #include <dev/gpio/gpiovar.h> 45 46 #include <dev/i2c/i2cvar.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbhid.h> 50 51 #include <dev/usb/usbdi.h> 52 #include <dev/usb/usbdi_util.h> 53 #include <dev/usb/usbdevs.h> 54 #include <dev/usb/uhidev.h> 55 #include <dev/hid/hid.h> 56 57 #include <dev/usb/umcpmio.h> 58 #include <dev/usb/umcpmio_subr.h> 59 #include <dev/usb/umcpmio_hid_reports.h> 60 #include <dev/usb/umcpmio_io.h> 61 62 int umcpmio_send_report(struct umcpmio_softc *, uint8_t *, size_t, uint8_t *, int); 63 64 static const struct usb_devno umcpmio_devs[] = { 65 { USB_VENDOR_MICROCHIP, USB_PRODUCT_MICROCHIP_MCP2221 }, 66 }; 67 #define umcpmio_lookup(v, p) usb_lookup(umcpmio_devs, v, p) 68 69 static int umcpmio_match(device_t, cfdata_t, void *); 70 static void umcpmio_attach(device_t, device_t, void *); 71 static int umcpmio_detach(device_t, int); 72 static int umcpmio_activate(device_t, enum devact); 73 static int umcpmio_verify_sysctl(SYSCTLFN_ARGS); 74 static int umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS); 75 static int umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS); 76 static int umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS); 77 static int umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS); 78 79 #define UMCPMIO_DEBUG 1 80 #ifdef UMCPMIO_DEBUG 81 #define DPRINTF(x) if (umcpmiodebug) printf x 82 #define DPRINTFN(n, x) if (umcpmiodebug > (n)) printf x 83 int umcpmiodebug = 0; 84 #else 85 #define DPRINTF(x) __nothing 86 #define DPRINTFN(n,x) __nothing 87 #endif 88 89 90 CFATTACH_DECL_NEW(umcpmio, sizeof(struct umcpmio_softc), umcpmio_match, 91 umcpmio_attach, umcpmio_detach, umcpmio_activate); 92 93 94 #define WAITMS(ms) if (ms > 0) delay(ms * 1000) 95 96 extern struct cfdriver umcpmio_cd; 97 98 static dev_type_open(umcpmio_dev_open); 99 static dev_type_read(umcpmio_dev_read); 100 static dev_type_write(umcpmio_dev_write); 101 static dev_type_close(umcpmio_dev_close); 102 static dev_type_ioctl(umcpmio_dev_ioctl); 103 const struct cdevsw umcpmio_cdevsw = { 104 .d_open = umcpmio_dev_open, 105 .d_close = umcpmio_dev_close, 106 .d_read = umcpmio_dev_read, 107 .d_write = umcpmio_dev_write, 108 .d_ioctl = umcpmio_dev_ioctl, 109 .d_stop = nostop, 110 .d_tty = notty, 111 .d_poll = nopoll, 112 .d_mmap = nommap, 113 .d_kqfilter = nokqfilter, 114 .d_discard = nodiscard, 115 .d_flag = D_OTHER 116 }; 117 118 119 static const char umcpmio_valid_vrefs[] = 120 "4.096V, 2.048V, 1.024V, OFF, VDD"; 121 122 static const char umcpmio_valid_dcs[] = 123 "75%, 50%, 25%, 0%"; 124 125 static const char umcpmio_valid_cds[] = 126 "375kHz, 750kHz, 1.5MHz, 3MHz, 6MHz, 12MHz, 24MHz"; 127 128 static void 129 umcpmio_dump_buffer(bool enabled, uint8_t *buf, u_int len, const char *name) 130 { 131 if (enabled) { 132 DPRINTF(("%s:",name)); 133 for(int i=0; i < len; i++) { 134 DPRINTF((" %02x",buf[i])); 135 } 136 DPRINTF(("\n")); 137 } 138 } 139 140 /* Communication with the HID function requires sending a HID report request and 141 * then waiting for a response. 142 * 143 * The panic that occurs when trying to use the interrupt... i.e. 144 * attaching though this driver seems to be related to the fact that 145 * a spin lock is held and the USB stack wants to wait. 146 * 147 * The USB stack *IS* going to have to wait for the response from 148 * the device, somehow... 149 * 150 * It didn't seem possible to defer the uhidev_write to a thread. 151 * Attempts to yield() while spinning hard also did not work and 152 * not yield()ing didn't allow anything else to run. 153 * 154 */ 155 156 /* 157 * This is the panic you will get: 158 * 159 panic: kernel diagnostic assertion "ci->ci_mtx_count == -1" failed: file "../../../../kern/kern_synch.c", line 762 mi_switch: cpu0: ci_mtx_count (-2) != -1 (block with spin-mutex held) 160 161 */ 162 163 static void 164 umcpmio_uhidev_intr(void *cookie, void *ibuf, u_int len) 165 { 166 struct umcpmio_softc *sc = cookie; 167 168 if (sc->sc_dying) 169 return; 170 171 DPRINTFN(30,("umcpmio_uhidev_intr: len=%d\n",len)); 172 173 mutex_enter(&sc->sc_res_mutex); 174 switch(len) { 175 case MCP2221_RES_BUFFER_SIZE: 176 if (sc->sc_res_buffer != NULL) { 177 memcpy(sc->sc_res_buffer, ibuf, MCP2221_RES_BUFFER_SIZE); 178 sc->sc_res_ready = true; 179 cv_signal(&sc->sc_res_cv); 180 } else { 181 int d=umcpmiodebug; 182 device_printf(sc->sc_dev,"umcpmio_uhidev_intr: NULL sc_res_buffer: len=%d\n",len); 183 umcpmiodebug=20; 184 umcpmio_dump_buffer(true, (uint8_t *)ibuf, len, "umcpmio_uhidev_intr: ibuf"); 185 umcpmiodebug=d; 186 } 187 188 break; 189 default: 190 device_printf(sc->sc_dev,"umcpmio_uhidev_intr: Unknown interrupt length: %d",len); 191 break; 192 } 193 mutex_exit(&sc->sc_res_mutex); 194 } 195 196 /* Send a HID report. This needs to be called with the action mutex held */ 197 198 int 199 umcpmio_send_report(struct umcpmio_softc *sc, uint8_t *sendbuf, 200 size_t sendlen, uint8_t *resbuf, int timeout) 201 { 202 int err = 0; 203 int err_count=0; 204 205 if (sc->sc_dying) 206 return EIO; 207 208 KASSERT(mutex_owned(&sc->sc_action_mutex)); 209 210 if (sc->sc_res_buffer != NULL) { 211 device_printf(sc->sc_dev,"umcpmio_send_report: sc->sc_res_buffer is not NULL\n"); 212 } 213 sc->sc_res_buffer = resbuf; 214 sc->sc_res_ready = false; 215 216 err = uhidev_write(sc->sc_hdev, sendbuf, sendlen); 217 218 if (err) { 219 DPRINTF(("umcpmio_send_report: uhidev_write errored with: err=%d\n", err)); 220 goto out; 221 } 222 223 DPRINTFN(30,("umcpmio_send_report: about to wait on cv. err=%d\n", err)); 224 225 mutex_enter(&sc->sc_res_mutex); 226 while (!sc->sc_res_ready) { 227 DPRINTFN(20,("umcpmio_send_report: LOOP for response. sc_res_ready=%d, err_count=%d, timeout=%d\n",sc->sc_res_ready, err_count, mstohz(timeout))); 228 229 err = cv_timedwait_sig(&sc->sc_res_cv, &sc->sc_res_mutex, mstohz(timeout)); 230 231 /* We are only going to allow this to loop on an error, 232 * any error at all, so many times. 233 */ 234 if (err) { 235 DPRINTF(("umcpmio_send_report: cv_timedwait_sig reported an error: err=%d, sc->sc_res_ready=%d\n",err,sc->sc_res_ready)); 236 err_count++; 237 } 238 239 /* The CV was interrupted, but the buffer is ready so, clear the error 240 * and break out. 241 */ 242 if ((err == ERESTART) && (sc->sc_res_ready)) { 243 DPRINTF(("umcpmio_send_report: ERESTART and buffer is ready\n")); 244 err = 0; 245 break; 246 } 247 248 /* Too many times though the loop, just break out. Turn 249 * a ERESTART (interruption) into a I/O error at this point. 250 */ 251 if (err_count > sc->sc_response_errcnt) { 252 DPRINTF(("umcpmio_send_report: err_count exceeded: err=%d\n",err)); 253 if (err == ERESTART) 254 err = EIO; 255 break; 256 } 257 258 /* This is a normal timeout, without interruption, try again */ 259 if (err == EWOULDBLOCK) { 260 DPRINTF(("umcpmio_send_report: EWOULDBLOCK: err_count=%d\n",err_count)); 261 continue; 262 } 263 264 /* The CV was interrupted and the buffer wasn't filled in, so try again */ 265 if ((err == ERESTART) && (!sc->sc_res_ready)) { 266 DPRINTF(("umcpmio_send_report: ERESTART and buffer is NOT ready. err_count=%d\n",err_count)); 267 continue; 268 } 269 } 270 271 sc->sc_res_buffer = NULL; 272 sc->sc_res_ready = false; 273 mutex_exit(&sc->sc_res_mutex); 274 275 /* Turn most errors into an I/O error */ 276 if (err && 277 err != ERESTART) 278 err = EIO; 279 280 out: 281 return err; 282 } 283 284 /* These are standard gpio reads and set calls */ 285 286 static int 287 umcpmio_gpio_pin_read(void *arg, int pin) 288 { 289 struct umcpmio_softc *sc = arg; 290 int r = GPIO_PIN_LOW; 291 292 r = umcpmio_get_gpio_value(sc, pin, true); 293 294 return(r); 295 } 296 297 static void 298 umcpmio_gpio_pin_write(void *arg, int pin, int value) 299 { 300 struct umcpmio_softc *sc = arg; 301 302 umcpmio_set_gpio_value_one(sc, pin, value, true); 303 } 304 305 /* Internal function that does the dirty work of setting a gpio 306 * pin to its "type". 307 * 308 * There are really two ways to do some of this, one is to set the pin to input 309 * and output, or whatever, using SRAM calls, the other is to use the GPIO 310 * config calls to set input and output and SRAM for everything else. This just 311 * uses SRAM for everything. 312 */ 313 314 static int 315 umcpmio_gpio_pin_ctlctl(void *arg, int pin, int flags, bool takemutex) 316 { 317 struct umcpmio_softc *sc = arg; 318 struct mcp2221_set_sram_req set_sram_req; 319 struct mcp2221_set_sram_res set_sram_res; 320 struct mcp2221_get_sram_res current_sram_res; 321 struct mcp2221_get_gpio_cfg_res current_gpio_cfg_res; 322 int err = 0; 323 324 if (sc->sc_dying) 325 return 0; 326 327 if (takemutex) 328 mutex_enter(&sc->sc_action_mutex); 329 330 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 331 if (err) 332 goto out; 333 334 err = umcpmio_get_gpio_cfg(sc, ¤t_gpio_cfg_res, false); 335 if (err) 336 goto out; 337 338 /* You can't just set one pin, you must set all of them, so copy the 339 * current settings for the pin we are not messing with. 340 * 341 * And, yes, of course, if the MCP-2210 is ever supported with this 342 * driver, this sort of unrolling will need to be turned into 343 * something different, but for now, just unroll as there are only 344 * 4 pins to care about. 345 * 346 */ 347 348 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 349 switch (pin) { 350 case 0: 351 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 352 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 353 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 354 break; 355 case 1: 356 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 357 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 358 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 359 break; 360 case 2: 361 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 362 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 363 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 364 break; 365 case 3: 366 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 367 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 368 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 369 break; 370 } 371 umcpmio_set_gpio_designation_sram(&set_sram_req, pin, flags); 372 umcpmio_set_gpio_dir_sram(&set_sram_req, pin, flags); 373 374 /* 375 * This part is unfortunate... if a pin is set to output, the value set 376 * on the pin is not mirrored by the chip into SRAM, but the chip will 377 * use the value from SRAM to set the value of the pin. What this means is 378 * that we have to learn the value from the GPIO config and make sure it is 379 * set properly when updating SRAM. 380 */ 381 382 if (current_gpio_cfg_res.gp0_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 383 if (current_gpio_cfg_res.gp0_pin_value == 1) 384 set_sram_req.gp0_settings |= MCP2221_SRAM_GPIO_OUTPUT_HIGH; 385 else 386 set_sram_req.gp0_settings &= ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 387 } 388 if (current_gpio_cfg_res.gp1_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 389 if (current_gpio_cfg_res.gp1_pin_value == 1) 390 set_sram_req.gp1_settings |= MCP2221_SRAM_GPIO_OUTPUT_HIGH; 391 else 392 set_sram_req.gp1_settings &= ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 393 } 394 if (current_gpio_cfg_res.gp2_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 395 if (current_gpio_cfg_res.gp2_pin_value == 1) 396 set_sram_req.gp2_settings |= MCP2221_SRAM_GPIO_OUTPUT_HIGH; 397 else 398 set_sram_req.gp2_settings &= ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 399 } 400 if (current_gpio_cfg_res.gp3_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 401 if (current_gpio_cfg_res.gp3_pin_value == 1) 402 set_sram_req.gp3_settings |= MCP2221_SRAM_GPIO_OUTPUT_HIGH; 403 else 404 set_sram_req.gp3_settings &= ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 405 } 406 407 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 408 if (! err) { 409 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_gpio_pin_ctlctl set sram buffer copy"); 410 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 411 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 412 sc->sc_gpio_pins[pin].pin_flags = flags; 413 } else { 414 device_printf(sc->sc_dev, "umcpmio_gpio_pin_ctlctl: not the command desired, or error: %02x %02x\n", 415 set_sram_res.cmd, 416 set_sram_res.completion); 417 err = EIO; 418 } 419 } 420 421 out: 422 if (takemutex) 423 mutex_exit(&sc->sc_action_mutex); 424 425 return err; 426 } 427 428 static void 429 umcpmio_gpio_pin_ctl(void *arg, int pin, int flags) 430 { 431 struct umcpmio_softc *sc = arg; 432 433 if (sc->sc_dying) 434 return; 435 436 umcpmio_gpio_pin_ctlctl(sc, pin, flags, true); 437 } 438 439 /* 440 XXX - 441 442 Since testing of gpio interrupts wasn't possible, this part probably is not 443 complete. At the very least, there is a scheduled callout that needs to exist 444 to read the interrupt status. The chip does not send anything on its own when 445 the interrupt happens. 446 */ 447 448 449 static void * 450 umcpmio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 451 int (*func)(void *), void *arg) 452 { 453 struct umcpmio_softc *sc = vsc; 454 struct umcpmio_irq *irq = &sc->sc_gpio_irqs[0]; 455 struct mcp2221_set_sram_req set_sram_req; 456 struct mcp2221_set_sram_res set_sram_res; 457 struct mcp2221_get_sram_res current_sram_res; 458 int err = 0; 459 460 if (sc->sc_dying) 461 return(NULL); 462 463 irq->sc_gpio_irqfunc = func; 464 irq->sc_gpio_irqarg = arg; 465 466 DPRINTF(("umcpmio_intr_establish: pin=%d, irqmode=%04x\n",pin,irqmode)); 467 468 mutex_enter(&sc->sc_action_mutex); 469 470 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 471 if (err) 472 goto out; 473 474 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 475 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 476 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 477 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 478 umcpmio_set_gpio_irq_sram(&set_sram_req, irqmode); 479 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 480 if (! err) { 481 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_intr_establish set sram buffer copy"); 482 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 483 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 484 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_ALT2; 485 } else { 486 device_printf(sc->sc_dev, "umcpmio_intr_establish: not the command desired, or error: %02x %02x\n", 487 set_sram_res.cmd, 488 set_sram_res.completion); 489 } 490 } else { 491 device_printf(sc->sc_dev, "umcpmio_intr_establish: set sram error: err=%d\n", 492 err); 493 } 494 495 out: 496 mutex_exit(&sc->sc_action_mutex); 497 498 return(irq); 499 } 500 501 static void 502 umcpmio_gpio_intr_disestablish(void *vsc, void *ih) 503 { 504 struct umcpmio_softc *sc = vsc; 505 struct mcp2221_set_sram_req set_sram_req; 506 struct mcp2221_set_sram_res set_sram_res; 507 struct mcp2221_get_sram_res current_sram_res; 508 int err = 0; 509 510 if (sc->sc_dying) 511 return; 512 513 DPRINTF(("umcpmio_intr_disestablish:\n")); 514 515 mutex_enter(&sc->sc_action_mutex); 516 517 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 518 if (err) 519 goto out; 520 521 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 522 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 523 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 524 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 525 umcpmio_set_gpio_irq_sram(&set_sram_req, 0); 526 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, true); 527 if (! err) { 528 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_intr_disestablish set sram buffer copy"); 529 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 530 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 531 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_INPUT; 532 } else { 533 device_printf(sc->sc_dev, "umcpmio_intr_disestablish: not the command desired, or error: %02x %02x\n", 534 set_sram_res.cmd, 535 set_sram_res.completion); 536 } 537 } else { 538 device_printf(sc->sc_dev, "umcpmio_intr_disestablish: set sram error: err=%d\n", 539 err); 540 } 541 out: 542 mutex_exit(&sc->sc_action_mutex); 543 } 544 545 static bool 546 umcpmio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 547 { 548 549 if (pin < 0 || pin >= MCP2221_NPINS) { 550 DPRINTF(("umcpmio_gpio_intrstr: pin %d less than zero or too big\n",pin)); 551 return (false); 552 } 553 554 if (pin != 1) { 555 DPRINTF(("umcpmio_gpio_intrstr: pin %d was not 1\n",pin)); 556 return (false); 557 } 558 559 snprintf(buf, buflen, "GPIO %d", pin); 560 561 return (true); 562 } 563 564 /* Clear status of the I2C engine */ 565 566 static int 567 umcpmio_i2c_clear(struct umcpmio_softc *sc, bool takemutex) 568 { 569 int err = 0; 570 struct mcp2221_status_req status_req; 571 struct mcp2221_status_res status_res; 572 573 memset(&status_req, 0, MCP2221_REQ_BUFFER_SIZE); 574 status_req.cmd = MCP2221_CMD_STATUS; 575 status_req.cancel_transfer = MCP2221_I2C_DO_CANCEL; 576 577 if (takemutex) 578 mutex_enter(&sc->sc_action_mutex); 579 err = umcpmio_send_report(sc, (uint8_t *)&status_req, MCP2221_REQ_BUFFER_SIZE, (uint8_t *)&status_res, sc->sc_cv_wait); 580 if (takemutex) 581 mutex_exit(&sc->sc_action_mutex); 582 583 if (! err) { 584 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_i2c_clear buffer copy"); 585 if (status_res.cmd == MCP2221_CMD_STATUS && 586 status_res.completion == MCP2221_CMD_COMPLETE_OK) { 587 umcpmio_dump_buffer(true, (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_i2c_clear res buffer"); 588 } else { 589 device_printf(sc->sc_dev, "umcpmio_i2c_clear: cmd exec: not the command desired, or error: %02x %02x\n", 590 status_res.cmd, 591 status_res.completion); 592 err = EIO; 593 } 594 } else { 595 device_printf(sc->sc_dev, "umcpmio_i2c_clear: request error: err=%d\n", err); 596 err = EIO; 597 } 598 599 return(err); 600 } 601 602 /* There isn't much required to acquire or release the I2C bus, but the man 603 * pages says these are needed 604 */ 605 606 static int 607 umcpmio_acquire_bus(void *v, int flags) 608 { 609 return(0); 610 } 611 612 static void 613 umcpmio_release_bus(void *v, int flags) 614 { 615 return; 616 } 617 618 /* The I2C write and I2C read functions mostly use an algorithm that Adafruit 619 * came up with in their Python based driver. A lot of other people have used 620 * this same algorithm to good effect. If changes are made to the I2C read and 621 * write functions, it is HIGHLY advisable that a MCP2221 or MCP2221A be on 622 * hand to test them. 623 */ 624 625 626 /* This is what is considered a fatal return from the engine. */ 627 628 static bool 629 umcpmio_i2c_fatal(uint8_t state) 630 { 631 int r = false; 632 633 if (state == MCP2221_ENGINE_ADDRNACK || 634 state == MCP2221_ENGINE_STARTTIMEOUT || 635 state == MCP2221_ENGINE_REPSTARTTIMEOUT || 636 state == MCP2221_ENGINE_STOPTIMEOUT || 637 state == MCP2221_ENGINE_READTIMEOUT || 638 state == MCP2221_ENGINE_WRITETIMEOUT || 639 state == MCP2221_ENGINE_ADDRTIMEOUT) 640 r = true; 641 return(r); 642 } 643 644 static int 645 umcpmio_i2c_write(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 646 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int flags) 647 { 648 struct mcp2221_i2c_req i2c_req; 649 struct mcp2221_i2c_res i2c_res; 650 struct mcp2221_status_res status_res; 651 int remaining; 652 int err = 0; 653 uint8_t cmd; 654 size_t totallen = 0; 655 int wretry = sc->sc_retry_busy_write; 656 int wsretry = sc->sc_retry_busy_write; 657 658 err = umcpmio_get_status(sc, &status_res, true); 659 if (err) 660 goto out; 661 if (status_res.internal_i2c_state != 0) { 662 DPRINTF(("umcpmio_i2c_write: internal state not zero, clearing. internal_i2c_state=%02x\n",status_res.internal_i2c_state)); 663 err = umcpmio_i2c_clear(sc, true); 664 } 665 if (err) 666 goto out; 667 668 if (cmdbuf != NULL) 669 totallen += cmdlen; 670 if (databuf != NULL) 671 totallen += datalen; 672 673 again: 674 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 675 cmd = MCP2221_I2C_WRITE_DATA_NS; 676 if (I2C_OP_STOP_P(op)) 677 cmd = MCP2221_I2C_WRITE_DATA; 678 i2c_req.cmd = cmd; 679 i2c_req.lsblen = totallen; 680 i2c_req.msblen = 0; 681 i2c_req.slaveaddr = addr << 1; 682 683 remaining = 0; 684 if (cmdbuf != NULL) { 685 memcpy(&i2c_req.data[0], cmdbuf, cmdlen); 686 remaining = cmdlen; 687 } 688 if (databuf != NULL) 689 memcpy(&i2c_req.data[remaining], databuf, datalen); 690 691 DPRINTF(("umcpmio_i2c_write: I2C WRITE: cmd: %02x\n",cmd)); 692 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, "umcpmio_i2c_write: write req buffer copy"); 693 694 mutex_enter(&sc->sc_action_mutex); 695 err = umcpmio_send_report(sc, (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, (uint8_t *)&i2c_res, sc->sc_cv_wait); 696 mutex_exit(&sc->sc_action_mutex); 697 if (! err) { 698 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_i2c_write: write res buffer copy"); 699 if (i2c_res.cmd == cmd && 700 i2c_res.completion == MCP2221_CMD_COMPLETE_OK) { 701 /* Adafruit does a read back of the status at this 702 * point. We choose not to do that. That is done later 703 * anyway, and it seemed to be redundent. 704 */ 705 } else { 706 if (i2c_res.cmd == cmd && 707 i2c_res.completion == MCP2221_I2C_ENGINE_BUSY) { 708 DPRINTF(("umcpmio_i2c_write: I2C engine busy\n")); 709 710 if (umcpmio_i2c_fatal(i2c_res.internal_i2c_state)) { 711 err = EIO; 712 } else { 713 wretry--; 714 if (wretry > 0) { 715 WAITMS(sc->sc_busy_delay); 716 goto again; 717 } else { 718 err = EBUSY; 719 } 720 } 721 } else { 722 device_printf(sc->sc_dev, "umcpmio_i2c_write: not the command desired, or error: %02x %02x\n", 723 i2c_res.cmd, 724 i2c_res.completion); 725 err = EIO; 726 } 727 } 728 } else { 729 device_printf(sc->sc_dev, "umcpmio_i2c_write request error: err=%d\n", err); 730 err = EIO; 731 } 732 733 if (! err) { 734 while (wsretry > 0) { 735 wsretry--; 736 737 DPRINTF(("umcpmio_i2c_write: checking status loop: wcretry=%d\n",wsretry)); 738 739 err = umcpmio_get_status(sc, &status_res, true); 740 if (! err) { 741 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_i2c_write post check status"); 742 /* Since there isn't any documentation on what 743 * some of the internal state means, it isn't 744 * clear that this is any different than than 745 * MCP2221_ENGINE_ADDRNACK in the other state 746 * register. 747 */ 748 749 if (status_res.internal_i2c_state20 & MCP2221_ENGINE_T1_MASK_NACK) { 750 DPRINTF(("umcpmio_i2c_write post check: engine internal state T1 says NACK\n")); 751 err = EIO; 752 break; 753 } 754 if (status_res.internal_i2c_state == 0) { 755 DPRINTF(("umcpmio_i2c_write post check: engine internal state is ZERO\n")); 756 err = 0; 757 break; 758 } 759 if (status_res.internal_i2c_state == MCP2221_ENGINE_WRITINGNOSTOP && 760 cmd == MCP2221_I2C_WRITE_DATA_NS) { 761 DPRINTF(("umcpmio_i2c_write post check: engine internal state is WRITINGNOSTOP\n")); 762 err = 0; 763 break; 764 } 765 if (umcpmio_i2c_fatal(status_res.internal_i2c_state)) { 766 DPRINTF(("umcpmio_i2c_write post check: engine internal state is fatal: %02x\n", status_res.internal_i2c_state)); 767 err = EIO; 768 break; 769 } 770 WAITMS(sc->sc_busy_delay); 771 } else { 772 err = EIO; 773 break; 774 } 775 } 776 } 777 778 out: 779 780 return(err); 781 } 782 783 /* This one deviates a bit from Adafruit in that is supports a straight read and 784 * a write + read. That is, write a register to read from and then do the read. 785 */ 786 787 static int 788 umcpmio_i2c_read(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 789 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int flags) 790 { 791 struct mcp2221_i2c_req i2c_req; 792 struct mcp2221_i2c_res i2c_res; 793 struct mcp2221_i2c_fetch_req i2c_fetch_req; 794 struct mcp2221_i2c_fetch_res i2c_fetch_res; 795 struct mcp2221_status_res status_res; 796 int err = 0; 797 uint8_t cmd; 798 int rretry = sc->sc_retry_busy_read; 799 800 if (cmdbuf != NULL) { 801 DPRINTF(("umcpmio_i2c_read: has a cmdbuf, doing write first: addr=%02x\n",addr)); 802 err = umcpmio_i2c_write(sc, I2C_OP_WRITE, addr, cmdbuf, cmdlen, NULL, 0, flags); 803 } 804 if (err) 805 goto out; 806 807 err = umcpmio_get_status(sc, &status_res, true); 808 if (err) 809 goto out; 810 811 if (status_res.internal_i2c_state !=0 && 812 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 813 DPRINTF(("umcpmio_i2c_read: internal state not zero and not WRITINGNOSTOP, clearing. internal_i2c_state=%02x\n",status_res.internal_i2c_state)); 814 err = umcpmio_i2c_clear(sc, true); 815 } 816 if (err) 817 goto out; 818 819 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 820 if (cmdbuf == NULL && 821 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 822 cmd = MCP2221_I2C_READ_DATA; 823 } else { 824 cmd = MCP2221_I2C_READ_DATA_RS; 825 } 826 827 /* The chip apparently can't do a READ without a STOP operation. Report that, and try 828 * treating it like a READ with a STOP. This won't work for a lot of devices. 829 */ 830 831 if (!I2C_OP_STOP_P(op) && 832 sc->sc_reportreadnostop) 833 device_printf(sc->sc_dev,"umcpmio_i2c_read: ************ called with READ without STOP ***************\n"); 834 835 i2c_req.cmd = cmd; 836 i2c_req.lsblen = datalen; 837 i2c_req.msblen = 0; 838 i2c_req.slaveaddr = (addr << 1) | 0x01; 839 840 DPRINTF(("umcpmio_i2c_read: I2C READ normal read: cmd=%02x, addr=%02x\n",cmd,addr)); 841 842 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&i2c_req, MCP2221_RES_BUFFER_SIZE, "umcpmio_i2c_read normal read req buffer copy"); 843 844 mutex_enter(&sc->sc_action_mutex); 845 err = umcpmio_send_report(sc, (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, (uint8_t *)&i2c_res, sc->sc_cv_wait); 846 mutex_exit(&sc->sc_action_mutex); 847 848 if (! err) { 849 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_i2c_read read-request response buffer copy"); 850 851 while (rretry > 0) { 852 rretry--; 853 DPRINTF(("umcpmio_i2c_read: fetch loop: rretry=%d\n",rretry)); 854 err = 0; 855 memset(&i2c_fetch_req, 0, MCP2221_REQ_BUFFER_SIZE); 856 i2c_fetch_req.cmd = MCP2221_CMD_I2C_FETCH_READ_DATA; 857 mutex_enter(&sc->sc_action_mutex); 858 err = umcpmio_send_report(sc, (uint8_t *)&i2c_fetch_req, MCP2221_REQ_BUFFER_SIZE, (uint8_t *)&i2c_fetch_res, sc->sc_cv_wait); 859 mutex_exit(&sc->sc_action_mutex); 860 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&i2c_fetch_req, MCP2221_RES_BUFFER_SIZE, "umcpmio_i2c_read fetch res buffer copy"); 861 862 if (i2c_fetch_res.cmd == MCP2221_CMD_I2C_FETCH_READ_DATA) { 863 if (i2c_fetch_res.completion == MCP2221_FETCH_READ_PARTIALDATA || 864 i2c_fetch_res.fetchlen == MCP2221_FETCH_READERROR) { 865 DPRINTF(("umcpmio_i2c_read: fetch loop: partial data or read error: completion=%02x,fetchlen=%02x\n",i2c_fetch_res.completion,i2c_fetch_res.fetchlen)); 866 WAITMS(sc->sc_busy_delay); 867 err = EAGAIN; 868 continue; 869 } 870 if (i2c_fetch_res.internal_i2c_state == MCP2221_ENGINE_ADDRNACK) { 871 DPRINTF(("umcpmio_i2c_read: fetch loop: engine NACK\n")); 872 err = EIO; 873 break; 874 } 875 if (i2c_fetch_res.internal_i2c_state == 0 && 876 i2c_fetch_res.fetchlen == 0) { 877 DPRINTF(("umcpmio_i2c_read: fetch loop: internal state and fetch len are ZERO\n")); 878 err = 0; 879 break; 880 } 881 if (i2c_fetch_res.internal_i2c_state == MCP2221_ENGINE_READPARTIAL || 882 i2c_fetch_res.internal_i2c_state == MCP2221_ENGINE_READCOMPLETE) { 883 DPRINTF(("umcpmio_i2c_read: fetch loop: read partial or read complete: internal_i2c_state=%02x\n", i2c_fetch_res.internal_i2c_state)); 884 err = 0; 885 break; 886 } 887 } else { 888 device_printf(sc->sc_dev, "umcpmio_i2c_read: fetch2: not the command desired: %02x\n", 889 i2c_fetch_res.cmd); 890 err = EIO; 891 break; 892 } 893 } 894 if (err == EAGAIN) 895 err = ETIMEDOUT; 896 897 if (! err) { 898 if (databuf != NULL && 899 i2c_fetch_res.fetchlen != MCP2221_FETCH_READERROR) { 900 int size = uimin(i2c_fetch_res.fetchlen, datalen); 901 DPRINTF(("umcpmio_i2c_read: copy data: size=%d,fetchlen=%d\n",size, i2c_fetch_res.fetchlen)); 902 if (size > 0) 903 memcpy(databuf, &i2c_fetch_res.data[0], size); 904 } else { 905 DPRINTF(("umcpmio_i2c_read: copy data: databuf is NULL\n")); 906 } 907 } 908 } else { 909 device_printf(sc->sc_dev, "umcpmio_i2c_read request error: cmd=%02x,err=%d\n", cmd, err); 910 err = EIO; 911 } 912 out: 913 914 return(err); 915 } 916 917 static int 918 umcpmio_i2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 919 size_t cmdlen, void *databuf, size_t datalen, int flags) 920 { 921 struct umcpmio_softc *sc = v; 922 size_t totallen = 0; 923 int err = 0; 924 925 if (addr > 0x7f) 926 return (ENOTSUP); 927 928 if (cmdbuf != NULL) 929 totallen += cmdlen; 930 if (databuf != NULL) 931 totallen += datalen; 932 933 /* There is a way to do a transfer that is larger than 60 bytes, 934 * but it requires that your break the transfer up into pieces and 935 * send them in 60 byte chunks. We just won't support that right now. 936 * It would be somewhat unusual for there to be a transfer that big, 937 * unless you are trying to do block transfers and that isn't natively 938 * supported by the chip anyway... so those have to be broken up and 939 * sent as bytes. 940 */ 941 942 if (totallen > 60) 943 return (ENOTSUP); 944 945 if (I2C_OP_WRITE_P(op)) { 946 err = umcpmio_i2c_write(sc, op, addr, cmdbuf, cmdlen, databuf, datalen, flags); 947 948 DPRINTF(("umcpmio_exec: I2C WRITE: err=%d\n", err)); 949 } else { 950 err = umcpmio_i2c_read(sc, op, addr, cmdbuf, cmdlen, databuf, datalen, flags); 951 952 DPRINTF(("umcpmio_exec: I2C READ: err=%d\n", err)); 953 } 954 955 return(err); 956 } 957 958 /* Accessing the ADC and DAC part of the chip */ 959 960 #define UMCPMIO_DEV_UNIT(m) (m & 0x80 ? (m & 0x7f) / 3 : m) 961 #define UMCPMIO_DEV_WHAT(m) (m & 0x80 ? ((m & 0x7f) % 3) + 1: CONTROL_DEV) 962 963 static int 964 umcpmio_dev_open(dev_t dev, int flags, int fmt, struct lwp *l) 965 { 966 struct umcpmio_softc *sc; 967 int dunit; 968 int pin = -1; 969 int error = 0; 970 971 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 972 if (!sc) 973 return ENXIO; 974 975 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 976 977 if (sc->sc_dev_open[dunit]) { 978 DPRINTF(("umcpmio_dev_open: dunit=%d BUSY\n",dunit)); 979 return EBUSY; 980 } 981 982 /* The control device only allows for ioctl calls, so pretty much allow 983 * any sort of access. For the ADC, you perform a strict O_RDONLY and 984 * for the DAC a strict O_WRONLY. It is an error to try and do a O_RDWR 985 * It makes little sense to try and support select or poll. The ADC and 986 * DAC are always available for use. 987 */ 988 989 if (dunit != CONTROL_DEV && 990 ((flags & FREAD) && (flags & FWRITE))) { 991 DPRINTF(("umcpmio_dev_open: Not CONTROL device and trying to do READ and WRITE\n")); 992 return EINVAL; 993 } 994 995 /* Ya, this unrolling will also have to be changed if the MCP-2210 is 996 * supported. There are currently only 4 pins, so don't worry too much 997 * about it. The MCP-2210 has RAM, so there would be a fifth for it. 998 */ 999 1000 mutex_enter(&sc->sc_action_mutex); 1001 if (dunit != CONTROL_DEV) { 1002 switch (dunit) { 1003 case GP1_DEV: 1004 pin = 1; 1005 break; 1006 case GP2_DEV: 1007 pin = 2; 1008 break; 1009 case GP3_DEV: 1010 pin = 3; 1011 break; 1012 default: 1013 error = EINVAL; 1014 break; 1015 } 1016 if (! error) { 1017 /* XXX - we can probably do better here... it doesn't 1018 * remember what the pin was set to and probably should. 1019 */ 1020 if (flags & FREAD) { 1021 error = umcpmio_gpio_pin_ctlctl(sc, pin, GPIO_PIN_ALT0, false); 1022 } else { 1023 if (pin == 1) { 1024 error = EINVAL; 1025 } else { 1026 error = umcpmio_gpio_pin_ctlctl(sc, pin, GPIO_PIN_ALT1, false); 1027 } 1028 } 1029 } 1030 } 1031 if (! error) 1032 sc->sc_dev_open[dunit] = true; 1033 mutex_exit(&sc->sc_action_mutex); 1034 1035 DPRINTF(("umcpmio_dev_open: Opened dunit=%d,pin=%d,error=%d\n",dunit,pin,error)); 1036 1037 return error; 1038 } 1039 1040 /* Read an ADC value */ 1041 1042 static int 1043 umcpmio_dev_read(dev_t dev, struct uio *uio, int flags) 1044 { 1045 struct umcpmio_softc *sc; 1046 struct mcp2221_status_res status_res; 1047 int dunit; 1048 int error = 0; 1049 uint8_t adc_lsb; 1050 uint8_t adc_msb; 1051 uint16_t buf; 1052 1053 if ((sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev)))) == NULL) 1054 return ENXIO; 1055 1056 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1057 1058 if (dunit != CONTROL_DEV) { 1059 while (uio->uio_resid && 1060 !sc->sc_dying) { 1061 error = umcpmio_get_status(sc, &status_res, true); 1062 if (! error) { 1063 switch (dunit) { 1064 case GP1_DEV: 1065 adc_lsb = status_res.adc_channel0_lsb; 1066 adc_msb = status_res.adc_channel0_msb; 1067 break; 1068 case GP2_DEV: 1069 adc_lsb = status_res.adc_channel1_lsb; 1070 adc_msb = status_res.adc_channel1_msb; 1071 break; 1072 case GP3_DEV: 1073 adc_lsb = status_res.adc_channel2_lsb; 1074 adc_msb = status_res.adc_channel2_msb; 1075 break; 1076 default: 1077 error = EINVAL; 1078 break; 1079 } 1080 1081 if (! error) { 1082 if (sc->sc_dying) 1083 break; 1084 1085 buf = adc_msb << 8; 1086 buf |= adc_lsb; 1087 error = uiomove(&buf, 2, uio); 1088 } 1089 } 1090 } 1091 } else { 1092 error = EINVAL; 1093 } 1094 1095 1096 return error; 1097 } 1098 1099 /* Write to the DAC */ 1100 1101 static int 1102 umcpmio_dev_write(dev_t dev, struct uio *uio, int flags) 1103 { 1104 struct umcpmio_softc *sc; 1105 int dunit; 1106 int error = 0; 1107 1108 if ((sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev)))) == NULL) 1109 return ENXIO; 1110 1111 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1112 1113 if (dunit != CONTROL_DEV) { 1114 while (uio->uio_resid && 1115 !sc->sc_dying) { 1116 uint8_t buf; 1117 1118 if ((error = uiomove(&buf, 1, uio)) != 0) 1119 break; 1120 1121 if (sc->sc_dying) 1122 break; 1123 1124 error = umcpmio_set_dac_value_one(sc, buf, true); 1125 if (error) 1126 break; 1127 } 1128 } else { 1129 error = EINVAL; 1130 } 1131 1132 return error; 1133 } 1134 1135 /* Close everything up */ 1136 1137 static int 1138 umcpmio_dev_close(dev_t dev, int flags, int fmt, struct lwp *l) 1139 { 1140 struct umcpmio_softc *sc; 1141 int dunit; 1142 int pin; 1143 int error = 0; 1144 1145 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1146 if (sc->sc_dying) 1147 return EIO; 1148 1149 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1150 1151 mutex_enter(&sc->sc_action_mutex); 1152 if (dunit != CONTROL_DEV) { 1153 switch (dunit) { 1154 case GP1_DEV: 1155 pin = 1; 1156 break; 1157 case GP2_DEV: 1158 pin = 2; 1159 break; 1160 case GP3_DEV: 1161 pin = 3; 1162 break; 1163 default: 1164 error = EINVAL; 1165 break; 1166 } 1167 if (! error) { 1168 /* XXX - Ya, this really could be done better. Probably should 1169 * read the sram config and maybe the gpio config and save out 1170 * what the pin was set to. 1171 */ 1172 1173 error = umcpmio_gpio_pin_ctlctl(sc, pin, GPIO_PIN_INPUT, false); 1174 } 1175 } 1176 sc->sc_dev_open[dunit] = false; 1177 mutex_exit(&sc->sc_action_mutex); 1178 1179 return error; 1180 } 1181 1182 static int 1183 umcpmio_dev_ioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1184 { 1185 struct umcpmio_softc *sc; 1186 struct mcp2221_status_res get_status_res; 1187 struct mcp2221_get_sram_res get_sram_res; 1188 struct mcp2221_get_gpio_cfg_res get_gpio_cfg_res; 1189 struct mcp2221_get_flash_res get_flash_res; 1190 struct mcp2221_status_res *ioctl_get_status; 1191 struct mcp2221_get_sram_res *ioctl_get_sram; 1192 struct mcp2221_get_gpio_cfg_res *ioctl_get_gpio_cfg; 1193 struct umcpmio_ioctl_get_flash *ioctl_get_flash; 1194 struct umcpmio_ioctl_put_flash *ioctl_put_flash; 1195 struct mcp2221_put_flash_req put_flash_req; 1196 struct mcp2221_put_flash_res put_flash_res; 1197 int dunit; 1198 int error = 0; 1199 1200 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1201 if (sc->sc_dying) 1202 return EIO; 1203 1204 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1205 1206 if (dunit != CONTROL_DEV) { 1207 /* It actually is fine to call ioctl with a unsupported cmd, 1208 * but be a little noisy if debug is enabled. 1209 */ 1210 DPRINTF(("umcpmio_dev_ioctl: dunit is not the CONTROL device: dunit=%d,cmd=%ld\n",dunit,cmd)); 1211 return EINVAL; 1212 } 1213 1214 mutex_enter(&sc->sc_action_mutex); 1215 1216 switch (cmd) { 1217 /* The GET calls use a shadow buffer for each type of call. That 1218 * probably isn't actually needed and the memcpy could be avoided. 1219 * but... it is only ever 64 bytes, so maybe not a big deal. 1220 */ 1221 case UMCPMIO_GET_STATUS: 1222 ioctl_get_status = (struct mcp2221_status_res *)data; 1223 error = umcpmio_get_status(sc, &get_status_res, false); 1224 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&get_status_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_dev_ioctl: UMCPMIO_GET_STATUS: get_status_res"); 1225 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_STATUS: umcpmio_get_status error=%d\n",error)); 1226 if (! error) 1227 memcpy(ioctl_get_status, &get_status_res, MCP2221_RES_BUFFER_SIZE); 1228 break; 1229 1230 case UMCPMIO_GET_SRAM: 1231 ioctl_get_sram = (struct mcp2221_get_sram_res *)data; 1232 error = umcpmio_get_sram(sc, &get_sram_res, false); 1233 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_dev_ioctl: UMCPMIO_GET_SRAM: get_sram_res"); 1234 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_SRAM: umcpmio_get_sram error=%d\n",error)); 1235 if (! error) 1236 memcpy(ioctl_get_sram, &get_sram_res, MCP2221_RES_BUFFER_SIZE); 1237 break; 1238 1239 case UMCPMIO_GET_GP_CFG: 1240 ioctl_get_gpio_cfg = (struct mcp2221_get_gpio_cfg_res *)data; 1241 error = umcpmio_get_gpio_cfg(sc, &get_gpio_cfg_res, false); 1242 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&get_gpio_cfg_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG: get_gpio_cfg_res"); 1243 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG: umcpmio_get_gpio_cfg error=%d\n",error)); 1244 if (! error) 1245 memcpy(ioctl_get_gpio_cfg, &get_gpio_cfg_res, MCP2221_RES_BUFFER_SIZE); 1246 break; 1247 1248 case UMCPMIO_GET_FLASH: 1249 ioctl_get_flash = (struct umcpmio_ioctl_get_flash *)data; 1250 error = umcpmio_get_flash(sc, ioctl_get_flash->subcode, &get_flash_res, false); 1251 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&get_flash_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_dev_ioctl: UMCPMIO_GET_FLASH: get_flash_res"); 1252 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_FLASH: umcpmio_get_flash subcode=%d,error=%d\n",ioctl_get_flash->subcode,error)); 1253 if (! error) 1254 memcpy(&ioctl_get_flash->get_flash_res, &get_flash_res, MCP2221_RES_BUFFER_SIZE); 1255 break; 1256 1257 case UMCPMIO_PUT_FLASH: 1258 /* We only allow the flash parts related to gpio to be changed. 1259 * Bounce any attempt to do something else. Also use a shadow 1260 * buffer for the put, so we get to control just literally 1261 * everything about the write to flash. 1262 */ 1263 ioctl_put_flash = (struct umcpmio_ioctl_put_flash *)data; 1264 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH: umcpmio_put_flash subcode=%d\n",ioctl_put_flash->subcode)); 1265 if (ioctl_put_flash->subcode == MCP2221_FLASH_SUBCODE_GP) { 1266 memset(&put_flash_req, 0, MCP2221_REQ_BUFFER_SIZE); 1267 put_flash_req.subcode = ioctl_put_flash->subcode; 1268 put_flash_req.u.gp.gp0_settings = ioctl_put_flash->put_flash_req.u.gp.gp0_settings; 1269 put_flash_req.u.gp.gp1_settings = ioctl_put_flash->put_flash_req.u.gp.gp1_settings; 1270 put_flash_req.u.gp.gp2_settings = ioctl_put_flash->put_flash_req.u.gp.gp2_settings; 1271 put_flash_req.u.gp.gp3_settings = ioctl_put_flash->put_flash_req.u.gp.gp3_settings; 1272 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&ioctl_put_flash->put_flash_req, MCP2221_REQ_BUFFER_SIZE, "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH: ioctl put_flash_req"); 1273 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&put_flash_req, MCP2221_REQ_BUFFER_SIZE, "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH: put_flash_req"); 1274 memset(&put_flash_res, 0, MCP2221_RES_BUFFER_SIZE); 1275 error = umcpmio_put_flash(sc, &put_flash_req, &put_flash_res, false); 1276 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&put_flash_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH: put_flash_res"); 1277 memcpy(&ioctl_put_flash->put_flash_res, &put_flash_res, MCP2221_RES_BUFFER_SIZE); 1278 } else { 1279 error = EINVAL; 1280 } 1281 break; 1282 default: 1283 error = EINVAL; 1284 } 1285 1286 mutex_exit(&sc->sc_action_mutex); 1287 1288 return error; 1289 } 1290 1291 /* This is for sysctl variables that don't actually change the chip. */ 1292 1293 int 1294 umcpmio_verify_sysctl(SYSCTLFN_ARGS) 1295 { 1296 int error, t; 1297 struct sysctlnode node; 1298 1299 node = *rnode; 1300 t = *(int *)rnode->sysctl_data; 1301 node.sysctl_data = &t; 1302 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1303 if (error || newp == NULL) 1304 return error; 1305 1306 if (t < 0) 1307 return EINVAL; 1308 1309 *(int *)rnode->sysctl_data = t; 1310 1311 return 0; 1312 } 1313 1314 /* sysctl validation for stuff that interacts with the chip needs to happen in a 1315 * transaction. The read of the current state and the update to new state can't 1316 * allow for someone to sneak in between the two. 1317 * 1318 * We use text for the values of a lot of these variables so you don't need the 1319 * datasheet in front of you. You get to do that with umcpmioctl(8). 1320 */ 1321 1322 static struct umcpmio_sysctl_name umcpmio_vref_names[] = { 1323 { 1324 .text = "4.096V", 1325 }, 1326 { 1327 .text = "2.048V", 1328 }, 1329 { 1330 .text = "1.024V", 1331 }, 1332 { 1333 .text = "OFF", 1334 }, 1335 { 1336 .text = "VDD", 1337 } 1338 }; 1339 1340 int 1341 umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS) 1342 { 1343 char buf[UMCPMIO_VREF_NAME]; 1344 char cbuf[UMCPMIO_VREF_NAME]; 1345 struct umcpmio_softc *sc; 1346 struct sysctlnode node; 1347 int error = 0; 1348 int vrm; 1349 size_t i; 1350 struct mcp2221_get_sram_res sram_res; 1351 1352 node = *rnode; 1353 sc = node.sysctl_data; 1354 1355 mutex_enter(&sc->sc_action_mutex); 1356 1357 error = umcpmio_get_sram(sc, &sram_res, false); 1358 if (error) 1359 goto out; 1360 1361 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&sram_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_verify_dac_sysctl SRAM res buffer"); 1362 1363 if (sram_res.dac_reference_voltage & MCP2221_SRAM_DAC_IS_VRM) { 1364 vrm = sram_res.dac_reference_voltage & MCP2221_SRAM_DAC_VRM_MASK; 1365 switch (vrm) { 1366 case MCP2221_SRAM_DAC_VRM_4096V: 1367 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1368 break; 1369 case MCP2221_SRAM_DAC_VRM_2048V: 1370 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1371 break; 1372 case MCP2221_SRAM_DAC_VRM_1024V: 1373 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1374 break; 1375 case MCP2221_SRAM_DAC_VRM_OFF: 1376 default: 1377 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1378 break; 1379 } 1380 } else { 1381 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1382 } 1383 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1384 node.sysctl_data = buf; 1385 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1386 if (error || newp == NULL) 1387 goto out; 1388 1389 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1390 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1391 UMCPMIO_VREF_NAME) == 0) { 1392 break; 1393 } 1394 } 1395 1396 if (i == __arraycount(umcpmio_vref_names)) 1397 error = EINVAL; 1398 1399 if (! error) { 1400 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) != 0) { 1401 DPRINTF(("umcpmio_verify_dac_sysctl: setting DAC vref: %s\n",buf)); 1402 error = umcpmio_set_dac_vref_one(sc, buf, false); 1403 } 1404 } 1405 1406 out: 1407 mutex_exit(&sc->sc_action_mutex); 1408 return error; 1409 } 1410 1411 int 1412 umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS) 1413 { 1414 char buf[UMCPMIO_VREF_NAME]; 1415 char cbuf[UMCPMIO_VREF_NAME]; 1416 struct umcpmio_softc *sc; 1417 struct sysctlnode node; 1418 int error = 0; 1419 int vrm; 1420 size_t i; 1421 struct mcp2221_get_sram_res sram_res; 1422 1423 node = *rnode; 1424 sc = node.sysctl_data; 1425 1426 mutex_enter(&sc->sc_action_mutex); 1427 1428 error = umcpmio_get_sram(sc, &sram_res, false); 1429 if (error) 1430 goto out; 1431 1432 if (sram_res.irq_adc_reference_voltage & MCP2221_SRAM_ADC_IS_VRM) { 1433 vrm = sram_res.irq_adc_reference_voltage & MCP2221_SRAM_ADC_VRM_MASK; 1434 switch (vrm) { 1435 case MCP2221_SRAM_ADC_VRM_4096V: 1436 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1437 break; 1438 case MCP2221_SRAM_ADC_VRM_2048V: 1439 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1440 break; 1441 case MCP2221_SRAM_ADC_VRM_1024V: 1442 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1443 break; 1444 case MCP2221_SRAM_ADC_VRM_OFF: 1445 default: 1446 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1447 break; 1448 } 1449 } else { 1450 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1451 } 1452 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1453 node.sysctl_data = buf; 1454 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1455 if (error || newp == NULL) 1456 goto out; 1457 1458 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1459 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1460 UMCPMIO_VREF_NAME) == 0) { 1461 break; 1462 } 1463 } 1464 1465 if (i == __arraycount(umcpmio_vref_names)) 1466 error = EINVAL; 1467 1468 if (! error) { 1469 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) != 0) { 1470 DPRINTF(("umcpmio_verify_adc_sysctl: setting ADC vref: %s\n",buf)); 1471 error = umcpmio_set_adc_vref_one(sc, buf, false); 1472 } 1473 } 1474 1475 out: 1476 mutex_exit(&sc->sc_action_mutex); 1477 return error; 1478 } 1479 1480 static struct umcpmio_sysctl_name umcpmio_dc_names[] = { 1481 { 1482 .text = "75%", 1483 }, 1484 { 1485 .text = "50%", 1486 }, 1487 { 1488 .text = "25%", 1489 }, 1490 { 1491 .text = "0%", 1492 } 1493 }; 1494 1495 static int 1496 umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS) 1497 { 1498 char buf[UMCPMIO_VREF_NAME]; 1499 char cbuf[UMCPMIO_VREF_NAME]; 1500 struct umcpmio_softc *sc; 1501 struct sysctlnode node; 1502 int error = 0; 1503 uint8_t duty_cycle; 1504 size_t i; 1505 struct mcp2221_get_sram_res sram_res; 1506 1507 node = *rnode; 1508 sc = node.sysctl_data; 1509 1510 mutex_enter(&sc->sc_action_mutex); 1511 1512 error = umcpmio_get_sram(sc, &sram_res, false); 1513 if (error) 1514 goto out; 1515 1516 duty_cycle = sram_res.clock_divider & MCP2221_SRAM_GPIO_CLOCK_DC_MASK; 1517 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl: current duty cycle: %02x\n",duty_cycle)); 1518 switch (duty_cycle) { 1519 case MCP2221_SRAM_GPIO_CLOCK_DC_75: 1520 strncpy(buf, "75%", UMCPMIO_DC_NAME); 1521 break; 1522 case MCP2221_SRAM_GPIO_CLOCK_DC_50: 1523 strncpy(buf, "50%", UMCPMIO_DC_NAME); 1524 break; 1525 case MCP2221_SRAM_GPIO_CLOCK_DC_25: 1526 strncpy(buf, "25%", UMCPMIO_DC_NAME); 1527 break; 1528 case MCP2221_SRAM_GPIO_CLOCK_DC_0: 1529 default: 1530 strncpy(buf, "0%", UMCPMIO_DC_NAME); 1531 break; 1532 } 1533 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1534 node.sysctl_data = buf; 1535 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1536 if (error || newp == NULL) 1537 goto out; 1538 1539 for (i = 0; i < __arraycount(umcpmio_dc_names); i++) { 1540 if (strncmp(node.sysctl_data, umcpmio_dc_names[i].text, 1541 UMCPMIO_VREF_NAME) == 0) { 1542 break; 1543 } 1544 } 1545 1546 if (i == __arraycount(umcpmio_dc_names)) 1547 error = EINVAL; 1548 1549 if (! error) { 1550 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) != 0) { 1551 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl: setting GPIO clock duty cycle: %s\n",buf)); 1552 error = umcpmio_set_gpioclock_dc_one(sc, buf, false); 1553 } 1554 } 1555 1556 out: 1557 mutex_exit(&sc->sc_action_mutex); 1558 return error; 1559 } 1560 1561 1562 static struct umcpmio_sysctl_name umcpmio_cd_names[] = { 1563 { 1564 .text = "375kHz", 1565 }, 1566 { 1567 .text = "750kHz", 1568 }, 1569 { 1570 .text = "1.5MHz", 1571 }, 1572 { 1573 .text = "3MHz", 1574 }, 1575 { 1576 .text = "6MHz", 1577 }, 1578 { 1579 .text = "12MHz", 1580 }, 1581 { 1582 .text = "24MHz", 1583 } 1584 }; 1585 1586 static int 1587 umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS) 1588 { 1589 char buf[UMCPMIO_CD_NAME]; 1590 char cbuf[UMCPMIO_CD_NAME]; 1591 struct umcpmio_softc *sc; 1592 struct sysctlnode node; 1593 int error = 0; 1594 uint8_t clock_divider; 1595 size_t i; 1596 struct mcp2221_get_sram_res sram_res; 1597 1598 node = *rnode; 1599 sc = node.sysctl_data; 1600 1601 mutex_enter(&sc->sc_action_mutex); 1602 1603 error = umcpmio_get_sram(sc, &sram_res, false); 1604 if (error) 1605 goto out; 1606 1607 clock_divider = sram_res.clock_divider & MCP2221_SRAM_GPIO_CLOCK_CD_MASK; 1608 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl: current clock divider: %02x\n",clock_divider)); 1609 switch (clock_divider) { 1610 1611 case MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ: 1612 strncpy(buf, "375kHz", UMCPMIO_CD_NAME); 1613 break; 1614 case MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ: 1615 strncpy(buf, "750kHz", UMCPMIO_CD_NAME); 1616 break; 1617 case MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ: 1618 strncpy(buf, "1.5MHz", UMCPMIO_CD_NAME); 1619 break; 1620 case MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ: 1621 strncpy(buf, "3MHz", UMCPMIO_CD_NAME); 1622 break; 1623 case MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ: 1624 strncpy(buf, "6MHz", UMCPMIO_CD_NAME); 1625 break; 1626 case MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ: 1627 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1628 break; 1629 case MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ: 1630 strncpy(buf, "24MHz", UMCPMIO_CD_NAME); 1631 break; 1632 default: 1633 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1634 break; 1635 } 1636 strncpy(cbuf, buf, UMCPMIO_CD_NAME); 1637 node.sysctl_data = buf; 1638 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1639 if (error || newp == NULL) 1640 goto out; 1641 1642 for (i = 0; i < __arraycount(umcpmio_cd_names); i++) { 1643 if (strncmp(node.sysctl_data, umcpmio_cd_names[i].text, 1644 UMCPMIO_CD_NAME) == 0) { 1645 break; 1646 } 1647 } 1648 1649 if (i == __arraycount(umcpmio_cd_names)) 1650 error = EINVAL; 1651 1652 if (! error) { 1653 if (strncmp(cbuf, buf, UMCPMIO_CD_NAME) != 0) { 1654 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl: setting GPIO clock clock divider: %s\n",buf)); 1655 error = umcpmio_set_gpioclock_cd_one(sc, buf, false); 1656 } 1657 } 1658 1659 out: 1660 mutex_exit(&sc->sc_action_mutex); 1661 return error; 1662 } 1663 1664 static int 1665 umcpmio_sysctl_init(struct umcpmio_softc *sc) 1666 { 1667 int error; 1668 const struct sysctlnode *cnode; 1669 int sysctlroot_num, i2c_num, adc_dac_num, adc_num, dac_num, gpio_num; 1670 1671 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1672 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 1673 SYSCTL_DESCR("mcpmio controls"), NULL, 0, NULL, 0, CTL_HW, 1674 CTL_CREATE, CTL_EOL)) != 0) 1675 return error; 1676 1677 sysctlroot_num = cnode->sysctl_num; 1678 1679 #ifdef UMCPMIO_DEBUG 1680 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1681 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 1682 SYSCTL_DESCR("Debug level"), umcpmio_verify_sysctl, 0, 1683 &umcpmiodebug, 0, CTL_HW, sysctlroot_num, CTL_CREATE, 1684 CTL_EOL)) != 0) 1685 return error; 1686 1687 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1688 CTLFLAG_READWRITE, CTLTYPE_BOOL, "dump_buffers", 1689 SYSCTL_DESCR("Dump buffer when debugging"), NULL, 0, &sc->sc_dumpbuffer, 1690 0, CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1691 return error; 1692 #endif 1693 1694 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1695 CTLFLAG_READWRITE, CTLTYPE_INT, "response_wait", 1696 SYSCTL_DESCR("How long to wait in ms for a response for a HID report"), 1697 umcpmio_verify_sysctl, 0, &sc->sc_cv_wait, 0, CTL_HW, 1698 sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1699 return error; 1700 1701 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1702 CTLFLAG_READWRITE, CTLTYPE_INT, "response_errcnt", 1703 SYSCTL_DESCR("How many errors to allow on a response"), 1704 umcpmio_verify_sysctl, 0, &sc->sc_response_errcnt, 0, CTL_HW, 1705 sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1706 return error; 1707 1708 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1709 0, CTLTYPE_NODE, "i2c", 1710 SYSCTL_DESCR("I2C controls"), NULL, 0, NULL, 0, CTL_HW, 1711 sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1712 return error; 1713 1714 i2c_num = cnode->sysctl_num; 1715 1716 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1717 0, CTLTYPE_NODE, "adcdac", 1718 SYSCTL_DESCR("ADC and DAC controls"), NULL, 0, NULL, 0, CTL_HW, 1719 sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1720 return error; 1721 1722 adc_dac_num = cnode->sysctl_num; 1723 1724 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1725 0, CTLTYPE_NODE, "adc", 1726 SYSCTL_DESCR("ADC controls"), NULL, 0, NULL, 0, CTL_HW, 1727 sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1728 return error; 1729 1730 adc_num = cnode->sysctl_num; 1731 1732 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1733 0, CTLTYPE_NODE, "dac", 1734 SYSCTL_DESCR("DAC controls"), NULL, 0, NULL, 0, CTL_HW, 1735 sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1736 return error; 1737 1738 dac_num = cnode->sysctl_num; 1739 1740 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1741 0, CTLTYPE_NODE, "gpio", 1742 SYSCTL_DESCR("GPIO controls"), NULL, 0, NULL, 0, CTL_HW, 1743 sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1744 return error; 1745 1746 gpio_num = cnode->sysctl_num; 1747 1748 /* I2C */ 1749 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1750 CTLFLAG_READWRITE, CTLTYPE_BOOL, "reportreadnostop", 1751 SYSCTL_DESCR("Report that a READ without STOP was attempted by a device"), 1752 NULL, 0, &sc->sc_reportreadnostop, 0, CTL_HW, sysctlroot_num, i2c_num, 1753 CTL_CREATE, CTL_EOL)) != 0) 1754 return error; 1755 1756 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1757 CTLFLAG_READWRITE, CTLTYPE_INT, "busy_delay", 1758 SYSCTL_DESCR("How long to wait in ms when the I2C engine is busy"), 1759 umcpmio_verify_sysctl, 0, &sc->sc_busy_delay, 0, CTL_HW, 1760 sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 1761 return error; 1762 1763 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1764 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_read", 1765 SYSCTL_DESCR("How many times to retry a busy I2C read"), 1766 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_read, 0, CTL_HW, 1767 sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 1768 return error; 1769 1770 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1771 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_write", 1772 SYSCTL_DESCR("How many times to retry a busy I2C write"), 1773 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_write, 0, CTL_HW, 1774 sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 1775 return error; 1776 1777 /* GPIO */ 1778 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1779 CTLFLAG_READWRITE, CTLTYPE_INT, "irq_poll", 1780 SYSCTL_DESCR("How often to poll for a IRQ change"), 1781 umcpmio_verify_sysctl, 0, &sc->sc_irq_poll, 0, CTL_HW, 1782 sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 1783 return error; 1784 1785 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1786 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_duty_cycles", 1787 SYSCTL_DESCR("Valid duty cycles for GPIO clock on GP1 ALT3 duty cycle"), 1788 0, 0, __UNCONST(umcpmio_valid_dcs), 1789 sizeof(umcpmio_valid_dcs) + 1, CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 1790 return error; 1791 1792 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1793 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_duty_cycle", 1794 SYSCTL_DESCR("GPIO clock on GP1 ALT3 duty cycle"), 1795 umcpmio_verify_gpioclock_dc_sysctl, 0, (void *) sc, 1796 UMCPMIO_DC_NAME, CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 1797 return error; 1798 1799 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1800 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_dividers", 1801 SYSCTL_DESCR("Valid clock dividers for GPIO clock on GP1 with ALT3"), 1802 0, 0, __UNCONST(umcpmio_valid_cds), 1803 sizeof(umcpmio_valid_cds) + 1, CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 1804 return error; 1805 1806 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1807 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_divider", 1808 SYSCTL_DESCR("GPIO clock on GP1 ALT3 clock divider"), 1809 umcpmio_verify_gpioclock_cd_sysctl, 0, (void *) sc, 1810 UMCPMIO_CD_NAME, CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 1811 return error; 1812 1813 /* ADC and DAC */ 1814 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1815 CTLFLAG_READONLY, CTLTYPE_STRING, "vrefs", 1816 SYSCTL_DESCR("Valid vref values for ADC and DAC"), 1817 0, 0, __UNCONST(umcpmio_valid_vrefs), 1818 sizeof(umcpmio_valid_vrefs) + 1, CTL_HW, sysctlroot_num, adc_dac_num, CTL_CREATE, CTL_EOL)) != 0) 1819 return error; 1820 1821 /* ADC */ 1822 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1823 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 1824 SYSCTL_DESCR("ADC voltage reference"), 1825 umcpmio_verify_adc_sysctl, 0, (void *) sc, 1826 UMCPMIO_VREF_NAME, CTL_HW, sysctlroot_num, adc_num, CTL_CREATE, CTL_EOL)) != 0) 1827 return error; 1828 1829 /* DAC */ 1830 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1831 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 1832 SYSCTL_DESCR("DAC voltage reference"), 1833 umcpmio_verify_dac_sysctl, 0, (void *) sc, 1834 UMCPMIO_VREF_NAME, CTL_HW, sysctlroot_num, dac_num, CTL_CREATE, CTL_EOL)) != 0) 1835 return error; 1836 1837 return 0; 1838 } 1839 1840 static int 1841 umcpmio_match(device_t parent, cfdata_t match, void *aux) 1842 { 1843 struct uhidev_attach_arg *uha = aux; 1844 1845 return umcpmio_lookup(uha->uiaa->uiaa_vendor, uha->uiaa->uiaa_product) 1846 != NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 1847 } 1848 1849 1850 /* This driver could be extended to support the MCP-2210 which is MCP's USB to 1851 * SPI / gpio chip. It also appears to be a something like the PIC16F1455 used in 1852 * the MCP2221 / MCP2221A. It is likely that a lot of this could use tables to 1853 * drive behavior. 1854 */ 1855 1856 static void 1857 umcpmio_attach(device_t parent, device_t self, void *aux) 1858 { 1859 struct umcpmio_softc *sc = device_private(self); 1860 struct uhidev_attach_arg *uha = aux; 1861 struct gpiobus_attach_args gba; 1862 struct i2cbus_attach_args iba; 1863 int err; 1864 struct mcp2221_status_res status_res; 1865 1866 sc->sc_dev = self; 1867 sc->sc_hdev = uha->parent; 1868 sc->sc_udev = uha->uiaa->uiaa_device; 1869 1870 sc->sc_umcpmiolog = NULL; 1871 sc->sc_dumpbuffer = false; 1872 1873 sc->sc_reportreadnostop = true; 1874 sc->sc_cv_wait = 2500; 1875 sc->sc_response_errcnt = 5; 1876 sc->sc_busy_delay = 1; 1877 sc->sc_retry_busy_read = 50; 1878 sc->sc_retry_busy_write = 50; 1879 sc->sc_irq_poll = 10; 1880 sc->sc_dev_open[CONTROL_DEV] = sc->sc_dev_open[GP1_DEV] = sc->sc_dev_open[GP2_DEV] = sc->sc_dev_open[GP3_DEV] = false; 1881 1882 aprint_normal("\n"); 1883 1884 if ((err = umcpmio_sysctl_init(sc)) != 0) { 1885 aprint_error_dev(self, "Can't setup sysctl tree (%d)\n", err); 1886 return; 1887 } 1888 1889 mutex_init(&sc->sc_action_mutex, MUTEX_DEFAULT, IPL_NONE); 1890 cv_init(&sc->sc_res_cv, "mcpres"); 1891 mutex_init(&sc->sc_res_mutex, MUTEX_DEFAULT, IPL_NONE); 1892 sc->sc_res_buffer = NULL; 1893 sc->sc_res_ready = false; 1894 1895 err = uhidev_open(sc->sc_hdev, &umcpmio_uhidev_intr, sc); 1896 1897 /* It is not clear that this should be needed, but it was noted 1898 * that the device would sometimes not be ready if this delay 1899 * was not present. In fact, the attempts to set stuff a little 1900 * later would sometimes fail. 1901 */ 1902 1903 delay(1000); 1904 1905 if (err) 1906 aprint_error_dev(sc->sc_dev, "umcpmio_attach: open uhidev_open: err=%d\n",err); 1907 1908 if (!err) 1909 err = umcpmio_get_status(sc, &status_res, true); 1910 1911 if (!err) { 1912 aprint_normal_dev(sc->sc_dev, "Hardware revision: %d.%d, Firmware revision: %d.%d\n", 1913 status_res.mcp2221_hardware_rev_major, 1914 status_res.mcp2221_hardware_rev_minor, 1915 status_res.mcp2221_firmware_rev_major, 1916 status_res.mcp2221_firmware_rev_minor); 1917 1918 /* The datasheet suggests that it is possble for this to fail if the I2C port 1919 * is currently being used. However... since you just plugged in the chip, 1920 * the I2C port should not really be in use at that moment. In any case, try 1921 * hard to set this and don't make it fatal if it did not get set. 1922 */ 1923 int i2cspeed=0; 1924 while (! err && i2cspeed < 3) { 1925 err = umcpmio_set_i2c_speed_one(sc, I2C_SPEED_SM, true); 1926 if (err) { 1927 aprint_error_dev(sc->sc_dev, "umcpmio_attach: set I2C speed: err=%d\n", 1928 err); 1929 delay(300); 1930 } 1931 i2cspeed++; 1932 } 1933 1934 struct mcp2221_get_sram_res get_sram_res; 1935 err = umcpmio_get_sram(sc, &get_sram_res, true); 1936 1937 if (! err) { 1938 umcpmio_dump_buffer(sc->sc_dumpbuffer, (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, "umcpmio_attach get sram buffer copy"); 1939 1940 /* There are only 4 pins right now, just unroll any loops */ 1941 1942 sc->sc_gpio_pins[0].pin_num = 0; 1943 sc->sc_gpio_pins[0].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_ALT0 | GPIO_PIN_ALT3; 1944 sc->sc_gpio_pins[0].pin_flags = umcpmio_sram_gpio_to_flags(get_sram_res.gp0_settings); 1945 sc->sc_gpio_pins[0].pin_intrcaps = 0; 1946 snprintf(sc->sc_gpio_pins[0].pin_defname, 4, "GP0"); 1947 1948 sc->sc_gpio_pins[1].pin_num = 1; 1949 sc->sc_gpio_pins[1].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | GPIO_PIN_ALT2 | GPIO_PIN_ALT3; 1950 sc->sc_gpio_pins[1].pin_flags = umcpmio_sram_gpio_to_flags(get_sram_res.gp1_settings); 1951 /* XXX - lets not advertise this right now... */ 1952 #if 0 1953 sc->sc_gpio_pins[1].pin_intrcaps = GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_MPSAFE; 1954 #endif 1955 sc->sc_gpio_pins[1].pin_intrcaps = 0; 1956 snprintf(sc->sc_gpio_pins[1].pin_defname, 4, "GP1"); 1957 1958 sc->sc_gpio_pins[2].pin_num = 2; 1959 sc->sc_gpio_pins[2].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | GPIO_PIN_ALT3; 1960 sc->sc_gpio_pins[2].pin_flags = umcpmio_sram_gpio_to_flags(get_sram_res.gp2_settings); 1961 sc->sc_gpio_pins[2].pin_intrcaps = 0; 1962 snprintf(sc->sc_gpio_pins[2].pin_defname, 4, "GP2"); 1963 1964 sc->sc_gpio_pins[3].pin_num = 3; 1965 sc->sc_gpio_pins[3].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_ALT0 | GPIO_PIN_ALT1 | GPIO_PIN_ALT3; 1966 sc->sc_gpio_pins[3].pin_flags = umcpmio_sram_gpio_to_flags(get_sram_res.gp3_settings); 1967 sc->sc_gpio_pins[3].pin_intrcaps = 0; 1968 snprintf(sc->sc_gpio_pins[3].pin_defname, 4, "GP3"); 1969 1970 sc->sc_gpio_gc.gp_cookie = sc; 1971 sc->sc_gpio_gc.gp_pin_read = umcpmio_gpio_pin_read; 1972 sc->sc_gpio_gc.gp_pin_write = umcpmio_gpio_pin_write; 1973 sc->sc_gpio_gc.gp_pin_ctl = umcpmio_gpio_pin_ctl; 1974 1975 sc->sc_gpio_gc.gp_intr_establish = umcpmio_gpio_intr_establish; 1976 sc->sc_gpio_gc.gp_intr_disestablish = umcpmio_gpio_intr_disestablish; 1977 sc->sc_gpio_gc.gp_intr_str = umcpmio_gpio_intrstr; 1978 1979 1980 gba.gba_gc = &sc->sc_gpio_gc; 1981 gba.gba_pins = sc->sc_gpio_pins; 1982 gba.gba_npins = MCP2221_NPINS; 1983 1984 sc->sc_gpio_dev = config_found(self, &gba, gpiobus_print, CFARGS(.iattr = "gpiobus")); 1985 1986 iic_tag_init(&sc->sc_i2c_tag); 1987 sc->sc_i2c_tag.ic_cookie = sc; 1988 sc->sc_i2c_tag.ic_acquire_bus = umcpmio_acquire_bus; 1989 sc->sc_i2c_tag.ic_release_bus = umcpmio_release_bus; 1990 sc->sc_i2c_tag.ic_exec = umcpmio_i2c_exec; 1991 1992 memset(&iba, 0, sizeof(iba)); 1993 iba.iba_tag = &sc->sc_i2c_tag; 1994 sc->sc_i2c_dev = config_found(self, &iba, iicbus_print, CFARGS(.iattr = "i2cbus")); 1995 } else { 1996 aprint_error_dev(sc->sc_dev, "umcpmio_attach: get sram error: err=%d\n", 1997 err); 1998 } 1999 } else { 2000 aprint_error_dev(sc->sc_dev, "umcpmio_attach: open uhidev_open: err=%d\n", err); 2001 } 2002 } 2003 2004 2005 static int 2006 umcpmio_detach(device_t self, int flags) 2007 { 2008 struct umcpmio_softc *sc = device_private(self); 2009 int err; 2010 2011 DPRINTF(("umcpmio_detach: sc=%p flags=%d\n", sc, flags)); 2012 2013 mutex_enter(&sc->sc_action_mutex); 2014 sc->sc_dying = 1; 2015 2016 err = config_detach_children(self, flags); 2017 if (err) 2018 return err; 2019 2020 uhidev_close(sc->sc_hdev); 2021 2022 mutex_destroy(&sc->sc_res_mutex); 2023 cv_destroy(&sc->sc_res_cv); 2024 2025 sysctl_teardown(&sc->sc_umcpmiolog); 2026 2027 mutex_exit(&sc->sc_action_mutex); 2028 mutex_destroy(&sc->sc_action_mutex); 2029 2030 return 0; 2031 } 2032 2033 static int 2034 umcpmio_activate(device_t self, enum devact act) 2035 { 2036 struct umcpmio_softc *sc = device_private(self); 2037 2038 DPRINTFN(5,("umcpmio_activate: %d\n", act)); 2039 2040 switch (act) { 2041 case DVACT_DEACTIVATE: 2042 sc->sc_dying = 1; 2043 return 0; 2044 default: 2045 return EOPNOTSUPP; 2046 } 2047 } 2048
Indexes created Mon Sep 22 05:09:51 GMT 2025