umcpmio.c revision 1.2
1 /* $NetBSD: umcpmio.c,v 1.2 2025/03/17 18:24:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: umcpmio.c,v 1.2 2025/03/17 18:24:08 riastradh Exp $"); 21 22 /* 23 * Driver for the Microchip MCP2221 / MCP2221A USB multi-io chip 24 */ 25 26 #ifdef _KERNEL_OPT 27 #include "opt_usb.h" 28 #endif 29 30 #include <sys/param.h> 31 #include <sys/types.h> 32 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/file.h> 36 #include <sys/gpio.h> 37 #include <sys/kauth.h> 38 #include <sys/kernel.h> 39 #include <sys/kmem.h> 40 #include <sys/lwp.h> 41 #include <sys/sysctl.h> 42 #include <sys/systm.h> 43 #include <sys/tty.h> 44 #include <sys/vnode.h> 45 46 #include <dev/i2c/i2cvar.h> 47 48 #include <dev/gpio/gpiovar.h> 49 50 #include <dev/hid/hid.h> 51 52 #include <dev/usb/uhidev.h> 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdevs.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbhid.h> 58 59 #include <dev/usb/umcpmio.h> 60 #include <dev/usb/umcpmio_hid_reports.h> 61 #include <dev/usb/umcpmio_io.h> 62 #include <dev/usb/umcpmio_subr.h> 63 64 int umcpmio_send_report(struct umcpmio_softc *, uint8_t *, size_t, uint8_t *, 65 int); 66 67 static const struct usb_devno umcpmio_devs[] = { 68 { USB_VENDOR_MICROCHIP, USB_PRODUCT_MICROCHIP_MCP2221 }, 69 }; 70 #define umcpmio_lookup(v, p) usb_lookup(umcpmio_devs, v, p) 71 72 static int umcpmio_match(device_t, cfdata_t, void *); 73 static void umcpmio_attach(device_t, device_t, void *); 74 static int umcpmio_detach(device_t, int); 75 static int umcpmio_activate(device_t, enum devact); 76 static int umcpmio_verify_sysctl(SYSCTLFN_ARGS); 77 static int umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS); 78 static int umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS); 79 static int umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS); 80 static int umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS); 81 82 #define UMCPMIO_DEBUG 1 83 #ifdef UMCPMIO_DEBUG 84 #define DPRINTF(x) do { if (umcpmiodebug) printf x; } while (0) 85 #define DPRINTFN(n, x) do { if (umcpmiodebug > (n)) printf x; } while (0) 86 int umcpmiodebug = 0; 87 #else 88 #define DPRINTF(x) __nothing 89 #define DPRINTFN(n, x) __nothing 90 #endif 91 92 CFATTACH_DECL_NEW(umcpmio, sizeof(struct umcpmio_softc), umcpmio_match, 93 umcpmio_attach, umcpmio_detach, umcpmio_activate); 94 95 static void 96 WAITMS(int ms) 97 { 98 if (ms > 0) 99 delay(ms * 1000); 100 } 101 102 extern struct cfdriver umcpmio_cd; 103 104 static dev_type_open(umcpmio_dev_open); 105 static dev_type_read(umcpmio_dev_read); 106 static dev_type_write(umcpmio_dev_write); 107 static dev_type_close(umcpmio_dev_close); 108 static dev_type_ioctl(umcpmio_dev_ioctl); 109 110 const struct cdevsw umcpmio_cdevsw = { 111 .d_open = umcpmio_dev_open, 112 .d_close = umcpmio_dev_close, 113 .d_read = umcpmio_dev_read, 114 .d_write = umcpmio_dev_write, 115 .d_ioctl = umcpmio_dev_ioctl, 116 .d_stop = nostop, 117 .d_tty = notty, 118 .d_poll = nopoll, 119 .d_mmap = nommap, 120 .d_kqfilter = nokqfilter, 121 .d_discard = nodiscard, 122 .d_flag = D_OTHER 123 }; 124 125 static const char umcpmio_valid_vrefs[] = 126 "4.096V, 2.048V, 1.024V, OFF, VDD"; 127 128 static const char umcpmio_valid_dcs[] = 129 "75%, 50%, 25%, 0%"; 130 131 static const char umcpmio_valid_cds[] = 132 "375kHz, 750kHz, 1.5MHz, 3MHz, 6MHz, 12MHz, 24MHz"; 133 134 static void 135 umcpmio_dump_buffer(bool enabled, uint8_t *buf, u_int len, const char *name) 136 { 137 int i; 138 139 if (enabled) { 140 DPRINTF(("%s:", name)); 141 for (i = 0; i < len; i++) { 142 DPRINTF((" %02x", buf[i])); 143 } 144 DPRINTF(("\n")); 145 } 146 } 147 148 /* 149 * Communication with the HID function requires sending a HID report 150 * request and then waiting for a response. 151 * 152 * The panic that occurs when trying to use the interrupt... i.e. 153 * attaching though this driver seems to be related to the fact that 154 * a spin lock is held and the USB stack wants to wait. 155 * 156 * The USB stack *IS* going to have to wait for the response from 157 * the device, somehow... 158 * 159 * It didn't seem possible to defer the uhidev_write to a thread. 160 * Attempts to yield() while spinning hard also did not work and 161 * not yield()ing didn't allow anything else to run. 162 * 163 */ 164 165 /* 166 * This is the panic you will get: 167 * 168 * panic: kernel diagnostic assertion "ci->ci_mtx_count == -1" failed: file "../../../../kern/kern_synch.c", line 762 mi_switch: cpu0: ci_mtx_count (-2) != -1 (block with spin-mutex held) 169 */ 170 171 static void 172 umcpmio_uhidev_intr(void *cookie, void *ibuf, u_int len) 173 { 174 struct umcpmio_softc *sc = cookie; 175 176 if (sc->sc_dying) 177 return; 178 179 DPRINTFN(30, ("umcpmio_uhidev_intr: len=%d\n", len)); 180 181 mutex_enter(&sc->sc_res_mutex); 182 switch(len) { 183 case MCP2221_RES_BUFFER_SIZE: 184 if (sc->sc_res_buffer != NULL) { 185 memcpy(sc->sc_res_buffer, ibuf, 186 MCP2221_RES_BUFFER_SIZE); 187 sc->sc_res_ready = true; 188 cv_signal(&sc->sc_res_cv); 189 } else { 190 int d = umcpmiodebug; 191 device_printf(sc->sc_dev, 192 "umcpmio_uhidev_intr: NULL sc_res_buffer:" 193 " len=%d\n", 194 len); 195 umcpmiodebug = 20; 196 umcpmio_dump_buffer(true, (uint8_t *)ibuf, len, 197 "umcpmio_uhidev_intr: ibuf"); 198 umcpmiodebug = d; 199 } 200 201 break; 202 default: 203 device_printf(sc->sc_dev, 204 "umcpmio_uhidev_intr: Unknown interrupt length: %d", 205 len); 206 break; 207 } 208 mutex_exit(&sc->sc_res_mutex); 209 } 210 211 /* Send a HID report. This needs to be called with the action mutex held */ 212 213 int 214 umcpmio_send_report(struct umcpmio_softc *sc, uint8_t *sendbuf, 215 size_t sendlen, uint8_t *resbuf, int timeout) 216 { 217 int err = 0; 218 int err_count = 0; 219 220 if (sc->sc_dying) 221 return EIO; 222 223 KASSERT(mutex_owned(&sc->sc_action_mutex)); 224 225 if (sc->sc_res_buffer != NULL) { 226 device_printf(sc->sc_dev, 227 "umcpmio_send_report: sc->sc_res_buffer is not NULL\n"); 228 } 229 sc->sc_res_buffer = resbuf; 230 sc->sc_res_ready = false; 231 232 err = uhidev_write(sc->sc_hdev, sendbuf, sendlen); 233 234 if (err) { 235 DPRINTF(("umcpmio_send_report: uhidev_write errored with:" 236 " err=%d\n", err)); 237 goto out; 238 } 239 240 DPRINTFN(30, ("umcpmio_send_report: about to wait on cv. err=%d\n", 241 err)); 242 243 mutex_enter(&sc->sc_res_mutex); 244 while (!sc->sc_res_ready) { 245 DPRINTFN(20, ("umcpmio_send_report: LOOP for response." 246 " sc_res_ready=%d, err_count=%d, timeout=%d\n", 247 sc->sc_res_ready, err_count, mstohz(timeout))); 248 249 err = cv_timedwait_sig(&sc->sc_res_cv, &sc->sc_res_mutex, 250 mstohz(timeout)); 251 252 /* 253 * We are only going to allow this to loop on an error, 254 * any error at all, so many times. 255 */ 256 if (err) { 257 DPRINTF(("umcpmio_send_report:" 258 " cv_timedwait_sig reported an error:" 259 " err=%d, sc->sc_res_ready=%d\n", 260 err, sc->sc_res_ready)); 261 err_count++; 262 } 263 264 /* 265 * The CV was interrupted, but the buffer is ready so, 266 * clear the error and break out. 267 */ 268 if ((err == ERESTART) && (sc->sc_res_ready)) { 269 DPRINTF(("umcpmio_send_report:" 270 " ERESTART and buffer is ready\n")); 271 err = 0; 272 break; 273 } 274 275 /* 276 * Too many times though the loop, just break out. Turn 277 * a ERESTART (interruption) into a I/O error at this point. 278 */ 279 if (err_count > sc->sc_response_errcnt) { 280 DPRINTF(("umcpmio_send_report: err_count exceeded:" 281 " err=%d\n", err)); 282 if (err == ERESTART) 283 err = EIO; 284 break; 285 } 286 287 /* This is a normal timeout, without interruption, try again */ 288 if (err == EWOULDBLOCK) { 289 DPRINTF(("umcpmio_send_report: EWOULDBLOCK:" 290 " err_count=%d\n", err_count)); 291 continue; 292 } 293 294 /* 295 * The CV was interrupted and the buffer wasn't filled 296 * in, so try again 297 */ 298 if ((err == ERESTART) && (!sc->sc_res_ready)) { 299 DPRINTF(("umcpmio_send_report:" 300 " ERESTART and buffer is NOT ready." 301 " err_count=%d\n", err_count)); 302 continue; 303 } 304 } 305 306 sc->sc_res_buffer = NULL; 307 sc->sc_res_ready = false; 308 mutex_exit(&sc->sc_res_mutex); 309 310 /* Turn most errors into an I/O error */ 311 if (err && 312 err != ERESTART) 313 err = EIO; 314 315 out: 316 return err; 317 } 318 319 /* These are standard gpio reads and set calls */ 320 321 static int 322 umcpmio_gpio_pin_read(void *arg, int pin) 323 { 324 struct umcpmio_softc *sc = arg; 325 int r = GPIO_PIN_LOW; 326 327 r = umcpmio_get_gpio_value(sc, pin, true); 328 329 return r; 330 } 331 332 static void 333 umcpmio_gpio_pin_write(void *arg, int pin, int value) 334 { 335 struct umcpmio_softc *sc = arg; 336 337 umcpmio_set_gpio_value_one(sc, pin, value, true); 338 } 339 340 /* 341 * Internal function that does the dirty work of setting a gpio 342 * pin to its "type". 343 * 344 * There are really two ways to do some of this, one is to set the pin 345 * to input and output, or whatever, using SRAM calls, the other is to 346 * use the GPIO config calls to set input and output and SRAM for 347 * everything else. This just uses SRAM for everything. 348 */ 349 350 static int 351 umcpmio_gpio_pin_ctlctl(void *arg, int pin, int flags, bool takemutex) 352 { 353 struct umcpmio_softc *sc = arg; 354 struct mcp2221_set_sram_req set_sram_req; 355 struct mcp2221_set_sram_res set_sram_res; 356 struct mcp2221_get_sram_res current_sram_res; 357 struct mcp2221_get_gpio_cfg_res current_gpio_cfg_res; 358 int err = 0; 359 360 if (sc->sc_dying) 361 return 0; 362 363 if (takemutex) 364 mutex_enter(&sc->sc_action_mutex); 365 366 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 367 if (err) 368 goto out; 369 370 err = umcpmio_get_gpio_cfg(sc, ¤t_gpio_cfg_res, false); 371 if (err) 372 goto out; 373 374 /* 375 * You can't just set one pin, you must set all of them, so copy the 376 * current settings for the pin we are not messing with. 377 * 378 * And, yes, of course, if the MCP-2210 is ever supported with this 379 * driver, this sort of unrolling will need to be turned into 380 * something different, but for now, just unroll as there are only 381 * 4 pins to care about. 382 * 383 */ 384 385 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 386 switch (pin) { 387 case 0: 388 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 389 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 390 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 391 break; 392 case 1: 393 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 394 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 395 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 396 break; 397 case 2: 398 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 399 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 400 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 401 break; 402 case 3: 403 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 404 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 405 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 406 break; 407 } 408 umcpmio_set_gpio_designation_sram(&set_sram_req, pin, flags); 409 umcpmio_set_gpio_dir_sram(&set_sram_req, pin, flags); 410 411 /* 412 * This part is unfortunate... if a pin is set to output, the 413 * value set on the pin is not mirrored by the chip into SRAM, 414 * but the chip will use the value from SRAM to set the value of 415 * the pin. What this means is that we have to learn the value 416 * from the GPIO config and make sure it is set properly when 417 * updating SRAM. 418 */ 419 420 if (current_gpio_cfg_res.gp0_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 421 if (current_gpio_cfg_res.gp0_pin_value == 1) { 422 set_sram_req.gp0_settings |= 423 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 424 } else { 425 set_sram_req.gp0_settings &= 426 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 427 } 428 } 429 if (current_gpio_cfg_res.gp1_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 430 if (current_gpio_cfg_res.gp1_pin_value == 1) { 431 set_sram_req.gp1_settings |= 432 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 433 } else { 434 set_sram_req.gp1_settings &= 435 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 436 } 437 } 438 if (current_gpio_cfg_res.gp2_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 439 if (current_gpio_cfg_res.gp2_pin_value == 1) { 440 set_sram_req.gp2_settings |= 441 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 442 } else { 443 set_sram_req.gp2_settings &= 444 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 445 } 446 } 447 if (current_gpio_cfg_res.gp3_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 448 if (current_gpio_cfg_res.gp3_pin_value == 1) { 449 set_sram_req.gp3_settings |= 450 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 451 } else { 452 set_sram_req.gp3_settings &= 453 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 454 } 455 } 456 457 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 458 if (! err) { 459 umcpmio_dump_buffer(sc->sc_dumpbuffer, 460 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 461 "umcpmio_gpio_pin_ctlctl set sram buffer copy"); 462 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 463 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 464 sc->sc_gpio_pins[pin].pin_flags = flags; 465 } else { 466 device_printf(sc->sc_dev, "umcpmio_gpio_pin_ctlctl:" 467 " not the command desired, or error: %02x %02x\n", 468 set_sram_res.cmd, 469 set_sram_res.completion); 470 err = EIO; 471 } 472 } 473 474 out: 475 if (takemutex) 476 mutex_exit(&sc->sc_action_mutex); 477 478 return err; 479 } 480 481 static void 482 umcpmio_gpio_pin_ctl(void *arg, int pin, int flags) 483 { 484 struct umcpmio_softc *sc = arg; 485 486 if (sc->sc_dying) 487 return; 488 489 umcpmio_gpio_pin_ctlctl(sc, pin, flags, true); 490 } 491 492 /* 493 * XXX - 494 * 495 * Since testing of gpio interrupts wasn't possible, this part probably 496 * is not complete. At the very least, there is a scheduled callout 497 * that needs to exist to read the interrupt status. The chip does not 498 * send anything on its own when the interrupt happens. 499 */ 500 501 static void * 502 umcpmio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 503 int (*func)(void *), void *arg) 504 { 505 struct umcpmio_softc *sc = vsc; 506 struct umcpmio_irq *irq = &sc->sc_gpio_irqs[0]; 507 struct mcp2221_set_sram_req set_sram_req; 508 struct mcp2221_set_sram_res set_sram_res; 509 struct mcp2221_get_sram_res current_sram_res; 510 int err = 0; 511 512 if (sc->sc_dying) 513 return NULL; 514 515 irq->sc_gpio_irqfunc = func; 516 irq->sc_gpio_irqarg = arg; 517 518 DPRINTF(("umcpmio_intr_establish: pin=%d, irqmode=%04x\n", 519 pin, irqmode)); 520 521 mutex_enter(&sc->sc_action_mutex); 522 523 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 524 if (err) 525 goto out; 526 527 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 528 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 529 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 530 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 531 umcpmio_set_gpio_irq_sram(&set_sram_req, irqmode); 532 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 533 if (! err) { 534 umcpmio_dump_buffer(sc->sc_dumpbuffer, 535 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 536 "umcpmio_intr_establish set sram buffer copy"); 537 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 538 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 539 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_ALT2; 540 } else { 541 device_printf(sc->sc_dev, "umcpmio_intr_establish:" 542 " not the command desired, or error: %02x %02x\n", 543 set_sram_res.cmd, 544 set_sram_res.completion); 545 } 546 } else { 547 device_printf(sc->sc_dev, "umcpmio_intr_establish:" 548 " set sram error: err=%d\n", 549 err); 550 } 551 552 out: 553 mutex_exit(&sc->sc_action_mutex); 554 555 return irq; 556 } 557 558 static void 559 umcpmio_gpio_intr_disestablish(void *vsc, void *ih) 560 { 561 struct umcpmio_softc *sc = vsc; 562 struct mcp2221_set_sram_req set_sram_req; 563 struct mcp2221_set_sram_res set_sram_res; 564 struct mcp2221_get_sram_res current_sram_res; 565 int err = 0; 566 567 if (sc->sc_dying) 568 return; 569 570 DPRINTF(("umcpmio_intr_disestablish:\n")); 571 572 mutex_enter(&sc->sc_action_mutex); 573 574 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 575 if (err) 576 goto out; 577 578 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 579 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 580 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 581 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 582 umcpmio_set_gpio_irq_sram(&set_sram_req, 0); 583 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, true); 584 if (! err) { 585 umcpmio_dump_buffer(sc->sc_dumpbuffer, 586 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 587 "umcpmio_intr_disestablish set sram buffer copy"); 588 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 589 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 590 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_INPUT; 591 } else { 592 device_printf(sc->sc_dev, "umcpmio_intr_disestablish:" 593 " not the command desired, or error: %02x %02x\n", 594 set_sram_res.cmd, 595 set_sram_res.completion); 596 } 597 } else { 598 device_printf(sc->sc_dev, "umcpmio_intr_disestablish:" 599 " set sram error: err=%d\n", 600 err); 601 } 602 out: 603 mutex_exit(&sc->sc_action_mutex); 604 } 605 606 static bool 607 umcpmio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 608 { 609 610 if (pin < 0 || pin >= MCP2221_NPINS) { 611 DPRINTF(("umcpmio_gpio_intrstr:" 612 " pin %d less than zero or too big\n", 613 pin)); 614 return false; 615 } 616 617 if (pin != 1) { 618 DPRINTF(("umcpmio_gpio_intrstr: pin %d was not 1\n", 619 pin)); 620 return false; 621 } 622 623 snprintf(buf, buflen, "GPIO %d", pin); 624 625 return true; 626 } 627 628 /* Clear status of the I2C engine */ 629 630 static int 631 umcpmio_i2c_clear(struct umcpmio_softc *sc, bool takemutex) 632 { 633 int err = 0; 634 struct mcp2221_status_req status_req; 635 struct mcp2221_status_res status_res; 636 637 memset(&status_req, 0, MCP2221_REQ_BUFFER_SIZE); 638 status_req.cmd = MCP2221_CMD_STATUS; 639 status_req.cancel_transfer = MCP2221_I2C_DO_CANCEL; 640 641 if (takemutex) 642 mutex_enter(&sc->sc_action_mutex); 643 err = umcpmio_send_report(sc, 644 (uint8_t *)&status_req, MCP2221_REQ_BUFFER_SIZE, 645 (uint8_t *)&status_res, sc->sc_cv_wait); 646 if (takemutex) 647 mutex_exit(&sc->sc_action_mutex); 648 649 if (! err) { 650 umcpmio_dump_buffer(sc->sc_dumpbuffer, 651 (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, 652 "umcpmio_i2c_clear buffer copy"); 653 if (status_res.cmd == MCP2221_CMD_STATUS && 654 status_res.completion == MCP2221_CMD_COMPLETE_OK) { 655 umcpmio_dump_buffer(true, 656 (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, 657 "umcpmio_i2c_clear res buffer"); 658 } else { 659 device_printf(sc->sc_dev, "umcpmio_i2c_clear:" 660 " cmd exec: not the command desired, or error:" 661 " %02x %02x\n", 662 status_res.cmd, 663 status_res.completion); 664 err = EIO; 665 } 666 } else { 667 device_printf(sc->sc_dev, "umcpmio_i2c_clear: request error:" 668 " err=%d\n", err); 669 err = EIO; 670 } 671 672 return err; 673 } 674 675 /* 676 * There isn't much required to acquire or release the I2C bus, but the man 677 * pages says these are needed 678 */ 679 680 static int 681 umcpmio_acquire_bus(void *v, int flags) 682 { 683 return 0; 684 } 685 686 static void 687 umcpmio_release_bus(void *v, int flags) 688 { 689 return; 690 } 691 692 /* 693 * The I2C write and I2C read functions mostly use an algorithm that Adafruit 694 * came up with in their Python based driver. A lot of other people have used 695 * this same algorithm to good effect. If changes are made to the I2C read and 696 * write functions, it is HIGHLY advisable that a MCP2221 or MCP2221A be on 697 * hand to test them. 698 */ 699 700 /* This is what is considered a fatal return from the engine. */ 701 702 static bool 703 umcpmio_i2c_fatal(uint8_t state) 704 { 705 int r = false; 706 707 if (state == MCP2221_ENGINE_ADDRNACK || 708 state == MCP2221_ENGINE_STARTTIMEOUT || 709 state == MCP2221_ENGINE_REPSTARTTIMEOUT || 710 state == MCP2221_ENGINE_STOPTIMEOUT || 711 state == MCP2221_ENGINE_READTIMEOUT || 712 state == MCP2221_ENGINE_WRITETIMEOUT || 713 state == MCP2221_ENGINE_ADDRTIMEOUT) 714 r = true; 715 return r; 716 } 717 718 static int 719 umcpmio_i2c_write(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 720 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, 721 int flags) 722 { 723 struct mcp2221_i2c_req i2c_req; 724 struct mcp2221_i2c_res i2c_res; 725 struct mcp2221_status_res status_res; 726 int remaining; 727 int err = 0; 728 uint8_t cmd; 729 size_t totallen = 0; 730 int wretry = sc->sc_retry_busy_write; 731 int wsretry = sc->sc_retry_busy_write; 732 733 err = umcpmio_get_status(sc, &status_res, true); 734 if (err) 735 goto out; 736 if (status_res.internal_i2c_state != 0) { 737 DPRINTF(("umcpmio_i2c_write: internal state not zero," 738 " clearing. internal_i2c_state=%02x\n", 739 status_res.internal_i2c_state)); 740 err = umcpmio_i2c_clear(sc, true); 741 } 742 if (err) 743 goto out; 744 745 if (cmdbuf != NULL) 746 totallen += cmdlen; 747 if (databuf != NULL) 748 totallen += datalen; 749 750 again: 751 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 752 cmd = MCP2221_I2C_WRITE_DATA_NS; 753 if (I2C_OP_STOP_P(op)) 754 cmd = MCP2221_I2C_WRITE_DATA; 755 i2c_req.cmd = cmd; 756 i2c_req.lsblen = totallen; 757 i2c_req.msblen = 0; 758 i2c_req.slaveaddr = addr << 1; 759 760 remaining = 0; 761 if (cmdbuf != NULL) { 762 memcpy(&i2c_req.data[0], cmdbuf, cmdlen); 763 remaining = cmdlen; 764 } 765 if (databuf != NULL) 766 memcpy(&i2c_req.data[remaining], databuf, datalen); 767 768 DPRINTF(("umcpmio_i2c_write: I2C WRITE: cmd: %02x\n", cmd)); 769 umcpmio_dump_buffer(sc->sc_dumpbuffer, 770 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 771 "umcpmio_i2c_write: write req buffer copy"); 772 773 mutex_enter(&sc->sc_action_mutex); 774 err = umcpmio_send_report(sc, 775 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 776 (uint8_t *)&i2c_res, sc->sc_cv_wait); 777 mutex_exit(&sc->sc_action_mutex); 778 if (! err) { 779 umcpmio_dump_buffer(sc->sc_dumpbuffer, 780 (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, 781 "umcpmio_i2c_write: write res buffer copy"); 782 if (i2c_res.cmd == cmd && 783 i2c_res.completion == MCP2221_CMD_COMPLETE_OK) { 784 /* 785 * Adafruit does a read back of the status at 786 * this point. We choose not to do that. That 787 * is done later anyway, and it seemed to be 788 * redundent. 789 */ 790 } else { 791 if (i2c_res.cmd == cmd && 792 i2c_res.completion == MCP2221_I2C_ENGINE_BUSY) { 793 DPRINTF(("umcpmio_i2c_write:" 794 " I2C engine busy\n")); 795 796 const uint8_t state = 797 i2c_res.internal_i2c_state; 798 if (umcpmio_i2c_fatal(state)) { 799 err = EIO; 800 } else { 801 wretry--; 802 if (wretry > 0) { 803 WAITMS(sc->sc_busy_delay); 804 goto again; 805 } else { 806 err = EBUSY; 807 } 808 } 809 } else { 810 device_printf(sc->sc_dev, "umcpmio_i2c_write:" 811 " not the command desired, or error:" 812 " %02x %02x\n", 813 i2c_res.cmd, 814 i2c_res.completion); 815 err = EIO; 816 } 817 } 818 } else { 819 device_printf(sc->sc_dev, "umcpmio_i2c_write request error:" 820 " err=%d\n", err); 821 err = EIO; 822 } 823 824 if (! err) { 825 while (wsretry > 0) { 826 wsretry--; 827 828 DPRINTF(("umcpmio_i2c_write: checking status loop:" 829 " wcretry=%d\n", wsretry)); 830 831 err = umcpmio_get_status(sc, &status_res, true); 832 if (! err) { 833 umcpmio_dump_buffer(sc->sc_dumpbuffer, 834 (uint8_t *)&status_res, 835 MCP2221_RES_BUFFER_SIZE, 836 "umcpmio_i2c_write post check status"); 837 /* 838 * Since there isn't any documentation on what 839 * some of the internal state means, it isn't 840 * clear that this is any different than than 841 * MCP2221_ENGINE_ADDRNACK in the other state 842 * register. 843 */ 844 845 const uint8_t state20 = 846 status_res.internal_i2c_state20; 847 if (state20 & MCP2221_ENGINE_T1_MASK_NACK) { 848 DPRINTF(("umcpmio_i2c_write" 849 " post check:" 850 " engine internal state T1" 851 " says NACK\n")); 852 err = EIO; 853 break; 854 } 855 if (status_res.internal_i2c_state == 0) { 856 DPRINTF(("umcpmio_i2c_write" 857 " post check:" 858 " engine internal state" 859 " is ZERO\n")); 860 err = 0; 861 break; 862 } 863 if (status_res.internal_i2c_state == 864 MCP2221_ENGINE_WRITINGNOSTOP && 865 cmd == MCP2221_I2C_WRITE_DATA_NS) { 866 DPRINTF(("umcpmio_i2c_write" 867 " post check:" 868 " engine internal state" 869 " is WRITINGNOSTOP\n")); 870 err = 0; 871 break; 872 } 873 const uint8_t state = 874 status_res.internal_i2c_state; 875 if (umcpmio_i2c_fatal(state)) { 876 DPRINTF(("umcpmio_i2c_write" 877 " post check:" 878 " engine internal state" 879 " is fatal: %02x\n", 880 state)); 881 err = EIO; 882 break; 883 } 884 WAITMS(sc->sc_busy_delay); 885 } else { 886 err = EIO; 887 break; 888 } 889 } 890 } 891 892 out: 893 return err; 894 } 895 896 /* 897 * This one deviates a bit from Adafruit in that is supports a straight 898 * read and a write + read. That is, write a register to read from and 899 * then do the read. 900 */ 901 902 static int 903 umcpmio_i2c_read(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 904 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int 905 flags) 906 { 907 struct mcp2221_i2c_req i2c_req; 908 struct mcp2221_i2c_res i2c_res; 909 struct mcp2221_i2c_fetch_req i2c_fetch_req; 910 struct mcp2221_i2c_fetch_res i2c_fetch_res; 911 struct mcp2221_status_res status_res; 912 int err = 0; 913 uint8_t cmd; 914 int rretry = sc->sc_retry_busy_read; 915 916 if (cmdbuf != NULL) { 917 DPRINTF(("umcpmio_i2c_read: has a cmdbuf, doing write first:" 918 " addr=%02x\n", addr)); 919 err = umcpmio_i2c_write(sc, I2C_OP_WRITE, addr, cmdbuf, cmdlen, 920 NULL, 0, flags); 921 } 922 if (err) 923 goto out; 924 925 err = umcpmio_get_status(sc, &status_res, true); 926 if (err) 927 goto out; 928 929 if (status_res.internal_i2c_state != 0 && 930 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 931 DPRINTF(("umcpmio_i2c_read:" 932 " internal state not zero and not WRITINGNOSTOP," 933 " clearing. internal_i2c_state=%02x\n", 934 status_res.internal_i2c_state)); 935 err = umcpmio_i2c_clear(sc, true); 936 } 937 if (err) 938 goto out; 939 940 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 941 if (cmdbuf == NULL && 942 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 943 cmd = MCP2221_I2C_READ_DATA; 944 } else { 945 cmd = MCP2221_I2C_READ_DATA_RS; 946 } 947 948 /* 949 * The chip apparently can't do a READ without a STOP 950 * operation. Report that, and try treating it like a READ 951 * with a STOP. This won't work for a lot of devices. 952 */ 953 954 if (!I2C_OP_STOP_P(op) && 955 sc->sc_reportreadnostop) { 956 device_printf(sc->sc_dev, 957 "umcpmio_i2c_read: ************ called with READ" 958 " without STOP ***************\n"); 959 } 960 961 i2c_req.cmd = cmd; 962 i2c_req.lsblen = datalen; 963 i2c_req.msblen = 0; 964 i2c_req.slaveaddr = (addr << 1) | 0x01; 965 966 DPRINTF(("umcpmio_i2c_read: I2C READ normal read:" 967 " cmd=%02x, addr=%02x\n", cmd, addr)); 968 969 umcpmio_dump_buffer(sc->sc_dumpbuffer, 970 (uint8_t *)&i2c_req, MCP2221_RES_BUFFER_SIZE, 971 "umcpmio_i2c_read normal read req buffer copy"); 972 973 mutex_enter(&sc->sc_action_mutex); 974 err = umcpmio_send_report(sc, 975 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 976 (uint8_t *)&i2c_res, sc->sc_cv_wait); 977 mutex_exit(&sc->sc_action_mutex); 978 979 if (! err) { 980 umcpmio_dump_buffer(sc->sc_dumpbuffer, 981 (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, 982 "umcpmio_i2c_read read-request response buffer copy"); 983 984 while (rretry > 0) { 985 rretry--; 986 DPRINTF(("umcpmio_i2c_read: fetch loop: rretry=%d\n", 987 rretry)); 988 err = 0; 989 memset(&i2c_fetch_req, 0, MCP2221_REQ_BUFFER_SIZE); 990 i2c_fetch_req.cmd = MCP2221_CMD_I2C_FETCH_READ_DATA; 991 mutex_enter(&sc->sc_action_mutex); 992 err = umcpmio_send_report(sc, 993 (uint8_t *)&i2c_fetch_req, MCP2221_REQ_BUFFER_SIZE, 994 (uint8_t *)&i2c_fetch_res, sc->sc_cv_wait); 995 mutex_exit(&sc->sc_action_mutex); 996 umcpmio_dump_buffer(sc->sc_dumpbuffer, 997 (uint8_t *)&i2c_fetch_req, MCP2221_RES_BUFFER_SIZE, 998 "umcpmio_i2c_read fetch res buffer copy"); 999 1000 if (i2c_fetch_res.cmd == 1001 MCP2221_CMD_I2C_FETCH_READ_DATA) { 1002 if (i2c_fetch_res.completion == 1003 MCP2221_FETCH_READ_PARTIALDATA || 1004 i2c_fetch_res.fetchlen == 1005 MCP2221_FETCH_READERROR) { 1006 DPRINTF(("umcpmio_i2c_read:" 1007 " fetch loop:" 1008 " partial data or read error:" 1009 " completion=%02x," 1010 " fetchlen=%02x\n", 1011 i2c_fetch_res.completion, 1012 i2c_fetch_res.fetchlen)); 1013 WAITMS(sc->sc_busy_delay); 1014 err = EAGAIN; 1015 continue; 1016 } 1017 if (i2c_fetch_res.internal_i2c_state == 1018 MCP2221_ENGINE_ADDRNACK) { 1019 DPRINTF(("umcpmio_i2c_read:" 1020 " fetch loop: engine NACK\n")); 1021 err = EIO; 1022 break; 1023 } 1024 if (i2c_fetch_res.internal_i2c_state == 0 && 1025 i2c_fetch_res.fetchlen == 0) { 1026 DPRINTF(("umcpmio_i2c_read:" 1027 " fetch loop:" 1028 " internal state and" 1029 " fetch len are ZERO\n")); 1030 err = 0; 1031 break; 1032 } 1033 if (i2c_fetch_res.internal_i2c_state == 1034 MCP2221_ENGINE_READPARTIAL || 1035 i2c_fetch_res.internal_i2c_state == 1036 MCP2221_ENGINE_READCOMPLETE) { 1037 int state = 1038 i2c_fetch_res.internal_i2c_state; 1039 DPRINTF(("umcpmio_i2c_read:" 1040 " fetch loop: read partial or" 1041 " read complete:" 1042 " internal_i2c_state=%02x\n", 1043 state)); 1044 err = 0; 1045 break; 1046 } 1047 } else { 1048 device_printf(sc->sc_dev, "umcpmio_i2c_read:" 1049 " fetch2: not the command desired: %02x\n", 1050 i2c_fetch_res.cmd); 1051 err = EIO; 1052 break; 1053 } 1054 } 1055 if (err == EAGAIN) 1056 err = ETIMEDOUT; 1057 1058 if (! err) { 1059 if (databuf != NULL && 1060 i2c_fetch_res.fetchlen != 1061 MCP2221_FETCH_READERROR) { 1062 int size = uimin(i2c_fetch_res.fetchlen, 1063 datalen); 1064 DPRINTF(("umcpmio_i2c_read: copy data:" 1065 " size=%d, fetchlen=%d\n", 1066 size, i2c_fetch_res.fetchlen)); 1067 if (size > 0) { 1068 memcpy(databuf, &i2c_fetch_res.data[0], 1069 size); 1070 } 1071 } else { 1072 DPRINTF(("umcpmio_i2c_read: copy data:" 1073 " databuf is NULL\n")); 1074 } 1075 } 1076 } else { 1077 device_printf(sc->sc_dev, "umcpmio_i2c_read request error:" 1078 " cmd=%02x, err=%d\n", cmd, err); 1079 err = EIO; 1080 } 1081 out: 1082 return err; 1083 } 1084 1085 static int 1086 umcpmio_i2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 1087 size_t cmdlen, void *databuf, size_t datalen, int flags) 1088 { 1089 struct umcpmio_softc *sc = v; 1090 size_t totallen = 0; 1091 int err = 0; 1092 1093 if (addr > 0x7f) 1094 return ENOTSUP; 1095 1096 if (cmdbuf != NULL) 1097 totallen += cmdlen; 1098 if (databuf != NULL) 1099 totallen += datalen; 1100 1101 /* 1102 * There is a way to do a transfer that is larger than 60 bytes, 1103 * but it requires that your break the transfer up into pieces and 1104 * send them in 60 byte chunks. We just won't support that right now. 1105 * It would be somewhat unusual for there to be a transfer that big, 1106 * unless you are trying to do block transfers and that isn't natively 1107 * supported by the chip anyway... so those have to be broken up and 1108 * sent as bytes. 1109 */ 1110 1111 if (totallen > 60) 1112 return ENOTSUP; 1113 1114 if (I2C_OP_WRITE_P(op)) { 1115 err = umcpmio_i2c_write(sc, op, addr, cmdbuf, cmdlen, 1116 databuf, datalen, flags); 1117 1118 DPRINTF(("umcpmio_exec: I2C WRITE: err=%d\n", err)); 1119 } else { 1120 err = umcpmio_i2c_read(sc, op, addr, cmdbuf, cmdlen, 1121 databuf, datalen, flags); 1122 1123 DPRINTF(("umcpmio_exec: I2C READ: err=%d\n", err)); 1124 } 1125 1126 return err; 1127 } 1128 1129 /* Accessing the ADC and DAC part of the chip */ 1130 1131 #define UMCPMIO_DEV_UNIT(m) ((m) & 0x80 ? ((m) & 0x7f) / 3 : (m)) 1132 #define UMCPMIO_DEV_WHAT(m) ((m) & 0x80 ? (((m) & 0x7f) % 3) + 1 : CONTROL_DEV) 1133 1134 static int 1135 umcpmio_dev_open(dev_t dev, int flags, int fmt, struct lwp *l) 1136 { 1137 struct umcpmio_softc *sc; 1138 int dunit; 1139 int pin = -1; 1140 int error = 0; 1141 1142 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1143 if (!sc) 1144 return ENXIO; 1145 1146 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1147 1148 if (sc->sc_dev_open[dunit]) { 1149 DPRINTF(("umcpmio_dev_open: dunit=%d BUSY\n", dunit)); 1150 return EBUSY; 1151 } 1152 1153 /* 1154 * The control device only allows for ioctl calls, so pretty 1155 * much allow any sort of access. For the ADC, you perform a 1156 * strict O_RDONLY and for the DAC a strict O_WRONLY. It is an 1157 * error to try and do a O_RDWR It makes little sense to try 1158 * and support select or poll. The ADC and DAC are always 1159 * available for use. 1160 */ 1161 1162 if (dunit != CONTROL_DEV && 1163 ((flags & FREAD) && (flags & FWRITE))) { 1164 DPRINTF(("umcpmio_dev_open: Not CONTROL device and trying to" 1165 " do READ and WRITE\n")); 1166 return EINVAL; 1167 } 1168 1169 /* 1170 * Ya, this unrolling will also have to be changed if the MCP-2210 is 1171 * supported. There are currently only 4 pins, so don't worry too much 1172 * about it. The MCP-2210 has RAM, so there would be a fifth for it. 1173 */ 1174 1175 mutex_enter(&sc->sc_action_mutex); 1176 if (dunit != CONTROL_DEV) { 1177 switch (dunit) { 1178 case GP1_DEV: 1179 pin = 1; 1180 break; 1181 case GP2_DEV: 1182 pin = 2; 1183 break; 1184 case GP3_DEV: 1185 pin = 3; 1186 break; 1187 default: 1188 error = EINVAL; 1189 break; 1190 } 1191 if (! error) { 1192 /* 1193 * XXX - we can probably do better here... it 1194 * doesn't remember what the pin was set to and 1195 * probably should. 1196 */ 1197 if (flags & FREAD) { 1198 error = umcpmio_gpio_pin_ctlctl(sc, pin, 1199 GPIO_PIN_ALT0, false); 1200 } else { 1201 if (pin == 1) { 1202 error = EINVAL; 1203 } else { 1204 error = umcpmio_gpio_pin_ctlctl(sc, 1205 pin, GPIO_PIN_ALT1, false); 1206 } 1207 } 1208 } 1209 } 1210 if (! error) 1211 sc->sc_dev_open[dunit] = true; 1212 mutex_exit(&sc->sc_action_mutex); 1213 1214 DPRINTF(("umcpmio_dev_open: Opened dunit=%d, pin=%d, error=%d\n", 1215 dunit, pin, error)); 1216 1217 return error; 1218 } 1219 1220 /* Read an ADC value */ 1221 1222 static int 1223 umcpmio_dev_read(dev_t dev, struct uio *uio, int flags) 1224 { 1225 struct umcpmio_softc *sc; 1226 struct mcp2221_status_res status_res; 1227 int dunit; 1228 int error = 0; 1229 uint8_t adc_lsb; 1230 uint8_t adc_msb; 1231 uint16_t buf; 1232 1233 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1234 if (sc == NULL) 1235 return ENXIO; 1236 1237 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1238 1239 if (dunit != CONTROL_DEV) { 1240 while (uio->uio_resid && 1241 !sc->sc_dying) { 1242 error = umcpmio_get_status(sc, &status_res, true); 1243 if (! error) { 1244 switch (dunit) { 1245 case GP1_DEV: 1246 adc_lsb = status_res.adc_channel0_lsb; 1247 adc_msb = status_res.adc_channel0_msb; 1248 break; 1249 case GP2_DEV: 1250 adc_lsb = status_res.adc_channel1_lsb; 1251 adc_msb = status_res.adc_channel1_msb; 1252 break; 1253 case GP3_DEV: 1254 adc_lsb = status_res.adc_channel2_lsb; 1255 adc_msb = status_res.adc_channel2_msb; 1256 break; 1257 default: 1258 error = EINVAL; 1259 break; 1260 } 1261 1262 if (! error) { 1263 if (sc->sc_dying) 1264 break; 1265 1266 buf = adc_msb << 8; 1267 buf |= adc_lsb; 1268 error = uiomove(&buf, 2, uio); 1269 } 1270 } 1271 } 1272 } else { 1273 error = EINVAL; 1274 } 1275 1276 return error; 1277 } 1278 1279 /* Write to the DAC */ 1280 1281 static int 1282 umcpmio_dev_write(dev_t dev, struct uio *uio, int flags) 1283 { 1284 struct umcpmio_softc *sc; 1285 int dunit; 1286 int error = 0; 1287 1288 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1289 if (sc == NULL) 1290 return ENXIO; 1291 1292 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1293 1294 if (dunit != CONTROL_DEV) { 1295 while (uio->uio_resid && 1296 !sc->sc_dying) { 1297 uint8_t buf; 1298 1299 if ((error = uiomove(&buf, 1, uio)) != 0) 1300 break; 1301 1302 if (sc->sc_dying) 1303 break; 1304 1305 error = umcpmio_set_dac_value_one(sc, buf, true); 1306 if (error) 1307 break; 1308 } 1309 } else { 1310 error = EINVAL; 1311 } 1312 1313 return error; 1314 } 1315 1316 /* Close everything up */ 1317 1318 static int 1319 umcpmio_dev_close(dev_t dev, int flags, int fmt, struct lwp *l) 1320 { 1321 struct umcpmio_softc *sc; 1322 int dunit; 1323 int pin; 1324 int error = 0; 1325 1326 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1327 if (sc->sc_dying) 1328 return EIO; 1329 1330 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1331 1332 mutex_enter(&sc->sc_action_mutex); 1333 if (dunit != CONTROL_DEV) { 1334 switch (dunit) { 1335 case GP1_DEV: 1336 pin = 1; 1337 break; 1338 case GP2_DEV: 1339 pin = 2; 1340 break; 1341 case GP3_DEV: 1342 pin = 3; 1343 break; 1344 default: 1345 error = EINVAL; 1346 break; 1347 } 1348 if (! error) { 1349 /* 1350 * XXX - Ya, this really could be done better. 1351 * Probably should read the sram config and 1352 * maybe the gpio config and save out what the 1353 * pin was set to. 1354 */ 1355 1356 error = umcpmio_gpio_pin_ctlctl(sc, pin, 1357 GPIO_PIN_INPUT, false); 1358 } 1359 } 1360 sc->sc_dev_open[dunit] = false; 1361 mutex_exit(&sc->sc_action_mutex); 1362 1363 return error; 1364 } 1365 1366 static int 1367 umcpmio_dev_ioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1368 { 1369 struct umcpmio_softc *sc; 1370 struct mcp2221_status_res get_status_res; 1371 struct mcp2221_get_sram_res get_sram_res; 1372 struct mcp2221_get_gpio_cfg_res get_gpio_cfg_res; 1373 struct mcp2221_get_flash_res get_flash_res; 1374 struct mcp2221_status_res *ioctl_get_status; 1375 struct mcp2221_get_sram_res *ioctl_get_sram; 1376 struct mcp2221_get_gpio_cfg_res *ioctl_get_gpio_cfg; 1377 struct umcpmio_ioctl_get_flash *ioctl_get_flash; 1378 struct umcpmio_ioctl_put_flash *ioctl_put_flash; 1379 struct mcp2221_put_flash_req put_flash_req; 1380 struct mcp2221_put_flash_res put_flash_res; 1381 int dunit; 1382 int error = 0; 1383 1384 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1385 if (sc->sc_dying) 1386 return EIO; 1387 1388 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1389 1390 if (dunit != CONTROL_DEV) { 1391 /* 1392 * It actually is fine to call ioctl with a unsupported 1393 * cmd, but be a little noisy if debug is enabled. 1394 */ 1395 DPRINTF(("umcpmio_dev_ioctl: dunit is not the CONTROL device:" 1396 " dunit=%d, cmd=%ld\n", dunit, cmd)); 1397 return EINVAL; 1398 } 1399 1400 mutex_enter(&sc->sc_action_mutex); 1401 1402 switch (cmd) { 1403 /* 1404 * The GET calls use a shadow buffer for each type of 1405 * call. That probably isn't actually needed and the 1406 * memcpy could be avoided. but... it is only ever 64 1407 * bytes, so maybe not a big deal. 1408 */ 1409 case UMCPMIO_GET_STATUS: 1410 ioctl_get_status = (struct mcp2221_status_res *)data; 1411 error = umcpmio_get_status(sc, &get_status_res, false); 1412 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1413 (uint8_t *)&get_status_res, MCP2221_RES_BUFFER_SIZE, 1414 "umcpmio_dev_ioctl: UMCPMIO_GET_STATUS: get_status_res"); 1415 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_STATUS:" 1416 " umcpmio_get_status error=%d\n", error)); 1417 if (! error) { 1418 memcpy(ioctl_get_status, &get_status_res, 1419 MCP2221_RES_BUFFER_SIZE); 1420 } 1421 break; 1422 1423 case UMCPMIO_GET_SRAM: 1424 ioctl_get_sram = (struct mcp2221_get_sram_res *)data; 1425 error = umcpmio_get_sram(sc, &get_sram_res, false); 1426 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1427 (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, 1428 "umcpmio_dev_ioctl: UMCPMIO_GET_SRAM: get_sram_res"); 1429 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_SRAM:" 1430 " umcpmio_get_sram error=%d\n", error)); 1431 if (! error) { 1432 memcpy(ioctl_get_sram, &get_sram_res, 1433 MCP2221_RES_BUFFER_SIZE); 1434 } 1435 break; 1436 1437 case UMCPMIO_GET_GP_CFG: 1438 ioctl_get_gpio_cfg = (struct mcp2221_get_gpio_cfg_res *)data; 1439 error = umcpmio_get_gpio_cfg(sc, &get_gpio_cfg_res, false); 1440 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1441 (uint8_t *)&get_gpio_cfg_res, MCP2221_RES_BUFFER_SIZE, 1442 "umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG: get_gpio_cfg_res"); 1443 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG:" 1444 " umcpmio_get_gpio_cfg error=%d\n", error)); 1445 if (! error) { 1446 memcpy(ioctl_get_gpio_cfg, &get_gpio_cfg_res, 1447 MCP2221_RES_BUFFER_SIZE); 1448 } 1449 break; 1450 1451 case UMCPMIO_GET_FLASH: 1452 ioctl_get_flash = (struct umcpmio_ioctl_get_flash *)data; 1453 error = umcpmio_get_flash(sc, ioctl_get_flash->subcode, 1454 &get_flash_res, false); 1455 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1456 (uint8_t *)&get_flash_res, MCP2221_RES_BUFFER_SIZE, 1457 "umcpmio_dev_ioctl: UMCPMIO_GET_FLASH: get_flash_res"); 1458 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_FLASH:" 1459 " umcpmio_get_flash subcode=%d, error=%d\n", 1460 ioctl_get_flash->subcode, error)); 1461 if (!error) { 1462 memcpy(&ioctl_get_flash->get_flash_res, &get_flash_res, 1463 MCP2221_RES_BUFFER_SIZE); 1464 } 1465 break; 1466 1467 case UMCPMIO_PUT_FLASH: 1468 /* 1469 * We only allow the flash parts related to gpio to be changed. 1470 * Bounce any attempt to do something else. Also use a shadow 1471 * buffer for the put, so we get to control just literally 1472 * everything about the write to flash. 1473 */ 1474 ioctl_put_flash = (struct umcpmio_ioctl_put_flash *)data; 1475 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1476 " umcpmio_put_flash subcode=%d\n", 1477 ioctl_put_flash->subcode)); 1478 if (ioctl_put_flash->subcode == MCP2221_FLASH_SUBCODE_GP) { 1479 memset(&put_flash_req, 0, MCP2221_REQ_BUFFER_SIZE); 1480 put_flash_req.subcode = ioctl_put_flash->subcode; 1481 put_flash_req.u.gp.gp0_settings = 1482 ioctl_put_flash->put_flash_req.u.gp.gp0_settings; 1483 put_flash_req.u.gp.gp1_settings = 1484 ioctl_put_flash->put_flash_req.u.gp.gp1_settings; 1485 put_flash_req.u.gp.gp2_settings = 1486 ioctl_put_flash->put_flash_req.u.gp.gp2_settings; 1487 put_flash_req.u.gp.gp3_settings = 1488 ioctl_put_flash->put_flash_req.u.gp.gp3_settings; 1489 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1490 (uint8_t *)&ioctl_put_flash->put_flash_req, 1491 MCP2221_REQ_BUFFER_SIZE, 1492 "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1493 " ioctl put_flash_req"); 1494 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1495 (uint8_t *)&put_flash_req, MCP2221_REQ_BUFFER_SIZE, 1496 "umcpmio_dev_ioctl:" 1497 " UMCPMIO_PUT_FLASH: put_flash_req"); 1498 memset(&put_flash_res, 0, MCP2221_RES_BUFFER_SIZE); 1499 error = umcpmio_put_flash(sc, &put_flash_req, 1500 &put_flash_res, false); 1501 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1502 (uint8_t *)&put_flash_res, MCP2221_RES_BUFFER_SIZE, 1503 "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1504 " put_flash_res"); 1505 memcpy(&ioctl_put_flash->put_flash_res, &put_flash_res, 1506 MCP2221_RES_BUFFER_SIZE); 1507 } else { 1508 error = EINVAL; 1509 } 1510 break; 1511 default: 1512 error = EINVAL; 1513 } 1514 1515 mutex_exit(&sc->sc_action_mutex); 1516 1517 return error; 1518 } 1519 1520 /* This is for sysctl variables that don't actually change the chip. */ 1521 1522 int 1523 umcpmio_verify_sysctl(SYSCTLFN_ARGS) 1524 { 1525 int error, t; 1526 struct sysctlnode node; 1527 1528 node = *rnode; 1529 t = *(int *)rnode->sysctl_data; 1530 node.sysctl_data = &t; 1531 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1532 if (error || newp == NULL) 1533 return error; 1534 1535 if (t < 0) 1536 return EINVAL; 1537 1538 *(int *)rnode->sysctl_data = t; 1539 1540 return 0; 1541 } 1542 1543 /* 1544 * sysctl validation for stuff that interacts with the chip needs to 1545 * happen in a transaction. The read of the current state and the 1546 * update to new state can't allow for someone to sneak in between the 1547 * two. 1548 * 1549 * We use text for the values of a lot of these variables so you don't 1550 * need the datasheet in front of you. You get to do that with 1551 * umcpmioctl(8). 1552 */ 1553 1554 static struct umcpmio_sysctl_name umcpmio_vref_names[] = { 1555 { 1556 .text = "4.096V", 1557 }, 1558 { 1559 .text = "2.048V", 1560 }, 1561 { 1562 .text = "1.024V", 1563 }, 1564 { 1565 .text = "OFF", 1566 }, 1567 { 1568 .text = "VDD", 1569 } 1570 }; 1571 1572 int 1573 umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS) 1574 { 1575 char buf[UMCPMIO_VREF_NAME]; 1576 char cbuf[UMCPMIO_VREF_NAME]; 1577 struct umcpmio_softc *sc; 1578 struct sysctlnode node; 1579 int error = 0; 1580 int vrm; 1581 size_t i; 1582 struct mcp2221_get_sram_res sram_res; 1583 1584 node = *rnode; 1585 sc = node.sysctl_data; 1586 1587 mutex_enter(&sc->sc_action_mutex); 1588 1589 error = umcpmio_get_sram(sc, &sram_res, false); 1590 if (error) 1591 goto out; 1592 1593 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1594 (uint8_t *)&sram_res, MCP2221_RES_BUFFER_SIZE, 1595 "umcpmio_verify_dac_sysctl SRAM res buffer"); 1596 1597 if (sram_res.dac_reference_voltage & MCP2221_SRAM_DAC_IS_VRM) { 1598 vrm = sram_res.dac_reference_voltage & 1599 MCP2221_SRAM_DAC_VRM_MASK; 1600 switch (vrm) { 1601 case MCP2221_SRAM_DAC_VRM_4096V: 1602 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1603 break; 1604 case MCP2221_SRAM_DAC_VRM_2048V: 1605 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1606 break; 1607 case MCP2221_SRAM_DAC_VRM_1024V: 1608 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1609 break; 1610 case MCP2221_SRAM_DAC_VRM_OFF: 1611 default: 1612 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1613 break; 1614 } 1615 } else { 1616 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1617 } 1618 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1619 node.sysctl_data = buf; 1620 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1621 if (error || newp == NULL) 1622 goto out; 1623 1624 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1625 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1626 UMCPMIO_VREF_NAME) == 0) { 1627 break; 1628 } 1629 } 1630 1631 if (i == __arraycount(umcpmio_vref_names)) 1632 error = EINVAL; 1633 1634 if (! error) { 1635 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) != 0) { 1636 DPRINTF(("umcpmio_verify_dac_sysctl: setting DAC vref:" 1637 " %s\n", buf)); 1638 error = umcpmio_set_dac_vref_one(sc, buf, false); 1639 } 1640 } 1641 1642 out: 1643 mutex_exit(&sc->sc_action_mutex); 1644 return error; 1645 } 1646 1647 int 1648 umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS) 1649 { 1650 char buf[UMCPMIO_VREF_NAME]; 1651 char cbuf[UMCPMIO_VREF_NAME]; 1652 struct umcpmio_softc *sc; 1653 struct sysctlnode node; 1654 int error = 0; 1655 int vrm; 1656 size_t i; 1657 struct mcp2221_get_sram_res sram_res; 1658 1659 node = *rnode; 1660 sc = node.sysctl_data; 1661 1662 mutex_enter(&sc->sc_action_mutex); 1663 1664 error = umcpmio_get_sram(sc, &sram_res, false); 1665 if (error) 1666 goto out; 1667 1668 if (sram_res.irq_adc_reference_voltage & MCP2221_SRAM_ADC_IS_VRM) { 1669 vrm = sram_res.irq_adc_reference_voltage & 1670 MCP2221_SRAM_ADC_VRM_MASK; 1671 switch (vrm) { 1672 case MCP2221_SRAM_ADC_VRM_4096V: 1673 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1674 break; 1675 case MCP2221_SRAM_ADC_VRM_2048V: 1676 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1677 break; 1678 case MCP2221_SRAM_ADC_VRM_1024V: 1679 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1680 break; 1681 case MCP2221_SRAM_ADC_VRM_OFF: 1682 default: 1683 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1684 break; 1685 } 1686 } else { 1687 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1688 } 1689 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1690 node.sysctl_data = buf; 1691 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1692 if (error || newp == NULL) 1693 goto out; 1694 1695 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1696 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1697 UMCPMIO_VREF_NAME) == 0) { 1698 break; 1699 } 1700 } 1701 1702 if (i == __arraycount(umcpmio_vref_names)) 1703 error = EINVAL; 1704 1705 if (! error) { 1706 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) != 0) { 1707 DPRINTF(("umcpmio_verify_adc_sysctl: setting ADC vref:" 1708 " %s\n", buf)); 1709 error = umcpmio_set_adc_vref_one(sc, buf, false); 1710 } 1711 } 1712 1713 out: 1714 mutex_exit(&sc->sc_action_mutex); 1715 return error; 1716 } 1717 1718 static struct umcpmio_sysctl_name umcpmio_dc_names[] = { 1719 { 1720 .text = "75%", 1721 }, 1722 { 1723 .text = "50%", 1724 }, 1725 { 1726 .text = "25%", 1727 }, 1728 { 1729 .text = "0%", 1730 } 1731 }; 1732 1733 static int 1734 umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS) 1735 { 1736 char buf[UMCPMIO_VREF_NAME]; 1737 char cbuf[UMCPMIO_VREF_NAME]; 1738 struct umcpmio_softc *sc; 1739 struct sysctlnode node; 1740 int error = 0; 1741 uint8_t duty_cycle; 1742 size_t i; 1743 struct mcp2221_get_sram_res sram_res; 1744 1745 node = *rnode; 1746 sc = node.sysctl_data; 1747 1748 mutex_enter(&sc->sc_action_mutex); 1749 1750 error = umcpmio_get_sram(sc, &sram_res, false); 1751 if (error) 1752 goto out; 1753 1754 duty_cycle = sram_res.clock_divider & MCP2221_SRAM_GPIO_CLOCK_DC_MASK; 1755 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl: current duty cycle:" 1756 " %02x\n", duty_cycle)); 1757 switch (duty_cycle) { 1758 case MCP2221_SRAM_GPIO_CLOCK_DC_75: 1759 strncpy(buf, "75%", UMCPMIO_DC_NAME); 1760 break; 1761 case MCP2221_SRAM_GPIO_CLOCK_DC_50: 1762 strncpy(buf, "50%", UMCPMIO_DC_NAME); 1763 break; 1764 case MCP2221_SRAM_GPIO_CLOCK_DC_25: 1765 strncpy(buf, "25%", UMCPMIO_DC_NAME); 1766 break; 1767 case MCP2221_SRAM_GPIO_CLOCK_DC_0: 1768 default: 1769 strncpy(buf, "0%", UMCPMIO_DC_NAME); 1770 break; 1771 } 1772 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1773 node.sysctl_data = buf; 1774 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1775 if (error || newp == NULL) 1776 goto out; 1777 1778 for (i = 0; i < __arraycount(umcpmio_dc_names); i++) { 1779 if (strncmp(node.sysctl_data, umcpmio_dc_names[i].text, 1780 UMCPMIO_VREF_NAME) == 0) { 1781 break; 1782 } 1783 } 1784 1785 if (i == __arraycount(umcpmio_dc_names)) 1786 error = EINVAL; 1787 1788 if (! error) { 1789 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) != 0) { 1790 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl:" 1791 " setting GPIO clock duty cycle: %s\n", buf)); 1792 error = umcpmio_set_gpioclock_dc_one(sc, buf, false); 1793 } 1794 } 1795 1796 out: 1797 mutex_exit(&sc->sc_action_mutex); 1798 return error; 1799 } 1800 1801 static struct umcpmio_sysctl_name umcpmio_cd_names[] = { 1802 { 1803 .text = "375kHz", 1804 }, 1805 { 1806 .text = "750kHz", 1807 }, 1808 { 1809 .text = "1.5MHz", 1810 }, 1811 { 1812 .text = "3MHz", 1813 }, 1814 { 1815 .text = "6MHz", 1816 }, 1817 { 1818 .text = "12MHz", 1819 }, 1820 { 1821 .text = "24MHz", 1822 } 1823 }; 1824 1825 static int 1826 umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS) 1827 { 1828 char buf[UMCPMIO_CD_NAME]; 1829 char cbuf[UMCPMIO_CD_NAME]; 1830 struct umcpmio_softc *sc; 1831 struct sysctlnode node; 1832 int error = 0; 1833 uint8_t clock_divider; 1834 size_t i; 1835 struct mcp2221_get_sram_res sram_res; 1836 1837 node = *rnode; 1838 sc = node.sysctl_data; 1839 1840 mutex_enter(&sc->sc_action_mutex); 1841 1842 error = umcpmio_get_sram(sc, &sram_res, false); 1843 if (error) 1844 goto out; 1845 1846 clock_divider = sram_res.clock_divider & 1847 MCP2221_SRAM_GPIO_CLOCK_CD_MASK; 1848 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl: current clock divider:" 1849 " %02x\n", clock_divider)); 1850 switch (clock_divider) { 1851 case MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ: 1852 strncpy(buf, "375kHz", UMCPMIO_CD_NAME); 1853 break; 1854 case MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ: 1855 strncpy(buf, "750kHz", UMCPMIO_CD_NAME); 1856 break; 1857 case MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ: 1858 strncpy(buf, "1.5MHz", UMCPMIO_CD_NAME); 1859 break; 1860 case MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ: 1861 strncpy(buf, "3MHz", UMCPMIO_CD_NAME); 1862 break; 1863 case MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ: 1864 strncpy(buf, "6MHz", UMCPMIO_CD_NAME); 1865 break; 1866 case MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ: 1867 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1868 break; 1869 case MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ: 1870 strncpy(buf, "24MHz", UMCPMIO_CD_NAME); 1871 break; 1872 default: 1873 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1874 break; 1875 } 1876 strncpy(cbuf, buf, UMCPMIO_CD_NAME); 1877 node.sysctl_data = buf; 1878 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1879 if (error || newp == NULL) 1880 goto out; 1881 1882 for (i = 0; i < __arraycount(umcpmio_cd_names); i++) { 1883 if (strncmp(node.sysctl_data, umcpmio_cd_names[i].text, 1884 UMCPMIO_CD_NAME) == 0) { 1885 break; 1886 } 1887 } 1888 1889 if (i == __arraycount(umcpmio_cd_names)) 1890 error = EINVAL; 1891 1892 if (! error) { 1893 if (strncmp(cbuf, buf, UMCPMIO_CD_NAME) != 0) { 1894 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl:" 1895 " setting GPIO clock clock divider: %s\n", 1896 buf)); 1897 error = umcpmio_set_gpioclock_cd_one(sc, buf, false); 1898 } 1899 } 1900 1901 out: 1902 mutex_exit(&sc->sc_action_mutex); 1903 return error; 1904 } 1905 1906 static int 1907 umcpmio_sysctl_init(struct umcpmio_softc *sc) 1908 { 1909 int error; 1910 const struct sysctlnode *cnode; 1911 int sysctlroot_num, i2c_num, adc_dac_num, adc_num, dac_num, gpio_num; 1912 1913 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1914 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 1915 SYSCTL_DESCR("mcpmio controls"), 1916 NULL, 0, NULL, 0, 1917 CTL_HW, CTL_CREATE, CTL_EOL)) != 0) 1918 return error; 1919 1920 sysctlroot_num = cnode->sysctl_num; 1921 1922 #ifdef UMCPMIO_DEBUG 1923 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1924 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 1925 SYSCTL_DESCR("Debug level"), 1926 umcpmio_verify_sysctl, 0, &umcpmiodebug, 0, 1927 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1928 return error; 1929 1930 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1931 CTLFLAG_READWRITE, CTLTYPE_BOOL, "dump_buffers", 1932 SYSCTL_DESCR("Dump buffer when debugging"), 1933 NULL, 0, &sc->sc_dumpbuffer, 0, 1934 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1935 return error; 1936 #endif 1937 1938 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1939 CTLFLAG_READWRITE, CTLTYPE_INT, "response_wait", 1940 SYSCTL_DESCR("How long to wait in ms for a response" 1941 " for a HID report"), 1942 umcpmio_verify_sysctl, 0, &sc->sc_cv_wait, 0, 1943 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1944 return error; 1945 1946 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1947 CTLFLAG_READWRITE, CTLTYPE_INT, "response_errcnt", 1948 SYSCTL_DESCR("How many errors to allow on a response"), 1949 umcpmio_verify_sysctl, 0, &sc->sc_response_errcnt, 0, 1950 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1951 return error; 1952 1953 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1954 0, CTLTYPE_NODE, "i2c", 1955 SYSCTL_DESCR("I2C controls"), 1956 NULL, 0, NULL, 0, 1957 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1958 return error; 1959 1960 i2c_num = cnode->sysctl_num; 1961 1962 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1963 0, CTLTYPE_NODE, "adcdac", 1964 SYSCTL_DESCR("ADC and DAC controls"), 1965 NULL, 0, NULL, 0, 1966 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1967 return error; 1968 1969 adc_dac_num = cnode->sysctl_num; 1970 1971 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1972 0, CTLTYPE_NODE, "adc", 1973 SYSCTL_DESCR("ADC controls"), 1974 NULL, 0, NULL, 0, 1975 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1976 return error; 1977 1978 adc_num = cnode->sysctl_num; 1979 1980 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1981 0, CTLTYPE_NODE, "dac", 1982 SYSCTL_DESCR("DAC controls"), 1983 NULL, 0, NULL, 0, 1984 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1985 return error; 1986 1987 dac_num = cnode->sysctl_num; 1988 1989 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1990 0, CTLTYPE_NODE, "gpio", 1991 SYSCTL_DESCR("GPIO controls"), 1992 NULL, 0, NULL, 0, 1993 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1994 return error; 1995 1996 gpio_num = cnode->sysctl_num; 1997 1998 /* I2C */ 1999 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2000 CTLFLAG_READWRITE, CTLTYPE_BOOL, "reportreadnostop", 2001 SYSCTL_DESCR("Report that a READ without STOP was attempted" 2002 " by a device"), 2003 NULL, 0, &sc->sc_reportreadnostop, 0, 2004 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2005 return error; 2006 2007 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2008 CTLFLAG_READWRITE, CTLTYPE_INT, "busy_delay", 2009 SYSCTL_DESCR("How long to wait in ms when the I2C engine is busy"), 2010 umcpmio_verify_sysctl, 0, &sc->sc_busy_delay, 0, 2011 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2012 return error; 2013 2014 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2015 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_read", 2016 SYSCTL_DESCR("How many times to retry a busy I2C read"), 2017 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_read, 0, 2018 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2019 return error; 2020 2021 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2022 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_write", 2023 SYSCTL_DESCR("How many times to retry a busy I2C write"), 2024 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_write, 0, 2025 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2026 return error; 2027 2028 /* GPIO */ 2029 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2030 CTLFLAG_READWRITE, CTLTYPE_INT, "irq_poll", 2031 SYSCTL_DESCR("How often to poll for a IRQ change"), 2032 umcpmio_verify_sysctl, 0, &sc->sc_irq_poll, 0, 2033 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2034 return error; 2035 2036 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2037 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_duty_cycles", 2038 SYSCTL_DESCR("Valid duty cycles for GPIO clock on" 2039 " GP1 ALT3 duty cycle"), 2040 0, 0, __UNCONST(umcpmio_valid_dcs), sizeof(umcpmio_valid_dcs) + 1, 2041 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2042 return error; 2043 2044 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2045 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_duty_cycle", 2046 SYSCTL_DESCR("GPIO clock on GP1 ALT3 duty cycle"), 2047 umcpmio_verify_gpioclock_dc_sysctl, 0, (void *)sc, UMCPMIO_DC_NAME, 2048 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2049 return error; 2050 2051 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2052 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_dividers", 2053 SYSCTL_DESCR("Valid clock dividers for GPIO clock on GP1" 2054 " with ALT3"), 2055 0, 0, __UNCONST(umcpmio_valid_cds), sizeof(umcpmio_valid_cds) + 1, 2056 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2057 return error; 2058 2059 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2060 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_divider", 2061 SYSCTL_DESCR("GPIO clock on GP1 ALT3 clock divider"), 2062 umcpmio_verify_gpioclock_cd_sysctl, 0, (void *)sc, UMCPMIO_CD_NAME, 2063 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2064 return error; 2065 2066 /* ADC and DAC */ 2067 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2068 CTLFLAG_READONLY, CTLTYPE_STRING, "vrefs", 2069 SYSCTL_DESCR("Valid vref values for ADC and DAC"), 2070 0, 0, 2071 __UNCONST(umcpmio_valid_vrefs), sizeof(umcpmio_valid_vrefs) + 1, 2072 CTL_HW, sysctlroot_num, adc_dac_num, CTL_CREATE, CTL_EOL)) != 0) 2073 return error; 2074 2075 /* ADC */ 2076 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2077 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 2078 SYSCTL_DESCR("ADC voltage reference"), 2079 umcpmio_verify_adc_sysctl, 0, (void *)sc, UMCPMIO_VREF_NAME, 2080 CTL_HW, sysctlroot_num, adc_num, CTL_CREATE, CTL_EOL)) != 0) 2081 return error; 2082 2083 /* DAC */ 2084 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2085 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 2086 SYSCTL_DESCR("DAC voltage reference"), 2087 umcpmio_verify_dac_sysctl, 0, (void *)sc, UMCPMIO_VREF_NAME, 2088 CTL_HW, sysctlroot_num, dac_num, CTL_CREATE, CTL_EOL)) != 0) 2089 return error; 2090 2091 return 0; 2092 } 2093 2094 static int 2095 umcpmio_match(device_t parent, cfdata_t match, void *aux) 2096 { 2097 struct uhidev_attach_arg *uha = aux; 2098 2099 return umcpmio_lookup(uha->uiaa->uiaa_vendor, uha->uiaa->uiaa_product) 2100 != NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 2101 } 2102 2103 /* 2104 * This driver could be extended to support the MCP-2210 which is MCP's 2105 * USB to SPI / gpio chip. It also appears to be a something like the 2106 * PIC16F1455 used in the MCP2221 / MCP2221A. It is likely that a lot 2107 * of this could use tables to drive behavior. 2108 */ 2109 2110 static void 2111 umcpmio_attach(device_t parent, device_t self, void *aux) 2112 { 2113 struct umcpmio_softc *sc = device_private(self); 2114 struct uhidev_attach_arg *uha = aux; 2115 struct gpiobus_attach_args gba; 2116 struct i2cbus_attach_args iba; 2117 int err; 2118 struct mcp2221_status_res status_res; 2119 2120 sc->sc_dev = self; 2121 sc->sc_hdev = uha->parent; 2122 sc->sc_udev = uha->uiaa->uiaa_device; 2123 2124 sc->sc_umcpmiolog = NULL; 2125 sc->sc_dumpbuffer = false; 2126 2127 sc->sc_reportreadnostop = true; 2128 sc->sc_cv_wait = 2500; 2129 sc->sc_response_errcnt = 5; 2130 sc->sc_busy_delay = 1; 2131 sc->sc_retry_busy_read = 50; 2132 sc->sc_retry_busy_write = 50; 2133 sc->sc_irq_poll = 10; 2134 sc->sc_dev_open[CONTROL_DEV] = false; 2135 sc->sc_dev_open[GP1_DEV] = false; 2136 sc->sc_dev_open[GP2_DEV] = false; 2137 sc->sc_dev_open[GP3_DEV] = false; 2138 2139 aprint_normal("\n"); 2140 2141 if ((err = umcpmio_sysctl_init(sc)) != 0) { 2142 aprint_error_dev(self, "Can't setup sysctl tree (%d)\n", err); 2143 return; 2144 } 2145 2146 mutex_init(&sc->sc_action_mutex, MUTEX_DEFAULT, IPL_NONE); 2147 cv_init(&sc->sc_res_cv, "mcpres"); 2148 mutex_init(&sc->sc_res_mutex, MUTEX_DEFAULT, IPL_NONE); 2149 sc->sc_res_buffer = NULL; 2150 sc->sc_res_ready = false; 2151 2152 err = uhidev_open(sc->sc_hdev, &umcpmio_uhidev_intr, sc); 2153 2154 /* 2155 * It is not clear that this should be needed, but it was noted 2156 * that the device would sometimes not be ready if this delay 2157 * was not present. In fact, the attempts to set stuff a 2158 * little later would sometimes fail. 2159 */ 2160 2161 delay(1000); 2162 2163 if (err) { 2164 aprint_error_dev(sc->sc_dev, "umcpmio_attach: " 2165 " open uhidev_open: err=%d\n", err); 2166 } 2167 2168 if (!err) 2169 err = umcpmio_get_status(sc, &status_res, true); 2170 2171 if (!err) { 2172 aprint_normal_dev(sc->sc_dev, 2173 "Hardware revision: %d.%d, Firmware revision: %d.%d\n", 2174 status_res.mcp2221_hardware_rev_major, 2175 status_res.mcp2221_hardware_rev_minor, 2176 status_res.mcp2221_firmware_rev_major, 2177 status_res.mcp2221_firmware_rev_minor); 2178 2179 /* 2180 * The datasheet suggests that it is possble for this 2181 * to fail if the I2C port is currently being used. 2182 * However... since you just plugged in the chip, the 2183 * I2C port should not really be in use at that moment. 2184 * In any case, try hard to set this and don't make it 2185 * fatal if it did not get set. 2186 */ 2187 int i2cspeed = 0; 2188 while (! err && i2cspeed < 3) { 2189 err = umcpmio_set_i2c_speed_one(sc, I2C_SPEED_SM, true); 2190 if (err) { 2191 aprint_error_dev(sc->sc_dev, "umcpmio_attach:" 2192 " set I2C speed: err=%d\n", 2193 err); 2194 delay(300); 2195 } 2196 i2cspeed++; 2197 } 2198 2199 struct mcp2221_get_sram_res get_sram_res; 2200 err = umcpmio_get_sram(sc, &get_sram_res, true); 2201 2202 if (! err) { 2203 umcpmio_dump_buffer(sc->sc_dumpbuffer, 2204 (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, 2205 "umcpmio_attach get sram buffer copy"); 2206 2207 /* 2208 * There are only 4 pins right now, just unroll 2209 * any loops 2210 */ 2211 2212 sc->sc_gpio_pins[0].pin_num = 0; 2213 sc->sc_gpio_pins[0].pin_caps = GPIO_PIN_INPUT; 2214 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_OUTPUT; 2215 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_ALT0; 2216 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_ALT3; 2217 sc->sc_gpio_pins[0].pin_flags = 2218 umcpmio_sram_gpio_to_flags( 2219 get_sram_res.gp0_settings); 2220 sc->sc_gpio_pins[0].pin_intrcaps = 0; 2221 snprintf(sc->sc_gpio_pins[0].pin_defname, 4, "GP0"); 2222 2223 sc->sc_gpio_pins[1].pin_num = 1; 2224 sc->sc_gpio_pins[1].pin_caps = GPIO_PIN_INPUT; 2225 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_OUTPUT; 2226 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT0; 2227 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT1; 2228 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT2; 2229 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT3; 2230 sc->sc_gpio_pins[1].pin_flags = 2231 umcpmio_sram_gpio_to_flags( 2232 get_sram_res.gp1_settings); 2233 /* XXX - lets not advertise this right now... */ 2234 #if 0 2235 sc->sc_gpio_pins[1].pin_intrcaps = GPIO_INTR_POS_EDGE; 2236 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_NEG_EDGE; 2237 sc->sc_gpio_pins[1].pin_intrcaps |= 2238 GPIO_INTR_DOUBLE_EDGE; 2239 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_MPSAFE; 2240 #endif 2241 sc->sc_gpio_pins[1].pin_intrcaps = 0; 2242 snprintf(sc->sc_gpio_pins[1].pin_defname, 4, "GP1"); 2243 2244 sc->sc_gpio_pins[2].pin_num = 2; 2245 sc->sc_gpio_pins[2].pin_caps = GPIO_PIN_INPUT; 2246 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_OUTPUT; 2247 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT0; 2248 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT1; 2249 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT3; 2250 sc->sc_gpio_pins[2].pin_flags = 2251 umcpmio_sram_gpio_to_flags( 2252 get_sram_res.gp2_settings); 2253 sc->sc_gpio_pins[2].pin_intrcaps = 0; 2254 snprintf(sc->sc_gpio_pins[2].pin_defname, 4, "GP2"); 2255 2256 sc->sc_gpio_pins[3].pin_num = 3; 2257 sc->sc_gpio_pins[3].pin_caps = GPIO_PIN_INPUT; 2258 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_OUTPUT; 2259 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT0; 2260 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT1; 2261 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT3; 2262 sc->sc_gpio_pins[3].pin_flags = 2263 umcpmio_sram_gpio_to_flags( 2264 get_sram_res.gp3_settings); 2265 sc->sc_gpio_pins[3].pin_intrcaps = 0; 2266 snprintf(sc->sc_gpio_pins[3].pin_defname, 4, "GP3"); 2267 2268 sc->sc_gpio_gc.gp_cookie = sc; 2269 sc->sc_gpio_gc.gp_pin_read = umcpmio_gpio_pin_read; 2270 sc->sc_gpio_gc.gp_pin_write = umcpmio_gpio_pin_write; 2271 sc->sc_gpio_gc.gp_pin_ctl = umcpmio_gpio_pin_ctl; 2272 2273 sc->sc_gpio_gc.gp_intr_establish = 2274 umcpmio_gpio_intr_establish; 2275 sc->sc_gpio_gc.gp_intr_disestablish = 2276 umcpmio_gpio_intr_disestablish; 2277 sc->sc_gpio_gc.gp_intr_str = umcpmio_gpio_intrstr; 2278 2279 gba.gba_gc = &sc->sc_gpio_gc; 2280 gba.gba_pins = sc->sc_gpio_pins; 2281 gba.gba_npins = MCP2221_NPINS; 2282 2283 sc->sc_gpio_dev = 2284 config_found(self, &gba, gpiobus_print, 2285 CFARGS(.iattr = "gpiobus")); 2286 2287 iic_tag_init(&sc->sc_i2c_tag); 2288 sc->sc_i2c_tag.ic_cookie = sc; 2289 sc->sc_i2c_tag.ic_acquire_bus = umcpmio_acquire_bus; 2290 sc->sc_i2c_tag.ic_release_bus = umcpmio_release_bus; 2291 sc->sc_i2c_tag.ic_exec = umcpmio_i2c_exec; 2292 2293 memset(&iba, 0, sizeof(iba)); 2294 iba.iba_tag = &sc->sc_i2c_tag; 2295 sc->sc_i2c_dev = config_found(self, &iba, iicbus_print, 2296 CFARGS(.iattr = "i2cbus")); 2297 } else { 2298 aprint_error_dev(sc->sc_dev, "umcpmio_attach:" 2299 " get sram error: err=%d\n", 2300 err); 2301 } 2302 } else { 2303 aprint_error_dev(sc->sc_dev, "umcpmio_attach:" 2304 " open uhidev_open: err=%d\n", err); 2305 } 2306 } 2307 2308 static int 2309 umcpmio_detach(device_t self, int flags) 2310 { 2311 struct umcpmio_softc *sc = device_private(self); 2312 int err; 2313 2314 DPRINTF(("umcpmio_detach: sc=%p flags=%d\n", sc, flags)); 2315 2316 mutex_enter(&sc->sc_action_mutex); 2317 sc->sc_dying = 1; 2318 2319 err = config_detach_children(self, flags); 2320 if (err) 2321 return err; 2322 2323 uhidev_close(sc->sc_hdev); 2324 2325 mutex_destroy(&sc->sc_res_mutex); 2326 cv_destroy(&sc->sc_res_cv); 2327 2328 sysctl_teardown(&sc->sc_umcpmiolog); 2329 2330 mutex_exit(&sc->sc_action_mutex); 2331 mutex_destroy(&sc->sc_action_mutex); 2332 2333 return 0; 2334 } 2335 2336 static int 2337 umcpmio_activate(device_t self, enum devact act) 2338 { 2339 struct umcpmio_softc *sc = device_private(self); 2340 2341 DPRINTFN(5, ("umcpmio_activate: %d\n", act)); 2342 2343 switch (act) { 2344 case DVACT_DEACTIVATE: 2345 sc->sc_dying = 1; 2346 return 0; 2347 default: 2348 return EOPNOTSUPP; 2349 } 2350 } 2351
Indexes created Sat Sep 20 22:09:52 GMT 2025