umcpmio.c revision 1.3
1 /* $NetBSD: umcpmio.c,v 1.3 2025/03/25 20:38:27 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: umcpmio.c,v 1.3 2025/03/25 20:38:27 riastradh Exp $"); 21 22 /* 23 * Driver for the Microchip MCP2221 / MCP2221A USB multi-io chip 24 */ 25 26 #ifdef _KERNEL_OPT 27 #include "opt_usb.h" 28 #endif 29 30 #include <sys/param.h> 31 #include <sys/types.h> 32 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/file.h> 36 #include <sys/gpio.h> 37 #include <sys/kauth.h> 38 #include <sys/kernel.h> 39 #include <sys/kmem.h> 40 #include <sys/lwp.h> 41 #include <sys/sysctl.h> 42 #include <sys/systm.h> 43 #include <sys/tty.h> 44 #include <sys/vnode.h> 45 46 #include <dev/i2c/i2cvar.h> 47 48 #include <dev/gpio/gpiovar.h> 49 50 #include <dev/hid/hid.h> 51 52 #include <dev/usb/uhidev.h> 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdevs.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbhid.h> 58 59 #include <dev/usb/umcpmio.h> 60 #include <dev/usb/umcpmio_hid_reports.h> 61 #include <dev/usb/umcpmio_io.h> 62 #include <dev/usb/umcpmio_subr.h> 63 64 int umcpmio_send_report(struct umcpmio_softc *, uint8_t *, size_t, uint8_t *, 65 int); 66 67 static const struct usb_devno umcpmio_devs[] = { 68 { USB_VENDOR_MICROCHIP, USB_PRODUCT_MICROCHIP_MCP2221 }, 69 }; 70 #define umcpmio_lookup(v, p) usb_lookup(umcpmio_devs, v, p) 71 72 static int umcpmio_match(device_t, cfdata_t, void *); 73 static void umcpmio_attach(device_t, device_t, void *); 74 static int umcpmio_detach(device_t, int); 75 static int umcpmio_activate(device_t, enum devact); 76 static int umcpmio_verify_sysctl(SYSCTLFN_ARGS); 77 static int umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS); 78 static int umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS); 79 static int umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS); 80 static int umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS); 81 82 #define UMCPMIO_DEBUG 1 83 #ifdef UMCPMIO_DEBUG 84 #define DPRINTF(x) do { if (umcpmiodebug) printf x; } while (0) 85 #define DPRINTFN(n, x) do { if (umcpmiodebug > (n)) printf x; } while (0) 86 int umcpmiodebug = 0; 87 #else 88 #define DPRINTF(x) __nothing 89 #define DPRINTFN(n, x) __nothing 90 #endif 91 92 CFATTACH_DECL_NEW(umcpmio, sizeof(struct umcpmio_softc), umcpmio_match, 93 umcpmio_attach, umcpmio_detach, umcpmio_activate); 94 95 static void 96 WAITMS(int ms) 97 { 98 if (ms > 0) 99 delay(ms * 1000); 100 } 101 102 extern struct cfdriver umcpmio_cd; 103 104 static dev_type_open(umcpmio_dev_open); 105 static dev_type_read(umcpmio_dev_read); 106 static dev_type_write(umcpmio_dev_write); 107 static dev_type_close(umcpmio_dev_close); 108 static dev_type_ioctl(umcpmio_dev_ioctl); 109 110 const struct cdevsw umcpmio_cdevsw = { 111 .d_open = umcpmio_dev_open, 112 .d_close = umcpmio_dev_close, 113 .d_read = umcpmio_dev_read, 114 .d_write = umcpmio_dev_write, 115 .d_ioctl = umcpmio_dev_ioctl, 116 .d_stop = nostop, 117 .d_tty = notty, 118 .d_poll = nopoll, 119 .d_mmap = nommap, 120 .d_kqfilter = nokqfilter, 121 .d_discard = nodiscard, 122 .d_flag = D_OTHER 123 }; 124 125 static const char umcpmio_valid_vrefs[] = 126 "4.096V, 2.048V, 1.024V, OFF, VDD"; 127 128 static const char umcpmio_valid_dcs[] = 129 "75%, 50%, 25%, 0%"; 130 131 static const char umcpmio_valid_cds[] = 132 "375kHz, 750kHz, 1.5MHz, 3MHz, 6MHz, 12MHz, 24MHz"; 133 134 static void 135 umcpmio_dump_buffer(bool enabled, uint8_t *buf, u_int len, const char *name) 136 { 137 int i; 138 139 if (enabled) { 140 DPRINTF(("%s:", name)); 141 for (i = 0; i < len; i++) { 142 DPRINTF((" %02x", buf[i])); 143 } 144 DPRINTF(("\n")); 145 } 146 } 147 148 /* 149 * Communication with the HID function requires sending a HID report 150 * request and then waiting for a response. 151 * 152 * The panic that occurs when trying to use the interrupt... i.e. 153 * attaching though this driver seems to be related to the fact that 154 * a spin lock is held and the USB stack wants to wait. 155 * 156 * The USB stack *IS* going to have to wait for the response from 157 * the device, somehow... 158 * 159 * It didn't seem possible to defer the uhidev_write to a thread. 160 * Attempts to yield() while spinning hard also did not work and 161 * not yield()ing didn't allow anything else to run. 162 * 163 */ 164 165 /* 166 * This is the panic you will get: 167 * 168 * panic: kernel diagnostic assertion "ci->ci_mtx_count == -1" failed: file "../../../../kern/kern_synch.c", line 762 mi_switch: cpu0: ci_mtx_count (-2) != -1 (block with spin-mutex held) 169 */ 170 171 static void 172 umcpmio_uhidev_intr(void *cookie, void *ibuf, u_int len) 173 { 174 struct umcpmio_softc *sc = cookie; 175 176 if (sc->sc_dying) 177 return; 178 179 DPRINTFN(30, ("umcpmio_uhidev_intr: len=%d\n", len)); 180 181 mutex_enter(&sc->sc_res_mutex); 182 switch(len) { 183 case MCP2221_RES_BUFFER_SIZE: 184 if (sc->sc_res_buffer != NULL) { 185 memcpy(sc->sc_res_buffer, ibuf, 186 MCP2221_RES_BUFFER_SIZE); 187 sc->sc_res_ready = true; 188 cv_signal(&sc->sc_res_cv); 189 } else { 190 int d = umcpmiodebug; 191 device_printf(sc->sc_dev, 192 "umcpmio_uhidev_intr: NULL sc_res_buffer:" 193 " len=%d\n", 194 len); 195 umcpmiodebug = 20; 196 umcpmio_dump_buffer(true, (uint8_t *)ibuf, len, 197 "umcpmio_uhidev_intr: ibuf"); 198 umcpmiodebug = d; 199 } 200 201 break; 202 default: 203 device_printf(sc->sc_dev, 204 "umcpmio_uhidev_intr: Unknown interrupt length: %d", 205 len); 206 break; 207 } 208 mutex_exit(&sc->sc_res_mutex); 209 } 210 211 /* Send a HID report. This needs to be called with the action mutex held */ 212 213 int 214 umcpmio_send_report(struct umcpmio_softc *sc, uint8_t *sendbuf, 215 size_t sendlen, uint8_t *resbuf, int timeout) 216 { 217 int err = 0; 218 int err_count = 0; 219 220 if (sc->sc_dying) 221 return EIO; 222 223 KASSERT(mutex_owned(&sc->sc_action_mutex)); 224 225 if (sc->sc_res_buffer != NULL) { 226 device_printf(sc->sc_dev, 227 "umcpmio_send_report: sc->sc_res_buffer is not NULL\n"); 228 } 229 sc->sc_res_buffer = resbuf; 230 sc->sc_res_ready = false; 231 232 err = uhidev_write(sc->sc_hdev, sendbuf, sendlen); 233 234 if (err) { 235 DPRINTF(("umcpmio_send_report: uhidev_write errored with:" 236 " err=%d\n", err)); 237 goto out; 238 } 239 240 DPRINTFN(30, ("umcpmio_send_report: about to wait on cv. err=%d\n", 241 err)); 242 243 mutex_enter(&sc->sc_res_mutex); 244 while (!sc->sc_res_ready) { 245 DPRINTFN(20, ("umcpmio_send_report: LOOP for response." 246 " sc_res_ready=%d, err_count=%d, timeout=%d\n", 247 sc->sc_res_ready, err_count, mstohz(timeout))); 248 249 err = cv_timedwait_sig(&sc->sc_res_cv, &sc->sc_res_mutex, 250 mstohz(timeout)); 251 252 /* 253 * We are only going to allow this to loop on an error, 254 * any error at all, so many times. 255 */ 256 if (err) { 257 DPRINTF(("umcpmio_send_report:" 258 " cv_timedwait_sig reported an error:" 259 " err=%d, sc->sc_res_ready=%d\n", 260 err, sc->sc_res_ready)); 261 err_count++; 262 } 263 264 /* 265 * The CV was interrupted, but the buffer is ready so, 266 * clear the error and break out. 267 */ 268 if ((err == ERESTART) && (sc->sc_res_ready)) { 269 DPRINTF(("umcpmio_send_report:" 270 " ERESTART and buffer is ready\n")); 271 err = 0; 272 break; 273 } 274 275 /* 276 * Too many times though the loop, just break out. Turn 277 * a ERESTART (interruption) into a I/O error at this point. 278 */ 279 if (err_count > sc->sc_response_errcnt) { 280 DPRINTF(("umcpmio_send_report: err_count exceeded:" 281 " err=%d\n", err)); 282 if (err == ERESTART) 283 err = EIO; 284 break; 285 } 286 287 /* This is a normal timeout, without interruption, try again */ 288 if (err == EWOULDBLOCK) { 289 DPRINTF(("umcpmio_send_report: EWOULDBLOCK:" 290 " err_count=%d\n", err_count)); 291 continue; 292 } 293 294 /* 295 * The CV was interrupted and the buffer wasn't filled 296 * in, so try again 297 */ 298 if ((err == ERESTART) && (!sc->sc_res_ready)) { 299 DPRINTF(("umcpmio_send_report:" 300 " ERESTART and buffer is NOT ready." 301 " err_count=%d\n", err_count)); 302 continue; 303 } 304 } 305 306 sc->sc_res_buffer = NULL; 307 sc->sc_res_ready = false; 308 mutex_exit(&sc->sc_res_mutex); 309 310 /* Turn most errors into an I/O error */ 311 if (err && 312 err != ERESTART) 313 err = EIO; 314 315 out: 316 return err; 317 } 318 319 /* These are standard gpio reads and set calls */ 320 321 static int 322 umcpmio_gpio_pin_read(void *arg, int pin) 323 { 324 struct umcpmio_softc *sc = arg; 325 int r = GPIO_PIN_LOW; 326 327 r = umcpmio_get_gpio_value(sc, pin, true); 328 329 return r; 330 } 331 332 static void 333 umcpmio_gpio_pin_write(void *arg, int pin, int value) 334 { 335 struct umcpmio_softc *sc = arg; 336 337 umcpmio_set_gpio_value_one(sc, pin, value, true); 338 } 339 340 /* 341 * Internal function that does the dirty work of setting a gpio 342 * pin to its "type". 343 * 344 * There are really two ways to do some of this, one is to set the pin 345 * to input and output, or whatever, using SRAM calls, the other is to 346 * use the GPIO config calls to set input and output and SRAM for 347 * everything else. This just uses SRAM for everything. 348 */ 349 350 static int 351 umcpmio_gpio_pin_ctlctl(void *arg, int pin, int flags, bool takemutex) 352 { 353 struct umcpmio_softc *sc = arg; 354 struct mcp2221_set_sram_req set_sram_req; 355 struct mcp2221_set_sram_res set_sram_res; 356 struct mcp2221_get_sram_res current_sram_res; 357 struct mcp2221_get_gpio_cfg_res current_gpio_cfg_res; 358 int err = 0; 359 360 if (sc->sc_dying) 361 return 0; 362 363 if (takemutex) 364 mutex_enter(&sc->sc_action_mutex); 365 366 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 367 if (err) 368 goto out; 369 370 err = umcpmio_get_gpio_cfg(sc, ¤t_gpio_cfg_res, false); 371 if (err) 372 goto out; 373 374 /* 375 * You can't just set one pin, you must set all of them, so copy the 376 * current settings for the pin we are not messing with. 377 * 378 * And, yes, of course, if the MCP-2210 is ever supported with this 379 * driver, this sort of unrolling will need to be turned into 380 * something different, but for now, just unroll as there are only 381 * 4 pins to care about. 382 * 383 */ 384 385 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 386 switch (pin) { 387 case 0: 388 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 389 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 390 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 391 break; 392 case 1: 393 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 394 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 395 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 396 break; 397 case 2: 398 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 399 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 400 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 401 break; 402 case 3: 403 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 404 set_sram_req.gp1_settings = current_sram_res.gp1_settings; 405 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 406 break; 407 } 408 umcpmio_set_gpio_designation_sram(&set_sram_req, pin, flags); 409 umcpmio_set_gpio_dir_sram(&set_sram_req, pin, flags); 410 411 /* 412 * This part is unfortunate... if a pin is set to output, the 413 * value set on the pin is not mirrored by the chip into SRAM, 414 * but the chip will use the value from SRAM to set the value of 415 * the pin. What this means is that we have to learn the value 416 * from the GPIO config and make sure it is set properly when 417 * updating SRAM. 418 */ 419 420 if (current_gpio_cfg_res.gp0_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 421 if (current_gpio_cfg_res.gp0_pin_value == 1) { 422 set_sram_req.gp0_settings |= 423 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 424 } else { 425 set_sram_req.gp0_settings &= 426 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 427 } 428 } 429 if (current_gpio_cfg_res.gp1_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 430 if (current_gpio_cfg_res.gp1_pin_value == 1) { 431 set_sram_req.gp1_settings |= 432 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 433 } else { 434 set_sram_req.gp1_settings &= 435 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 436 } 437 } 438 if (current_gpio_cfg_res.gp2_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 439 if (current_gpio_cfg_res.gp2_pin_value == 1) { 440 set_sram_req.gp2_settings |= 441 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 442 } else { 443 set_sram_req.gp2_settings &= 444 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 445 } 446 } 447 if (current_gpio_cfg_res.gp3_pin_dir == MCP2221_GPIO_CFG_DIR_OUTPUT) { 448 if (current_gpio_cfg_res.gp3_pin_value == 1) { 449 set_sram_req.gp3_settings |= 450 MCP2221_SRAM_GPIO_OUTPUT_HIGH; 451 } else { 452 set_sram_req.gp3_settings &= 453 ~MCP2221_SRAM_GPIO_OUTPUT_HIGH; 454 } 455 } 456 457 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 458 if (err) 459 goto out; 460 461 umcpmio_dump_buffer(sc->sc_dumpbuffer, 462 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 463 "umcpmio_gpio_pin_ctlctl set sram buffer copy"); 464 if (set_sram_res.cmd != MCP2221_CMD_SET_SRAM || 465 set_sram_res.completion != MCP2221_CMD_COMPLETE_OK) { 466 device_printf(sc->sc_dev, "umcpmio_gpio_pin_ctlctl:" 467 " not the command desired, or error: %02x %02x\n", 468 set_sram_res.cmd, 469 set_sram_res.completion); 470 err = EIO; 471 goto out; 472 } 473 474 sc->sc_gpio_pins[pin].pin_flags = flags; 475 err = 0; 476 477 out: 478 if (takemutex) 479 mutex_exit(&sc->sc_action_mutex); 480 481 return err; 482 } 483 484 static void 485 umcpmio_gpio_pin_ctl(void *arg, int pin, int flags) 486 { 487 struct umcpmio_softc *sc = arg; 488 489 if (sc->sc_dying) 490 return; 491 492 umcpmio_gpio_pin_ctlctl(sc, pin, flags, true); 493 } 494 495 /* 496 * XXX - 497 * 498 * Since testing of gpio interrupts wasn't possible, this part probably 499 * is not complete. At the very least, there is a scheduled callout 500 * that needs to exist to read the interrupt status. The chip does not 501 * send anything on its own when the interrupt happens. 502 */ 503 504 static void * 505 umcpmio_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 506 int (*func)(void *), void *arg) 507 { 508 struct umcpmio_softc *sc = vsc; 509 struct umcpmio_irq *irq = &sc->sc_gpio_irqs[0]; 510 struct mcp2221_set_sram_req set_sram_req; 511 struct mcp2221_set_sram_res set_sram_res; 512 struct mcp2221_get_sram_res current_sram_res; 513 int err = 0; 514 515 if (sc->sc_dying) 516 return NULL; 517 518 irq->sc_gpio_irqfunc = func; 519 irq->sc_gpio_irqarg = arg; 520 521 DPRINTF(("umcpmio_intr_establish: pin=%d, irqmode=%04x\n", 522 pin, irqmode)); 523 524 mutex_enter(&sc->sc_action_mutex); 525 526 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 527 if (err) 528 goto out; 529 530 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 531 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 532 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 533 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 534 umcpmio_set_gpio_irq_sram(&set_sram_req, irqmode); 535 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, false); 536 if (err) { 537 device_printf(sc->sc_dev, "umcpmio_intr_establish:" 538 " set sram error: err=%d\n", 539 err); 540 goto out; 541 } 542 umcpmio_dump_buffer(sc->sc_dumpbuffer, 543 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 544 "umcpmio_intr_establish set sram buffer copy"); 545 if (set_sram_res.cmd != MCP2221_CMD_SET_SRAM || 546 set_sram_res.completion != MCP2221_CMD_COMPLETE_OK) { 547 device_printf(sc->sc_dev, "umcpmio_intr_establish:" 548 " not the command desired, or error: %02x %02x\n", 549 set_sram_res.cmd, 550 set_sram_res.completion); 551 goto out; 552 } 553 554 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_ALT2; 555 556 out: 557 mutex_exit(&sc->sc_action_mutex); 558 559 return irq; 560 } 561 562 static void 563 umcpmio_gpio_intr_disestablish(void *vsc, void *ih) 564 { 565 struct umcpmio_softc *sc = vsc; 566 struct mcp2221_set_sram_req set_sram_req; 567 struct mcp2221_set_sram_res set_sram_res; 568 struct mcp2221_get_sram_res current_sram_res; 569 int err = 0; 570 571 if (sc->sc_dying) 572 return; 573 574 DPRINTF(("umcpmio_intr_disestablish:\n")); 575 576 mutex_enter(&sc->sc_action_mutex); 577 578 err = umcpmio_get_sram(sc, ¤t_sram_res, false); 579 if (err) 580 goto out; 581 582 memset(&set_sram_req, 0, MCP2221_REQ_BUFFER_SIZE); 583 set_sram_req.gp0_settings = current_sram_res.gp0_settings; 584 set_sram_req.gp2_settings = current_sram_res.gp2_settings; 585 set_sram_req.gp3_settings = current_sram_res.gp3_settings; 586 umcpmio_set_gpio_irq_sram(&set_sram_req, 0); 587 err = umcpmio_put_sram(sc, &set_sram_req, &set_sram_res, true); 588 if (err) { 589 device_printf(sc->sc_dev, "umcpmio_intr_disestablish:" 590 " set sram error: err=%d\n", 591 err); 592 goto out; 593 } 594 595 umcpmio_dump_buffer(sc->sc_dumpbuffer, 596 (uint8_t *)&set_sram_res, MCP2221_RES_BUFFER_SIZE, 597 "umcpmio_intr_disestablish set sram buffer copy"); 598 if (set_sram_res.cmd == MCP2221_CMD_SET_SRAM && 599 set_sram_res.completion == MCP2221_CMD_COMPLETE_OK) { 600 device_printf(sc->sc_dev, "umcpmio_intr_disestablish:" 601 " not the command desired, or error: %02x %02x\n", 602 set_sram_res.cmd, 603 set_sram_res.completion); 604 goto out; 605 } 606 607 sc->sc_gpio_pins[1].pin_flags = GPIO_PIN_INPUT; 608 609 out: 610 mutex_exit(&sc->sc_action_mutex); 611 } 612 613 static bool 614 umcpmio_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 615 { 616 617 if (pin < 0 || pin >= MCP2221_NPINS) { 618 DPRINTF(("umcpmio_gpio_intrstr:" 619 " pin %d less than zero or too big\n", 620 pin)); 621 return false; 622 } 623 624 if (pin != 1) { 625 DPRINTF(("umcpmio_gpio_intrstr: pin %d was not 1\n", 626 pin)); 627 return false; 628 } 629 630 snprintf(buf, buflen, "GPIO %d", pin); 631 632 return true; 633 } 634 635 /* Clear status of the I2C engine */ 636 637 static int 638 umcpmio_i2c_clear(struct umcpmio_softc *sc, bool takemutex) 639 { 640 int err = 0; 641 struct mcp2221_status_req status_req; 642 struct mcp2221_status_res status_res; 643 644 memset(&status_req, 0, MCP2221_REQ_BUFFER_SIZE); 645 status_req.cmd = MCP2221_CMD_STATUS; 646 status_req.cancel_transfer = MCP2221_I2C_DO_CANCEL; 647 648 if (takemutex) 649 mutex_enter(&sc->sc_action_mutex); 650 err = umcpmio_send_report(sc, 651 (uint8_t *)&status_req, MCP2221_REQ_BUFFER_SIZE, 652 (uint8_t *)&status_res, sc->sc_cv_wait); 653 if (takemutex) 654 mutex_exit(&sc->sc_action_mutex); 655 if (err) { 656 device_printf(sc->sc_dev, "umcpmio_i2c_clear: request error:" 657 " err=%d\n", err); 658 err = EIO; 659 goto out; 660 } 661 662 umcpmio_dump_buffer(sc->sc_dumpbuffer, 663 (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, 664 "umcpmio_i2c_clear buffer copy"); 665 666 if (status_res.cmd != MCP2221_CMD_STATUS && 667 status_res.completion != MCP2221_CMD_COMPLETE_OK) { 668 device_printf(sc->sc_dev, "umcpmio_i2c_clear:" 669 " cmd exec: not the command desired, or error:" 670 " %02x %02x\n", 671 status_res.cmd, 672 status_res.completion); 673 err = EIO; 674 goto out; 675 } 676 677 umcpmio_dump_buffer(true, 678 (uint8_t *)&status_res, MCP2221_RES_BUFFER_SIZE, 679 "umcpmio_i2c_clear res buffer"); 680 681 out: 682 return err; 683 } 684 685 /* 686 * There isn't much required to acquire or release the I2C bus, but the man 687 * pages says these are needed 688 */ 689 690 static int 691 umcpmio_acquire_bus(void *v, int flags) 692 { 693 return 0; 694 } 695 696 static void 697 umcpmio_release_bus(void *v, int flags) 698 { 699 return; 700 } 701 702 /* 703 * The I2C write and I2C read functions mostly use an algorithm that Adafruit 704 * came up with in their Python based driver. A lot of other people have used 705 * this same algorithm to good effect. If changes are made to the I2C read and 706 * write functions, it is HIGHLY advisable that a MCP2221 or MCP2221A be on 707 * hand to test them. 708 */ 709 710 /* This is what is considered a fatal return from the engine. */ 711 712 static bool 713 umcpmio_i2c_fatal(uint8_t state) 714 { 715 int r = false; 716 717 if (state == MCP2221_ENGINE_ADDRNACK || 718 state == MCP2221_ENGINE_STARTTIMEOUT || 719 state == MCP2221_ENGINE_REPSTARTTIMEOUT || 720 state == MCP2221_ENGINE_STOPTIMEOUT || 721 state == MCP2221_ENGINE_READTIMEOUT || 722 state == MCP2221_ENGINE_WRITETIMEOUT || 723 state == MCP2221_ENGINE_ADDRTIMEOUT) 724 r = true; 725 return r; 726 } 727 728 static int 729 umcpmio_i2c_write(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 730 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, 731 int flags) 732 { 733 struct mcp2221_i2c_req i2c_req; 734 struct mcp2221_i2c_res i2c_res; 735 struct mcp2221_status_res status_res; 736 int remaining; 737 int err = 0; 738 uint8_t cmd; 739 size_t totallen = 0; 740 int wretry = sc->sc_retry_busy_write; 741 int wsretry = sc->sc_retry_busy_write; 742 743 err = umcpmio_get_status(sc, &status_res, true); 744 if (err) 745 goto out; 746 if (status_res.internal_i2c_state != 0) { 747 DPRINTF(("umcpmio_i2c_write: internal state not zero," 748 " clearing. internal_i2c_state=%02x\n", 749 status_res.internal_i2c_state)); 750 err = umcpmio_i2c_clear(sc, true); 751 } 752 if (err) 753 goto out; 754 755 if (cmdbuf != NULL) 756 totallen += cmdlen; 757 if (databuf != NULL) 758 totallen += datalen; 759 760 again: 761 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 762 cmd = MCP2221_I2C_WRITE_DATA_NS; 763 if (I2C_OP_STOP_P(op)) 764 cmd = MCP2221_I2C_WRITE_DATA; 765 i2c_req.cmd = cmd; 766 i2c_req.lsblen = totallen; 767 i2c_req.msblen = 0; 768 i2c_req.slaveaddr = addr << 1; 769 770 remaining = 0; 771 if (cmdbuf != NULL) { 772 memcpy(&i2c_req.data[0], cmdbuf, cmdlen); 773 remaining = cmdlen; 774 } 775 if (databuf != NULL) 776 memcpy(&i2c_req.data[remaining], databuf, datalen); 777 778 DPRINTF(("umcpmio_i2c_write: I2C WRITE: cmd: %02x\n", cmd)); 779 umcpmio_dump_buffer(sc->sc_dumpbuffer, 780 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 781 "umcpmio_i2c_write: write req buffer copy"); 782 783 mutex_enter(&sc->sc_action_mutex); 784 err = umcpmio_send_report(sc, 785 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 786 (uint8_t *)&i2c_res, sc->sc_cv_wait); 787 mutex_exit(&sc->sc_action_mutex); 788 if (err) { 789 device_printf(sc->sc_dev, "umcpmio_i2c_write request error:" 790 " err=%d\n", err); 791 err = EIO; 792 goto out; 793 } 794 795 umcpmio_dump_buffer(sc->sc_dumpbuffer, 796 (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, 797 "umcpmio_i2c_write: write res buffer copy"); 798 if (i2c_res.cmd == cmd && 799 i2c_res.completion == MCP2221_CMD_COMPLETE_OK) { 800 /* 801 * Adafruit does a read back of the status at 802 * this point. We choose not to do that. That 803 * is done later anyway, and it seemed to be 804 * redundent. 805 */ 806 } else if (i2c_res.cmd == cmd && 807 i2c_res.completion == MCP2221_I2C_ENGINE_BUSY) { 808 DPRINTF(("umcpmio_i2c_write:" 809 " I2C engine busy\n")); 810 811 if (umcpmio_i2c_fatal(i2c_res.internal_i2c_state)) { 812 err = EIO; 813 goto out; 814 } 815 wretry--; 816 if (wretry > 0) { 817 WAITMS(sc->sc_busy_delay); 818 goto again; 819 } else { 820 err = EBUSY; 821 goto out; 822 } 823 } else { 824 device_printf(sc->sc_dev, "umcpmio_i2c_write:" 825 " not the command desired, or error:" 826 " %02x %02x\n", 827 i2c_res.cmd, 828 i2c_res.completion); 829 err = EIO; 830 goto out; 831 } 832 833 while (wsretry > 0) { 834 wsretry--; 835 836 DPRINTF(("umcpmio_i2c_write: checking status loop:" 837 " wcretry=%d\n", wsretry)); 838 839 err = umcpmio_get_status(sc, &status_res, true); 840 if (err) { 841 err = EIO; 842 break; 843 } 844 umcpmio_dump_buffer(sc->sc_dumpbuffer, 845 (uint8_t *)&status_res, 846 MCP2221_RES_BUFFER_SIZE, 847 "umcpmio_i2c_write post check status"); 848 /* 849 * Since there isn't any documentation on what 850 * some of the internal state means, it isn't 851 * clear that this is any different than than 852 * MCP2221_ENGINE_ADDRNACK in the other state 853 * register. 854 */ 855 856 if (status_res.internal_i2c_state20 & 857 MCP2221_ENGINE_T1_MASK_NACK) { 858 DPRINTF(("umcpmio_i2c_write post check:" 859 " engine internal state T1 says NACK\n")); 860 err = EIO; 861 break; 862 } 863 if (status_res.internal_i2c_state == 0) { 864 DPRINTF(("umcpmio_i2c_write post check:" 865 " engine internal state is ZERO\n")); 866 err = 0; 867 break; 868 } 869 if (status_res.internal_i2c_state == 870 MCP2221_ENGINE_WRITINGNOSTOP && 871 cmd == MCP2221_I2C_WRITE_DATA_NS) { 872 DPRINTF(("umcpmio_i2c_write post check:" 873 " engine internal state is WRITINGNOSTOP\n")); 874 err = 0; 875 break; 876 } 877 if (umcpmio_i2c_fatal(status_res.internal_i2c_state)) { 878 DPRINTF(("umcpmio_i2c_write post check:" 879 " engine internal state is fatal: %02x\n", 880 status_res.internal_i2c_state)); 881 err = EIO; 882 break; 883 } 884 WAITMS(sc->sc_busy_delay); 885 } 886 887 out: 888 return err; 889 } 890 891 /* 892 * This one deviates a bit from Adafruit in that is supports a straight 893 * read and a write + read. That is, write a register to read from and 894 * then do the read. 895 */ 896 897 static int 898 umcpmio_i2c_read(struct umcpmio_softc *sc, i2c_op_t op, i2c_addr_t addr, 899 const void *cmdbuf, size_t cmdlen, void *databuf, size_t datalen, int 900 flags) 901 { 902 struct mcp2221_i2c_req i2c_req; 903 struct mcp2221_i2c_res i2c_res; 904 struct mcp2221_i2c_fetch_req i2c_fetch_req; 905 struct mcp2221_i2c_fetch_res i2c_fetch_res; 906 struct mcp2221_status_res status_res; 907 int err = 0; 908 uint8_t cmd; 909 int rretry = sc->sc_retry_busy_read; 910 911 if (cmdbuf != NULL) { 912 DPRINTF(("umcpmio_i2c_read: has a cmdbuf, doing write first:" 913 " addr=%02x\n", addr)); 914 err = umcpmio_i2c_write(sc, I2C_OP_WRITE, addr, cmdbuf, cmdlen, 915 NULL, 0, flags); 916 } 917 if (err) 918 goto out; 919 920 err = umcpmio_get_status(sc, &status_res, true); 921 if (err) 922 goto out; 923 924 if (status_res.internal_i2c_state != 0 && 925 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 926 DPRINTF(("umcpmio_i2c_read:" 927 " internal state not zero and not WRITINGNOSTOP," 928 " clearing. internal_i2c_state=%02x\n", 929 status_res.internal_i2c_state)); 930 err = umcpmio_i2c_clear(sc, true); 931 } 932 if (err) 933 goto out; 934 935 memset(&i2c_req, 0, MCP2221_REQ_BUFFER_SIZE); 936 if (cmdbuf == NULL && 937 status_res.internal_i2c_state != MCP2221_ENGINE_WRITINGNOSTOP) { 938 cmd = MCP2221_I2C_READ_DATA; 939 } else { 940 cmd = MCP2221_I2C_READ_DATA_RS; 941 } 942 943 /* 944 * The chip apparently can't do a READ without a STOP 945 * operation. Report that, and try treating it like a READ 946 * with a STOP. This won't work for a lot of devices. 947 */ 948 949 if (!I2C_OP_STOP_P(op) && sc->sc_reportreadnostop) { 950 device_printf(sc->sc_dev, 951 "umcpmio_i2c_read: ************ called with READ" 952 " without STOP ***************\n"); 953 } 954 955 i2c_req.cmd = cmd; 956 i2c_req.lsblen = datalen; 957 i2c_req.msblen = 0; 958 i2c_req.slaveaddr = (addr << 1) | 0x01; 959 960 DPRINTF(("umcpmio_i2c_read: I2C READ normal read:" 961 " cmd=%02x, addr=%02x\n", cmd, addr)); 962 963 umcpmio_dump_buffer(sc->sc_dumpbuffer, 964 (uint8_t *)&i2c_req, MCP2221_RES_BUFFER_SIZE, 965 "umcpmio_i2c_read normal read req buffer copy"); 966 967 mutex_enter(&sc->sc_action_mutex); 968 err = umcpmio_send_report(sc, 969 (uint8_t *)&i2c_req, MCP2221_REQ_BUFFER_SIZE, 970 (uint8_t *)&i2c_res, sc->sc_cv_wait); 971 mutex_exit(&sc->sc_action_mutex); 972 973 if (err) { 974 device_printf(sc->sc_dev, "umcpmio_i2c_read request error:" 975 " cmd=%02x, err=%d\n", cmd, err); 976 err = EIO; 977 goto out; 978 } 979 980 umcpmio_dump_buffer(sc->sc_dumpbuffer, 981 (uint8_t *)&i2c_res, MCP2221_RES_BUFFER_SIZE, 982 "umcpmio_i2c_read read-request response buffer copy"); 983 984 while (rretry > 0) { 985 rretry--; 986 DPRINTF(("umcpmio_i2c_read: fetch loop: rretry=%d\n", rretry)); 987 err = 0; 988 memset(&i2c_fetch_req, 0, MCP2221_REQ_BUFFER_SIZE); 989 i2c_fetch_req.cmd = MCP2221_CMD_I2C_FETCH_READ_DATA; 990 mutex_enter(&sc->sc_action_mutex); 991 err = umcpmio_send_report(sc, 992 (uint8_t *)&i2c_fetch_req, MCP2221_REQ_BUFFER_SIZE, 993 (uint8_t *)&i2c_fetch_res, sc->sc_cv_wait); 994 mutex_exit(&sc->sc_action_mutex); 995 umcpmio_dump_buffer(sc->sc_dumpbuffer, 996 (uint8_t *)&i2c_fetch_req, MCP2221_RES_BUFFER_SIZE, 997 "umcpmio_i2c_read fetch res buffer copy"); 998 999 if (i2c_fetch_res.cmd != MCP2221_CMD_I2C_FETCH_READ_DATA) { 1000 device_printf(sc->sc_dev, "umcpmio_i2c_read:" 1001 " fetch2: not the command desired: %02x\n", 1002 i2c_fetch_res.cmd); 1003 err = EIO; 1004 break; 1005 } 1006 if (i2c_fetch_res.completion == 1007 MCP2221_FETCH_READ_PARTIALDATA || 1008 i2c_fetch_res.fetchlen == MCP2221_FETCH_READERROR) { 1009 DPRINTF(("umcpmio_i2c_read: fetch loop:" 1010 " partial data or read error:" 1011 " completion=%02x, fetchlen=%02x\n", 1012 i2c_fetch_res.completion, 1013 i2c_fetch_res.fetchlen)); 1014 WAITMS(sc->sc_busy_delay); 1015 err = EAGAIN; 1016 continue; 1017 } 1018 if (i2c_fetch_res.internal_i2c_state == 1019 MCP2221_ENGINE_ADDRNACK) { 1020 DPRINTF(("umcpmio_i2c_read:" 1021 " fetch loop: engine NACK\n")); 1022 err = EIO; 1023 break; 1024 } 1025 if (i2c_fetch_res.internal_i2c_state == 0 && 1026 i2c_fetch_res.fetchlen == 0) { 1027 DPRINTF(("umcpmio_i2c_read: fetch loop:" 1028 " internal state and fetch len are ZERO\n")); 1029 err = 0; 1030 break; 1031 } 1032 if (i2c_fetch_res.internal_i2c_state == 1033 MCP2221_ENGINE_READPARTIAL || 1034 i2c_fetch_res.internal_i2c_state == 1035 MCP2221_ENGINE_READCOMPLETE) { 1036 DPRINTF(("umcpmio_i2c_read:" 1037 " fetch loop: read partial or" 1038 " read complete: internal_i2c_state=%02x\n", 1039 i2c_fetch_res.internal_i2c_state)); 1040 err = 0; 1041 break; 1042 } 1043 } 1044 if (err == EAGAIN) 1045 err = ETIMEDOUT; 1046 if (err) 1047 goto out; 1048 1049 if (databuf == NULL || 1050 i2c_fetch_res.fetchlen == MCP2221_FETCH_READERROR) { 1051 DPRINTF(("umcpmio_i2c_read: copy data:" 1052 " databuf is NULL\n")); 1053 goto out; 1054 } 1055 1056 const int size = uimin(i2c_fetch_res.fetchlen, datalen); 1057 DPRINTF(("umcpmio_i2c_read: copy data: size=%d, fetchlen=%d\n", 1058 size, i2c_fetch_res.fetchlen)); 1059 if (size > 0) { 1060 memcpy(databuf, &i2c_fetch_res.data[0], size); 1061 } 1062 1063 out: 1064 return err; 1065 } 1066 1067 static int 1068 umcpmio_i2c_exec(void *v, i2c_op_t op, i2c_addr_t addr, const void *cmdbuf, 1069 size_t cmdlen, void *databuf, size_t datalen, int flags) 1070 { 1071 struct umcpmio_softc *sc = v; 1072 size_t totallen = 0; 1073 int err = 0; 1074 1075 if (addr > 0x7f) 1076 return ENOTSUP; 1077 1078 if (cmdbuf != NULL) 1079 totallen += cmdlen; 1080 if (databuf != NULL) 1081 totallen += datalen; 1082 1083 /* 1084 * There is a way to do a transfer that is larger than 60 bytes, 1085 * but it requires that your break the transfer up into pieces and 1086 * send them in 60 byte chunks. We just won't support that right now. 1087 * It would be somewhat unusual for there to be a transfer that big, 1088 * unless you are trying to do block transfers and that isn't natively 1089 * supported by the chip anyway... so those have to be broken up and 1090 * sent as bytes. 1091 */ 1092 1093 if (totallen > 60) 1094 return ENOTSUP; 1095 1096 if (I2C_OP_WRITE_P(op)) { 1097 err = umcpmio_i2c_write(sc, op, addr, cmdbuf, cmdlen, 1098 databuf, datalen, flags); 1099 1100 DPRINTF(("umcpmio_exec: I2C WRITE: err=%d\n", err)); 1101 } else { 1102 err = umcpmio_i2c_read(sc, op, addr, cmdbuf, cmdlen, 1103 databuf, datalen, flags); 1104 1105 DPRINTF(("umcpmio_exec: I2C READ: err=%d\n", err)); 1106 } 1107 1108 return err; 1109 } 1110 1111 /* Accessing the ADC and DAC part of the chip */ 1112 1113 #define UMCPMIO_DEV_UNIT(m) ((m) & 0x80 ? ((m) & 0x7f) / 3 : (m)) 1114 #define UMCPMIO_DEV_WHAT(m) ((m) & 0x80 ? (((m) & 0x7f) % 3) + 1 : CONTROL_DEV) 1115 1116 static int 1117 umcpmio_dev_open(dev_t dev, int flags, int fmt, struct lwp *l) 1118 { 1119 struct umcpmio_softc *sc; 1120 int dunit; 1121 int pin = -1; 1122 int error = 0; 1123 1124 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1125 if (!sc) 1126 return ENXIO; 1127 1128 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1129 1130 if (sc->sc_dev_open[dunit]) { 1131 DPRINTF(("umcpmio_dev_open: dunit=%d BUSY\n", dunit)); 1132 return EBUSY; 1133 } 1134 1135 /* 1136 * The control device only allows for ioctl calls, so pretty 1137 * much allow any sort of access. For the ADC, you perform a 1138 * strict O_RDONLY and for the DAC a strict O_WRONLY. It is an 1139 * error to try and do a O_RDWR It makes little sense to try 1140 * and support select or poll. The ADC and DAC are always 1141 * available for use. 1142 */ 1143 1144 if (dunit != CONTROL_DEV && 1145 ((flags & FREAD) && (flags & FWRITE))) { 1146 DPRINTF(("umcpmio_dev_open: Not CONTROL device and trying to" 1147 " do READ and WRITE\n")); 1148 return EINVAL; 1149 } 1150 1151 /* 1152 * Ya, this unrolling will also have to be changed if the MCP-2210 is 1153 * supported. There are currently only 4 pins, so don't worry too much 1154 * about it. The MCP-2210 has RAM, so there would be a fifth for it. 1155 */ 1156 1157 mutex_enter(&sc->sc_action_mutex); 1158 if (dunit != CONTROL_DEV) { 1159 switch (dunit) { 1160 case GP1_DEV: 1161 pin = 1; 1162 break; 1163 case GP2_DEV: 1164 pin = 2; 1165 break; 1166 case GP3_DEV: 1167 pin = 3; 1168 break; 1169 default: 1170 error = EINVAL; 1171 goto out; 1172 } 1173 /* 1174 * XXX - we can probably do better here... it 1175 * doesn't remember what the pin was set to and 1176 * probably should. 1177 */ 1178 if (flags & FREAD) { 1179 error = umcpmio_gpio_pin_ctlctl(sc, pin, 1180 GPIO_PIN_ALT0, false); 1181 } else { 1182 if (pin == 1) { 1183 error = EINVAL; 1184 } else { 1185 error = umcpmio_gpio_pin_ctlctl(sc, 1186 pin, GPIO_PIN_ALT1, false); 1187 } 1188 } 1189 } 1190 if (error) 1191 goto out; 1192 sc->sc_dev_open[dunit] = true; 1193 out: 1194 mutex_exit(&sc->sc_action_mutex); 1195 1196 DPRINTF(("umcpmio_dev_open: Opened dunit=%d, pin=%d, error=%d\n", 1197 dunit, pin, error)); 1198 1199 return error; 1200 } 1201 1202 /* Read an ADC value */ 1203 1204 static int 1205 umcpmio_dev_read(dev_t dev, struct uio *uio, int flags) 1206 { 1207 struct umcpmio_softc *sc; 1208 struct mcp2221_status_res status_res; 1209 int dunit; 1210 int error = 0; 1211 uint8_t adc_lsb; 1212 uint8_t adc_msb; 1213 uint16_t buf; 1214 1215 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1216 if (sc == NULL) 1217 return ENXIO; 1218 1219 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1220 1221 if (dunit == CONTROL_DEV) { 1222 error = EINVAL; 1223 goto out; 1224 } 1225 1226 while (uio->uio_resid && !sc->sc_dying) { 1227 error = umcpmio_get_status(sc, &status_res, true); 1228 if (error) 1229 continue; /* XXX goto out? */ 1230 switch (dunit) { 1231 case GP1_DEV: 1232 adc_lsb = status_res.adc_channel0_lsb; 1233 adc_msb = status_res.adc_channel0_msb; 1234 break; 1235 case GP2_DEV: 1236 adc_lsb = status_res.adc_channel1_lsb; 1237 adc_msb = status_res.adc_channel1_msb; 1238 break; 1239 case GP3_DEV: 1240 adc_lsb = status_res.adc_channel2_lsb; 1241 adc_msb = status_res.adc_channel2_msb; 1242 break; 1243 default: 1244 error = EINVAL; 1245 break; 1246 } 1247 if (error) 1248 continue; /* XXX goto out? */ 1249 if (sc->sc_dying) 1250 break; 1251 1252 buf = adc_msb << 8; 1253 buf |= adc_lsb; 1254 error = uiomove(&buf, 2, uio); 1255 /* XXX missing error test */ 1256 } 1257 out: 1258 return error; 1259 } 1260 1261 /* Write to the DAC */ 1262 1263 static int 1264 umcpmio_dev_write(dev_t dev, struct uio *uio, int flags) 1265 { 1266 struct umcpmio_softc *sc; 1267 int dunit; 1268 int error = 0; 1269 1270 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1271 if (sc == NULL) 1272 return ENXIO; 1273 1274 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1275 1276 if (dunit == CONTROL_DEV) { 1277 error = EINVAL; 1278 goto out; 1279 } 1280 1281 while (uio->uio_resid && !sc->sc_dying) { 1282 uint8_t buf; 1283 1284 if ((error = uiomove(&buf, 1, uio)) != 0) 1285 break; 1286 1287 if (sc->sc_dying) 1288 break; 1289 1290 error = umcpmio_set_dac_value_one(sc, buf, true); 1291 if (error) 1292 break; 1293 } 1294 out: 1295 return error; 1296 } 1297 1298 /* Close everything up */ 1299 1300 static int 1301 umcpmio_dev_close(dev_t dev, int flags, int fmt, struct lwp *l) 1302 { 1303 struct umcpmio_softc *sc; 1304 int dunit; 1305 int pin; 1306 int error = 0; 1307 1308 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1309 if (sc->sc_dying) 1310 return EIO; 1311 1312 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1313 1314 mutex_enter(&sc->sc_action_mutex); 1315 if (dunit != CONTROL_DEV) { 1316 switch (dunit) { 1317 case GP1_DEV: 1318 pin = 1; 1319 break; 1320 case GP2_DEV: 1321 pin = 2; 1322 break; 1323 case GP3_DEV: 1324 pin = 3; 1325 break; 1326 default: 1327 error = EINVAL; 1328 goto out; 1329 break; 1330 } 1331 /* 1332 * XXX - Ya, this really could be done better. 1333 * Probably should read the sram config and 1334 * maybe the gpio config and save out what the 1335 * pin was set to. 1336 */ 1337 error = umcpmio_gpio_pin_ctlctl(sc, pin, 1338 GPIO_PIN_INPUT, false); 1339 } 1340 out: 1341 sc->sc_dev_open[dunit] = false; 1342 mutex_exit(&sc->sc_action_mutex); 1343 1344 return error; 1345 } 1346 1347 static int 1348 umcpmio_dev_ioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1349 { 1350 struct umcpmio_softc *sc; 1351 struct mcp2221_status_res get_status_res; 1352 struct mcp2221_get_sram_res get_sram_res; 1353 struct mcp2221_get_gpio_cfg_res get_gpio_cfg_res; 1354 struct mcp2221_get_flash_res get_flash_res; 1355 struct mcp2221_status_res *ioctl_get_status; 1356 struct mcp2221_get_sram_res *ioctl_get_sram; 1357 struct mcp2221_get_gpio_cfg_res *ioctl_get_gpio_cfg; 1358 struct umcpmio_ioctl_get_flash *ioctl_get_flash; 1359 struct umcpmio_ioctl_put_flash *ioctl_put_flash; 1360 struct mcp2221_put_flash_req put_flash_req; 1361 struct mcp2221_put_flash_res put_flash_res; 1362 int dunit; 1363 int error = 0; 1364 1365 sc = device_lookup_private(&umcpmio_cd, UMCPMIO_DEV_UNIT(minor(dev))); 1366 if (sc->sc_dying) 1367 return EIO; 1368 1369 dunit = UMCPMIO_DEV_WHAT(minor(dev)); 1370 1371 if (dunit != CONTROL_DEV) { 1372 /* 1373 * It actually is fine to call ioctl with a unsupported 1374 * cmd, but be a little noisy if debug is enabled. 1375 */ 1376 DPRINTF(("umcpmio_dev_ioctl: dunit is not the CONTROL device:" 1377 " dunit=%d, cmd=%ld\n", dunit, cmd)); 1378 return EINVAL; 1379 } 1380 1381 mutex_enter(&sc->sc_action_mutex); 1382 1383 switch (cmd) { 1384 /* 1385 * The GET calls use a shadow buffer for each type of 1386 * call. That probably isn't actually needed and the 1387 * memcpy could be avoided. but... it is only ever 64 1388 * bytes, so maybe not a big deal. 1389 */ 1390 case UMCPMIO_GET_STATUS: 1391 ioctl_get_status = (struct mcp2221_status_res *)data; 1392 error = umcpmio_get_status(sc, &get_status_res, false); 1393 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1394 (uint8_t *)&get_status_res, MCP2221_RES_BUFFER_SIZE, 1395 "umcpmio_dev_ioctl: UMCPMIO_GET_STATUS: get_status_res"); 1396 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_STATUS:" 1397 " umcpmio_get_status error=%d\n", error)); 1398 if (error) 1399 break; 1400 memcpy(ioctl_get_status, &get_status_res, 1401 MCP2221_RES_BUFFER_SIZE); 1402 break; 1403 1404 case UMCPMIO_GET_SRAM: 1405 ioctl_get_sram = (struct mcp2221_get_sram_res *)data; 1406 error = umcpmio_get_sram(sc, &get_sram_res, false); 1407 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1408 (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, 1409 "umcpmio_dev_ioctl: UMCPMIO_GET_SRAM: get_sram_res"); 1410 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_SRAM:" 1411 " umcpmio_get_sram error=%d\n", error)); 1412 if (error) 1413 break; 1414 memcpy(ioctl_get_sram, &get_sram_res, 1415 MCP2221_RES_BUFFER_SIZE); 1416 break; 1417 1418 case UMCPMIO_GET_GP_CFG: 1419 ioctl_get_gpio_cfg = (struct mcp2221_get_gpio_cfg_res *)data; 1420 error = umcpmio_get_gpio_cfg(sc, &get_gpio_cfg_res, false); 1421 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1422 (uint8_t *)&get_gpio_cfg_res, MCP2221_RES_BUFFER_SIZE, 1423 "umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG: get_gpio_cfg_res"); 1424 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_GP_CFG:" 1425 " umcpmio_get_gpio_cfg error=%d\n", error)); 1426 if (error) 1427 break; 1428 memcpy(ioctl_get_gpio_cfg, &get_gpio_cfg_res, 1429 MCP2221_RES_BUFFER_SIZE); 1430 break; 1431 1432 case UMCPMIO_GET_FLASH: 1433 ioctl_get_flash = (struct umcpmio_ioctl_get_flash *)data; 1434 error = umcpmio_get_flash(sc, ioctl_get_flash->subcode, 1435 &get_flash_res, false); 1436 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1437 (uint8_t *)&get_flash_res, MCP2221_RES_BUFFER_SIZE, 1438 "umcpmio_dev_ioctl: UMCPMIO_GET_FLASH: get_flash_res"); 1439 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_GET_FLASH:" 1440 " umcpmio_get_flash subcode=%d, error=%d\n", 1441 ioctl_get_flash->subcode, error)); 1442 if (error) 1443 break; 1444 memcpy(&ioctl_get_flash->get_flash_res, &get_flash_res, 1445 MCP2221_RES_BUFFER_SIZE); 1446 break; 1447 1448 case UMCPMIO_PUT_FLASH: 1449 /* 1450 * We only allow the flash parts related to gpio to be changed. 1451 * Bounce any attempt to do something else. Also use a shadow 1452 * buffer for the put, so we get to control just literally 1453 * everything about the write to flash. 1454 */ 1455 ioctl_put_flash = (struct umcpmio_ioctl_put_flash *)data; 1456 DPRINTF(("umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1457 " umcpmio_put_flash subcode=%d\n", 1458 ioctl_put_flash->subcode)); 1459 if (ioctl_put_flash->subcode != MCP2221_FLASH_SUBCODE_GP) { 1460 error = EINVAL; 1461 break; 1462 } 1463 memset(&put_flash_req, 0, MCP2221_REQ_BUFFER_SIZE); 1464 put_flash_req.subcode = ioctl_put_flash->subcode; 1465 put_flash_req.u.gp.gp0_settings = 1466 ioctl_put_flash->put_flash_req.u.gp.gp0_settings; 1467 put_flash_req.u.gp.gp1_settings = 1468 ioctl_put_flash->put_flash_req.u.gp.gp1_settings; 1469 put_flash_req.u.gp.gp2_settings = 1470 ioctl_put_flash->put_flash_req.u.gp.gp2_settings; 1471 put_flash_req.u.gp.gp3_settings = 1472 ioctl_put_flash->put_flash_req.u.gp.gp3_settings; 1473 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1474 (uint8_t *)&ioctl_put_flash->put_flash_req, 1475 MCP2221_REQ_BUFFER_SIZE, 1476 "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1477 " ioctl put_flash_req"); 1478 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1479 (uint8_t *)&put_flash_req, MCP2221_REQ_BUFFER_SIZE, 1480 "umcpmio_dev_ioctl:" 1481 " UMCPMIO_PUT_FLASH: put_flash_req"); 1482 memset(&put_flash_res, 0, MCP2221_RES_BUFFER_SIZE); 1483 error = umcpmio_put_flash(sc, &put_flash_req, 1484 &put_flash_res, false); 1485 /* XXX missing error test? */ 1486 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1487 (uint8_t *)&put_flash_res, MCP2221_RES_BUFFER_SIZE, 1488 "umcpmio_dev_ioctl: UMCPMIO_PUT_FLASH:" 1489 " put_flash_res"); 1490 memcpy(&ioctl_put_flash->put_flash_res, &put_flash_res, 1491 MCP2221_RES_BUFFER_SIZE); 1492 break; 1493 default: 1494 error = EINVAL; 1495 } 1496 1497 mutex_exit(&sc->sc_action_mutex); 1498 1499 return error; 1500 } 1501 1502 /* This is for sysctl variables that don't actually change the chip. */ 1503 1504 int 1505 umcpmio_verify_sysctl(SYSCTLFN_ARGS) 1506 { 1507 int error, t; 1508 struct sysctlnode node; 1509 1510 node = *rnode; 1511 t = *(int *)rnode->sysctl_data; 1512 node.sysctl_data = &t; 1513 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1514 if (error || newp == NULL) 1515 return error; 1516 1517 if (t < 0) 1518 return EINVAL; 1519 1520 *(int *)rnode->sysctl_data = t; 1521 1522 return 0; 1523 } 1524 1525 /* 1526 * sysctl validation for stuff that interacts with the chip needs to 1527 * happen in a transaction. The read of the current state and the 1528 * update to new state can't allow for someone to sneak in between the 1529 * two. 1530 * 1531 * We use text for the values of a lot of these variables so you don't 1532 * need the datasheet in front of you. You get to do that with 1533 * umcpmioctl(8). 1534 */ 1535 1536 static struct umcpmio_sysctl_name umcpmio_vref_names[] = { 1537 { 1538 .text = "4.096V", 1539 }, 1540 { 1541 .text = "2.048V", 1542 }, 1543 { 1544 .text = "1.024V", 1545 }, 1546 { 1547 .text = "OFF", 1548 }, 1549 { 1550 .text = "VDD", 1551 } 1552 }; 1553 1554 int 1555 umcpmio_verify_dac_sysctl(SYSCTLFN_ARGS) 1556 { 1557 char buf[UMCPMIO_VREF_NAME]; 1558 char cbuf[UMCPMIO_VREF_NAME]; 1559 struct umcpmio_softc *sc; 1560 struct sysctlnode node; 1561 int error = 0; 1562 int vrm; 1563 size_t i; 1564 struct mcp2221_get_sram_res sram_res; 1565 1566 node = *rnode; 1567 sc = node.sysctl_data; 1568 1569 mutex_enter(&sc->sc_action_mutex); 1570 1571 error = umcpmio_get_sram(sc, &sram_res, false); 1572 if (error) 1573 goto out; 1574 1575 umcpmio_dump_buffer(sc->sc_dumpbuffer, 1576 (uint8_t *)&sram_res, MCP2221_RES_BUFFER_SIZE, 1577 "umcpmio_verify_dac_sysctl SRAM res buffer"); 1578 1579 if (sram_res.dac_reference_voltage & MCP2221_SRAM_DAC_IS_VRM) { 1580 vrm = sram_res.dac_reference_voltage & 1581 MCP2221_SRAM_DAC_VRM_MASK; 1582 switch (vrm) { 1583 case MCP2221_SRAM_DAC_VRM_4096V: 1584 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1585 break; 1586 case MCP2221_SRAM_DAC_VRM_2048V: 1587 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1588 break; 1589 case MCP2221_SRAM_DAC_VRM_1024V: 1590 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1591 break; 1592 case MCP2221_SRAM_DAC_VRM_OFF: 1593 default: 1594 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1595 break; 1596 } 1597 } else { 1598 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1599 } 1600 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1601 node.sysctl_data = buf; 1602 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1603 if (error || newp == NULL) 1604 goto out; 1605 1606 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1607 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1608 UMCPMIO_VREF_NAME) == 0) { 1609 break; 1610 } 1611 } 1612 if (i == __arraycount(umcpmio_vref_names)) { 1613 error = EINVAL; 1614 goto out; 1615 } 1616 1617 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) == 0) { 1618 error = 0; 1619 goto out; 1620 } 1621 1622 DPRINTF(("umcpmio_verify_dac_sysctl: setting DAC vref: %s\n", buf)); 1623 error = umcpmio_set_dac_vref_one(sc, buf, false); 1624 1625 out: 1626 mutex_exit(&sc->sc_action_mutex); 1627 return error; 1628 } 1629 1630 int 1631 umcpmio_verify_adc_sysctl(SYSCTLFN_ARGS) 1632 { 1633 char buf[UMCPMIO_VREF_NAME]; 1634 char cbuf[UMCPMIO_VREF_NAME]; 1635 struct umcpmio_softc *sc; 1636 struct sysctlnode node; 1637 int error = 0; 1638 int vrm; 1639 size_t i; 1640 struct mcp2221_get_sram_res sram_res; 1641 1642 node = *rnode; 1643 sc = node.sysctl_data; 1644 1645 mutex_enter(&sc->sc_action_mutex); 1646 1647 error = umcpmio_get_sram(sc, &sram_res, false); 1648 if (error) 1649 goto out; 1650 1651 if (sram_res.irq_adc_reference_voltage & MCP2221_SRAM_ADC_IS_VRM) { 1652 vrm = sram_res.irq_adc_reference_voltage & 1653 MCP2221_SRAM_ADC_VRM_MASK; 1654 switch (vrm) { 1655 case MCP2221_SRAM_ADC_VRM_4096V: 1656 strncpy(buf, "4.096V", UMCPMIO_VREF_NAME); 1657 break; 1658 case MCP2221_SRAM_ADC_VRM_2048V: 1659 strncpy(buf, "2.048V", UMCPMIO_VREF_NAME); 1660 break; 1661 case MCP2221_SRAM_ADC_VRM_1024V: 1662 strncpy(buf, "1.024V", UMCPMIO_VREF_NAME); 1663 break; 1664 case MCP2221_SRAM_ADC_VRM_OFF: 1665 default: 1666 strncpy(buf, "OFF", UMCPMIO_VREF_NAME); 1667 break; 1668 } 1669 } else { 1670 strncpy(buf, "VDD", UMCPMIO_VREF_NAME); 1671 } 1672 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1673 node.sysctl_data = buf; 1674 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1675 if (error || newp == NULL) 1676 goto out; 1677 1678 for (i = 0; i < __arraycount(umcpmio_vref_names); i++) { 1679 if (strncmp(node.sysctl_data, umcpmio_vref_names[i].text, 1680 UMCPMIO_VREF_NAME) == 0) { 1681 break; 1682 } 1683 } 1684 if (i == __arraycount(umcpmio_vref_names)) { 1685 error = EINVAL; 1686 goto out; 1687 } 1688 1689 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) == 0) { 1690 error = 0; 1691 goto out; 1692 } 1693 1694 DPRINTF(("umcpmio_verify_adc_sysctl: setting ADC vref: %s\n", buf)); 1695 error = umcpmio_set_adc_vref_one(sc, buf, false); 1696 1697 out: 1698 mutex_exit(&sc->sc_action_mutex); 1699 return error; 1700 } 1701 1702 static struct umcpmio_sysctl_name umcpmio_dc_names[] = { 1703 { 1704 .text = "75%", 1705 }, 1706 { 1707 .text = "50%", 1708 }, 1709 { 1710 .text = "25%", 1711 }, 1712 { 1713 .text = "0%", 1714 } 1715 }; 1716 1717 static int 1718 umcpmio_verify_gpioclock_dc_sysctl(SYSCTLFN_ARGS) 1719 { 1720 char buf[UMCPMIO_VREF_NAME]; 1721 char cbuf[UMCPMIO_VREF_NAME]; 1722 struct umcpmio_softc *sc; 1723 struct sysctlnode node; 1724 int error = 0; 1725 uint8_t duty_cycle; 1726 size_t i; 1727 struct mcp2221_get_sram_res sram_res; 1728 1729 node = *rnode; 1730 sc = node.sysctl_data; 1731 1732 mutex_enter(&sc->sc_action_mutex); 1733 1734 error = umcpmio_get_sram(sc, &sram_res, false); 1735 if (error) 1736 goto out; 1737 1738 duty_cycle = sram_res.clock_divider & MCP2221_SRAM_GPIO_CLOCK_DC_MASK; 1739 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl: current duty cycle:" 1740 " %02x\n", duty_cycle)); 1741 switch (duty_cycle) { 1742 case MCP2221_SRAM_GPIO_CLOCK_DC_75: 1743 strncpy(buf, "75%", UMCPMIO_DC_NAME); 1744 break; 1745 case MCP2221_SRAM_GPIO_CLOCK_DC_50: 1746 strncpy(buf, "50%", UMCPMIO_DC_NAME); 1747 break; 1748 case MCP2221_SRAM_GPIO_CLOCK_DC_25: 1749 strncpy(buf, "25%", UMCPMIO_DC_NAME); 1750 break; 1751 case MCP2221_SRAM_GPIO_CLOCK_DC_0: 1752 default: 1753 strncpy(buf, "0%", UMCPMIO_DC_NAME); 1754 break; 1755 } 1756 strncpy(cbuf, buf, UMCPMIO_VREF_NAME); 1757 node.sysctl_data = buf; 1758 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1759 if (error || newp == NULL) 1760 goto out; 1761 1762 for (i = 0; i < __arraycount(umcpmio_dc_names); i++) { 1763 if (strncmp(node.sysctl_data, umcpmio_dc_names[i].text, 1764 UMCPMIO_VREF_NAME) == 0) { 1765 break; 1766 } 1767 } 1768 if (i == __arraycount(umcpmio_dc_names)) { 1769 error = EINVAL; 1770 goto out; 1771 } 1772 1773 if (strncmp(cbuf, buf, UMCPMIO_VREF_NAME) == 0) { 1774 error = 0; 1775 goto out; 1776 } 1777 1778 DPRINTF(("umcpmio_verify_gpioclock_dc_sysctl:" 1779 " setting GPIO clock duty cycle: %s\n", buf)); 1780 error = umcpmio_set_gpioclock_dc_one(sc, buf, false); 1781 1782 out: 1783 mutex_exit(&sc->sc_action_mutex); 1784 return error; 1785 } 1786 1787 static struct umcpmio_sysctl_name umcpmio_cd_names[] = { 1788 { 1789 .text = "375kHz", 1790 }, 1791 { 1792 .text = "750kHz", 1793 }, 1794 { 1795 .text = "1.5MHz", 1796 }, 1797 { 1798 .text = "3MHz", 1799 }, 1800 { 1801 .text = "6MHz", 1802 }, 1803 { 1804 .text = "12MHz", 1805 }, 1806 { 1807 .text = "24MHz", 1808 } 1809 }; 1810 1811 static int 1812 umcpmio_verify_gpioclock_cd_sysctl(SYSCTLFN_ARGS) 1813 { 1814 char buf[UMCPMIO_CD_NAME]; 1815 char cbuf[UMCPMIO_CD_NAME]; 1816 struct umcpmio_softc *sc; 1817 struct sysctlnode node; 1818 int error = 0; 1819 uint8_t clock_divider; 1820 size_t i; 1821 struct mcp2221_get_sram_res sram_res; 1822 1823 node = *rnode; 1824 sc = node.sysctl_data; 1825 1826 mutex_enter(&sc->sc_action_mutex); 1827 1828 error = umcpmio_get_sram(sc, &sram_res, false); 1829 if (error) 1830 goto out; 1831 1832 clock_divider = sram_res.clock_divider & 1833 MCP2221_SRAM_GPIO_CLOCK_CD_MASK; 1834 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl: current clock divider:" 1835 " %02x\n", clock_divider)); 1836 switch (clock_divider) { 1837 case MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ: 1838 strncpy(buf, "375kHz", UMCPMIO_CD_NAME); 1839 break; 1840 case MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ: 1841 strncpy(buf, "750kHz", UMCPMIO_CD_NAME); 1842 break; 1843 case MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ: 1844 strncpy(buf, "1.5MHz", UMCPMIO_CD_NAME); 1845 break; 1846 case MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ: 1847 strncpy(buf, "3MHz", UMCPMIO_CD_NAME); 1848 break; 1849 case MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ: 1850 strncpy(buf, "6MHz", UMCPMIO_CD_NAME); 1851 break; 1852 case MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ: 1853 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1854 break; 1855 case MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ: 1856 strncpy(buf, "24MHz", UMCPMIO_CD_NAME); 1857 break; 1858 default: 1859 strncpy(buf, "12MHz", UMCPMIO_CD_NAME); 1860 break; 1861 } 1862 strncpy(cbuf, buf, UMCPMIO_CD_NAME); 1863 node.sysctl_data = buf; 1864 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1865 if (error || newp == NULL) 1866 goto out; 1867 1868 for (i = 0; i < __arraycount(umcpmio_cd_names); i++) { 1869 if (strncmp(node.sysctl_data, umcpmio_cd_names[i].text, 1870 UMCPMIO_CD_NAME) == 0) { 1871 break; 1872 } 1873 } 1874 if (i == __arraycount(umcpmio_cd_names)) { 1875 error = EINVAL; 1876 goto out; 1877 } 1878 1879 if (strncmp(cbuf, buf, UMCPMIO_CD_NAME) == 0) { 1880 error = 0; 1881 goto out; 1882 } 1883 1884 DPRINTF(("umcpmio_verify_gpioclock_cd_sysctl:" 1885 " setting GPIO clock clock divider: %s\n", 1886 buf)); 1887 error = umcpmio_set_gpioclock_cd_one(sc, buf, false); 1888 1889 out: 1890 mutex_exit(&sc->sc_action_mutex); 1891 return error; 1892 } 1893 1894 static int 1895 umcpmio_sysctl_init(struct umcpmio_softc *sc) 1896 { 1897 int error; 1898 const struct sysctlnode *cnode; 1899 int sysctlroot_num, i2c_num, adc_dac_num, adc_num, dac_num, gpio_num; 1900 1901 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1902 0, CTLTYPE_NODE, device_xname(sc->sc_dev), 1903 SYSCTL_DESCR("mcpmio controls"), 1904 NULL, 0, NULL, 0, 1905 CTL_HW, CTL_CREATE, CTL_EOL)) != 0) 1906 return error; 1907 1908 sysctlroot_num = cnode->sysctl_num; 1909 1910 #ifdef UMCPMIO_DEBUG 1911 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1912 CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 1913 SYSCTL_DESCR("Debug level"), 1914 umcpmio_verify_sysctl, 0, &umcpmiodebug, 0, 1915 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1916 return error; 1917 1918 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1919 CTLFLAG_READWRITE, CTLTYPE_BOOL, "dump_buffers", 1920 SYSCTL_DESCR("Dump buffer when debugging"), 1921 NULL, 0, &sc->sc_dumpbuffer, 0, 1922 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1923 return error; 1924 #endif 1925 1926 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1927 CTLFLAG_READWRITE, CTLTYPE_INT, "response_wait", 1928 SYSCTL_DESCR("How long to wait in ms for a response" 1929 " for a HID report"), 1930 umcpmio_verify_sysctl, 0, &sc->sc_cv_wait, 0, 1931 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1932 return error; 1933 1934 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1935 CTLFLAG_READWRITE, CTLTYPE_INT, "response_errcnt", 1936 SYSCTL_DESCR("How many errors to allow on a response"), 1937 umcpmio_verify_sysctl, 0, &sc->sc_response_errcnt, 0, 1938 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1939 return error; 1940 1941 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1942 0, CTLTYPE_NODE, "i2c", 1943 SYSCTL_DESCR("I2C controls"), 1944 NULL, 0, NULL, 0, 1945 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1946 return error; 1947 1948 i2c_num = cnode->sysctl_num; 1949 1950 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1951 0, CTLTYPE_NODE, "adcdac", 1952 SYSCTL_DESCR("ADC and DAC controls"), 1953 NULL, 0, NULL, 0, 1954 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1955 return error; 1956 1957 adc_dac_num = cnode->sysctl_num; 1958 1959 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1960 0, CTLTYPE_NODE, "adc", 1961 SYSCTL_DESCR("ADC controls"), 1962 NULL, 0, NULL, 0, 1963 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1964 return error; 1965 1966 adc_num = cnode->sysctl_num; 1967 1968 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1969 0, CTLTYPE_NODE, "dac", 1970 SYSCTL_DESCR("DAC controls"), 1971 NULL, 0, NULL, 0, 1972 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1973 return error; 1974 1975 dac_num = cnode->sysctl_num; 1976 1977 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1978 0, CTLTYPE_NODE, "gpio", 1979 SYSCTL_DESCR("GPIO controls"), 1980 NULL, 0, NULL, 0, 1981 CTL_HW, sysctlroot_num, CTL_CREATE, CTL_EOL)) != 0) 1982 return error; 1983 1984 gpio_num = cnode->sysctl_num; 1985 1986 /* I2C */ 1987 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1988 CTLFLAG_READWRITE, CTLTYPE_BOOL, "reportreadnostop", 1989 SYSCTL_DESCR("Report that a READ without STOP was attempted" 1990 " by a device"), 1991 NULL, 0, &sc->sc_reportreadnostop, 0, 1992 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 1993 return error; 1994 1995 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 1996 CTLFLAG_READWRITE, CTLTYPE_INT, "busy_delay", 1997 SYSCTL_DESCR("How long to wait in ms when the I2C engine is busy"), 1998 umcpmio_verify_sysctl, 0, &sc->sc_busy_delay, 0, 1999 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2000 return error; 2001 2002 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2003 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_read", 2004 SYSCTL_DESCR("How many times to retry a busy I2C read"), 2005 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_read, 0, 2006 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2007 return error; 2008 2009 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2010 CTLFLAG_READWRITE, CTLTYPE_INT, "retry_busy_write", 2011 SYSCTL_DESCR("How many times to retry a busy I2C write"), 2012 umcpmio_verify_sysctl, 0, &sc->sc_retry_busy_write, 0, 2013 CTL_HW, sysctlroot_num, i2c_num, CTL_CREATE, CTL_EOL)) != 0) 2014 return error; 2015 2016 /* GPIO */ 2017 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2018 CTLFLAG_READWRITE, CTLTYPE_INT, "irq_poll", 2019 SYSCTL_DESCR("How often to poll for a IRQ change"), 2020 umcpmio_verify_sysctl, 0, &sc->sc_irq_poll, 0, 2021 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2022 return error; 2023 2024 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2025 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_duty_cycles", 2026 SYSCTL_DESCR("Valid duty cycles for GPIO clock on" 2027 " GP1 ALT3 duty cycle"), 2028 0, 0, __UNCONST(umcpmio_valid_dcs), sizeof(umcpmio_valid_dcs) + 1, 2029 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2030 return error; 2031 2032 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2033 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_duty_cycle", 2034 SYSCTL_DESCR("GPIO clock on GP1 ALT3 duty cycle"), 2035 umcpmio_verify_gpioclock_dc_sysctl, 0, (void *)sc, UMCPMIO_DC_NAME, 2036 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2037 return error; 2038 2039 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2040 CTLFLAG_READONLY, CTLTYPE_STRING, "clock_dividers", 2041 SYSCTL_DESCR("Valid clock dividers for GPIO clock on GP1" 2042 " with ALT3"), 2043 0, 0, __UNCONST(umcpmio_valid_cds), sizeof(umcpmio_valid_cds) + 1, 2044 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2045 return error; 2046 2047 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2048 CTLFLAG_READWRITE, CTLTYPE_STRING, "clock_divider", 2049 SYSCTL_DESCR("GPIO clock on GP1 ALT3 clock divider"), 2050 umcpmio_verify_gpioclock_cd_sysctl, 0, (void *)sc, UMCPMIO_CD_NAME, 2051 CTL_HW, sysctlroot_num, gpio_num, CTL_CREATE, CTL_EOL)) != 0) 2052 return error; 2053 2054 /* ADC and DAC */ 2055 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2056 CTLFLAG_READONLY, CTLTYPE_STRING, "vrefs", 2057 SYSCTL_DESCR("Valid vref values for ADC and DAC"), 2058 0, 0, 2059 __UNCONST(umcpmio_valid_vrefs), sizeof(umcpmio_valid_vrefs) + 1, 2060 CTL_HW, sysctlroot_num, adc_dac_num, CTL_CREATE, CTL_EOL)) != 0) 2061 return error; 2062 2063 /* ADC */ 2064 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2065 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 2066 SYSCTL_DESCR("ADC voltage reference"), 2067 umcpmio_verify_adc_sysctl, 0, (void *)sc, UMCPMIO_VREF_NAME, 2068 CTL_HW, sysctlroot_num, adc_num, CTL_CREATE, CTL_EOL)) != 0) 2069 return error; 2070 2071 /* DAC */ 2072 if ((error = sysctl_createv(&sc->sc_umcpmiolog, 0, NULL, &cnode, 2073 CTLFLAG_READWRITE, CTLTYPE_STRING, "vref", 2074 SYSCTL_DESCR("DAC voltage reference"), 2075 umcpmio_verify_dac_sysctl, 0, (void *)sc, UMCPMIO_VREF_NAME, 2076 CTL_HW, sysctlroot_num, dac_num, CTL_CREATE, CTL_EOL)) != 0) 2077 return error; 2078 2079 return 0; 2080 } 2081 2082 static int 2083 umcpmio_match(device_t parent, cfdata_t match, void *aux) 2084 { 2085 struct uhidev_attach_arg *uha = aux; 2086 2087 return umcpmio_lookup(uha->uiaa->uiaa_vendor, uha->uiaa->uiaa_product) 2088 != NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 2089 } 2090 2091 /* 2092 * This driver could be extended to support the MCP-2210 which is MCP's 2093 * USB to SPI / gpio chip. It also appears to be a something like the 2094 * PIC16F1455 used in the MCP2221 / MCP2221A. It is likely that a lot 2095 * of this could use tables to drive behavior. 2096 */ 2097 2098 static void 2099 umcpmio_attach(device_t parent, device_t self, void *aux) 2100 { 2101 struct umcpmio_softc *sc = device_private(self); 2102 struct uhidev_attach_arg *uha = aux; 2103 struct gpiobus_attach_args gba; 2104 struct i2cbus_attach_args iba; 2105 struct mcp2221_status_res status_res; 2106 int err; 2107 2108 sc->sc_dev = self; 2109 sc->sc_hdev = uha->parent; 2110 sc->sc_udev = uha->uiaa->uiaa_device; 2111 2112 sc->sc_umcpmiolog = NULL; 2113 sc->sc_dumpbuffer = false; 2114 2115 sc->sc_reportreadnostop = true; 2116 sc->sc_cv_wait = 2500; 2117 sc->sc_response_errcnt = 5; 2118 sc->sc_busy_delay = 1; 2119 sc->sc_retry_busy_read = 50; 2120 sc->sc_retry_busy_write = 50; 2121 sc->sc_irq_poll = 10; 2122 sc->sc_dev_open[CONTROL_DEV] = false; 2123 sc->sc_dev_open[GP1_DEV] = false; 2124 sc->sc_dev_open[GP2_DEV] = false; 2125 sc->sc_dev_open[GP3_DEV] = false; 2126 2127 aprint_normal("\n"); 2128 2129 if ((err = umcpmio_sysctl_init(sc)) != 0) { 2130 aprint_error_dev(self, "Can't setup sysctl tree (%d)\n", err); 2131 return; 2132 } 2133 2134 mutex_init(&sc->sc_action_mutex, MUTEX_DEFAULT, IPL_NONE); 2135 cv_init(&sc->sc_res_cv, "mcpres"); 2136 mutex_init(&sc->sc_res_mutex, MUTEX_DEFAULT, IPL_NONE); 2137 sc->sc_res_buffer = NULL; 2138 sc->sc_res_ready = false; 2139 2140 err = uhidev_open(sc->sc_hdev, &umcpmio_uhidev_intr, sc); 2141 if (err) { 2142 aprint_error_dev(sc->sc_dev, "umcpmio_attach: " 2143 " uhidev_open: err=%d\n", err); 2144 return; 2145 } 2146 2147 /* 2148 * It is not clear that this should be needed, but it was noted 2149 * that the device would sometimes not be ready if this delay 2150 * was not present. In fact, the attempts to set stuff a 2151 * little later would sometimes fail. 2152 */ 2153 2154 delay(1000); 2155 2156 err = umcpmio_get_status(sc, &status_res, true); 2157 if (err) { 2158 aprint_error_dev(sc->sc_dev, "umcpmio_attach: " 2159 " umcpmio_get_status: err=%d\n", err); 2160 return; 2161 } 2162 2163 aprint_normal_dev(sc->sc_dev, 2164 "Hardware revision: %d.%d, Firmware revision: %d.%d\n", 2165 status_res.mcp2221_hardware_rev_major, 2166 status_res.mcp2221_hardware_rev_minor, 2167 status_res.mcp2221_firmware_rev_major, 2168 status_res.mcp2221_firmware_rev_minor); 2169 2170 /* 2171 * The datasheet suggests that it is possble for this 2172 * to fail if the I2C port is currently being used. 2173 * However... since you just plugged in the chip, the 2174 * I2C port should not really be in use at that moment. 2175 * In any case, try hard to set this and don't make it 2176 * fatal if it did not get set. 2177 */ 2178 int i2cspeed; 2179 for (i2cspeed = 0; i2cspeed < 3; i2cspeed++) { 2180 err = umcpmio_set_i2c_speed_one(sc, I2C_SPEED_SM, true); 2181 if (err) { 2182 aprint_error_dev(sc->sc_dev, "umcpmio_attach:" 2183 " set I2C speed: err=%d\n", 2184 err); 2185 delay(300); 2186 } 2187 break; 2188 } 2189 2190 struct mcp2221_get_sram_res get_sram_res; 2191 err = umcpmio_get_sram(sc, &get_sram_res, true); 2192 if (err) { 2193 aprint_error_dev(sc->sc_dev, "umcpmio_attach:" 2194 " get sram error: err=%d\n", 2195 err); 2196 return; 2197 } 2198 2199 umcpmio_dump_buffer(sc->sc_dumpbuffer, 2200 (uint8_t *)&get_sram_res, MCP2221_RES_BUFFER_SIZE, 2201 "umcpmio_attach get sram buffer copy"); 2202 2203 /* 2204 * There are only 4 pins right now, just unroll 2205 * any loops 2206 */ 2207 2208 sc->sc_gpio_pins[0].pin_num = 0; 2209 sc->sc_gpio_pins[0].pin_caps = GPIO_PIN_INPUT; 2210 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_OUTPUT; 2211 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_ALT0; 2212 sc->sc_gpio_pins[0].pin_caps |= GPIO_PIN_ALT3; 2213 sc->sc_gpio_pins[0].pin_flags = 2214 umcpmio_sram_gpio_to_flags(get_sram_res.gp0_settings); 2215 sc->sc_gpio_pins[0].pin_intrcaps = 0; 2216 snprintf(sc->sc_gpio_pins[0].pin_defname, 4, "GP0"); 2217 2218 sc->sc_gpio_pins[1].pin_num = 1; 2219 sc->sc_gpio_pins[1].pin_caps = GPIO_PIN_INPUT; 2220 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_OUTPUT; 2221 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT0; 2222 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT1; 2223 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT2; 2224 sc->sc_gpio_pins[1].pin_caps |= GPIO_PIN_ALT3; 2225 sc->sc_gpio_pins[1].pin_flags = 2226 umcpmio_sram_gpio_to_flags(get_sram_res.gp1_settings); 2227 /* XXX - lets not advertise this right now... */ 2228 #if 0 2229 sc->sc_gpio_pins[1].pin_intrcaps = GPIO_INTR_POS_EDGE; 2230 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_NEG_EDGE; 2231 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_DOUBLE_EDGE; 2232 sc->sc_gpio_pins[1].pin_intrcaps |= GPIO_INTR_MPSAFE; 2233 #endif 2234 sc->sc_gpio_pins[1].pin_intrcaps = 0; 2235 snprintf(sc->sc_gpio_pins[1].pin_defname, 4, "GP1"); 2236 2237 sc->sc_gpio_pins[2].pin_num = 2; 2238 sc->sc_gpio_pins[2].pin_caps = GPIO_PIN_INPUT; 2239 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_OUTPUT; 2240 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT0; 2241 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT1; 2242 sc->sc_gpio_pins[2].pin_caps |= GPIO_PIN_ALT3; 2243 sc->sc_gpio_pins[2].pin_flags = 2244 umcpmio_sram_gpio_to_flags(get_sram_res.gp2_settings); 2245 sc->sc_gpio_pins[2].pin_intrcaps = 0; 2246 snprintf(sc->sc_gpio_pins[2].pin_defname, 4, "GP2"); 2247 2248 sc->sc_gpio_pins[3].pin_num = 3; 2249 sc->sc_gpio_pins[3].pin_caps = GPIO_PIN_INPUT; 2250 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_OUTPUT; 2251 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT0; 2252 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT1; 2253 sc->sc_gpio_pins[3].pin_caps |= GPIO_PIN_ALT3; 2254 sc->sc_gpio_pins[3].pin_flags = 2255 umcpmio_sram_gpio_to_flags(get_sram_res.gp3_settings); 2256 sc->sc_gpio_pins[3].pin_intrcaps = 0; 2257 snprintf(sc->sc_gpio_pins[3].pin_defname, 4, "GP3"); 2258 2259 sc->sc_gpio_gc.gp_cookie = sc; 2260 sc->sc_gpio_gc.gp_pin_read = umcpmio_gpio_pin_read; 2261 sc->sc_gpio_gc.gp_pin_write = umcpmio_gpio_pin_write; 2262 sc->sc_gpio_gc.gp_pin_ctl = umcpmio_gpio_pin_ctl; 2263 2264 sc->sc_gpio_gc.gp_intr_establish = umcpmio_gpio_intr_establish; 2265 sc->sc_gpio_gc.gp_intr_disestablish = umcpmio_gpio_intr_disestablish; 2266 sc->sc_gpio_gc.gp_intr_str = umcpmio_gpio_intrstr; 2267 2268 gba.gba_gc = &sc->sc_gpio_gc; 2269 gba.gba_pins = sc->sc_gpio_pins; 2270 gba.gba_npins = MCP2221_NPINS; 2271 2272 sc->sc_gpio_dev = config_found(self, &gba, gpiobus_print, 2273 CFARGS(.iattr = "gpiobus")); 2274 2275 iic_tag_init(&sc->sc_i2c_tag); 2276 sc->sc_i2c_tag.ic_cookie = sc; 2277 sc->sc_i2c_tag.ic_acquire_bus = umcpmio_acquire_bus; 2278 sc->sc_i2c_tag.ic_release_bus = umcpmio_release_bus; 2279 sc->sc_i2c_tag.ic_exec = umcpmio_i2c_exec; 2280 2281 memset(&iba, 0, sizeof(iba)); 2282 iba.iba_tag = &sc->sc_i2c_tag; 2283 sc->sc_i2c_dev = config_found(self, &iba, iicbus_print, 2284 CFARGS(.iattr = "i2cbus")); 2285 } 2286 2287 static int 2288 umcpmio_detach(device_t self, int flags) 2289 { 2290 struct umcpmio_softc *sc = device_private(self); 2291 int err; 2292 2293 DPRINTF(("umcpmio_detach: sc=%p flags=%d\n", sc, flags)); 2294 2295 mutex_enter(&sc->sc_action_mutex); 2296 sc->sc_dying = 1; 2297 2298 err = config_detach_children(self, flags); 2299 if (err) 2300 return err; 2301 2302 uhidev_close(sc->sc_hdev); 2303 2304 mutex_destroy(&sc->sc_res_mutex); 2305 cv_destroy(&sc->sc_res_cv); 2306 2307 sysctl_teardown(&sc->sc_umcpmiolog); 2308 2309 mutex_exit(&sc->sc_action_mutex); 2310 mutex_destroy(&sc->sc_action_mutex); 2311 2312 return 0; 2313 } 2314 2315 static int 2316 umcpmio_activate(device_t self, enum devact act) 2317 { 2318 struct umcpmio_softc *sc = device_private(self); 2319 2320 DPRINTFN(5, ("umcpmio_activate: %d\n", act)); 2321 2322 switch (act) { 2323 case DVACT_DEACTIVATE: 2324 sc->sc_dying = 1; 2325 return 0; 2326 default: 2327 return EOPNOTSUPP; 2328 } 2329 } 2330
Indexes created Sat Sep 20 22:09:52 GMT 2025