umcpmio_hid_reports.h revision 1.1
1 /* $NetBSD: umcpmio_hid_reports.h,v 1.1 2024/12/16 16:37:38 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 20 #ifndef _UMCPMIO_HID_REPORTS_H_ 21 #define _UMCPMIO_HID_REPORTS_H_ 22 23 24 #include <sys/types.h> 25 26 27 /* It is nice that all HID reports want a 64 byte request and return a 64 byte 28 * response. 29 */ 30 31 #define MCP2221_REQ_BUFFER_SIZE 64 32 #define MCP2221_RES_BUFFER_SIZE 64 33 34 #define MCP2221_CMD_STATUS 0x10 35 36 #define MCP2221_CMD_I2C_FETCH_READ_DATA 0x40 37 38 #define MCP2221_CMD_SET_GPIO_CFG 0x50 39 #define MCP2221_CMD_GET_GPIO_CFG 0x51 40 41 #define MCP2221_CMD_SET_SRAM 0x60 42 #define MCP2221_CMD_GET_SRAM 0x61 43 44 #define MCP2221_I2C_WRITE_DATA 0x90 45 #define MCP2221_I2C_READ_DATA 0x91 46 #define MCP2221_I2C_WRITE_DATA_RS 0x92 47 #define MCP2221_I2C_READ_DATA_RS 0x93 48 #define MCP2221_I2C_WRITE_DATA_NS 0x94 49 50 #define MCP2221_CMD_GET_FLASH 0xb0 51 #define MCP2221_CMD_SET_FLASH 0xb1 52 #define MCP2221_CMD_SEND_FLASH_PASSWORD 0xb2 53 54 #define MCP2221_CMD_COMPLETE_OK 0x00 55 #define MCP2221_CMD_COMPLETE_NO_SUPPORT 0x02 56 #define MCP2221_CMD_COMPLETE_EPERM 0x03 57 58 #define MCP2221_I2C_DO_CANCEL 0x10 59 #define MCP2221_INTERNAL_CLOCK 12000000 60 #define MCP2221_DEFAULT_I2C_SPEED 100000 61 #define MCP2221_I2C_SET_SPEED 0x20 62 63 /* The request and response structures are, perhaps, over literal. */ 64 65 struct mcp2221_status_req { 66 uint8_t cmd; /* MCP2221_CMD_STATUS */ 67 uint8_t dontcare1; 68 uint8_t cancel_transfer; 69 uint8_t set_i2c_speed; 70 uint8_t i2c_clock_divider; 71 uint8_t dontcare2[59]; 72 }; 73 74 #define MCP2221_I2C_SPEED_SET 0x20 75 #define MCP2221_I2C_SPEED_BUSY 0x21 76 #define MCP2221_ENGINE_T1_MASK_NACK 0x40 77 78 struct mcp2221_status_res { 79 uint8_t cmd; 80 uint8_t completion; 81 uint8_t cancel_transfer; 82 uint8_t set_i2c_speed; 83 uint8_t i2c_clock_divider; 84 uint8_t dontcare2[3]; 85 uint8_t internal_i2c_state; 86 uint8_t lsb_i2c_req_len; 87 uint8_t msb_i2c_req_len; 88 uint8_t lsb_i2c_trans_len; 89 uint8_t msb_i2c_trans_len; 90 uint8_t internal_i2c_bcount; 91 uint8_t i2c_speed_divider; 92 uint8_t i2c_timeout_value; 93 uint8_t lsb_i2c_address; 94 uint8_t msb_i2c_address; 95 uint8_t dontcare3a[2]; 96 uint8_t internal_i2c_state20; 97 uint8_t dontcare3b; 98 uint8_t scl_line_value; 99 uint8_t sda_line_value; 100 uint8_t interrupt_edge_state; 101 uint8_t i2c_read_pending; 102 uint8_t dontcare4[20]; 103 uint8_t mcp2221_hardware_rev_major; 104 uint8_t mcp2221_hardware_rev_minor; 105 uint8_t mcp2221_firmware_rev_major; 106 uint8_t mcp2221_firmware_rev_minor; 107 uint8_t adc_channel0_lsb; 108 uint8_t adc_channel0_msb; 109 uint8_t adc_channel1_lsb; 110 uint8_t adc_channel1_msb; 111 uint8_t adc_channel2_lsb; 112 uint8_t adc_channel2_msb; 113 uint8_t dontcare5[8]; 114 }; 115 116 #define MCP2221_GPIO_CFG_ALTER 0xff 117 118 struct mcp2221_set_gpio_cfg_req { 119 uint8_t cmd; /* MCP2221_CMD_SET_GPIO_CFG */ 120 uint8_t dontcare1; 121 122 uint8_t alter_gp0_value; 123 uint8_t new_gp0_value; 124 uint8_t alter_gp0_dir; 125 uint8_t new_gp0_dir; 126 127 uint8_t alter_gp1_value; 128 uint8_t new_gp1_value; 129 uint8_t alter_gp1_dir; 130 uint8_t new_gp1_dir; 131 132 uint8_t alter_gp2_value; 133 uint8_t new_gp2_value; 134 uint8_t alter_gp2_dir; 135 uint8_t new_gp2_dir; 136 137 uint8_t alter_gp3_value; 138 uint8_t new_gp3_value; 139 uint8_t alter_gp3_dir; 140 uint8_t new_gp3_dir; 141 142 uint8_t reserved[46]; 143 }; 144 145 struct mcp2221_set_gpio_cfg_res { 146 uint8_t cmd; 147 uint8_t completion; 148 149 uint8_t alter_gp0_value; 150 uint8_t new_gp0_value; 151 uint8_t alter_gp0_dir; 152 uint8_t new_gp0_dir; 153 154 uint8_t alter_gp1_value; 155 uint8_t new_gp1_value; 156 uint8_t alter_gp1_dir; 157 uint8_t new_gp1_dir; 158 159 uint8_t alter_gp2_value; 160 uint8_t new_gp2_value; 161 uint8_t alter_gp2_dir; 162 uint8_t new_gp2_dir; 163 164 uint8_t alter_gp3_value; 165 uint8_t new_gp3_value; 166 uint8_t alter_gp3_dir; 167 uint8_t new_gp3_dir; 168 169 uint8_t dontcare[46]; 170 }; 171 172 struct mcp2221_get_gpio_cfg_req { 173 uint8_t cmd; /* MCP2221_CMD_GET_GPIO_CFG */ 174 uint8_t dontcare[63]; 175 }; 176 177 #define MCP2221_GPIO_CFG_VALUE_NOT_GPIO 0xEE 178 #define MCP2221_GPIO_CFG_DIR_NOT_GPIO 0xEF 179 #define MCP2221_GPIO_CFG_DIR_INPUT 0x01 180 #define MCP2221_GPIO_CFG_DIR_OUTPUT 0x00 181 182 struct mcp2221_get_gpio_cfg_res { 183 uint8_t cmd; 184 uint8_t completion; 185 186 uint8_t gp0_pin_value; 187 uint8_t gp0_pin_dir; 188 189 uint8_t gp1_pin_value; 190 uint8_t gp1_pin_dir; 191 192 uint8_t gp2_pin_value; 193 uint8_t gp2_pin_dir; 194 195 uint8_t gp3_pin_value; 196 uint8_t gp3_pin_dir; 197 198 uint8_t dontcare[54]; 199 }; 200 201 #define MCP2221_SRAM_GPIO_CHANGE_DCCD 0x80 202 203 #define MCP2221_SRAM_GPIO_CLOCK_DC_MASK 0x18 204 #define MCP2221_SRAM_GPIO_CLOCK_DC_75 0x18 205 #define MCP2221_SRAM_GPIO_CLOCK_DC_50 0x10 206 #define MCP2221_SRAM_GPIO_CLOCK_DC_25 0x08 207 #define MCP2221_SRAM_GPIO_CLOCK_DC_0 0x00 208 209 #define MCP2221_SRAM_GPIO_CLOCK_CD_MASK 0x07 210 #define MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ 0x07 211 #define MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ 0x06 212 #define MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ 0x05 213 #define MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ 0x04 214 #define MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ 0x03 215 #define MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ 0x02 216 #define MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ 0x01 217 218 #define MCP2221_SRAM_CHANGE_DAC_VREF 0x80 219 #define MCP2221_SRAM_DAC_IS_VRM 0x20 220 #define MCP2221_SRAM_DAC_VRM_MASK 0xC0 221 #define MCP2221_SRAM_DAC_VRM_4096V 0xC0 222 #define MCP2221_SRAM_DAC_VRM_2048V 0x80 223 #define MCP2221_SRAM_DAC_VRM_1024V 0x40 224 #define MCP2221_SRAM_DAC_VRM_OFF 0x00 225 #define MCP2221_SRAM_CHANGE_DAC_VALUE 0x80 226 #define MCP2221_SRAM_DAC_VALUE_MASK 0x1F 227 228 #define MCP2221_SRAM_CHANGE_ADC_VREF 0x80 229 #define MCP2221_SRAM_ADC_IS_VRM 0x04 230 #define MCP2221_SRAM_ADC_VRM_MASK 0x18 231 #define MCP2221_SRAM_ADC_VRM_4096V 0x18 232 #define MCP2221_SRAM_ADC_VRM_2048V 0x10 233 #define MCP2221_SRAM_ADC_VRM_1024V 0x08 234 #define MCP2221_SRAM_ADC_VRM_OFF 0x00 235 236 #define MCP2221_SRAM_ALTER_IRQ 0x80 237 #define MCP2221_SRAM_ALTER_POS_EDGE 0x10 238 #define MCP2221_SRAM_ENABLE_POS_EDGE 0x08 239 #define MCP2221_SRAM_ALTER_NEG_EDGE 0x04 240 #define MCP2221_SRAM_ENABLE_NEG_EDGE 0x02 241 #define MCP2221_SRAM_CLEAR_IRQ 0x01 242 243 #define MCP2221_SRAM_ALTER_GPIO 0xff 244 #define MCP2221_SRAM_GPIO_HIGH 0x0f 245 #define MCP2221_SRAM_GPIO_OUTPUT_HIGH 0x10 246 #define MCP2221_SRAM_GPIO_TYPE_MASK 0x08 247 #define MCP2221_SRAM_GPIO_INPUT 0x08 248 #define MCP2221_SRAM_PIN_TYPE_MASK 0x07 249 #define MCP2221_SRAM_PIN_IS_GPIO 0x00 250 #define MCP2221_SRAM_PIN_IS_DED 0x01 251 #define MCP2221_SRAM_PIN_IS_ALT0 0x02 252 #define MCP2221_SRAM_PIN_IS_ALT1 0x03 253 #define MCP2221_SRAM_PIN_IS_ALT2 0x04 254 255 256 struct mcp2221_set_sram_req { 257 uint8_t cmd; /* MCP2221_CMD_SET_SRAM */ 258 uint8_t dontcare1; 259 260 uint8_t clock_output_divider; 261 uint8_t dac_voltage_reference; 262 uint8_t set_dac_output_value; 263 uint8_t adc_voltage_reference; 264 uint8_t irq_config; 265 266 uint8_t alter_gpio_config; 267 uint8_t gp0_settings; 268 uint8_t gp1_settings; 269 uint8_t gp2_settings; 270 uint8_t gp3_settings; 271 272 uint8_t reserved[52]; 273 }; 274 275 struct mcp2221_set_sram_res { 276 uint8_t cmd; 277 uint8_t completion; 278 uint8_t dontcare[62]; 279 }; 280 281 struct mcp2221_get_sram_req { 282 uint8_t cmd; /* MCP2221_CMD_GET_SRAM */ 283 uint8_t dontcare[63]; 284 }; 285 286 struct mcp2221_get_sram_res { 287 uint8_t cmd; 288 uint8_t completion; 289 290 uint8_t len_chip_setting; 291 uint8_t len_gpio_setting; 292 293 uint8_t sn_initial_ps_cs; 294 uint8_t clock_divider; 295 uint8_t dac_reference_voltage; 296 uint8_t irq_adc_reference_voltage; 297 298 uint8_t lsb_usb_vid; 299 uint8_t msb_usb_vid; 300 uint8_t lsb_usb_pid; 301 uint8_t msb_usb_pid; 302 303 uint8_t usb_power_attributes; 304 uint8_t usb_requested_ma; 305 306 uint8_t current_password_byte_1; 307 uint8_t current_password_byte_2; 308 uint8_t current_password_byte_3; 309 uint8_t current_password_byte_4; 310 uint8_t current_password_byte_5; 311 uint8_t current_password_byte_6; 312 uint8_t current_password_byte_7; 313 uint8_t current_password_byte_8; 314 315 uint8_t gp0_settings; 316 uint8_t gp1_settings; 317 uint8_t gp2_settings; 318 uint8_t gp3_settings; 319 320 uint8_t dontcare[38]; 321 }; 322 323 #define MCP2221_I2C_ENGINE_BUSY 0x01 324 #define MCP2221_ENGINE_STARTTIMEOUT 0x12 325 #define MCP2221_ENGINE_REPSTARTTIMEOUT 0x17 326 #define MCP2221_ENGINE_STOPTIMEOUT 0x62 327 #define MCP2221_ENGINE_ADDRSEND 0x21 328 #define MCP2221_ENGINE_ADDRTIMEOUT 0x23 329 #define MCP2221_ENGINE_PARTIALDATA 0x41 330 #define MCP2221_ENGINE_READMORE 0x43 331 #define MCP2221_ENGINE_WRITETIMEOUT 0x44 332 #define MCP2221_ENGINE_READTIMEOUT 0x52 333 #define MCP2221_ENGINE_READPARTIAL 0x54 334 #define MCP2221_ENGINE_READCOMPLETE 0x55 335 #define MCP2221_ENGINE_ADDRNACK 0x25 336 #define MCP2221_ENGINE_WRITINGNOSTOP 0x45 337 338 struct mcp2221_i2c_req { 339 uint8_t cmd; /* MCP2221_I2C_WRITE_DATA 340 * MCP2221_I2C_READ_DATA 341 * MCP2221_I2C_WRITE_DATA_RS 342 * MCP2221_I2C_READ_DATA_RS 343 * MCP2221_I2C_WRITE_DATA_NS 344 */ 345 uint8_t lsblen; 346 uint8_t msblen; 347 uint8_t slaveaddr; 348 uint8_t data[60]; 349 }; 350 351 struct mcp2221_i2c_res { 352 uint8_t cmd; 353 uint8_t completion; 354 uint8_t internal_i2c_state; 355 uint8_t dontcare[61]; 356 }; 357 358 #define MCP2221_FETCH_READ_PARTIALDATA 0x41 359 #define MCP2221_FETCH_READERROR 0x7F 360 361 struct mcp2221_i2c_fetch_req { 362 uint8_t cmd; /* MCP2221_CMD_I2C_FETCH_READ_DATA */ 363 uint8_t dontcare[63]; 364 }; 365 366 struct mcp2221_i2c_fetch_res { 367 uint8_t cmd; 368 uint8_t completion; 369 uint8_t internal_i2c_state; 370 uint8_t fetchlen; 371 uint8_t data[60]; 372 }; 373 374 #define MCP2221_FLASH_SUBCODE_CS 0x00 375 #define MCP2221_FLASH_SUBCODE_GP 0x01 376 #define MCP2221_FLASH_SUBCODE_USBMAN 0x02 377 #define MCP2221_FLASH_SUBCODE_USBPROD 0x03 378 #define MCP2221_FLASH_SUBCODE_USBSN 0x04 379 #define MCP2221_FLASH_SUBCODE_CHIPSN 0x05 380 381 struct mcp2221_get_flash_req { 382 uint8_t cmd; /* MCP2221_CMD_GET_FLASH */ 383 uint8_t subcode; 384 uint8_t reserved[62]; 385 }; 386 387 struct mcp2221_get_flash_res { 388 uint8_t cmd; 389 uint8_t completion; 390 uint8_t res_len; 391 union { 392 struct { 393 uint8_t dontcare; 394 uint8_t uartenum_led_protection; 395 uint8_t clock_divider; 396 uint8_t dac_reference_voltage; 397 uint8_t irq_adc_reference_voltage; 398 uint8_t lsb_usb_vid; 399 uint8_t msb_usb_vid; 400 uint8_t lsb_usb_pid; 401 uint8_t msb_usb_pid; 402 uint8_t usb_power_attributes; 403 uint8_t usb_requested_ma; 404 uint8_t dontcare2[50]; 405 } cs; 406 struct { 407 uint8_t dontcare; 408 uint8_t gp0_settings; 409 uint8_t gp1_settings; 410 uint8_t gp2_settings; 411 uint8_t gp3_settings; 412 uint8_t dontcare2[56]; 413 } gp; 414 struct { 415 uint8_t always0x03; 416 uint8_t unicode_man_descriptor[60]; 417 } usbman; 418 struct { 419 uint8_t always0x03; 420 uint8_t unicode_product_descriptor[60]; 421 } usbprod; 422 struct usbsn { 423 uint8_t always0x03; 424 uint8_t unicode_serial_number[60]; 425 } usbsn; 426 struct { 427 uint8_t dontcare; 428 uint8_t factory_serial_number[60]; 429 } chipsn; 430 } u; 431 }; 432 433 #define MCP2221_FLASH_GPIO_HIGH 0x0f 434 #define MCP2221_FLASH_GPIO_VALUE_MASK 0x10 435 #define MCP2221_FLASH_GPIO_TYPE_MASK 0x08 436 #define MCP2221_FLASH_GPIO_INPUT 0x08 437 #define MCP2221_FLASH_PIN_TYPE_MASK 0x07 438 #define MCP2221_FLASH_PIN_IS_GPIO 0x00 439 #define MCP2221_FLASH_PIN_IS_DED 0x01 440 #define MCP2221_FLASH_PIN_IS_ALT0 0x02 441 #define MCP2221_FLASH_PIN_IS_ALT1 0x03 442 #define MCP2221_FLASH_PIN_IS_ALT2 0x04 443 444 struct mcp2221_put_flash_req { 445 uint8_t cmd; /* MCP2221_CMD_SET_FLASH */ 446 uint8_t subcode; 447 union { 448 struct { 449 uint8_t uartenum_led_protection; 450 uint8_t clock_divider; 451 uint8_t dac_reference_voltage; 452 uint8_t irq_adc_reference_voltage; 453 uint8_t lsb_usb_vid; 454 uint8_t msb_usb_vid; 455 uint8_t lsb_usb_pid; 456 uint8_t msb_usb_pid; 457 uint8_t usb_power_attributes; 458 uint8_t usb_requested_ma; 459 uint8_t password_byte_1; 460 uint8_t password_byte_2; 461 uint8_t password_byte_3; 462 uint8_t password_byte_4; 463 uint8_t password_byte_5; 464 uint8_t password_byte_6; 465 uint8_t password_byte_7; 466 uint8_t password_byte_8; 467 uint8_t dontcare[44]; 468 } cs; 469 struct { 470 uint8_t gp0_settings; 471 uint8_t gp1_settings; 472 uint8_t gp2_settings; 473 uint8_t gp3_settings; 474 uint8_t dontcare[58]; 475 } gp; 476 struct { 477 uint8_t len; 478 uint8_t always0x03; 479 uint8_t unicode_man_descriptor[60]; 480 } usbman; 481 struct { 482 uint8_t len; 483 uint8_t always0x03; 484 uint8_t unicode_product_descriptor[60]; 485 } usbprod; 486 struct { 487 uint8_t len; 488 uint8_t always0x03; 489 uint8_t unicode_serial_number[60]; 490 } usbsn; 491 } u; 492 }; 493 494 struct mcp2221_put_flash_res { 495 uint8_t cmd; 496 uint8_t completion; 497 uint8_t dontcare[62]; 498 }; 499 500 /* XXX - missing is the submit password call to unlock the chip */ 501 502 #endif 503
Indexes created Thu Oct 02 10:09:58 GMT 2025