umcpmio_hid_reports.h revision 1.2
1 /* $NetBSD: umcpmio_hid_reports.h,v 1.2 2025/03/17 18:24:08 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2024 Brad Spencer <brad (at) anduin.eldar.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _UMCPMIO_HID_REPORTS_H_ 20 #define _UMCPMIO_HID_REPORTS_H_ 21 22 #include <sys/types.h> 23 24 /* 25 * It is nice that all HID reports want a 64 byte request and return a 26 * 64 byte response. 27 */ 28 29 #define MCP2221_REQ_BUFFER_SIZE 64 30 #define MCP2221_RES_BUFFER_SIZE 64 31 32 #define MCP2221_CMD_STATUS 0x10 33 34 #define MCP2221_CMD_I2C_FETCH_READ_DATA 0x40 35 36 #define MCP2221_CMD_SET_GPIO_CFG 0x50 37 #define MCP2221_CMD_GET_GPIO_CFG 0x51 38 39 #define MCP2221_CMD_SET_SRAM 0x60 40 #define MCP2221_CMD_GET_SRAM 0x61 41 42 #define MCP2221_I2C_WRITE_DATA 0x90 43 #define MCP2221_I2C_READ_DATA 0x91 44 #define MCP2221_I2C_WRITE_DATA_RS 0x92 45 #define MCP2221_I2C_READ_DATA_RS 0x93 46 #define MCP2221_I2C_WRITE_DATA_NS 0x94 47 48 #define MCP2221_CMD_GET_FLASH 0xb0 49 #define MCP2221_CMD_SET_FLASH 0xb1 50 #define MCP2221_CMD_SEND_FLASH_PASSWORD 0xb2 51 52 #define MCP2221_CMD_COMPLETE_OK 0x00 53 #define MCP2221_CMD_COMPLETE_NO_SUPPORT 0x02 54 #define MCP2221_CMD_COMPLETE_EPERM 0x03 55 56 #define MCP2221_I2C_DO_CANCEL 0x10 57 #define MCP2221_INTERNAL_CLOCK 12000000 58 #define MCP2221_DEFAULT_I2C_SPEED 100000 59 #define MCP2221_I2C_SET_SPEED 0x20 60 61 /* The request and response structures are, perhaps, over literal. */ 62 63 struct mcp2221_status_req { 64 uint8_t cmd; /* MCP2221_CMD_STATUS */ 65 uint8_t dontcare1; 66 uint8_t cancel_transfer; 67 uint8_t set_i2c_speed; 68 uint8_t i2c_clock_divider; 69 uint8_t dontcare2[59]; 70 }; 71 72 #define MCP2221_I2C_SPEED_SET 0x20 73 #define MCP2221_I2C_SPEED_BUSY 0x21 74 #define MCP2221_ENGINE_T1_MASK_NACK 0x40 75 76 struct mcp2221_status_res { 77 uint8_t cmd; 78 uint8_t completion; 79 uint8_t cancel_transfer; 80 uint8_t set_i2c_speed; 81 uint8_t i2c_clock_divider; 82 uint8_t dontcare2[3]; 83 uint8_t internal_i2c_state; 84 uint8_t lsb_i2c_req_len; 85 uint8_t msb_i2c_req_len; 86 uint8_t lsb_i2c_trans_len; 87 uint8_t msb_i2c_trans_len; 88 uint8_t internal_i2c_bcount; 89 uint8_t i2c_speed_divider; 90 uint8_t i2c_timeout_value; 91 uint8_t lsb_i2c_address; 92 uint8_t msb_i2c_address; 93 uint8_t dontcare3a[2]; 94 uint8_t internal_i2c_state20; 95 uint8_t dontcare3b; 96 uint8_t scl_line_value; 97 uint8_t sda_line_value; 98 uint8_t interrupt_edge_state; 99 uint8_t i2c_read_pending; 100 uint8_t dontcare4[20]; 101 uint8_t mcp2221_hardware_rev_major; 102 uint8_t mcp2221_hardware_rev_minor; 103 uint8_t mcp2221_firmware_rev_major; 104 uint8_t mcp2221_firmware_rev_minor; 105 uint8_t adc_channel0_lsb; 106 uint8_t adc_channel0_msb; 107 uint8_t adc_channel1_lsb; 108 uint8_t adc_channel1_msb; 109 uint8_t adc_channel2_lsb; 110 uint8_t adc_channel2_msb; 111 uint8_t dontcare5[8]; 112 }; 113 114 #define MCP2221_GPIO_CFG_ALTER 0xff 115 116 struct mcp2221_set_gpio_cfg_req { 117 uint8_t cmd; /* MCP2221_CMD_SET_GPIO_CFG */ 118 uint8_t dontcare1; 119 120 uint8_t alter_gp0_value; 121 uint8_t new_gp0_value; 122 uint8_t alter_gp0_dir; 123 uint8_t new_gp0_dir; 124 125 uint8_t alter_gp1_value; 126 uint8_t new_gp1_value; 127 uint8_t alter_gp1_dir; 128 uint8_t new_gp1_dir; 129 130 uint8_t alter_gp2_value; 131 uint8_t new_gp2_value; 132 uint8_t alter_gp2_dir; 133 uint8_t new_gp2_dir; 134 135 uint8_t alter_gp3_value; 136 uint8_t new_gp3_value; 137 uint8_t alter_gp3_dir; 138 uint8_t new_gp3_dir; 139 140 uint8_t reserved[46]; 141 }; 142 143 struct mcp2221_set_gpio_cfg_res { 144 uint8_t cmd; 145 uint8_t completion; 146 147 uint8_t alter_gp0_value; 148 uint8_t new_gp0_value; 149 uint8_t alter_gp0_dir; 150 uint8_t new_gp0_dir; 151 152 uint8_t alter_gp1_value; 153 uint8_t new_gp1_value; 154 uint8_t alter_gp1_dir; 155 uint8_t new_gp1_dir; 156 157 uint8_t alter_gp2_value; 158 uint8_t new_gp2_value; 159 uint8_t alter_gp2_dir; 160 uint8_t new_gp2_dir; 161 162 uint8_t alter_gp3_value; 163 uint8_t new_gp3_value; 164 uint8_t alter_gp3_dir; 165 uint8_t new_gp3_dir; 166 167 uint8_t dontcare[46]; 168 }; 169 170 struct mcp2221_get_gpio_cfg_req { 171 uint8_t cmd; /* MCP2221_CMD_GET_GPIO_CFG */ 172 uint8_t dontcare[63]; 173 }; 174 175 #define MCP2221_GPIO_CFG_VALUE_NOT_GPIO 0xEE 176 #define MCP2221_GPIO_CFG_DIR_NOT_GPIO 0xEF 177 #define MCP2221_GPIO_CFG_DIR_INPUT 0x01 178 #define MCP2221_GPIO_CFG_DIR_OUTPUT 0x00 179 180 struct mcp2221_get_gpio_cfg_res { 181 uint8_t cmd; 182 uint8_t completion; 183 184 uint8_t gp0_pin_value; 185 uint8_t gp0_pin_dir; 186 187 uint8_t gp1_pin_value; 188 uint8_t gp1_pin_dir; 189 190 uint8_t gp2_pin_value; 191 uint8_t gp2_pin_dir; 192 193 uint8_t gp3_pin_value; 194 uint8_t gp3_pin_dir; 195 196 uint8_t dontcare[54]; 197 }; 198 199 #define MCP2221_SRAM_GPIO_CHANGE_DCCD 0x80 200 201 #define MCP2221_SRAM_GPIO_CLOCK_DC_MASK 0x18 202 #define MCP2221_SRAM_GPIO_CLOCK_DC_75 0x18 203 #define MCP2221_SRAM_GPIO_CLOCK_DC_50 0x10 204 #define MCP2221_SRAM_GPIO_CLOCK_DC_25 0x08 205 #define MCP2221_SRAM_GPIO_CLOCK_DC_0 0x00 206 207 #define MCP2221_SRAM_GPIO_CLOCK_CD_MASK 0x07 208 #define MCP2221_SRAM_GPIO_CLOCK_CD_375KHZ 0x07 209 #define MCP2221_SRAM_GPIO_CLOCK_CD_750KHZ 0x06 210 #define MCP2221_SRAM_GPIO_CLOCK_CD_1P5MHZ 0x05 211 #define MCP2221_SRAM_GPIO_CLOCK_CD_3MHZ 0x04 212 #define MCP2221_SRAM_GPIO_CLOCK_CD_6MHZ 0x03 213 #define MCP2221_SRAM_GPIO_CLOCK_CD_12MHZ 0x02 214 #define MCP2221_SRAM_GPIO_CLOCK_CD_24MHZ 0x01 215 216 #define MCP2221_SRAM_CHANGE_DAC_VREF 0x80 217 #define MCP2221_SRAM_DAC_IS_VRM 0x20 218 #define MCP2221_SRAM_DAC_VRM_MASK 0xC0 219 #define MCP2221_SRAM_DAC_VRM_4096V 0xC0 220 #define MCP2221_SRAM_DAC_VRM_2048V 0x80 221 #define MCP2221_SRAM_DAC_VRM_1024V 0x40 222 #define MCP2221_SRAM_DAC_VRM_OFF 0x00 223 #define MCP2221_SRAM_CHANGE_DAC_VALUE 0x80 224 #define MCP2221_SRAM_DAC_VALUE_MASK 0x1F 225 226 #define MCP2221_SRAM_CHANGE_ADC_VREF 0x80 227 #define MCP2221_SRAM_ADC_IS_VRM 0x04 228 #define MCP2221_SRAM_ADC_VRM_MASK 0x18 229 #define MCP2221_SRAM_ADC_VRM_4096V 0x18 230 #define MCP2221_SRAM_ADC_VRM_2048V 0x10 231 #define MCP2221_SRAM_ADC_VRM_1024V 0x08 232 #define MCP2221_SRAM_ADC_VRM_OFF 0x00 233 234 #define MCP2221_SRAM_ALTER_IRQ 0x80 235 #define MCP2221_SRAM_ALTER_POS_EDGE 0x10 236 #define MCP2221_SRAM_ENABLE_POS_EDGE 0x08 237 #define MCP2221_SRAM_ALTER_NEG_EDGE 0x04 238 #define MCP2221_SRAM_ENABLE_NEG_EDGE 0x02 239 #define MCP2221_SRAM_CLEAR_IRQ 0x01 240 241 #define MCP2221_SRAM_ALTER_GPIO 0xff 242 #define MCP2221_SRAM_GPIO_HIGH 0x0f 243 #define MCP2221_SRAM_GPIO_OUTPUT_HIGH 0x10 244 #define MCP2221_SRAM_GPIO_TYPE_MASK 0x08 245 #define MCP2221_SRAM_GPIO_INPUT 0x08 246 #define MCP2221_SRAM_PIN_TYPE_MASK 0x07 247 #define MCP2221_SRAM_PIN_IS_GPIO 0x00 248 #define MCP2221_SRAM_PIN_IS_DED 0x01 249 #define MCP2221_SRAM_PIN_IS_ALT0 0x02 250 #define MCP2221_SRAM_PIN_IS_ALT1 0x03 251 #define MCP2221_SRAM_PIN_IS_ALT2 0x04 252 253 struct mcp2221_set_sram_req { 254 uint8_t cmd; /* MCP2221_CMD_SET_SRAM */ 255 uint8_t dontcare1; 256 257 uint8_t clock_output_divider; 258 uint8_t dac_voltage_reference; 259 uint8_t set_dac_output_value; 260 uint8_t adc_voltage_reference; 261 uint8_t irq_config; 262 263 uint8_t alter_gpio_config; 264 uint8_t gp0_settings; 265 uint8_t gp1_settings; 266 uint8_t gp2_settings; 267 uint8_t gp3_settings; 268 269 uint8_t reserved[52]; 270 }; 271 272 struct mcp2221_set_sram_res { 273 uint8_t cmd; 274 uint8_t completion; 275 uint8_t dontcare[62]; 276 }; 277 278 struct mcp2221_get_sram_req { 279 uint8_t cmd; /* MCP2221_CMD_GET_SRAM */ 280 uint8_t dontcare[63]; 281 }; 282 283 struct mcp2221_get_sram_res { 284 uint8_t cmd; 285 uint8_t completion; 286 287 uint8_t len_chip_setting; 288 uint8_t len_gpio_setting; 289 290 uint8_t sn_initial_ps_cs; 291 uint8_t clock_divider; 292 uint8_t dac_reference_voltage; 293 uint8_t irq_adc_reference_voltage; 294 295 uint8_t lsb_usb_vid; 296 uint8_t msb_usb_vid; 297 uint8_t lsb_usb_pid; 298 uint8_t msb_usb_pid; 299 300 uint8_t usb_power_attributes; 301 uint8_t usb_requested_ma; 302 303 uint8_t current_password_byte_1; 304 uint8_t current_password_byte_2; 305 uint8_t current_password_byte_3; 306 uint8_t current_password_byte_4; 307 uint8_t current_password_byte_5; 308 uint8_t current_password_byte_6; 309 uint8_t current_password_byte_7; 310 uint8_t current_password_byte_8; 311 312 uint8_t gp0_settings; 313 uint8_t gp1_settings; 314 uint8_t gp2_settings; 315 uint8_t gp3_settings; 316 317 uint8_t dontcare[38]; 318 }; 319 320 #define MCP2221_I2C_ENGINE_BUSY 0x01 321 #define MCP2221_ENGINE_STARTTIMEOUT 0x12 322 #define MCP2221_ENGINE_REPSTARTTIMEOUT 0x17 323 #define MCP2221_ENGINE_STOPTIMEOUT 0x62 324 #define MCP2221_ENGINE_ADDRSEND 0x21 325 #define MCP2221_ENGINE_ADDRTIMEOUT 0x23 326 #define MCP2221_ENGINE_PARTIALDATA 0x41 327 #define MCP2221_ENGINE_READMORE 0x43 328 #define MCP2221_ENGINE_WRITETIMEOUT 0x44 329 #define MCP2221_ENGINE_READTIMEOUT 0x52 330 #define MCP2221_ENGINE_READPARTIAL 0x54 331 #define MCP2221_ENGINE_READCOMPLETE 0x55 332 #define MCP2221_ENGINE_ADDRNACK 0x25 333 #define MCP2221_ENGINE_WRITINGNOSTOP 0x45 334 335 struct mcp2221_i2c_req { 336 uint8_t cmd; /* MCP2221_I2C_WRITE_DATA 337 * MCP2221_I2C_READ_DATA 338 * MCP2221_I2C_WRITE_DATA_RS 339 * MCP2221_I2C_READ_DATA_RS 340 * MCP2221_I2C_WRITE_DATA_NS 341 */ 342 uint8_t lsblen; 343 uint8_t msblen; 344 uint8_t slaveaddr; 345 uint8_t data[60]; 346 }; 347 348 struct mcp2221_i2c_res { 349 uint8_t cmd; 350 uint8_t completion; 351 uint8_t internal_i2c_state; 352 uint8_t dontcare[61]; 353 }; 354 355 #define MCP2221_FETCH_READ_PARTIALDATA 0x41 356 #define MCP2221_FETCH_READERROR 0x7F 357 358 struct mcp2221_i2c_fetch_req { 359 uint8_t cmd; /* MCP2221_CMD_I2C_FETCH_READ_DATA */ 360 uint8_t dontcare[63]; 361 }; 362 363 struct mcp2221_i2c_fetch_res { 364 uint8_t cmd; 365 uint8_t completion; 366 uint8_t internal_i2c_state; 367 uint8_t fetchlen; 368 uint8_t data[60]; 369 }; 370 371 #define MCP2221_FLASH_SUBCODE_CS 0x00 372 #define MCP2221_FLASH_SUBCODE_GP 0x01 373 #define MCP2221_FLASH_SUBCODE_USBMAN 0x02 374 #define MCP2221_FLASH_SUBCODE_USBPROD 0x03 375 #define MCP2221_FLASH_SUBCODE_USBSN 0x04 376 #define MCP2221_FLASH_SUBCODE_CHIPSN 0x05 377 378 struct mcp2221_get_flash_req { 379 uint8_t cmd; /* MCP2221_CMD_GET_FLASH */ 380 uint8_t subcode; 381 uint8_t reserved[62]; 382 }; 383 384 struct mcp2221_get_flash_res { 385 uint8_t cmd; 386 uint8_t completion; 387 uint8_t res_len; 388 union { 389 struct { 390 uint8_t dontcare; 391 uint8_t uartenum_led_protection; 392 uint8_t clock_divider; 393 uint8_t dac_reference_voltage; 394 uint8_t irq_adc_reference_voltage; 395 uint8_t lsb_usb_vid; 396 uint8_t msb_usb_vid; 397 uint8_t lsb_usb_pid; 398 uint8_t msb_usb_pid; 399 uint8_t usb_power_attributes; 400 uint8_t usb_requested_ma; 401 uint8_t dontcare2[50]; 402 } cs; 403 struct { 404 uint8_t dontcare; 405 uint8_t gp0_settings; 406 uint8_t gp1_settings; 407 uint8_t gp2_settings; 408 uint8_t gp3_settings; 409 uint8_t dontcare2[56]; 410 } gp; 411 struct { 412 uint8_t always0x03; 413 uint8_t unicode_man_descriptor[60]; 414 } usbman; 415 struct { 416 uint8_t always0x03; 417 uint8_t unicode_product_descriptor[60]; 418 } usbprod; 419 struct usbsn { 420 uint8_t always0x03; 421 uint8_t unicode_serial_number[60]; 422 } usbsn; 423 struct { 424 uint8_t dontcare; 425 uint8_t factory_serial_number[60]; 426 } chipsn; 427 } u; 428 }; 429 430 #define MCP2221_FLASH_GPIO_HIGH 0x0f 431 #define MCP2221_FLASH_GPIO_VALUE_MASK 0x10 432 #define MCP2221_FLASH_GPIO_TYPE_MASK 0x08 433 #define MCP2221_FLASH_GPIO_INPUT 0x08 434 #define MCP2221_FLASH_PIN_TYPE_MASK 0x07 435 #define MCP2221_FLASH_PIN_IS_GPIO 0x00 436 #define MCP2221_FLASH_PIN_IS_DED 0x01 437 #define MCP2221_FLASH_PIN_IS_ALT0 0x02 438 #define MCP2221_FLASH_PIN_IS_ALT1 0x03 439 #define MCP2221_FLASH_PIN_IS_ALT2 0x04 440 441 struct mcp2221_put_flash_req { 442 uint8_t cmd; /* MCP2221_CMD_SET_FLASH */ 443 uint8_t subcode; 444 union { 445 struct { 446 uint8_t uartenum_led_protection; 447 uint8_t clock_divider; 448 uint8_t dac_reference_voltage; 449 uint8_t irq_adc_reference_voltage; 450 uint8_t lsb_usb_vid; 451 uint8_t msb_usb_vid; 452 uint8_t lsb_usb_pid; 453 uint8_t msb_usb_pid; 454 uint8_t usb_power_attributes; 455 uint8_t usb_requested_ma; 456 uint8_t password_byte_1; 457 uint8_t password_byte_2; 458 uint8_t password_byte_3; 459 uint8_t password_byte_4; 460 uint8_t password_byte_5; 461 uint8_t password_byte_6; 462 uint8_t password_byte_7; 463 uint8_t password_byte_8; 464 uint8_t dontcare[44]; 465 } cs; 466 struct { 467 uint8_t gp0_settings; 468 uint8_t gp1_settings; 469 uint8_t gp2_settings; 470 uint8_t gp3_settings; 471 uint8_t dontcare[58]; 472 } gp; 473 struct { 474 uint8_t len; 475 uint8_t always0x03; 476 uint8_t unicode_man_descriptor[60]; 477 } usbman; 478 struct { 479 uint8_t len; 480 uint8_t always0x03; 481 uint8_t unicode_product_descriptor[60]; 482 } usbprod; 483 struct { 484 uint8_t len; 485 uint8_t always0x03; 486 uint8_t unicode_serial_number[60]; 487 } usbsn; 488 } u; 489 }; 490 491 struct mcp2221_put_flash_res { 492 uint8_t cmd; 493 uint8_t completion; 494 uint8_t dontcare[62]; 495 }; 496 497 /* XXX - missing is the submit password call to unlock the chip */ 498 499 #endif /* _UMCPMIO_HID_REPORTS_H_ */ 500
Indexes created Tue Sep 23 14:10:03 GMT 2025