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      1  1.2  martin /*	$NetBSD: umct.h,v 1.2 2008/04/28 20:24:00 martin Exp $	*/
      2  1.1  ichiro /*
      3  1.1  ichiro  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      4  1.1  ichiro  * All rights reserved.
      5  1.1  ichiro  *
      6  1.1  ichiro  * This code is derived from software contributed to The NetBSD Foundation
      7  1.1  ichiro  * by Ichiro FUKUHARA (ichiro (at) ichiro.org).
      8  1.1  ichiro  *
      9  1.1  ichiro  * Redistribution and use in source and binary forms, with or without
     10  1.1  ichiro  * modification, are permitted provided that the following conditions
     11  1.1  ichiro  * are met:
     12  1.1  ichiro  * 1. Redistributions of source code must retain the above copyright
     13  1.1  ichiro  *    notice, this list of conditions and the following disclaimer.
     14  1.1  ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     15  1.1  ichiro  *    notice, this list of conditions and the following disclaimer in the
     16  1.1  ichiro  *    documentation and/or other materials provided with the distribution.
     17  1.1  ichiro  *
     18  1.1  ichiro  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     19  1.1  ichiro  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     20  1.1  ichiro  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     21  1.1  ichiro  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     22  1.1  ichiro  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  1.1  ichiro  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  1.1  ichiro  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  1.1  ichiro  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  1.1  ichiro  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  1.1  ichiro  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  1.1  ichiro  * POSSIBILITY OF SUCH DAMAGE.
     29  1.1  ichiro  */
     30  1.1  ichiro 
     31  1.1  ichiro /*
     32  1.1  ichiro  * Vendor Request Interface
     33  1.1  ichiro  */
     34  1.1  ichiro #define UMCT_SET_REQUEST	0x40
     35  1.1  ichiro #define UMCT_GET_REQUEST	0xc0
     36  1.1  ichiro 
     37  1.1  ichiro #define REQ_SET_BAUD_RATE	5	/* Set Baud Rate Divisor */
     38  1.1  ichiro #define LENGTH_BAUD_RATE	4
     39  1.1  ichiro 
     40  1.1  ichiro #define REQ_GET_MSR		2	/* Get Modem Status Register (MSR) */
     41  1.1  ichiro #define LENGTH_GET_MSR		1
     42  1.1  ichiro 
     43  1.1  ichiro #define REQ_GET_LCR		6	/* Get Line Control Register (LCR) */
     44  1.1  ichiro #define LENGTH_GET_LCR		1
     45  1.1  ichiro 
     46  1.1  ichiro #define REQ_SET_LCR		7	/* Set Line Control Register (LCR) */
     47  1.1  ichiro #define LENGTH_SET_LCR		1
     48  1.1  ichiro 
     49  1.1  ichiro #define REQ_SET_MCR		10	/* Set Modem Control Register (MCR) */
     50  1.1  ichiro #define LENGTH_SET_MCR		1
     51  1.1  ichiro 
     52  1.1  ichiro /*
     53  1.1  ichiro  * Baud rate (divisor)
     54  1.1  ichiro  */
     55  1.1  ichiro #define UMCT_BAUD_RATE(b)	(115200/b)
     56  1.1  ichiro 
     57  1.1  ichiro /*
     58  1.1  ichiro  * Line Control Register (LCR)
     59  1.1  ichiro  */
     60  1.1  ichiro #define LCR_SET_BREAK		0x40
     61  1.1  ichiro #define LCR_PARITY_EVEN		0x18
     62  1.1  ichiro #define LCR_PARITY_ODD		0x08
     63  1.1  ichiro #define LCR_PARITY_NONE		0x00
     64  1.1  ichiro #define LCR_DATA_BITS_5		0x00
     65  1.1  ichiro #define LCR_DATA_BITS_6		0x01
     66  1.1  ichiro #define LCR_DATA_BITS_7		0x02
     67  1.1  ichiro #define LCR_DATA_BITS_8		0x03
     68  1.1  ichiro #define LCR_STOP_BITS_2		0x04
     69  1.1  ichiro #define LCR_STOP_BITS_1		0x00
     70  1.1  ichiro 
     71  1.1  ichiro /*
     72  1.1  ichiro  * Modem Control Register (MCR)
     73  1.1  ichiro  */
     74  1.1  ichiro #define MCR_NONE		0x8
     75  1.1  ichiro #define MCR_RTS			0xa
     76  1.1  ichiro #define MCR_DTR			0x9
     77  1.1  ichiro 
     78  1.1  ichiro /*
     79  1.1  ichiro  * Modem Status Register (MSR)
     80  1.1  ichiro  */
     81  1.1  ichiro #define MSR_CD			0x80	/* Current CD */
     82  1.1  ichiro #define MSR_RI			0x40	/* Current RI */
     83  1.1  ichiro #define MSR_DSR			0x20	/* Current DSR */
     84  1.1  ichiro #define MSR_CTS			0x10	/* Current CTS */
     85  1.1  ichiro #define MSR_DCD			0x08	/* Delta CD */
     86  1.1  ichiro #define MSR_DRI			0x04	/* Delta RI */
     87  1.1  ichiro #define MSR_DDSR		0x02	/* Delta DSR */
     88  1.1  ichiro #define MSR_DCTS		0x01	/* Delta CTS */
     89  1.1  ichiro 
     90  1.1  ichiro /*
     91  1.1  ichiro  * Line Status Register (LSR)
     92  1.1  ichiro  */
     93  1.1  ichiro #define LSR_ERR			0x80	/* OE | PE | FE | BI */
     94  1.1  ichiro #define LSR_TEMT		0x40	/* transmit register empty */
     95  1.1  ichiro #define LSR_THRE		0x20	/* transmit holding register empty */
     96  1.1  ichiro #define LSR_BI			0x10	/* break indicator */
     97  1.1  ichiro #define LSR_FE			0x08	/* framing error */
     98  1.1  ichiro #define LSR_OE			0x02	/* overrun error */
     99  1.1  ichiro #define LSR_PE			0x04	/* parity error */
    100  1.1  ichiro #define LSR_OE			0x02	/* overrun error */
    101  1.1  ichiro #define LSR_DR			0x01	/* receive data ready */
    102