xhci.c revision 1.1
1 /* $NetBSD: xhci.c,v 1.1 2013/09/14 00:40:31 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.1 2013/09/14 00:40:31 jakllsch Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/kmem.h> 36 #include <sys/malloc.h> 37 #include <sys/device.h> 38 #include <sys/select.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 #include <sys/cpu.h> 45 46 #include <machine/endian.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 #include <dev/usb/usb_quirks.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 #include <dev/usb/usbroothub_subr.h> 57 58 #ifdef XHCI_DEBUG 59 int xhcidebug = 0; 60 #define DPRINTF(x) do { if (xhcidebug) printf x; } while(0) 61 #define DPRINTFN(n,x) do { if (xhcidebug>(n)) printf x; } while (0) 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #define XHCI_DCI_SLOT 0 68 #define XHCI_DCI_EP_CONTROL 1 69 70 #define XHCI_ICI_INPUT_CONTROL 0 71 72 struct xhci_pipe { 73 struct usbd_pipe xp_pipe; 74 }; 75 76 #define XHCI_INTR_ENDPT 1 77 #define XHCI_COMMAND_RING_TRBS 256 78 #define XHCI_EVENT_RING_TRBS 256 79 #define XHCI_EVENT_RING_SEGMENTS 1 80 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 81 82 static usbd_status xhci_open(usbd_pipe_handle); 83 static int xhci_intr1(struct xhci_softc * const); 84 static void xhci_softintr(void *); 85 static void xhci_poll(struct usbd_bus *); 86 static usbd_status xhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 87 static void xhci_freem(struct usbd_bus *, usb_dma_t *); 88 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 89 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 90 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 91 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 92 struct usbd_port *); 93 94 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 95 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 96 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 97 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 98 99 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 100 101 static usbd_status xhci_do_command(struct xhci_softc * const, 102 struct xhci_trb * const, int); 103 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 104 int, int, int, int); 105 static usbd_status xhci_enable_slot(struct xhci_softc * const, 106 uint8_t * const); 107 static usbd_status xhci_address_device(struct xhci_softc * const, 108 uint64_t, uint8_t, bool); 109 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 110 struct xhci_slot * const, u_int); 111 static usbd_status xhci_ring_init(struct xhci_softc * const, 112 struct xhci_ring * const, size_t, size_t); 113 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 114 115 static void xhci_noop(usbd_pipe_handle); 116 117 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 118 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 119 static void xhci_root_ctrl_abort(usbd_xfer_handle); 120 static void xhci_root_ctrl_close(usbd_pipe_handle); 121 static void xhci_root_ctrl_done(usbd_xfer_handle); 122 123 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 124 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 125 static void xhci_root_intr_abort(usbd_xfer_handle); 126 static void xhci_root_intr_close(usbd_pipe_handle); 127 static void xhci_root_intr_done(usbd_xfer_handle); 128 129 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 130 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 131 static void xhci_device_ctrl_abort(usbd_xfer_handle); 132 static void xhci_device_ctrl_close(usbd_pipe_handle); 133 static void xhci_device_ctrl_done(usbd_xfer_handle); 134 135 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 136 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 137 static void xhci_device_intr_abort(usbd_xfer_handle); 138 static void xhci_device_intr_close(usbd_pipe_handle); 139 static void xhci_device_intr_done(usbd_xfer_handle); 140 141 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 142 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 143 static void xhci_device_bulk_abort(usbd_xfer_handle); 144 static void xhci_device_bulk_close(usbd_pipe_handle); 145 static void xhci_device_bulk_done(usbd_xfer_handle); 146 147 static void xhci_timeout(void *); 148 static void xhci_timeout_task(void *); 149 150 static const struct usbd_bus_methods xhci_bus_methods = { 151 .open_pipe = xhci_open, 152 .soft_intr = xhci_softintr, 153 .do_poll = xhci_poll, 154 .allocm = xhci_allocm, 155 .freem = xhci_freem, 156 .allocx = xhci_allocx, 157 .freex = xhci_freex, 158 .get_lock = xhci_get_lock, 159 .new_device = xhci_new_device, 160 }; 161 162 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 163 .transfer = xhci_root_ctrl_transfer, 164 .start = xhci_root_ctrl_start, 165 .abort = xhci_root_ctrl_abort, 166 .close = xhci_root_ctrl_close, 167 .cleartoggle = xhci_noop, 168 .done = xhci_root_ctrl_done, 169 }; 170 171 static const struct usbd_pipe_methods xhci_root_intr_methods = { 172 .transfer = xhci_root_intr_transfer, 173 .start = xhci_root_intr_start, 174 .abort = xhci_root_intr_abort, 175 .close = xhci_root_intr_close, 176 .cleartoggle = xhci_noop, 177 .done = xhci_root_intr_done, 178 }; 179 180 181 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 182 .transfer = xhci_device_ctrl_transfer, 183 .start = xhci_device_ctrl_start, 184 .abort = xhci_device_ctrl_abort, 185 .close = xhci_device_ctrl_close, 186 .cleartoggle = xhci_noop, 187 .done = xhci_device_ctrl_done, 188 }; 189 190 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 191 .cleartoggle = xhci_noop, 192 }; 193 194 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 195 .transfer = xhci_device_bulk_transfer, 196 .start = xhci_device_bulk_start, 197 .abort = xhci_device_bulk_abort, 198 .close = xhci_device_bulk_close, 199 .cleartoggle = xhci_noop, 200 .done = xhci_device_bulk_done, 201 }; 202 203 static const struct usbd_pipe_methods xhci_device_intr_methods = { 204 .transfer = xhci_device_intr_transfer, 205 .start = xhci_device_intr_start, 206 .abort = xhci_device_intr_abort, 207 .close = xhci_device_intr_close, 208 .cleartoggle = xhci_noop, 209 .done = xhci_device_intr_done, 210 }; 211 212 static inline uint32_t 213 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 214 { 215 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 216 } 217 218 static inline void 219 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 220 uint32_t value) 221 { 222 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 223 } 224 225 static inline uint32_t 226 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 227 { 228 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 229 } 230 231 static inline uint32_t 232 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 233 { 234 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 235 } 236 237 static inline void 238 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 239 uint32_t value) 240 { 241 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 242 } 243 244 static inline uint64_t 245 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 246 { 247 uint64_t value; 248 249 if (sc->sc_ac64) { 250 #ifdef XHCI_USE_BUS_SPACE_8 251 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 252 #else 253 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 254 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 255 offset + 4) << 32; 256 #endif 257 } else { 258 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 259 } 260 261 return value; 262 } 263 264 static inline void 265 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 266 uint64_t value) 267 { 268 if (sc->sc_ac64) { 269 #ifdef XHCI_USE_BUS_SPACE_8 270 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 271 #else 272 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 273 (value >> 0) & 0xffffffff); 274 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 275 (value >> 32) & 0xffffffff); 276 #endif 277 } else { 278 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 279 } 280 } 281 282 static inline uint32_t 283 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 286 } 287 288 static inline void 289 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 290 uint32_t value) 291 { 292 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 293 } 294 295 static inline uint64_t 296 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 297 { 298 uint64_t value; 299 300 if (sc->sc_ac64) { 301 #ifdef XHCI_USE_BUS_SPACE_8 302 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 303 #else 304 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 305 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 306 offset + 4) << 32; 307 #endif 308 } else { 309 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 310 } 311 312 return value; 313 } 314 315 static inline void 316 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 317 uint64_t value) 318 { 319 if (sc->sc_ac64) { 320 #ifdef XHCI_USE_BUS_SPACE_8 321 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 322 #else 323 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 324 (value >> 0) & 0xffffffff); 325 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 326 (value >> 32) & 0xffffffff); 327 #endif 328 } else { 329 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 330 } 331 } 332 333 static inline uint32_t 334 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 335 { 336 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 337 } 338 339 static inline void 340 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 341 uint32_t value) 342 { 343 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 344 } 345 346 /* --- */ 347 348 static inline uint8_t 349 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 350 { 351 u_int eptype; 352 353 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 354 case UE_CONTROL: 355 eptype = 0x0; 356 break; 357 case UE_ISOCHRONOUS: 358 eptype = 0x1; 359 break; 360 case UE_BULK: 361 eptype = 0x2; 362 break; 363 case UE_INTERRUPT: 364 eptype = 0x3; 365 break; 366 } 367 368 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 369 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 370 return eptype | 0x4; 371 else 372 return eptype; 373 } 374 375 static u_int 376 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 377 { 378 /* xHCI 1.0 section 4.5.1 */ 379 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 380 u_int in = 0; 381 382 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 383 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 384 in = 1; 385 386 return epaddr * 2 + in; 387 } 388 389 static inline u_int 390 xhci_dci_to_ici(const u_int i) 391 { 392 return i + 1; 393 } 394 395 static inline void * 396 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 397 const u_int dci) 398 { 399 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 400 } 401 402 static inline bus_addr_t 403 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 404 const u_int dci) 405 { 406 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 407 } 408 409 static inline void * 410 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 411 const u_int ici) 412 { 413 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 414 } 415 416 static inline bus_addr_t 417 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 418 const u_int ici) 419 { 420 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 421 } 422 423 static inline struct xhci_trb * 424 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 425 { 426 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 427 } 428 429 static inline bus_addr_t 430 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 431 { 432 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 433 } 434 435 static inline void 436 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 437 uint32_t control) 438 { 439 trb->trb_0 = parameter; 440 trb->trb_2 = status; 441 trb->trb_3 = control; 442 } 443 444 /* --- */ 445 446 void 447 xhci_childdet(device_t self, device_t child) 448 { 449 struct xhci_softc * const sc = device_private(self); 450 451 KASSERT(sc->sc_child == child); 452 if (child == sc->sc_child) 453 sc->sc_child = NULL; 454 } 455 456 int 457 xhci_detach(struct xhci_softc *sc, int flags) 458 { 459 int rv = 0; 460 461 if (sc->sc_child != NULL) 462 rv = config_detach(sc->sc_child, flags); 463 464 if (rv != 0) 465 return (rv); 466 467 /* XXX unconfigure/free slots */ 468 469 /* verify: */ 470 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 471 xhci_op_write_4(sc, XHCI_USBCMD, 0); 472 /* do we need to wait for stop? */ 473 474 xhci_op_write_8(sc, XHCI_CRCR, 0); 475 xhci_ring_free(sc, &sc->sc_cr); 476 cv_destroy(&sc->sc_command_cv); 477 478 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 479 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 480 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 481 xhci_ring_free(sc, &sc->sc_er); 482 483 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 484 485 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 486 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 487 488 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 489 490 mutex_destroy(&sc->sc_lock); 491 mutex_destroy(&sc->sc_intr_lock); 492 493 pool_cache_destroy(sc->sc_xferpool); 494 495 return rv; 496 } 497 498 int 499 xhci_activate(device_t self, enum devact act) 500 { 501 struct xhci_softc * const sc = device_private(self); 502 503 switch (act) { 504 case DVACT_DEACTIVATE: 505 sc->sc_dying = true; 506 return 0; 507 default: 508 return EOPNOTSUPP; 509 } 510 } 511 512 bool 513 xhci_suspend(device_t dv, const pmf_qual_t *qual) 514 { 515 return false; 516 } 517 518 bool 519 xhci_resume(device_t dv, const pmf_qual_t *qual) 520 { 521 return false; 522 } 523 524 bool 525 xhci_shutdown(device_t self, int flags) 526 { 527 return false; 528 } 529 530 531 static void 532 hexdump(const char *msg, const void *base, size_t len) 533 { 534 #if 0 535 size_t cnt; 536 const uint32_t *p; 537 extern paddr_t vtophys(vaddr_t); 538 539 p = base; 540 cnt = 0; 541 542 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 543 (void *)vtophys((vaddr_t)base)); 544 545 while (cnt < len) { 546 if (cnt % 16 == 0) 547 printf("%p: ", p); 548 else if (cnt % 8 == 0) 549 printf(" |"); 550 printf(" %08x", *p++); 551 cnt += 4; 552 if (cnt % 16 == 0) 553 printf("\n"); 554 } 555 #endif 556 } 557 558 559 usbd_status 560 xhci_init(struct xhci_softc *sc) 561 { 562 bus_size_t bsz; 563 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 564 uint32_t ecp, ecr; 565 uint32_t usbcmd, usbsts, pagesize, config; 566 int i; 567 uint16_t hciversion; 568 uint8_t caplength; 569 570 DPRINTF(("%s\n", __func__)); 571 572 sc->sc_bus.usbrev = USBREV_2_0; /* XXX Low/Full/High speeds for now */ 573 574 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 575 caplength = XHCI_CAP_CAPLENGTH(cap); 576 hciversion = XHCI_CAP_HCIVERSION(cap); 577 578 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 579 aprint_normal_dev(sc->sc_dev, 580 "xHCI version %x.%x not known to be supported\n", 581 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 582 } else { 583 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 584 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 585 } 586 587 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 588 &sc->sc_cbh) != 0) { 589 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 590 return USBD_NOMEM; 591 } 592 593 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 594 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 595 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 596 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 597 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 598 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 599 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 600 601 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 602 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 603 device_printf(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 604 sc->sc_ctxsz); 605 606 device_printf(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 607 ecp = XHCI_HCC_XECP(hcc) * 4; 608 while (ecp != 0) { 609 ecr = xhci_read_4(sc, ecp); 610 device_printf(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 611 switch (XHCI_XECP_ID(ecr)) { 612 case XHCI_ID_PROTOCOLS: { 613 uint32_t w0, w4, w8; 614 uint16_t w2; 615 w0 = xhci_read_4(sc, ecp + 0); 616 w2 = (w0 >> 16) & 0xffff; 617 w4 = xhci_read_4(sc, ecp + 4); 618 w8 = xhci_read_4(sc, ecp + 8); 619 device_printf(sc->sc_dev, "SP: %08x %08x %08x\n", 620 w0, w4, w8); 621 if (w4 == 0x20425355 && w2 == 0x0300) { 622 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 623 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 624 } 625 if (w4 == 0x20425355 && w2 == 0x0200) { 626 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 627 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 628 } 629 break; 630 } 631 default: 632 break; 633 } 634 ecr = xhci_read_4(sc, ecp); 635 if (XHCI_XECP_NEXT(ecr) == 0) { 636 ecp = 0; 637 } else { 638 ecp += XHCI_XECP_NEXT(ecr) * 4; 639 } 640 } 641 642 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 643 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 644 &sc->sc_obh) != 0) { 645 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 646 return USBD_NOMEM; 647 } 648 649 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 650 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 651 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 652 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 653 return USBD_NOMEM; 654 } 655 656 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 657 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 658 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 659 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 660 return USBD_NOMEM; 661 } 662 663 for (i = 0; i < 100; i++) { 664 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 665 if ((usbsts & XHCI_STS_CNR) == 0) 666 break; 667 usb_delay_ms(&sc->sc_bus, 1); 668 } 669 if (i >= 100) 670 return USBD_IOERROR; 671 672 usbcmd = 0; 673 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 674 usb_delay_ms(&sc->sc_bus, 1); 675 676 usbcmd = XHCI_CMD_HCRST; 677 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 678 for (i = 0; i < 100; i++) { 679 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 680 if ((usbcmd & XHCI_CMD_HCRST) == 0) 681 break; 682 usb_delay_ms(&sc->sc_bus, 1); 683 } 684 if (i >= 100) 685 return USBD_IOERROR; 686 687 for (i = 0; i < 100; i++) { 688 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 689 if ((usbsts & XHCI_STS_CNR) == 0) 690 break; 691 usb_delay_ms(&sc->sc_bus, 1); 692 } 693 if (i >= 100) 694 return USBD_IOERROR; 695 696 device_printf(sc->sc_dev, "maxspbuf %d\n", XHCI_HCS2_MAXSPBUF(hcs2)); 697 if (XHCI_HCS2_MAXSPBUF(hcs2) != 0) { 698 /* XXX */ 699 aprint_error_dev(sc->sc_dev, 700 "TODO implement scratchpad allocation\n"); 701 return USBD_INVAL; 702 } 703 704 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 705 device_printf(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 706 pagesize = ffs(pagesize); 707 if (pagesize == 0) 708 return USBD_IOERROR; 709 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 710 device_printf(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 711 device_printf(sc->sc_dev, "sc_maxslots 0x%08x\n", 712 (uint32_t)sc->sc_maxslots); 713 714 config = xhci_op_read_4(sc, XHCI_CONFIG); 715 config &= ~0xFF; 716 config |= sc->sc_maxslots & 0xFF; 717 xhci_op_write_4(sc, XHCI_CONFIG, config); 718 719 usbd_status err; 720 721 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 722 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 723 if (err) { 724 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 725 return err; 726 } 727 728 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 729 XHCI_EVENT_RING_SEGMENTS_ALIGN); 730 if (err) { 731 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 732 return err; 733 } 734 735 { 736 usb_dma_t *dma; 737 size_t size; 738 size_t align; 739 740 dma = &sc->sc_eventst_dma; 741 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 742 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 743 KASSERT(size <= (512 * 1024)); 744 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 745 err = usb_allocmem(&sc->sc_bus, size, align, dma); 746 memset(KERNADDR(dma, 0), 0, size); 747 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 748 device_printf(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 749 usbd_errstr(err), 750 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 751 KERNADDR(&sc->sc_eventst_dma, 0), 752 sc->sc_eventst_dma.block->size); 753 754 dma = &sc->sc_dcbaa_dma; 755 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 756 KASSERT(size <= 2048); 757 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 758 err = usb_allocmem(&sc->sc_bus, size, align, dma); 759 memset(KERNADDR(dma, 0), 0, size); 760 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 761 device_printf(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 762 usbd_errstr(err), 763 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 764 KERNADDR(&sc->sc_dcbaa_dma, 0), 765 sc->sc_dcbaa_dma.block->size); 766 } 767 768 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 769 KM_SLEEP); 770 771 cv_init(&sc->sc_command_cv, "xhcicmd"); 772 773 struct xhci_erste *erst; 774 erst = KERNADDR(&sc->sc_eventst_dma, 0); 775 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 776 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 777 erst[0].erste_3 = htole32(0); 778 usb_syncmem(&sc->sc_eventst_dma, 0, 779 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 780 781 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 782 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 783 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 784 XHCI_ERDP_LO_BUSY); 785 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 786 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 787 sc->sc_cr.xr_cs); 788 789 #if 0 790 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 791 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 792 #endif 793 794 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 795 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 796 797 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 798 device_printf(sc->sc_dev, "USBCMD %08"PRIx32"\n", 799 xhci_op_read_4(sc, XHCI_USBCMD)); 800 801 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 802 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 803 cv_init(&sc->sc_softwake_cv, "xhciab"); 804 805 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 806 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 807 808 /* Set up the bus struct. */ 809 sc->sc_bus.methods = &xhci_bus_methods; 810 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 811 812 return USBD_NORMAL_COMPLETION; 813 } 814 815 int 816 xhci_intr(void *v) 817 { 818 struct xhci_softc * const sc = v; 819 820 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 821 return 0; 822 823 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 824 825 /* If we get an interrupt while polling, then just ignore it. */ 826 if (sc->sc_bus.use_polling) { 827 #ifdef DIAGNOSTIC 828 DPRINTFN(16, ("xhci_intr: ignored interrupt while polling\n")); 829 #endif 830 return 0; 831 } 832 833 return xhci_intr1(sc); 834 } 835 836 int 837 xhci_intr1(struct xhci_softc * const sc) 838 { 839 uint32_t usbsts; 840 uint32_t iman; 841 842 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 843 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 844 #if 0 845 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 846 return 0; 847 } 848 #endif 849 xhci_op_write_4(sc, XHCI_USBSTS, 850 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 851 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 852 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 853 854 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 855 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 856 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 857 return 0; 858 } 859 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 860 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 861 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 862 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 863 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 864 865 sc->sc_bus.no_intrs++; 866 usb_schedsoftintr(&sc->sc_bus); 867 868 return 1; 869 } 870 871 static usbd_status 872 xhci_configure_endpoint(usbd_pipe_handle pipe) 873 { 874 struct xhci_softc * const sc = pipe->device->bus->hci_private; 875 struct xhci_slot * const xs = pipe->device->hci_private; 876 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 877 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 878 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 879 struct xhci_trb trb; 880 usbd_status err; 881 uint32_t *cp; 882 883 device_printf(sc->sc_dev, "%s dci %u (0x%x)\n", __func__, dci, 884 pipe->endpoint->edesc->bEndpointAddress); 885 886 /* XXX ensure input context is available? */ 887 888 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 889 890 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 891 cp[0] = htole32(0); 892 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 893 894 /* set up input slot context */ 895 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 896 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 897 cp[1] = htole32(0); 898 cp[2] = htole32(0); 899 cp[3] = htole32(0); 900 901 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 902 if (xfertype == UE_INTERRUPT) { 903 cp[0] = htole32( 904 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 905 ); 906 cp[1] = htole32( 907 XHCI_EPCTX_1_CERR_SET(3) | 908 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 909 XHCI_EPCTX_1_MAXB_SET(0) | 910 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 911 ); 912 cp[4] = htole32( 913 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 914 ); 915 } else { 916 cp[0] = htole32(0); 917 cp[1] = htole32( 918 XHCI_EPCTX_1_CERR_SET(3) | 919 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 920 XHCI_EPCTX_1_MAXB_SET(0) | 921 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 922 ); 923 } 924 *(uint64_t *)(&cp[2]) = htole64( 925 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 926 XHCI_EPCTX_2_DCS_SET(1)); 927 928 /* sync input contexts before they are read from memory */ 929 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 930 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 931 sc->sc_ctxsz * 1); 932 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 933 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 934 935 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 936 trb.trb_2 = 0; 937 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 938 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 939 940 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 941 942 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 943 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 944 sc->sc_ctxsz * 1); 945 946 return err; 947 } 948 949 static usbd_status 950 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 951 { 952 return USBD_NORMAL_COMPLETION; 953 } 954 955 static usbd_status 956 xhci_reset_endpoint(usbd_pipe_handle pipe) 957 { 958 struct xhci_softc * const sc = pipe->device->bus->hci_private; 959 struct xhci_slot * const xs = pipe->device->hci_private; 960 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 961 struct xhci_trb trb; 962 usbd_status err; 963 964 device_printf(sc->sc_dev, "%s\n", __func__); 965 966 trb.trb_0 = 0; 967 trb.trb_2 = 0; 968 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 969 XHCI_TRB_3_EP_SET(dci) | 970 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 971 972 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 973 974 return err; 975 } 976 977 #if 0 978 static usbd_status 979 xhci_stop_endpoint(usbd_pipe_handle pipe) 980 { 981 struct xhci_softc * const sc = pipe->device->bus->hci_private; 982 struct xhci_slot * const xs = pipe->device->hci_private; 983 struct xhci_trb trb; 984 usbd_status err; 985 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 986 987 device_printf(sc->sc_dev, "%s\n", __func__); 988 989 trb.trb_0 = 0; 990 trb.trb_2 = 0; 991 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 992 XHCI_TRB_3_EP_SET(dci) | 993 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 994 995 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 996 997 return err; 998 } 999 #endif 1000 1001 static usbd_status 1002 xhci_set_dequeue(usbd_pipe_handle pipe) 1003 { 1004 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1005 struct xhci_slot * const xs = pipe->device->hci_private; 1006 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1007 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1008 struct xhci_trb trb; 1009 usbd_status err; 1010 1011 device_printf(sc->sc_dev, "%s\n", __func__); 1012 1013 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1014 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1015 BUS_DMASYNC_PREWRITE); 1016 1017 xr->xr_ep = 0; 1018 xr->xr_cs = 1; 1019 1020 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1021 trb.trb_2 = 0; 1022 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1023 XHCI_TRB_3_EP_SET(dci) | 1024 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1025 1026 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1027 1028 return err; 1029 } 1030 1031 static usbd_status 1032 xhci_open(usbd_pipe_handle pipe) 1033 { 1034 usbd_device_handle const dev = pipe->device; 1035 struct xhci_softc * const sc = dev->bus->hci_private; 1036 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 1037 const int8_t addr = dev->address; 1038 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1039 1040 DPRINTF(("%s\n", __func__)); 1041 DPRINTF(("addr %d\n", addr)); 1042 device_printf(sc->sc_dev, "%s addr %d depth %d port %d speed %d\n", 1043 __func__, addr, dev->depth, dev->powersrc->portno, dev->speed); 1044 1045 if (sc->sc_dying) 1046 return USBD_IOERROR; 1047 1048 /* Root Hub */ 1049 if (dev->depth == 0 && dev->powersrc->portno == 0 && 1050 dev->speed != USB_SPEED_SUPER) { 1051 switch (ed->bEndpointAddress) { 1052 case USB_CONTROL_ENDPOINT: 1053 pipe->methods = &xhci_root_ctrl_methods; 1054 break; 1055 case UE_DIR_IN | XHCI_INTR_ENDPT: 1056 pipe->methods = &xhci_root_intr_methods; 1057 break; 1058 default: 1059 pipe->methods = NULL; 1060 DPRINTF(("xhci_open: bad bEndpointAddress 0x%02x\n", 1061 ed->bEndpointAddress)); 1062 return USBD_INVAL; 1063 } 1064 return USBD_NORMAL_COMPLETION; 1065 } 1066 1067 switch (xfertype) { 1068 case UE_CONTROL: 1069 pipe->methods = &xhci_device_ctrl_methods; 1070 break; 1071 case UE_ISOCHRONOUS: 1072 pipe->methods = &xhci_device_isoc_methods; 1073 return USBD_INVAL; 1074 break; 1075 case UE_BULK: 1076 pipe->methods = &xhci_device_bulk_methods; 1077 break; 1078 case UE_INTERRUPT: 1079 pipe->methods = &xhci_device_intr_methods; 1080 break; 1081 default: 1082 return USBD_IOERROR; 1083 break; 1084 } 1085 1086 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1087 xhci_configure_endpoint(pipe); 1088 1089 return USBD_NORMAL_COMPLETION; 1090 } 1091 1092 static void 1093 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1094 { 1095 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1096 uint8_t *p; 1097 1098 device_printf(sc->sc_dev, "port %u status change\n", port); 1099 1100 if (xfer == NULL) 1101 return; 1102 1103 if (!(port >= sc->sc_hs_port_start && 1104 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1105 return; 1106 1107 port -= sc->sc_hs_port_start; 1108 port += 1; 1109 device_printf(sc->sc_dev, "hs port %u status change\n", port); 1110 1111 p = KERNADDR(&xfer->dmabuf, 0); 1112 memset(p, 0, xfer->length); 1113 p[port/NBBY] |= 1 << (port%NBBY); 1114 xfer->actlen = xfer->length; 1115 xfer->status = USBD_NORMAL_COMPLETION; 1116 usb_transfer_complete(xfer); 1117 } 1118 1119 static void 1120 xhci_handle_event(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1121 { 1122 uint64_t trb_0; 1123 uint32_t trb_2, trb_3; 1124 1125 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1126 1127 trb_0 = le64toh(trb->trb_0); 1128 trb_2 = le32toh(trb->trb_2); 1129 trb_3 = le32toh(trb->trb_3); 1130 1131 #if 0 1132 device_printf(sc->sc_dev, 1133 "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", trb, 1134 trb_0, trb_2, trb_3); 1135 #endif 1136 1137 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1138 case XHCI_TRB_EVENT_TRANSFER: { 1139 u_int slot, dci; 1140 struct xhci_slot *xs; 1141 struct xhci_ring *xr; 1142 struct xhci_xfer *xx; 1143 usbd_xfer_handle xfer; 1144 usbd_status err; 1145 1146 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1147 dci = XHCI_TRB_3_EP_GET(trb_3); 1148 1149 xs = &sc->sc_slots[slot]; 1150 xr = &xs->xs_ep[dci].xe_tr; 1151 1152 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1153 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1154 sizeof(struct xhci_trb)]; 1155 } else { 1156 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1157 } 1158 xfer = &xx->xx_xfer; 1159 #if 0 1160 device_printf(sc->sc_dev, "%s xfer %p\n", __func__, xfer); 1161 #endif 1162 1163 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1164 #if 0 1165 device_printf(sc->sc_dev, "transfer event data: " 1166 "0x%016"PRIx64" 0x%08"PRIx32" %02x\n", 1167 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1168 XHCI_TRB_2_ERROR_GET(trb_2)); 1169 #endif 1170 if ((trb_0 & 0x3) == 0x3) { 1171 xfer->actlen = XHCI_TRB_2_REM_GET(trb_2); 1172 } 1173 } 1174 1175 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1176 XHCI_TRB_ERROR_SUCCESS) { 1177 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1178 err = USBD_NORMAL_COMPLETION; 1179 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1180 XHCI_TRB_ERROR_SHORT_PKT) { 1181 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1182 err = USBD_NORMAL_COMPLETION; 1183 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1184 XHCI_TRB_ERROR_STALL) { 1185 err = USBD_STALLED; 1186 xr->is_halted = true; 1187 } else { 1188 err = USBD_IOERROR; 1189 } 1190 xfer->status = err; 1191 1192 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1193 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1194 if ((trb_0 & 0x3) == 0x0) { 1195 usb_transfer_complete(xfer); 1196 } 1197 } else { 1198 usb_transfer_complete(xfer); 1199 } 1200 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1201 1202 } 1203 break; 1204 case XHCI_TRB_EVENT_CMD_COMPLETE: 1205 if (trb_0 == sc->sc_command_addr) { 1206 sc->sc_result_trb.trb_0 = trb_0; 1207 sc->sc_result_trb.trb_2 = trb_2; 1208 sc->sc_result_trb.trb_3 = trb_3; 1209 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1210 XHCI_TRB_ERROR_SUCCESS) { 1211 device_printf(sc->sc_dev, "command completion " 1212 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1213 "0x%08"PRIx32"\n", trb_0, trb_2, trb_3); 1214 } 1215 cv_signal(&sc->sc_command_cv); 1216 } else { 1217 device_printf(sc->sc_dev, "event: %p 0x%016"PRIx64" " 1218 "0x%08"PRIx32" 0x%08"PRIx32"\n", trb, trb_0, 1219 trb_2, trb_3); 1220 } 1221 break; 1222 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1223 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1224 break; 1225 default: 1226 break; 1227 } 1228 } 1229 1230 static void 1231 xhci_softintr(void *v) 1232 { 1233 struct usbd_bus * const bus = v; 1234 struct xhci_softc * const sc = bus->hci_private; 1235 struct xhci_ring * const er = &sc->sc_er; 1236 struct xhci_trb *trb; 1237 int i, j, k; 1238 1239 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1240 1241 i = er->xr_ep; 1242 j = er->xr_cs; 1243 1244 while (1) { 1245 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1246 BUS_DMASYNC_POSTREAD); 1247 trb = &er->xr_trb[i]; 1248 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1249 1250 if (j != k) 1251 break; 1252 1253 xhci_handle_event(sc, trb); 1254 1255 i++; 1256 if (i == XHCI_EVENT_RING_TRBS) { 1257 i = 0; 1258 j ^= 1; 1259 } 1260 } 1261 1262 er->xr_ep = i; 1263 er->xr_cs = j; 1264 1265 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1266 XHCI_ERDP_LO_BUSY); 1267 1268 DPRINTF(("%s: %s ends\n", __func__, device_xname(sc->sc_dev))); 1269 1270 return; 1271 } 1272 1273 static void 1274 xhci_poll(struct usbd_bus *bus) 1275 { 1276 struct xhci_softc * const sc = bus->hci_private; 1277 1278 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1279 1280 xhci_intr1(sc); 1281 1282 return; 1283 } 1284 1285 static usbd_status 1286 xhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1287 { 1288 struct xhci_softc * const sc = bus->hci_private; 1289 usbd_status err; 1290 1291 DPRINTF(("%s\n", __func__)); 1292 1293 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, 0); 1294 #if 0 1295 if (err == USBD_NOMEM) 1296 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1297 #endif 1298 #ifdef XHCI_DEBUG 1299 if (err) 1300 device_printf(sc->sc_dev, "xhci_allocm: usb_allocmem()=%d\n", 1301 err); 1302 #endif 1303 1304 return err; 1305 } 1306 1307 static void 1308 xhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1309 { 1310 struct xhci_softc * const sc = bus->hci_private; 1311 1312 // DPRINTF(("%s\n", __func__)); 1313 1314 #if 0 1315 if (dma->block->flags & USB_DMA_RESERVE) { 1316 usb_reserve_freem(&sc->sc_dma_reserve, dma); 1317 return; 1318 } 1319 #endif 1320 usb_freemem(&sc->sc_bus, dma); 1321 } 1322 1323 static usbd_xfer_handle 1324 xhci_allocx(struct usbd_bus *bus) 1325 { 1326 struct xhci_softc * const sc = bus->hci_private; 1327 usbd_xfer_handle xfer; 1328 1329 // DPRINTF(("%s\n", __func__)); 1330 1331 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1332 if (xfer != NULL) { 1333 #ifdef DIAGNOSTIC 1334 memset(xfer, 0, sizeof(struct xhci_xfer)); 1335 xfer->busy_free = XFER_BUSY; 1336 #endif 1337 } 1338 1339 return xfer; 1340 } 1341 1342 static void 1343 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1344 { 1345 struct xhci_softc * const sc = bus->hci_private; 1346 1347 // DPRINTF(("%s\n", __func__)); 1348 1349 #ifdef DIAGNOSTIC 1350 if (xfer->busy_free != XFER_BUSY) { 1351 device_printf(sc->sc_dev, "xhci_freex: xfer=%p " 1352 "not busy, 0x%08x\n", xfer, xfer->busy_free); 1353 } 1354 xfer->busy_free = XFER_FREE; 1355 #endif 1356 pool_cache_put(sc->sc_xferpool, xfer); 1357 } 1358 1359 static void 1360 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1361 { 1362 struct xhci_softc * const sc = bus->hci_private; 1363 1364 *lock = &sc->sc_lock; 1365 } 1366 1367 extern u_int32_t usb_cookie_no; 1368 1369 static usbd_status 1370 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1371 int speed, int port, struct usbd_port *up) 1372 { 1373 struct xhci_softc * const sc = bus->hci_private; 1374 usbd_device_handle dev; 1375 usbd_status err; 1376 usb_device_descriptor_t *dd; 1377 struct usbd_device *hub; 1378 struct usbd_device *adev; 1379 int rhport = 0; 1380 struct xhci_slot *xs; 1381 uint32_t *cp; 1382 uint8_t slot; 1383 uint8_t addr; 1384 1385 dev = malloc(sizeof *dev, M_USB, M_NOWAIT|M_ZERO); 1386 if (dev == NULL) 1387 return USBD_NOMEM; 1388 1389 dev->bus = bus; 1390 1391 /* Set up default endpoint handle. */ 1392 dev->def_ep.edesc = &dev->def_ep_desc; 1393 1394 /* Set up default endpoint descriptor. */ 1395 dev->def_ep_desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1396 dev->def_ep_desc.bDescriptorType = UDESC_ENDPOINT; 1397 dev->def_ep_desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1398 dev->def_ep_desc.bmAttributes = UE_CONTROL; 1399 /* XXX */ 1400 USETW(dev->def_ep_desc.wMaxPacketSize, 64); 1401 dev->def_ep_desc.bInterval = 0; 1402 1403 /* doesn't matter, just don't let it uninitialized */ 1404 dev->def_ep.datatoggle = 0; 1405 1406 device_printf(sc->sc_dev, "%s up %p portno %d\n", __func__, up, 1407 up->portno); 1408 1409 dev->quirks = &usbd_no_quirk; 1410 dev->address = 0; 1411 dev->ddesc.bMaxPacketSize = 0; 1412 dev->depth = depth; 1413 dev->powersrc = up; 1414 dev->myhub = up->parent; 1415 1416 up->device = dev; 1417 1418 /* Locate root hub port */ 1419 for (adev = dev, hub = dev; 1420 hub != NULL; 1421 adev = hub, hub = hub->myhub) { 1422 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1423 } 1424 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1425 1426 if (hub != NULL) { 1427 for (int p = 0; p < hub->hub->hubdesc.bNbrPorts; p++) { 1428 if (hub->hub->ports[p].device == adev) { 1429 rhport = p; 1430 } 1431 } 1432 } else { 1433 rhport = port; 1434 } 1435 if (speed == USB_SPEED_SUPER) { 1436 rhport += sc->sc_ss_port_start - 1; 1437 } else { 1438 rhport += sc->sc_hs_port_start - 1; 1439 } 1440 device_printf(sc->sc_dev, "%s rhport %d\n", __func__, rhport); 1441 1442 dev->speed = speed; 1443 dev->langid = USBD_NOLANG; 1444 dev->cookie.cookie = ++usb_cookie_no; 1445 1446 /* Establish the default pipe. */ 1447 err = usbd_setup_pipe(dev, 0, &dev->def_ep, USBD_DEFAULT_INTERVAL, 1448 &dev->default_pipe); 1449 if (err) { 1450 usbd_remove_device(dev, up); 1451 return (err); 1452 } 1453 1454 dd = &dev->ddesc; 1455 1456 if ((depth == 0) && (port == 0)) { 1457 KASSERT(bus->devices[dev->address] == NULL); 1458 bus->devices[dev->address] = dev; 1459 err = usbd_get_initial_ddesc(dev, dd); 1460 if (err) 1461 return err; 1462 err = usbd_reload_device_desc(dev); 1463 if (err) 1464 return err; 1465 } else { 1466 err = xhci_enable_slot(sc, &slot); 1467 if (err) 1468 return err; 1469 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1470 if (err) 1471 return err; 1472 xs = &sc->sc_slots[slot]; 1473 dev->hci_private = xs; 1474 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1475 //hexdump("slot context", cp, sc->sc_ctxsz); 1476 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1477 device_printf(sc->sc_dev, "%s device address %u\n", 1478 __func__, addr); 1479 /* XXX ensure we know when the hardware does something 1480 we can't yet cope with */ 1481 KASSERT(addr >= 1 && addr <= 127); 1482 dev->address = addr; 1483 /* XXX dev->address not necessarily unique on bus */ 1484 KASSERT(bus->devices[dev->address] == NULL); 1485 bus->devices[dev->address] = dev; 1486 1487 err = usbd_get_initial_ddesc(dev, dd); 1488 if (err) 1489 return err; 1490 USETW(dev->def_ep_desc.wMaxPacketSize, dd->bMaxPacketSize); 1491 device_printf(sc->sc_dev, "%s bMaxPacketSize %u\n", __func__, dd->bMaxPacketSize); 1492 xhci_update_ep0_mps(sc, xs, dd->bMaxPacketSize); 1493 err = usbd_reload_device_desc(dev); 1494 if (err) 1495 return err; 1496 1497 usbd_kill_pipe(dev->default_pipe); 1498 err = usbd_setup_pipe(dev, 0, &dev->def_ep, 1499 USBD_DEFAULT_INTERVAL, &dev->default_pipe); 1500 } 1501 1502 DPRINTF(("usbd_new_device: adding unit addr=%d, rev=%02x, class=%d, " 1503 "subclass=%d, protocol=%d, maxpacket=%d, len=%d, noconf=%d, " 1504 "speed=%d\n", dev->address,UGETW(dd->bcdUSB), 1505 dd->bDeviceClass, dd->bDeviceSubClass, dd->bDeviceProtocol, 1506 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1507 dev->speed)); 1508 1509 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1510 1511 if ((depth == 0) && (port == 0)) { 1512 usbd_attach_roothub(parent, dev); 1513 device_printf(sc->sc_dev, "root_hub %p\n", bus->root_hub); 1514 return USBD_NORMAL_COMPLETION; 1515 } 1516 1517 1518 err = usbd_probe_and_attach(parent, dev, port, dev->address); 1519 if (err) { 1520 usbd_remove_device(dev, up); 1521 return (err); 1522 } 1523 1524 return USBD_NORMAL_COMPLETION; 1525 } 1526 1527 static usbd_status 1528 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1529 size_t ntrb, size_t align) 1530 { 1531 usbd_status err; 1532 size_t size = ntrb * XHCI_TRB_SIZE; 1533 1534 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1535 if (err) 1536 return err; 1537 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1538 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1539 xr->xr_trb = xhci_ring_trbv(xr, 0); 1540 xr->xr_ntrb = ntrb; 1541 xr->xr_ep = 0; 1542 xr->xr_cs = 1; 1543 memset(xr->xr_trb, 0, size); 1544 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1545 xr->is_halted = false; 1546 1547 return USBD_NORMAL_COMPLETION; 1548 } 1549 1550 static void 1551 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1552 { 1553 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1554 mutex_destroy(&xr->xr_lock); 1555 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1556 } 1557 1558 static void 1559 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1560 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1561 { 1562 size_t i; 1563 u_int ri; 1564 u_int cs; 1565 uint64_t parameter; 1566 uint32_t status; 1567 uint32_t control; 1568 1569 for (i = 0; i < ntrbs; i++) { 1570 #if 0 1571 device_printf(sc->sc_dev, "%s %p %p %zu " 1572 "%016"PRIx64" %08"PRIx32" %08"PRIx32"\n", __func__, xr, 1573 trbs, i, trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3); 1574 #endif 1575 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1576 XHCI_TRB_TYPE_LINK); 1577 } 1578 1579 #if 0 1580 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1581 xr, xr->xr_ep, xr->xr_cs); 1582 #endif 1583 1584 ri = xr->xr_ep; 1585 cs = xr->xr_cs; 1586 1587 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1588 parameter = xhci_ring_trbp(xr, 0); 1589 status = 0; 1590 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1591 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1592 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1593 htole32(status), htole32(control)); 1594 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1595 BUS_DMASYNC_PREWRITE); 1596 xr->xr_cookies[ri] = NULL; 1597 xr->xr_ep = 0; 1598 xr->xr_cs ^= 1; 1599 ri = xr->xr_ep; 1600 cs = xr->xr_cs; 1601 } 1602 1603 ri++; 1604 1605 for (i = 1; i < ntrbs; i++) { 1606 parameter = trbs[i].trb_0; 1607 status = trbs[i].trb_2; 1608 control = trbs[i].trb_3; 1609 1610 if (cs) { 1611 control |= XHCI_TRB_3_CYCLE_BIT; 1612 } else { 1613 control &= ~XHCI_TRB_3_CYCLE_BIT; 1614 } 1615 1616 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1617 htole32(status), htole32(control)); 1618 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1619 BUS_DMASYNC_PREWRITE); 1620 xr->xr_cookies[ri] = cookie; 1621 ri++; 1622 } 1623 1624 i = 0; 1625 { 1626 parameter = trbs[i].trb_0; 1627 status = trbs[i].trb_2; 1628 control = trbs[i].trb_3; 1629 1630 if (xr->xr_cs) { 1631 control |= XHCI_TRB_3_CYCLE_BIT; 1632 } else { 1633 control &= ~XHCI_TRB_3_CYCLE_BIT; 1634 } 1635 1636 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1637 htole32(status), htole32(control)); 1638 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1639 BUS_DMASYNC_PREWRITE); 1640 xr->xr_cookies[xr->xr_ep] = cookie; 1641 } 1642 1643 xr->xr_ep = ri; 1644 xr->xr_cs = cs; 1645 1646 #if 0 1647 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1648 xr, xr->xr_ep, xr->xr_cs); 1649 #endif 1650 } 1651 1652 static usbd_status 1653 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1654 int timeout) 1655 { 1656 struct xhci_ring * const cr = &sc->sc_cr; 1657 usbd_status err; 1658 1659 device_printf(sc->sc_dev, "%s input: " 1660 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1661 trb->trb_0, trb->trb_2, trb->trb_3); 1662 1663 mutex_enter(&sc->sc_lock); 1664 1665 KASSERT(sc->sc_command_addr == 0); 1666 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1667 1668 mutex_enter(&cr->xr_lock); 1669 xhci_ring_put(sc, cr, NULL, trb, 1); 1670 mutex_exit(&cr->xr_lock); 1671 1672 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1673 1674 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1675 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1676 err = USBD_TIMEOUT; 1677 goto timedout; 1678 } 1679 1680 trb->trb_0 = sc->sc_result_trb.trb_0; 1681 trb->trb_2 = sc->sc_result_trb.trb_2; 1682 trb->trb_3 = sc->sc_result_trb.trb_3; 1683 1684 device_printf(sc->sc_dev, "%s output: " 1685 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1686 trb->trb_0, trb->trb_2, trb->trb_3); 1687 1688 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1689 case XHCI_TRB_ERROR_SUCCESS: 1690 err = USBD_NORMAL_COMPLETION; 1691 break; 1692 default: 1693 case 192 ... 223: 1694 err = USBD_IOERROR; 1695 break; 1696 case 224 ... 255: 1697 err = USBD_NORMAL_COMPLETION; 1698 break; 1699 } 1700 1701 timedout: 1702 sc->sc_command_addr = 0; 1703 mutex_exit(&sc->sc_lock); 1704 return err; 1705 } 1706 1707 static usbd_status 1708 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1709 { 1710 struct xhci_trb trb; 1711 usbd_status err; 1712 1713 trb.trb_0 = 0; 1714 trb.trb_2 = 0; 1715 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1716 1717 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1718 if (err != USBD_NORMAL_COMPLETION) { 1719 return err; 1720 } 1721 1722 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1723 1724 return err; 1725 } 1726 1727 static usbd_status 1728 xhci_address_device(struct xhci_softc * const sc, 1729 uint64_t icp, uint8_t slot_id, bool bsr) 1730 { 1731 struct xhci_trb trb; 1732 usbd_status err; 1733 1734 trb.trb_0 = icp; 1735 trb.trb_2 = 0; 1736 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1737 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1738 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1739 1740 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1741 return err; 1742 } 1743 1744 static usbd_status 1745 xhci_update_ep0_mps(struct xhci_softc * const sc, 1746 struct xhci_slot * const xs, u_int mps) 1747 { 1748 struct xhci_trb trb; 1749 usbd_status err; 1750 uint32_t * cp; 1751 1752 device_printf(sc->sc_dev, "%s\n", __func__); 1753 1754 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1755 cp[0] = htole32(0); 1756 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1757 1758 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1759 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1760 1761 /* sync input contexts before they are read from memory */ 1762 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1763 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1764 sc->sc_ctxsz * 4); 1765 1766 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1767 trb.trb_2 = 0; 1768 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1769 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1770 1771 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1772 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1773 return err; 1774 } 1775 1776 static void 1777 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1778 { 1779 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1780 1781 device_printf(sc->sc_dev, "dcbaa %p dc %016"PRIx64" slot %d\n", 1782 &dcbaa[si], dcba, si); 1783 1784 dcbaa[si] = dcba; 1785 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1786 BUS_DMASYNC_PREWRITE); 1787 } 1788 1789 static usbd_status 1790 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1791 int speed, int port, int rhport) 1792 { 1793 struct xhci_slot *xs; 1794 usbd_status err; 1795 u_int dci; 1796 uint32_t *cp; 1797 uint32_t mps; 1798 uint32_t xspeed; 1799 1800 switch (speed) { 1801 case USB_SPEED_LOW: 1802 xspeed = 2; 1803 mps = USB_MAX_IPACKET; 1804 break; 1805 case USB_SPEED_FULL: 1806 xspeed = 1; 1807 mps = 64; 1808 break; 1809 case USB_SPEED_HIGH: 1810 xspeed = 3; 1811 mps = USB_2_MAX_CTRL_PACKET; 1812 break; 1813 case USB_SPEED_SUPER: 1814 xspeed = 4; 1815 mps = USB_3_MAX_CTRL_PACKET; 1816 break; 1817 } 1818 1819 xs = &sc->sc_slots[slot]; 1820 xs->xs_idx = slot; 1821 1822 /* allocate contexts */ 1823 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1824 &xs->xs_dc_dma); 1825 if (err) 1826 return err; 1827 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1828 1829 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1830 &xs->xs_ic_dma); 1831 if (err) 1832 return err; 1833 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1834 1835 for (dci = 0; dci < 32; dci++) { 1836 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1837 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1838 if (dci == XHCI_DCI_SLOT) 1839 continue; 1840 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1841 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1842 if (err) { 1843 device_printf(sc->sc_dev, "ring init failure\n"); 1844 return err; 1845 } 1846 } 1847 1848 /* set up initial input control context */ 1849 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1850 cp[0] = htole32(0); 1851 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1852 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1853 1854 /* set up input slot context */ 1855 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1856 cp[0] = htole32( 1857 XHCI_SCTX_0_CTX_NUM_SET(1) | 1858 XHCI_SCTX_0_SPEED_SET(xspeed) 1859 ); 1860 cp[1] = htole32( 1861 XHCI_SCTX_1_RH_PORT_SET(rhport) 1862 ); 1863 cp[2] = htole32( 1864 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1865 ); 1866 cp[3] = htole32(0); 1867 1868 /* set up input EP0 context */ 1869 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1870 cp[0] = htole32(0); 1871 cp[1] = htole32( 1872 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1873 XHCI_EPCTX_1_EPTYPE_SET(4) | 1874 XHCI_EPCTX_1_CERR_SET(3) 1875 ); 1876 /* can't use xhci_ep_get_dci() yet? */ 1877 *(uint64_t *)(&cp[2]) = htole64( 1878 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1879 XHCI_EPCTX_2_DCS_SET(1)); 1880 cp[4] = htole32( 1881 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1882 ); 1883 1884 /* sync input contexts before they are read from memory */ 1885 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1886 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1887 sc->sc_ctxsz * 3); 1888 1889 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1890 1891 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1892 false); 1893 1894 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1895 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1896 sc->sc_ctxsz * 2); 1897 1898 return err; 1899 } 1900 1901 /* ----- */ 1902 1903 static void 1904 xhci_noop(usbd_pipe_handle pipe) 1905 { 1906 DPRINTF(("%s\n", __func__)); 1907 } 1908 1909 /* root hub descriptors */ 1910 1911 static const usb_device_descriptor_t xhci_devd = { 1912 USB_DEVICE_DESCRIPTOR_SIZE, 1913 UDESC_DEVICE, /* type */ 1914 {0x00, 0x02}, /* USB version */ 1915 UDCLASS_HUB, /* class */ 1916 UDSUBCLASS_HUB, /* subclass */ 1917 UDPROTO_HSHUBSTT, /* protocol */ 1918 64, /* max packet */ 1919 {0},{0},{0x00,0x01}, /* device id */ 1920 1,2,0, /* string indexes */ 1921 1 /* # of configurations */ 1922 }; 1923 1924 static const usb_device_qualifier_t xhci_odevd = { 1925 USB_DEVICE_DESCRIPTOR_SIZE, 1926 UDESC_DEVICE_QUALIFIER, /* type */ 1927 {0x00, 0x02}, /* USB version */ 1928 UDCLASS_HUB, /* class */ 1929 UDSUBCLASS_HUB, /* subclass */ 1930 UDPROTO_FSHUB, /* protocol */ 1931 64, /* max packet */ 1932 1, /* # of configurations */ 1933 0 1934 }; 1935 1936 static const usb_config_descriptor_t xhci_confd = { 1937 USB_CONFIG_DESCRIPTOR_SIZE, 1938 UDESC_CONFIG, 1939 {USB_CONFIG_DESCRIPTOR_SIZE + 1940 USB_INTERFACE_DESCRIPTOR_SIZE + 1941 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1942 1, 1943 1, 1944 0, 1945 UC_ATTR_MBO | UC_SELF_POWERED, 1946 0 /* max power */ 1947 }; 1948 1949 static const usb_interface_descriptor_t xhci_ifcd = { 1950 USB_INTERFACE_DESCRIPTOR_SIZE, 1951 UDESC_INTERFACE, 1952 0, 1953 0, 1954 1, 1955 UICLASS_HUB, 1956 UISUBCLASS_HUB, 1957 UIPROTO_HSHUBSTT, 1958 0 1959 }; 1960 1961 static const usb_endpoint_descriptor_t xhci_endpd = { 1962 USB_ENDPOINT_DESCRIPTOR_SIZE, 1963 UDESC_ENDPOINT, 1964 UE_DIR_IN | XHCI_INTR_ENDPT, 1965 UE_INTERRUPT, 1966 {8, 0}, /* max packet */ 1967 12 1968 }; 1969 1970 static const usb_hub_descriptor_t xhci_hubd = { 1971 USB_HUB_DESCRIPTOR_SIZE, 1972 UDESC_HUB, 1973 0, 1974 {0,0}, 1975 0, 1976 0, 1977 {""}, 1978 {""}, 1979 }; 1980 1981 /* root hub control */ 1982 1983 static usbd_status 1984 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 1985 { 1986 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 1987 usbd_status err; 1988 1989 DPRINTF(("%s\n", __func__)); 1990 1991 /* Insert last in queue. */ 1992 mutex_enter(&sc->sc_lock); 1993 err = usb_insert_transfer(xfer); 1994 mutex_exit(&sc->sc_lock); 1995 if (err) 1996 return err; 1997 1998 /* Pipe isn't running, start first */ 1999 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2000 } 2001 2002 static usbd_status 2003 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2004 { 2005 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2006 usb_port_status_t ps; 2007 usb_device_request_t *req; 2008 void *buf = NULL; 2009 usb_hub_descriptor_t hubd; 2010 usbd_status err; 2011 int len, value, index; 2012 int l, totlen = 0; 2013 int port, i; 2014 uint32_t v; 2015 2016 DPRINTF(("%s\n", __func__)); 2017 2018 if (sc->sc_dying) 2019 return USBD_IOERROR; 2020 2021 req = &xfer->request; 2022 2023 value = UGETW(req->wValue); 2024 index = UGETW(req->wIndex); 2025 len = UGETW(req->wLength); 2026 2027 if (len != 0) 2028 buf = KERNADDR(&xfer->dmabuf, 0); 2029 2030 DPRINTF(("root req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2031 req->bRequest, value, index, len)); 2032 2033 #define C(x,y) ((x) | ((y) << 8)) 2034 switch(C(req->bRequest, req->bmRequestType)) { 2035 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2036 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2037 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2038 /* 2039 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2040 * for the integrated root hub. 2041 */ 2042 break; 2043 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2044 if (len > 0) { 2045 *(uint8_t *)buf = sc->sc_conf; 2046 totlen = 1; 2047 } 2048 break; 2049 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2050 DPRINTFN(8,("xhci_root_ctrl_start: wValue=0x%04x\n", value)); 2051 if (len == 0) 2052 break; 2053 switch(value >> 8) { 2054 case UDESC_DEVICE: 2055 if ((value & 0xff) != 0) { 2056 err = USBD_IOERROR; 2057 goto ret; 2058 } 2059 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2060 memcpy(buf, &xhci_devd, l); 2061 break; 2062 case UDESC_DEVICE_QUALIFIER: 2063 if ((value & 0xff) != 0) { 2064 } 2065 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2066 memcpy(buf, &xhci_odevd, l); 2067 break; 2068 case UDESC_OTHER_SPEED_CONFIGURATION: 2069 case UDESC_CONFIG: 2070 if ((value & 0xff) != 0) { 2071 err = USBD_IOERROR; 2072 goto ret; 2073 } 2074 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2075 memcpy(buf, &xhci_confd, l); 2076 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2077 value >> 8; 2078 buf = (char *)buf + l; 2079 len -= l; 2080 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2081 totlen += l; 2082 memcpy(buf, &xhci_ifcd, l); 2083 buf = (char *)buf + l; 2084 len -= l; 2085 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2086 totlen += l; 2087 memcpy(buf, &xhci_endpd, l); 2088 break; 2089 case UDESC_STRING: 2090 #define sd ((usb_string_descriptor_t *)buf) 2091 switch (value & 0xff) { 2092 case 0: /* Language table */ 2093 totlen = usb_makelangtbl(sd, len); 2094 break; 2095 case 1: /* Vendor */ 2096 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2097 break; 2098 case 2: /* Product */ 2099 totlen = usb_makestrdesc(sd, len, 2100 "xHCI Root Hub"); 2101 break; 2102 } 2103 #undef sd 2104 break; 2105 default: 2106 err = USBD_IOERROR; 2107 goto ret; 2108 } 2109 break; 2110 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2111 if (len > 0) { 2112 *(uint8_t *)buf = 0; 2113 totlen = 1; 2114 } 2115 break; 2116 case C(UR_GET_STATUS, UT_READ_DEVICE): 2117 if (len > 1) { 2118 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2119 totlen = 2; 2120 } 2121 break; 2122 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2123 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2124 if (len > 1) { 2125 USETW(((usb_status_t *)buf)->wStatus, 0); 2126 totlen = 2; 2127 } 2128 break; 2129 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2130 if (value >= USB_MAX_DEVICES) { 2131 err = USBD_IOERROR; 2132 goto ret; 2133 } 2134 //sc->sc_addr = value; 2135 break; 2136 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2137 if (value != 0 && value != 1) { 2138 err = USBD_IOERROR; 2139 goto ret; 2140 } 2141 sc->sc_conf = value; 2142 break; 2143 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2144 break; 2145 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2146 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2147 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2148 err = USBD_IOERROR; 2149 goto ret; 2150 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2151 break; 2152 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2153 break; 2154 /* Hub requests */ 2155 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2156 break; 2157 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2158 DPRINTFN(4, ("xhci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2159 "port=%d feature=%d\n", 2160 index, value)); 2161 if (index < 1 || index > sc->sc_hs_port_count) { 2162 err = USBD_IOERROR; 2163 goto ret; 2164 } 2165 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2166 v = xhci_op_read_4(sc, port); 2167 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2168 v &= ~XHCI_PS_CLEAR; 2169 switch (value) { 2170 case UHF_PORT_ENABLE: 2171 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2172 break; 2173 case UHF_PORT_SUSPEND: 2174 err = USBD_IOERROR; 2175 goto ret; 2176 case UHF_PORT_POWER: 2177 break; 2178 case UHF_PORT_TEST: 2179 case UHF_PORT_INDICATOR: 2180 err = USBD_IOERROR; 2181 goto ret; 2182 case UHF_C_PORT_CONNECTION: 2183 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2184 break; 2185 case UHF_C_PORT_ENABLE: 2186 case UHF_C_PORT_SUSPEND: 2187 case UHF_C_PORT_OVER_CURRENT: 2188 err = USBD_IOERROR; 2189 goto ret; 2190 case UHF_C_PORT_RESET: 2191 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2192 break; 2193 default: 2194 err = USBD_IOERROR; 2195 goto ret; 2196 } 2197 2198 break; 2199 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2200 if (len == 0) 2201 break; 2202 if ((value & 0xff) != 0) { 2203 err = USBD_IOERROR; 2204 goto ret; 2205 } 2206 hubd = xhci_hubd; 2207 hubd.bNbrPorts = sc->sc_hs_port_count; 2208 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2209 hubd.bPwrOn2PwrGood = 200; 2210 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8, v >>= 8) 2211 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2212 l = min(len, hubd.bDescLength); 2213 totlen = l; 2214 memcpy(buf, &hubd, l); 2215 break; 2216 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2217 if (len != 4) { 2218 err = USBD_IOERROR; 2219 goto ret; 2220 } 2221 memset(buf, 0, len); /* ? XXX */ 2222 totlen = len; 2223 break; 2224 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2225 DPRINTFN(8,("xhci_root_ctrl_start: get port status i=%d\n", 2226 index)); 2227 if (index < 1 || index > sc->sc_maxports) { 2228 err = USBD_IOERROR; 2229 goto ret; 2230 } 2231 if (len != 4) { 2232 err = USBD_IOERROR; 2233 goto ret; 2234 } 2235 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2236 index)); 2237 DPRINTF(("%s READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x\n", 2238 __func__, index, sc->sc_hs_port_start - 1 + index, v)); 2239 switch (XHCI_PS_SPEED_GET(v)) { 2240 case 1: 2241 i = UPS_FULL_SPEED; 2242 break; 2243 case 2: 2244 i = UPS_LOW_SPEED; 2245 break; 2246 case 3: 2247 i = UPS_HIGH_SPEED; 2248 break; 2249 default: 2250 i = 0; 2251 break; 2252 } 2253 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2254 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2255 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2256 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2257 if (v & XHCI_PS_PR) i |= UPS_RESET; 2258 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2259 USETW(ps.wPortStatus, i); 2260 i = 0; 2261 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2262 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2263 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2264 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2265 USETW(ps.wPortChange, i); 2266 l = min(len, sizeof ps); 2267 memcpy(buf, &ps, l); 2268 totlen = l; 2269 break; 2270 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2271 err = USBD_IOERROR; 2272 goto ret; 2273 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2274 break; 2275 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2276 if (index < 1 || index > sc->sc_hs_port_count) { 2277 err = USBD_IOERROR; 2278 goto ret; 2279 } 2280 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2281 v = xhci_op_read_4(sc, port); 2282 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2283 v &= ~XHCI_PS_CLEAR; 2284 switch (value) { 2285 case UHF_PORT_ENABLE: 2286 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2287 break; 2288 case UHF_PORT_SUSPEND: 2289 /* XXX suspend */ 2290 break; 2291 case UHF_PORT_RESET: 2292 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2293 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2294 /* Wait for reset to complete. */ 2295 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2296 if (sc->sc_dying) { 2297 err = USBD_IOERROR; 2298 goto ret; 2299 } 2300 v = xhci_op_read_4(sc, port); 2301 if (v & XHCI_PS_PR) { 2302 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2303 usb_delay_ms(&sc->sc_bus, 10); 2304 /* XXX */ 2305 } 2306 break; 2307 case UHF_PORT_POWER: 2308 /* XXX power control */ 2309 break; 2310 /* XXX more */ 2311 case UHF_C_PORT_RESET: 2312 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2313 break; 2314 default: 2315 err = USBD_IOERROR; 2316 goto ret; 2317 } 2318 break; 2319 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2320 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2321 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2322 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2323 break; 2324 default: 2325 err = USBD_IOERROR; 2326 goto ret; 2327 } 2328 xfer->actlen = totlen; 2329 err = USBD_NORMAL_COMPLETION; 2330 ret: 2331 xfer->status = err; 2332 mutex_enter(&sc->sc_lock); 2333 usb_transfer_complete(xfer); 2334 mutex_exit(&sc->sc_lock); 2335 return USBD_IN_PROGRESS; 2336 } 2337 2338 2339 static void 2340 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2341 { 2342 /* Nothing to do, all transfers are synchronous. */ 2343 } 2344 2345 2346 static void 2347 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2348 { 2349 DPRINTF(("%s\n", __func__)); 2350 /* Nothing to do. */ 2351 } 2352 2353 static void 2354 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2355 { 2356 xfer->hcpriv = NULL; 2357 } 2358 2359 /* root hub intrerrupt */ 2360 2361 static usbd_status 2362 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2363 { 2364 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2365 usbd_status err; 2366 2367 /* Insert last in queue. */ 2368 mutex_enter(&sc->sc_lock); 2369 err = usb_insert_transfer(xfer); 2370 mutex_exit(&sc->sc_lock); 2371 if (err) 2372 return err; 2373 2374 /* Pipe isn't running, start first */ 2375 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2376 } 2377 2378 static usbd_status 2379 xhci_root_intr_start(usbd_xfer_handle xfer) 2380 { 2381 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2382 2383 if (sc->sc_dying) 2384 return USBD_IOERROR; 2385 2386 mutex_enter(&sc->sc_lock); 2387 sc->sc_intrxfer = xfer; 2388 mutex_exit(&sc->sc_lock); 2389 2390 return USBD_IN_PROGRESS; 2391 } 2392 2393 static void 2394 xhci_root_intr_abort(usbd_xfer_handle xfer) 2395 { 2396 #ifdef DIAGNOSTIC 2397 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2398 #endif 2399 2400 KASSERT(mutex_owned(&sc->sc_lock)); 2401 if (xfer->pipe->intrxfer == xfer) { 2402 DPRINTF(("%s: remove\n", __func__)); 2403 xfer->pipe->intrxfer = NULL; 2404 } 2405 xfer->status = USBD_CANCELLED; 2406 usb_transfer_complete(xfer); 2407 } 2408 2409 static void 2410 xhci_root_intr_close(usbd_pipe_handle pipe) 2411 { 2412 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2413 2414 KASSERT(mutex_owned(&sc->sc_lock)); 2415 2416 DPRINTF(("%s\n", __func__)); 2417 2418 sc->sc_intrxfer = NULL; 2419 } 2420 2421 static void 2422 xhci_root_intr_done(usbd_xfer_handle xfer) 2423 { 2424 xfer->hcpriv = NULL; 2425 } 2426 2427 /* -------------- */ 2428 /* device control */ 2429 2430 static usbd_status 2431 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2432 { 2433 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2434 usbd_status err; 2435 2436 /* Insert last in queue. */ 2437 mutex_enter(&sc->sc_lock); 2438 err = usb_insert_transfer(xfer); 2439 mutex_exit(&sc->sc_lock); 2440 if (err) 2441 return (err); 2442 2443 /* Pipe isn't running, start first */ 2444 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2445 } 2446 2447 static usbd_status 2448 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2449 { 2450 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2451 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2452 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2453 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2454 struct xhci_xfer * const xx = (void *)xfer; 2455 usb_device_request_t * const req = &xfer->request; 2456 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2457 const uint32_t len = UGETW(req->wLength); 2458 usb_dma_t * const dma = &xfer->dmabuf; 2459 uint64_t parameter; 2460 uint32_t status; 2461 uint32_t control; 2462 u_int i; 2463 2464 DPRINTF(("%s\n", __func__)); 2465 DPRINTF(("req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2466 req->bRequest, UGETW(req->wValue), UGETW(req->wIndex), 2467 UGETW(req->wLength))); 2468 2469 /* XXX */ 2470 if (tr->is_halted) { 2471 xhci_reset_endpoint(xfer->pipe); 2472 tr->is_halted = false; 2473 xhci_set_dequeue(xfer->pipe); 2474 } 2475 2476 /* we rely on the bottom bits for extra info */ 2477 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2478 2479 KASSERT((xfer->rqflags & URQ_REQUEST) != 0); 2480 2481 i = 0; 2482 2483 /* setup phase */ 2484 memcpy(¶meter, req, sizeof(*req)); 2485 parameter = le64toh(parameter); 2486 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2487 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2488 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2489 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2490 XHCI_TRB_3_IDT_BIT; 2491 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2492 2493 if (len == 0) 2494 goto no_data; 2495 2496 /* data phase */ 2497 parameter = DMAADDR(dma, 0); 2498 KASSERT(len <= 0x10000); 2499 status = XHCI_TRB_2_IRQ_SET(0) | 2500 XHCI_TRB_2_TDSZ_SET(1) | 2501 XHCI_TRB_2_BYTES_SET(len); 2502 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2503 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2504 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2505 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2506 2507 parameter = (uintptr_t)xfer | 0x3; 2508 status = XHCI_TRB_2_IRQ_SET(0); 2509 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2510 XHCI_TRB_3_IOC_BIT; 2511 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2512 2513 no_data: 2514 parameter = 0; 2515 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_TDSZ_SET(1); 2516 /* the status stage has inverted direction */ 2517 control = (isread ? 0 : XHCI_TRB_3_DIR_IN) | 2518 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2519 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2520 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2521 2522 parameter = (uintptr_t)xfer | 0x0; 2523 status = XHCI_TRB_2_IRQ_SET(0); 2524 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2525 XHCI_TRB_3_IOC_BIT; 2526 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2527 2528 mutex_enter(&tr->xr_lock); 2529 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2530 mutex_exit(&tr->xr_lock); 2531 2532 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2533 2534 if (xfer->timeout && !sc->sc_bus.use_polling) { 2535 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2536 xhci_timeout, xfer); 2537 } 2538 2539 if (sc->sc_bus.use_polling) { 2540 device_printf(sc->sc_dev, "%s polling\n", __func__); 2541 //xhci_waitintr(sc, xfer); 2542 } 2543 2544 return USBD_IN_PROGRESS; 2545 } 2546 2547 static void 2548 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2549 { 2550 DPRINTF(("%s\n", __func__)); 2551 2552 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2553 2554 } 2555 2556 static void 2557 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2558 { 2559 DPRINTF(("%s\n", __func__)); 2560 } 2561 2562 static void 2563 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2564 { 2565 DPRINTF(("%s\n", __func__)); 2566 } 2567 2568 /* ----------------- */ 2569 /* device isochronus */ 2570 2571 /* ----------- */ 2572 /* device bulk */ 2573 2574 static usbd_status 2575 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2576 { 2577 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2578 usbd_status err; 2579 2580 /* Insert last in queue. */ 2581 mutex_enter(&sc->sc_lock); 2582 err = usb_insert_transfer(xfer); 2583 mutex_exit(&sc->sc_lock); 2584 if (err) 2585 return err; 2586 2587 /* 2588 * Pipe isn't running (otherwise err would be USBD_INPROG), 2589 * so start it first. 2590 */ 2591 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2592 } 2593 2594 static usbd_status 2595 xhci_device_bulk_start(usbd_xfer_handle xfer) 2596 { 2597 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2598 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2599 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2600 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2601 struct xhci_xfer * const xx = (void *)xfer; 2602 const uint32_t len = xfer->length; 2603 usb_dma_t * const dma = &xfer->dmabuf; 2604 uint64_t parameter; 2605 uint32_t status; 2606 uint32_t control; 2607 u_int i = 0; 2608 2609 #if 0 2610 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2611 xs->xs_idx, dci); 2612 #endif 2613 2614 if (sc->sc_dying) 2615 return USBD_IOERROR; 2616 2617 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2618 2619 parameter = DMAADDR(dma, 0); 2620 KASSERT(len <= 0x10000); 2621 status = XHCI_TRB_2_IRQ_SET(0) | 2622 XHCI_TRB_2_TDSZ_SET(1) | 2623 XHCI_TRB_2_BYTES_SET(len); 2624 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2625 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2626 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2627 2628 mutex_enter(&tr->xr_lock); 2629 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2630 mutex_exit(&tr->xr_lock); 2631 2632 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2633 2634 if (sc->sc_bus.use_polling) { 2635 device_printf(sc->sc_dev, "%s polling\n", __func__); 2636 //xhci_waitintr(sc, xfer); 2637 } 2638 2639 return USBD_IN_PROGRESS; 2640 } 2641 2642 static void 2643 xhci_device_bulk_done(usbd_xfer_handle xfer) 2644 { 2645 //struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2646 //struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2647 //const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2648 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2649 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2650 2651 DPRINTF(("%s\n", __func__)); 2652 2653 #if 0 2654 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2655 xs->xs_idx, dci); 2656 #endif 2657 2658 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2659 2660 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2661 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2662 2663 2664 } 2665 2666 static void 2667 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2668 { 2669 DPRINTF(("%s\n", __func__)); 2670 } 2671 2672 static void 2673 xhci_device_bulk_close(usbd_pipe_handle pipe) 2674 { 2675 DPRINTF(("%s\n", __func__)); 2676 } 2677 2678 /* --------------- */ 2679 /* device intrrupt */ 2680 2681 static usbd_status 2682 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2683 { 2684 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2685 usbd_status err; 2686 2687 /* Insert last in queue. */ 2688 mutex_enter(&sc->sc_lock); 2689 err = usb_insert_transfer(xfer); 2690 mutex_exit(&sc->sc_lock); 2691 if (err) 2692 return err; 2693 2694 /* 2695 * Pipe isn't running (otherwise err would be USBD_INPROG), 2696 * so start it first. 2697 */ 2698 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2699 } 2700 2701 static usbd_status 2702 xhci_device_intr_start(usbd_xfer_handle xfer) 2703 { 2704 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2705 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2706 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2707 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2708 struct xhci_xfer * const xx = (void *)xfer; 2709 const uint32_t len = xfer->length; 2710 usb_dma_t * const dma = &xfer->dmabuf; 2711 uint64_t parameter; 2712 uint32_t status; 2713 uint32_t control; 2714 u_int i = 0; 2715 2716 #if 0 2717 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2718 xs->xs_idx, dci); 2719 #endif 2720 2721 if (sc->sc_dying) 2722 return USBD_IOERROR; 2723 2724 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2725 2726 parameter = DMAADDR(dma, 0); 2727 KASSERT(len <= 0x10000); 2728 status = XHCI_TRB_2_IRQ_SET(0) | 2729 XHCI_TRB_2_TDSZ_SET(1) | 2730 XHCI_TRB_2_BYTES_SET(len); 2731 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2732 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2733 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2734 2735 mutex_enter(&tr->xr_lock); 2736 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2737 mutex_exit(&tr->xr_lock); 2738 2739 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2740 2741 if (sc->sc_bus.use_polling) { 2742 device_printf(sc->sc_dev, "%s polling\n", __func__); 2743 //xhci_waitintr(sc, xfer); 2744 } 2745 2746 return USBD_IN_PROGRESS; 2747 } 2748 2749 static void 2750 xhci_device_intr_done(usbd_xfer_handle xfer) 2751 { 2752 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2753 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2754 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2755 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2756 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2757 DPRINTF(("%s\n", __func__)); 2758 2759 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2760 xs->xs_idx, dci); 2761 2762 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2763 2764 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2765 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2766 2767 #if 0 2768 device_printf(sc->sc_dev, ""); 2769 for (size_t i = 0; i < xfer->length; i++) { 2770 printf(" %02x", ((uint8_t const *)xfer->buffer)[i]); 2771 } 2772 printf("\n"); 2773 #endif 2774 2775 if (xfer->pipe->repeat) { 2776 xfer->status = xhci_device_intr_start(xfer); 2777 } else { 2778 callout_stop(&xfer->timeout_handle); /* XXX */ 2779 } 2780 2781 } 2782 2783 static void 2784 xhci_device_intr_abort(usbd_xfer_handle xfer) 2785 { 2786 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2787 DPRINTF(("%s\n", __func__)); 2788 device_printf(sc->sc_dev, "%s %p\n", __func__, xfer); 2789 /* XXX */ 2790 if (xfer->pipe->intrxfer == xfer) { 2791 xfer->pipe->intrxfer = NULL; 2792 } 2793 xfer->status = USBD_CANCELLED; 2794 mutex_enter(&sc->sc_lock); 2795 usb_transfer_complete(xfer); 2796 mutex_exit(&sc->sc_lock); 2797 } 2798 2799 static void 2800 xhci_device_intr_close(usbd_pipe_handle pipe) 2801 { 2802 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2803 DPRINTF(("%s\n", __func__)); 2804 device_printf(sc->sc_dev, "%s %p\n", __func__, pipe); 2805 xhci_unconfigure_endpoint(pipe); 2806 } 2807 2808 /* ------------ */ 2809 2810 static void 2811 xhci_timeout(void *addr) 2812 { 2813 struct xhci_xfer * const xx = addr; 2814 usbd_xfer_handle const xfer = &xx->xx_xfer; 2815 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2816 2817 if (sc->sc_dying) { 2818 return; 2819 } 2820 2821 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2822 USB_TASKQ_MPSAFE); 2823 usb_add_task(xx->xx_xfer.pipe->device, &xx->xx_abort_task, 2824 USB_TASKQ_HC); 2825 } 2826 2827 static void 2828 xhci_timeout_task(void *addr) 2829 { 2830 usbd_xfer_handle const xfer = addr; 2831 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2832 2833 mutex_enter(&sc->sc_lock); 2834 #if 0 2835 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2836 #else 2837 xfer->status = USBD_TIMEOUT; 2838 usb_transfer_complete(xfer); 2839 #endif 2840 mutex_exit(&sc->sc_lock); 2841 } 2842
Indexes created Wed Sep 24 05:09:52 GMT 2025