xhci.c revision 1.107.2.11
1 /* $NetBSD: xhci.c,v 1.107.2.11 2023/01/23 12:05:36 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.107.2.11 2023/01/23 12:05:36 martin Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 119 #define XHCIHIST_FUNC() USBHIST_FUNC() 120 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 121 #define XHCIHIST_CALLARGS(FMT,A,B,C,D) \ 122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D) 123 124 #define XHCI_DCI_SLOT 0 125 #define XHCI_DCI_EP_CONTROL 1 126 127 #define XHCI_ICI_INPUT_CONTROL 0 128 129 struct xhci_pipe { 130 struct usbd_pipe xp_pipe; 131 struct usb_task xp_async_task; 132 }; 133 134 #define XHCI_COMMAND_RING_TRBS 256 135 #define XHCI_EVENT_RING_TRBS 256 136 #define XHCI_EVENT_RING_SEGMENTS 1 137 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 138 139 static usbd_status xhci_open(struct usbd_pipe *); 140 static void xhci_close_pipe(struct usbd_pipe *); 141 static int xhci_intr1(struct xhci_softc * const); 142 static void xhci_softintr(void *); 143 static void xhci_poll(struct usbd_bus *); 144 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 145 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 146 static void xhci_abortx(struct usbd_xfer *); 147 static bool xhci_dying(struct usbd_bus *); 148 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 149 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 150 struct usbd_port *); 151 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 152 void *, int); 153 154 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 155 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 156 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 157 static usbd_status xhci_stop_endpoint_cmd(struct xhci_softc *, 158 struct xhci_slot *, u_int, uint32_t); 159 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 160 161 static void xhci_host_dequeue(struct xhci_ring * const); 162 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 163 164 static usbd_status xhci_do_command(struct xhci_softc * const, 165 struct xhci_soft_trb * const, int); 166 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 167 struct xhci_soft_trb * const, int); 168 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 169 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 170 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 171 static usbd_status xhci_enable_slot(struct xhci_softc * const, 172 uint8_t * const); 173 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 174 static usbd_status xhci_address_device(struct xhci_softc * const, 175 uint64_t, uint8_t, bool); 176 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 177 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 178 struct xhci_slot * const, u_int); 179 static usbd_status xhci_ring_init(struct xhci_softc * const, 180 struct xhci_ring * const, size_t, size_t); 181 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 182 183 static void xhci_setup_ctx(struct usbd_pipe *); 184 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 185 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 186 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 187 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 188 189 static void xhci_noop(struct usbd_pipe *); 190 191 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 192 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 193 static void xhci_root_intr_abort(struct usbd_xfer *); 194 static void xhci_root_intr_close(struct usbd_pipe *); 195 static void xhci_root_intr_done(struct usbd_xfer *); 196 197 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 198 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 199 static void xhci_device_ctrl_abort(struct usbd_xfer *); 200 static void xhci_device_ctrl_close(struct usbd_pipe *); 201 static void xhci_device_ctrl_done(struct usbd_xfer *); 202 203 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 204 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 205 static void xhci_device_intr_abort(struct usbd_xfer *); 206 static void xhci_device_intr_close(struct usbd_pipe *); 207 static void xhci_device_intr_done(struct usbd_xfer *); 208 209 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 210 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 211 static void xhci_device_bulk_abort(struct usbd_xfer *); 212 static void xhci_device_bulk_close(struct usbd_pipe *); 213 static void xhci_device_bulk_done(struct usbd_xfer *); 214 215 static const struct usbd_bus_methods xhci_bus_methods = { 216 .ubm_open = xhci_open, 217 .ubm_softint = xhci_softintr, 218 .ubm_dopoll = xhci_poll, 219 .ubm_allocx = xhci_allocx, 220 .ubm_freex = xhci_freex, 221 .ubm_abortx = xhci_abortx, 222 .ubm_dying = xhci_dying, 223 .ubm_getlock = xhci_get_lock, 224 .ubm_newdev = xhci_new_device, 225 .ubm_rhctrl = xhci_roothub_ctrl, 226 }; 227 228 static const struct usbd_pipe_methods xhci_root_intr_methods = { 229 .upm_transfer = xhci_root_intr_transfer, 230 .upm_start = xhci_root_intr_start, 231 .upm_abort = xhci_root_intr_abort, 232 .upm_close = xhci_root_intr_close, 233 .upm_cleartoggle = xhci_noop, 234 .upm_done = xhci_root_intr_done, 235 }; 236 237 238 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 239 .upm_transfer = xhci_device_ctrl_transfer, 240 .upm_start = xhci_device_ctrl_start, 241 .upm_abort = xhci_device_ctrl_abort, 242 .upm_close = xhci_device_ctrl_close, 243 .upm_cleartoggle = xhci_noop, 244 .upm_done = xhci_device_ctrl_done, 245 }; 246 247 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 248 .upm_cleartoggle = xhci_noop, 249 }; 250 251 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 252 .upm_transfer = xhci_device_bulk_transfer, 253 .upm_start = xhci_device_bulk_start, 254 .upm_abort = xhci_device_bulk_abort, 255 .upm_close = xhci_device_bulk_close, 256 .upm_cleartoggle = xhci_noop, 257 .upm_done = xhci_device_bulk_done, 258 }; 259 260 static const struct usbd_pipe_methods xhci_device_intr_methods = { 261 .upm_transfer = xhci_device_intr_transfer, 262 .upm_start = xhci_device_intr_start, 263 .upm_abort = xhci_device_intr_abort, 264 .upm_close = xhci_device_intr_close, 265 .upm_cleartoggle = xhci_noop, 266 .upm_done = xhci_device_intr_done, 267 }; 268 269 static inline uint32_t 270 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 271 { 272 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 273 } 274 275 static inline uint32_t 276 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 277 { 278 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 279 } 280 281 static inline void 282 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 283 uint32_t value) 284 { 285 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 286 } 287 288 #if 0 /* unused */ 289 static inline void 290 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 291 uint32_t value) 292 { 293 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 294 } 295 #endif /* unused */ 296 297 static inline uint32_t 298 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 299 { 300 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 301 } 302 303 static inline uint32_t 304 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 305 { 306 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 307 } 308 309 static inline void 310 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 311 uint32_t value) 312 { 313 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 314 } 315 316 static inline uint64_t 317 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 318 { 319 uint64_t value; 320 321 if (sc->sc_ac64) { 322 #ifdef XHCI_USE_BUS_SPACE_8 323 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 324 #else 325 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 326 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 327 offset + 4) << 32; 328 #endif 329 } else { 330 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 331 } 332 333 return value; 334 } 335 336 static inline void 337 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 338 uint64_t value) 339 { 340 if (sc->sc_ac64) { 341 #ifdef XHCI_USE_BUS_SPACE_8 342 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 343 #else 344 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 345 (value >> 0) & 0xffffffff); 346 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 347 (value >> 32) & 0xffffffff); 348 #endif 349 } else { 350 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 351 } 352 } 353 354 static inline void 355 xhci_op_barrier(const struct xhci_softc * const sc, bus_size_t offset, 356 bus_size_t len, int flags) 357 { 358 bus_space_barrier(sc->sc_iot, sc->sc_obh, offset, len, flags); 359 } 360 361 static inline uint32_t 362 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 363 { 364 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 365 } 366 367 static inline void 368 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 369 uint32_t value) 370 { 371 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 372 } 373 374 static inline uint64_t 375 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 376 { 377 uint64_t value; 378 379 if (sc->sc_ac64) { 380 #ifdef XHCI_USE_BUS_SPACE_8 381 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 382 #else 383 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 384 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 385 offset + 4) << 32; 386 #endif 387 } else { 388 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 389 } 390 391 return value; 392 } 393 394 static inline void 395 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 396 uint64_t value) 397 { 398 if (sc->sc_ac64) { 399 #ifdef XHCI_USE_BUS_SPACE_8 400 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 401 #else 402 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 403 (value >> 0) & 0xffffffff); 404 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 405 (value >> 32) & 0xffffffff); 406 #endif 407 } else { 408 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 409 } 410 } 411 412 #if 0 /* unused */ 413 static inline uint32_t 414 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 415 { 416 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 417 } 418 #endif /* unused */ 419 420 static inline void 421 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 422 uint32_t value) 423 { 424 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 425 } 426 427 /* --- */ 428 429 static inline uint8_t 430 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 431 { 432 u_int eptype = 0; 433 434 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 435 case UE_CONTROL: 436 eptype = 0x0; 437 break; 438 case UE_ISOCHRONOUS: 439 eptype = 0x1; 440 break; 441 case UE_BULK: 442 eptype = 0x2; 443 break; 444 case UE_INTERRUPT: 445 eptype = 0x3; 446 break; 447 } 448 449 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 450 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 451 return eptype | 0x4; 452 else 453 return eptype; 454 } 455 456 static u_int 457 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 458 { 459 /* xHCI 1.0 section 4.5.1 */ 460 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 461 u_int in = 0; 462 463 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 464 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 465 in = 1; 466 467 return epaddr * 2 + in; 468 } 469 470 static inline u_int 471 xhci_dci_to_ici(const u_int i) 472 { 473 return i + 1; 474 } 475 476 static inline void * 477 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 478 const u_int dci) 479 { 480 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 481 } 482 483 #if 0 /* unused */ 484 static inline bus_addr_t 485 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 486 const u_int dci) 487 { 488 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 489 } 490 #endif /* unused */ 491 492 static inline void * 493 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 494 const u_int ici) 495 { 496 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 497 } 498 499 static inline bus_addr_t 500 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 501 const u_int ici) 502 { 503 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 504 } 505 506 static inline struct xhci_trb * 507 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 508 { 509 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 510 } 511 512 static inline bus_addr_t 513 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 514 { 515 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 516 } 517 518 static inline void 519 xhci_soft_trb_put(struct xhci_soft_trb * const trb, 520 uint64_t parameter, uint32_t status, uint32_t control) 521 { 522 trb->trb_0 = parameter; 523 trb->trb_2 = status; 524 trb->trb_3 = control; 525 } 526 527 static inline void 528 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 529 uint32_t control) 530 { 531 trb->trb_0 = htole64(parameter); 532 trb->trb_2 = htole32(status); 533 trb->trb_3 = htole32(control); 534 } 535 536 static int 537 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 538 { 539 /* base address of TRBs */ 540 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 541 542 /* trb_0 range sanity check */ 543 if (trb_0 == 0 || trb_0 < trbp || 544 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 545 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 546 return 1; 547 } 548 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 549 return 0; 550 } 551 552 static unsigned int 553 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 554 u_int dci) 555 { 556 uint32_t *cp; 557 558 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 559 cp = xhci_slot_get_dcv(sc, xs, dci); 560 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 561 } 562 563 static inline unsigned int 564 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 565 { 566 const unsigned int port = ctlrport - 1; 567 const uint8_t bit = __BIT(port % NBBY); 568 569 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 570 } 571 572 /* 573 * Return the roothub port for a controller port. Both are 1..n. 574 */ 575 static inline unsigned int 576 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 577 { 578 579 return sc->sc_ctlrportmap[ctrlport - 1]; 580 } 581 582 /* 583 * Return the controller port for a bus roothub port. Both are 1..n. 584 */ 585 static inline unsigned int 586 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 587 unsigned int rhport) 588 { 589 590 return sc->sc_rhportmap[bn][rhport - 1]; 591 } 592 593 /* --- */ 594 595 void 596 xhci_childdet(device_t self, device_t child) 597 { 598 struct xhci_softc * const sc = device_private(self); 599 600 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 601 if (child == sc->sc_child2) 602 sc->sc_child2 = NULL; 603 else if (child == sc->sc_child) 604 sc->sc_child = NULL; 605 } 606 607 int 608 xhci_detach(struct xhci_softc *sc, int flags) 609 { 610 int rv = 0; 611 612 if (sc->sc_child2 != NULL) { 613 rv = config_detach(sc->sc_child2, flags); 614 if (rv != 0) 615 return rv; 616 KASSERT(sc->sc_child2 == NULL); 617 } 618 619 if (sc->sc_child != NULL) { 620 rv = config_detach(sc->sc_child, flags); 621 if (rv != 0) 622 return rv; 623 KASSERT(sc->sc_child == NULL); 624 } 625 626 /* XXX unconfigure/free slots */ 627 628 /* verify: */ 629 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 630 xhci_op_write_4(sc, XHCI_USBCMD, 0); 631 /* do we need to wait for stop? */ 632 633 xhci_op_write_8(sc, XHCI_CRCR, 0); 634 xhci_ring_free(sc, &sc->sc_cr); 635 cv_destroy(&sc->sc_command_cv); 636 cv_destroy(&sc->sc_cmdbusy_cv); 637 638 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 639 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 640 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 641 xhci_ring_free(sc, &sc->sc_er); 642 643 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 644 645 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 646 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 647 648 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 649 650 kmem_free(sc->sc_ctlrportbus, 651 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 652 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 653 654 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 655 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 656 } 657 658 mutex_destroy(&sc->sc_lock); 659 mutex_destroy(&sc->sc_intr_lock); 660 661 pool_cache_destroy(sc->sc_xferpool); 662 663 return rv; 664 } 665 666 int 667 xhci_activate(device_t self, enum devact act) 668 { 669 struct xhci_softc * const sc = device_private(self); 670 671 switch (act) { 672 case DVACT_DEACTIVATE: 673 sc->sc_dying = true; 674 return 0; 675 default: 676 return EOPNOTSUPP; 677 } 678 } 679 680 bool 681 xhci_suspend(device_t self, const pmf_qual_t *qual) 682 { 683 struct xhci_softc * const sc = device_private(self); 684 size_t i, j, bn, dci; 685 int port; 686 uint32_t v; 687 usbd_status err; 688 bool ok = false; 689 690 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 691 692 mutex_enter(&sc->sc_lock); 693 694 /* 695 * Block issuance of new commands, and wait for all pending 696 * commands to complete. 697 */ 698 KASSERT(sc->sc_suspender == NULL); 699 sc->sc_suspender = curlwp; 700 while (sc->sc_command_addr != 0) 701 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 702 703 /* 704 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 705 * xHCI Power Management, p. 342 706 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=342 707 */ 708 709 /* 710 * `1. Stop all USB activity by issuing Stop Endpoint Commands 711 * for Busy endpoints in the Running state. If the Force 712 * Save Context Capability (FSC = ``0'') is not supported, 713 * then Stop Endpoint Commands shall be issued for all idle 714 * endpoints in the Running state as well. The Stop 715 * Endpoint Command causes the xHC to update the respective 716 * Endpoint or Stream Contexts in system memory, e.g. the 717 * TR Dequeue Pointer, DCS, etc. fields. Refer to 718 * Implementation Note "0".' 719 */ 720 for (i = 0; i < sc->sc_maxslots; i++) { 721 struct xhci_slot *xs = &sc->sc_slots[i]; 722 723 /* Skip if the slot is not in use. */ 724 if (xs->xs_idx == 0) 725 continue; 726 727 for (dci = 0; dci < 32; dci++) { 728 /* Skip if the endpoint is not Running. */ 729 /* XXX What about Busy? */ 730 if (xhci_get_epstate(sc, xs, dci) != 731 XHCI_EPSTATE_RUNNING) 732 continue; 733 734 /* Stop endpoint. */ 735 err = xhci_stop_endpoint_cmd(sc, xs, dci, 736 XHCI_TRB_3_SUSP_EP_BIT); 737 if (err) { 738 device_printf(self, "failed to stop endpoint" 739 " slot %zu dci %zu err %d\n", 740 i, dci, err); 741 goto out; 742 } 743 } 744 } 745 746 /* 747 * Next, suspend all the ports: 748 * 749 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.15: 750 * Suspend-Resume, pp. 276-283 751 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=276 752 */ 753 for (bn = 0; bn < 2; bn++) { 754 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 755 /* 4.15.1: Port Suspend. */ 756 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 757 758 /* 759 * `System software places individual ports 760 * into suspend mode by writing a ``3'' into 761 * the appropriate PORTSC register Port Link 762 * State (PLS) field (refer to Section 5.4.8). 763 * Software should only set the PLS field to 764 * ``3'' when the port is in the Enabled 765 * state.' 766 * 767 * `Software should not attempt to suspend a 768 * port unless the port reports that it is in 769 * the enabled (PED = ``1''; PLS < ``3'') 770 * state (refer to Section 5.4.8 for more 771 * information about PED and PLS).' 772 */ 773 v = xhci_op_read_4(sc, port); 774 if (((v & XHCI_PS_PED) == 0) || 775 XHCI_PS_PLS_GET(v) >= XHCI_PS_PLS_U3) 776 continue; 777 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 778 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU3); 779 xhci_op_write_4(sc, port, v); 780 781 /* 782 * `When the PLS field is written with U3 783 * (``3''), the status of the PLS bit will not 784 * change to the target U state U3 until the 785 * suspend signaling has completed to the 786 * attached device (which may be as long as 787 * 10ms.).' 788 * 789 * `Software is required to wait for U3 790 * transitions to complete before it puts the 791 * xHC into a low power state, and before 792 * resuming the port.' 793 * 794 * XXX Take advantage of the technique to 795 * reduce polling on host controllers that 796 * support the U3C capability. 797 */ 798 for (j = 0; j < XHCI_WAIT_PLS_U3; j++) { 799 v = xhci_op_read_4(sc, port); 800 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U3) 801 break; 802 usb_delay_ms(&sc->sc_bus, 1); 803 } 804 if (j == XHCI_WAIT_PLS_U3) { 805 device_printf(self, 806 "suspend timeout on bus %zu port %zu\n", 807 bn, i); 808 goto out; 809 } 810 } 811 } 812 813 /* 814 * `2. Ensure that the Command Ring is in the Stopped state 815 * (CRR = ``0'') or Idle (i.e. the Command Transfer Ring is 816 * empty), and all Command Completion Events associated 817 * with them have been received.' 818 * 819 * XXX 820 */ 821 822 /* `3. Stop the controller by setting Run/Stop (R/S) = ``0''.' */ 823 xhci_op_write_4(sc, XHCI_USBCMD, 824 xhci_op_read_4(sc, XHCI_USBCMD) & ~XHCI_CMD_RS); 825 826 /* 827 * `4. Read the Operational Runtime, and VTIO registers in the 828 * following order: USBCMD, DNCTRL, DCBAAP, CONFIG, ERSTSZ, 829 * ERSTBA, ERDP, IMAN, IMOD, and VTIO and save their 830 * state.' 831 * 832 * (We don't use VTIO here (XXX for now?).) 833 */ 834 sc->sc_regs.usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 835 sc->sc_regs.dnctrl = xhci_op_read_4(sc, XHCI_DNCTRL); 836 sc->sc_regs.dcbaap = xhci_op_read_8(sc, XHCI_DCBAAP); 837 sc->sc_regs.config = xhci_op_read_4(sc, XHCI_CONFIG); 838 sc->sc_regs.erstsz0 = xhci_rt_read_4(sc, XHCI_ERSTSZ(0)); 839 sc->sc_regs.erstba0 = xhci_rt_read_8(sc, XHCI_ERSTBA(0)); 840 sc->sc_regs.erdp0 = xhci_rt_read_8(sc, XHCI_ERDP(0)); 841 sc->sc_regs.iman0 = xhci_rt_read_4(sc, XHCI_IMAN(0)); 842 sc->sc_regs.imod0 = xhci_rt_read_4(sc, XHCI_IMOD(0)); 843 844 /* 845 * `5. Set the Controller Save State (CSS) flag in the USBCMD 846 * register (5.4.1)...' 847 */ 848 xhci_op_write_4(sc, XHCI_USBCMD, 849 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CSS); 850 851 /* 852 * `...and wait for the Save State Status (SSS) flag in the 853 * USBSTS register (5.4.2) to transition to ``0''.' 854 */ 855 for (i = 0; i < XHCI_WAIT_SSS; i++) { 856 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SSS) == 0) 857 break; 858 usb_delay_ms(&sc->sc_bus, 1); 859 } 860 if (i >= XHCI_WAIT_SSS) { 861 device_printf(self, "suspend timeout, USBSTS.SSS\n"); 862 /* 863 * Just optimistically go on and check SRE anyway -- 864 * what's the worst that could happen? 865 */ 866 } 867 868 /* 869 * `Note: After a Save or Restore operation completes, the 870 * Save/Restore Error (SRE) flag in the USBSTS register should 871 * be checked to ensure that the operation completed 872 * successfully.' 873 */ 874 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 875 device_printf(self, "suspend error, USBSTS.SRE\n"); 876 goto out; 877 } 878 879 /* Success! */ 880 ok = true; 881 882 out: mutex_exit(&sc->sc_lock); 883 return ok; 884 } 885 886 bool 887 xhci_resume(device_t self, const pmf_qual_t *qual) 888 { 889 struct xhci_softc * const sc = device_private(self); 890 size_t i, j, bn, dci; 891 int port; 892 uint32_t v; 893 bool ok = false; 894 895 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 896 897 mutex_enter(&sc->sc_lock); 898 KASSERT(sc->sc_suspender); 899 900 /* 901 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 902 * xHCI Power Management, p. 343 903 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=343 904 */ 905 906 /* 907 * `4. Restore the Operational Runtime, and VTIO registers with 908 * their previously saved state in the following order: 909 * DNCTRL, DCBAAP, CONFIG, ERSTSZ, ERSTBA, ERDP, IMAN, 910 * IMOD, and VTIO.' 911 * 912 * (We don't use VTIO here (for now?).) 913 */ 914 xhci_op_write_4(sc, XHCI_USBCMD, sc->sc_regs.usbcmd); 915 xhci_op_write_4(sc, XHCI_DNCTRL, sc->sc_regs.dnctrl); 916 xhci_op_write_8(sc, XHCI_DCBAAP, sc->sc_regs.dcbaap); 917 xhci_op_write_4(sc, XHCI_CONFIG, sc->sc_regs.config); 918 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), sc->sc_regs.erstsz0); 919 xhci_rt_write_8(sc, XHCI_ERSTBA(0), sc->sc_regs.erstba0); 920 xhci_rt_write_8(sc, XHCI_ERDP(0), sc->sc_regs.erdp0); 921 xhci_rt_write_4(sc, XHCI_IMAN(0), sc->sc_regs.iman0); 922 xhci_rt_write_4(sc, XHCI_IMOD(0), sc->sc_regs.imod0); 923 924 memset(&sc->sc_regs, 0, sizeof(sc->sc_regs)); /* paranoia */ 925 926 /* 927 * `5. Set the Controller Restore State (CRS) flag in the 928 * USBCMD register (5.4.1) to ``1''...' 929 */ 930 xhci_op_write_4(sc, XHCI_USBCMD, 931 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CRS); 932 933 /* 934 * `...and wait for the Restore State Status (RSS) in the 935 * USBSTS register (5.4.2) to transition to ``0''.' 936 */ 937 for (i = 0; i < XHCI_WAIT_RSS; i++) { 938 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_RSS) == 0) 939 break; 940 usb_delay_ms(&sc->sc_bus, 1); 941 } 942 if (i >= XHCI_WAIT_RSS) { 943 device_printf(self, "suspend timeout, USBSTS.RSS\n"); 944 goto out; 945 } 946 947 /* 948 * `6. Reinitialize the Command Ring, i.e. so its Cycle bits 949 * are consistent with the RCS values to be written to the 950 * CRCR.' 951 * 952 * XXX Hope just zeroing it is good enough! 953 */ 954 xhci_host_dequeue(&sc->sc_cr); 955 956 /* 957 * `7. Write the CRCR with the address and RCS value of the 958 * reinitialized Command Ring. Note that this write will 959 * cause the Command Ring to restart at the address 960 * specified by the CRCR.' 961 */ 962 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 963 sc->sc_cr.xr_cs); 964 965 /* 966 * `8. Enable the controller by setting Run/Stop (R/S) = 967 * ``1''.' 968 */ 969 xhci_op_write_4(sc, XHCI_USBCMD, 970 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_RS); 971 972 /* 973 * `9. Software shall walk the USB topology and initialize each 974 * of the xHC PORTSC, PORTPMSC, and PORTLI registers, and 975 * external hub ports attached to USB devices.' 976 * 977 * This follows the procedure in 4.15 `Suspend-Resume', 4.15.2 978 * `Port Resume', 4.15.2.1 `Host Initiated'. 979 * 980 * XXX We should maybe batch up initiating the state 981 * transitions, and then wait for them to complete all at once. 982 */ 983 for (bn = 0; bn < 2; bn++) { 984 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 985 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 986 987 /* `When a port is in the U3 state: ...' */ 988 v = xhci_op_read_4(sc, port); 989 if (XHCI_PS_PLS_GET(v) != XHCI_PS_PLS_U3) 990 continue; 991 992 /* 993 * `For a USB2 protocol port, software shall 994 * write a ``15'' (Resume) to the PLS field to 995 * initiate resume signaling. The port shall 996 * transition to the Resume substate and the 997 * xHC shall transmit the resume signaling 998 * within 1ms (T_URSM). Software shall ensure 999 * that resume is signaled for at least 20ms 1000 * (T_DRSMDN). Software shall start timing 1001 * T_DRSMDN from the write of ``15'' (Resume) 1002 * to PLS.' 1003 */ 1004 if (bn == 1) { 1005 KASSERT(sc->sc_bus2.ub_revision == USBREV_2_0); 1006 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1007 v |= XHCI_PS_LWS; 1008 v |= XHCI_PS_PLS_SET(XHCI_PS_PLS_SETRESUME); 1009 xhci_op_write_4(sc, port, v); 1010 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1011 } else { 1012 KASSERT(sc->sc_bus.ub_revision > USBREV_2_0); 1013 } 1014 1015 /* 1016 * `For a USB3 protocol port [and a USB2 1017 * protocol port after transitioning to 1018 * Resume], software shall write a ``0'' (U0) 1019 * to the PLS field...' 1020 */ 1021 v = xhci_op_read_4(sc, port); 1022 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1023 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU0); 1024 xhci_op_write_4(sc, port, v); 1025 1026 for (j = 0; j < XHCI_WAIT_PLS_U0; j++) { 1027 v = xhci_op_read_4(sc, port); 1028 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U0) 1029 break; 1030 usb_delay_ms(&sc->sc_bus, 1); 1031 } 1032 if (j == XHCI_WAIT_PLS_U0) { 1033 device_printf(self, 1034 "resume timeout on bus %zu port %zu\n", 1035 bn, i); 1036 goto out; 1037 } 1038 } 1039 } 1040 1041 /* 1042 * `10. Restart each of the previously Running endpoints by 1043 * ringing their doorbells.' 1044 */ 1045 for (i = 0; i < sc->sc_maxslots; i++) { 1046 struct xhci_slot *xs = &sc->sc_slots[i]; 1047 1048 /* Skip if the slot is not in use. */ 1049 if (xs->xs_idx == 0) 1050 continue; 1051 1052 for (dci = 0; dci < 32; dci++) { 1053 /* Skip if the endpoint is not Running. */ 1054 if (xhci_get_epstate(sc, xs, dci) != 1055 XHCI_EPSTATE_RUNNING) 1056 continue; 1057 1058 /* Ring the doorbell. */ 1059 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 1060 } 1061 } 1062 1063 /* 1064 * `Note: After a Save or Restore operation completes, the 1065 * Save/Restore Error (SRE) flag in the USBSTS register should 1066 * be checked to ensure that the operation completed 1067 * successfully.' 1068 */ 1069 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 1070 device_printf(self, "resume error, USBSTS.SRE\n"); 1071 goto out; 1072 } 1073 1074 /* Resume command issuance. */ 1075 sc->sc_suspender = NULL; 1076 cv_broadcast(&sc->sc_cmdbusy_cv); 1077 1078 /* Success! */ 1079 ok = true; 1080 1081 out: mutex_exit(&sc->sc_lock); 1082 return ok; 1083 } 1084 1085 bool 1086 xhci_shutdown(device_t self, int flags) 1087 { 1088 return false; 1089 } 1090 1091 static int 1092 xhci_hc_reset(struct xhci_softc * const sc) 1093 { 1094 uint32_t usbcmd, usbsts; 1095 int i; 1096 1097 /* Check controller not ready */ 1098 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1099 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1100 if ((usbsts & XHCI_STS_CNR) == 0) 1101 break; 1102 usb_delay_ms(&sc->sc_bus, 1); 1103 } 1104 if (i >= XHCI_WAIT_CNR) { 1105 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 1106 return EIO; 1107 } 1108 1109 /* Halt controller */ 1110 usbcmd = 0; 1111 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1112 usb_delay_ms(&sc->sc_bus, 1); 1113 1114 /* Reset controller */ 1115 usbcmd = XHCI_CMD_HCRST; 1116 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1117 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 1118 /* 1119 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 1120 * prevent system hang (Errata). 1121 */ 1122 usb_delay_ms(&sc->sc_bus, 1); 1123 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 1124 if ((usbcmd & XHCI_CMD_HCRST) == 0) 1125 break; 1126 } 1127 if (i >= XHCI_WAIT_HCRST) { 1128 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 1129 return EIO; 1130 } 1131 1132 /* Check controller not ready */ 1133 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1134 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1135 if ((usbsts & XHCI_STS_CNR) == 0) 1136 break; 1137 usb_delay_ms(&sc->sc_bus, 1); 1138 } 1139 if (i >= XHCI_WAIT_CNR) { 1140 aprint_error_dev(sc->sc_dev, 1141 "controller not ready timeout after reset\n"); 1142 return EIO; 1143 } 1144 1145 return 0; 1146 } 1147 1148 /* 7.2 xHCI Support Protocol Capability */ 1149 static void 1150 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 1151 { 1152 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1153 1154 /* XXX Cache this lot */ 1155 1156 const uint32_t w0 = xhci_read_4(sc, ecp); 1157 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 1158 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 1159 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 1160 1161 aprint_debug_dev(sc->sc_dev, 1162 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 1163 1164 if (w4 != XHCI_XECP_USBID) 1165 return; 1166 1167 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 1168 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 1169 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 1170 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 1171 1172 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 1173 switch (mm) { 1174 case 0x0200: 1175 case 0x0300: 1176 case 0x0301: 1177 case 0x0310: 1178 case 0x0320: 1179 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 1180 major == 3 ? "ss" : "hs", cpo, cpo + cpc - 1); 1181 if (major == 3) 1182 sc->sc_usb3nports += cpo + cpc - 1; 1183 else 1184 sc->sc_usb2nports += cpo + cpc - 1; 1185 break; 1186 default: 1187 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 1188 major, minor); 1189 return; 1190 } 1191 1192 const size_t bus = (major == 3) ? 0 : 1; 1193 1194 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 1195 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 1196 if (sc->sc_ctlrportmap[cp] != 0) { 1197 aprint_error_dev(sc->sc_dev, "controller port %zu " 1198 "already assigned", cp); 1199 continue; 1200 } 1201 1202 sc->sc_ctlrportbus[cp / NBBY] |= 1203 bus == 0 ? 0 : __BIT(cp % NBBY); 1204 1205 const size_t rhp = sc->sc_rhportcount[bus]++; 1206 1207 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 1208 "bus %zu rhp %zu is %d", bus, rhp, 1209 sc->sc_rhportmap[bus][rhp]); 1210 1211 sc->sc_rhportmap[bus][rhp] = cp + 1; 1212 sc->sc_ctlrportmap[cp] = rhp + 1; 1213 } 1214 } 1215 1216 /* Process extended capabilities */ 1217 static void 1218 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 1219 { 1220 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1221 1222 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 1223 while (ecp != 0) { 1224 uint32_t ecr = xhci_read_4(sc, ecp); 1225 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 1226 switch (XHCI_XECP_ID(ecr)) { 1227 case XHCI_ID_PROTOCOLS: { 1228 xhci_id_protocols(sc, ecp); 1229 break; 1230 } 1231 case XHCI_ID_USB_LEGACY: { 1232 uint8_t bios_sem; 1233 1234 /* Take host controller ownership from BIOS */ 1235 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 1236 if (bios_sem) { 1237 /* sets xHCI to be owned by OS */ 1238 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 1239 aprint_debug_dev(sc->sc_dev, 1240 "waiting for BIOS to give up control\n"); 1241 for (int i = 0; i < 5000; i++) { 1242 bios_sem = xhci_read_1(sc, ecp + 1243 XHCI_XECP_BIOS_SEM); 1244 if (bios_sem == 0) 1245 break; 1246 DELAY(1000); 1247 } 1248 if (bios_sem) { 1249 aprint_error_dev(sc->sc_dev, 1250 "timed out waiting for BIOS\n"); 1251 } 1252 } 1253 break; 1254 } 1255 default: 1256 break; 1257 } 1258 ecr = xhci_read_4(sc, ecp); 1259 if (XHCI_XECP_NEXT(ecr) == 0) { 1260 ecp = 0; 1261 } else { 1262 ecp += XHCI_XECP_NEXT(ecr) * 4; 1263 } 1264 } 1265 } 1266 1267 #define XHCI_HCCPREV1_BITS \ 1268 "\177\020" /* New bitmask */ \ 1269 "f\020\020XECP\0" \ 1270 "f\014\4MAXPSA\0" \ 1271 "b\013CFC\0" \ 1272 "b\012SEC\0" \ 1273 "b\011SBD\0" \ 1274 "b\010FSE\0" \ 1275 "b\7NSS\0" \ 1276 "b\6LTC\0" \ 1277 "b\5LHRC\0" \ 1278 "b\4PIND\0" \ 1279 "b\3PPC\0" \ 1280 "b\2CZC\0" \ 1281 "b\1BNC\0" \ 1282 "b\0AC64\0" \ 1283 "\0" 1284 #define XHCI_HCCV1_x_BITS \ 1285 "\177\020" /* New bitmask */ \ 1286 "f\020\020XECP\0" \ 1287 "f\014\4MAXPSA\0" \ 1288 "b\013CFC\0" \ 1289 "b\012SEC\0" \ 1290 "b\011SPC\0" \ 1291 "b\010PAE\0" \ 1292 "b\7NSS\0" \ 1293 "b\6LTC\0" \ 1294 "b\5LHRC\0" \ 1295 "b\4PIND\0" \ 1296 "b\3PPC\0" \ 1297 "b\2CSZ\0" \ 1298 "b\1BNC\0" \ 1299 "b\0AC64\0" \ 1300 "\0" 1301 1302 #define XHCI_HCC2_BITS \ 1303 "\177\020" /* New bitmask */ \ 1304 "b\7ETC_TSC\0" \ 1305 "b\6ETC\0" \ 1306 "b\5CIC\0" \ 1307 "b\4LEC\0" \ 1308 "b\3CTC\0" \ 1309 "b\2FSC\0" \ 1310 "b\1CMC\0" \ 1311 "b\0U3C\0" \ 1312 "\0" 1313 1314 void 1315 xhci_start(struct xhci_softc *sc) 1316 { 1317 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1318 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1319 /* Intel xhci needs interrupt rate moderated. */ 1320 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1321 else 1322 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1323 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1324 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1325 1326 /* Go! */ 1327 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 1328 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1329 xhci_op_read_4(sc, XHCI_USBCMD)); 1330 } 1331 1332 int 1333 xhci_init(struct xhci_softc *sc) 1334 { 1335 bus_size_t bsz; 1336 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff, hcc2; 1337 uint32_t pagesize, config; 1338 int i = 0; 1339 uint16_t hciversion; 1340 uint8_t caplength; 1341 1342 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1343 1344 /* Set up the bus struct for the usb 3 and usb 2 buses */ 1345 sc->sc_bus.ub_methods = &xhci_bus_methods; 1346 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1347 sc->sc_bus.ub_usedma = true; 1348 sc->sc_bus.ub_hcpriv = sc; 1349 1350 sc->sc_bus2.ub_methods = &xhci_bus_methods; 1351 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 1352 sc->sc_bus2.ub_revision = USBREV_2_0; 1353 sc->sc_bus2.ub_usedma = true; 1354 sc->sc_bus2.ub_hcpriv = sc; 1355 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 1356 1357 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 1358 caplength = XHCI_CAP_CAPLENGTH(cap); 1359 hciversion = XHCI_CAP_HCIVERSION(cap); 1360 1361 if (hciversion < XHCI_HCIVERSION_0_96 || 1362 hciversion >= 0x0200) { 1363 aprint_normal_dev(sc->sc_dev, 1364 "xHCI version %x.%x not known to be supported\n", 1365 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1366 } else { 1367 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 1368 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1369 } 1370 1371 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 1372 &sc->sc_cbh) != 0) { 1373 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 1374 return ENOMEM; 1375 } 1376 1377 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 1378 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 1379 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 1380 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 1381 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 1382 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 1383 aprint_debug_dev(sc->sc_dev, 1384 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 1385 1386 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 1387 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 1388 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 1389 1390 char sbuf[128]; 1391 if (hciversion < XHCI_HCIVERSION_1_0) 1392 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 1393 else 1394 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 1395 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 1396 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 1397 if (hciversion >= XHCI_HCIVERSION_1_1) { 1398 hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 1399 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, hcc2); 1400 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 1401 } 1402 1403 /* default all ports to bus 0, i.e. usb 3 */ 1404 sc->sc_ctlrportbus = kmem_zalloc( 1405 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 1406 sc->sc_ctlrportmap = 1407 kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1408 1409 /* controller port to bus roothub port map */ 1410 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 1411 sc->sc_rhportmap[j] = 1412 kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1413 } 1414 1415 /* 1416 * Process all Extended Capabilities 1417 */ 1418 xhci_ecp(sc, hcc); 1419 1420 bsz = XHCI_PORTSC(sc->sc_maxports); 1421 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1422 &sc->sc_obh) != 0) { 1423 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1424 return ENOMEM; 1425 } 1426 1427 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1428 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1429 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1430 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1431 return ENOMEM; 1432 } 1433 1434 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1435 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1436 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1437 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1438 return ENOMEM; 1439 } 1440 1441 int rv; 1442 rv = xhci_hc_reset(sc); 1443 if (rv != 0) { 1444 return rv; 1445 } 1446 1447 if (sc->sc_vendor_init) 1448 sc->sc_vendor_init(sc); 1449 1450 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1451 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1452 pagesize = ffs(pagesize); 1453 if (pagesize == 0) { 1454 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1455 return EIO; 1456 } 1457 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1458 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1459 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1460 (uint32_t)sc->sc_maxslots); 1461 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1462 1463 usbd_status err; 1464 1465 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1466 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1467 if (sc->sc_maxspbuf != 0) { 1468 err = usb_allocmem(&sc->sc_bus, 1469 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1470 &sc->sc_spbufarray_dma); 1471 if (err) { 1472 aprint_error_dev(sc->sc_dev, 1473 "spbufarray init fail, err %d\n", err); 1474 return ENOMEM; 1475 } 1476 1477 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1478 sc->sc_maxspbuf, KM_SLEEP); 1479 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1480 for (i = 0; i < sc->sc_maxspbuf; i++) { 1481 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1482 /* allocate contexts */ 1483 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1484 sc->sc_pgsz, dma); 1485 if (err) { 1486 aprint_error_dev(sc->sc_dev, 1487 "spbufarray_dma init fail, err %d\n", err); 1488 rv = ENOMEM; 1489 goto bad1; 1490 } 1491 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1492 usb_syncmem(dma, 0, sc->sc_pgsz, 1493 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1494 } 1495 1496 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1497 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1498 } 1499 1500 config = xhci_op_read_4(sc, XHCI_CONFIG); 1501 config &= ~0xFF; 1502 config |= sc->sc_maxslots & 0xFF; 1503 xhci_op_write_4(sc, XHCI_CONFIG, config); 1504 1505 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1506 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1507 if (err) { 1508 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1509 err); 1510 rv = ENOMEM; 1511 goto bad1; 1512 } 1513 1514 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1515 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1516 if (err) { 1517 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1518 err); 1519 rv = ENOMEM; 1520 goto bad2; 1521 } 1522 1523 usb_dma_t *dma; 1524 size_t size; 1525 size_t align; 1526 1527 dma = &sc->sc_eventst_dma; 1528 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1529 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1530 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1531 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1532 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1533 if (err) { 1534 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1535 err); 1536 rv = ENOMEM; 1537 goto bad3; 1538 } 1539 1540 memset(KERNADDR(dma, 0), 0, size); 1541 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1542 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1543 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1544 KERNADDR(&sc->sc_eventst_dma, 0), 1545 sc->sc_eventst_dma.udma_block->size); 1546 1547 dma = &sc->sc_dcbaa_dma; 1548 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1549 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1550 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1551 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1552 if (err) { 1553 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1554 rv = ENOMEM; 1555 goto bad4; 1556 } 1557 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1558 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1559 KERNADDR(&sc->sc_dcbaa_dma, 0), 1560 sc->sc_dcbaa_dma.udma_block->size); 1561 1562 memset(KERNADDR(dma, 0), 0, size); 1563 if (sc->sc_maxspbuf != 0) { 1564 /* 1565 * DCBA entry 0 hold the scratchbuf array pointer. 1566 */ 1567 *(uint64_t *)KERNADDR(dma, 0) = 1568 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1569 } 1570 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1571 1572 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1573 KM_SLEEP); 1574 if (sc->sc_slots == NULL) { 1575 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1576 rv = ENOMEM; 1577 goto bad; 1578 } 1579 1580 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1581 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1582 if (sc->sc_xferpool == NULL) { 1583 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1584 err); 1585 rv = ENOMEM; 1586 goto bad; 1587 } 1588 1589 cv_init(&sc->sc_command_cv, "xhcicmd"); 1590 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1591 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1592 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1593 1594 struct xhci_erste *erst; 1595 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1596 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1597 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1598 erst[0].erste_3 = htole32(0); 1599 usb_syncmem(&sc->sc_eventst_dma, 0, 1600 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1601 1602 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1603 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1604 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1605 XHCI_ERDP_LO_BUSY); 1606 1607 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1608 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1609 sc->sc_cr.xr_cs); 1610 1611 xhci_op_barrier(sc, 0, 4, BUS_SPACE_BARRIER_WRITE); 1612 1613 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1614 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1615 1616 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1617 xhci_start(sc); 1618 1619 return 0; 1620 1621 bad: 1622 if (sc->sc_xferpool) { 1623 pool_cache_destroy(sc->sc_xferpool); 1624 sc->sc_xferpool = NULL; 1625 } 1626 1627 if (sc->sc_slots) { 1628 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1629 sc->sc_maxslots); 1630 sc->sc_slots = NULL; 1631 } 1632 1633 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1634 bad4: 1635 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1636 bad3: 1637 xhci_ring_free(sc, &sc->sc_er); 1638 bad2: 1639 xhci_ring_free(sc, &sc->sc_cr); 1640 i = sc->sc_maxspbuf; 1641 bad1: 1642 for (int j = 0; j < i; j++) 1643 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1644 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1645 1646 return rv; 1647 } 1648 1649 static inline bool 1650 xhci_polling_p(struct xhci_softc * const sc) 1651 { 1652 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1653 } 1654 1655 int 1656 xhci_intr(void *v) 1657 { 1658 struct xhci_softc * const sc = v; 1659 int ret = 0; 1660 1661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1662 1663 if (sc == NULL) 1664 return 0; 1665 1666 mutex_spin_enter(&sc->sc_intr_lock); 1667 1668 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1669 goto done; 1670 1671 /* If we get an interrupt while polling, then just ignore it. */ 1672 if (xhci_polling_p(sc)) { 1673 #ifdef DIAGNOSTIC 1674 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1675 #endif 1676 goto done; 1677 } 1678 1679 ret = xhci_intr1(sc); 1680 if (ret) { 1681 KASSERT(sc->sc_child || sc->sc_child2); 1682 1683 /* 1684 * One of child busses could be already detached. It doesn't 1685 * matter on which of the two the softintr is scheduled. 1686 */ 1687 if (sc->sc_child) 1688 usb_schedsoftintr(&sc->sc_bus); 1689 else 1690 usb_schedsoftintr(&sc->sc_bus2); 1691 } 1692 done: 1693 mutex_spin_exit(&sc->sc_intr_lock); 1694 return ret; 1695 } 1696 1697 int 1698 xhci_intr1(struct xhci_softc * const sc) 1699 { 1700 uint32_t usbsts; 1701 uint32_t iman; 1702 1703 XHCIHIST_FUNC(); 1704 1705 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1706 XHCIHIST_CALLARGS("USBSTS %08jx", usbsts, 0, 0, 0); 1707 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1708 XHCI_STS_HCE)) == 0) { 1709 DPRINTFN(16, "ignored intr not for %s", 1710 (uintptr_t)device_xname(sc->sc_dev), 0, 0, 0); 1711 return 0; 1712 } 1713 1714 /* 1715 * Clear EINT and other transient flags, to not misenterpret 1716 * next shared interrupt. Also, to avoid race, EINT must be cleared 1717 * before XHCI_IMAN_INTR_PEND is cleared. 1718 */ 1719 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1720 1721 #ifdef XHCI_DEBUG 1722 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1723 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1724 #endif 1725 1726 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1727 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1728 iman |= XHCI_IMAN_INTR_PEND; 1729 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1730 1731 #ifdef XHCI_DEBUG 1732 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1733 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1734 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1735 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1736 #endif 1737 1738 return 1; 1739 } 1740 1741 /* 1742 * 3 port speed types used in USB stack 1743 * 1744 * usbdi speed 1745 * definition: USB_SPEED_* in usb.h 1746 * They are used in struct usbd_device in USB stack. 1747 * ioctl interface uses these values too. 1748 * port_status speed 1749 * definition: UPS_*_SPEED in usb.h 1750 * They are used in usb_port_status_t and valid only for USB 2.0. 1751 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1752 * of usb_port_status_ext_t indicates port speed. 1753 * Note that some 3.0 values overlap with 2.0 values. 1754 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1755 * means UPS_LOW_SPEED in HS.) 1756 * port status returned from hub also uses these values. 1757 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1758 * or more. 1759 * xspeed: 1760 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1761 * They are used in only slot context and PORTSC reg of xhci. 1762 * The difference between usbdi speed and xspeed is 1763 * that FS and LS values are swapped. 1764 */ 1765 1766 /* convert usbdi speed to xspeed */ 1767 static int 1768 xhci_speed2xspeed(int speed) 1769 { 1770 switch (speed) { 1771 case USB_SPEED_LOW: return 2; 1772 case USB_SPEED_FULL: return 1; 1773 default: return speed; 1774 } 1775 } 1776 1777 #if 0 1778 /* convert xspeed to usbdi speed */ 1779 static int 1780 xhci_xspeed2speed(int xspeed) 1781 { 1782 switch (xspeed) { 1783 case 1: return USB_SPEED_FULL; 1784 case 2: return USB_SPEED_LOW; 1785 default: return xspeed; 1786 } 1787 } 1788 #endif 1789 1790 /* convert xspeed to port status speed */ 1791 static int 1792 xhci_xspeed2psspeed(int xspeed) 1793 { 1794 switch (xspeed) { 1795 case 0: return 0; 1796 case 1: return UPS_FULL_SPEED; 1797 case 2: return UPS_LOW_SPEED; 1798 case 3: return UPS_HIGH_SPEED; 1799 default: return UPS_OTHER_SPEED; 1800 } 1801 } 1802 1803 /* 1804 * Construct input contexts and issue TRB to open pipe. 1805 */ 1806 static usbd_status 1807 xhci_configure_endpoint(struct usbd_pipe *pipe) 1808 { 1809 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1810 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1811 #ifdef USB_DEBUG 1812 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1813 #endif 1814 struct xhci_soft_trb trb; 1815 usbd_status err; 1816 1817 XHCIHIST_FUNC(); 1818 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1819 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1820 pipe->up_endpoint->ue_edesc->bmAttributes); 1821 1822 /* XXX ensure input context is available? */ 1823 1824 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1825 1826 /* set up context */ 1827 xhci_setup_ctx(pipe); 1828 1829 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1830 sc->sc_ctxsz * 1); 1831 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1832 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1833 1834 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1835 trb.trb_2 = 0; 1836 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1837 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1838 1839 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1840 1841 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1842 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1843 sc->sc_ctxsz * 1); 1844 1845 return err; 1846 } 1847 1848 #if 0 1849 static usbd_status 1850 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1851 { 1852 #ifdef USB_DEBUG 1853 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1854 #endif 1855 1856 XHCIHIST_FUNC(); 1857 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 1858 1859 return USBD_NORMAL_COMPLETION; 1860 } 1861 #endif 1862 1863 /* 4.6.8, 6.4.3.7 */ 1864 static usbd_status 1865 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1866 { 1867 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1868 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1869 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1870 struct xhci_soft_trb trb; 1871 usbd_status err; 1872 1873 XHCIHIST_FUNC(); 1874 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1875 1876 KASSERT(mutex_owned(&sc->sc_lock)); 1877 1878 trb.trb_0 = 0; 1879 trb.trb_2 = 0; 1880 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1881 XHCI_TRB_3_EP_SET(dci) | 1882 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1883 1884 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1885 1886 return err; 1887 } 1888 1889 static usbd_status 1890 xhci_reset_endpoint(struct usbd_pipe *pipe) 1891 { 1892 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1893 1894 mutex_enter(&sc->sc_lock); 1895 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1896 mutex_exit(&sc->sc_lock); 1897 1898 return ret; 1899 } 1900 1901 /* 1902 * 4.6.9, 6.4.3.8 1903 * Stop execution of TDs on xfer ring. 1904 * Should be called with sc_lock held. 1905 */ 1906 static usbd_status 1907 xhci_stop_endpoint_cmd(struct xhci_softc *sc, struct xhci_slot *xs, u_int dci, 1908 uint32_t trb3flags) 1909 { 1910 struct xhci_soft_trb trb; 1911 usbd_status err; 1912 1913 XHCIHIST_FUNC(); 1914 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1915 1916 KASSERT(mutex_owned(&sc->sc_lock)); 1917 1918 trb.trb_0 = 0; 1919 trb.trb_2 = 0; 1920 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1921 XHCI_TRB_3_EP_SET(dci) | 1922 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1923 trb3flags; 1924 1925 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1926 1927 return err; 1928 } 1929 1930 static usbd_status 1931 xhci_stop_endpoint(struct usbd_pipe *pipe) 1932 { 1933 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1934 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1935 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1936 1937 XHCIHIST_FUNC(); 1938 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1939 1940 KASSERT(mutex_owned(&sc->sc_lock)); 1941 1942 return xhci_stop_endpoint_cmd(sc, xs, dci, 0); 1943 } 1944 1945 /* 1946 * Set TR Dequeue Pointer. 1947 * xHCI 1.1 4.6.10 6.4.3.9 1948 * Purge all of the TRBs on ring and reinitialize ring. 1949 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1950 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1951 * error will be generated. 1952 */ 1953 static usbd_status 1954 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1955 { 1956 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1957 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1958 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1959 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1960 struct xhci_soft_trb trb; 1961 usbd_status err; 1962 1963 XHCIHIST_FUNC(); 1964 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1965 1966 KASSERT(mutex_owned(&sc->sc_lock)); 1967 1968 xhci_host_dequeue(xr); 1969 1970 /* set DCS */ 1971 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1972 trb.trb_2 = 0; 1973 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1974 XHCI_TRB_3_EP_SET(dci) | 1975 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1976 1977 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1978 1979 return err; 1980 } 1981 1982 static usbd_status 1983 xhci_set_dequeue(struct usbd_pipe *pipe) 1984 { 1985 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1986 1987 mutex_enter(&sc->sc_lock); 1988 usbd_status ret = xhci_set_dequeue_locked(pipe); 1989 mutex_exit(&sc->sc_lock); 1990 1991 return ret; 1992 } 1993 1994 /* 1995 * Open new pipe: called from usbd_setup_pipe_flags. 1996 * Fills methods of pipe. 1997 * If pipe is not for ep0, calls configure_endpoint. 1998 */ 1999 static usbd_status 2000 xhci_open(struct usbd_pipe *pipe) 2001 { 2002 struct usbd_device * const dev = pipe->up_dev; 2003 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2004 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2005 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2006 2007 XHCIHIST_FUNC(); 2008 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 2009 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 2010 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 2011 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 2012 ed->bmAttributes); 2013 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 2014 ed->bInterval, 0, 0); 2015 2016 if (sc->sc_dying) 2017 return USBD_IOERROR; 2018 2019 /* Root Hub */ 2020 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 2021 switch (ed->bEndpointAddress) { 2022 case USB_CONTROL_ENDPOINT: 2023 pipe->up_methods = &roothub_ctrl_methods; 2024 break; 2025 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2026 pipe->up_methods = &xhci_root_intr_methods; 2027 break; 2028 default: 2029 pipe->up_methods = NULL; 2030 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 2031 ed->bEndpointAddress, 0, 0, 0); 2032 return USBD_INVAL; 2033 } 2034 return USBD_NORMAL_COMPLETION; 2035 } 2036 2037 switch (xfertype) { 2038 case UE_CONTROL: 2039 pipe->up_methods = &xhci_device_ctrl_methods; 2040 break; 2041 case UE_ISOCHRONOUS: 2042 pipe->up_methods = &xhci_device_isoc_methods; 2043 return USBD_INVAL; 2044 break; 2045 case UE_BULK: 2046 pipe->up_methods = &xhci_device_bulk_methods; 2047 break; 2048 case UE_INTERRUPT: 2049 pipe->up_methods = &xhci_device_intr_methods; 2050 break; 2051 default: 2052 return USBD_IOERROR; 2053 break; 2054 } 2055 2056 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 2057 return xhci_configure_endpoint(pipe); 2058 2059 return USBD_NORMAL_COMPLETION; 2060 } 2061 2062 /* 2063 * Closes pipe, called from usbd_kill_pipe via close methods. 2064 * If the endpoint to be closed is ep0, disable_slot. 2065 * Should be called with sc_lock held. 2066 */ 2067 static void 2068 xhci_close_pipe(struct usbd_pipe *pipe) 2069 { 2070 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2071 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2072 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2073 const u_int dci = xhci_ep_get_dci(ed); 2074 struct xhci_soft_trb trb; 2075 uint32_t *cp; 2076 2077 XHCIHIST_FUNC(); 2078 2079 if (sc->sc_dying) 2080 return; 2081 2082 /* xs is uninitialized before xhci_init_slot */ 2083 if (xs == NULL || xs->xs_idx == 0) 2084 return; 2085 2086 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 2087 (uintptr_t)pipe, xs->xs_idx, dci, 0); 2088 2089 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2090 KASSERT(mutex_owned(&sc->sc_lock)); 2091 2092 if (pipe->up_dev->ud_depth == 0) 2093 return; 2094 2095 if (dci == XHCI_DCI_EP_CONTROL) { 2096 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 2097 xhci_disable_slot(sc, xs->xs_idx); 2098 return; 2099 } 2100 2101 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 2102 (void)xhci_stop_endpoint(pipe); 2103 2104 /* 2105 * set appropriate bit to be dropped. 2106 * don't set DC bit to 1, otherwise all endpoints 2107 * would be deconfigured. 2108 */ 2109 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2110 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 2111 cp[1] = htole32(0); 2112 2113 /* XXX should be most significant one, not dci? */ 2114 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2115 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 2116 2117 /* configure ep context performs an implicit dequeue */ 2118 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 2119 2120 /* sync input contexts before they are read from memory */ 2121 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2122 2123 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2124 trb.trb_2 = 0; 2125 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2126 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 2127 2128 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2129 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2130 } 2131 2132 /* 2133 * Abort transfer. 2134 * Should be called with sc_lock held. 2135 */ 2136 static void 2137 xhci_abortx(struct usbd_xfer *xfer) 2138 { 2139 XHCIHIST_FUNC(); 2140 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2141 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2142 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2143 2144 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx", 2145 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0); 2146 2147 KASSERT(mutex_owned(&sc->sc_lock)); 2148 ASSERT_SLEEPABLE(); 2149 2150 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2151 xfer->ux_status == USBD_TIMEOUT), 2152 "bad abort status: %d", xfer->ux_status); 2153 2154 /* 2155 * If we're dying, skip the hardware action and just notify the 2156 * software that we're done. 2157 */ 2158 if (sc->sc_dying) { 2159 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2160 xfer->ux_status, 0, 0); 2161 goto dying; 2162 } 2163 2164 /* 2165 * HC Step 1: Stop execution of TD on the ring. 2166 */ 2167 switch (xhci_get_epstate(sc, xs, dci)) { 2168 case XHCI_EPSTATE_HALTED: 2169 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 2170 break; 2171 case XHCI_EPSTATE_STOPPED: 2172 break; 2173 default: 2174 (void)xhci_stop_endpoint(xfer->ux_pipe); 2175 break; 2176 } 2177 #ifdef DIAGNOSTIC 2178 uint32_t epst = xhci_get_epstate(sc, xs, dci); 2179 if (epst != XHCI_EPSTATE_STOPPED) 2180 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 2181 #endif 2182 2183 /* 2184 * HC Step 2: Remove any vestiges of the xfer from the ring. 2185 */ 2186 xhci_set_dequeue_locked(xfer->ux_pipe); 2187 2188 /* 2189 * Final Step: Notify completion to waiting xfers. 2190 */ 2191 dying: 2192 usb_transfer_complete(xfer); 2193 DPRINTFN(14, "end", 0, 0, 0, 0); 2194 2195 KASSERT(mutex_owned(&sc->sc_lock)); 2196 } 2197 2198 static void 2199 xhci_host_dequeue(struct xhci_ring * const xr) 2200 { 2201 /* When dequeueing the controller, update our struct copy too */ 2202 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 2203 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 2204 BUS_DMASYNC_PREWRITE); 2205 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 2206 2207 xr->xr_ep = 0; 2208 xr->xr_cs = 1; 2209 } 2210 2211 /* 2212 * Recover STALLed endpoint. 2213 * xHCI 1.1 sect 4.10.2.1 2214 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 2215 * all transfers on transfer ring. 2216 * These are done in thread context asynchronously. 2217 */ 2218 static void 2219 xhci_clear_endpoint_stall_async_task(void *cookie) 2220 { 2221 struct usbd_xfer * const xfer = cookie; 2222 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2223 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2224 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2225 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2226 2227 XHCIHIST_FUNC(); 2228 XHCIHIST_CALLARGS("xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 2229 dci, 0); 2230 2231 /* 2232 * XXXMRG: Stall task can run after slot is disabled when yanked. 2233 * This hack notices that the xs has been memset() in 2234 * xhci_disable_slot() and returns. Both xhci_reset_endpoint() 2235 * and xhci_set_dequeue() rely upon a valid ring setup for correct 2236 * operation, and the latter will fault, as would 2237 * usb_transfer_complete() if it got that far. 2238 */ 2239 if (xs->xs_idx == 0) { 2240 DPRINTFN(4, "ends xs_idx is 0", 0, 0, 0, 0); 2241 return; 2242 } 2243 2244 xhci_reset_endpoint(xfer->ux_pipe); 2245 xhci_set_dequeue(xfer->ux_pipe); 2246 2247 mutex_enter(&sc->sc_lock); 2248 tr->is_halted = false; 2249 usb_transfer_complete(xfer); 2250 mutex_exit(&sc->sc_lock); 2251 DPRINTFN(4, "ends", 0, 0, 0, 0); 2252 } 2253 2254 static usbd_status 2255 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 2256 { 2257 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2258 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 2259 2260 XHCIHIST_FUNC(); 2261 XHCIHIST_CALLARGS("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 2262 2263 if (sc->sc_dying) { 2264 return USBD_IOERROR; 2265 } 2266 2267 usb_init_task(&xp->xp_async_task, 2268 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 2269 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 2270 DPRINTFN(4, "ends", 0, 0, 0, 0); 2271 2272 return USBD_NORMAL_COMPLETION; 2273 } 2274 2275 /* Process roothub port status/change events and notify to uhub_intr. */ 2276 static void 2277 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 2278 { 2279 XHCIHIST_FUNC(); 2280 XHCIHIST_CALLARGS("xhci%jd: port %ju status change", 2281 device_unit(sc->sc_dev), ctlrport, 0, 0); 2282 2283 if (ctlrport > sc->sc_maxports) 2284 return; 2285 2286 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 2287 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 2288 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 2289 2290 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 2291 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 2292 2293 if (xfer == NULL) 2294 return; 2295 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2296 2297 uint8_t *p = xfer->ux_buf; 2298 memset(p, 0, xfer->ux_length); 2299 p[rhp / NBBY] |= 1 << (rhp % NBBY); 2300 xfer->ux_actlen = xfer->ux_length; 2301 xfer->ux_status = USBD_NORMAL_COMPLETION; 2302 usb_transfer_complete(xfer); 2303 } 2304 2305 /* Process Transfer Events */ 2306 static void 2307 xhci_event_transfer(struct xhci_softc * const sc, 2308 const struct xhci_trb * const trb) 2309 { 2310 uint64_t trb_0; 2311 uint32_t trb_2, trb_3; 2312 uint8_t trbcode; 2313 u_int slot, dci; 2314 struct xhci_slot *xs; 2315 struct xhci_ring *xr; 2316 struct xhci_xfer *xx; 2317 struct usbd_xfer *xfer; 2318 usbd_status err; 2319 2320 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2321 2322 trb_0 = le64toh(trb->trb_0); 2323 trb_2 = le32toh(trb->trb_2); 2324 trb_3 = le32toh(trb->trb_3); 2325 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 2326 slot = XHCI_TRB_3_SLOT_GET(trb_3); 2327 dci = XHCI_TRB_3_EP_GET(trb_3); 2328 xs = &sc->sc_slots[slot]; 2329 xr = &xs->xs_ep[dci].xe_tr; 2330 2331 /* sanity check */ 2332 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 2333 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 2334 2335 int idx = 0; 2336 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2337 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 2338 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 2339 return; 2340 } 2341 xx = xr->xr_cookies[idx]; 2342 2343 /* clear cookie of consumed TRB */ 2344 xr->xr_cookies[idx] = NULL; 2345 2346 /* 2347 * xx is NULL if pipe is opened but xfer is not started. 2348 * It happens when stopping idle pipe. 2349 */ 2350 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 2351 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 2352 idx, (uintptr_t)xx, trbcode, dci); 2353 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 2354 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 2355 0, 0); 2356 return; 2357 } 2358 } else { 2359 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 2360 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 2361 } 2362 /* XXX this may not happen */ 2363 if (xx == NULL) { 2364 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 2365 return; 2366 } 2367 xfer = &xx->xx_xfer; 2368 /* XXX this may happen when detaching */ 2369 if (xfer == NULL) { 2370 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 2371 (uintptr_t)xx, trb_0, 0, 0); 2372 return; 2373 } 2374 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 2375 /* XXX I dunno why this happens */ 2376 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 2377 2378 if (!xfer->ux_pipe->up_repeat && 2379 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 2380 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 2381 0, 0, 0); 2382 return; 2383 } 2384 2385 /* 4.11.5.2 Event Data TRB */ 2386 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2387 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 2388 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 2389 if ((trb_0 & 0x3) == 0x3) { 2390 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 2391 } 2392 } 2393 2394 switch (trbcode) { 2395 case XHCI_TRB_ERROR_SHORT_PKT: 2396 case XHCI_TRB_ERROR_SUCCESS: 2397 /* 2398 * A ctrl transfer can generate two events if it has a Data 2399 * stage. A short data stage can be OK and should not 2400 * complete the transfer as the status stage needs to be 2401 * performed. 2402 * 2403 * Note: Data and Status stage events point at same xfer. 2404 * ux_actlen and ux_dmabuf will be passed to 2405 * usb_transfer_complete after the Status stage event. 2406 * 2407 * It can be distingished which stage generates the event: 2408 * + by checking least 3 bits of trb_0 if ED==1. 2409 * (see xhci_device_ctrl_start). 2410 * + by checking the type of original TRB if ED==0. 2411 * 2412 * In addition, intr, bulk, and isoc transfer currently 2413 * consists of single TD, so the "skip" is not needed. 2414 * ctrl xfer uses EVENT_DATA, and others do not. 2415 * Thus driver can switch the flow by checking ED bit. 2416 */ 2417 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2418 if (xfer->ux_actlen == 0) 2419 xfer->ux_actlen = xfer->ux_length - 2420 XHCI_TRB_2_REM_GET(trb_2); 2421 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 2422 == XHCI_TRB_TYPE_DATA_STAGE) { 2423 return; 2424 } 2425 } else if ((trb_0 & 0x3) == 0x3) { 2426 return; 2427 } 2428 err = USBD_NORMAL_COMPLETION; 2429 break; 2430 case XHCI_TRB_ERROR_STOPPED: 2431 case XHCI_TRB_ERROR_LENGTH: 2432 case XHCI_TRB_ERROR_STOPPED_SHORT: 2433 err = USBD_IOERROR; 2434 break; 2435 case XHCI_TRB_ERROR_STALL: 2436 case XHCI_TRB_ERROR_BABBLE: 2437 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2438 xr->is_halted = true; 2439 /* 2440 * Try to claim this xfer for completion. If it has already 2441 * completed or aborted, drop it on the floor. 2442 */ 2443 if (!usbd_xfer_trycomplete(xfer)) 2444 return; 2445 2446 /* 2447 * Stalled endpoints can be recoverd by issuing 2448 * command TRB TYPE_RESET_EP on xHCI instead of 2449 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2450 * on the endpoint. However, this function may be 2451 * called from softint context (e.g. from umass), 2452 * in that case driver gets KASSERT in cv_timedwait 2453 * in xhci_do_command. 2454 * To avoid this, this runs reset_endpoint and 2455 * usb_transfer_complete in usb task thread 2456 * asynchronously (and then umass issues clear 2457 * UF_ENDPOINT_HALT). 2458 */ 2459 2460 /* Override the status. */ 2461 xfer->ux_status = USBD_STALLED; 2462 2463 xhci_clear_endpoint_stall_async(xfer); 2464 return; 2465 default: 2466 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2467 err = USBD_IOERROR; 2468 break; 2469 } 2470 2471 /* 2472 * Try to claim this xfer for completion. If it has already 2473 * completed or aborted, drop it on the floor. 2474 */ 2475 if (!usbd_xfer_trycomplete(xfer)) 2476 return; 2477 2478 /* Set the status. */ 2479 xfer->ux_status = err; 2480 2481 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2482 (trb_0 & 0x3) == 0x0) { 2483 usb_transfer_complete(xfer); 2484 } 2485 } 2486 2487 /* Process Command complete events */ 2488 static void 2489 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2490 { 2491 uint64_t trb_0; 2492 uint32_t trb_2, trb_3; 2493 2494 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2495 2496 KASSERT(mutex_owned(&sc->sc_lock)); 2497 2498 trb_0 = le64toh(trb->trb_0); 2499 trb_2 = le32toh(trb->trb_2); 2500 trb_3 = le32toh(trb->trb_3); 2501 2502 if (trb_0 == sc->sc_command_addr) { 2503 sc->sc_resultpending = false; 2504 2505 sc->sc_result_trb.trb_0 = trb_0; 2506 sc->sc_result_trb.trb_2 = trb_2; 2507 sc->sc_result_trb.trb_3 = trb_3; 2508 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2509 XHCI_TRB_ERROR_SUCCESS) { 2510 DPRINTFN(1, "command completion " 2511 "failure: 0x%016jx 0x%08jx 0x%08jx", 2512 trb_0, trb_2, trb_3, 0); 2513 } 2514 cv_signal(&sc->sc_command_cv); 2515 } else { 2516 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2517 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2518 } 2519 } 2520 2521 /* 2522 * Process events. 2523 * called from xhci_softintr 2524 */ 2525 static void 2526 xhci_handle_event(struct xhci_softc * const sc, 2527 const struct xhci_trb * const trb) 2528 { 2529 uint64_t trb_0; 2530 uint32_t trb_2, trb_3; 2531 2532 XHCIHIST_FUNC(); 2533 2534 trb_0 = le64toh(trb->trb_0); 2535 trb_2 = le32toh(trb->trb_2); 2536 trb_3 = le32toh(trb->trb_3); 2537 2538 XHCIHIST_CALLARGS("event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2539 (uintptr_t)trb, trb_0, trb_2, trb_3); 2540 2541 /* 2542 * 4.11.3.1, 6.4.2.1 2543 * TRB Pointer is invalid for these completion codes. 2544 */ 2545 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2546 case XHCI_TRB_ERROR_RING_UNDERRUN: 2547 case XHCI_TRB_ERROR_RING_OVERRUN: 2548 case XHCI_TRB_ERROR_VF_RING_FULL: 2549 return; 2550 default: 2551 if (trb_0 == 0) { 2552 return; 2553 } 2554 break; 2555 } 2556 2557 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2558 case XHCI_TRB_EVENT_TRANSFER: 2559 xhci_event_transfer(sc, trb); 2560 break; 2561 case XHCI_TRB_EVENT_CMD_COMPLETE: 2562 xhci_event_cmd(sc, trb); 2563 break; 2564 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2565 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2566 break; 2567 default: 2568 break; 2569 } 2570 } 2571 2572 static void 2573 xhci_softintr(void *v) 2574 { 2575 struct usbd_bus * const bus = v; 2576 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2577 struct xhci_ring * const er = &sc->sc_er; 2578 struct xhci_trb *trb; 2579 int i, j, k; 2580 2581 XHCIHIST_FUNC(); 2582 2583 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2584 2585 i = er->xr_ep; 2586 j = er->xr_cs; 2587 2588 XHCIHIST_CALLARGS("er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2589 2590 while (1) { 2591 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2592 BUS_DMASYNC_POSTREAD); 2593 trb = &er->xr_trb[i]; 2594 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2595 2596 if (j != k) 2597 break; 2598 2599 xhci_handle_event(sc, trb); 2600 2601 i++; 2602 if (i == er->xr_ntrb) { 2603 i = 0; 2604 j ^= 1; 2605 } 2606 } 2607 2608 er->xr_ep = i; 2609 er->xr_cs = j; 2610 2611 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2612 XHCI_ERDP_LO_BUSY); 2613 2614 DPRINTFN(16, "ends", 0, 0, 0, 0); 2615 2616 return; 2617 } 2618 2619 static void 2620 xhci_poll(struct usbd_bus *bus) 2621 { 2622 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2623 2624 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2625 2626 mutex_enter(&sc->sc_intr_lock); 2627 int ret = xhci_intr1(sc); 2628 if (ret) { 2629 xhci_softintr(bus); 2630 } 2631 mutex_exit(&sc->sc_intr_lock); 2632 2633 return; 2634 } 2635 2636 static struct usbd_xfer * 2637 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2638 { 2639 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2640 struct usbd_xfer *xfer; 2641 2642 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2643 2644 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2645 if (xfer != NULL) { 2646 memset(xfer, 0, sizeof(struct xhci_xfer)); 2647 #ifdef DIAGNOSTIC 2648 xfer->ux_state = XFER_BUSY; 2649 #endif 2650 } 2651 2652 return xfer; 2653 } 2654 2655 static void 2656 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2657 { 2658 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2659 2660 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2661 2662 #ifdef DIAGNOSTIC 2663 if (xfer->ux_state != XFER_BUSY && 2664 xfer->ux_status != USBD_NOT_STARTED) { 2665 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2666 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2667 } 2668 xfer->ux_state = XFER_FREE; 2669 #endif 2670 pool_cache_put(sc->sc_xferpool, xfer); 2671 } 2672 2673 static bool 2674 xhci_dying(struct usbd_bus *bus) 2675 { 2676 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2677 2678 return sc->sc_dying; 2679 } 2680 2681 static void 2682 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2683 { 2684 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2685 2686 *lock = &sc->sc_lock; 2687 } 2688 2689 extern uint32_t usb_cookie_no; 2690 2691 /* 2692 * xHCI 4.3 2693 * Called when uhub_explore finds a new device (via usbd_new_device). 2694 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2695 * This function does: 2696 * Allocate and construct dev structure of default endpoint (ep0). 2697 * Allocate and open pipe of ep0. 2698 * Enable slot and initialize slot context. 2699 * Set Address. 2700 * Read initial device descriptor. 2701 * Determine initial MaxPacketSize (mps) by speed. 2702 * Read full device descriptor. 2703 * Register this device. 2704 * Finally state of device transitions ADDRESSED. 2705 */ 2706 static usbd_status 2707 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2708 int speed, int port, struct usbd_port *up) 2709 { 2710 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2711 struct usbd_device *dev; 2712 usbd_status err; 2713 usb_device_descriptor_t *dd; 2714 struct xhci_slot *xs; 2715 uint32_t *cp; 2716 2717 XHCIHIST_FUNC(); 2718 XHCIHIST_CALLARGS("port %ju depth %ju speed %ju up %#jx", 2719 port, depth, speed, (uintptr_t)up); 2720 2721 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2722 dev->ud_bus = bus; 2723 dev->ud_quirks = &usbd_no_quirk; 2724 dev->ud_addr = 0; 2725 dev->ud_ddesc.bMaxPacketSize = 0; 2726 dev->ud_depth = depth; 2727 dev->ud_powersrc = up; 2728 dev->ud_myhub = up->up_parent; 2729 dev->ud_speed = speed; 2730 dev->ud_langid = USBD_NOLANG; 2731 dev->ud_cookie.cookie = ++usb_cookie_no; 2732 2733 /* Set up default endpoint handle. */ 2734 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2735 /* doesn't matter, just don't let it uninitialized */ 2736 dev->ud_ep0.ue_toggle = 0; 2737 2738 /* Set up default endpoint descriptor. */ 2739 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2740 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2741 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2742 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2743 dev->ud_ep0desc.bInterval = 0; 2744 2745 /* 4.3, 4.8.2.1 */ 2746 switch (speed) { 2747 case USB_SPEED_SUPER: 2748 case USB_SPEED_SUPER_PLUS: 2749 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2750 break; 2751 case USB_SPEED_FULL: 2752 /* XXX using 64 as initial mps of ep0 in FS */ 2753 case USB_SPEED_HIGH: 2754 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2755 break; 2756 case USB_SPEED_LOW: 2757 default: 2758 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2759 break; 2760 } 2761 2762 up->up_dev = dev; 2763 2764 /* Establish the default pipe. */ 2765 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2766 &dev->ud_pipe0); 2767 if (err) { 2768 goto bad; 2769 } 2770 2771 dd = &dev->ud_ddesc; 2772 2773 if (depth == 0 && port == 0) { 2774 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2775 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2776 err = usbd_get_initial_ddesc(dev, dd); 2777 if (err) { 2778 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2779 goto bad; 2780 } 2781 2782 err = usbd_reload_device_desc(dev); 2783 if (err) { 2784 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2785 goto bad; 2786 } 2787 } else { 2788 uint8_t slot = 0; 2789 2790 /* 4.3.2 */ 2791 err = xhci_enable_slot(sc, &slot); 2792 if (err) { 2793 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2794 goto bad; 2795 } 2796 2797 xs = &sc->sc_slots[slot]; 2798 dev->ud_hcpriv = xs; 2799 2800 /* 4.3.3 initialize slot structure */ 2801 err = xhci_init_slot(dev, slot); 2802 if (err) { 2803 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2804 dev->ud_hcpriv = NULL; 2805 /* 2806 * We have to disable_slot here because 2807 * xs->xs_idx == 0 when xhci_init_slot fails, 2808 * in that case usbd_remove_dev won't work. 2809 */ 2810 mutex_enter(&sc->sc_lock); 2811 xhci_disable_slot(sc, slot); 2812 mutex_exit(&sc->sc_lock); 2813 goto bad; 2814 } 2815 2816 /* 4.3.4 Address Assignment */ 2817 err = xhci_set_address(dev, slot, false); 2818 if (err) { 2819 DPRINTFN(1, "failed! to set address: %ju", err, 0, 0, 0); 2820 goto bad; 2821 } 2822 2823 /* Allow device time to set new address */ 2824 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2825 2826 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2827 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2828 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2829 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2830 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2831 /* 2832 * XXX ensure we know when the hardware does something 2833 * we can't yet cope with 2834 */ 2835 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2836 dev->ud_addr = addr; 2837 2838 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2839 "addr %d already allocated", dev->ud_addr); 2840 /* 2841 * The root hub is given its own slot 2842 */ 2843 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2844 2845 err = usbd_get_initial_ddesc(dev, dd); 2846 if (err) { 2847 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2848 goto bad; 2849 } 2850 2851 /* 4.8.2.1 */ 2852 if (USB_IS_SS(speed)) { 2853 if (dd->bMaxPacketSize != 9) { 2854 printf("%s: invalid mps 2^%u for SS ep0," 2855 " using 512\n", 2856 device_xname(sc->sc_dev), 2857 dd->bMaxPacketSize); 2858 dd->bMaxPacketSize = 9; 2859 } 2860 USETW(dev->ud_ep0desc.wMaxPacketSize, 2861 (1 << dd->bMaxPacketSize)); 2862 } else 2863 USETW(dev->ud_ep0desc.wMaxPacketSize, 2864 dd->bMaxPacketSize); 2865 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2866 err = xhci_update_ep0_mps(sc, xs, 2867 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2868 if (err) { 2869 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2870 goto bad; 2871 } 2872 2873 err = usbd_reload_device_desc(dev); 2874 if (err) { 2875 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2876 goto bad; 2877 } 2878 } 2879 2880 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2881 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2882 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2883 dd->bDeviceClass, dd->bDeviceSubClass, 2884 dd->bDeviceProtocol, 0); 2885 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2886 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2887 dev->ud_speed); 2888 2889 usbd_get_device_strings(dev); 2890 2891 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2892 2893 if (depth == 0 && port == 0) { 2894 usbd_attach_roothub(parent, dev); 2895 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2896 return USBD_NORMAL_COMPLETION; 2897 } 2898 2899 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2900 bad: 2901 if (err != USBD_NORMAL_COMPLETION) { 2902 usbd_remove_device(dev, up); 2903 } 2904 2905 return err; 2906 } 2907 2908 static usbd_status 2909 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2910 size_t ntrb, size_t align) 2911 { 2912 usbd_status err; 2913 size_t size = ntrb * XHCI_TRB_SIZE; 2914 2915 XHCIHIST_FUNC(); 2916 XHCIHIST_CALLARGS("xr %#jx ntrb %#jx align %#jx", 2917 (uintptr_t)xr, ntrb, align, 0); 2918 2919 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2920 if (err) 2921 return err; 2922 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2923 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2924 xr->xr_trb = xhci_ring_trbv(xr, 0); 2925 xr->xr_ntrb = ntrb; 2926 xr->is_halted = false; 2927 xhci_host_dequeue(xr); 2928 2929 return USBD_NORMAL_COMPLETION; 2930 } 2931 2932 static void 2933 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2934 { 2935 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2936 mutex_destroy(&xr->xr_lock); 2937 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2938 } 2939 2940 static void 2941 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2942 void *cookie, struct xhci_soft_trb * const trbs, size_t ntrbs) 2943 { 2944 size_t i; 2945 u_int ri; 2946 u_int cs; 2947 uint64_t parameter; 2948 uint32_t status; 2949 uint32_t control; 2950 2951 XHCIHIST_FUNC(); 2952 XHCIHIST_CALLARGS("%#jx xr_ep 0x%jx xr_cs %ju", 2953 (uintptr_t)xr, xr->xr_ep, xr->xr_cs, 0); 2954 2955 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2956 for (i = 0; i < ntrbs; i++) { 2957 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2958 (uintptr_t)trbs, i, 0); 2959 DPRINTFN(12, " %016jx %08jx %08jx", 2960 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2961 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2962 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2963 } 2964 2965 ri = xr->xr_ep; 2966 cs = xr->xr_cs; 2967 2968 /* 2969 * Although the xhci hardware can do scatter/gather dma from 2970 * arbitrary sized buffers, there is a non-obvious restriction 2971 * that a LINK trb is only allowed at the end of a burst of 2972 * transfers - which might be 16kB. 2973 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2974 * The simple solution is not to allow a LINK trb in the middle 2975 * of anything - as here. 2976 * XXX: (dsl) There are xhci controllers out there (eg some made by 2977 * ASMedia) that seem to lock up if they process a LINK trb but 2978 * cannot process the linked-to trb yet. 2979 * The code should write the 'cycle' bit on the link trb AFTER 2980 * adding the other trb. 2981 */ 2982 u_int firstep = xr->xr_ep; 2983 u_int firstcs = xr->xr_cs; 2984 2985 for (i = 0; i < ntrbs; ) { 2986 u_int oldri = ri; 2987 u_int oldcs = cs; 2988 2989 if (ri >= (xr->xr_ntrb - 1)) { 2990 /* Put Link TD at the end of ring */ 2991 parameter = xhci_ring_trbp(xr, 0); 2992 status = 0; 2993 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2994 XHCI_TRB_3_TC_BIT; 2995 xr->xr_cookies[ri] = NULL; 2996 xr->xr_ep = 0; 2997 xr->xr_cs ^= 1; 2998 ri = xr->xr_ep; 2999 cs = xr->xr_cs; 3000 } else { 3001 parameter = trbs[i].trb_0; 3002 status = trbs[i].trb_2; 3003 control = trbs[i].trb_3; 3004 3005 xr->xr_cookies[ri] = cookie; 3006 ri++; 3007 i++; 3008 } 3009 /* 3010 * If this is a first TRB, mark it invalid to prevent 3011 * xHC from running it immediately. 3012 */ 3013 if (oldri == firstep) { 3014 if (oldcs) { 3015 control &= ~XHCI_TRB_3_CYCLE_BIT; 3016 } else { 3017 control |= XHCI_TRB_3_CYCLE_BIT; 3018 } 3019 } else { 3020 if (oldcs) { 3021 control |= XHCI_TRB_3_CYCLE_BIT; 3022 } else { 3023 control &= ~XHCI_TRB_3_CYCLE_BIT; 3024 } 3025 } 3026 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 3027 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 3028 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3029 } 3030 3031 /* Now invert cycle bit of first TRB */ 3032 if (firstcs) { 3033 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 3034 } else { 3035 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 3036 } 3037 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 3038 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3039 3040 xr->xr_ep = ri; 3041 xr->xr_cs = cs; 3042 3043 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 3044 xr->xr_cs, 0); 3045 } 3046 3047 /* 3048 * Stop execution commands, purge all commands on command ring, and 3049 * rewind dequeue pointer. 3050 */ 3051 static void 3052 xhci_abort_command(struct xhci_softc *sc) 3053 { 3054 struct xhci_ring * const cr = &sc->sc_cr; 3055 uint64_t crcr; 3056 int i; 3057 3058 XHCIHIST_FUNC(); 3059 XHCIHIST_CALLARGS("command %#jx timeout, aborting", 3060 sc->sc_command_addr, 0, 0, 0); 3061 3062 mutex_enter(&cr->xr_lock); 3063 3064 /* 4.6.1.2 Aborting a Command */ 3065 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3066 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 3067 3068 for (i = 0; i < 500; i++) { 3069 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3070 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 3071 break; 3072 usb_delay_ms(&sc->sc_bus, 1); 3073 } 3074 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 3075 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 3076 /* reset HC here? */ 3077 } 3078 3079 /* reset command ring dequeue pointer */ 3080 cr->xr_ep = 0; 3081 cr->xr_cs = 1; 3082 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 3083 3084 mutex_exit(&cr->xr_lock); 3085 } 3086 3087 /* 3088 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 3089 * Command completion is notified by cv_signal from xhci_event_cmd() 3090 * (called from xhci_softint), or timed-out. 3091 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 3092 * then do_command examines it. 3093 */ 3094 static usbd_status 3095 xhci_do_command_locked(struct xhci_softc * const sc, 3096 struct xhci_soft_trb * const trb, int timeout) 3097 { 3098 struct xhci_ring * const cr = &sc->sc_cr; 3099 usbd_status err; 3100 3101 XHCIHIST_FUNC(); 3102 XHCIHIST_CALLARGS("input: 0x%016jx 0x%08jx 0x%08jx", 3103 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3104 3105 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 3106 KASSERT(mutex_owned(&sc->sc_lock)); 3107 3108 while (sc->sc_command_addr != 0 || 3109 (sc->sc_suspender != NULL && sc->sc_suspender != curlwp)) 3110 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 3111 3112 /* 3113 * If enqueue pointer points at last of ring, it's Link TRB, 3114 * command TRB will be stored in 0th TRB. 3115 */ 3116 if (cr->xr_ep == cr->xr_ntrb - 1) 3117 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 3118 else 3119 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 3120 3121 sc->sc_resultpending = true; 3122 3123 mutex_enter(&cr->xr_lock); 3124 xhci_ring_put(sc, cr, NULL, trb, 1); 3125 mutex_exit(&cr->xr_lock); 3126 3127 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 3128 3129 while (sc->sc_resultpending) { 3130 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 3131 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 3132 xhci_abort_command(sc); 3133 err = USBD_TIMEOUT; 3134 goto timedout; 3135 } 3136 } 3137 3138 trb->trb_0 = sc->sc_result_trb.trb_0; 3139 trb->trb_2 = sc->sc_result_trb.trb_2; 3140 trb->trb_3 = sc->sc_result_trb.trb_3; 3141 3142 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 3143 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3144 3145 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 3146 case XHCI_TRB_ERROR_SUCCESS: 3147 err = USBD_NORMAL_COMPLETION; 3148 break; 3149 default: 3150 case 192 ... 223: 3151 DPRINTFN(5, "error %x", 3152 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0); 3153 err = USBD_IOERROR; 3154 break; 3155 case 224 ... 255: 3156 err = USBD_NORMAL_COMPLETION; 3157 break; 3158 } 3159 3160 timedout: 3161 sc->sc_resultpending = false; 3162 sc->sc_command_addr = 0; 3163 cv_broadcast(&sc->sc_cmdbusy_cv); 3164 3165 return err; 3166 } 3167 3168 static usbd_status 3169 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb, 3170 int timeout) 3171 { 3172 3173 mutex_enter(&sc->sc_lock); 3174 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 3175 mutex_exit(&sc->sc_lock); 3176 3177 return ret; 3178 } 3179 3180 static usbd_status 3181 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 3182 { 3183 struct xhci_soft_trb trb; 3184 usbd_status err; 3185 3186 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3187 3188 trb.trb_0 = 0; 3189 trb.trb_2 = 0; 3190 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 3191 3192 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3193 if (err != USBD_NORMAL_COMPLETION) { 3194 return err; 3195 } 3196 3197 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 3198 3199 return err; 3200 } 3201 3202 /* 3203 * xHCI 4.6.4 3204 * Deallocate ring and device/input context DMA buffers, and disable_slot. 3205 * All endpoints in the slot should be stopped. 3206 * Should be called with sc_lock held. 3207 */ 3208 static usbd_status 3209 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 3210 { 3211 struct xhci_soft_trb trb; 3212 struct xhci_slot *xs; 3213 usbd_status err; 3214 3215 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3216 3217 if (sc->sc_dying) 3218 return USBD_IOERROR; 3219 3220 trb.trb_0 = 0; 3221 trb.trb_2 = 0; 3222 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) | 3223 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT); 3224 3225 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 3226 3227 if (!err) { 3228 xs = &sc->sc_slots[slot]; 3229 if (xs->xs_idx != 0) { 3230 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 3231 xhci_set_dcba(sc, 0, slot); 3232 memset(xs, 0, sizeof(*xs)); 3233 } 3234 } 3235 3236 return err; 3237 } 3238 3239 /* 3240 * Set address of device and transition slot state from ENABLED to ADDRESSED 3241 * if Block Setaddress Request (BSR) is false. 3242 * If BSR==true, transition slot state from ENABLED to DEFAULT. 3243 * see xHCI 1.1 4.5.3, 3.3.4 3244 * Should be called without sc_lock held. 3245 */ 3246 static usbd_status 3247 xhci_address_device(struct xhci_softc * const sc, 3248 uint64_t icp, uint8_t slot_id, bool bsr) 3249 { 3250 struct xhci_soft_trb trb; 3251 usbd_status err; 3252 3253 XHCIHIST_FUNC(); 3254 if (bsr) { 3255 XHCIHIST_CALLARGS("icp %jx slot %jx with bsr", 3256 icp, slot_id, 0, 0); 3257 } else { 3258 XHCIHIST_CALLARGS("icp %jx slot %jx nobsr", 3259 icp, slot_id, 0, 0); 3260 } 3261 3262 trb.trb_0 = icp; 3263 trb.trb_2 = 0; 3264 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 3265 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 3266 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 3267 3268 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3269 3270 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 3271 err = USBD_NO_ADDR; 3272 3273 return err; 3274 } 3275 3276 static usbd_status 3277 xhci_update_ep0_mps(struct xhci_softc * const sc, 3278 struct xhci_slot * const xs, u_int mps) 3279 { 3280 struct xhci_soft_trb trb; 3281 usbd_status err; 3282 uint32_t * cp; 3283 3284 XHCIHIST_FUNC(); 3285 XHCIHIST_CALLARGS("slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 3286 3287 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3288 cp[0] = htole32(0); 3289 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 3290 3291 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 3292 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 3293 3294 /* sync input contexts before they are read from memory */ 3295 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3296 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3297 sc->sc_ctxsz * 4); 3298 3299 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 3300 trb.trb_2 = 0; 3301 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 3302 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 3303 3304 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3305 return err; 3306 } 3307 3308 static void 3309 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 3310 { 3311 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 3312 3313 XHCIHIST_FUNC(); 3314 XHCIHIST_CALLARGS("dcbaa %#jx dc %016jx slot %jd", 3315 (uintptr_t)&dcbaa[si], dcba, si, 0); 3316 3317 dcbaa[si] = htole64(dcba); 3318 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 3319 BUS_DMASYNC_PREWRITE); 3320 } 3321 3322 /* 3323 * Allocate device and input context DMA buffer, and 3324 * TRB DMA buffer for each endpoint. 3325 */ 3326 static usbd_status 3327 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 3328 { 3329 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3330 struct xhci_slot *xs; 3331 usbd_status err; 3332 u_int dci; 3333 3334 XHCIHIST_FUNC(); 3335 XHCIHIST_CALLARGS("slot %ju", slot, 0, 0, 0); 3336 3337 xs = &sc->sc_slots[slot]; 3338 3339 /* allocate contexts */ 3340 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 3341 &xs->xs_dc_dma); 3342 if (err) 3343 return err; 3344 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 3345 3346 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 3347 &xs->xs_ic_dma); 3348 if (err) 3349 goto bad1; 3350 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 3351 3352 for (dci = 0; dci < 32; dci++) { 3353 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 3354 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 3355 if (dci == XHCI_DCI_SLOT) 3356 continue; 3357 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 3358 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 3359 if (err) { 3360 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 3361 goto bad2; 3362 } 3363 } 3364 3365 bad2: 3366 if (err == USBD_NORMAL_COMPLETION) { 3367 xs->xs_idx = slot; 3368 } else { 3369 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 3370 } 3371 3372 return err; 3373 3374 bad1: 3375 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3376 xs->xs_idx = 0; 3377 return err; 3378 } 3379 3380 static void 3381 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 3382 int end_dci) 3383 { 3384 u_int dci; 3385 3386 XHCIHIST_FUNC(); 3387 XHCIHIST_CALLARGS("slot %ju start %ju end %ju", 3388 xs->xs_idx, start_dci, end_dci, 0); 3389 3390 for (dci = start_dci; dci < end_dci; dci++) { 3391 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 3392 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 3393 } 3394 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 3395 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3396 xs->xs_idx = 0; 3397 } 3398 3399 /* 3400 * Setup slot context, set Device Context Base Address, and issue 3401 * Set Address Device command. 3402 */ 3403 static usbd_status 3404 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 3405 { 3406 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3407 struct xhci_slot *xs; 3408 usbd_status err; 3409 3410 XHCIHIST_FUNC(); 3411 XHCIHIST_CALLARGS("slot %ju bsr %ju", slot, bsr, 0, 0); 3412 3413 xs = &sc->sc_slots[slot]; 3414 3415 xhci_setup_ctx(dev->ud_pipe0); 3416 3417 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3418 sc->sc_ctxsz * 3); 3419 3420 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3421 3422 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3423 3424 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3425 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 3426 sc->sc_ctxsz * 2); 3427 3428 return err; 3429 } 3430 3431 /* 3432 * 4.8.2, 6.2.3.2 3433 * construct slot/endpoint context parameters and do syncmem 3434 */ 3435 static void 3436 xhci_setup_ctx(struct usbd_pipe *pipe) 3437 { 3438 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3439 struct usbd_device *dev = pipe->up_dev; 3440 struct xhci_slot * const xs = dev->ud_hcpriv; 3441 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3442 const u_int dci = xhci_ep_get_dci(ed); 3443 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3444 uint32_t *cp; 3445 uint16_t mps = UGETW(ed->wMaxPacketSize); 3446 uint8_t speed = dev->ud_speed; 3447 uint8_t ival = ed->bInterval; 3448 3449 XHCIHIST_FUNC(); 3450 XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju", 3451 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3452 3453 /* set up initial input control context */ 3454 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3455 cp[0] = htole32(0); 3456 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3457 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3458 cp[7] = htole32(0); 3459 3460 /* set up input slot context */ 3461 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3462 cp[0] = 3463 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3464 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3465 cp[1] = 0; 3466 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3467 cp[3] = 0; 3468 xhci_setup_route(pipe, cp); 3469 xhci_setup_tthub(pipe, cp); 3470 3471 cp[0] = htole32(cp[0]); 3472 cp[1] = htole32(cp[1]); 3473 cp[2] = htole32(cp[2]); 3474 cp[3] = htole32(cp[3]); 3475 3476 /* set up input endpoint context */ 3477 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3478 cp[0] = 3479 XHCI_EPCTX_0_EPSTATE_SET(0) | 3480 XHCI_EPCTX_0_MULT_SET(0) | 3481 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3482 XHCI_EPCTX_0_LSA_SET(0) | 3483 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3484 cp[1] = 3485 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3486 XHCI_EPCTX_1_HID_SET(0) | 3487 XHCI_EPCTX_1_MAXB_SET(0); 3488 3489 if (xfertype != UE_ISOCHRONOUS) 3490 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3491 3492 if (xfertype == UE_CONTROL) 3493 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3494 else if (USB_IS_SS(speed)) 3495 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3496 else 3497 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3498 3499 xhci_setup_maxburst(pipe, cp); 3500 3501 switch (xfertype) { 3502 case UE_CONTROL: 3503 break; 3504 case UE_BULK: 3505 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3506 break; 3507 case UE_INTERRUPT: 3508 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3509 ival = pipe->up_interval; 3510 3511 ival = xhci_bival2ival(ival, speed); 3512 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3513 break; 3514 case UE_ISOCHRONOUS: 3515 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3516 ival = pipe->up_interval; 3517 3518 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3519 if (speed == USB_SPEED_FULL) 3520 ival += 3; /* 1ms -> 125us */ 3521 ival--; 3522 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3523 break; 3524 default: 3525 break; 3526 } 3527 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3528 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3529 3530 /* rewind TR dequeue pointer in xHC */ 3531 /* can't use xhci_ep_get_dci() yet? */ 3532 *(uint64_t *)(&cp[2]) = htole64( 3533 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3534 XHCI_EPCTX_2_DCS_SET(1)); 3535 3536 cp[0] = htole32(cp[0]); 3537 cp[1] = htole32(cp[1]); 3538 cp[4] = htole32(cp[4]); 3539 3540 /* rewind TR dequeue pointer in driver */ 3541 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3542 mutex_enter(&xr->xr_lock); 3543 xhci_host_dequeue(xr); 3544 mutex_exit(&xr->xr_lock); 3545 3546 /* sync input contexts before they are read from memory */ 3547 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3548 } 3549 3550 /* 3551 * Setup route string and roothub port of given device for slot context 3552 */ 3553 static void 3554 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3555 { 3556 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3557 struct usbd_device *dev = pipe->up_dev; 3558 struct usbd_port *up = dev->ud_powersrc; 3559 struct usbd_device *hub; 3560 struct usbd_device *adev; 3561 uint8_t rhport = 0; 3562 uint32_t route = 0; 3563 3564 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3565 3566 /* Locate root hub port and Determine route string */ 3567 /* 4.3.3 route string does not include roothub port */ 3568 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3569 uint32_t dep; 3570 3571 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3572 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3573 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3574 -1); 3575 3576 if (hub->ud_powersrc == NULL) 3577 break; 3578 dep = hub->ud_depth; 3579 if (dep == 0) 3580 break; 3581 rhport = hub->ud_powersrc->up_portno; 3582 if (dep > USB_HUB_MAX_DEPTH) 3583 continue; 3584 3585 route |= 3586 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3587 << ((dep - 1) * 4); 3588 } 3589 route = route >> 4; 3590 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3591 3592 /* Locate port on upstream high speed hub */ 3593 for (adev = dev, hub = up->up_parent; 3594 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3595 adev = hub, hub = hub->ud_myhub) 3596 ; 3597 if (hub) { 3598 int p; 3599 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3600 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3601 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3602 goto found; 3603 } 3604 } 3605 panic("%s: cannot find HS port", __func__); 3606 found: 3607 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3608 } else { 3609 dev->ud_myhsport = NULL; 3610 } 3611 3612 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3613 3614 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3615 ctlrport, route, (uintptr_t)hub); 3616 3617 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3618 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3619 } 3620 3621 /* 3622 * Setup whether device is hub, whether device uses MTT, and 3623 * TT informations if it uses MTT. 3624 */ 3625 static void 3626 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3627 { 3628 struct usbd_device *dev = pipe->up_dev; 3629 struct usbd_port *myhsport = dev->ud_myhsport; 3630 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3631 uint32_t speed = dev->ud_speed; 3632 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3633 uint8_t tthubslot, ttportnum; 3634 bool ishub; 3635 bool usemtt; 3636 3637 XHCIHIST_FUNC(); 3638 3639 /* 3640 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3641 * tthubslot: 3642 * This is the slot ID of parent HS hub 3643 * if LS/FS device is connected && connected through HS hub. 3644 * This is 0 if device is not LS/FS device || 3645 * parent hub is not HS hub || 3646 * attached to root hub. 3647 * ttportnum: 3648 * This is the downstream facing port of parent HS hub 3649 * if LS/FS device is connected. 3650 * This is 0 if device is not LS/FS device || 3651 * parent hub is not HS hub || 3652 * attached to root hub. 3653 */ 3654 if (myhsport && 3655 myhsport->up_parent->ud_addr != rhaddr && 3656 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3657 ttportnum = myhsport->up_portno; 3658 tthubslot = myhsport->up_parent->ud_addr; 3659 } else { 3660 ttportnum = 0; 3661 tthubslot = 0; 3662 } 3663 XHCIHIST_CALLARGS("myhsport %#jx ttportnum=%jd tthubslot=%jd", 3664 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3665 3666 /* ishub is valid after reading UDESC_DEVICE */ 3667 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3668 3669 /* dev->ud_hub is valid after reading UDESC_HUB */ 3670 if (ishub && dev->ud_hub) { 3671 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3672 uint8_t ttt = 3673 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3674 3675 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3676 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3677 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3678 } 3679 3680 #define IS_MTTHUB(dd) \ 3681 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3682 3683 /* 3684 * MTT flag is set if 3685 * 1. this is HS hub && MTTs are supported and enabled; or 3686 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3687 * are supported and enabled. 3688 * 3689 * XXX enabled is not tested yet 3690 */ 3691 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3692 usemtt = true; 3693 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3694 myhsport && 3695 myhsport->up_parent->ud_addr != rhaddr && 3696 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3697 usemtt = true; 3698 else 3699 usemtt = false; 3700 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3701 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3702 3703 #undef IS_MTTHUB 3704 3705 cp[0] |= 3706 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3707 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3708 cp[2] |= 3709 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3710 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3711 } 3712 3713 /* set up params for periodic endpoint */ 3714 static void 3715 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3716 { 3717 struct usbd_device *dev = pipe->up_dev; 3718 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3719 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3720 usbd_desc_iter_t iter; 3721 const usb_cdc_descriptor_t *cdcd; 3722 uint32_t maxb = 0; 3723 uint16_t mps = UGETW(ed->wMaxPacketSize); 3724 uint8_t speed = dev->ud_speed; 3725 uint8_t ep; 3726 3727 /* config desc is NULL when opening ep0 */ 3728 if (dev == NULL || dev->ud_cdesc == NULL) 3729 goto no_cdcd; 3730 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3731 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3732 if (cdcd == NULL) 3733 goto no_cdcd; 3734 usb_desc_iter_init(dev, &iter); 3735 iter.cur = (const void *)cdcd; 3736 3737 /* find endpoint_ss_comp desc for ep of this pipe */ 3738 for (ep = 0;;) { 3739 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3740 if (cdcd == NULL) 3741 break; 3742 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3743 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3744 bEndpointAddress; 3745 if (UE_GET_ADDR(ep) == 3746 UE_GET_ADDR(ed->bEndpointAddress)) { 3747 cdcd = (const usb_cdc_descriptor_t *) 3748 usb_desc_iter_next(&iter); 3749 break; 3750 } 3751 ep = 0; 3752 } 3753 } 3754 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3755 const usb_endpoint_ss_comp_descriptor_t * esscd = 3756 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3757 maxb = esscd->bMaxBurst; 3758 } 3759 3760 no_cdcd: 3761 /* 6.2.3.4, 4.8.2.4 */ 3762 if (USB_IS_SS(speed)) { 3763 /* USB 3.1 9.6.6 */ 3764 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3765 /* USB 3.1 9.6.7 */ 3766 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3767 #ifdef notyet 3768 if (xfertype == UE_ISOCHRONOUS) { 3769 } 3770 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3771 /* use ESIT */ 3772 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3773 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3774 3775 /* XXX if LEC = 1, set ESIT instead */ 3776 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3777 } else { 3778 /* use ival */ 3779 } 3780 #endif 3781 } else { 3782 /* USB 2.0 9.6.6 */ 3783 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3784 3785 /* 6.2.3.4 */ 3786 if (speed == USB_SPEED_HIGH && 3787 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3788 maxb = UE_GET_TRANS(mps); 3789 } else { 3790 /* LS/FS or HS CTRL or HS BULK */ 3791 maxb = 0; 3792 } 3793 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3794 } 3795 } 3796 3797 /* 3798 * Convert endpoint bInterval value to endpoint context interval value 3799 * for Interrupt pipe. 3800 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3801 */ 3802 static uint32_t 3803 xhci_bival2ival(uint32_t ival, uint32_t speed) 3804 { 3805 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3806 int i; 3807 3808 /* 3809 * round ival down to "the nearest base 2 multiple of 3810 * bInterval * 8". 3811 * bInterval is at most 255 as its type is uByte. 3812 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3813 */ 3814 for (i = 10; i > 0; i--) { 3815 if ((ival * 8) >= (1 << i)) 3816 break; 3817 } 3818 ival = i; 3819 } else { 3820 /* Interval = bInterval-1 for SS/HS */ 3821 ival--; 3822 } 3823 3824 return ival; 3825 } 3826 3827 /* ----- */ 3828 3829 static void 3830 xhci_noop(struct usbd_pipe *pipe) 3831 { 3832 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3833 } 3834 3835 /* 3836 * Process root hub request. 3837 */ 3838 static int 3839 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3840 void *buf, int buflen) 3841 { 3842 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3843 usb_port_status_t ps; 3844 int l, totlen = 0; 3845 uint16_t len, value, index; 3846 int port, i; 3847 uint32_t v; 3848 3849 XHCIHIST_FUNC(); 3850 3851 if (sc->sc_dying) 3852 return -1; 3853 3854 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3855 3856 len = UGETW(req->wLength); 3857 value = UGETW(req->wValue); 3858 index = UGETW(req->wIndex); 3859 3860 XHCIHIST_CALLARGS("rhreq: %04jx %04jx %04jx %04jx", 3861 req->bmRequestType | (req->bRequest << 8), value, index, len); 3862 3863 #define C(x,y) ((x) | ((y) << 8)) 3864 switch (C(req->bRequest, req->bmRequestType)) { 3865 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3866 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3867 if (len == 0) 3868 break; 3869 switch (value) { 3870 #define sd ((usb_string_descriptor_t *)buf) 3871 case C(2, UDESC_STRING): 3872 /* Product */ 3873 totlen = usb_makestrdesc(sd, len, "xHCI root hub"); 3874 break; 3875 #undef sd 3876 default: 3877 /* default from usbroothub */ 3878 return buflen; 3879 } 3880 break; 3881 3882 /* Hub requests */ 3883 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3884 break; 3885 /* Clear Port Feature request */ 3886 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3887 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3888 3889 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3890 index, value, bn, cp); 3891 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3892 return -1; 3893 } 3894 port = XHCI_PORTSC(cp); 3895 v = xhci_op_read_4(sc, port); 3896 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3897 v &= ~XHCI_PS_CLEAR; 3898 switch (value) { 3899 case UHF_PORT_ENABLE: 3900 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3901 break; 3902 case UHF_PORT_SUSPEND: 3903 return -1; 3904 case UHF_PORT_POWER: 3905 break; 3906 case UHF_PORT_TEST: 3907 case UHF_PORT_INDICATOR: 3908 return -1; 3909 case UHF_C_PORT_CONNECTION: 3910 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3911 break; 3912 case UHF_C_PORT_ENABLE: 3913 case UHF_C_PORT_SUSPEND: 3914 case UHF_C_PORT_OVER_CURRENT: 3915 return -1; 3916 case UHF_C_BH_PORT_RESET: 3917 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3918 break; 3919 case UHF_C_PORT_RESET: 3920 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3921 break; 3922 case UHF_C_PORT_LINK_STATE: 3923 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3924 break; 3925 case UHF_C_PORT_CONFIG_ERROR: 3926 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3927 break; 3928 default: 3929 return -1; 3930 } 3931 break; 3932 } 3933 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3934 if (len == 0) 3935 break; 3936 if ((value & 0xff) != 0) { 3937 return -1; 3938 } 3939 usb_hub_descriptor_t hubd; 3940 3941 totlen = uimin(buflen, sizeof(hubd)); 3942 memcpy(&hubd, buf, totlen); 3943 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3944 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3945 hubd.bPwrOn2PwrGood = 200; 3946 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3947 /* XXX can't find out? */ 3948 hubd.DeviceRemovable[i++] = 0; 3949 } 3950 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3951 totlen = uimin(totlen, hubd.bDescLength); 3952 memcpy(buf, &hubd, totlen); 3953 break; 3954 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3955 if (len != 4) { 3956 return -1; 3957 } 3958 memset(buf, 0, len); /* ? XXX */ 3959 totlen = len; 3960 break; 3961 /* Get Port Status request */ 3962 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3963 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3964 3965 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3966 bn, index, cp, 0); 3967 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3968 DPRINTFN(5, "bad get port status: index=%jd bn=%jd " 3969 "portcount=%jd", 3970 index, bn, sc->sc_rhportcount[bn], 0); 3971 return -1; 3972 } 3973 if (len != 4) { 3974 DPRINTFN(5, "bad get port status: len %d != 4", 3975 len, 0, 0, 0); 3976 return -1; 3977 } 3978 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3979 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3980 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3981 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3982 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3983 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3984 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3985 if (v & XHCI_PS_PR) i |= UPS_RESET; 3986 if (v & XHCI_PS_PP) { 3987 if (i & UPS_OTHER_SPEED) 3988 i |= UPS_PORT_POWER_SS; 3989 else 3990 i |= UPS_PORT_POWER; 3991 } 3992 if (i & UPS_OTHER_SPEED) 3993 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3994 if (sc->sc_vendor_port_status) 3995 i = sc->sc_vendor_port_status(sc, v, i); 3996 USETW(ps.wPortStatus, i); 3997 i = 0; 3998 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3999 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 4000 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 4001 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 4002 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 4003 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 4004 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 4005 USETW(ps.wPortChange, i); 4006 totlen = uimin(len, sizeof(ps)); 4007 memcpy(buf, &ps, totlen); 4008 DPRINTFN(5, "get port status: wPortStatus %x wPortChange %x " 4009 "totlen %d", 4010 UGETW(ps.wPortStatus), UGETW(ps.wPortChange), totlen, 0); 4011 break; 4012 } 4013 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 4014 return -1; 4015 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 4016 break; 4017 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 4018 break; 4019 /* Set Port Feature request */ 4020 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 4021 int optval = (index >> 8) & 0xff; 4022 index &= 0xff; 4023 if (index < 1 || index > sc->sc_rhportcount[bn]) { 4024 return -1; 4025 } 4026 4027 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 4028 4029 port = XHCI_PORTSC(cp); 4030 v = xhci_op_read_4(sc, port); 4031 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 4032 v &= ~XHCI_PS_CLEAR; 4033 switch (value) { 4034 case UHF_PORT_ENABLE: 4035 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 4036 break; 4037 case UHF_PORT_SUSPEND: 4038 /* XXX suspend */ 4039 break; 4040 case UHF_PORT_RESET: 4041 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 4042 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 4043 /* Wait for reset to complete. */ 4044 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 4045 if (sc->sc_dying) { 4046 return -1; 4047 } 4048 v = xhci_op_read_4(sc, port); 4049 if (v & XHCI_PS_PR) { 4050 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 4051 usb_delay_ms(&sc->sc_bus, 10); 4052 /* XXX */ 4053 } 4054 break; 4055 case UHF_PORT_POWER: 4056 /* XXX power control */ 4057 break; 4058 /* XXX more */ 4059 case UHF_C_PORT_RESET: 4060 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 4061 break; 4062 case UHF_PORT_U1_TIMEOUT: 4063 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4064 return -1; 4065 } 4066 port = XHCI_PORTPMSC(cp); 4067 v = xhci_op_read_4(sc, port); 4068 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4069 index, cp, v, 0); 4070 v &= ~XHCI_PM3_U1TO_SET(0xff); 4071 v |= XHCI_PM3_U1TO_SET(optval); 4072 xhci_op_write_4(sc, port, v); 4073 break; 4074 case UHF_PORT_U2_TIMEOUT: 4075 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4076 return -1; 4077 } 4078 port = XHCI_PORTPMSC(cp); 4079 v = xhci_op_read_4(sc, port); 4080 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4081 index, cp, v, 0); 4082 v &= ~XHCI_PM3_U2TO_SET(0xff); 4083 v |= XHCI_PM3_U2TO_SET(optval); 4084 xhci_op_write_4(sc, port, v); 4085 break; 4086 default: 4087 return -1; 4088 } 4089 } 4090 break; 4091 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 4092 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 4093 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 4094 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 4095 break; 4096 default: 4097 /* default from usbroothub */ 4098 return buflen; 4099 } 4100 4101 return totlen; 4102 } 4103 4104 /* root hub interrupt */ 4105 4106 static usbd_status 4107 xhci_root_intr_transfer(struct usbd_xfer *xfer) 4108 { 4109 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4110 usbd_status err; 4111 4112 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4113 4114 /* Insert last in queue. */ 4115 mutex_enter(&sc->sc_lock); 4116 err = usb_insert_transfer(xfer); 4117 mutex_exit(&sc->sc_lock); 4118 if (err) 4119 return err; 4120 4121 /* Pipe isn't running, start first */ 4122 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4123 } 4124 4125 /* Wait for roothub port status/change */ 4126 static usbd_status 4127 xhci_root_intr_start(struct usbd_xfer *xfer) 4128 { 4129 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4130 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4131 const bool polling = xhci_polling_p(sc); 4132 4133 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4134 4135 if (sc->sc_dying) 4136 return USBD_IOERROR; 4137 4138 if (!polling) 4139 mutex_enter(&sc->sc_lock); 4140 KASSERT(sc->sc_intrxfer[bn] == NULL); 4141 sc->sc_intrxfer[bn] = xfer; 4142 xfer->ux_status = USBD_IN_PROGRESS; 4143 if (!polling) 4144 mutex_exit(&sc->sc_lock); 4145 4146 return USBD_IN_PROGRESS; 4147 } 4148 4149 static void 4150 xhci_root_intr_abort(struct usbd_xfer *xfer) 4151 { 4152 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4153 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4154 4155 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4156 4157 KASSERT(mutex_owned(&sc->sc_lock)); 4158 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4159 4160 /* If xfer has already completed, nothing to do here. */ 4161 if (sc->sc_intrxfer[bn] == NULL) 4162 return; 4163 4164 /* 4165 * Otherwise, sc->sc_intrxfer[bn] had better be this transfer. 4166 * Cancel it. 4167 */ 4168 KASSERT(sc->sc_intrxfer[bn] == xfer); 4169 xfer->ux_status = USBD_CANCELLED; 4170 usb_transfer_complete(xfer); 4171 } 4172 4173 static void 4174 xhci_root_intr_close(struct usbd_pipe *pipe) 4175 { 4176 struct xhci_softc * const sc __diagused = XHCI_PIPE2SC(pipe); 4177 const struct usbd_xfer *xfer __diagused = pipe->up_intrxfer; 4178 const size_t bn __diagused = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4179 4180 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4181 4182 KASSERT(mutex_owned(&sc->sc_lock)); 4183 4184 /* 4185 * Caller must guarantee the xfer has completed first, by 4186 * closing the pipe only after normal completion or an abort. 4187 */ 4188 KASSERT(sc->sc_intrxfer[bn] == NULL); 4189 } 4190 4191 static void 4192 xhci_root_intr_done(struct usbd_xfer *xfer) 4193 { 4194 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4195 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4196 4197 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4198 4199 KASSERT(mutex_owned(&sc->sc_lock)); 4200 4201 /* Claim the xfer so it doesn't get completed again. */ 4202 KASSERT(sc->sc_intrxfer[bn] == xfer); 4203 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 4204 sc->sc_intrxfer[bn] = NULL; 4205 } 4206 4207 /* -------------- */ 4208 /* device control */ 4209 4210 static usbd_status 4211 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 4212 { 4213 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4214 usbd_status err; 4215 4216 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4217 4218 /* Insert last in queue. */ 4219 mutex_enter(&sc->sc_lock); 4220 err = usb_insert_transfer(xfer); 4221 mutex_exit(&sc->sc_lock); 4222 if (err) 4223 return err; 4224 4225 /* Pipe isn't running, start first */ 4226 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4227 } 4228 4229 static usbd_status 4230 xhci_device_ctrl_start(struct usbd_xfer *xfer) 4231 { 4232 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4233 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4234 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4235 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4236 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4237 usb_device_request_t * const req = &xfer->ux_request; 4238 const int isread = usbd_xfer_isread(xfer); 4239 const uint32_t len = UGETW(req->wLength); 4240 usb_dma_t * const dma = &xfer->ux_dmabuf; 4241 uint64_t parameter; 4242 uint32_t status; 4243 uint32_t control; 4244 u_int i; 4245 const bool polling = xhci_polling_p(sc); 4246 4247 XHCIHIST_FUNC(); 4248 XHCIHIST_CALLARGS("req: %04jx %04jx %04jx %04jx", 4249 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 4250 UGETW(req->wIndex), UGETW(req->wLength)); 4251 4252 /* we rely on the bottom bits for extra info */ 4253 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 4254 (uintptr_t) xfer); 4255 4256 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 4257 4258 i = 0; 4259 4260 /* setup phase */ 4261 memcpy(¶meter, req, sizeof(parameter)); 4262 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 4263 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 4264 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 4265 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 4266 XHCI_TRB_3_IDT_BIT; 4267 /* we need parameter un-swapped on big endian, so pre-swap it here */ 4268 xhci_soft_trb_put(&xx->xx_trb[i++], htole64(parameter), status, control); 4269 4270 if (len != 0) { 4271 /* data phase */ 4272 parameter = DMAADDR(dma, 0); 4273 KASSERTMSG(len <= 0x10000, "len %d", len); 4274 status = XHCI_TRB_2_IRQ_SET(0) | 4275 XHCI_TRB_2_TDSZ_SET(0) | 4276 XHCI_TRB_2_BYTES_SET(len); 4277 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 4278 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 4279 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4280 XHCI_TRB_3_IOC_BIT; 4281 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4282 } 4283 4284 parameter = 0; 4285 status = XHCI_TRB_2_IRQ_SET(0); 4286 /* the status stage has inverted direction */ 4287 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 4288 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 4289 XHCI_TRB_3_IOC_BIT; 4290 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4291 4292 if (!polling) 4293 mutex_enter(&tr->xr_lock); 4294 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4295 if (!polling) 4296 mutex_exit(&tr->xr_lock); 4297 4298 if (!polling) 4299 mutex_enter(&sc->sc_lock); 4300 xfer->ux_status = USBD_IN_PROGRESS; 4301 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4302 usbd_xfer_schedule_timeout(xfer); 4303 if (!polling) 4304 mutex_exit(&sc->sc_lock); 4305 4306 return USBD_IN_PROGRESS; 4307 } 4308 4309 static void 4310 xhci_device_ctrl_done(struct usbd_xfer *xfer) 4311 { 4312 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4313 usb_device_request_t *req = &xfer->ux_request; 4314 int len = UGETW(req->wLength); 4315 int rd = req->bmRequestType & UT_READ; 4316 4317 if (len) 4318 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4319 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4320 } 4321 4322 static void 4323 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 4324 { 4325 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4326 4327 usbd_xfer_abort(xfer); 4328 } 4329 4330 static void 4331 xhci_device_ctrl_close(struct usbd_pipe *pipe) 4332 { 4333 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4334 4335 xhci_close_pipe(pipe); 4336 } 4337 4338 /* ------------------ */ 4339 /* device isochronous */ 4340 4341 /* ----------- */ 4342 /* device bulk */ 4343 4344 static usbd_status 4345 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 4346 { 4347 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4348 usbd_status err; 4349 4350 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4351 4352 /* Insert last in queue. */ 4353 mutex_enter(&sc->sc_lock); 4354 err = usb_insert_transfer(xfer); 4355 mutex_exit(&sc->sc_lock); 4356 if (err) 4357 return err; 4358 4359 /* 4360 * Pipe isn't running (otherwise err would be USBD_INPROG), 4361 * so start it first. 4362 */ 4363 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4364 } 4365 4366 static usbd_status 4367 xhci_device_bulk_start(struct usbd_xfer *xfer) 4368 { 4369 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4370 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4371 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4372 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4373 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4374 const uint32_t len = xfer->ux_length; 4375 usb_dma_t * const dma = &xfer->ux_dmabuf; 4376 uint64_t parameter; 4377 uint32_t status; 4378 uint32_t control; 4379 u_int i = 0; 4380 const bool polling = xhci_polling_p(sc); 4381 4382 XHCIHIST_FUNC(); 4383 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4384 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4385 4386 if (sc->sc_dying) 4387 return USBD_IOERROR; 4388 4389 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4390 4391 parameter = DMAADDR(dma, 0); 4392 /* 4393 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 4394 * If the user supplied buffer crosses such a boundary then 2 4395 * (or more) TRB should be used. 4396 * If multiple TRB are used the td_size field must be set correctly. 4397 * For v1.0 devices (like ivy bridge) this is the number of usb data 4398 * blocks needed to complete the transfer. 4399 * Setting it to 1 in the last TRB causes an extra zero-length 4400 * data block be sent. 4401 * The earlier documentation differs, I don't know how it behaves. 4402 */ 4403 KASSERTMSG(len <= 0x10000, "len %d", len); 4404 status = XHCI_TRB_2_IRQ_SET(0) | 4405 XHCI_TRB_2_TDSZ_SET(0) | 4406 XHCI_TRB_2_BYTES_SET(len); 4407 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4408 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4409 XHCI_TRB_3_IOC_BIT; 4410 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4411 4412 if (!polling) 4413 mutex_enter(&tr->xr_lock); 4414 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4415 if (!polling) 4416 mutex_exit(&tr->xr_lock); 4417 4418 if (!polling) 4419 mutex_enter(&sc->sc_lock); 4420 xfer->ux_status = USBD_IN_PROGRESS; 4421 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4422 usbd_xfer_schedule_timeout(xfer); 4423 if (!polling) 4424 mutex_exit(&sc->sc_lock); 4425 4426 return USBD_IN_PROGRESS; 4427 } 4428 4429 static void 4430 xhci_device_bulk_done(struct usbd_xfer *xfer) 4431 { 4432 #ifdef USB_DEBUG 4433 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4434 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4435 #endif 4436 const int isread = usbd_xfer_isread(xfer); 4437 4438 XHCIHIST_FUNC(); 4439 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4440 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4441 4442 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4443 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4444 } 4445 4446 static void 4447 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4448 { 4449 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4450 4451 usbd_xfer_abort(xfer); 4452 } 4453 4454 static void 4455 xhci_device_bulk_close(struct usbd_pipe *pipe) 4456 { 4457 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4458 4459 xhci_close_pipe(pipe); 4460 } 4461 4462 /* ---------------- */ 4463 /* device interrupt */ 4464 4465 static usbd_status 4466 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4467 { 4468 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4469 usbd_status err; 4470 4471 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4472 4473 /* Insert last in queue. */ 4474 mutex_enter(&sc->sc_lock); 4475 err = usb_insert_transfer(xfer); 4476 mutex_exit(&sc->sc_lock); 4477 if (err) 4478 return err; 4479 4480 /* 4481 * Pipe isn't running (otherwise err would be USBD_INPROG), 4482 * so start it first. 4483 */ 4484 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4485 } 4486 4487 static usbd_status 4488 xhci_device_intr_start(struct usbd_xfer *xfer) 4489 { 4490 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4491 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4492 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4493 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4494 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4495 const uint32_t len = xfer->ux_length; 4496 const bool polling = xhci_polling_p(sc); 4497 usb_dma_t * const dma = &xfer->ux_dmabuf; 4498 uint64_t parameter; 4499 uint32_t status; 4500 uint32_t control; 4501 u_int i = 0; 4502 4503 XHCIHIST_FUNC(); 4504 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4505 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4506 4507 if (sc->sc_dying) 4508 return USBD_IOERROR; 4509 4510 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4511 4512 parameter = DMAADDR(dma, 0); 4513 KASSERTMSG(len <= 0x10000, "len %d", len); 4514 status = XHCI_TRB_2_IRQ_SET(0) | 4515 XHCI_TRB_2_TDSZ_SET(0) | 4516 XHCI_TRB_2_BYTES_SET(len); 4517 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4518 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4519 XHCI_TRB_3_IOC_BIT; 4520 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4521 4522 if (!polling) 4523 mutex_enter(&tr->xr_lock); 4524 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4525 if (!polling) 4526 mutex_exit(&tr->xr_lock); 4527 4528 if (!polling) 4529 mutex_enter(&sc->sc_lock); 4530 xfer->ux_status = USBD_IN_PROGRESS; 4531 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4532 usbd_xfer_schedule_timeout(xfer); 4533 if (!polling) 4534 mutex_exit(&sc->sc_lock); 4535 4536 return USBD_IN_PROGRESS; 4537 } 4538 4539 static void 4540 xhci_device_intr_done(struct usbd_xfer *xfer) 4541 { 4542 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4543 #ifdef USB_DEBUG 4544 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4545 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4546 #endif 4547 const int isread = usbd_xfer_isread(xfer); 4548 4549 XHCIHIST_FUNC(); 4550 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4551 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4552 4553 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4554 4555 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4556 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4557 } 4558 4559 static void 4560 xhci_device_intr_abort(struct usbd_xfer *xfer) 4561 { 4562 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4563 4564 XHCIHIST_FUNC(); 4565 XHCIHIST_CALLARGS("%#jx", (uintptr_t)xfer, 0, 0, 0); 4566 4567 KASSERT(mutex_owned(&sc->sc_lock)); 4568 usbd_xfer_abort(xfer); 4569 } 4570 4571 static void 4572 xhci_device_intr_close(struct usbd_pipe *pipe) 4573 { 4574 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4575 4576 XHCIHIST_FUNC(); 4577 XHCIHIST_CALLARGS("%#jx", (uintptr_t)pipe, 0, 0, 0); 4578 4579 xhci_close_pipe(pipe); 4580 } 4581
Indexes created Wed Oct 01 18:09:54 GMT 2025