xhci.c revision 1.107.2.9
1 /* $NetBSD: xhci.c,v 1.107.2.9 2021/06/22 05:10:50 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.107.2.9 2021/06/22 05:10:50 martin Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 119 #define XHCIHIST_FUNC() USBHIST_FUNC() 120 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 121 #define XHCIHIST_CALLARGS(FMT,A,B,C,D) \ 122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D) 123 124 #define XHCI_DCI_SLOT 0 125 #define XHCI_DCI_EP_CONTROL 1 126 127 #define XHCI_ICI_INPUT_CONTROL 0 128 129 struct xhci_pipe { 130 struct usbd_pipe xp_pipe; 131 struct usb_task xp_async_task; 132 }; 133 134 #define XHCI_COMMAND_RING_TRBS 256 135 #define XHCI_EVENT_RING_TRBS 256 136 #define XHCI_EVENT_RING_SEGMENTS 1 137 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 138 139 static usbd_status xhci_open(struct usbd_pipe *); 140 static void xhci_close_pipe(struct usbd_pipe *); 141 static int xhci_intr1(struct xhci_softc * const); 142 static void xhci_softintr(void *); 143 static void xhci_poll(struct usbd_bus *); 144 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 145 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 146 static void xhci_abortx(struct usbd_xfer *); 147 static bool xhci_dying(struct usbd_bus *); 148 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 149 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 150 struct usbd_port *); 151 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 152 void *, int); 153 154 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 155 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 156 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 157 static usbd_status xhci_stop_endpoint_cmd(struct xhci_softc *, 158 struct xhci_slot *, u_int, uint32_t); 159 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 160 161 static void xhci_host_dequeue(struct xhci_ring * const); 162 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 163 164 static usbd_status xhci_do_command(struct xhci_softc * const, 165 struct xhci_soft_trb * const, int); 166 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 167 struct xhci_soft_trb * const, int); 168 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 169 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 170 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 171 static usbd_status xhci_enable_slot(struct xhci_softc * const, 172 uint8_t * const); 173 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 174 static usbd_status xhci_address_device(struct xhci_softc * const, 175 uint64_t, uint8_t, bool); 176 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 177 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 178 struct xhci_slot * const, u_int); 179 static usbd_status xhci_ring_init(struct xhci_softc * const, 180 struct xhci_ring * const, size_t, size_t); 181 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 182 183 static void xhci_setup_ctx(struct usbd_pipe *); 184 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 185 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 186 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 187 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 188 189 static void xhci_noop(struct usbd_pipe *); 190 191 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 192 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 193 static void xhci_root_intr_abort(struct usbd_xfer *); 194 static void xhci_root_intr_close(struct usbd_pipe *); 195 static void xhci_root_intr_done(struct usbd_xfer *); 196 197 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 198 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 199 static void xhci_device_ctrl_abort(struct usbd_xfer *); 200 static void xhci_device_ctrl_close(struct usbd_pipe *); 201 static void xhci_device_ctrl_done(struct usbd_xfer *); 202 203 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 204 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 205 static void xhci_device_intr_abort(struct usbd_xfer *); 206 static void xhci_device_intr_close(struct usbd_pipe *); 207 static void xhci_device_intr_done(struct usbd_xfer *); 208 209 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 210 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 211 static void xhci_device_bulk_abort(struct usbd_xfer *); 212 static void xhci_device_bulk_close(struct usbd_pipe *); 213 static void xhci_device_bulk_done(struct usbd_xfer *); 214 215 static const struct usbd_bus_methods xhci_bus_methods = { 216 .ubm_open = xhci_open, 217 .ubm_softint = xhci_softintr, 218 .ubm_dopoll = xhci_poll, 219 .ubm_allocx = xhci_allocx, 220 .ubm_freex = xhci_freex, 221 .ubm_abortx = xhci_abortx, 222 .ubm_dying = xhci_dying, 223 .ubm_getlock = xhci_get_lock, 224 .ubm_newdev = xhci_new_device, 225 .ubm_rhctrl = xhci_roothub_ctrl, 226 }; 227 228 static const struct usbd_pipe_methods xhci_root_intr_methods = { 229 .upm_transfer = xhci_root_intr_transfer, 230 .upm_start = xhci_root_intr_start, 231 .upm_abort = xhci_root_intr_abort, 232 .upm_close = xhci_root_intr_close, 233 .upm_cleartoggle = xhci_noop, 234 .upm_done = xhci_root_intr_done, 235 }; 236 237 238 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 239 .upm_transfer = xhci_device_ctrl_transfer, 240 .upm_start = xhci_device_ctrl_start, 241 .upm_abort = xhci_device_ctrl_abort, 242 .upm_close = xhci_device_ctrl_close, 243 .upm_cleartoggle = xhci_noop, 244 .upm_done = xhci_device_ctrl_done, 245 }; 246 247 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 248 .upm_cleartoggle = xhci_noop, 249 }; 250 251 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 252 .upm_transfer = xhci_device_bulk_transfer, 253 .upm_start = xhci_device_bulk_start, 254 .upm_abort = xhci_device_bulk_abort, 255 .upm_close = xhci_device_bulk_close, 256 .upm_cleartoggle = xhci_noop, 257 .upm_done = xhci_device_bulk_done, 258 }; 259 260 static const struct usbd_pipe_methods xhci_device_intr_methods = { 261 .upm_transfer = xhci_device_intr_transfer, 262 .upm_start = xhci_device_intr_start, 263 .upm_abort = xhci_device_intr_abort, 264 .upm_close = xhci_device_intr_close, 265 .upm_cleartoggle = xhci_noop, 266 .upm_done = xhci_device_intr_done, 267 }; 268 269 static inline uint32_t 270 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 271 { 272 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 273 } 274 275 static inline uint32_t 276 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 277 { 278 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 279 } 280 281 static inline void 282 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 283 uint32_t value) 284 { 285 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 286 } 287 288 #if 0 /* unused */ 289 static inline void 290 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 291 uint32_t value) 292 { 293 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 294 } 295 #endif /* unused */ 296 297 static inline uint32_t 298 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 299 { 300 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 301 } 302 303 static inline uint32_t 304 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 305 { 306 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 307 } 308 309 static inline void 310 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 311 uint32_t value) 312 { 313 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 314 } 315 316 static inline uint64_t 317 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 318 { 319 uint64_t value; 320 321 if (sc->sc_ac64) { 322 #ifdef XHCI_USE_BUS_SPACE_8 323 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 324 #else 325 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 326 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 327 offset + 4) << 32; 328 #endif 329 } else { 330 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 331 } 332 333 return value; 334 } 335 336 static inline void 337 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 338 uint64_t value) 339 { 340 if (sc->sc_ac64) { 341 #ifdef XHCI_USE_BUS_SPACE_8 342 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 343 #else 344 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 345 (value >> 0) & 0xffffffff); 346 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 347 (value >> 32) & 0xffffffff); 348 #endif 349 } else { 350 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 351 } 352 } 353 354 static inline void 355 xhci_op_barrier(const struct xhci_softc * const sc, bus_size_t offset, 356 bus_size_t len, int flags) 357 { 358 bus_space_barrier(sc->sc_iot, sc->sc_obh, offset, len, flags); 359 } 360 361 static inline uint32_t 362 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 363 { 364 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 365 } 366 367 static inline void 368 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 369 uint32_t value) 370 { 371 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 372 } 373 374 static inline uint64_t 375 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 376 { 377 uint64_t value; 378 379 if (sc->sc_ac64) { 380 #ifdef XHCI_USE_BUS_SPACE_8 381 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 382 #else 383 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 384 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 385 offset + 4) << 32; 386 #endif 387 } else { 388 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 389 } 390 391 return value; 392 } 393 394 static inline void 395 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 396 uint64_t value) 397 { 398 if (sc->sc_ac64) { 399 #ifdef XHCI_USE_BUS_SPACE_8 400 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 401 #else 402 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 403 (value >> 0) & 0xffffffff); 404 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 405 (value >> 32) & 0xffffffff); 406 #endif 407 } else { 408 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 409 } 410 } 411 412 #if 0 /* unused */ 413 static inline uint32_t 414 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 415 { 416 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 417 } 418 #endif /* unused */ 419 420 static inline void 421 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 422 uint32_t value) 423 { 424 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 425 } 426 427 /* --- */ 428 429 static inline uint8_t 430 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 431 { 432 u_int eptype = 0; 433 434 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 435 case UE_CONTROL: 436 eptype = 0x0; 437 break; 438 case UE_ISOCHRONOUS: 439 eptype = 0x1; 440 break; 441 case UE_BULK: 442 eptype = 0x2; 443 break; 444 case UE_INTERRUPT: 445 eptype = 0x3; 446 break; 447 } 448 449 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 450 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 451 return eptype | 0x4; 452 else 453 return eptype; 454 } 455 456 static u_int 457 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 458 { 459 /* xHCI 1.0 section 4.5.1 */ 460 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 461 u_int in = 0; 462 463 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 464 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 465 in = 1; 466 467 return epaddr * 2 + in; 468 } 469 470 static inline u_int 471 xhci_dci_to_ici(const u_int i) 472 { 473 return i + 1; 474 } 475 476 static inline void * 477 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 478 const u_int dci) 479 { 480 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 481 } 482 483 #if 0 /* unused */ 484 static inline bus_addr_t 485 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 486 const u_int dci) 487 { 488 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 489 } 490 #endif /* unused */ 491 492 static inline void * 493 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 494 const u_int ici) 495 { 496 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 497 } 498 499 static inline bus_addr_t 500 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 501 const u_int ici) 502 { 503 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 504 } 505 506 static inline struct xhci_trb * 507 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 508 { 509 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 510 } 511 512 static inline bus_addr_t 513 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 514 { 515 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 516 } 517 518 static inline void 519 xhci_soft_trb_put(struct xhci_soft_trb * const trb, 520 uint64_t parameter, uint32_t status, uint32_t control) 521 { 522 trb->trb_0 = parameter; 523 trb->trb_2 = status; 524 trb->trb_3 = control; 525 } 526 527 static inline void 528 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 529 uint32_t control) 530 { 531 trb->trb_0 = htole64(parameter); 532 trb->trb_2 = htole32(status); 533 trb->trb_3 = htole32(control); 534 } 535 536 static int 537 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 538 { 539 /* base address of TRBs */ 540 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 541 542 /* trb_0 range sanity check */ 543 if (trb_0 == 0 || trb_0 < trbp || 544 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 545 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 546 return 1; 547 } 548 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 549 return 0; 550 } 551 552 static unsigned int 553 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 554 u_int dci) 555 { 556 uint32_t *cp; 557 558 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 559 cp = xhci_slot_get_dcv(sc, xs, dci); 560 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 561 } 562 563 static inline unsigned int 564 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 565 { 566 const unsigned int port = ctlrport - 1; 567 const uint8_t bit = __BIT(port % NBBY); 568 569 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 570 } 571 572 /* 573 * Return the roothub port for a controller port. Both are 1..n. 574 */ 575 static inline unsigned int 576 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 577 { 578 579 return sc->sc_ctlrportmap[ctrlport - 1]; 580 } 581 582 /* 583 * Return the controller port for a bus roothub port. Both are 1..n. 584 */ 585 static inline unsigned int 586 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 587 unsigned int rhport) 588 { 589 590 return sc->sc_rhportmap[bn][rhport - 1]; 591 } 592 593 /* --- */ 594 595 void 596 xhci_childdet(device_t self, device_t child) 597 { 598 struct xhci_softc * const sc = device_private(self); 599 600 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 601 if (child == sc->sc_child2) 602 sc->sc_child2 = NULL; 603 else if (child == sc->sc_child) 604 sc->sc_child = NULL; 605 } 606 607 int 608 xhci_detach(struct xhci_softc *sc, int flags) 609 { 610 int rv = 0; 611 612 if (sc->sc_child2 != NULL) { 613 rv = config_detach(sc->sc_child2, flags); 614 if (rv != 0) 615 return rv; 616 KASSERT(sc->sc_child2 == NULL); 617 } 618 619 if (sc->sc_child != NULL) { 620 rv = config_detach(sc->sc_child, flags); 621 if (rv != 0) 622 return rv; 623 KASSERT(sc->sc_child == NULL); 624 } 625 626 /* XXX unconfigure/free slots */ 627 628 /* verify: */ 629 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 630 xhci_op_write_4(sc, XHCI_USBCMD, 0); 631 /* do we need to wait for stop? */ 632 633 xhci_op_write_8(sc, XHCI_CRCR, 0); 634 xhci_ring_free(sc, &sc->sc_cr); 635 cv_destroy(&sc->sc_command_cv); 636 cv_destroy(&sc->sc_cmdbusy_cv); 637 638 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 639 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 640 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 641 xhci_ring_free(sc, &sc->sc_er); 642 643 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 644 645 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 646 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 647 648 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 649 650 kmem_free(sc->sc_ctlrportbus, 651 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 652 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 653 654 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 655 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 656 } 657 658 mutex_destroy(&sc->sc_lock); 659 mutex_destroy(&sc->sc_intr_lock); 660 661 pool_cache_destroy(sc->sc_xferpool); 662 663 return rv; 664 } 665 666 int 667 xhci_activate(device_t self, enum devact act) 668 { 669 struct xhci_softc * const sc = device_private(self); 670 671 switch (act) { 672 case DVACT_DEACTIVATE: 673 sc->sc_dying = true; 674 return 0; 675 default: 676 return EOPNOTSUPP; 677 } 678 } 679 680 bool 681 xhci_suspend(device_t self, const pmf_qual_t *qual) 682 { 683 struct xhci_softc * const sc = device_private(self); 684 size_t i, j, bn, dci; 685 int port; 686 uint32_t v; 687 usbd_status err; 688 bool ok = false; 689 690 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 691 692 mutex_enter(&sc->sc_lock); 693 694 /* 695 * Block issuance of new commands, and wait for all pending 696 * commands to complete. 697 */ 698 KASSERT(sc->sc_suspender == NULL); 699 sc->sc_suspender = curlwp; 700 while (sc->sc_command_addr != 0) 701 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 702 703 /* 704 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 705 * xHCI Power Management, p. 342 706 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=342 707 */ 708 709 /* 710 * `1. Stop all USB activity by issuing Stop Endpoint Commands 711 * for Busy endpoints in the Running state. If the Force 712 * Save Context Capability (FSC = ``0'') is not supported, 713 * then Stop Endpoint Commands shall be issued for all idle 714 * endpoints in the Running state as well. The Stop 715 * Endpoint Command causes the xHC to update the respective 716 * Endpoint or Stream Contexts in system memory, e.g. the 717 * TR Dequeue Pointer, DCS, etc. fields. Refer to 718 * Implementation Note "0".' 719 */ 720 for (i = 0; i < sc->sc_maxslots; i++) { 721 struct xhci_slot *xs = &sc->sc_slots[i]; 722 723 /* Skip if the slot is not in use. */ 724 if (xs->xs_idx == 0) 725 continue; 726 727 for (dci = 0; dci < 32; dci++) { 728 /* Skip if the endpoint is not Running. */ 729 /* XXX What about Busy? */ 730 if (xhci_get_epstate(sc, xs, dci) != 731 XHCI_EPSTATE_RUNNING) 732 continue; 733 734 /* Stop endpoint. */ 735 err = xhci_stop_endpoint_cmd(sc, xs, dci, 736 XHCI_TRB_3_SUSP_EP_BIT); 737 if (err) { 738 device_printf(self, "failed to stop endpoint" 739 " slot %zu dci %zu err %d\n", 740 i, dci, err); 741 goto out; 742 } 743 } 744 } 745 746 /* 747 * Next, suspend all the ports: 748 * 749 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.15: 750 * Suspend-Resume, pp. 276-283 751 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=276 752 */ 753 for (bn = 0; bn < 2; bn++) { 754 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 755 /* 4.15.1: Port Suspend. */ 756 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 757 758 /* 759 * `System software places individual ports 760 * into suspend mode by writing a ``3'' into 761 * the appropriate PORTSC register Port Link 762 * State (PLS) field (refer to Section 5.4.8). 763 * Software should only set the PLS field to 764 * ``3'' when the port is in the Enabled 765 * state.' 766 * 767 * `Software should not attempt to suspend a 768 * port unless the port reports that it is in 769 * the enabled (PED = ``1''; PLS < ``3'') 770 * state (refer to Section 5.4.8 for more 771 * information about PED and PLS).' 772 */ 773 v = xhci_op_read_4(sc, port); 774 if (((v & XHCI_PS_PED) == 0) || 775 XHCI_PS_PLS_GET(v) >= XHCI_PS_PLS_U3) 776 continue; 777 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 778 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU3); 779 xhci_op_write_4(sc, port, v); 780 781 /* 782 * `When the PLS field is written with U3 783 * (``3''), the status of the PLS bit will not 784 * change to the target U state U3 until the 785 * suspend signaling has completed to the 786 * attached device (which may be as long as 787 * 10ms.).' 788 * 789 * `Software is required to wait for U3 790 * transitions to complete before it puts the 791 * xHC into a low power state, and before 792 * resuming the port.' 793 * 794 * XXX Take advantage of the technique to 795 * reduce polling on host controllers that 796 * support the U3C capability. 797 */ 798 for (j = 0; j < XHCI_WAIT_PLS_U3; j++) { 799 v = xhci_op_read_4(sc, port); 800 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U3) 801 break; 802 usb_delay_ms(&sc->sc_bus, 1); 803 } 804 if (j == XHCI_WAIT_PLS_U3) { 805 device_printf(self, 806 "suspend timeout on bus %zu port %zu\n", 807 bn, i); 808 goto out; 809 } 810 } 811 } 812 813 /* 814 * `2. Ensure that the Command Ring is in the Stopped state 815 * (CRR = ``0'') or Idle (i.e. the Command Transfer Ring is 816 * empty), and all Command Completion Events associated 817 * with them have been received.' 818 * 819 * XXX 820 */ 821 822 /* `3. Stop the controller by setting Run/Stop (R/S) = ``0''.' */ 823 xhci_op_write_4(sc, XHCI_USBCMD, 824 xhci_op_read_4(sc, XHCI_USBCMD) & ~XHCI_CMD_RS); 825 826 /* 827 * `4. Read the Operational Runtime, and VTIO registers in the 828 * following order: USBCMD, DNCTRL, DCBAAP, CONFIG, ERSTSZ, 829 * ERSTBA, ERDP, IMAN, IMOD, and VTIO and save their 830 * state.' 831 * 832 * (We don't use VTIO here (XXX for now?).) 833 */ 834 sc->sc_regs.usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 835 sc->sc_regs.dnctrl = xhci_op_read_4(sc, XHCI_DNCTRL); 836 sc->sc_regs.dcbaap = xhci_op_read_8(sc, XHCI_DCBAAP); 837 sc->sc_regs.config = xhci_op_read_4(sc, XHCI_CONFIG); 838 sc->sc_regs.erstsz0 = xhci_rt_read_4(sc, XHCI_ERSTSZ(0)); 839 sc->sc_regs.erstba0 = xhci_rt_read_8(sc, XHCI_ERSTBA(0)); 840 sc->sc_regs.erdp0 = xhci_rt_read_8(sc, XHCI_ERDP(0)); 841 sc->sc_regs.iman0 = xhci_rt_read_4(sc, XHCI_IMAN(0)); 842 sc->sc_regs.imod0 = xhci_rt_read_4(sc, XHCI_IMOD(0)); 843 844 /* 845 * `5. Set the Controller Save State (CSS) flag in the USBCMD 846 * register (5.4.1)...' 847 */ 848 xhci_op_write_4(sc, XHCI_USBCMD, 849 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CSS); 850 851 /* 852 * `...and wait for the Save State Status (SSS) flag in the 853 * USBSTS register (5.4.2) to transition to ``0''.' 854 */ 855 for (i = 0; i < XHCI_WAIT_SSS; i++) { 856 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SSS) == 0) 857 break; 858 usb_delay_ms(&sc->sc_bus, 1); 859 } 860 if (i >= XHCI_WAIT_SSS) { 861 device_printf(self, "suspend timeout, USBSTS.SSS\n"); 862 /* 863 * Just optimistically go on and check SRE anyway -- 864 * what's the worst that could happen? 865 */ 866 } 867 868 /* 869 * `Note: After a Save or Restore operation completes, the 870 * Save/Restore Error (SRE) flag in the USBSTS register should 871 * be checked to ensure that the operation completed 872 * successfully.' 873 */ 874 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 875 device_printf(self, "suspend error, USBSTS.SRE\n"); 876 goto out; 877 } 878 879 /* Success! */ 880 ok = true; 881 882 out: mutex_exit(&sc->sc_lock); 883 return ok; 884 } 885 886 bool 887 xhci_resume(device_t self, const pmf_qual_t *qual) 888 { 889 struct xhci_softc * const sc = device_private(self); 890 size_t i, j, bn, dci; 891 int port; 892 uint32_t v; 893 bool ok = false; 894 895 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 896 897 mutex_enter(&sc->sc_lock); 898 KASSERT(sc->sc_suspender); 899 900 /* 901 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 902 * xHCI Power Management, p. 343 903 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=343 904 */ 905 906 /* 907 * `4. Restore the Operational Runtime, and VTIO registers with 908 * their previously saved state in the following order: 909 * DNCTRL, DCBAAP, CONFIG, ERSTSZ, ERSTBA, ERDP, IMAN, 910 * IMOD, and VTIO.' 911 * 912 * (We don't use VTIO here (for now?).) 913 */ 914 xhci_op_write_4(sc, XHCI_USBCMD, sc->sc_regs.usbcmd); 915 xhci_op_write_4(sc, XHCI_DNCTRL, sc->sc_regs.dnctrl); 916 xhci_op_write_8(sc, XHCI_DCBAAP, sc->sc_regs.dcbaap); 917 xhci_op_write_4(sc, XHCI_CONFIG, sc->sc_regs.config); 918 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), sc->sc_regs.erstsz0); 919 xhci_rt_write_8(sc, XHCI_ERSTBA(0), sc->sc_regs.erstba0); 920 xhci_rt_write_8(sc, XHCI_ERDP(0), sc->sc_regs.erdp0); 921 xhci_rt_write_4(sc, XHCI_IMAN(0), sc->sc_regs.iman0); 922 xhci_rt_write_4(sc, XHCI_IMOD(0), sc->sc_regs.imod0); 923 924 memset(&sc->sc_regs, 0, sizeof(sc->sc_regs)); /* paranoia */ 925 926 /* 927 * `5. Set the Controller Restore State (CRS) flag in the 928 * USBCMD register (5.4.1) to ``1''...' 929 */ 930 xhci_op_write_4(sc, XHCI_USBCMD, 931 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CRS); 932 933 /* 934 * `...and wait for the Restore State Status (RSS) in the 935 * USBSTS register (5.4.2) to transition to ``0''.' 936 */ 937 for (i = 0; i < XHCI_WAIT_RSS; i++) { 938 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_RSS) == 0) 939 break; 940 usb_delay_ms(&sc->sc_bus, 1); 941 } 942 if (i >= XHCI_WAIT_RSS) { 943 device_printf(self, "suspend timeout, USBSTS.RSS\n"); 944 goto out; 945 } 946 947 /* 948 * `6. Reinitialize the Command Ring, i.e. so its Cycle bits 949 * are consistent with the RCS values to be written to the 950 * CRCR.' 951 * 952 * XXX Hope just zeroing it is good enough! 953 */ 954 xhci_host_dequeue(&sc->sc_cr); 955 956 /* 957 * `7. Write the CRCR with the address and RCS value of the 958 * reinitialized Command Ring. Note that this write will 959 * cause the Command Ring to restart at the address 960 * specified by the CRCR.' 961 */ 962 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 963 sc->sc_cr.xr_cs); 964 965 /* 966 * `8. Enable the controller by setting Run/Stop (R/S) = 967 * ``1''.' 968 */ 969 xhci_op_write_4(sc, XHCI_USBCMD, 970 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_RS); 971 972 /* 973 * `9. Software shall walk the USB topology and initialize each 974 * of the xHC PORTSC, PORTPMSC, and PORTLI registers, and 975 * external hub ports attached to USB devices.' 976 * 977 * This follows the procedure in 4.15 `Suspend-Resume', 4.15.2 978 * `Port Resume', 4.15.2.1 `Host Initiated'. 979 * 980 * XXX We should maybe batch up initiating the state 981 * transitions, and then wait for them to complete all at once. 982 */ 983 for (bn = 0; bn < 2; bn++) { 984 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 985 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 986 987 /* `When a port is in the U3 state: ...' */ 988 v = xhci_op_read_4(sc, port); 989 if (XHCI_PS_PLS_GET(v) != XHCI_PS_PLS_U3) 990 continue; 991 992 /* 993 * `For a USB2 protocol port, software shall 994 * write a ``15'' (Resume) to the PLS field to 995 * initiate resume signaling. The port shall 996 * transition to the Resume substate and the 997 * xHC shall transmit the resume signaling 998 * within 1ms (T_URSM). Software shall ensure 999 * that resume is signaled for at least 20ms 1000 * (T_DRSMDN). Software shall start timing 1001 * T_DRSMDN from the write of ``15'' (Resume) 1002 * to PLS.' 1003 */ 1004 if (bn == 1) { 1005 KASSERT(sc->sc_bus2.ub_revision == USBREV_2_0); 1006 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1007 v |= XHCI_PS_LWS; 1008 v |= XHCI_PS_PLS_SET(XHCI_PS_PLS_SETRESUME); 1009 xhci_op_write_4(sc, port, v); 1010 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1011 } else { 1012 KASSERT(sc->sc_bus.ub_revision > USBREV_2_0); 1013 } 1014 1015 /* 1016 * `For a USB3 protocol port [and a USB2 1017 * protocol port after transitioning to 1018 * Resume], software shall write a ``0'' (U0) 1019 * to the PLS field...' 1020 */ 1021 v = xhci_op_read_4(sc, port); 1022 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1023 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU0); 1024 xhci_op_write_4(sc, port, v); 1025 1026 for (j = 0; j < XHCI_WAIT_PLS_U0; j++) { 1027 v = xhci_op_read_4(sc, port); 1028 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U0) 1029 break; 1030 usb_delay_ms(&sc->sc_bus, 1); 1031 } 1032 if (j == XHCI_WAIT_PLS_U0) { 1033 device_printf(self, 1034 "resume timeout on bus %zu port %zu\n", 1035 bn, i); 1036 goto out; 1037 } 1038 } 1039 } 1040 1041 /* 1042 * `10. Restart each of the previously Running endpoints by 1043 * ringing their doorbells.' 1044 */ 1045 for (i = 0; i < sc->sc_maxslots; i++) { 1046 struct xhci_slot *xs = &sc->sc_slots[i]; 1047 1048 /* Skip if the slot is not in use. */ 1049 if (xs->xs_idx == 0) 1050 continue; 1051 1052 for (dci = 0; dci < 32; dci++) { 1053 /* Skip if the endpoint is not Running. */ 1054 if (xhci_get_epstate(sc, xs, dci) != 1055 XHCI_EPSTATE_RUNNING) 1056 continue; 1057 1058 /* Ring the doorbell. */ 1059 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 1060 } 1061 } 1062 1063 /* 1064 * `Note: After a Save or Restore operation completes, the 1065 * Save/Restore Error (SRE) flag in the USBSTS register should 1066 * be checked to ensure that the operation completed 1067 * successfully.' 1068 */ 1069 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 1070 device_printf(self, "resume error, USBSTS.SRE\n"); 1071 goto out; 1072 } 1073 1074 /* Resume command issuance. */ 1075 sc->sc_suspender = NULL; 1076 cv_broadcast(&sc->sc_cmdbusy_cv); 1077 1078 /* Success! */ 1079 ok = true; 1080 1081 out: mutex_exit(&sc->sc_lock); 1082 return ok; 1083 } 1084 1085 bool 1086 xhci_shutdown(device_t self, int flags) 1087 { 1088 return false; 1089 } 1090 1091 static int 1092 xhci_hc_reset(struct xhci_softc * const sc) 1093 { 1094 uint32_t usbcmd, usbsts; 1095 int i; 1096 1097 /* Check controller not ready */ 1098 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1099 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1100 if ((usbsts & XHCI_STS_CNR) == 0) 1101 break; 1102 usb_delay_ms(&sc->sc_bus, 1); 1103 } 1104 if (i >= XHCI_WAIT_CNR) { 1105 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 1106 return EIO; 1107 } 1108 1109 /* Halt controller */ 1110 usbcmd = 0; 1111 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1112 usb_delay_ms(&sc->sc_bus, 1); 1113 1114 /* Reset controller */ 1115 usbcmd = XHCI_CMD_HCRST; 1116 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1117 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 1118 /* 1119 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 1120 * prevent system hang (Errata). 1121 */ 1122 usb_delay_ms(&sc->sc_bus, 1); 1123 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 1124 if ((usbcmd & XHCI_CMD_HCRST) == 0) 1125 break; 1126 } 1127 if (i >= XHCI_WAIT_HCRST) { 1128 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 1129 return EIO; 1130 } 1131 1132 /* Check controller not ready */ 1133 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1134 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1135 if ((usbsts & XHCI_STS_CNR) == 0) 1136 break; 1137 usb_delay_ms(&sc->sc_bus, 1); 1138 } 1139 if (i >= XHCI_WAIT_CNR) { 1140 aprint_error_dev(sc->sc_dev, 1141 "controller not ready timeout after reset\n"); 1142 return EIO; 1143 } 1144 1145 return 0; 1146 } 1147 1148 /* 7.2 xHCI Support Protocol Capability */ 1149 static void 1150 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 1151 { 1152 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1153 1154 /* XXX Cache this lot */ 1155 1156 const uint32_t w0 = xhci_read_4(sc, ecp); 1157 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 1158 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 1159 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 1160 1161 aprint_debug_dev(sc->sc_dev, 1162 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 1163 1164 if (w4 != XHCI_XECP_USBID) 1165 return; 1166 1167 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 1168 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 1169 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 1170 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 1171 1172 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 1173 switch (mm) { 1174 case 0x0200: 1175 case 0x0300: 1176 case 0x0301: 1177 case 0x0310: 1178 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 1179 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 1180 break; 1181 default: 1182 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 1183 major, minor); 1184 return; 1185 } 1186 1187 const size_t bus = (major == 3) ? 0 : 1; 1188 1189 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 1190 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 1191 if (sc->sc_ctlrportmap[cp] != 0) { 1192 aprint_error_dev(sc->sc_dev, "controller port %zu " 1193 "already assigned", cp); 1194 continue; 1195 } 1196 1197 sc->sc_ctlrportbus[cp / NBBY] |= 1198 bus == 0 ? 0 : __BIT(cp % NBBY); 1199 1200 const size_t rhp = sc->sc_rhportcount[bus]++; 1201 1202 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 1203 "bus %zu rhp %zu is %d", bus, rhp, 1204 sc->sc_rhportmap[bus][rhp]); 1205 1206 sc->sc_rhportmap[bus][rhp] = cp + 1; 1207 sc->sc_ctlrportmap[cp] = rhp + 1; 1208 } 1209 } 1210 1211 /* Process extended capabilities */ 1212 static void 1213 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 1214 { 1215 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1216 1217 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 1218 while (ecp != 0) { 1219 uint32_t ecr = xhci_read_4(sc, ecp); 1220 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 1221 switch (XHCI_XECP_ID(ecr)) { 1222 case XHCI_ID_PROTOCOLS: { 1223 xhci_id_protocols(sc, ecp); 1224 break; 1225 } 1226 case XHCI_ID_USB_LEGACY: { 1227 uint8_t bios_sem; 1228 1229 /* Take host controller ownership from BIOS */ 1230 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 1231 if (bios_sem) { 1232 /* sets xHCI to be owned by OS */ 1233 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 1234 aprint_debug_dev(sc->sc_dev, 1235 "waiting for BIOS to give up control\n"); 1236 for (int i = 0; i < 5000; i++) { 1237 bios_sem = xhci_read_1(sc, ecp + 1238 XHCI_XECP_BIOS_SEM); 1239 if (bios_sem == 0) 1240 break; 1241 DELAY(1000); 1242 } 1243 if (bios_sem) { 1244 aprint_error_dev(sc->sc_dev, 1245 "timed out waiting for BIOS\n"); 1246 } 1247 } 1248 break; 1249 } 1250 default: 1251 break; 1252 } 1253 ecr = xhci_read_4(sc, ecp); 1254 if (XHCI_XECP_NEXT(ecr) == 0) { 1255 ecp = 0; 1256 } else { 1257 ecp += XHCI_XECP_NEXT(ecr) * 4; 1258 } 1259 } 1260 } 1261 1262 #define XHCI_HCCPREV1_BITS \ 1263 "\177\020" /* New bitmask */ \ 1264 "f\020\020XECP\0" \ 1265 "f\014\4MAXPSA\0" \ 1266 "b\013CFC\0" \ 1267 "b\012SEC\0" \ 1268 "b\011SBD\0" \ 1269 "b\010FSE\0" \ 1270 "b\7NSS\0" \ 1271 "b\6LTC\0" \ 1272 "b\5LHRC\0" \ 1273 "b\4PIND\0" \ 1274 "b\3PPC\0" \ 1275 "b\2CZC\0" \ 1276 "b\1BNC\0" \ 1277 "b\0AC64\0" \ 1278 "\0" 1279 #define XHCI_HCCV1_x_BITS \ 1280 "\177\020" /* New bitmask */ \ 1281 "f\020\020XECP\0" \ 1282 "f\014\4MAXPSA\0" \ 1283 "b\013CFC\0" \ 1284 "b\012SEC\0" \ 1285 "b\011SPC\0" \ 1286 "b\010PAE\0" \ 1287 "b\7NSS\0" \ 1288 "b\6LTC\0" \ 1289 "b\5LHRC\0" \ 1290 "b\4PIND\0" \ 1291 "b\3PPC\0" \ 1292 "b\2CSZ\0" \ 1293 "b\1BNC\0" \ 1294 "b\0AC64\0" \ 1295 "\0" 1296 1297 #define XHCI_HCC2_BITS \ 1298 "\177\020" /* New bitmask */ \ 1299 "b\7ETC_TSC\0" \ 1300 "b\6ETC\0" \ 1301 "b\5CIC\0" \ 1302 "b\4LEC\0" \ 1303 "b\3CTC\0" \ 1304 "b\2FSC\0" \ 1305 "b\1CMC\0" \ 1306 "b\0U3C\0" \ 1307 "\0" 1308 1309 void 1310 xhci_start(struct xhci_softc *sc) 1311 { 1312 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1313 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1314 /* Intel xhci needs interrupt rate moderated. */ 1315 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1316 else 1317 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1318 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1319 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1320 1321 /* Go! */ 1322 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 1323 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1324 xhci_op_read_4(sc, XHCI_USBCMD)); 1325 } 1326 1327 int 1328 xhci_init(struct xhci_softc *sc) 1329 { 1330 bus_size_t bsz; 1331 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff, hcc2; 1332 uint32_t pagesize, config; 1333 int i = 0; 1334 uint16_t hciversion; 1335 uint8_t caplength; 1336 1337 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1338 1339 /* Set up the bus struct for the usb 3 and usb 2 buses */ 1340 sc->sc_bus.ub_methods = &xhci_bus_methods; 1341 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1342 sc->sc_bus.ub_usedma = true; 1343 sc->sc_bus.ub_hcpriv = sc; 1344 1345 sc->sc_bus2.ub_methods = &xhci_bus_methods; 1346 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 1347 sc->sc_bus2.ub_revision = USBREV_2_0; 1348 sc->sc_bus2.ub_usedma = true; 1349 sc->sc_bus2.ub_hcpriv = sc; 1350 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 1351 1352 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 1353 caplength = XHCI_CAP_CAPLENGTH(cap); 1354 hciversion = XHCI_CAP_HCIVERSION(cap); 1355 1356 if (hciversion < XHCI_HCIVERSION_0_96 || 1357 hciversion >= 0x0200) { 1358 aprint_normal_dev(sc->sc_dev, 1359 "xHCI version %x.%x not known to be supported\n", 1360 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1361 } else { 1362 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 1363 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1364 } 1365 1366 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 1367 &sc->sc_cbh) != 0) { 1368 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 1369 return ENOMEM; 1370 } 1371 1372 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 1373 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 1374 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 1375 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 1376 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 1377 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 1378 aprint_debug_dev(sc->sc_dev, 1379 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 1380 1381 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 1382 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 1383 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 1384 1385 char sbuf[128]; 1386 if (hciversion < XHCI_HCIVERSION_1_0) 1387 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 1388 else 1389 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 1390 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 1391 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 1392 if (hciversion >= XHCI_HCIVERSION_1_1) { 1393 hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 1394 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, hcc2); 1395 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 1396 } 1397 1398 /* default all ports to bus 0, i.e. usb 3 */ 1399 sc->sc_ctlrportbus = kmem_zalloc( 1400 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 1401 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1402 1403 /* controller port to bus roothub port map */ 1404 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 1405 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1406 } 1407 1408 /* 1409 * Process all Extended Capabilities 1410 */ 1411 xhci_ecp(sc, hcc); 1412 1413 bsz = XHCI_PORTSC(sc->sc_maxports); 1414 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1415 &sc->sc_obh) != 0) { 1416 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1417 return ENOMEM; 1418 } 1419 1420 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1421 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1422 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1423 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1424 return ENOMEM; 1425 } 1426 1427 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1428 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1429 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1430 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1431 return ENOMEM; 1432 } 1433 1434 int rv; 1435 rv = xhci_hc_reset(sc); 1436 if (rv != 0) { 1437 return rv; 1438 } 1439 1440 if (sc->sc_vendor_init) 1441 sc->sc_vendor_init(sc); 1442 1443 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1444 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1445 pagesize = ffs(pagesize); 1446 if (pagesize == 0) { 1447 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1448 return EIO; 1449 } 1450 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1451 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1452 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1453 (uint32_t)sc->sc_maxslots); 1454 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1455 1456 usbd_status err; 1457 1458 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1459 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1460 if (sc->sc_maxspbuf != 0) { 1461 err = usb_allocmem(&sc->sc_bus, 1462 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1463 &sc->sc_spbufarray_dma); 1464 if (err) { 1465 aprint_error_dev(sc->sc_dev, 1466 "spbufarray init fail, err %d\n", err); 1467 return ENOMEM; 1468 } 1469 1470 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1471 sc->sc_maxspbuf, KM_SLEEP); 1472 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1473 for (i = 0; i < sc->sc_maxspbuf; i++) { 1474 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1475 /* allocate contexts */ 1476 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1477 sc->sc_pgsz, dma); 1478 if (err) { 1479 aprint_error_dev(sc->sc_dev, 1480 "spbufarray_dma init fail, err %d\n", err); 1481 rv = ENOMEM; 1482 goto bad1; 1483 } 1484 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1485 usb_syncmem(dma, 0, sc->sc_pgsz, 1486 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1487 } 1488 1489 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1490 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1491 } 1492 1493 config = xhci_op_read_4(sc, XHCI_CONFIG); 1494 config &= ~0xFF; 1495 config |= sc->sc_maxslots & 0xFF; 1496 xhci_op_write_4(sc, XHCI_CONFIG, config); 1497 1498 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1499 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1500 if (err) { 1501 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1502 err); 1503 rv = ENOMEM; 1504 goto bad1; 1505 } 1506 1507 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1508 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1509 if (err) { 1510 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1511 err); 1512 rv = ENOMEM; 1513 goto bad2; 1514 } 1515 1516 usb_dma_t *dma; 1517 size_t size; 1518 size_t align; 1519 1520 dma = &sc->sc_eventst_dma; 1521 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1522 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1523 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1524 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1525 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1526 if (err) { 1527 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1528 err); 1529 rv = ENOMEM; 1530 goto bad3; 1531 } 1532 1533 memset(KERNADDR(dma, 0), 0, size); 1534 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1535 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1536 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1537 KERNADDR(&sc->sc_eventst_dma, 0), 1538 sc->sc_eventst_dma.udma_block->size); 1539 1540 dma = &sc->sc_dcbaa_dma; 1541 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1542 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1543 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1544 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1545 if (err) { 1546 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1547 rv = ENOMEM; 1548 goto bad4; 1549 } 1550 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1551 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1552 KERNADDR(&sc->sc_dcbaa_dma, 0), 1553 sc->sc_dcbaa_dma.udma_block->size); 1554 1555 memset(KERNADDR(dma, 0), 0, size); 1556 if (sc->sc_maxspbuf != 0) { 1557 /* 1558 * DCBA entry 0 hold the scratchbuf array pointer. 1559 */ 1560 *(uint64_t *)KERNADDR(dma, 0) = 1561 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1562 } 1563 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1564 1565 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1566 KM_SLEEP); 1567 if (sc->sc_slots == NULL) { 1568 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1569 rv = ENOMEM; 1570 goto bad; 1571 } 1572 1573 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1574 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1575 if (sc->sc_xferpool == NULL) { 1576 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1577 err); 1578 rv = ENOMEM; 1579 goto bad; 1580 } 1581 1582 cv_init(&sc->sc_command_cv, "xhcicmd"); 1583 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1584 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1585 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1586 1587 struct xhci_erste *erst; 1588 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1589 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1590 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1591 erst[0].erste_3 = htole32(0); 1592 usb_syncmem(&sc->sc_eventst_dma, 0, 1593 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1594 1595 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1596 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1597 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1598 XHCI_ERDP_LO_BUSY); 1599 1600 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1601 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1602 sc->sc_cr.xr_cs); 1603 1604 xhci_op_barrier(sc, 0, 4, BUS_SPACE_BARRIER_WRITE); 1605 1606 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1607 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1608 1609 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1610 xhci_start(sc); 1611 1612 return 0; 1613 1614 bad: 1615 if (sc->sc_xferpool) { 1616 pool_cache_destroy(sc->sc_xferpool); 1617 sc->sc_xferpool = NULL; 1618 } 1619 1620 if (sc->sc_slots) { 1621 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1622 sc->sc_maxslots); 1623 sc->sc_slots = NULL; 1624 } 1625 1626 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1627 bad4: 1628 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1629 bad3: 1630 xhci_ring_free(sc, &sc->sc_er); 1631 bad2: 1632 xhci_ring_free(sc, &sc->sc_cr); 1633 i = sc->sc_maxspbuf; 1634 bad1: 1635 for (int j = 0; j < i; j++) 1636 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1637 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1638 1639 return rv; 1640 } 1641 1642 static inline bool 1643 xhci_polling_p(struct xhci_softc * const sc) 1644 { 1645 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1646 } 1647 1648 int 1649 xhci_intr(void *v) 1650 { 1651 struct xhci_softc * const sc = v; 1652 int ret = 0; 1653 1654 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1655 1656 if (sc == NULL) 1657 return 0; 1658 1659 mutex_spin_enter(&sc->sc_intr_lock); 1660 1661 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1662 goto done; 1663 1664 /* If we get an interrupt while polling, then just ignore it. */ 1665 if (xhci_polling_p(sc)) { 1666 #ifdef DIAGNOSTIC 1667 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1668 #endif 1669 goto done; 1670 } 1671 1672 ret = xhci_intr1(sc); 1673 if (ret) { 1674 KASSERT(sc->sc_child || sc->sc_child2); 1675 1676 /* 1677 * One of child busses could be already detached. It doesn't 1678 * matter on which of the two the softintr is scheduled. 1679 */ 1680 if (sc->sc_child) 1681 usb_schedsoftintr(&sc->sc_bus); 1682 else 1683 usb_schedsoftintr(&sc->sc_bus2); 1684 } 1685 done: 1686 mutex_spin_exit(&sc->sc_intr_lock); 1687 return ret; 1688 } 1689 1690 int 1691 xhci_intr1(struct xhci_softc * const sc) 1692 { 1693 uint32_t usbsts; 1694 uint32_t iman; 1695 1696 XHCIHIST_FUNC(); 1697 1698 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1699 XHCIHIST_CALLARGS("USBSTS %08jx", usbsts, 0, 0, 0); 1700 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1701 XHCI_STS_HCE)) == 0) { 1702 DPRINTFN(16, "ignored intr not for %s", 1703 (uintptr_t)device_xname(sc->sc_dev), 0, 0, 0); 1704 return 0; 1705 } 1706 1707 /* 1708 * Clear EINT and other transient flags, to not misenterpret 1709 * next shared interrupt. Also, to avoid race, EINT must be cleared 1710 * before XHCI_IMAN_INTR_PEND is cleared. 1711 */ 1712 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1713 1714 #ifdef XHCI_DEBUG 1715 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1716 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1717 #endif 1718 1719 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1720 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1721 iman |= XHCI_IMAN_INTR_PEND; 1722 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1723 1724 #ifdef XHCI_DEBUG 1725 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1726 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1727 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1728 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1729 #endif 1730 1731 return 1; 1732 } 1733 1734 /* 1735 * 3 port speed types used in USB stack 1736 * 1737 * usbdi speed 1738 * definition: USB_SPEED_* in usb.h 1739 * They are used in struct usbd_device in USB stack. 1740 * ioctl interface uses these values too. 1741 * port_status speed 1742 * definition: UPS_*_SPEED in usb.h 1743 * They are used in usb_port_status_t and valid only for USB 2.0. 1744 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1745 * of usb_port_status_ext_t indicates port speed. 1746 * Note that some 3.0 values overlap with 2.0 values. 1747 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1748 * means UPS_LOW_SPEED in HS.) 1749 * port status returned from hub also uses these values. 1750 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1751 * or more. 1752 * xspeed: 1753 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1754 * They are used in only slot context and PORTSC reg of xhci. 1755 * The difference between usbdi speed and xspeed is 1756 * that FS and LS values are swapped. 1757 */ 1758 1759 /* convert usbdi speed to xspeed */ 1760 static int 1761 xhci_speed2xspeed(int speed) 1762 { 1763 switch (speed) { 1764 case USB_SPEED_LOW: return 2; 1765 case USB_SPEED_FULL: return 1; 1766 default: return speed; 1767 } 1768 } 1769 1770 #if 0 1771 /* convert xspeed to usbdi speed */ 1772 static int 1773 xhci_xspeed2speed(int xspeed) 1774 { 1775 switch (xspeed) { 1776 case 1: return USB_SPEED_FULL; 1777 case 2: return USB_SPEED_LOW; 1778 default: return xspeed; 1779 } 1780 } 1781 #endif 1782 1783 /* convert xspeed to port status speed */ 1784 static int 1785 xhci_xspeed2psspeed(int xspeed) 1786 { 1787 switch (xspeed) { 1788 case 0: return 0; 1789 case 1: return UPS_FULL_SPEED; 1790 case 2: return UPS_LOW_SPEED; 1791 case 3: return UPS_HIGH_SPEED; 1792 default: return UPS_OTHER_SPEED; 1793 } 1794 } 1795 1796 /* 1797 * Construct input contexts and issue TRB to open pipe. 1798 */ 1799 static usbd_status 1800 xhci_configure_endpoint(struct usbd_pipe *pipe) 1801 { 1802 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1803 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1804 #ifdef USB_DEBUG 1805 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1806 #endif 1807 struct xhci_soft_trb trb; 1808 usbd_status err; 1809 1810 XHCIHIST_FUNC(); 1811 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1812 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1813 pipe->up_endpoint->ue_edesc->bmAttributes); 1814 1815 /* XXX ensure input context is available? */ 1816 1817 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1818 1819 /* set up context */ 1820 xhci_setup_ctx(pipe); 1821 1822 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1823 sc->sc_ctxsz * 1); 1824 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1825 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1826 1827 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1828 trb.trb_2 = 0; 1829 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1830 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1831 1832 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1833 1834 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1835 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1836 sc->sc_ctxsz * 1); 1837 1838 return err; 1839 } 1840 1841 #if 0 1842 static usbd_status 1843 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1844 { 1845 #ifdef USB_DEBUG 1846 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1847 #endif 1848 1849 XHCIHIST_FUNC(); 1850 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 1851 1852 return USBD_NORMAL_COMPLETION; 1853 } 1854 #endif 1855 1856 /* 4.6.8, 6.4.3.7 */ 1857 static usbd_status 1858 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1859 { 1860 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1861 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1862 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1863 struct xhci_soft_trb trb; 1864 usbd_status err; 1865 1866 XHCIHIST_FUNC(); 1867 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1868 1869 KASSERT(mutex_owned(&sc->sc_lock)); 1870 1871 trb.trb_0 = 0; 1872 trb.trb_2 = 0; 1873 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1874 XHCI_TRB_3_EP_SET(dci) | 1875 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1876 1877 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1878 1879 return err; 1880 } 1881 1882 static usbd_status 1883 xhci_reset_endpoint(struct usbd_pipe *pipe) 1884 { 1885 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1886 1887 mutex_enter(&sc->sc_lock); 1888 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1889 mutex_exit(&sc->sc_lock); 1890 1891 return ret; 1892 } 1893 1894 /* 1895 * 4.6.9, 6.4.3.8 1896 * Stop execution of TDs on xfer ring. 1897 * Should be called with sc_lock held. 1898 */ 1899 static usbd_status 1900 xhci_stop_endpoint_cmd(struct xhci_softc *sc, struct xhci_slot *xs, u_int dci, 1901 uint32_t trb3flags) 1902 { 1903 struct xhci_soft_trb trb; 1904 usbd_status err; 1905 1906 XHCIHIST_FUNC(); 1907 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1908 1909 KASSERT(mutex_owned(&sc->sc_lock)); 1910 1911 trb.trb_0 = 0; 1912 trb.trb_2 = 0; 1913 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1914 XHCI_TRB_3_EP_SET(dci) | 1915 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1916 trb3flags; 1917 1918 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1919 1920 return err; 1921 } 1922 1923 static usbd_status 1924 xhci_stop_endpoint(struct usbd_pipe *pipe) 1925 { 1926 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1927 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1928 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1929 1930 XHCIHIST_FUNC(); 1931 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1932 1933 KASSERT(mutex_owned(&sc->sc_lock)); 1934 1935 return xhci_stop_endpoint_cmd(sc, xs, dci, 0); 1936 } 1937 1938 /* 1939 * Set TR Dequeue Pointer. 1940 * xHCI 1.1 4.6.10 6.4.3.9 1941 * Purge all of the TRBs on ring and reinitialize ring. 1942 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1943 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1944 * error will be generated. 1945 */ 1946 static usbd_status 1947 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1948 { 1949 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1950 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1951 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1952 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1953 struct xhci_soft_trb trb; 1954 usbd_status err; 1955 1956 XHCIHIST_FUNC(); 1957 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1958 1959 KASSERT(mutex_owned(&sc->sc_lock)); 1960 1961 xhci_host_dequeue(xr); 1962 1963 /* set DCS */ 1964 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1965 trb.trb_2 = 0; 1966 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1967 XHCI_TRB_3_EP_SET(dci) | 1968 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1969 1970 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1971 1972 return err; 1973 } 1974 1975 static usbd_status 1976 xhci_set_dequeue(struct usbd_pipe *pipe) 1977 { 1978 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1979 1980 mutex_enter(&sc->sc_lock); 1981 usbd_status ret = xhci_set_dequeue_locked(pipe); 1982 mutex_exit(&sc->sc_lock); 1983 1984 return ret; 1985 } 1986 1987 /* 1988 * Open new pipe: called from usbd_setup_pipe_flags. 1989 * Fills methods of pipe. 1990 * If pipe is not for ep0, calls configure_endpoint. 1991 */ 1992 static usbd_status 1993 xhci_open(struct usbd_pipe *pipe) 1994 { 1995 struct usbd_device * const dev = pipe->up_dev; 1996 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1997 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1998 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1999 2000 XHCIHIST_FUNC(); 2001 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 2002 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 2003 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 2004 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 2005 ed->bmAttributes); 2006 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 2007 ed->bInterval, 0, 0); 2008 2009 if (sc->sc_dying) 2010 return USBD_IOERROR; 2011 2012 /* Root Hub */ 2013 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 2014 switch (ed->bEndpointAddress) { 2015 case USB_CONTROL_ENDPOINT: 2016 pipe->up_methods = &roothub_ctrl_methods; 2017 break; 2018 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2019 pipe->up_methods = &xhci_root_intr_methods; 2020 break; 2021 default: 2022 pipe->up_methods = NULL; 2023 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 2024 ed->bEndpointAddress, 0, 0, 0); 2025 return USBD_INVAL; 2026 } 2027 return USBD_NORMAL_COMPLETION; 2028 } 2029 2030 switch (xfertype) { 2031 case UE_CONTROL: 2032 pipe->up_methods = &xhci_device_ctrl_methods; 2033 break; 2034 case UE_ISOCHRONOUS: 2035 pipe->up_methods = &xhci_device_isoc_methods; 2036 return USBD_INVAL; 2037 break; 2038 case UE_BULK: 2039 pipe->up_methods = &xhci_device_bulk_methods; 2040 break; 2041 case UE_INTERRUPT: 2042 pipe->up_methods = &xhci_device_intr_methods; 2043 break; 2044 default: 2045 return USBD_IOERROR; 2046 break; 2047 } 2048 2049 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 2050 return xhci_configure_endpoint(pipe); 2051 2052 return USBD_NORMAL_COMPLETION; 2053 } 2054 2055 /* 2056 * Closes pipe, called from usbd_kill_pipe via close methods. 2057 * If the endpoint to be closed is ep0, disable_slot. 2058 * Should be called with sc_lock held. 2059 */ 2060 static void 2061 xhci_close_pipe(struct usbd_pipe *pipe) 2062 { 2063 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2064 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2065 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2066 const u_int dci = xhci_ep_get_dci(ed); 2067 struct xhci_soft_trb trb; 2068 uint32_t *cp; 2069 2070 XHCIHIST_FUNC(); 2071 2072 if (sc->sc_dying) 2073 return; 2074 2075 /* xs is uninitialized before xhci_init_slot */ 2076 if (xs == NULL || xs->xs_idx == 0) 2077 return; 2078 2079 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 2080 (uintptr_t)pipe, xs->xs_idx, dci, 0); 2081 2082 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2083 KASSERT(mutex_owned(&sc->sc_lock)); 2084 2085 if (pipe->up_dev->ud_depth == 0) 2086 return; 2087 2088 if (dci == XHCI_DCI_EP_CONTROL) { 2089 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 2090 xhci_disable_slot(sc, xs->xs_idx); 2091 return; 2092 } 2093 2094 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 2095 (void)xhci_stop_endpoint(pipe); 2096 2097 /* 2098 * set appropriate bit to be dropped. 2099 * don't set DC bit to 1, otherwise all endpoints 2100 * would be deconfigured. 2101 */ 2102 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2103 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 2104 cp[1] = htole32(0); 2105 2106 /* XXX should be most significant one, not dci? */ 2107 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2108 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 2109 2110 /* configure ep context performs an implicit dequeue */ 2111 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 2112 2113 /* sync input contexts before they are read from memory */ 2114 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2115 2116 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2117 trb.trb_2 = 0; 2118 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2119 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 2120 2121 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2122 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2123 } 2124 2125 /* 2126 * Abort transfer. 2127 * Should be called with sc_lock held. 2128 */ 2129 static void 2130 xhci_abortx(struct usbd_xfer *xfer) 2131 { 2132 XHCIHIST_FUNC(); 2133 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2134 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2135 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2136 2137 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx", 2138 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0); 2139 2140 KASSERT(mutex_owned(&sc->sc_lock)); 2141 ASSERT_SLEEPABLE(); 2142 2143 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2144 xfer->ux_status == USBD_TIMEOUT), 2145 "bad abort status: %d", xfer->ux_status); 2146 2147 /* 2148 * If we're dying, skip the hardware action and just notify the 2149 * software that we're done. 2150 */ 2151 if (sc->sc_dying) { 2152 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 2153 xfer->ux_status, 0, 0); 2154 goto dying; 2155 } 2156 2157 /* 2158 * HC Step 1: Stop execution of TD on the ring. 2159 */ 2160 switch (xhci_get_epstate(sc, xs, dci)) { 2161 case XHCI_EPSTATE_HALTED: 2162 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 2163 break; 2164 case XHCI_EPSTATE_STOPPED: 2165 break; 2166 default: 2167 (void)xhci_stop_endpoint(xfer->ux_pipe); 2168 break; 2169 } 2170 #ifdef DIAGNOSTIC 2171 uint32_t epst = xhci_get_epstate(sc, xs, dci); 2172 if (epst != XHCI_EPSTATE_STOPPED) 2173 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 2174 #endif 2175 2176 /* 2177 * HC Step 2: Remove any vestiges of the xfer from the ring. 2178 */ 2179 xhci_set_dequeue_locked(xfer->ux_pipe); 2180 2181 /* 2182 * Final Step: Notify completion to waiting xfers. 2183 */ 2184 dying: 2185 usb_transfer_complete(xfer); 2186 DPRINTFN(14, "end", 0, 0, 0, 0); 2187 2188 KASSERT(mutex_owned(&sc->sc_lock)); 2189 } 2190 2191 static void 2192 xhci_host_dequeue(struct xhci_ring * const xr) 2193 { 2194 /* When dequeueing the controller, update our struct copy too */ 2195 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 2196 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 2197 BUS_DMASYNC_PREWRITE); 2198 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 2199 2200 xr->xr_ep = 0; 2201 xr->xr_cs = 1; 2202 } 2203 2204 /* 2205 * Recover STALLed endpoint. 2206 * xHCI 1.1 sect 4.10.2.1 2207 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 2208 * all transfers on transfer ring. 2209 * These are done in thread context asynchronously. 2210 */ 2211 static void 2212 xhci_clear_endpoint_stall_async_task(void *cookie) 2213 { 2214 struct usbd_xfer * const xfer = cookie; 2215 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2216 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2217 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2218 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2219 2220 XHCIHIST_FUNC(); 2221 XHCIHIST_CALLARGS("xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 2222 dci, 0); 2223 2224 /* 2225 * XXXMRG: Stall task can run after slot is disabled when yanked. 2226 * This hack notices that the xs has been memset() in 2227 * xhci_disable_slot() and returns. Both xhci_reset_endpoint() 2228 * and xhci_set_dequeue() rely upon a valid ring setup for correct 2229 * operation, and the latter will fault, as would 2230 * usb_transfer_complete() if it got that far. 2231 */ 2232 if (xs->xs_idx == 0) { 2233 DPRINTFN(4, "ends xs_idx is 0", 0, 0, 0, 0); 2234 return; 2235 } 2236 2237 xhci_reset_endpoint(xfer->ux_pipe); 2238 xhci_set_dequeue(xfer->ux_pipe); 2239 2240 mutex_enter(&sc->sc_lock); 2241 tr->is_halted = false; 2242 usb_transfer_complete(xfer); 2243 mutex_exit(&sc->sc_lock); 2244 DPRINTFN(4, "ends", 0, 0, 0, 0); 2245 } 2246 2247 static usbd_status 2248 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 2249 { 2250 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2251 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 2252 2253 XHCIHIST_FUNC(); 2254 XHCIHIST_CALLARGS("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 2255 2256 if (sc->sc_dying) { 2257 return USBD_IOERROR; 2258 } 2259 2260 usb_init_task(&xp->xp_async_task, 2261 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 2262 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 2263 DPRINTFN(4, "ends", 0, 0, 0, 0); 2264 2265 return USBD_NORMAL_COMPLETION; 2266 } 2267 2268 /* Process roothub port status/change events and notify to uhub_intr. */ 2269 static void 2270 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 2271 { 2272 XHCIHIST_FUNC(); 2273 XHCIHIST_CALLARGS("xhci%jd: port %ju status change", 2274 device_unit(sc->sc_dev), ctlrport, 0, 0); 2275 2276 if (ctlrport > sc->sc_maxports) 2277 return; 2278 2279 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 2280 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 2281 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 2282 2283 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 2284 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 2285 2286 if (xfer == NULL) 2287 return; 2288 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2289 2290 uint8_t *p = xfer->ux_buf; 2291 memset(p, 0, xfer->ux_length); 2292 p[rhp / NBBY] |= 1 << (rhp % NBBY); 2293 xfer->ux_actlen = xfer->ux_length; 2294 xfer->ux_status = USBD_NORMAL_COMPLETION; 2295 usb_transfer_complete(xfer); 2296 } 2297 2298 /* Process Transfer Events */ 2299 static void 2300 xhci_event_transfer(struct xhci_softc * const sc, 2301 const struct xhci_trb * const trb) 2302 { 2303 uint64_t trb_0; 2304 uint32_t trb_2, trb_3; 2305 uint8_t trbcode; 2306 u_int slot, dci; 2307 struct xhci_slot *xs; 2308 struct xhci_ring *xr; 2309 struct xhci_xfer *xx; 2310 struct usbd_xfer *xfer; 2311 usbd_status err; 2312 2313 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2314 2315 trb_0 = le64toh(trb->trb_0); 2316 trb_2 = le32toh(trb->trb_2); 2317 trb_3 = le32toh(trb->trb_3); 2318 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 2319 slot = XHCI_TRB_3_SLOT_GET(trb_3); 2320 dci = XHCI_TRB_3_EP_GET(trb_3); 2321 xs = &sc->sc_slots[slot]; 2322 xr = &xs->xs_ep[dci].xe_tr; 2323 2324 /* sanity check */ 2325 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 2326 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 2327 2328 int idx = 0; 2329 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2330 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 2331 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 2332 return; 2333 } 2334 xx = xr->xr_cookies[idx]; 2335 2336 /* clear cookie of consumed TRB */ 2337 xr->xr_cookies[idx] = NULL; 2338 2339 /* 2340 * xx is NULL if pipe is opened but xfer is not started. 2341 * It happens when stopping idle pipe. 2342 */ 2343 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 2344 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 2345 idx, (uintptr_t)xx, trbcode, dci); 2346 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 2347 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 2348 0, 0); 2349 return; 2350 } 2351 } else { 2352 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 2353 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 2354 } 2355 /* XXX this may not happen */ 2356 if (xx == NULL) { 2357 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 2358 return; 2359 } 2360 xfer = &xx->xx_xfer; 2361 /* XXX this may happen when detaching */ 2362 if (xfer == NULL) { 2363 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 2364 (uintptr_t)xx, trb_0, 0, 0); 2365 return; 2366 } 2367 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 2368 /* XXX I dunno why this happens */ 2369 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 2370 2371 if (!xfer->ux_pipe->up_repeat && 2372 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 2373 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 2374 0, 0, 0); 2375 return; 2376 } 2377 2378 /* 4.11.5.2 Event Data TRB */ 2379 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2380 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 2381 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 2382 if ((trb_0 & 0x3) == 0x3) { 2383 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 2384 } 2385 } 2386 2387 switch (trbcode) { 2388 case XHCI_TRB_ERROR_SHORT_PKT: 2389 case XHCI_TRB_ERROR_SUCCESS: 2390 /* 2391 * A ctrl transfer can generate two events if it has a Data 2392 * stage. A short data stage can be OK and should not 2393 * complete the transfer as the status stage needs to be 2394 * performed. 2395 * 2396 * Note: Data and Status stage events point at same xfer. 2397 * ux_actlen and ux_dmabuf will be passed to 2398 * usb_transfer_complete after the Status stage event. 2399 * 2400 * It can be distingished which stage generates the event: 2401 * + by checking least 3 bits of trb_0 if ED==1. 2402 * (see xhci_device_ctrl_start). 2403 * + by checking the type of original TRB if ED==0. 2404 * 2405 * In addition, intr, bulk, and isoc transfer currently 2406 * consists of single TD, so the "skip" is not needed. 2407 * ctrl xfer uses EVENT_DATA, and others do not. 2408 * Thus driver can switch the flow by checking ED bit. 2409 */ 2410 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2411 if (xfer->ux_actlen == 0) 2412 xfer->ux_actlen = xfer->ux_length - 2413 XHCI_TRB_2_REM_GET(trb_2); 2414 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 2415 == XHCI_TRB_TYPE_DATA_STAGE) { 2416 return; 2417 } 2418 } else if ((trb_0 & 0x3) == 0x3) { 2419 return; 2420 } 2421 err = USBD_NORMAL_COMPLETION; 2422 break; 2423 case XHCI_TRB_ERROR_STOPPED: 2424 case XHCI_TRB_ERROR_LENGTH: 2425 case XHCI_TRB_ERROR_STOPPED_SHORT: 2426 err = USBD_IOERROR; 2427 break; 2428 case XHCI_TRB_ERROR_STALL: 2429 case XHCI_TRB_ERROR_BABBLE: 2430 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2431 xr->is_halted = true; 2432 /* 2433 * Try to claim this xfer for completion. If it has already 2434 * completed or aborted, drop it on the floor. 2435 */ 2436 if (!usbd_xfer_trycomplete(xfer)) 2437 return; 2438 2439 /* 2440 * Stalled endpoints can be recoverd by issuing 2441 * command TRB TYPE_RESET_EP on xHCI instead of 2442 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2443 * on the endpoint. However, this function may be 2444 * called from softint context (e.g. from umass), 2445 * in that case driver gets KASSERT in cv_timedwait 2446 * in xhci_do_command. 2447 * To avoid this, this runs reset_endpoint and 2448 * usb_transfer_complete in usb task thread 2449 * asynchronously (and then umass issues clear 2450 * UF_ENDPOINT_HALT). 2451 */ 2452 2453 /* Override the status. */ 2454 xfer->ux_status = USBD_STALLED; 2455 2456 xhci_clear_endpoint_stall_async(xfer); 2457 return; 2458 default: 2459 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2460 err = USBD_IOERROR; 2461 break; 2462 } 2463 2464 /* 2465 * Try to claim this xfer for completion. If it has already 2466 * completed or aborted, drop it on the floor. 2467 */ 2468 if (!usbd_xfer_trycomplete(xfer)) 2469 return; 2470 2471 /* Set the status. */ 2472 xfer->ux_status = err; 2473 2474 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2475 (trb_0 & 0x3) == 0x0) { 2476 usb_transfer_complete(xfer); 2477 } 2478 } 2479 2480 /* Process Command complete events */ 2481 static void 2482 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2483 { 2484 uint64_t trb_0; 2485 uint32_t trb_2, trb_3; 2486 2487 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2488 2489 KASSERT(mutex_owned(&sc->sc_lock)); 2490 2491 trb_0 = le64toh(trb->trb_0); 2492 trb_2 = le32toh(trb->trb_2); 2493 trb_3 = le32toh(trb->trb_3); 2494 2495 if (trb_0 == sc->sc_command_addr) { 2496 sc->sc_resultpending = false; 2497 2498 sc->sc_result_trb.trb_0 = trb_0; 2499 sc->sc_result_trb.trb_2 = trb_2; 2500 sc->sc_result_trb.trb_3 = trb_3; 2501 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2502 XHCI_TRB_ERROR_SUCCESS) { 2503 DPRINTFN(1, "command completion " 2504 "failure: 0x%016jx 0x%08jx 0x%08jx", 2505 trb_0, trb_2, trb_3, 0); 2506 } 2507 cv_signal(&sc->sc_command_cv); 2508 } else { 2509 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2510 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2511 } 2512 } 2513 2514 /* 2515 * Process events. 2516 * called from xhci_softintr 2517 */ 2518 static void 2519 xhci_handle_event(struct xhci_softc * const sc, 2520 const struct xhci_trb * const trb) 2521 { 2522 uint64_t trb_0; 2523 uint32_t trb_2, trb_3; 2524 2525 XHCIHIST_FUNC(); 2526 2527 trb_0 = le64toh(trb->trb_0); 2528 trb_2 = le32toh(trb->trb_2); 2529 trb_3 = le32toh(trb->trb_3); 2530 2531 XHCIHIST_CALLARGS("event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2532 (uintptr_t)trb, trb_0, trb_2, trb_3); 2533 2534 /* 2535 * 4.11.3.1, 6.4.2.1 2536 * TRB Pointer is invalid for these completion codes. 2537 */ 2538 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2539 case XHCI_TRB_ERROR_RING_UNDERRUN: 2540 case XHCI_TRB_ERROR_RING_OVERRUN: 2541 case XHCI_TRB_ERROR_VF_RING_FULL: 2542 return; 2543 default: 2544 if (trb_0 == 0) { 2545 return; 2546 } 2547 break; 2548 } 2549 2550 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2551 case XHCI_TRB_EVENT_TRANSFER: 2552 xhci_event_transfer(sc, trb); 2553 break; 2554 case XHCI_TRB_EVENT_CMD_COMPLETE: 2555 xhci_event_cmd(sc, trb); 2556 break; 2557 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2558 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2559 break; 2560 default: 2561 break; 2562 } 2563 } 2564 2565 static void 2566 xhci_softintr(void *v) 2567 { 2568 struct usbd_bus * const bus = v; 2569 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2570 struct xhci_ring * const er = &sc->sc_er; 2571 struct xhci_trb *trb; 2572 int i, j, k; 2573 2574 XHCIHIST_FUNC(); 2575 2576 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2577 2578 i = er->xr_ep; 2579 j = er->xr_cs; 2580 2581 XHCIHIST_CALLARGS("er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2582 2583 while (1) { 2584 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2585 BUS_DMASYNC_POSTREAD); 2586 trb = &er->xr_trb[i]; 2587 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2588 2589 if (j != k) 2590 break; 2591 2592 xhci_handle_event(sc, trb); 2593 2594 i++; 2595 if (i == er->xr_ntrb) { 2596 i = 0; 2597 j ^= 1; 2598 } 2599 } 2600 2601 er->xr_ep = i; 2602 er->xr_cs = j; 2603 2604 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2605 XHCI_ERDP_LO_BUSY); 2606 2607 DPRINTFN(16, "ends", 0, 0, 0, 0); 2608 2609 return; 2610 } 2611 2612 static void 2613 xhci_poll(struct usbd_bus *bus) 2614 { 2615 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2616 2617 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2618 2619 mutex_enter(&sc->sc_intr_lock); 2620 int ret = xhci_intr1(sc); 2621 if (ret) { 2622 xhci_softintr(bus); 2623 } 2624 mutex_exit(&sc->sc_intr_lock); 2625 2626 return; 2627 } 2628 2629 static struct usbd_xfer * 2630 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2631 { 2632 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2633 struct usbd_xfer *xfer; 2634 2635 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2636 2637 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2638 if (xfer != NULL) { 2639 memset(xfer, 0, sizeof(struct xhci_xfer)); 2640 #ifdef DIAGNOSTIC 2641 xfer->ux_state = XFER_BUSY; 2642 #endif 2643 } 2644 2645 return xfer; 2646 } 2647 2648 static void 2649 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2650 { 2651 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2652 2653 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2654 2655 #ifdef DIAGNOSTIC 2656 if (xfer->ux_state != XFER_BUSY && 2657 xfer->ux_status != USBD_NOT_STARTED) { 2658 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2659 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2660 } 2661 xfer->ux_state = XFER_FREE; 2662 #endif 2663 pool_cache_put(sc->sc_xferpool, xfer); 2664 } 2665 2666 static bool 2667 xhci_dying(struct usbd_bus *bus) 2668 { 2669 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2670 2671 return sc->sc_dying; 2672 } 2673 2674 static void 2675 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2676 { 2677 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2678 2679 *lock = &sc->sc_lock; 2680 } 2681 2682 extern uint32_t usb_cookie_no; 2683 2684 /* 2685 * xHCI 4.3 2686 * Called when uhub_explore finds a new device (via usbd_new_device). 2687 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2688 * This function does: 2689 * Allocate and construct dev structure of default endpoint (ep0). 2690 * Allocate and open pipe of ep0. 2691 * Enable slot and initialize slot context. 2692 * Set Address. 2693 * Read initial device descriptor. 2694 * Determine initial MaxPacketSize (mps) by speed. 2695 * Read full device descriptor. 2696 * Register this device. 2697 * Finally state of device transitions ADDRESSED. 2698 */ 2699 static usbd_status 2700 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2701 int speed, int port, struct usbd_port *up) 2702 { 2703 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2704 struct usbd_device *dev; 2705 usbd_status err; 2706 usb_device_descriptor_t *dd; 2707 struct xhci_slot *xs; 2708 uint32_t *cp; 2709 2710 XHCIHIST_FUNC(); 2711 XHCIHIST_CALLARGS("port %ju depth %ju speed %ju up %#jx", 2712 port, depth, speed, (uintptr_t)up); 2713 2714 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2715 dev->ud_bus = bus; 2716 dev->ud_quirks = &usbd_no_quirk; 2717 dev->ud_addr = 0; 2718 dev->ud_ddesc.bMaxPacketSize = 0; 2719 dev->ud_depth = depth; 2720 dev->ud_powersrc = up; 2721 dev->ud_myhub = up->up_parent; 2722 dev->ud_speed = speed; 2723 dev->ud_langid = USBD_NOLANG; 2724 dev->ud_cookie.cookie = ++usb_cookie_no; 2725 2726 /* Set up default endpoint handle. */ 2727 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2728 /* doesn't matter, just don't let it uninitialized */ 2729 dev->ud_ep0.ue_toggle = 0; 2730 2731 /* Set up default endpoint descriptor. */ 2732 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2733 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2734 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2735 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2736 dev->ud_ep0desc.bInterval = 0; 2737 2738 /* 4.3, 4.8.2.1 */ 2739 switch (speed) { 2740 case USB_SPEED_SUPER: 2741 case USB_SPEED_SUPER_PLUS: 2742 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2743 break; 2744 case USB_SPEED_FULL: 2745 /* XXX using 64 as initial mps of ep0 in FS */ 2746 case USB_SPEED_HIGH: 2747 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2748 break; 2749 case USB_SPEED_LOW: 2750 default: 2751 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2752 break; 2753 } 2754 2755 up->up_dev = dev; 2756 2757 /* Establish the default pipe. */ 2758 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2759 &dev->ud_pipe0); 2760 if (err) { 2761 goto bad; 2762 } 2763 2764 dd = &dev->ud_ddesc; 2765 2766 if (depth == 0 && port == 0) { 2767 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2768 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2769 err = usbd_get_initial_ddesc(dev, dd); 2770 if (err) { 2771 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2772 goto bad; 2773 } 2774 2775 err = usbd_reload_device_desc(dev); 2776 if (err) { 2777 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2778 goto bad; 2779 } 2780 } else { 2781 uint8_t slot = 0; 2782 2783 /* 4.3.2 */ 2784 err = xhci_enable_slot(sc, &slot); 2785 if (err) { 2786 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2787 goto bad; 2788 } 2789 2790 xs = &sc->sc_slots[slot]; 2791 dev->ud_hcpriv = xs; 2792 2793 /* 4.3.3 initialize slot structure */ 2794 err = xhci_init_slot(dev, slot); 2795 if (err) { 2796 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2797 dev->ud_hcpriv = NULL; 2798 /* 2799 * We have to disable_slot here because 2800 * xs->xs_idx == 0 when xhci_init_slot fails, 2801 * in that case usbd_remove_dev won't work. 2802 */ 2803 mutex_enter(&sc->sc_lock); 2804 xhci_disable_slot(sc, slot); 2805 mutex_exit(&sc->sc_lock); 2806 goto bad; 2807 } 2808 2809 /* 4.3.4 Address Assignment */ 2810 err = xhci_set_address(dev, slot, false); 2811 if (err) { 2812 DPRINTFN(1, "failed! to set address: %ju", err, 0, 0, 0); 2813 goto bad; 2814 } 2815 2816 /* Allow device time to set new address */ 2817 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2818 2819 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2820 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2821 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2822 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2823 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2824 /* 2825 * XXX ensure we know when the hardware does something 2826 * we can't yet cope with 2827 */ 2828 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2829 dev->ud_addr = addr; 2830 2831 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2832 "addr %d already allocated", dev->ud_addr); 2833 /* 2834 * The root hub is given its own slot 2835 */ 2836 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2837 2838 err = usbd_get_initial_ddesc(dev, dd); 2839 if (err) { 2840 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2841 goto bad; 2842 } 2843 2844 /* 4.8.2.1 */ 2845 if (USB_IS_SS(speed)) { 2846 if (dd->bMaxPacketSize != 9) { 2847 printf("%s: invalid mps 2^%u for SS ep0," 2848 " using 512\n", 2849 device_xname(sc->sc_dev), 2850 dd->bMaxPacketSize); 2851 dd->bMaxPacketSize = 9; 2852 } 2853 USETW(dev->ud_ep0desc.wMaxPacketSize, 2854 (1 << dd->bMaxPacketSize)); 2855 } else 2856 USETW(dev->ud_ep0desc.wMaxPacketSize, 2857 dd->bMaxPacketSize); 2858 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2859 err = xhci_update_ep0_mps(sc, xs, 2860 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2861 if (err) { 2862 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2863 goto bad; 2864 } 2865 2866 err = usbd_reload_device_desc(dev); 2867 if (err) { 2868 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2869 goto bad; 2870 } 2871 } 2872 2873 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2874 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2875 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2876 dd->bDeviceClass, dd->bDeviceSubClass, 2877 dd->bDeviceProtocol, 0); 2878 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2879 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2880 dev->ud_speed); 2881 2882 usbd_get_device_strings(dev); 2883 2884 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2885 2886 if (depth == 0 && port == 0) { 2887 usbd_attach_roothub(parent, dev); 2888 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2889 return USBD_NORMAL_COMPLETION; 2890 } 2891 2892 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2893 bad: 2894 if (err != USBD_NORMAL_COMPLETION) { 2895 usbd_remove_device(dev, up); 2896 } 2897 2898 return err; 2899 } 2900 2901 static usbd_status 2902 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2903 size_t ntrb, size_t align) 2904 { 2905 usbd_status err; 2906 size_t size = ntrb * XHCI_TRB_SIZE; 2907 2908 XHCIHIST_FUNC(); 2909 XHCIHIST_CALLARGS("xr %#jx ntrb %#jx align %#jx", 2910 (uintptr_t)xr, ntrb, align, 0); 2911 2912 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2913 if (err) 2914 return err; 2915 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2916 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2917 xr->xr_trb = xhci_ring_trbv(xr, 0); 2918 xr->xr_ntrb = ntrb; 2919 xr->is_halted = false; 2920 xhci_host_dequeue(xr); 2921 2922 return USBD_NORMAL_COMPLETION; 2923 } 2924 2925 static void 2926 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2927 { 2928 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2929 mutex_destroy(&xr->xr_lock); 2930 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2931 } 2932 2933 static void 2934 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2935 void *cookie, struct xhci_soft_trb * const trbs, size_t ntrbs) 2936 { 2937 size_t i; 2938 u_int ri; 2939 u_int cs; 2940 uint64_t parameter; 2941 uint32_t status; 2942 uint32_t control; 2943 2944 XHCIHIST_FUNC(); 2945 XHCIHIST_CALLARGS("%#jx xr_ep 0x%jx xr_cs %ju", 2946 (uintptr_t)xr, xr->xr_ep, xr->xr_cs, 0); 2947 2948 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2949 for (i = 0; i < ntrbs; i++) { 2950 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2951 (uintptr_t)trbs, i, 0); 2952 DPRINTFN(12, " %016jx %08jx %08jx", 2953 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2954 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2955 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2956 } 2957 2958 ri = xr->xr_ep; 2959 cs = xr->xr_cs; 2960 2961 /* 2962 * Although the xhci hardware can do scatter/gather dma from 2963 * arbitrary sized buffers, there is a non-obvious restriction 2964 * that a LINK trb is only allowed at the end of a burst of 2965 * transfers - which might be 16kB. 2966 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2967 * The simple solution is not to allow a LINK trb in the middle 2968 * of anything - as here. 2969 * XXX: (dsl) There are xhci controllers out there (eg some made by 2970 * ASMedia) that seem to lock up if they process a LINK trb but 2971 * cannot process the linked-to trb yet. 2972 * The code should write the 'cycle' bit on the link trb AFTER 2973 * adding the other trb. 2974 */ 2975 u_int firstep = xr->xr_ep; 2976 u_int firstcs = xr->xr_cs; 2977 2978 for (i = 0; i < ntrbs; ) { 2979 u_int oldri = ri; 2980 u_int oldcs = cs; 2981 2982 if (ri >= (xr->xr_ntrb - 1)) { 2983 /* Put Link TD at the end of ring */ 2984 parameter = xhci_ring_trbp(xr, 0); 2985 status = 0; 2986 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2987 XHCI_TRB_3_TC_BIT; 2988 xr->xr_cookies[ri] = NULL; 2989 xr->xr_ep = 0; 2990 xr->xr_cs ^= 1; 2991 ri = xr->xr_ep; 2992 cs = xr->xr_cs; 2993 } else { 2994 parameter = trbs[i].trb_0; 2995 status = trbs[i].trb_2; 2996 control = trbs[i].trb_3; 2997 2998 xr->xr_cookies[ri] = cookie; 2999 ri++; 3000 i++; 3001 } 3002 /* 3003 * If this is a first TRB, mark it invalid to prevent 3004 * xHC from running it immediately. 3005 */ 3006 if (oldri == firstep) { 3007 if (oldcs) { 3008 control &= ~XHCI_TRB_3_CYCLE_BIT; 3009 } else { 3010 control |= XHCI_TRB_3_CYCLE_BIT; 3011 } 3012 } else { 3013 if (oldcs) { 3014 control |= XHCI_TRB_3_CYCLE_BIT; 3015 } else { 3016 control &= ~XHCI_TRB_3_CYCLE_BIT; 3017 } 3018 } 3019 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 3020 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 3021 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3022 } 3023 3024 /* Now invert cycle bit of first TRB */ 3025 if (firstcs) { 3026 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 3027 } else { 3028 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 3029 } 3030 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 3031 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3032 3033 xr->xr_ep = ri; 3034 xr->xr_cs = cs; 3035 3036 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 3037 xr->xr_cs, 0); 3038 } 3039 3040 /* 3041 * Stop execution commands, purge all commands on command ring, and 3042 * rewind dequeue pointer. 3043 */ 3044 static void 3045 xhci_abort_command(struct xhci_softc *sc) 3046 { 3047 struct xhci_ring * const cr = &sc->sc_cr; 3048 uint64_t crcr; 3049 int i; 3050 3051 XHCIHIST_FUNC(); 3052 XHCIHIST_CALLARGS("command %#jx timeout, aborting", 3053 sc->sc_command_addr, 0, 0, 0); 3054 3055 mutex_enter(&cr->xr_lock); 3056 3057 /* 4.6.1.2 Aborting a Command */ 3058 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3059 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 3060 3061 for (i = 0; i < 500; i++) { 3062 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3063 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 3064 break; 3065 usb_delay_ms(&sc->sc_bus, 1); 3066 } 3067 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 3068 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 3069 /* reset HC here? */ 3070 } 3071 3072 /* reset command ring dequeue pointer */ 3073 cr->xr_ep = 0; 3074 cr->xr_cs = 1; 3075 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 3076 3077 mutex_exit(&cr->xr_lock); 3078 } 3079 3080 /* 3081 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 3082 * Command completion is notified by cv_signal from xhci_event_cmd() 3083 * (called from xhci_softint), or timed-out. 3084 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 3085 * then do_command examines it. 3086 */ 3087 static usbd_status 3088 xhci_do_command_locked(struct xhci_softc * const sc, 3089 struct xhci_soft_trb * const trb, int timeout) 3090 { 3091 struct xhci_ring * const cr = &sc->sc_cr; 3092 usbd_status err; 3093 3094 XHCIHIST_FUNC(); 3095 XHCIHIST_CALLARGS("input: 0x%016jx 0x%08jx 0x%08jx", 3096 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3097 3098 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 3099 KASSERT(mutex_owned(&sc->sc_lock)); 3100 3101 while (sc->sc_command_addr != 0 || 3102 (sc->sc_suspender != NULL && sc->sc_suspender != curlwp)) 3103 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 3104 3105 /* 3106 * If enqueue pointer points at last of ring, it's Link TRB, 3107 * command TRB will be stored in 0th TRB. 3108 */ 3109 if (cr->xr_ep == cr->xr_ntrb - 1) 3110 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 3111 else 3112 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 3113 3114 sc->sc_resultpending = true; 3115 3116 mutex_enter(&cr->xr_lock); 3117 xhci_ring_put(sc, cr, NULL, trb, 1); 3118 mutex_exit(&cr->xr_lock); 3119 3120 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 3121 3122 while (sc->sc_resultpending) { 3123 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 3124 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 3125 xhci_abort_command(sc); 3126 err = USBD_TIMEOUT; 3127 goto timedout; 3128 } 3129 } 3130 3131 trb->trb_0 = sc->sc_result_trb.trb_0; 3132 trb->trb_2 = sc->sc_result_trb.trb_2; 3133 trb->trb_3 = sc->sc_result_trb.trb_3; 3134 3135 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 3136 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3137 3138 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 3139 case XHCI_TRB_ERROR_SUCCESS: 3140 err = USBD_NORMAL_COMPLETION; 3141 break; 3142 default: 3143 case 192 ... 223: 3144 DPRINTFN(5, "error %x", 3145 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0); 3146 err = USBD_IOERROR; 3147 break; 3148 case 224 ... 255: 3149 err = USBD_NORMAL_COMPLETION; 3150 break; 3151 } 3152 3153 timedout: 3154 sc->sc_resultpending = false; 3155 sc->sc_command_addr = 0; 3156 cv_broadcast(&sc->sc_cmdbusy_cv); 3157 3158 return err; 3159 } 3160 3161 static usbd_status 3162 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb, 3163 int timeout) 3164 { 3165 3166 mutex_enter(&sc->sc_lock); 3167 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 3168 mutex_exit(&sc->sc_lock); 3169 3170 return ret; 3171 } 3172 3173 static usbd_status 3174 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 3175 { 3176 struct xhci_soft_trb trb; 3177 usbd_status err; 3178 3179 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3180 3181 trb.trb_0 = 0; 3182 trb.trb_2 = 0; 3183 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 3184 3185 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3186 if (err != USBD_NORMAL_COMPLETION) { 3187 return err; 3188 } 3189 3190 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 3191 3192 return err; 3193 } 3194 3195 /* 3196 * xHCI 4.6.4 3197 * Deallocate ring and device/input context DMA buffers, and disable_slot. 3198 * All endpoints in the slot should be stopped. 3199 * Should be called with sc_lock held. 3200 */ 3201 static usbd_status 3202 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 3203 { 3204 struct xhci_soft_trb trb; 3205 struct xhci_slot *xs; 3206 usbd_status err; 3207 3208 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3209 3210 if (sc->sc_dying) 3211 return USBD_IOERROR; 3212 3213 trb.trb_0 = 0; 3214 trb.trb_2 = 0; 3215 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) | 3216 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT); 3217 3218 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 3219 3220 if (!err) { 3221 xs = &sc->sc_slots[slot]; 3222 if (xs->xs_idx != 0) { 3223 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 3224 xhci_set_dcba(sc, 0, slot); 3225 memset(xs, 0, sizeof(*xs)); 3226 } 3227 } 3228 3229 return err; 3230 } 3231 3232 /* 3233 * Set address of device and transition slot state from ENABLED to ADDRESSED 3234 * if Block Setaddress Request (BSR) is false. 3235 * If BSR==true, transition slot state from ENABLED to DEFAULT. 3236 * see xHCI 1.1 4.5.3, 3.3.4 3237 * Should be called without sc_lock held. 3238 */ 3239 static usbd_status 3240 xhci_address_device(struct xhci_softc * const sc, 3241 uint64_t icp, uint8_t slot_id, bool bsr) 3242 { 3243 struct xhci_soft_trb trb; 3244 usbd_status err; 3245 3246 XHCIHIST_FUNC(); 3247 if (bsr) { 3248 XHCIHIST_CALLARGS("icp %jx slot %jx with bsr", 3249 icp, slot_id, 0, 0); 3250 } else { 3251 XHCIHIST_CALLARGS("icp %jx slot %jx nobsr", 3252 icp, slot_id, 0, 0); 3253 } 3254 3255 trb.trb_0 = icp; 3256 trb.trb_2 = 0; 3257 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 3258 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 3259 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 3260 3261 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3262 3263 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 3264 err = USBD_NO_ADDR; 3265 3266 return err; 3267 } 3268 3269 static usbd_status 3270 xhci_update_ep0_mps(struct xhci_softc * const sc, 3271 struct xhci_slot * const xs, u_int mps) 3272 { 3273 struct xhci_soft_trb trb; 3274 usbd_status err; 3275 uint32_t * cp; 3276 3277 XHCIHIST_FUNC(); 3278 XHCIHIST_CALLARGS("slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 3279 3280 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3281 cp[0] = htole32(0); 3282 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 3283 3284 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 3285 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 3286 3287 /* sync input contexts before they are read from memory */ 3288 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3289 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3290 sc->sc_ctxsz * 4); 3291 3292 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 3293 trb.trb_2 = 0; 3294 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 3295 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 3296 3297 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3298 return err; 3299 } 3300 3301 static void 3302 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 3303 { 3304 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 3305 3306 XHCIHIST_FUNC(); 3307 XHCIHIST_CALLARGS("dcbaa %#jx dc %016jx slot %jd", 3308 (uintptr_t)&dcbaa[si], dcba, si, 0); 3309 3310 dcbaa[si] = htole64(dcba); 3311 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 3312 BUS_DMASYNC_PREWRITE); 3313 } 3314 3315 /* 3316 * Allocate device and input context DMA buffer, and 3317 * TRB DMA buffer for each endpoint. 3318 */ 3319 static usbd_status 3320 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 3321 { 3322 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3323 struct xhci_slot *xs; 3324 usbd_status err; 3325 u_int dci; 3326 3327 XHCIHIST_FUNC(); 3328 XHCIHIST_CALLARGS("slot %ju", slot, 0, 0, 0); 3329 3330 xs = &sc->sc_slots[slot]; 3331 3332 /* allocate contexts */ 3333 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 3334 &xs->xs_dc_dma); 3335 if (err) 3336 return err; 3337 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 3338 3339 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 3340 &xs->xs_ic_dma); 3341 if (err) 3342 goto bad1; 3343 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 3344 3345 for (dci = 0; dci < 32; dci++) { 3346 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 3347 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 3348 if (dci == XHCI_DCI_SLOT) 3349 continue; 3350 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 3351 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 3352 if (err) { 3353 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 3354 goto bad2; 3355 } 3356 } 3357 3358 bad2: 3359 if (err == USBD_NORMAL_COMPLETION) { 3360 xs->xs_idx = slot; 3361 } else { 3362 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 3363 } 3364 3365 return err; 3366 3367 bad1: 3368 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3369 xs->xs_idx = 0; 3370 return err; 3371 } 3372 3373 static void 3374 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 3375 int end_dci) 3376 { 3377 u_int dci; 3378 3379 XHCIHIST_FUNC(); 3380 XHCIHIST_CALLARGS("slot %ju start %ju end %ju", 3381 xs->xs_idx, start_dci, end_dci, 0); 3382 3383 for (dci = start_dci; dci < end_dci; dci++) { 3384 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 3385 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 3386 } 3387 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 3388 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3389 xs->xs_idx = 0; 3390 } 3391 3392 /* 3393 * Setup slot context, set Device Context Base Address, and issue 3394 * Set Address Device command. 3395 */ 3396 static usbd_status 3397 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 3398 { 3399 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3400 struct xhci_slot *xs; 3401 usbd_status err; 3402 3403 XHCIHIST_FUNC(); 3404 XHCIHIST_CALLARGS("slot %ju bsr %ju", slot, bsr, 0, 0); 3405 3406 xs = &sc->sc_slots[slot]; 3407 3408 xhci_setup_ctx(dev->ud_pipe0); 3409 3410 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3411 sc->sc_ctxsz * 3); 3412 3413 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3414 3415 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3416 3417 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3418 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 3419 sc->sc_ctxsz * 2); 3420 3421 return err; 3422 } 3423 3424 /* 3425 * 4.8.2, 6.2.3.2 3426 * construct slot/endpoint context parameters and do syncmem 3427 */ 3428 static void 3429 xhci_setup_ctx(struct usbd_pipe *pipe) 3430 { 3431 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3432 struct usbd_device *dev = pipe->up_dev; 3433 struct xhci_slot * const xs = dev->ud_hcpriv; 3434 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3435 const u_int dci = xhci_ep_get_dci(ed); 3436 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3437 uint32_t *cp; 3438 uint16_t mps = UGETW(ed->wMaxPacketSize); 3439 uint8_t speed = dev->ud_speed; 3440 uint8_t ival = ed->bInterval; 3441 3442 XHCIHIST_FUNC(); 3443 XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju", 3444 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3445 3446 /* set up initial input control context */ 3447 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3448 cp[0] = htole32(0); 3449 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3450 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3451 cp[7] = htole32(0); 3452 3453 /* set up input slot context */ 3454 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3455 cp[0] = 3456 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3457 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3458 cp[1] = 0; 3459 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3460 cp[3] = 0; 3461 xhci_setup_route(pipe, cp); 3462 xhci_setup_tthub(pipe, cp); 3463 3464 cp[0] = htole32(cp[0]); 3465 cp[1] = htole32(cp[1]); 3466 cp[2] = htole32(cp[2]); 3467 cp[3] = htole32(cp[3]); 3468 3469 /* set up input endpoint context */ 3470 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3471 cp[0] = 3472 XHCI_EPCTX_0_EPSTATE_SET(0) | 3473 XHCI_EPCTX_0_MULT_SET(0) | 3474 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3475 XHCI_EPCTX_0_LSA_SET(0) | 3476 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3477 cp[1] = 3478 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3479 XHCI_EPCTX_1_HID_SET(0) | 3480 XHCI_EPCTX_1_MAXB_SET(0); 3481 3482 if (xfertype != UE_ISOCHRONOUS) 3483 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3484 3485 if (xfertype == UE_CONTROL) 3486 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3487 else if (USB_IS_SS(speed)) 3488 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3489 else 3490 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3491 3492 xhci_setup_maxburst(pipe, cp); 3493 3494 switch (xfertype) { 3495 case UE_CONTROL: 3496 break; 3497 case UE_BULK: 3498 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3499 break; 3500 case UE_INTERRUPT: 3501 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3502 ival = pipe->up_interval; 3503 3504 ival = xhci_bival2ival(ival, speed); 3505 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3506 break; 3507 case UE_ISOCHRONOUS: 3508 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3509 ival = pipe->up_interval; 3510 3511 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3512 if (speed == USB_SPEED_FULL) 3513 ival += 3; /* 1ms -> 125us */ 3514 ival--; 3515 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3516 break; 3517 default: 3518 break; 3519 } 3520 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3521 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3522 3523 /* rewind TR dequeue pointer in xHC */ 3524 /* can't use xhci_ep_get_dci() yet? */ 3525 *(uint64_t *)(&cp[2]) = htole64( 3526 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3527 XHCI_EPCTX_2_DCS_SET(1)); 3528 3529 cp[0] = htole32(cp[0]); 3530 cp[1] = htole32(cp[1]); 3531 cp[4] = htole32(cp[4]); 3532 3533 /* rewind TR dequeue pointer in driver */ 3534 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3535 mutex_enter(&xr->xr_lock); 3536 xhci_host_dequeue(xr); 3537 mutex_exit(&xr->xr_lock); 3538 3539 /* sync input contexts before they are read from memory */ 3540 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3541 } 3542 3543 /* 3544 * Setup route string and roothub port of given device for slot context 3545 */ 3546 static void 3547 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3548 { 3549 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3550 struct usbd_device *dev = pipe->up_dev; 3551 struct usbd_port *up = dev->ud_powersrc; 3552 struct usbd_device *hub; 3553 struct usbd_device *adev; 3554 uint8_t rhport = 0; 3555 uint32_t route = 0; 3556 3557 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3558 3559 /* Locate root hub port and Determine route string */ 3560 /* 4.3.3 route string does not include roothub port */ 3561 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3562 uint32_t dep; 3563 3564 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3565 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3566 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3567 -1); 3568 3569 if (hub->ud_powersrc == NULL) 3570 break; 3571 dep = hub->ud_depth; 3572 if (dep == 0) 3573 break; 3574 rhport = hub->ud_powersrc->up_portno; 3575 if (dep > USB_HUB_MAX_DEPTH) 3576 continue; 3577 3578 route |= 3579 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3580 << ((dep - 1) * 4); 3581 } 3582 route = route >> 4; 3583 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3584 3585 /* Locate port on upstream high speed hub */ 3586 for (adev = dev, hub = up->up_parent; 3587 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3588 adev = hub, hub = hub->ud_myhub) 3589 ; 3590 if (hub) { 3591 int p; 3592 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3593 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3594 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3595 goto found; 3596 } 3597 } 3598 panic("%s: cannot find HS port", __func__); 3599 found: 3600 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3601 } else { 3602 dev->ud_myhsport = NULL; 3603 } 3604 3605 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3606 3607 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3608 ctlrport, route, (uintptr_t)hub); 3609 3610 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3611 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3612 } 3613 3614 /* 3615 * Setup whether device is hub, whether device uses MTT, and 3616 * TT informations if it uses MTT. 3617 */ 3618 static void 3619 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3620 { 3621 struct usbd_device *dev = pipe->up_dev; 3622 struct usbd_port *myhsport = dev->ud_myhsport; 3623 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3624 uint32_t speed = dev->ud_speed; 3625 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3626 uint8_t tthubslot, ttportnum; 3627 bool ishub; 3628 bool usemtt; 3629 3630 XHCIHIST_FUNC(); 3631 3632 /* 3633 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3634 * tthubslot: 3635 * This is the slot ID of parent HS hub 3636 * if LS/FS device is connected && connected through HS hub. 3637 * This is 0 if device is not LS/FS device || 3638 * parent hub is not HS hub || 3639 * attached to root hub. 3640 * ttportnum: 3641 * This is the downstream facing port of parent HS hub 3642 * if LS/FS device is connected. 3643 * This is 0 if device is not LS/FS device || 3644 * parent hub is not HS hub || 3645 * attached to root hub. 3646 */ 3647 if (myhsport && 3648 myhsport->up_parent->ud_addr != rhaddr && 3649 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3650 ttportnum = myhsport->up_portno; 3651 tthubslot = myhsport->up_parent->ud_addr; 3652 } else { 3653 ttportnum = 0; 3654 tthubslot = 0; 3655 } 3656 XHCIHIST_CALLARGS("myhsport %#jx ttportnum=%jd tthubslot=%jd", 3657 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3658 3659 /* ishub is valid after reading UDESC_DEVICE */ 3660 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3661 3662 /* dev->ud_hub is valid after reading UDESC_HUB */ 3663 if (ishub && dev->ud_hub) { 3664 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3665 uint8_t ttt = 3666 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3667 3668 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3669 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3670 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3671 } 3672 3673 #define IS_MTTHUB(dd) \ 3674 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3675 3676 /* 3677 * MTT flag is set if 3678 * 1. this is HS hub && MTTs are supported and enabled; or 3679 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3680 * are supported and enabled. 3681 * 3682 * XXX enabled is not tested yet 3683 */ 3684 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3685 usemtt = true; 3686 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3687 myhsport && 3688 myhsport->up_parent->ud_addr != rhaddr && 3689 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3690 usemtt = true; 3691 else 3692 usemtt = false; 3693 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3694 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3695 3696 #undef IS_MTTHUB 3697 3698 cp[0] |= 3699 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3700 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3701 cp[2] |= 3702 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3703 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3704 } 3705 3706 /* set up params for periodic endpoint */ 3707 static void 3708 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3709 { 3710 struct usbd_device *dev = pipe->up_dev; 3711 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3712 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3713 usbd_desc_iter_t iter; 3714 const usb_cdc_descriptor_t *cdcd; 3715 uint32_t maxb = 0; 3716 uint16_t mps = UGETW(ed->wMaxPacketSize); 3717 uint8_t speed = dev->ud_speed; 3718 uint8_t ep; 3719 3720 /* config desc is NULL when opening ep0 */ 3721 if (dev == NULL || dev->ud_cdesc == NULL) 3722 goto no_cdcd; 3723 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3724 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3725 if (cdcd == NULL) 3726 goto no_cdcd; 3727 usb_desc_iter_init(dev, &iter); 3728 iter.cur = (const void *)cdcd; 3729 3730 /* find endpoint_ss_comp desc for ep of this pipe */ 3731 for (ep = 0;;) { 3732 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3733 if (cdcd == NULL) 3734 break; 3735 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3736 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3737 bEndpointAddress; 3738 if (UE_GET_ADDR(ep) == 3739 UE_GET_ADDR(ed->bEndpointAddress)) { 3740 cdcd = (const usb_cdc_descriptor_t *) 3741 usb_desc_iter_next(&iter); 3742 break; 3743 } 3744 ep = 0; 3745 } 3746 } 3747 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3748 const usb_endpoint_ss_comp_descriptor_t * esscd = 3749 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3750 maxb = esscd->bMaxBurst; 3751 } 3752 3753 no_cdcd: 3754 /* 6.2.3.4, 4.8.2.4 */ 3755 if (USB_IS_SS(speed)) { 3756 /* USB 3.1 9.6.6 */ 3757 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3758 /* USB 3.1 9.6.7 */ 3759 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3760 #ifdef notyet 3761 if (xfertype == UE_ISOCHRONOUS) { 3762 } 3763 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3764 /* use ESIT */ 3765 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3766 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3767 3768 /* XXX if LEC = 1, set ESIT instead */ 3769 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3770 } else { 3771 /* use ival */ 3772 } 3773 #endif 3774 } else { 3775 /* USB 2.0 9.6.6 */ 3776 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3777 3778 /* 6.2.3.4 */ 3779 if (speed == USB_SPEED_HIGH && 3780 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3781 maxb = UE_GET_TRANS(mps); 3782 } else { 3783 /* LS/FS or HS CTRL or HS BULK */ 3784 maxb = 0; 3785 } 3786 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3787 } 3788 } 3789 3790 /* 3791 * Convert endpoint bInterval value to endpoint context interval value 3792 * for Interrupt pipe. 3793 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3794 */ 3795 static uint32_t 3796 xhci_bival2ival(uint32_t ival, uint32_t speed) 3797 { 3798 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3799 int i; 3800 3801 /* 3802 * round ival down to "the nearest base 2 multiple of 3803 * bInterval * 8". 3804 * bInterval is at most 255 as its type is uByte. 3805 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3806 */ 3807 for (i = 10; i > 0; i--) { 3808 if ((ival * 8) >= (1 << i)) 3809 break; 3810 } 3811 ival = i; 3812 } else { 3813 /* Interval = bInterval-1 for SS/HS */ 3814 ival--; 3815 } 3816 3817 return ival; 3818 } 3819 3820 /* ----- */ 3821 3822 static void 3823 xhci_noop(struct usbd_pipe *pipe) 3824 { 3825 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3826 } 3827 3828 /* 3829 * Process root hub request. 3830 */ 3831 static int 3832 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3833 void *buf, int buflen) 3834 { 3835 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3836 usb_port_status_t ps; 3837 int l, totlen = 0; 3838 uint16_t len, value, index; 3839 int port, i; 3840 uint32_t v; 3841 3842 XHCIHIST_FUNC(); 3843 3844 if (sc->sc_dying) 3845 return -1; 3846 3847 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3848 3849 len = UGETW(req->wLength); 3850 value = UGETW(req->wValue); 3851 index = UGETW(req->wIndex); 3852 3853 XHCIHIST_CALLARGS("rhreq: %04jx %04jx %04jx %04jx", 3854 req->bmRequestType | (req->bRequest << 8), value, index, len); 3855 3856 #define C(x,y) ((x) | ((y) << 8)) 3857 switch (C(req->bRequest, req->bmRequestType)) { 3858 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3859 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3860 if (len == 0) 3861 break; 3862 switch (value) { 3863 #define sd ((usb_string_descriptor_t *)buf) 3864 case C(2, UDESC_STRING): 3865 /* Product */ 3866 totlen = usb_makestrdesc(sd, len, "xHCI root hub"); 3867 break; 3868 #undef sd 3869 default: 3870 /* default from usbroothub */ 3871 return buflen; 3872 } 3873 break; 3874 3875 /* Hub requests */ 3876 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3877 break; 3878 /* Clear Port Feature request */ 3879 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3880 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3881 3882 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3883 index, value, bn, cp); 3884 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3885 return -1; 3886 } 3887 port = XHCI_PORTSC(cp); 3888 v = xhci_op_read_4(sc, port); 3889 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3890 v &= ~XHCI_PS_CLEAR; 3891 switch (value) { 3892 case UHF_PORT_ENABLE: 3893 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3894 break; 3895 case UHF_PORT_SUSPEND: 3896 return -1; 3897 case UHF_PORT_POWER: 3898 break; 3899 case UHF_PORT_TEST: 3900 case UHF_PORT_INDICATOR: 3901 return -1; 3902 case UHF_C_PORT_CONNECTION: 3903 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3904 break; 3905 case UHF_C_PORT_ENABLE: 3906 case UHF_C_PORT_SUSPEND: 3907 case UHF_C_PORT_OVER_CURRENT: 3908 return -1; 3909 case UHF_C_BH_PORT_RESET: 3910 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3911 break; 3912 case UHF_C_PORT_RESET: 3913 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3914 break; 3915 case UHF_C_PORT_LINK_STATE: 3916 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3917 break; 3918 case UHF_C_PORT_CONFIG_ERROR: 3919 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3920 break; 3921 default: 3922 return -1; 3923 } 3924 break; 3925 } 3926 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3927 if (len == 0) 3928 break; 3929 if ((value & 0xff) != 0) { 3930 return -1; 3931 } 3932 usb_hub_descriptor_t hubd; 3933 3934 totlen = uimin(buflen, sizeof(hubd)); 3935 memcpy(&hubd, buf, totlen); 3936 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3937 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3938 hubd.bPwrOn2PwrGood = 200; 3939 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3940 /* XXX can't find out? */ 3941 hubd.DeviceRemovable[i++] = 0; 3942 } 3943 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3944 totlen = uimin(totlen, hubd.bDescLength); 3945 memcpy(buf, &hubd, totlen); 3946 break; 3947 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3948 if (len != 4) { 3949 return -1; 3950 } 3951 memset(buf, 0, len); /* ? XXX */ 3952 totlen = len; 3953 break; 3954 /* Get Port Status request */ 3955 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3956 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3957 3958 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3959 bn, index, cp, 0); 3960 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3961 DPRINTFN(5, "bad get port status: index=%jd bn=%jd " 3962 "portcount=%jd", 3963 index, bn, sc->sc_rhportcount[bn], 0); 3964 return -1; 3965 } 3966 if (len != 4) { 3967 DPRINTFN(5, "bad get port status: len %d != 4", 3968 len, 0, 0, 0); 3969 return -1; 3970 } 3971 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3972 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3973 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3974 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3975 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3976 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3977 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3978 if (v & XHCI_PS_PR) i |= UPS_RESET; 3979 if (v & XHCI_PS_PP) { 3980 if (i & UPS_OTHER_SPEED) 3981 i |= UPS_PORT_POWER_SS; 3982 else 3983 i |= UPS_PORT_POWER; 3984 } 3985 if (i & UPS_OTHER_SPEED) 3986 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3987 if (sc->sc_vendor_port_status) 3988 i = sc->sc_vendor_port_status(sc, v, i); 3989 USETW(ps.wPortStatus, i); 3990 i = 0; 3991 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3992 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3993 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3994 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3995 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3996 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3997 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3998 USETW(ps.wPortChange, i); 3999 totlen = uimin(len, sizeof(ps)); 4000 memcpy(buf, &ps, totlen); 4001 DPRINTFN(5, "get port status: wPortStatus %x wPortChange %x " 4002 "totlen %d", 4003 UGETW(ps.wPortStatus), UGETW(ps.wPortChange), totlen, 0); 4004 break; 4005 } 4006 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 4007 return -1; 4008 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 4009 break; 4010 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 4011 break; 4012 /* Set Port Feature request */ 4013 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 4014 int optval = (index >> 8) & 0xff; 4015 index &= 0xff; 4016 if (index < 1 || index > sc->sc_rhportcount[bn]) { 4017 return -1; 4018 } 4019 4020 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 4021 4022 port = XHCI_PORTSC(cp); 4023 v = xhci_op_read_4(sc, port); 4024 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 4025 v &= ~XHCI_PS_CLEAR; 4026 switch (value) { 4027 case UHF_PORT_ENABLE: 4028 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 4029 break; 4030 case UHF_PORT_SUSPEND: 4031 /* XXX suspend */ 4032 break; 4033 case UHF_PORT_RESET: 4034 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 4035 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 4036 /* Wait for reset to complete. */ 4037 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 4038 if (sc->sc_dying) { 4039 return -1; 4040 } 4041 v = xhci_op_read_4(sc, port); 4042 if (v & XHCI_PS_PR) { 4043 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 4044 usb_delay_ms(&sc->sc_bus, 10); 4045 /* XXX */ 4046 } 4047 break; 4048 case UHF_PORT_POWER: 4049 /* XXX power control */ 4050 break; 4051 /* XXX more */ 4052 case UHF_C_PORT_RESET: 4053 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 4054 break; 4055 case UHF_PORT_U1_TIMEOUT: 4056 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4057 return -1; 4058 } 4059 port = XHCI_PORTPMSC(cp); 4060 v = xhci_op_read_4(sc, port); 4061 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4062 index, cp, v, 0); 4063 v &= ~XHCI_PM3_U1TO_SET(0xff); 4064 v |= XHCI_PM3_U1TO_SET(optval); 4065 xhci_op_write_4(sc, port, v); 4066 break; 4067 case UHF_PORT_U2_TIMEOUT: 4068 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4069 return -1; 4070 } 4071 port = XHCI_PORTPMSC(cp); 4072 v = xhci_op_read_4(sc, port); 4073 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4074 index, cp, v, 0); 4075 v &= ~XHCI_PM3_U2TO_SET(0xff); 4076 v |= XHCI_PM3_U2TO_SET(optval); 4077 xhci_op_write_4(sc, port, v); 4078 break; 4079 default: 4080 return -1; 4081 } 4082 } 4083 break; 4084 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 4085 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 4086 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 4087 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 4088 break; 4089 default: 4090 /* default from usbroothub */ 4091 return buflen; 4092 } 4093 4094 return totlen; 4095 } 4096 4097 /* root hub interrupt */ 4098 4099 static usbd_status 4100 xhci_root_intr_transfer(struct usbd_xfer *xfer) 4101 { 4102 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4103 usbd_status err; 4104 4105 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4106 4107 /* Insert last in queue. */ 4108 mutex_enter(&sc->sc_lock); 4109 err = usb_insert_transfer(xfer); 4110 mutex_exit(&sc->sc_lock); 4111 if (err) 4112 return err; 4113 4114 /* Pipe isn't running, start first */ 4115 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4116 } 4117 4118 /* Wait for roothub port status/change */ 4119 static usbd_status 4120 xhci_root_intr_start(struct usbd_xfer *xfer) 4121 { 4122 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4123 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4124 const bool polling = xhci_polling_p(sc); 4125 4126 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4127 4128 if (sc->sc_dying) 4129 return USBD_IOERROR; 4130 4131 if (!polling) 4132 mutex_enter(&sc->sc_lock); 4133 KASSERT(sc->sc_intrxfer[bn] == NULL); 4134 sc->sc_intrxfer[bn] = xfer; 4135 xfer->ux_status = USBD_IN_PROGRESS; 4136 if (!polling) 4137 mutex_exit(&sc->sc_lock); 4138 4139 return USBD_IN_PROGRESS; 4140 } 4141 4142 static void 4143 xhci_root_intr_abort(struct usbd_xfer *xfer) 4144 { 4145 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4146 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4147 4148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4149 4150 KASSERT(mutex_owned(&sc->sc_lock)); 4151 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4152 4153 /* If xfer has already completed, nothing to do here. */ 4154 if (sc->sc_intrxfer[bn] == NULL) 4155 return; 4156 4157 /* 4158 * Otherwise, sc->sc_intrxfer[bn] had better be this transfer. 4159 * Cancel it. 4160 */ 4161 KASSERT(sc->sc_intrxfer[bn] == xfer); 4162 xfer->ux_status = USBD_CANCELLED; 4163 usb_transfer_complete(xfer); 4164 } 4165 4166 static void 4167 xhci_root_intr_close(struct usbd_pipe *pipe) 4168 { 4169 struct xhci_softc * const sc __diagused = XHCI_PIPE2SC(pipe); 4170 const struct usbd_xfer *xfer __diagused = pipe->up_intrxfer; 4171 const size_t bn __diagused = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4172 4173 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4174 4175 KASSERT(mutex_owned(&sc->sc_lock)); 4176 4177 /* 4178 * Caller must guarantee the xfer has completed first, by 4179 * closing the pipe only after normal completion or an abort. 4180 */ 4181 KASSERT(sc->sc_intrxfer[bn] == NULL); 4182 } 4183 4184 static void 4185 xhci_root_intr_done(struct usbd_xfer *xfer) 4186 { 4187 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4188 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4189 4190 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4191 4192 KASSERT(mutex_owned(&sc->sc_lock)); 4193 4194 /* Claim the xfer so it doesn't get completed again. */ 4195 KASSERT(sc->sc_intrxfer[bn] == xfer); 4196 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 4197 sc->sc_intrxfer[bn] = NULL; 4198 } 4199 4200 /* -------------- */ 4201 /* device control */ 4202 4203 static usbd_status 4204 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 4205 { 4206 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4207 usbd_status err; 4208 4209 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4210 4211 /* Insert last in queue. */ 4212 mutex_enter(&sc->sc_lock); 4213 err = usb_insert_transfer(xfer); 4214 mutex_exit(&sc->sc_lock); 4215 if (err) 4216 return err; 4217 4218 /* Pipe isn't running, start first */ 4219 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4220 } 4221 4222 static usbd_status 4223 xhci_device_ctrl_start(struct usbd_xfer *xfer) 4224 { 4225 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4226 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4227 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4228 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4229 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4230 usb_device_request_t * const req = &xfer->ux_request; 4231 const int isread = usbd_xfer_isread(xfer); 4232 const uint32_t len = UGETW(req->wLength); 4233 usb_dma_t * const dma = &xfer->ux_dmabuf; 4234 uint64_t parameter; 4235 uint32_t status; 4236 uint32_t control; 4237 u_int i; 4238 const bool polling = xhci_polling_p(sc); 4239 4240 XHCIHIST_FUNC(); 4241 XHCIHIST_CALLARGS("req: %04jx %04jx %04jx %04jx", 4242 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 4243 UGETW(req->wIndex), UGETW(req->wLength)); 4244 4245 /* we rely on the bottom bits for extra info */ 4246 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 4247 (uintptr_t) xfer); 4248 4249 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 4250 4251 i = 0; 4252 4253 /* setup phase */ 4254 memcpy(¶meter, req, sizeof(parameter)); 4255 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 4256 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 4257 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 4258 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 4259 XHCI_TRB_3_IDT_BIT; 4260 /* we need parameter un-swapped on big endian, so pre-swap it here */ 4261 xhci_soft_trb_put(&xx->xx_trb[i++], htole64(parameter), status, control); 4262 4263 if (len != 0) { 4264 /* data phase */ 4265 parameter = DMAADDR(dma, 0); 4266 KASSERTMSG(len <= 0x10000, "len %d", len); 4267 status = XHCI_TRB_2_IRQ_SET(0) | 4268 XHCI_TRB_2_TDSZ_SET(0) | 4269 XHCI_TRB_2_BYTES_SET(len); 4270 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 4271 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 4272 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4273 XHCI_TRB_3_IOC_BIT; 4274 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4275 } 4276 4277 parameter = 0; 4278 status = XHCI_TRB_2_IRQ_SET(0); 4279 /* the status stage has inverted direction */ 4280 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 4281 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 4282 XHCI_TRB_3_IOC_BIT; 4283 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4284 4285 if (!polling) 4286 mutex_enter(&tr->xr_lock); 4287 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4288 if (!polling) 4289 mutex_exit(&tr->xr_lock); 4290 4291 if (!polling) 4292 mutex_enter(&sc->sc_lock); 4293 xfer->ux_status = USBD_IN_PROGRESS; 4294 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4295 usbd_xfer_schedule_timeout(xfer); 4296 if (!polling) 4297 mutex_exit(&sc->sc_lock); 4298 4299 return USBD_IN_PROGRESS; 4300 } 4301 4302 static void 4303 xhci_device_ctrl_done(struct usbd_xfer *xfer) 4304 { 4305 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4306 usb_device_request_t *req = &xfer->ux_request; 4307 int len = UGETW(req->wLength); 4308 int rd = req->bmRequestType & UT_READ; 4309 4310 if (len) 4311 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4312 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4313 } 4314 4315 static void 4316 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 4317 { 4318 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4319 4320 usbd_xfer_abort(xfer); 4321 } 4322 4323 static void 4324 xhci_device_ctrl_close(struct usbd_pipe *pipe) 4325 { 4326 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4327 4328 xhci_close_pipe(pipe); 4329 } 4330 4331 /* ------------------ */ 4332 /* device isochronous */ 4333 4334 /* ----------- */ 4335 /* device bulk */ 4336 4337 static usbd_status 4338 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 4339 { 4340 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4341 usbd_status err; 4342 4343 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4344 4345 /* Insert last in queue. */ 4346 mutex_enter(&sc->sc_lock); 4347 err = usb_insert_transfer(xfer); 4348 mutex_exit(&sc->sc_lock); 4349 if (err) 4350 return err; 4351 4352 /* 4353 * Pipe isn't running (otherwise err would be USBD_INPROG), 4354 * so start it first. 4355 */ 4356 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4357 } 4358 4359 static usbd_status 4360 xhci_device_bulk_start(struct usbd_xfer *xfer) 4361 { 4362 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4363 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4364 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4365 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4366 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4367 const uint32_t len = xfer->ux_length; 4368 usb_dma_t * const dma = &xfer->ux_dmabuf; 4369 uint64_t parameter; 4370 uint32_t status; 4371 uint32_t control; 4372 u_int i = 0; 4373 const bool polling = xhci_polling_p(sc); 4374 4375 XHCIHIST_FUNC(); 4376 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4377 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4378 4379 if (sc->sc_dying) 4380 return USBD_IOERROR; 4381 4382 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4383 4384 parameter = DMAADDR(dma, 0); 4385 /* 4386 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 4387 * If the user supplied buffer crosses such a boundary then 2 4388 * (or more) TRB should be used. 4389 * If multiple TRB are used the td_size field must be set correctly. 4390 * For v1.0 devices (like ivy bridge) this is the number of usb data 4391 * blocks needed to complete the transfer. 4392 * Setting it to 1 in the last TRB causes an extra zero-length 4393 * data block be sent. 4394 * The earlier documentation differs, I don't know how it behaves. 4395 */ 4396 KASSERTMSG(len <= 0x10000, "len %d", len); 4397 status = XHCI_TRB_2_IRQ_SET(0) | 4398 XHCI_TRB_2_TDSZ_SET(0) | 4399 XHCI_TRB_2_BYTES_SET(len); 4400 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4401 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4402 XHCI_TRB_3_IOC_BIT; 4403 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4404 4405 if (!polling) 4406 mutex_enter(&tr->xr_lock); 4407 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4408 if (!polling) 4409 mutex_exit(&tr->xr_lock); 4410 4411 if (!polling) 4412 mutex_enter(&sc->sc_lock); 4413 xfer->ux_status = USBD_IN_PROGRESS; 4414 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4415 usbd_xfer_schedule_timeout(xfer); 4416 if (!polling) 4417 mutex_exit(&sc->sc_lock); 4418 4419 return USBD_IN_PROGRESS; 4420 } 4421 4422 static void 4423 xhci_device_bulk_done(struct usbd_xfer *xfer) 4424 { 4425 #ifdef USB_DEBUG 4426 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4427 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4428 #endif 4429 const int isread = usbd_xfer_isread(xfer); 4430 4431 XHCIHIST_FUNC(); 4432 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4433 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4434 4435 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4436 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4437 } 4438 4439 static void 4440 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4441 { 4442 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4443 4444 usbd_xfer_abort(xfer); 4445 } 4446 4447 static void 4448 xhci_device_bulk_close(struct usbd_pipe *pipe) 4449 { 4450 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4451 4452 xhci_close_pipe(pipe); 4453 } 4454 4455 /* ---------------- */ 4456 /* device interrupt */ 4457 4458 static usbd_status 4459 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4460 { 4461 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4462 usbd_status err; 4463 4464 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4465 4466 /* Insert last in queue. */ 4467 mutex_enter(&sc->sc_lock); 4468 err = usb_insert_transfer(xfer); 4469 mutex_exit(&sc->sc_lock); 4470 if (err) 4471 return err; 4472 4473 /* 4474 * Pipe isn't running (otherwise err would be USBD_INPROG), 4475 * so start it first. 4476 */ 4477 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4478 } 4479 4480 static usbd_status 4481 xhci_device_intr_start(struct usbd_xfer *xfer) 4482 { 4483 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4484 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4485 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4486 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4487 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4488 const uint32_t len = xfer->ux_length; 4489 const bool polling = xhci_polling_p(sc); 4490 usb_dma_t * const dma = &xfer->ux_dmabuf; 4491 uint64_t parameter; 4492 uint32_t status; 4493 uint32_t control; 4494 u_int i = 0; 4495 4496 XHCIHIST_FUNC(); 4497 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4498 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4499 4500 if (sc->sc_dying) 4501 return USBD_IOERROR; 4502 4503 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4504 4505 parameter = DMAADDR(dma, 0); 4506 KASSERTMSG(len <= 0x10000, "len %d", len); 4507 status = XHCI_TRB_2_IRQ_SET(0) | 4508 XHCI_TRB_2_TDSZ_SET(0) | 4509 XHCI_TRB_2_BYTES_SET(len); 4510 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4511 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4512 XHCI_TRB_3_IOC_BIT; 4513 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4514 4515 if (!polling) 4516 mutex_enter(&tr->xr_lock); 4517 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4518 if (!polling) 4519 mutex_exit(&tr->xr_lock); 4520 4521 if (!polling) 4522 mutex_enter(&sc->sc_lock); 4523 xfer->ux_status = USBD_IN_PROGRESS; 4524 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4525 usbd_xfer_schedule_timeout(xfer); 4526 if (!polling) 4527 mutex_exit(&sc->sc_lock); 4528 4529 return USBD_IN_PROGRESS; 4530 } 4531 4532 static void 4533 xhci_device_intr_done(struct usbd_xfer *xfer) 4534 { 4535 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4536 #ifdef USB_DEBUG 4537 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4538 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4539 #endif 4540 const int isread = usbd_xfer_isread(xfer); 4541 4542 XHCIHIST_FUNC(); 4543 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4544 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4545 4546 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4547 4548 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4549 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4550 } 4551 4552 static void 4553 xhci_device_intr_abort(struct usbd_xfer *xfer) 4554 { 4555 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4556 4557 XHCIHIST_FUNC(); 4558 XHCIHIST_CALLARGS("%#jx", (uintptr_t)xfer, 0, 0, 0); 4559 4560 KASSERT(mutex_owned(&sc->sc_lock)); 4561 usbd_xfer_abort(xfer); 4562 } 4563 4564 static void 4565 xhci_device_intr_close(struct usbd_pipe *pipe) 4566 { 4567 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4568 4569 XHCIHIST_FUNC(); 4570 XHCIHIST_CALLARGS("%#jx", (uintptr_t)pipe, 0, 0, 0); 4571 4572 xhci_close_pipe(pipe); 4573 } 4574
Indexes created Wed Oct 01 18:09:54 GMT 2025