xhci.c revision 1.123
1 /* $NetBSD: xhci.c,v 1.123 2020/04/02 11:37:23 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.123 2020/04/02 11:37:23 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 119 #define XHCIHIST_FUNC() USBHIST_FUNC() 120 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 121 #define XHCIHIST_CALLARGS(FMT,A,B,C,D) \ 122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D) 123 124 #define XHCI_DCI_SLOT 0 125 #define XHCI_DCI_EP_CONTROL 1 126 127 #define XHCI_ICI_INPUT_CONTROL 0 128 129 struct xhci_pipe { 130 struct usbd_pipe xp_pipe; 131 struct usb_task xp_async_task; 132 }; 133 134 #define XHCI_COMMAND_RING_TRBS 256 135 #define XHCI_EVENT_RING_TRBS 256 136 #define XHCI_EVENT_RING_SEGMENTS 1 137 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 138 139 static usbd_status xhci_open(struct usbd_pipe *); 140 static void xhci_close_pipe(struct usbd_pipe *); 141 static int xhci_intr1(struct xhci_softc * const); 142 static void xhci_softintr(void *); 143 static void xhci_poll(struct usbd_bus *); 144 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 145 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 146 static void xhci_abortx(struct usbd_xfer *); 147 static bool xhci_dying(struct usbd_bus *); 148 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 149 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 150 struct usbd_port *); 151 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 152 void *, int); 153 154 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 155 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 156 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 157 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 158 159 static void xhci_host_dequeue(struct xhci_ring * const); 160 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 161 162 static usbd_status xhci_do_command(struct xhci_softc * const, 163 struct xhci_soft_trb * const, int); 164 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 165 struct xhci_soft_trb * const, int); 166 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 167 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *); 168 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 169 static usbd_status xhci_enable_slot(struct xhci_softc * const, 170 uint8_t * const); 171 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 172 static usbd_status xhci_address_device(struct xhci_softc * const, 173 uint64_t, uint8_t, bool); 174 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 175 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 176 struct xhci_slot * const, u_int); 177 static usbd_status xhci_ring_init(struct xhci_softc * const, 178 struct xhci_ring **, size_t, size_t); 179 static void xhci_ring_free(struct xhci_softc * const, 180 struct xhci_ring ** const); 181 182 static void xhci_setup_ctx(struct usbd_pipe *); 183 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 184 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 185 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 186 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 187 188 static void xhci_noop(struct usbd_pipe *); 189 190 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 191 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 192 static void xhci_root_intr_abort(struct usbd_xfer *); 193 static void xhci_root_intr_close(struct usbd_pipe *); 194 static void xhci_root_intr_done(struct usbd_xfer *); 195 196 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 197 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 198 static void xhci_device_ctrl_abort(struct usbd_xfer *); 199 static void xhci_device_ctrl_close(struct usbd_pipe *); 200 static void xhci_device_ctrl_done(struct usbd_xfer *); 201 202 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 203 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 204 static void xhci_device_intr_abort(struct usbd_xfer *); 205 static void xhci_device_intr_close(struct usbd_pipe *); 206 static void xhci_device_intr_done(struct usbd_xfer *); 207 208 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 209 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 210 static void xhci_device_bulk_abort(struct usbd_xfer *); 211 static void xhci_device_bulk_close(struct usbd_pipe *); 212 static void xhci_device_bulk_done(struct usbd_xfer *); 213 214 static const struct usbd_bus_methods xhci_bus_methods = { 215 .ubm_open = xhci_open, 216 .ubm_softint = xhci_softintr, 217 .ubm_dopoll = xhci_poll, 218 .ubm_allocx = xhci_allocx, 219 .ubm_freex = xhci_freex, 220 .ubm_abortx = xhci_abortx, 221 .ubm_dying = xhci_dying, 222 .ubm_getlock = xhci_get_lock, 223 .ubm_newdev = xhci_new_device, 224 .ubm_rhctrl = xhci_roothub_ctrl, 225 }; 226 227 static const struct usbd_pipe_methods xhci_root_intr_methods = { 228 .upm_transfer = xhci_root_intr_transfer, 229 .upm_start = xhci_root_intr_start, 230 .upm_abort = xhci_root_intr_abort, 231 .upm_close = xhci_root_intr_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_root_intr_done, 234 }; 235 236 237 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 238 .upm_transfer = xhci_device_ctrl_transfer, 239 .upm_start = xhci_device_ctrl_start, 240 .upm_abort = xhci_device_ctrl_abort, 241 .upm_close = xhci_device_ctrl_close, 242 .upm_cleartoggle = xhci_noop, 243 .upm_done = xhci_device_ctrl_done, 244 }; 245 246 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 247 .upm_cleartoggle = xhci_noop, 248 }; 249 250 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 251 .upm_transfer = xhci_device_bulk_transfer, 252 .upm_start = xhci_device_bulk_start, 253 .upm_abort = xhci_device_bulk_abort, 254 .upm_close = xhci_device_bulk_close, 255 .upm_cleartoggle = xhci_noop, 256 .upm_done = xhci_device_bulk_done, 257 }; 258 259 static const struct usbd_pipe_methods xhci_device_intr_methods = { 260 .upm_transfer = xhci_device_intr_transfer, 261 .upm_start = xhci_device_intr_start, 262 .upm_abort = xhci_device_intr_abort, 263 .upm_close = xhci_device_intr_close, 264 .upm_cleartoggle = xhci_noop, 265 .upm_done = xhci_device_intr_done, 266 }; 267 268 static inline uint32_t 269 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 270 { 271 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 272 } 273 274 static inline uint32_t 275 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 276 { 277 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 278 } 279 280 static inline void 281 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 282 uint32_t value) 283 { 284 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 285 } 286 287 #if 0 /* unused */ 288 static inline void 289 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 290 uint32_t value) 291 { 292 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 293 } 294 #endif /* unused */ 295 296 static inline uint32_t 297 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 298 { 299 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 300 } 301 302 static inline uint32_t 303 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 304 { 305 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 306 } 307 308 static inline void 309 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 310 uint32_t value) 311 { 312 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 313 } 314 315 static inline uint64_t 316 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 317 { 318 uint64_t value; 319 320 if (sc->sc_ac64) { 321 #ifdef XHCI_USE_BUS_SPACE_8 322 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 323 #else 324 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 325 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 326 offset + 4) << 32; 327 #endif 328 } else { 329 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 330 } 331 332 return value; 333 } 334 335 static inline void 336 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 337 uint64_t value) 338 { 339 if (sc->sc_ac64) { 340 #ifdef XHCI_USE_BUS_SPACE_8 341 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 342 #else 343 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 344 (value >> 0) & 0xffffffff); 345 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 346 (value >> 32) & 0xffffffff); 347 #endif 348 } else { 349 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 350 } 351 } 352 353 static inline void 354 xhci_op_barrier(const struct xhci_softc * const sc, bus_size_t offset, 355 bus_size_t len, int flags) 356 { 357 bus_space_barrier(sc->sc_iot, sc->sc_obh, offset, len, flags); 358 } 359 360 static inline uint32_t 361 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 362 { 363 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 364 } 365 366 static inline void 367 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 368 uint32_t value) 369 { 370 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 371 } 372 373 #if 0 /* unused */ 374 static inline uint64_t 375 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 376 { 377 uint64_t value; 378 379 if (sc->sc_ac64) { 380 #ifdef XHCI_USE_BUS_SPACE_8 381 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 382 #else 383 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 384 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 385 offset + 4) << 32; 386 #endif 387 } else { 388 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 389 } 390 391 return value; 392 } 393 #endif /* unused */ 394 395 static inline void 396 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 397 uint64_t value) 398 { 399 if (sc->sc_ac64) { 400 #ifdef XHCI_USE_BUS_SPACE_8 401 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 402 #else 403 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 404 (value >> 0) & 0xffffffff); 405 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 406 (value >> 32) & 0xffffffff); 407 #endif 408 } else { 409 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 410 } 411 } 412 413 #if 0 /* unused */ 414 static inline uint32_t 415 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 416 { 417 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 418 } 419 #endif /* unused */ 420 421 static inline void 422 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 423 uint32_t value) 424 { 425 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 426 } 427 428 /* --- */ 429 430 static inline uint8_t 431 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 432 { 433 u_int eptype = 0; 434 435 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 436 case UE_CONTROL: 437 eptype = 0x0; 438 break; 439 case UE_ISOCHRONOUS: 440 eptype = 0x1; 441 break; 442 case UE_BULK: 443 eptype = 0x2; 444 break; 445 case UE_INTERRUPT: 446 eptype = 0x3; 447 break; 448 } 449 450 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 451 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 452 return eptype | 0x4; 453 else 454 return eptype; 455 } 456 457 static u_int 458 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 459 { 460 /* xHCI 1.0 section 4.5.1 */ 461 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 462 u_int in = 0; 463 464 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 465 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 466 in = 1; 467 468 return epaddr * 2 + in; 469 } 470 471 static inline u_int 472 xhci_dci_to_ici(const u_int i) 473 { 474 return i + 1; 475 } 476 477 static inline void * 478 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 479 const u_int dci) 480 { 481 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 482 } 483 484 #if 0 /* unused */ 485 static inline bus_addr_t 486 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 487 const u_int dci) 488 { 489 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 490 } 491 #endif /* unused */ 492 493 static inline void * 494 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 495 const u_int ici) 496 { 497 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 498 } 499 500 static inline bus_addr_t 501 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 502 const u_int ici) 503 { 504 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 505 } 506 507 static inline struct xhci_trb * 508 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 509 { 510 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 511 } 512 513 static inline bus_addr_t 514 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 515 { 516 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 517 } 518 519 static inline void 520 xhci_soft_trb_put(struct xhci_soft_trb * const trb, 521 uint64_t parameter, uint32_t status, uint32_t control) 522 { 523 trb->trb_0 = parameter; 524 trb->trb_2 = status; 525 trb->trb_3 = control; 526 } 527 528 static inline void 529 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 530 uint32_t control) 531 { 532 trb->trb_0 = htole64(parameter); 533 trb->trb_2 = htole32(status); 534 trb->trb_3 = htole32(control); 535 } 536 537 static int 538 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 539 { 540 /* base address of TRBs */ 541 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 542 543 /* trb_0 range sanity check */ 544 if (trb_0 == 0 || trb_0 < trbp || 545 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 546 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 547 return 1; 548 } 549 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 550 return 0; 551 } 552 553 static unsigned int 554 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 555 u_int dci) 556 { 557 uint32_t *cp; 558 559 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 560 cp = xhci_slot_get_dcv(sc, xs, dci); 561 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 562 } 563 564 static inline unsigned int 565 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 566 { 567 const unsigned int port = ctlrport - 1; 568 const uint8_t bit = __BIT(port % NBBY); 569 570 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 571 } 572 573 /* 574 * Return the roothub port for a controller port. Both are 1..n. 575 */ 576 static inline unsigned int 577 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 578 { 579 580 return sc->sc_ctlrportmap[ctrlport - 1]; 581 } 582 583 /* 584 * Return the controller port for a bus roothub port. Both are 1..n. 585 */ 586 static inline unsigned int 587 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 588 unsigned int rhport) 589 { 590 591 return sc->sc_rhportmap[bn][rhport - 1]; 592 } 593 594 /* --- */ 595 596 void 597 xhci_childdet(device_t self, device_t child) 598 { 599 struct xhci_softc * const sc = device_private(self); 600 601 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 602 if (child == sc->sc_child2) 603 sc->sc_child2 = NULL; 604 else if (child == sc->sc_child) 605 sc->sc_child = NULL; 606 } 607 608 int 609 xhci_detach(struct xhci_softc *sc, int flags) 610 { 611 int rv = 0; 612 613 if (sc->sc_child2 != NULL) { 614 rv = config_detach(sc->sc_child2, flags); 615 if (rv != 0) 616 return rv; 617 KASSERT(sc->sc_child2 == NULL); 618 } 619 620 if (sc->sc_child != NULL) { 621 rv = config_detach(sc->sc_child, flags); 622 if (rv != 0) 623 return rv; 624 KASSERT(sc->sc_child == NULL); 625 } 626 627 /* XXX unconfigure/free slots */ 628 629 /* verify: */ 630 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 631 xhci_op_write_4(sc, XHCI_USBCMD, 0); 632 /* do we need to wait for stop? */ 633 634 xhci_op_write_8(sc, XHCI_CRCR, 0); 635 xhci_ring_free(sc, &sc->sc_cr); 636 cv_destroy(&sc->sc_command_cv); 637 cv_destroy(&sc->sc_cmdbusy_cv); 638 639 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 640 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 641 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 642 xhci_ring_free(sc, &sc->sc_er); 643 644 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 645 646 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 647 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 648 649 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 650 651 kmem_free(sc->sc_ctlrportbus, 652 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 653 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 654 655 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 656 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 657 } 658 659 mutex_destroy(&sc->sc_lock); 660 mutex_destroy(&sc->sc_intr_lock); 661 662 pool_cache_destroy(sc->sc_xferpool); 663 664 return rv; 665 } 666 667 int 668 xhci_activate(device_t self, enum devact act) 669 { 670 struct xhci_softc * const sc = device_private(self); 671 672 switch (act) { 673 case DVACT_DEACTIVATE: 674 sc->sc_dying = true; 675 return 0; 676 default: 677 return EOPNOTSUPP; 678 } 679 } 680 681 bool 682 xhci_suspend(device_t dv, const pmf_qual_t *qual) 683 { 684 return false; 685 } 686 687 bool 688 xhci_resume(device_t dv, const pmf_qual_t *qual) 689 { 690 return false; 691 } 692 693 bool 694 xhci_shutdown(device_t self, int flags) 695 { 696 return false; 697 } 698 699 static int 700 xhci_hc_reset(struct xhci_softc * const sc) 701 { 702 uint32_t usbcmd, usbsts; 703 int i; 704 705 /* Check controller not ready */ 706 for (i = 0; i < XHCI_WAIT_CNR; i++) { 707 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 708 if ((usbsts & XHCI_STS_CNR) == 0) 709 break; 710 usb_delay_ms(&sc->sc_bus, 1); 711 } 712 if (i >= XHCI_WAIT_CNR) { 713 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 714 return EIO; 715 } 716 717 /* Halt controller */ 718 usbcmd = 0; 719 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 720 usb_delay_ms(&sc->sc_bus, 1); 721 722 /* Reset controller */ 723 usbcmd = XHCI_CMD_HCRST; 724 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 725 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 726 /* 727 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 728 * prevent system hang (Errata). 729 */ 730 usb_delay_ms(&sc->sc_bus, 1); 731 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 732 if ((usbcmd & XHCI_CMD_HCRST) == 0) 733 break; 734 } 735 if (i >= XHCI_WAIT_HCRST) { 736 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 737 return EIO; 738 } 739 740 /* Check controller not ready */ 741 for (i = 0; i < XHCI_WAIT_CNR; i++) { 742 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 743 if ((usbsts & XHCI_STS_CNR) == 0) 744 break; 745 usb_delay_ms(&sc->sc_bus, 1); 746 } 747 if (i >= XHCI_WAIT_CNR) { 748 aprint_error_dev(sc->sc_dev, 749 "controller not ready timeout after reset\n"); 750 return EIO; 751 } 752 753 return 0; 754 } 755 756 757 /* 7.2 xHCI Support Protocol Capability */ 758 static void 759 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 760 { 761 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 762 763 /* XXX Cache this lot */ 764 765 const uint32_t w0 = xhci_read_4(sc, ecp); 766 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 767 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 768 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 769 770 aprint_debug_dev(sc->sc_dev, 771 " SP: 0x%08x 0x%08x 0x%08x 0x%08x\n", w0, w4, w8, wc); 772 773 if (w4 != XHCI_XECP_USBID) 774 return; 775 776 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 777 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 778 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 779 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 780 781 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 782 switch (mm) { 783 case 0x0200: 784 case 0x0300: 785 case 0x0301: 786 case 0x0310: 787 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 788 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 789 break; 790 default: 791 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 792 major, minor); 793 return; 794 } 795 796 const size_t bus = (major == 3) ? 0 : 1; 797 798 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 799 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 800 if (sc->sc_ctlrportmap[cp] != 0) { 801 aprint_error_dev(sc->sc_dev, "controller port %zu " 802 "already assigned", cp); 803 continue; 804 } 805 806 sc->sc_ctlrportbus[cp / NBBY] |= 807 bus == 0 ? 0 : __BIT(cp % NBBY); 808 809 const size_t rhp = sc->sc_rhportcount[bus]++; 810 811 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 812 "bus %zu rhp %zu is %d", bus, rhp, 813 sc->sc_rhportmap[bus][rhp]); 814 815 sc->sc_rhportmap[bus][rhp] = cp + 1; 816 sc->sc_ctlrportmap[cp] = rhp + 1; 817 } 818 } 819 820 /* Process extended capabilities */ 821 static void 822 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 823 { 824 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 825 826 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 827 while (ecp != 0) { 828 uint32_t ecr = xhci_read_4(sc, ecp); 829 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 830 switch (XHCI_XECP_ID(ecr)) { 831 case XHCI_ID_PROTOCOLS: { 832 xhci_id_protocols(sc, ecp); 833 break; 834 } 835 case XHCI_ID_USB_LEGACY: { 836 uint8_t bios_sem; 837 838 /* Take host controller ownership from BIOS */ 839 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 840 if (bios_sem) { 841 /* sets xHCI to be owned by OS */ 842 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 843 aprint_debug_dev(sc->sc_dev, 844 "waiting for BIOS to give up control\n"); 845 for (int i = 0; i < 5000; i++) { 846 bios_sem = xhci_read_1(sc, ecp + 847 XHCI_XECP_BIOS_SEM); 848 if (bios_sem == 0) 849 break; 850 DELAY(1000); 851 } 852 if (bios_sem) { 853 aprint_error_dev(sc->sc_dev, 854 "timed out waiting for BIOS\n"); 855 } 856 } 857 break; 858 } 859 default: 860 break; 861 } 862 ecr = xhci_read_4(sc, ecp); 863 if (XHCI_XECP_NEXT(ecr) == 0) { 864 ecp = 0; 865 } else { 866 ecp += XHCI_XECP_NEXT(ecr) * 4; 867 } 868 } 869 } 870 871 #define XHCI_HCCPREV1_BITS \ 872 "\177\020" /* New bitmask */ \ 873 "f\020\020XECP\0" \ 874 "f\014\4MAXPSA\0" \ 875 "b\013CFC\0" \ 876 "b\012SEC\0" \ 877 "b\011SBD\0" \ 878 "b\010FSE\0" \ 879 "b\7NSS\0" \ 880 "b\6LTC\0" \ 881 "b\5LHRC\0" \ 882 "b\4PIND\0" \ 883 "b\3PPC\0" \ 884 "b\2CZC\0" \ 885 "b\1BNC\0" \ 886 "b\0AC64\0" \ 887 "\0" 888 #define XHCI_HCCV1_x_BITS \ 889 "\177\020" /* New bitmask */ \ 890 "f\020\020XECP\0" \ 891 "f\014\4MAXPSA\0" \ 892 "b\013CFC\0" \ 893 "b\012SEC\0" \ 894 "b\011SPC\0" \ 895 "b\010PAE\0" \ 896 "b\7NSS\0" \ 897 "b\6LTC\0" \ 898 "b\5LHRC\0" \ 899 "b\4PIND\0" \ 900 "b\3PPC\0" \ 901 "b\2CSZ\0" \ 902 "b\1BNC\0" \ 903 "b\0AC64\0" \ 904 "\0" 905 906 #define XHCI_HCC2_BITS \ 907 "\177\020" /* New bitmask */ \ 908 "b\7ETC_TSC\0" \ 909 "b\6ETC\0" \ 910 "b\5CIC\0" \ 911 "b\4LEC\0" \ 912 "b\3CTC\0" \ 913 "b\2FSC\0" \ 914 "b\1CMC\0" \ 915 "b\0U3C\0" \ 916 "\0" 917 918 void 919 xhci_start(struct xhci_softc *sc) 920 { 921 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 922 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 923 /* Intel xhci needs interrupt rate moderated. */ 924 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 925 else 926 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 927 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 928 xhci_rt_read_4(sc, XHCI_IMOD(0))); 929 930 /* Go! */ 931 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 932 aprint_debug_dev(sc->sc_dev, "USBCMD 0x%08"PRIx32"\n", 933 xhci_op_read_4(sc, XHCI_USBCMD)); 934 } 935 936 int 937 xhci_init(struct xhci_softc *sc) 938 { 939 bus_size_t bsz; 940 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff, hcc2; 941 uint32_t pagesize, config; 942 int i = 0; 943 uint16_t hciversion; 944 uint8_t caplength; 945 946 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 947 948 /* Set up the bus struct for the usb 3 and usb 2 buses */ 949 sc->sc_bus.ub_methods = &xhci_bus_methods; 950 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 951 sc->sc_bus.ub_usedma = true; 952 sc->sc_bus.ub_hcpriv = sc; 953 954 sc->sc_bus2.ub_methods = &xhci_bus_methods; 955 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 956 sc->sc_bus2.ub_revision = USBREV_2_0; 957 sc->sc_bus2.ub_usedma = true; 958 sc->sc_bus2.ub_hcpriv = sc; 959 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 960 961 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 962 caplength = XHCI_CAP_CAPLENGTH(cap); 963 hciversion = XHCI_CAP_HCIVERSION(cap); 964 965 if (hciversion < XHCI_HCIVERSION_0_96 || 966 hciversion >= 0x0200) { 967 aprint_normal_dev(sc->sc_dev, 968 "xHCI version %x.%x not known to be supported\n", 969 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 970 } else { 971 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 972 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 973 } 974 975 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 976 &sc->sc_cbh) != 0) { 977 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 978 return ENOMEM; 979 } 980 981 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 982 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 983 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 984 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 985 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 986 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 987 aprint_debug_dev(sc->sc_dev, 988 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 989 990 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 991 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 992 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 993 994 char sbuf[128]; 995 if (hciversion < XHCI_HCIVERSION_1_0) 996 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 997 else 998 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 999 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 1000 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 1001 if (hciversion >= XHCI_HCIVERSION_1_1) { 1002 hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 1003 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, hcc2); 1004 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 1005 } 1006 1007 /* default all ports to bus 0, i.e. usb 3 */ 1008 sc->sc_ctlrportbus = kmem_zalloc( 1009 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 1010 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1011 1012 /* controller port to bus roothub port map */ 1013 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 1014 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1015 } 1016 1017 /* 1018 * Process all Extended Capabilities 1019 */ 1020 xhci_ecp(sc, hcc); 1021 1022 bsz = XHCI_PORTSC(sc->sc_maxports); 1023 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1024 &sc->sc_obh) != 0) { 1025 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1026 return ENOMEM; 1027 } 1028 1029 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1030 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1031 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1032 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1033 return ENOMEM; 1034 } 1035 1036 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1037 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1038 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1039 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1040 return ENOMEM; 1041 } 1042 1043 int rv; 1044 rv = xhci_hc_reset(sc); 1045 if (rv != 0) { 1046 return rv; 1047 } 1048 1049 if (sc->sc_vendor_init) 1050 sc->sc_vendor_init(sc); 1051 1052 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1053 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1054 pagesize = ffs(pagesize); 1055 if (pagesize == 0) { 1056 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1057 return EIO; 1058 } 1059 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1060 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1061 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1062 (uint32_t)sc->sc_maxslots); 1063 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1064 1065 usbd_status err; 1066 1067 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1068 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1069 if (sc->sc_maxspbuf != 0) { 1070 err = usb_allocmem(&sc->sc_bus, 1071 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1072 &sc->sc_spbufarray_dma); 1073 if (err) { 1074 aprint_error_dev(sc->sc_dev, 1075 "spbufarray init fail, err %d\n", err); 1076 return ENOMEM; 1077 } 1078 1079 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1080 sc->sc_maxspbuf, KM_SLEEP); 1081 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1082 for (i = 0; i < sc->sc_maxspbuf; i++) { 1083 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1084 /* allocate contexts */ 1085 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1086 sc->sc_pgsz, dma); 1087 if (err) { 1088 aprint_error_dev(sc->sc_dev, 1089 "spbufarray_dma init fail, err %d\n", err); 1090 rv = ENOMEM; 1091 goto bad1; 1092 } 1093 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1094 usb_syncmem(dma, 0, sc->sc_pgsz, 1095 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1096 } 1097 1098 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1099 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1100 } 1101 1102 config = xhci_op_read_4(sc, XHCI_CONFIG); 1103 config &= ~0xFF; 1104 config |= sc->sc_maxslots & 0xFF; 1105 xhci_op_write_4(sc, XHCI_CONFIG, config); 1106 1107 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1108 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1109 if (err) { 1110 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1111 err); 1112 rv = ENOMEM; 1113 goto bad1; 1114 } 1115 1116 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1117 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1118 if (err) { 1119 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1120 err); 1121 rv = ENOMEM; 1122 goto bad2; 1123 } 1124 1125 usb_dma_t *dma; 1126 size_t size; 1127 size_t align; 1128 1129 dma = &sc->sc_eventst_dma; 1130 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1131 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1132 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1133 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1134 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1135 if (err) { 1136 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1137 err); 1138 rv = ENOMEM; 1139 goto bad3; 1140 } 1141 1142 memset(KERNADDR(dma, 0), 0, size); 1143 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1144 aprint_debug_dev(sc->sc_dev, "eventst: 0x%016jx %p %zx\n", 1145 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1146 KERNADDR(&sc->sc_eventst_dma, 0), 1147 sc->sc_eventst_dma.udma_block->size); 1148 1149 dma = &sc->sc_dcbaa_dma; 1150 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1151 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1152 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1153 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1154 if (err) { 1155 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1156 rv = ENOMEM; 1157 goto bad4; 1158 } 1159 aprint_debug_dev(sc->sc_dev, "dcbaa: 0x%016jx %p %zx\n", 1160 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1161 KERNADDR(&sc->sc_dcbaa_dma, 0), 1162 sc->sc_dcbaa_dma.udma_block->size); 1163 1164 memset(KERNADDR(dma, 0), 0, size); 1165 if (sc->sc_maxspbuf != 0) { 1166 /* 1167 * DCBA entry 0 hold the scratchbuf array pointer. 1168 */ 1169 *(uint64_t *)KERNADDR(dma, 0) = 1170 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1171 } 1172 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1173 1174 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1175 KM_SLEEP); 1176 if (sc->sc_slots == NULL) { 1177 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1178 rv = ENOMEM; 1179 goto bad; 1180 } 1181 1182 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1183 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1184 if (sc->sc_xferpool == NULL) { 1185 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1186 err); 1187 rv = ENOMEM; 1188 goto bad; 1189 } 1190 1191 cv_init(&sc->sc_command_cv, "xhcicmd"); 1192 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1193 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1194 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1195 1196 struct xhci_erste *erst; 1197 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1198 erst[0].erste_0 = htole64(xhci_ring_trbp(sc->sc_er, 0)); 1199 erst[0].erste_2 = htole32(sc->sc_er->xr_ntrb); 1200 erst[0].erste_3 = htole32(0); 1201 usb_syncmem(&sc->sc_eventst_dma, 0, 1202 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1203 1204 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1205 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1206 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(sc->sc_er, 0) | 1207 XHCI_ERDP_LO_BUSY); 1208 1209 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1210 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) | 1211 sc->sc_cr->xr_cs); 1212 1213 xhci_op_barrier(sc, 0, 4, BUS_SPACE_BARRIER_WRITE); 1214 1215 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1216 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1217 1218 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1219 xhci_start(sc); 1220 1221 return 0; 1222 1223 bad: 1224 if (sc->sc_xferpool) { 1225 pool_cache_destroy(sc->sc_xferpool); 1226 sc->sc_xferpool = NULL; 1227 } 1228 1229 if (sc->sc_slots) { 1230 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1231 sc->sc_maxslots); 1232 sc->sc_slots = NULL; 1233 } 1234 1235 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1236 bad4: 1237 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1238 bad3: 1239 xhci_ring_free(sc, &sc->sc_er); 1240 bad2: 1241 xhci_ring_free(sc, &sc->sc_cr); 1242 i = sc->sc_maxspbuf; 1243 bad1: 1244 for (int j = 0; j < i; j++) 1245 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1246 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1247 1248 return rv; 1249 } 1250 1251 static inline bool 1252 xhci_polling_p(struct xhci_softc * const sc) 1253 { 1254 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1255 } 1256 1257 int 1258 xhci_intr(void *v) 1259 { 1260 struct xhci_softc * const sc = v; 1261 int ret = 0; 1262 1263 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1264 1265 if (sc == NULL) 1266 return 0; 1267 1268 mutex_spin_enter(&sc->sc_intr_lock); 1269 1270 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1271 goto done; 1272 1273 /* If we get an interrupt while polling, then just ignore it. */ 1274 if (xhci_polling_p(sc)) { 1275 #ifdef DIAGNOSTIC 1276 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1277 #endif 1278 goto done; 1279 } 1280 1281 ret = xhci_intr1(sc); 1282 if (ret) { 1283 KASSERT(sc->sc_child || sc->sc_child2); 1284 1285 /* 1286 * One of child busses could be already detached. It doesn't 1287 * matter on which of the two the softintr is scheduled. 1288 */ 1289 if (sc->sc_child) 1290 usb_schedsoftintr(&sc->sc_bus); 1291 else 1292 usb_schedsoftintr(&sc->sc_bus2); 1293 } 1294 done: 1295 mutex_spin_exit(&sc->sc_intr_lock); 1296 return ret; 1297 } 1298 1299 int 1300 xhci_intr1(struct xhci_softc * const sc) 1301 { 1302 uint32_t usbsts; 1303 uint32_t iman; 1304 1305 XHCIHIST_FUNC(); 1306 1307 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1308 XHCIHIST_CALLARGS("USBSTS 0x%08jx", usbsts, 0, 0, 0); 1309 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1310 XHCI_STS_HCE)) == 0) { 1311 DPRINTFN(16, "ignored intr not for %jd", 1312 device_unit(sc->sc_dev), 0, 0, 0); 1313 return 0; 1314 } 1315 1316 /* 1317 * Clear EINT and other transient flags, to not misenterpret 1318 * next shared interrupt. Also, to avoid race, EINT must be cleared 1319 * before XHCI_IMAN_INTR_PEND is cleared. 1320 */ 1321 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1322 1323 #ifdef XHCI_DEBUG 1324 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1325 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1326 #endif 1327 1328 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1329 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1330 iman |= XHCI_IMAN_INTR_PEND; 1331 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1332 1333 #ifdef XHCI_DEBUG 1334 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1335 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1336 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1337 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1338 #endif 1339 1340 return 1; 1341 } 1342 1343 /* 1344 * 3 port speed types used in USB stack 1345 * 1346 * usbdi speed 1347 * definition: USB_SPEED_* in usb.h 1348 * They are used in struct usbd_device in USB stack. 1349 * ioctl interface uses these values too. 1350 * port_status speed 1351 * definition: UPS_*_SPEED in usb.h 1352 * They are used in usb_port_status_t and valid only for USB 2.0. 1353 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1354 * of usb_port_status_ext_t indicates port speed. 1355 * Note that some 3.0 values overlap with 2.0 values. 1356 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1357 * means UPS_LOW_SPEED in HS.) 1358 * port status returned from hub also uses these values. 1359 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1360 * or more. 1361 * xspeed: 1362 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1363 * They are used in only slot context and PORTSC reg of xhci. 1364 * The difference between usbdi speed and xspeed is 1365 * that FS and LS values are swapped. 1366 */ 1367 1368 /* convert usbdi speed to xspeed */ 1369 static int 1370 xhci_speed2xspeed(int speed) 1371 { 1372 switch (speed) { 1373 case USB_SPEED_LOW: return 2; 1374 case USB_SPEED_FULL: return 1; 1375 default: return speed; 1376 } 1377 } 1378 1379 #if 0 1380 /* convert xspeed to usbdi speed */ 1381 static int 1382 xhci_xspeed2speed(int xspeed) 1383 { 1384 switch (xspeed) { 1385 case 1: return USB_SPEED_FULL; 1386 case 2: return USB_SPEED_LOW; 1387 default: return xspeed; 1388 } 1389 } 1390 #endif 1391 1392 /* convert xspeed to port status speed */ 1393 static int 1394 xhci_xspeed2psspeed(int xspeed) 1395 { 1396 switch (xspeed) { 1397 case 0: return 0; 1398 case 1: return UPS_FULL_SPEED; 1399 case 2: return UPS_LOW_SPEED; 1400 case 3: return UPS_HIGH_SPEED; 1401 default: return UPS_OTHER_SPEED; 1402 } 1403 } 1404 1405 /* 1406 * Construct input contexts and issue TRB to open pipe. 1407 */ 1408 static usbd_status 1409 xhci_configure_endpoint(struct usbd_pipe *pipe) 1410 { 1411 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1412 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1413 #ifdef USB_DEBUG 1414 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1415 #endif 1416 struct xhci_soft_trb trb; 1417 usbd_status err; 1418 1419 XHCIHIST_FUNC(); 1420 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1421 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1422 pipe->up_endpoint->ue_edesc->bmAttributes); 1423 1424 /* XXX ensure input context is available? */ 1425 1426 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1427 1428 /* set up context */ 1429 xhci_setup_ctx(pipe); 1430 1431 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1432 sc->sc_ctxsz * 1); 1433 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1434 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1435 1436 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1437 trb.trb_2 = 0; 1438 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1439 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1440 1441 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1442 1443 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1444 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1445 sc->sc_ctxsz * 1); 1446 1447 return err; 1448 } 1449 1450 #if 0 1451 static usbd_status 1452 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1453 { 1454 #ifdef USB_DEBUG 1455 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1456 #endif 1457 1458 XHCIHIST_FUNC(); 1459 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 1460 1461 return USBD_NORMAL_COMPLETION; 1462 } 1463 #endif 1464 1465 /* 4.6.8, 6.4.3.7 */ 1466 static usbd_status 1467 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1468 { 1469 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1470 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1471 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1472 struct xhci_soft_trb trb; 1473 usbd_status err; 1474 1475 XHCIHIST_FUNC(); 1476 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1477 1478 KASSERT(mutex_owned(&sc->sc_lock)); 1479 1480 trb.trb_0 = 0; 1481 trb.trb_2 = 0; 1482 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1483 XHCI_TRB_3_EP_SET(dci) | 1484 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1485 1486 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1487 1488 return err; 1489 } 1490 1491 static usbd_status 1492 xhci_reset_endpoint(struct usbd_pipe *pipe) 1493 { 1494 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1495 1496 mutex_enter(&sc->sc_lock); 1497 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1498 mutex_exit(&sc->sc_lock); 1499 1500 return ret; 1501 } 1502 1503 /* 1504 * 4.6.9, 6.4.3.8 1505 * Stop execution of TDs on xfer ring. 1506 * Should be called with sc_lock held. 1507 */ 1508 static usbd_status 1509 xhci_stop_endpoint(struct usbd_pipe *pipe) 1510 { 1511 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1512 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1513 struct xhci_soft_trb trb; 1514 usbd_status err; 1515 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1516 1517 XHCIHIST_FUNC(); 1518 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1519 1520 KASSERT(mutex_owned(&sc->sc_lock)); 1521 1522 trb.trb_0 = 0; 1523 trb.trb_2 = 0; 1524 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1525 XHCI_TRB_3_EP_SET(dci) | 1526 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1527 1528 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1529 1530 return err; 1531 } 1532 1533 /* 1534 * Set TR Dequeue Pointer. 1535 * xHCI 1.1 4.6.10 6.4.3.9 1536 * Purge all of the TRBs on ring and reinitialize ring. 1537 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1538 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1539 * error will be generated. 1540 */ 1541 static usbd_status 1542 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1543 { 1544 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1545 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1546 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1547 struct xhci_ring * const xr = xs->xs_xr[dci]; 1548 struct xhci_soft_trb trb; 1549 usbd_status err; 1550 1551 XHCIHIST_FUNC(); 1552 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1553 1554 KASSERT(mutex_owned(&sc->sc_lock)); 1555 KASSERT(xr != NULL); 1556 1557 xhci_host_dequeue(xr); 1558 1559 /* set DCS */ 1560 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1561 trb.trb_2 = 0; 1562 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1563 XHCI_TRB_3_EP_SET(dci) | 1564 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1565 1566 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1567 1568 return err; 1569 } 1570 1571 static usbd_status 1572 xhci_set_dequeue(struct usbd_pipe *pipe) 1573 { 1574 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1575 1576 mutex_enter(&sc->sc_lock); 1577 usbd_status ret = xhci_set_dequeue_locked(pipe); 1578 mutex_exit(&sc->sc_lock); 1579 1580 return ret; 1581 } 1582 1583 /* 1584 * Open new pipe: called from usbd_setup_pipe_flags. 1585 * Fills methods of pipe. 1586 * If pipe is not for ep0, calls configure_endpoint. 1587 */ 1588 static usbd_status 1589 xhci_open(struct usbd_pipe *pipe) 1590 { 1591 struct usbd_device * const dev = pipe->up_dev; 1592 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1593 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1594 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1595 const u_int dci = xhci_ep_get_dci(ed); 1596 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1597 usbd_status err; 1598 1599 XHCIHIST_FUNC(); 1600 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1601 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1602 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1603 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1604 ed->bmAttributes); 1605 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1606 ed->bInterval, 0, 0); 1607 1608 if (sc->sc_dying) 1609 return USBD_IOERROR; 1610 1611 /* Root Hub */ 1612 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1613 switch (ed->bEndpointAddress) { 1614 case USB_CONTROL_ENDPOINT: 1615 pipe->up_methods = &roothub_ctrl_methods; 1616 break; 1617 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1618 pipe->up_methods = &xhci_root_intr_methods; 1619 break; 1620 default: 1621 pipe->up_methods = NULL; 1622 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1623 ed->bEndpointAddress, 0, 0, 0); 1624 return USBD_INVAL; 1625 } 1626 return USBD_NORMAL_COMPLETION; 1627 } 1628 1629 switch (xfertype) { 1630 case UE_CONTROL: 1631 pipe->up_methods = &xhci_device_ctrl_methods; 1632 break; 1633 case UE_ISOCHRONOUS: 1634 pipe->up_methods = &xhci_device_isoc_methods; 1635 return USBD_INVAL; 1636 break; 1637 case UE_BULK: 1638 pipe->up_methods = &xhci_device_bulk_methods; 1639 break; 1640 case UE_INTERRUPT: 1641 pipe->up_methods = &xhci_device_intr_methods; 1642 break; 1643 default: 1644 return USBD_IOERROR; 1645 break; 1646 } 1647 1648 KASSERT(xs != NULL); 1649 KASSERT(xs->xs_xr[dci] == NULL); 1650 1651 /* allocate transfer ring */ 1652 err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS, 1653 XHCI_TRB_ALIGN); 1654 if (err) { 1655 DPRINTFN(1, "ring alloc failed %jd", err, 0, 0, 0); 1656 return err; 1657 } 1658 1659 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1660 return xhci_configure_endpoint(pipe); 1661 1662 return USBD_NORMAL_COMPLETION; 1663 } 1664 1665 /* 1666 * Closes pipe, called from usbd_kill_pipe via close methods. 1667 * If the endpoint to be closed is ep0, disable_slot. 1668 * Should be called with sc_lock held. 1669 */ 1670 static void 1671 xhci_close_pipe(struct usbd_pipe *pipe) 1672 { 1673 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1674 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1675 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1676 const u_int dci = xhci_ep_get_dci(ed); 1677 struct xhci_soft_trb trb; 1678 uint32_t *cp; 1679 1680 XHCIHIST_FUNC(); 1681 1682 if (sc->sc_dying) 1683 return; 1684 1685 /* xs is uninitialized before xhci_init_slot */ 1686 if (xs == NULL || xs->xs_idx == 0) 1687 return; 1688 1689 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 1690 (uintptr_t)pipe, xs->xs_idx, dci, 0); 1691 1692 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1693 KASSERT(mutex_owned(&sc->sc_lock)); 1694 1695 if (pipe->up_dev->ud_depth == 0) 1696 return; 1697 1698 if (dci == XHCI_DCI_EP_CONTROL) { 1699 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1700 /* This frees all rings */ 1701 xhci_disable_slot(sc, xs->xs_idx); 1702 return; 1703 } 1704 1705 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1706 (void)xhci_stop_endpoint(pipe); 1707 1708 /* 1709 * set appropriate bit to be dropped. 1710 * don't set DC bit to 1, otherwise all endpoints 1711 * would be deconfigured. 1712 */ 1713 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1714 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1715 cp[1] = htole32(0); 1716 1717 /* XXX should be most significant one, not dci? */ 1718 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1719 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1720 1721 /* configure ep context performs an implicit dequeue */ 1722 xhci_host_dequeue(xs->xs_xr[dci]); 1723 1724 /* sync input contexts before they are read from memory */ 1725 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1726 1727 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1728 trb.trb_2 = 0; 1729 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1730 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1731 1732 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1733 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1734 1735 xhci_ring_free(sc, &xs->xs_xr[dci]); 1736 } 1737 1738 /* 1739 * Abort transfer. 1740 * Should be called with sc_lock held. 1741 */ 1742 static void 1743 xhci_abortx(struct usbd_xfer *xfer) 1744 { 1745 XHCIHIST_FUNC(); 1746 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1747 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1748 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1749 1750 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx", 1751 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0); 1752 1753 KASSERT(mutex_owned(&sc->sc_lock)); 1754 ASSERT_SLEEPABLE(); 1755 1756 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 1757 xfer->ux_status == USBD_TIMEOUT), 1758 "bad abort status: %d", xfer->ux_status); 1759 1760 /* 1761 * If we're dying, skip the hardware action and just notify the 1762 * software that we're done. 1763 */ 1764 if (sc->sc_dying) { 1765 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1766 xfer->ux_status, 0, 0); 1767 goto dying; 1768 } 1769 1770 /* 1771 * HC Step 1: Stop execution of TD on the ring. 1772 */ 1773 switch (xhci_get_epstate(sc, xs, dci)) { 1774 case XHCI_EPSTATE_HALTED: 1775 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1776 break; 1777 case XHCI_EPSTATE_STOPPED: 1778 break; 1779 default: 1780 (void)xhci_stop_endpoint(xfer->ux_pipe); 1781 break; 1782 } 1783 #ifdef DIAGNOSTIC 1784 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1785 if (epst != XHCI_EPSTATE_STOPPED) 1786 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1787 #endif 1788 1789 /* 1790 * HC Step 2: Remove any vestiges of the xfer from the ring. 1791 */ 1792 xhci_set_dequeue_locked(xfer->ux_pipe); 1793 1794 /* 1795 * Final Step: Notify completion to waiting xfers. 1796 */ 1797 dying: 1798 usb_transfer_complete(xfer); 1799 DPRINTFN(14, "end", 0, 0, 0, 0); 1800 1801 KASSERT(mutex_owned(&sc->sc_lock)); 1802 } 1803 1804 static void 1805 xhci_host_dequeue(struct xhci_ring * const xr) 1806 { 1807 /* When dequeueing the controller, update our struct copy too */ 1808 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1809 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1810 BUS_DMASYNC_PREWRITE); 1811 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1812 1813 xr->xr_ep = 0; 1814 xr->xr_cs = 1; 1815 } 1816 1817 /* 1818 * Recover STALLed endpoint. 1819 * xHCI 1.1 sect 4.10.2.1 1820 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1821 * all transfers on transfer ring. 1822 * These are done in thread context asynchronously. 1823 */ 1824 static void 1825 xhci_clear_endpoint_stall_async_task(void *cookie) 1826 { 1827 struct usbd_xfer * const xfer = cookie; 1828 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1829 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1830 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1831 struct xhci_ring * const tr = xs->xs_xr[dci]; 1832 1833 XHCIHIST_FUNC(); 1834 XHCIHIST_CALLARGS("xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1835 dci, 0); 1836 1837 /* 1838 * XXXMRG: Stall task can run after slot is disabled when yanked. 1839 * This hack notices that the xs has been memset() in 1840 * xhci_disable_slot() and returns. Both xhci_reset_endpoint() 1841 * and xhci_set_dequeue() rely upon a valid ring setup for correct 1842 * operation, and the latter will fault, as would 1843 * usb_transfer_complete() if it got that far. 1844 */ 1845 if (xs->xs_idx == 0) { 1846 DPRINTFN(4, "ends xs_idx is 0", 0, 0, 0, 0); 1847 return; 1848 } 1849 1850 KASSERT(tr != NULL); 1851 1852 xhci_reset_endpoint(xfer->ux_pipe); 1853 xhci_set_dequeue(xfer->ux_pipe); 1854 1855 mutex_enter(&sc->sc_lock); 1856 tr->is_halted = false; 1857 usb_transfer_complete(xfer); 1858 mutex_exit(&sc->sc_lock); 1859 DPRINTFN(4, "ends", 0, 0, 0, 0); 1860 } 1861 1862 static usbd_status 1863 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1864 { 1865 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1866 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1867 1868 XHCIHIST_FUNC(); 1869 XHCIHIST_CALLARGS("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1870 1871 if (sc->sc_dying) { 1872 return USBD_IOERROR; 1873 } 1874 1875 usb_init_task(&xp->xp_async_task, 1876 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1877 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1878 DPRINTFN(4, "ends", 0, 0, 0, 0); 1879 1880 return USBD_NORMAL_COMPLETION; 1881 } 1882 1883 /* Process roothub port status/change events and notify to uhub_intr. */ 1884 static void 1885 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1886 { 1887 XHCIHIST_FUNC(); 1888 XHCIHIST_CALLARGS("xhci%jd: port %ju status change", 1889 device_unit(sc->sc_dev), ctlrport, 0, 0); 1890 1891 if (ctlrport > sc->sc_maxports) 1892 return; 1893 1894 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1895 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1896 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1897 1898 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1899 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1900 1901 if (xfer == NULL) 1902 return; 1903 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1904 1905 uint8_t *p = xfer->ux_buf; 1906 memset(p, 0, xfer->ux_length); 1907 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1908 xfer->ux_actlen = xfer->ux_length; 1909 xfer->ux_status = USBD_NORMAL_COMPLETION; 1910 usb_transfer_complete(xfer); 1911 } 1912 1913 /* Process Transfer Events */ 1914 static void 1915 xhci_event_transfer(struct xhci_softc * const sc, 1916 const struct xhci_trb * const trb) 1917 { 1918 uint64_t trb_0; 1919 uint32_t trb_2, trb_3; 1920 uint8_t trbcode; 1921 u_int slot, dci; 1922 struct xhci_slot *xs; 1923 struct xhci_ring *xr; 1924 struct xhci_xfer *xx; 1925 struct usbd_xfer *xfer; 1926 usbd_status err; 1927 1928 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1929 1930 trb_0 = le64toh(trb->trb_0); 1931 trb_2 = le32toh(trb->trb_2); 1932 trb_3 = le32toh(trb->trb_3); 1933 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1934 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1935 dci = XHCI_TRB_3_EP_GET(trb_3); 1936 xs = &sc->sc_slots[slot]; 1937 xr = xs->xs_xr[dci]; 1938 1939 /* sanity check */ 1940 KASSERT(xr != NULL); 1941 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1942 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1943 1944 int idx = 0; 1945 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1946 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1947 DPRINTFN(0, "invalid trb_0 %#jx", trb_0, 0, 0, 0); 1948 return; 1949 } 1950 xx = xr->xr_cookies[idx]; 1951 1952 /* clear cookie of consumed TRB */ 1953 xr->xr_cookies[idx] = NULL; 1954 1955 /* 1956 * xx is NULL if pipe is opened but xfer is not started. 1957 * It happens when stopping idle pipe. 1958 */ 1959 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1960 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1961 idx, (uintptr_t)xx, trbcode, dci); 1962 DPRINTFN(1, " orig TRB %#jx type %ju", trb_0, 1963 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1964 0, 0); 1965 return; 1966 } 1967 } else { 1968 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1969 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1970 } 1971 /* XXX this may not happen */ 1972 if (xx == NULL) { 1973 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1974 return; 1975 } 1976 xfer = &xx->xx_xfer; 1977 /* XXX this may happen when detaching */ 1978 if (xfer == NULL) { 1979 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1980 (uintptr_t)xx, trb_0, 0, 0); 1981 return; 1982 } 1983 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1984 /* XXX I dunno why this happens */ 1985 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1986 1987 if (!xfer->ux_pipe->up_repeat && 1988 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1989 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1990 0, 0, 0); 1991 return; 1992 } 1993 1994 /* 1995 * Try to claim this xfer for completion. If it has already 1996 * completed or aborted, drop it on the floor. 1997 */ 1998 if (!usbd_xfer_trycomplete(xfer)) 1999 return; 2000 2001 /* 4.11.5.2 Event Data TRB */ 2002 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2003 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 2004 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 2005 if ((trb_0 & 0x3) == 0x3) { 2006 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 2007 } 2008 } 2009 2010 switch (trbcode) { 2011 case XHCI_TRB_ERROR_SHORT_PKT: 2012 case XHCI_TRB_ERROR_SUCCESS: 2013 /* 2014 * A ctrl transfer can generate two events if it has a Data 2015 * stage. A short data stage can be OK and should not 2016 * complete the transfer as the status stage needs to be 2017 * performed. 2018 * 2019 * Note: Data and Status stage events point at same xfer. 2020 * ux_actlen and ux_dmabuf will be passed to 2021 * usb_transfer_complete after the Status stage event. 2022 * 2023 * It can be distingished which stage generates the event: 2024 * + by checking least 3 bits of trb_0 if ED==1. 2025 * (see xhci_device_ctrl_start). 2026 * + by checking the type of original TRB if ED==0. 2027 * 2028 * In addition, intr, bulk, and isoc transfer currently 2029 * consists of single TD, so the "skip" is not needed. 2030 * ctrl xfer uses EVENT_DATA, and others do not. 2031 * Thus driver can switch the flow by checking ED bit. 2032 */ 2033 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2034 if (xfer->ux_actlen == 0) 2035 xfer->ux_actlen = xfer->ux_length - 2036 XHCI_TRB_2_REM_GET(trb_2); 2037 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 2038 == XHCI_TRB_TYPE_DATA_STAGE) { 2039 return; 2040 } 2041 } else if ((trb_0 & 0x3) == 0x3) { 2042 return; 2043 } 2044 err = USBD_NORMAL_COMPLETION; 2045 break; 2046 case XHCI_TRB_ERROR_STOPPED: 2047 case XHCI_TRB_ERROR_LENGTH: 2048 case XHCI_TRB_ERROR_STOPPED_SHORT: 2049 err = USBD_IOERROR; 2050 break; 2051 case XHCI_TRB_ERROR_STALL: 2052 case XHCI_TRB_ERROR_BABBLE: 2053 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2054 xr->is_halted = true; 2055 /* 2056 * Stalled endpoints can be recoverd by issuing 2057 * command TRB TYPE_RESET_EP on xHCI instead of 2058 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2059 * on the endpoint. However, this function may be 2060 * called from softint context (e.g. from umass), 2061 * in that case driver gets KASSERT in cv_timedwait 2062 * in xhci_do_command. 2063 * To avoid this, this runs reset_endpoint and 2064 * usb_transfer_complete in usb task thread 2065 * asynchronously (and then umass issues clear 2066 * UF_ENDPOINT_HALT). 2067 */ 2068 2069 /* Override the status. */ 2070 xfer->ux_status = USBD_STALLED; 2071 2072 xhci_clear_endpoint_stall_async(xfer); 2073 return; 2074 default: 2075 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2076 err = USBD_IOERROR; 2077 break; 2078 } 2079 2080 /* Set the status. */ 2081 xfer->ux_status = err; 2082 2083 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2084 (trb_0 & 0x3) == 0x0) { 2085 usb_transfer_complete(xfer); 2086 } 2087 } 2088 2089 /* Process Command complete events */ 2090 static void 2091 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2092 { 2093 uint64_t trb_0; 2094 uint32_t trb_2, trb_3; 2095 2096 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2097 2098 KASSERT(mutex_owned(&sc->sc_lock)); 2099 2100 trb_0 = le64toh(trb->trb_0); 2101 trb_2 = le32toh(trb->trb_2); 2102 trb_3 = le32toh(trb->trb_3); 2103 2104 if (trb_0 == sc->sc_command_addr) { 2105 sc->sc_resultpending = false; 2106 2107 sc->sc_result_trb.trb_0 = trb_0; 2108 sc->sc_result_trb.trb_2 = trb_2; 2109 sc->sc_result_trb.trb_3 = trb_3; 2110 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2111 XHCI_TRB_ERROR_SUCCESS) { 2112 DPRINTFN(1, "command completion " 2113 "failure: 0x%016jx 0x%08jx 0x%08jx", 2114 trb_0, trb_2, trb_3, 0); 2115 } 2116 cv_signal(&sc->sc_command_cv); 2117 } else { 2118 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2119 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2120 } 2121 } 2122 2123 /* 2124 * Process events. 2125 * called from xhci_softintr 2126 */ 2127 static void 2128 xhci_handle_event(struct xhci_softc * const sc, 2129 const struct xhci_trb * const trb) 2130 { 2131 uint64_t trb_0; 2132 uint32_t trb_2, trb_3; 2133 2134 XHCIHIST_FUNC(); 2135 2136 trb_0 = le64toh(trb->trb_0); 2137 trb_2 = le32toh(trb->trb_2); 2138 trb_3 = le32toh(trb->trb_3); 2139 2140 XHCIHIST_CALLARGS("event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2141 (uintptr_t)trb, trb_0, trb_2, trb_3); 2142 2143 /* 2144 * 4.11.3.1, 6.4.2.1 2145 * TRB Pointer is invalid for these completion codes. 2146 */ 2147 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2148 case XHCI_TRB_ERROR_RING_UNDERRUN: 2149 case XHCI_TRB_ERROR_RING_OVERRUN: 2150 case XHCI_TRB_ERROR_VF_RING_FULL: 2151 return; 2152 default: 2153 if (trb_0 == 0) { 2154 return; 2155 } 2156 break; 2157 } 2158 2159 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2160 case XHCI_TRB_EVENT_TRANSFER: 2161 xhci_event_transfer(sc, trb); 2162 break; 2163 case XHCI_TRB_EVENT_CMD_COMPLETE: 2164 xhci_event_cmd(sc, trb); 2165 break; 2166 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2167 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2168 break; 2169 default: 2170 break; 2171 } 2172 } 2173 2174 static void 2175 xhci_softintr(void *v) 2176 { 2177 struct usbd_bus * const bus = v; 2178 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2179 struct xhci_ring * const er = sc->sc_er; 2180 struct xhci_trb *trb; 2181 int i, j, k; 2182 2183 XHCIHIST_FUNC(); 2184 2185 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2186 2187 i = er->xr_ep; 2188 j = er->xr_cs; 2189 2190 XHCIHIST_CALLARGS("er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2191 2192 while (1) { 2193 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2194 BUS_DMASYNC_POSTREAD); 2195 trb = &er->xr_trb[i]; 2196 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2197 2198 if (j != k) 2199 break; 2200 2201 xhci_handle_event(sc, trb); 2202 2203 i++; 2204 if (i == er->xr_ntrb) { 2205 i = 0; 2206 j ^= 1; 2207 } 2208 } 2209 2210 er->xr_ep = i; 2211 er->xr_cs = j; 2212 2213 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2214 XHCI_ERDP_LO_BUSY); 2215 2216 DPRINTFN(16, "ends", 0, 0, 0, 0); 2217 2218 return; 2219 } 2220 2221 static void 2222 xhci_poll(struct usbd_bus *bus) 2223 { 2224 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2225 2226 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2227 2228 mutex_enter(&sc->sc_intr_lock); 2229 int ret = xhci_intr1(sc); 2230 if (ret) { 2231 xhci_softintr(bus); 2232 } 2233 mutex_exit(&sc->sc_intr_lock); 2234 2235 return; 2236 } 2237 2238 static struct usbd_xfer * 2239 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2240 { 2241 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2242 struct usbd_xfer *xfer; 2243 2244 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2245 2246 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2247 if (xfer != NULL) { 2248 memset(xfer, 0, sizeof(struct xhci_xfer)); 2249 #ifdef DIAGNOSTIC 2250 xfer->ux_state = XFER_BUSY; 2251 #endif 2252 } 2253 2254 return xfer; 2255 } 2256 2257 static void 2258 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2259 { 2260 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2261 2262 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2263 2264 #ifdef DIAGNOSTIC 2265 if (xfer->ux_state != XFER_BUSY && 2266 xfer->ux_status != USBD_NOT_STARTED) { 2267 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2268 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2269 } 2270 xfer->ux_state = XFER_FREE; 2271 #endif 2272 pool_cache_put(sc->sc_xferpool, xfer); 2273 } 2274 2275 static bool 2276 xhci_dying(struct usbd_bus *bus) 2277 { 2278 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2279 2280 return sc->sc_dying; 2281 } 2282 2283 static void 2284 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2285 { 2286 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2287 2288 *lock = &sc->sc_lock; 2289 } 2290 2291 extern uint32_t usb_cookie_no; 2292 2293 /* 2294 * xHCI 4.3 2295 * Called when uhub_explore finds a new device (via usbd_new_device). 2296 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2297 * This function does: 2298 * Allocate and construct dev structure of default endpoint (ep0). 2299 * Allocate and open pipe of ep0. 2300 * Enable slot and initialize slot context. 2301 * Set Address. 2302 * Read initial device descriptor. 2303 * Determine initial MaxPacketSize (mps) by speed. 2304 * Read full device descriptor. 2305 * Register this device. 2306 * Finally state of device transitions ADDRESSED. 2307 */ 2308 static usbd_status 2309 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2310 int speed, int port, struct usbd_port *up) 2311 { 2312 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2313 struct usbd_device *dev; 2314 usbd_status err; 2315 usb_device_descriptor_t *dd; 2316 struct xhci_slot *xs; 2317 uint32_t *cp; 2318 2319 XHCIHIST_FUNC(); 2320 XHCIHIST_CALLARGS("port %ju depth %ju speed %ju up %#jx", 2321 port, depth, speed, (uintptr_t)up); 2322 2323 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2324 dev->ud_bus = bus; 2325 dev->ud_quirks = &usbd_no_quirk; 2326 dev->ud_addr = 0; 2327 dev->ud_ddesc.bMaxPacketSize = 0; 2328 dev->ud_depth = depth; 2329 dev->ud_powersrc = up; 2330 dev->ud_myhub = up->up_parent; 2331 dev->ud_speed = speed; 2332 dev->ud_langid = USBD_NOLANG; 2333 dev->ud_cookie.cookie = ++usb_cookie_no; 2334 2335 /* Set up default endpoint handle. */ 2336 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2337 /* doesn't matter, just don't let it uninitialized */ 2338 dev->ud_ep0.ue_toggle = 0; 2339 2340 /* Set up default endpoint descriptor. */ 2341 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2342 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2343 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2344 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2345 dev->ud_ep0desc.bInterval = 0; 2346 2347 /* 4.3, 4.8.2.1 */ 2348 switch (speed) { 2349 case USB_SPEED_SUPER: 2350 case USB_SPEED_SUPER_PLUS: 2351 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2352 break; 2353 case USB_SPEED_FULL: 2354 /* XXX using 64 as initial mps of ep0 in FS */ 2355 case USB_SPEED_HIGH: 2356 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2357 break; 2358 case USB_SPEED_LOW: 2359 default: 2360 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2361 break; 2362 } 2363 2364 up->up_dev = dev; 2365 2366 dd = &dev->ud_ddesc; 2367 2368 if (depth == 0 && port == 0) { 2369 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2370 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2371 2372 /* Establish the default pipe. */ 2373 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2374 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2375 if (err) { 2376 DPRINTFN(1, "setup default pipe failed %jd", err,0,0,0); 2377 goto bad; 2378 } 2379 err = usbd_get_initial_ddesc(dev, dd); 2380 if (err) { 2381 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2382 goto bad; 2383 } 2384 } else { 2385 uint8_t slot = 0; 2386 2387 /* 4.3.2 */ 2388 err = xhci_enable_slot(sc, &slot); 2389 if (err) { 2390 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2391 goto bad; 2392 } 2393 2394 xs = &sc->sc_slots[slot]; 2395 dev->ud_hcpriv = xs; 2396 2397 /* 4.3.3 initialize slot structure */ 2398 err = xhci_init_slot(dev, slot); 2399 if (err) { 2400 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2401 dev->ud_hcpriv = NULL; 2402 /* 2403 * We have to disable_slot here because 2404 * xs->xs_idx == 0 when xhci_init_slot fails, 2405 * in that case usbd_remove_dev won't work. 2406 */ 2407 mutex_enter(&sc->sc_lock); 2408 xhci_disable_slot(sc, slot); 2409 mutex_exit(&sc->sc_lock); 2410 goto bad; 2411 } 2412 2413 /* 2414 * We have to establish the default pipe _after_ slot 2415 * structure has been prepared. 2416 */ 2417 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2418 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2419 if (err) { 2420 DPRINTFN(1, "setup default pipe failed %jd", err, 0, 0, 2421 0); 2422 goto bad; 2423 } 2424 2425 /* 4.3.4 Address Assignment */ 2426 err = xhci_set_address(dev, slot, false); 2427 if (err) { 2428 DPRINTFN(1, "failed! to set address: %ju", err, 0, 0, 0); 2429 goto bad; 2430 } 2431 2432 /* Allow device time to set new address */ 2433 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2434 2435 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2436 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2437 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2438 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2439 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2440 /* 2441 * XXX ensure we know when the hardware does something 2442 * we can't yet cope with 2443 */ 2444 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2445 dev->ud_addr = addr; 2446 2447 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2448 "addr %d already allocated", dev->ud_addr); 2449 /* 2450 * The root hub is given its own slot 2451 */ 2452 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2453 2454 err = usbd_get_initial_ddesc(dev, dd); 2455 if (err) { 2456 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2457 goto bad; 2458 } 2459 2460 /* 4.8.2.1 */ 2461 if (USB_IS_SS(speed)) { 2462 if (dd->bMaxPacketSize != 9) { 2463 printf("%s: invalid mps 2^%u for SS ep0," 2464 " using 512\n", 2465 device_xname(sc->sc_dev), 2466 dd->bMaxPacketSize); 2467 dd->bMaxPacketSize = 9; 2468 } 2469 USETW(dev->ud_ep0desc.wMaxPacketSize, 2470 (1 << dd->bMaxPacketSize)); 2471 } else 2472 USETW(dev->ud_ep0desc.wMaxPacketSize, 2473 dd->bMaxPacketSize); 2474 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2475 err = xhci_update_ep0_mps(sc, xs, 2476 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2477 if (err) { 2478 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2479 goto bad; 2480 } 2481 } 2482 2483 err = usbd_reload_device_desc(dev); 2484 if (err) { 2485 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2486 goto bad; 2487 } 2488 2489 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2490 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2491 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2492 dd->bDeviceClass, dd->bDeviceSubClass, 2493 dd->bDeviceProtocol, 0); 2494 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2495 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2496 dev->ud_speed); 2497 2498 usbd_get_device_strings(dev); 2499 2500 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2501 2502 if (depth == 0 && port == 0) { 2503 usbd_attach_roothub(parent, dev); 2504 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2505 return USBD_NORMAL_COMPLETION; 2506 } 2507 2508 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2509 bad: 2510 if (err != USBD_NORMAL_COMPLETION) { 2511 usbd_remove_device(dev, up); 2512 } 2513 2514 return err; 2515 } 2516 2517 static usbd_status 2518 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring **xrp, 2519 size_t ntrb, size_t align) 2520 { 2521 usbd_status err; 2522 size_t size = ntrb * XHCI_TRB_SIZE; 2523 struct xhci_ring *xr; 2524 2525 XHCIHIST_FUNC(); 2526 XHCIHIST_CALLARGS("xr %#jx ntrb %#jx align %#jx", 2527 (uintptr_t)*xrp, ntrb, align, 0); 2528 2529 xr = kmem_zalloc(sizeof(struct xhci_ring), KM_SLEEP); 2530 DPRINTFN(1, "ring %#jx", (uintptr_t)xr, 0, 0, 0); 2531 2532 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2533 if (err) { 2534 kmem_free(xr, sizeof(struct xhci_ring)); 2535 DPRINTFN(1, "alloc xr_dma failed %jd", err, 0, 0, 0); 2536 return err; 2537 } 2538 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2539 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2540 xr->xr_trb = xhci_ring_trbv(xr, 0); 2541 xr->xr_ntrb = ntrb; 2542 xr->is_halted = false; 2543 xhci_host_dequeue(xr); 2544 *xrp = xr; 2545 2546 return USBD_NORMAL_COMPLETION; 2547 } 2548 2549 static void 2550 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring ** const xr) 2551 { 2552 if (*xr == NULL) 2553 return; 2554 2555 usb_freemem(&sc->sc_bus, &(*xr)->xr_dma); 2556 mutex_destroy(&(*xr)->xr_lock); 2557 kmem_free((*xr)->xr_cookies, 2558 sizeof(*(*xr)->xr_cookies) * (*xr)->xr_ntrb); 2559 kmem_free(*xr, sizeof(struct xhci_ring)); 2560 *xr = NULL; 2561 } 2562 2563 static void 2564 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2565 void *cookie, struct xhci_soft_trb * const trbs, size_t ntrbs) 2566 { 2567 size_t i; 2568 u_int ri; 2569 u_int cs; 2570 uint64_t parameter; 2571 uint32_t status; 2572 uint32_t control; 2573 2574 XHCIHIST_FUNC(); 2575 XHCIHIST_CALLARGS("%#jx xr_ep %#jx xr_cs %ju", 2576 (uintptr_t)xr, xr->xr_ep, xr->xr_cs, 0); 2577 2578 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2579 for (i = 0; i < ntrbs; i++) { 2580 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2581 (uintptr_t)trbs, i, 0); 2582 DPRINTFN(12, " 0x%016jx 0x%08jx 0x%08jx", 2583 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2584 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2585 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2586 } 2587 2588 ri = xr->xr_ep; 2589 cs = xr->xr_cs; 2590 2591 /* 2592 * Although the xhci hardware can do scatter/gather dma from 2593 * arbitrary sized buffers, there is a non-obvious restriction 2594 * that a LINK trb is only allowed at the end of a burst of 2595 * transfers - which might be 16kB. 2596 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2597 * The simple solution is not to allow a LINK trb in the middle 2598 * of anything - as here. 2599 * XXX: (dsl) There are xhci controllers out there (eg some made by 2600 * ASMedia) that seem to lock up if they process a LINK trb but 2601 * cannot process the linked-to trb yet. 2602 * The code should write the 'cycle' bit on the link trb AFTER 2603 * adding the other trb. 2604 */ 2605 u_int firstep = xr->xr_ep; 2606 u_int firstcs = xr->xr_cs; 2607 2608 for (i = 0; i < ntrbs; ) { 2609 u_int oldri = ri; 2610 u_int oldcs = cs; 2611 2612 if (ri >= (xr->xr_ntrb - 1)) { 2613 /* Put Link TD at the end of ring */ 2614 parameter = xhci_ring_trbp(xr, 0); 2615 status = 0; 2616 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2617 XHCI_TRB_3_TC_BIT; 2618 xr->xr_cookies[ri] = NULL; 2619 xr->xr_ep = 0; 2620 xr->xr_cs ^= 1; 2621 ri = xr->xr_ep; 2622 cs = xr->xr_cs; 2623 } else { 2624 parameter = trbs[i].trb_0; 2625 status = trbs[i].trb_2; 2626 control = trbs[i].trb_3; 2627 2628 xr->xr_cookies[ri] = cookie; 2629 ri++; 2630 i++; 2631 } 2632 /* 2633 * If this is a first TRB, mark it invalid to prevent 2634 * xHC from running it immediately. 2635 */ 2636 if (oldri == firstep) { 2637 if (oldcs) { 2638 control &= ~XHCI_TRB_3_CYCLE_BIT; 2639 } else { 2640 control |= XHCI_TRB_3_CYCLE_BIT; 2641 } 2642 } else { 2643 if (oldcs) { 2644 control |= XHCI_TRB_3_CYCLE_BIT; 2645 } else { 2646 control &= ~XHCI_TRB_3_CYCLE_BIT; 2647 } 2648 } 2649 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2650 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2651 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2652 } 2653 2654 /* Now invert cycle bit of first TRB */ 2655 if (firstcs) { 2656 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2657 } else { 2658 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2659 } 2660 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2661 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2662 2663 xr->xr_ep = ri; 2664 xr->xr_cs = cs; 2665 2666 DPRINTFN(12, "%#jx xr_ep %#jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2667 xr->xr_cs, 0); 2668 } 2669 2670 /* 2671 * Stop execution commands, purge all commands on command ring, and 2672 * rewind dequeue pointer. 2673 */ 2674 static void 2675 xhci_abort_command(struct xhci_softc *sc) 2676 { 2677 struct xhci_ring * const cr = sc->sc_cr; 2678 uint64_t crcr; 2679 int i; 2680 2681 XHCIHIST_FUNC(); 2682 XHCIHIST_CALLARGS("command %#jx timeout, aborting", 2683 sc->sc_command_addr, 0, 0, 0); 2684 2685 mutex_enter(&cr->xr_lock); 2686 2687 /* 4.6.1.2 Aborting a Command */ 2688 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2689 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2690 2691 for (i = 0; i < 500; i++) { 2692 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2693 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2694 break; 2695 usb_delay_ms(&sc->sc_bus, 1); 2696 } 2697 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2698 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2699 /* reset HC here? */ 2700 } 2701 2702 /* reset command ring dequeue pointer */ 2703 cr->xr_ep = 0; 2704 cr->xr_cs = 1; 2705 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2706 2707 mutex_exit(&cr->xr_lock); 2708 } 2709 2710 /* 2711 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2712 * Command completion is notified by cv_signal from xhci_event_cmd() 2713 * (called from xhci_softint), or timed-out. 2714 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2715 * then do_command examines it. 2716 */ 2717 static usbd_status 2718 xhci_do_command_locked(struct xhci_softc * const sc, 2719 struct xhci_soft_trb * const trb, int timeout) 2720 { 2721 struct xhci_ring * const cr = sc->sc_cr; 2722 usbd_status err; 2723 2724 XHCIHIST_FUNC(); 2725 XHCIHIST_CALLARGS("input: 0x%016jx 0x%08jx 0x%08jx", 2726 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2727 2728 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2729 KASSERT(mutex_owned(&sc->sc_lock)); 2730 2731 while (sc->sc_command_addr != 0) 2732 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2733 2734 /* 2735 * If enqueue pointer points at last of ring, it's Link TRB, 2736 * command TRB will be stored in 0th TRB. 2737 */ 2738 if (cr->xr_ep == cr->xr_ntrb - 1) 2739 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2740 else 2741 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2742 2743 sc->sc_resultpending = true; 2744 2745 mutex_enter(&cr->xr_lock); 2746 xhci_ring_put(sc, cr, NULL, trb, 1); 2747 mutex_exit(&cr->xr_lock); 2748 2749 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2750 2751 while (sc->sc_resultpending) { 2752 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2753 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2754 xhci_abort_command(sc); 2755 err = USBD_TIMEOUT; 2756 goto timedout; 2757 } 2758 } 2759 2760 trb->trb_0 = sc->sc_result_trb.trb_0; 2761 trb->trb_2 = sc->sc_result_trb.trb_2; 2762 trb->trb_3 = sc->sc_result_trb.trb_3; 2763 2764 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2765 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2766 2767 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2768 case XHCI_TRB_ERROR_SUCCESS: 2769 err = USBD_NORMAL_COMPLETION; 2770 break; 2771 default: 2772 case 192 ... 223: 2773 DPRINTFN(5, "error %#jx", 2774 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0); 2775 err = USBD_IOERROR; 2776 break; 2777 case 224 ... 255: 2778 err = USBD_NORMAL_COMPLETION; 2779 break; 2780 } 2781 2782 timedout: 2783 sc->sc_resultpending = false; 2784 sc->sc_command_addr = 0; 2785 cv_broadcast(&sc->sc_cmdbusy_cv); 2786 2787 return err; 2788 } 2789 2790 static usbd_status 2791 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb, 2792 int timeout) 2793 { 2794 2795 mutex_enter(&sc->sc_lock); 2796 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2797 mutex_exit(&sc->sc_lock); 2798 2799 return ret; 2800 } 2801 2802 static usbd_status 2803 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2804 { 2805 struct xhci_soft_trb trb; 2806 usbd_status err; 2807 2808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2809 2810 trb.trb_0 = 0; 2811 trb.trb_2 = 0; 2812 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2813 2814 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2815 if (err != USBD_NORMAL_COMPLETION) { 2816 return err; 2817 } 2818 2819 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2820 2821 return err; 2822 } 2823 2824 /* 2825 * xHCI 4.6.4 2826 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2827 * All endpoints in the slot should be stopped. 2828 * Should be called with sc_lock held. 2829 */ 2830 static usbd_status 2831 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2832 { 2833 struct xhci_soft_trb trb; 2834 struct xhci_slot *xs; 2835 usbd_status err; 2836 2837 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2838 2839 if (sc->sc_dying) 2840 return USBD_IOERROR; 2841 2842 trb.trb_0 = 0; 2843 trb.trb_2 = 0; 2844 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) | 2845 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT); 2846 2847 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2848 2849 if (!err) { 2850 xs = &sc->sc_slots[slot]; 2851 if (xs->xs_idx != 0) { 2852 xhci_free_slot(sc, xs); 2853 xhci_set_dcba(sc, 0, slot); 2854 memset(xs, 0, sizeof(*xs)); 2855 } 2856 } 2857 2858 return err; 2859 } 2860 2861 /* 2862 * Set address of device and transition slot state from ENABLED to ADDRESSED 2863 * if Block Setaddress Request (BSR) is false. 2864 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2865 * see xHCI 1.1 4.5.3, 3.3.4 2866 * Should be called without sc_lock held. 2867 */ 2868 static usbd_status 2869 xhci_address_device(struct xhci_softc * const sc, 2870 uint64_t icp, uint8_t slot_id, bool bsr) 2871 { 2872 struct xhci_soft_trb trb; 2873 usbd_status err; 2874 2875 XHCIHIST_FUNC(); 2876 if (bsr) { 2877 XHCIHIST_CALLARGS("icp %#jx slot %#jx with bsr", 2878 icp, slot_id, 0, 0); 2879 } else { 2880 XHCIHIST_CALLARGS("icp %#jx slot %#jx nobsr", 2881 icp, slot_id, 0, 0); 2882 } 2883 2884 trb.trb_0 = icp; 2885 trb.trb_2 = 0; 2886 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2887 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2888 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2889 2890 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2891 2892 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2893 err = USBD_NO_ADDR; 2894 2895 return err; 2896 } 2897 2898 static usbd_status 2899 xhci_update_ep0_mps(struct xhci_softc * const sc, 2900 struct xhci_slot * const xs, u_int mps) 2901 { 2902 struct xhci_soft_trb trb; 2903 usbd_status err; 2904 uint32_t * cp; 2905 2906 XHCIHIST_FUNC(); 2907 XHCIHIST_CALLARGS("slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2908 2909 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2910 cp[0] = htole32(0); 2911 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2912 2913 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2914 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2915 2916 /* sync input contexts before they are read from memory */ 2917 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2918 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2919 sc->sc_ctxsz * 4); 2920 2921 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2922 trb.trb_2 = 0; 2923 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2924 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2925 2926 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2927 return err; 2928 } 2929 2930 static void 2931 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2932 { 2933 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2934 2935 XHCIHIST_FUNC(); 2936 XHCIHIST_CALLARGS("dcbaa %#jx dc 0x%016jx slot %jd", 2937 (uintptr_t)&dcbaa[si], dcba, si, 0); 2938 2939 dcbaa[si] = htole64(dcba); 2940 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2941 BUS_DMASYNC_PREWRITE); 2942 } 2943 2944 /* 2945 * Allocate device and input context DMA buffer, and 2946 * TRB DMA buffer for each endpoint. 2947 */ 2948 static usbd_status 2949 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2950 { 2951 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2952 struct xhci_slot *xs; 2953 usbd_status err; 2954 2955 XHCIHIST_FUNC(); 2956 XHCIHIST_CALLARGS("slot %ju", slot, 0, 0, 0); 2957 2958 xs = &sc->sc_slots[slot]; 2959 2960 /* allocate contexts */ 2961 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2962 &xs->xs_dc_dma); 2963 if (err) { 2964 DPRINTFN(1, "failed to allocmem output device context %jd", 2965 err, 0, 0, 0); 2966 return err; 2967 } 2968 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2969 2970 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2971 &xs->xs_ic_dma); 2972 if (err) { 2973 DPRINTFN(1, "failed to allocmem input device context %jd", 2974 err, 0, 0, 0); 2975 goto bad1; 2976 } 2977 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2978 2979 memset(&xs->xs_xr[0], 0, sizeof(xs->xs_xr)); 2980 xs->xs_idx = slot; 2981 2982 return USBD_NORMAL_COMPLETION; 2983 2984 bad1: 2985 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2986 xs->xs_idx = 0; 2987 return err; 2988 } 2989 2990 static void 2991 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs) 2992 { 2993 u_int dci; 2994 2995 XHCIHIST_FUNC(); 2996 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 2997 2998 /* deallocate all allocated rings in the slot */ 2999 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 3000 if (xs->xs_xr[dci] != NULL) 3001 xhci_ring_free(sc, &xs->xs_xr[dci]); 3002 } 3003 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 3004 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3005 xs->xs_idx = 0; 3006 } 3007 3008 /* 3009 * Setup slot context, set Device Context Base Address, and issue 3010 * Set Address Device command. 3011 */ 3012 static usbd_status 3013 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 3014 { 3015 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3016 struct xhci_slot *xs; 3017 usbd_status err; 3018 3019 XHCIHIST_FUNC(); 3020 XHCIHIST_CALLARGS("slot %ju bsr %ju", slot, bsr, 0, 0); 3021 3022 xs = &sc->sc_slots[slot]; 3023 3024 xhci_setup_ctx(dev->ud_pipe0); 3025 3026 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3027 sc->sc_ctxsz * 3); 3028 3029 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3030 3031 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3032 3033 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3034 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 3035 sc->sc_ctxsz * 2); 3036 3037 return err; 3038 } 3039 3040 /* 3041 * 4.8.2, 6.2.3.2 3042 * construct slot/endpoint context parameters and do syncmem 3043 */ 3044 static void 3045 xhci_setup_ctx(struct usbd_pipe *pipe) 3046 { 3047 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3048 struct usbd_device *dev = pipe->up_dev; 3049 struct xhci_slot * const xs = dev->ud_hcpriv; 3050 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3051 const u_int dci = xhci_ep_get_dci(ed); 3052 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3053 uint32_t *cp; 3054 uint16_t mps = UGETW(ed->wMaxPacketSize); 3055 uint8_t speed = dev->ud_speed; 3056 uint8_t ival = ed->bInterval; 3057 3058 XHCIHIST_FUNC(); 3059 XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju", 3060 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3061 3062 /* set up initial input control context */ 3063 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3064 cp[0] = htole32(0); 3065 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3066 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3067 cp[7] = htole32(0); 3068 3069 /* set up input slot context */ 3070 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3071 cp[0] = 3072 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3073 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3074 cp[1] = 0; 3075 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3076 cp[3] = 0; 3077 xhci_setup_route(pipe, cp); 3078 xhci_setup_tthub(pipe, cp); 3079 3080 cp[0] = htole32(cp[0]); 3081 cp[1] = htole32(cp[1]); 3082 cp[2] = htole32(cp[2]); 3083 cp[3] = htole32(cp[3]); 3084 3085 /* set up input endpoint context */ 3086 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3087 cp[0] = 3088 XHCI_EPCTX_0_EPSTATE_SET(0) | 3089 XHCI_EPCTX_0_MULT_SET(0) | 3090 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3091 XHCI_EPCTX_0_LSA_SET(0) | 3092 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3093 cp[1] = 3094 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3095 XHCI_EPCTX_1_HID_SET(0) | 3096 XHCI_EPCTX_1_MAXB_SET(0); 3097 3098 if (xfertype != UE_ISOCHRONOUS) 3099 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3100 3101 if (xfertype == UE_CONTROL) 3102 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3103 else if (USB_IS_SS(speed)) 3104 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3105 else 3106 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3107 3108 xhci_setup_maxburst(pipe, cp); 3109 3110 switch (xfertype) { 3111 case UE_CONTROL: 3112 break; 3113 case UE_BULK: 3114 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3115 break; 3116 case UE_INTERRUPT: 3117 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3118 ival = pipe->up_interval; 3119 3120 ival = xhci_bival2ival(ival, speed); 3121 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3122 break; 3123 case UE_ISOCHRONOUS: 3124 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3125 ival = pipe->up_interval; 3126 3127 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3128 if (speed == USB_SPEED_FULL) 3129 ival += 3; /* 1ms -> 125us */ 3130 ival--; 3131 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3132 break; 3133 default: 3134 break; 3135 } 3136 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3137 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3138 3139 /* rewind TR dequeue pointer in xHC */ 3140 /* can't use xhci_ep_get_dci() yet? */ 3141 *(uint64_t *)(&cp[2]) = htole64( 3142 xhci_ring_trbp(xs->xs_xr[dci], 0) | 3143 XHCI_EPCTX_2_DCS_SET(1)); 3144 3145 cp[0] = htole32(cp[0]); 3146 cp[1] = htole32(cp[1]); 3147 cp[4] = htole32(cp[4]); 3148 3149 /* rewind TR dequeue pointer in driver */ 3150 struct xhci_ring *xr = xs->xs_xr[dci]; 3151 mutex_enter(&xr->xr_lock); 3152 xhci_host_dequeue(xr); 3153 mutex_exit(&xr->xr_lock); 3154 3155 /* sync input contexts before they are read from memory */ 3156 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3157 } 3158 3159 /* 3160 * Setup route string and roothub port of given device for slot context 3161 */ 3162 static void 3163 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3164 { 3165 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3166 struct usbd_device *dev = pipe->up_dev; 3167 struct usbd_port *up = dev->ud_powersrc; 3168 struct usbd_device *hub; 3169 struct usbd_device *adev; 3170 uint8_t rhport = 0; 3171 uint32_t route = 0; 3172 3173 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3174 3175 /* Locate root hub port and Determine route string */ 3176 /* 4.3.3 route string does not include roothub port */ 3177 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3178 uint32_t dep; 3179 3180 DPRINTFN(4, "hub %#jx depth %jd upport %#jx upportno %jd", 3181 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3182 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3183 -1); 3184 3185 if (hub->ud_powersrc == NULL) 3186 break; 3187 dep = hub->ud_depth; 3188 if (dep == 0) 3189 break; 3190 rhport = hub->ud_powersrc->up_portno; 3191 if (dep > USB_HUB_MAX_DEPTH) 3192 continue; 3193 3194 route |= 3195 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3196 << ((dep - 1) * 4); 3197 } 3198 route = route >> 4; 3199 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3200 3201 /* Locate port on upstream high speed hub */ 3202 for (adev = dev, hub = up->up_parent; 3203 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3204 adev = hub, hub = hub->ud_myhub) 3205 ; 3206 if (hub) { 3207 int p; 3208 for (p = 1; p <= hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3209 if (hub->ud_hub->uh_ports[p - 1].up_dev == adev) { 3210 dev->ud_myhsport = &hub->ud_hub->uh_ports[p - 1]; 3211 goto found; 3212 } 3213 } 3214 panic("%s: cannot find HS port", __func__); 3215 found: 3216 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3217 } else { 3218 dev->ud_myhsport = NULL; 3219 } 3220 3221 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3222 3223 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3224 ctlrport, route, (uintptr_t)hub); 3225 3226 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3227 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3228 } 3229 3230 /* 3231 * Setup whether device is hub, whether device uses MTT, and 3232 * TT informations if it uses MTT. 3233 */ 3234 static void 3235 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3236 { 3237 struct usbd_device *dev = pipe->up_dev; 3238 struct usbd_port *myhsport = dev->ud_myhsport; 3239 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3240 uint32_t speed = dev->ud_speed; 3241 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3242 uint8_t tthubslot, ttportnum; 3243 bool ishub; 3244 bool usemtt; 3245 3246 XHCIHIST_FUNC(); 3247 3248 /* 3249 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3250 * tthubslot: 3251 * This is the slot ID of parent HS hub 3252 * if LS/FS device is connected && connected through HS hub. 3253 * This is 0 if device is not LS/FS device || 3254 * parent hub is not HS hub || 3255 * attached to root hub. 3256 * ttportnum: 3257 * This is the downstream facing port of parent HS hub 3258 * if LS/FS device is connected. 3259 * This is 0 if device is not LS/FS device || 3260 * parent hub is not HS hub || 3261 * attached to root hub. 3262 */ 3263 if (myhsport && 3264 myhsport->up_parent->ud_addr != rhaddr && 3265 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3266 ttportnum = myhsport->up_portno; 3267 tthubslot = myhsport->up_parent->ud_addr; 3268 } else { 3269 ttportnum = 0; 3270 tthubslot = 0; 3271 } 3272 XHCIHIST_CALLARGS("myhsport %#jx ttportnum=%jd tthubslot=%jd", 3273 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3274 3275 /* ishub is valid after reading UDESC_DEVICE */ 3276 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3277 3278 /* dev->ud_hub is valid after reading UDESC_HUB */ 3279 if (ishub && dev->ud_hub) { 3280 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3281 uint8_t ttt = 3282 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3283 3284 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3285 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3286 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3287 } 3288 3289 #define IS_MTTHUB(dd) \ 3290 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3291 3292 /* 3293 * MTT flag is set if 3294 * 1. this is HS hub && MTTs are supported and enabled; or 3295 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3296 * are supported and enabled. 3297 * 3298 * XXX enabled is not tested yet 3299 */ 3300 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3301 usemtt = true; 3302 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3303 myhsport && 3304 myhsport->up_parent->ud_addr != rhaddr && 3305 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3306 usemtt = true; 3307 else 3308 usemtt = false; 3309 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3310 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3311 3312 #undef IS_MTTHUB 3313 3314 cp[0] |= 3315 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3316 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3317 cp[2] |= 3318 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3319 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3320 } 3321 3322 /* set up params for periodic endpoint */ 3323 static void 3324 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3325 { 3326 struct usbd_device *dev = pipe->up_dev; 3327 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3328 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3329 usbd_desc_iter_t iter; 3330 const usb_cdc_descriptor_t *cdcd; 3331 uint32_t maxb = 0; 3332 uint16_t mps = UGETW(ed->wMaxPacketSize); 3333 uint8_t speed = dev->ud_speed; 3334 uint8_t ep; 3335 3336 /* config desc is NULL when opening ep0 */ 3337 if (dev == NULL || dev->ud_cdesc == NULL) 3338 goto no_cdcd; 3339 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3340 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3341 if (cdcd == NULL) 3342 goto no_cdcd; 3343 usb_desc_iter_init(dev, &iter); 3344 iter.cur = (const void *)cdcd; 3345 3346 /* find endpoint_ss_comp desc for ep of this pipe */ 3347 for (ep = 0;;) { 3348 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3349 if (cdcd == NULL) 3350 break; 3351 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3352 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3353 bEndpointAddress; 3354 if (UE_GET_ADDR(ep) == 3355 UE_GET_ADDR(ed->bEndpointAddress)) { 3356 cdcd = (const usb_cdc_descriptor_t *) 3357 usb_desc_iter_next(&iter); 3358 break; 3359 } 3360 ep = 0; 3361 } 3362 } 3363 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3364 const usb_endpoint_ss_comp_descriptor_t * esscd = 3365 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3366 maxb = esscd->bMaxBurst; 3367 } 3368 3369 no_cdcd: 3370 /* 6.2.3.4, 4.8.2.4 */ 3371 if (USB_IS_SS(speed)) { 3372 /* USB 3.1 9.6.6 */ 3373 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3374 /* USB 3.1 9.6.7 */ 3375 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3376 #ifdef notyet 3377 if (xfertype == UE_ISOCHRONOUS) { 3378 } 3379 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3380 /* use ESIT */ 3381 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3382 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3383 3384 /* XXX if LEC = 1, set ESIT instead */ 3385 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3386 } else { 3387 /* use ival */ 3388 } 3389 #endif 3390 } else { 3391 /* USB 2.0 9.6.6 */ 3392 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3393 3394 /* 6.2.3.4 */ 3395 if (speed == USB_SPEED_HIGH && 3396 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3397 maxb = UE_GET_TRANS(mps); 3398 } else { 3399 /* LS/FS or HS CTRL or HS BULK */ 3400 maxb = 0; 3401 } 3402 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3403 } 3404 } 3405 3406 /* 3407 * Convert endpoint bInterval value to endpoint context interval value 3408 * for Interrupt pipe. 3409 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3410 */ 3411 static uint32_t 3412 xhci_bival2ival(uint32_t ival, uint32_t speed) 3413 { 3414 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3415 int i; 3416 3417 /* 3418 * round ival down to "the nearest base 2 multiple of 3419 * bInterval * 8". 3420 * bInterval is at most 255 as its type is uByte. 3421 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3422 */ 3423 for (i = 10; i > 0; i--) { 3424 if ((ival * 8) >= (1 << i)) 3425 break; 3426 } 3427 ival = i; 3428 } else { 3429 /* Interval = bInterval-1 for SS/HS */ 3430 ival--; 3431 } 3432 3433 return ival; 3434 } 3435 3436 /* ----- */ 3437 3438 static void 3439 xhci_noop(struct usbd_pipe *pipe) 3440 { 3441 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3442 } 3443 3444 /* 3445 * Process root hub request. 3446 */ 3447 static int 3448 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3449 void *buf, int buflen) 3450 { 3451 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3452 usb_port_status_t ps; 3453 int l, totlen = 0; 3454 uint16_t len, value, index; 3455 int port, i; 3456 uint32_t v; 3457 3458 XHCIHIST_FUNC(); 3459 3460 if (sc->sc_dying) 3461 return -1; 3462 3463 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3464 3465 len = UGETW(req->wLength); 3466 value = UGETW(req->wValue); 3467 index = UGETW(req->wIndex); 3468 3469 XHCIHIST_CALLARGS("rhreq: %04jx %04jx %04jx %04jx", 3470 req->bmRequestType | (req->bRequest << 8), value, index, len); 3471 3472 #define C(x,y) ((x) | ((y) << 8)) 3473 switch (C(req->bRequest, req->bmRequestType)) { 3474 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3475 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3476 if (len == 0) 3477 break; 3478 switch (value) { 3479 #define sd ((usb_string_descriptor_t *)buf) 3480 case C(2, UDESC_STRING): 3481 /* Product */ 3482 totlen = usb_makestrdesc(sd, len, "xHCI root hub"); 3483 break; 3484 #undef sd 3485 default: 3486 /* default from usbroothub */ 3487 return buflen; 3488 } 3489 break; 3490 3491 /* Hub requests */ 3492 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3493 break; 3494 /* Clear Port Feature request */ 3495 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3496 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3497 3498 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3499 index, value, bn, cp); 3500 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3501 return -1; 3502 } 3503 port = XHCI_PORTSC(cp); 3504 v = xhci_op_read_4(sc, port); 3505 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3506 v &= ~XHCI_PS_CLEAR; 3507 switch (value) { 3508 case UHF_PORT_ENABLE: 3509 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3510 break; 3511 case UHF_PORT_SUSPEND: 3512 return -1; 3513 case UHF_PORT_POWER: 3514 break; 3515 case UHF_PORT_TEST: 3516 case UHF_PORT_INDICATOR: 3517 return -1; 3518 case UHF_C_PORT_CONNECTION: 3519 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3520 break; 3521 case UHF_C_PORT_ENABLE: 3522 case UHF_C_PORT_SUSPEND: 3523 case UHF_C_PORT_OVER_CURRENT: 3524 return -1; 3525 case UHF_C_BH_PORT_RESET: 3526 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3527 break; 3528 case UHF_C_PORT_RESET: 3529 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3530 break; 3531 case UHF_C_PORT_LINK_STATE: 3532 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3533 break; 3534 case UHF_C_PORT_CONFIG_ERROR: 3535 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3536 break; 3537 default: 3538 return -1; 3539 } 3540 break; 3541 } 3542 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3543 if (len == 0) 3544 break; 3545 if ((value & 0xff) != 0) { 3546 return -1; 3547 } 3548 usb_hub_descriptor_t hubd; 3549 3550 totlen = uimin(buflen, sizeof(hubd)); 3551 memcpy(&hubd, buf, totlen); 3552 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3553 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3554 hubd.bPwrOn2PwrGood = 200; 3555 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3556 /* XXX can't find out? */ 3557 hubd.DeviceRemovable[i++] = 0; 3558 } 3559 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3560 totlen = uimin(totlen, hubd.bDescLength); 3561 memcpy(buf, &hubd, totlen); 3562 break; 3563 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3564 if (len != 4) { 3565 return -1; 3566 } 3567 memset(buf, 0, len); /* ? XXX */ 3568 totlen = len; 3569 break; 3570 /* Get Port Status request */ 3571 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3572 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3573 3574 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3575 bn, index, cp, 0); 3576 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3577 DPRINTFN(5, "bad get port status: index=%jd bn=%jd " 3578 "portcount=%jd", 3579 index, bn, sc->sc_rhportcount[bn], 0); 3580 return -1; 3581 } 3582 if (len != 4) { 3583 DPRINTFN(5, "bad get port status: len %jd != 4", 3584 len, 0, 0, 0); 3585 return -1; 3586 } 3587 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3588 DPRINTFN(4, "getrhportsc %jd 0x%08jx", cp, v, 0, 0); 3589 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3590 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3591 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3592 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3593 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3594 if (v & XHCI_PS_PR) i |= UPS_RESET; 3595 if (v & XHCI_PS_PP) { 3596 if (i & UPS_OTHER_SPEED) 3597 i |= UPS_PORT_POWER_SS; 3598 else 3599 i |= UPS_PORT_POWER; 3600 } 3601 if (i & UPS_OTHER_SPEED) 3602 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3603 if (sc->sc_vendor_port_status) 3604 i = sc->sc_vendor_port_status(sc, v, i); 3605 USETW(ps.wPortStatus, i); 3606 i = 0; 3607 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3608 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3609 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3610 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3611 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3612 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3613 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3614 USETW(ps.wPortChange, i); 3615 totlen = uimin(len, sizeof(ps)); 3616 memcpy(buf, &ps, totlen); 3617 DPRINTFN(5, "get port status: wPortStatus %#jx wPortChange %#jx" 3618 " totlen %jd", 3619 UGETW(ps.wPortStatus), UGETW(ps.wPortChange), totlen, 0); 3620 break; 3621 } 3622 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3623 return -1; 3624 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3625 break; 3626 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3627 break; 3628 /* Set Port Feature request */ 3629 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3630 int optval = (index >> 8) & 0xff; 3631 index &= 0xff; 3632 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3633 return -1; 3634 } 3635 3636 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3637 3638 port = XHCI_PORTSC(cp); 3639 v = xhci_op_read_4(sc, port); 3640 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3641 v &= ~XHCI_PS_CLEAR; 3642 switch (value) { 3643 case UHF_PORT_ENABLE: 3644 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3645 break; 3646 case UHF_PORT_SUSPEND: 3647 /* XXX suspend */ 3648 break; 3649 case UHF_PORT_RESET: 3650 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3651 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3652 /* Wait for reset to complete. */ 3653 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3654 if (sc->sc_dying) { 3655 return -1; 3656 } 3657 v = xhci_op_read_4(sc, port); 3658 if (v & XHCI_PS_PR) { 3659 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3660 usb_delay_ms(&sc->sc_bus, 10); 3661 /* XXX */ 3662 } 3663 break; 3664 case UHF_PORT_POWER: 3665 /* XXX power control */ 3666 break; 3667 /* XXX more */ 3668 case UHF_C_PORT_RESET: 3669 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3670 break; 3671 case UHF_PORT_U1_TIMEOUT: 3672 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3673 return -1; 3674 } 3675 port = XHCI_PORTPMSC(cp); 3676 v = xhci_op_read_4(sc, port); 3677 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3678 index, cp, v, 0); 3679 v &= ~XHCI_PM3_U1TO_SET(0xff); 3680 v |= XHCI_PM3_U1TO_SET(optval); 3681 xhci_op_write_4(sc, port, v); 3682 break; 3683 case UHF_PORT_U2_TIMEOUT: 3684 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3685 return -1; 3686 } 3687 port = XHCI_PORTPMSC(cp); 3688 v = xhci_op_read_4(sc, port); 3689 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3690 index, cp, v, 0); 3691 v &= ~XHCI_PM3_U2TO_SET(0xff); 3692 v |= XHCI_PM3_U2TO_SET(optval); 3693 xhci_op_write_4(sc, port, v); 3694 break; 3695 default: 3696 return -1; 3697 } 3698 } 3699 break; 3700 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3701 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3702 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3703 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3704 break; 3705 default: 3706 /* default from usbroothub */ 3707 return buflen; 3708 } 3709 3710 return totlen; 3711 } 3712 3713 /* root hub interrupt */ 3714 3715 static usbd_status 3716 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3717 { 3718 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3719 usbd_status err; 3720 3721 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3722 3723 /* Insert last in queue. */ 3724 mutex_enter(&sc->sc_lock); 3725 err = usb_insert_transfer(xfer); 3726 mutex_exit(&sc->sc_lock); 3727 if (err) 3728 return err; 3729 3730 /* Pipe isn't running, start first */ 3731 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3732 } 3733 3734 /* Wait for roothub port status/change */ 3735 static usbd_status 3736 xhci_root_intr_start(struct usbd_xfer *xfer) 3737 { 3738 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3739 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3740 const bool polling = xhci_polling_p(sc); 3741 3742 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3743 3744 if (sc->sc_dying) 3745 return USBD_IOERROR; 3746 3747 if (!polling) 3748 mutex_enter(&sc->sc_lock); 3749 KASSERT(sc->sc_intrxfer[bn] == NULL); 3750 sc->sc_intrxfer[bn] = xfer; 3751 xfer->ux_status = USBD_IN_PROGRESS; 3752 if (!polling) 3753 mutex_exit(&sc->sc_lock); 3754 3755 return USBD_IN_PROGRESS; 3756 } 3757 3758 static void 3759 xhci_root_intr_abort(struct usbd_xfer *xfer) 3760 { 3761 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3762 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3763 3764 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3765 3766 KASSERT(mutex_owned(&sc->sc_lock)); 3767 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3768 3769 /* If xfer has already completed, nothing to do here. */ 3770 if (sc->sc_intrxfer[bn] == NULL) 3771 return; 3772 3773 /* 3774 * Otherwise, sc->sc_intrxfer[bn] had better be this transfer. 3775 * Cancel it. 3776 */ 3777 KASSERT(sc->sc_intrxfer[bn] == xfer); 3778 xfer->ux_status = USBD_CANCELLED; 3779 usb_transfer_complete(xfer); 3780 } 3781 3782 static void 3783 xhci_root_intr_close(struct usbd_pipe *pipe) 3784 { 3785 struct xhci_softc * const sc __diagused = XHCI_PIPE2SC(pipe); 3786 const struct usbd_xfer *xfer __diagused = pipe->up_intrxfer; 3787 const size_t bn __diagused = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3788 3789 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3790 3791 KASSERT(mutex_owned(&sc->sc_lock)); 3792 3793 /* 3794 * Caller must guarantee the xfer has completed first, by 3795 * closing the pipe only after normal completion or an abort. 3796 */ 3797 KASSERT(sc->sc_intrxfer[bn] == NULL); 3798 } 3799 3800 static void 3801 xhci_root_intr_done(struct usbd_xfer *xfer) 3802 { 3803 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3804 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3805 3806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3807 3808 KASSERT(mutex_owned(&sc->sc_lock)); 3809 3810 /* Claim the xfer so it doesn't get completed again. */ 3811 KASSERT(sc->sc_intrxfer[bn] == xfer); 3812 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 3813 sc->sc_intrxfer[bn] = NULL; 3814 } 3815 3816 /* -------------- */ 3817 /* device control */ 3818 3819 static usbd_status 3820 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3821 { 3822 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3823 usbd_status err; 3824 3825 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3826 3827 /* Insert last in queue. */ 3828 mutex_enter(&sc->sc_lock); 3829 err = usb_insert_transfer(xfer); 3830 mutex_exit(&sc->sc_lock); 3831 if (err) 3832 return err; 3833 3834 /* Pipe isn't running, start first */ 3835 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3836 } 3837 3838 static usbd_status 3839 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3840 { 3841 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3842 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3843 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3844 struct xhci_ring * const tr = xs->xs_xr[dci]; 3845 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3846 usb_device_request_t * const req = &xfer->ux_request; 3847 const int isread = usbd_xfer_isread(xfer); 3848 const uint32_t len = UGETW(req->wLength); 3849 usb_dma_t * const dma = &xfer->ux_dmabuf; 3850 uint64_t parameter; 3851 uint32_t status; 3852 uint32_t control; 3853 u_int i; 3854 const bool polling = xhci_polling_p(sc); 3855 3856 XHCIHIST_FUNC(); 3857 XHCIHIST_CALLARGS("req: %04jx %04jx %04jx %04jx", 3858 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3859 UGETW(req->wIndex), UGETW(req->wLength)); 3860 3861 /* we rely on the bottom bits for extra info */ 3862 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3863 (uintptr_t) xfer); 3864 3865 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3866 3867 i = 0; 3868 3869 /* setup phase */ 3870 memcpy(¶meter, req, sizeof(parameter)); 3871 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3872 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3873 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3874 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3875 XHCI_TRB_3_IDT_BIT; 3876 /* we need parameter un-swapped on big endian, so pre-swap it here */ 3877 xhci_soft_trb_put(&xx->xx_trb[i++], htole64(parameter), status, control); 3878 3879 if (len != 0) { 3880 /* data phase */ 3881 parameter = DMAADDR(dma, 0); 3882 KASSERTMSG(len <= 0x10000, "len %d", len); 3883 status = XHCI_TRB_2_IRQ_SET(0) | 3884 XHCI_TRB_2_TDSZ_SET(0) | 3885 XHCI_TRB_2_BYTES_SET(len); 3886 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3887 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3888 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3889 XHCI_TRB_3_IOC_BIT; 3890 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 3891 } 3892 3893 parameter = 0; 3894 status = XHCI_TRB_2_IRQ_SET(0); 3895 /* the status stage has inverted direction */ 3896 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3897 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3898 XHCI_TRB_3_IOC_BIT; 3899 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 3900 3901 if (!polling) 3902 mutex_enter(&tr->xr_lock); 3903 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3904 if (!polling) 3905 mutex_exit(&tr->xr_lock); 3906 3907 if (!polling) 3908 mutex_enter(&sc->sc_lock); 3909 xfer->ux_status = USBD_IN_PROGRESS; 3910 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3911 usbd_xfer_schedule_timeout(xfer); 3912 if (!polling) 3913 mutex_exit(&sc->sc_lock); 3914 3915 return USBD_IN_PROGRESS; 3916 } 3917 3918 static void 3919 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3920 { 3921 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3922 usb_device_request_t *req = &xfer->ux_request; 3923 int len = UGETW(req->wLength); 3924 int rd = req->bmRequestType & UT_READ; 3925 3926 if (len) 3927 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3928 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3929 } 3930 3931 static void 3932 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3933 { 3934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3935 3936 usbd_xfer_abort(xfer); 3937 } 3938 3939 static void 3940 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3941 { 3942 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3943 3944 xhci_close_pipe(pipe); 3945 } 3946 3947 /* ------------------ */ 3948 /* device isochronous */ 3949 3950 /* ----------- */ 3951 /* device bulk */ 3952 3953 static usbd_status 3954 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3955 { 3956 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3957 usbd_status err; 3958 3959 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3960 3961 /* Insert last in queue. */ 3962 mutex_enter(&sc->sc_lock); 3963 err = usb_insert_transfer(xfer); 3964 mutex_exit(&sc->sc_lock); 3965 if (err) 3966 return err; 3967 3968 /* 3969 * Pipe isn't running (otherwise err would be USBD_INPROG), 3970 * so start it first. 3971 */ 3972 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3973 } 3974 3975 static usbd_status 3976 xhci_device_bulk_start(struct usbd_xfer *xfer) 3977 { 3978 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3979 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3980 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3981 struct xhci_ring * const tr = xs->xs_xr[dci]; 3982 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3983 const uint32_t len = xfer->ux_length; 3984 usb_dma_t * const dma = &xfer->ux_dmabuf; 3985 uint64_t parameter; 3986 uint32_t status; 3987 uint32_t control; 3988 u_int i = 0; 3989 const bool polling = xhci_polling_p(sc); 3990 3991 XHCIHIST_FUNC(); 3992 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 3993 (uintptr_t)xfer, xs->xs_idx, dci, 0); 3994 3995 if (sc->sc_dying) 3996 return USBD_IOERROR; 3997 3998 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3999 4000 parameter = DMAADDR(dma, 0); 4001 /* 4002 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 4003 * If the user supplied buffer crosses such a boundary then 2 4004 * (or more) TRB should be used. 4005 * If multiple TRB are used the td_size field must be set correctly. 4006 * For v1.0 devices (like ivy bridge) this is the number of usb data 4007 * blocks needed to complete the transfer. 4008 * Setting it to 1 in the last TRB causes an extra zero-length 4009 * data block be sent. 4010 * The earlier documentation differs, I don't know how it behaves. 4011 */ 4012 KASSERTMSG(len <= 0x10000, "len %d", len); 4013 status = XHCI_TRB_2_IRQ_SET(0) | 4014 XHCI_TRB_2_TDSZ_SET(0) | 4015 XHCI_TRB_2_BYTES_SET(len); 4016 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4017 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4018 XHCI_TRB_3_IOC_BIT; 4019 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4020 4021 if (!polling) 4022 mutex_enter(&tr->xr_lock); 4023 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4024 if (!polling) 4025 mutex_exit(&tr->xr_lock); 4026 4027 if (!polling) 4028 mutex_enter(&sc->sc_lock); 4029 xfer->ux_status = USBD_IN_PROGRESS; 4030 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4031 usbd_xfer_schedule_timeout(xfer); 4032 if (!polling) 4033 mutex_exit(&sc->sc_lock); 4034 4035 return USBD_IN_PROGRESS; 4036 } 4037 4038 static void 4039 xhci_device_bulk_done(struct usbd_xfer *xfer) 4040 { 4041 #ifdef USB_DEBUG 4042 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4043 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4044 #endif 4045 const int isread = usbd_xfer_isread(xfer); 4046 4047 XHCIHIST_FUNC(); 4048 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4049 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4050 4051 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4052 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4053 } 4054 4055 static void 4056 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4057 { 4058 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4059 4060 usbd_xfer_abort(xfer); 4061 } 4062 4063 static void 4064 xhci_device_bulk_close(struct usbd_pipe *pipe) 4065 { 4066 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4067 4068 xhci_close_pipe(pipe); 4069 } 4070 4071 /* ---------------- */ 4072 /* device interrupt */ 4073 4074 static usbd_status 4075 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4076 { 4077 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4078 usbd_status err; 4079 4080 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4081 4082 /* Insert last in queue. */ 4083 mutex_enter(&sc->sc_lock); 4084 err = usb_insert_transfer(xfer); 4085 mutex_exit(&sc->sc_lock); 4086 if (err) 4087 return err; 4088 4089 /* 4090 * Pipe isn't running (otherwise err would be USBD_INPROG), 4091 * so start it first. 4092 */ 4093 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4094 } 4095 4096 static usbd_status 4097 xhci_device_intr_start(struct usbd_xfer *xfer) 4098 { 4099 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4100 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4101 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4102 struct xhci_ring * const tr = xs->xs_xr[dci]; 4103 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4104 const uint32_t len = xfer->ux_length; 4105 const bool polling = xhci_polling_p(sc); 4106 usb_dma_t * const dma = &xfer->ux_dmabuf; 4107 uint64_t parameter; 4108 uint32_t status; 4109 uint32_t control; 4110 u_int i = 0; 4111 4112 XHCIHIST_FUNC(); 4113 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4114 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4115 4116 if (sc->sc_dying) 4117 return USBD_IOERROR; 4118 4119 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4120 4121 parameter = DMAADDR(dma, 0); 4122 KASSERTMSG(len <= 0x10000, "len %d", len); 4123 status = XHCI_TRB_2_IRQ_SET(0) | 4124 XHCI_TRB_2_TDSZ_SET(0) | 4125 XHCI_TRB_2_BYTES_SET(len); 4126 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4127 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4128 XHCI_TRB_3_IOC_BIT; 4129 xhci_soft_trb_put(&xx->xx_trb[i++], parameter, status, control); 4130 4131 if (!polling) 4132 mutex_enter(&tr->xr_lock); 4133 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4134 if (!polling) 4135 mutex_exit(&tr->xr_lock); 4136 4137 if (!polling) 4138 mutex_enter(&sc->sc_lock); 4139 xfer->ux_status = USBD_IN_PROGRESS; 4140 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4141 usbd_xfer_schedule_timeout(xfer); 4142 if (!polling) 4143 mutex_exit(&sc->sc_lock); 4144 4145 return USBD_IN_PROGRESS; 4146 } 4147 4148 static void 4149 xhci_device_intr_done(struct usbd_xfer *xfer) 4150 { 4151 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4152 #ifdef USB_DEBUG 4153 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4154 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4155 #endif 4156 const int isread = usbd_xfer_isread(xfer); 4157 4158 XHCIHIST_FUNC(); 4159 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4160 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4161 4162 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4163 4164 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4165 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4166 } 4167 4168 static void 4169 xhci_device_intr_abort(struct usbd_xfer *xfer) 4170 { 4171 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4172 4173 XHCIHIST_FUNC(); 4174 XHCIHIST_CALLARGS("%#jx", (uintptr_t)xfer, 0, 0, 0); 4175 4176 KASSERT(mutex_owned(&sc->sc_lock)); 4177 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4178 usbd_xfer_abort(xfer); 4179 } 4180 4181 static void 4182 xhci_device_intr_close(struct usbd_pipe *pipe) 4183 { 4184 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4185 4186 XHCIHIST_FUNC(); 4187 XHCIHIST_CALLARGS("%#jx", (uintptr_t)pipe, 0, 0, 0); 4188 4189 xhci_close_pipe(pipe); 4190 } 4191
Indexes created Fri Sep 26 08:10:20 GMT 2025