xhci.c revision 1.128
1 /* $NetBSD: xhci.c,v 1.128 2020/05/21 13:47:10 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.128 2020/05/21 13:47:10 jakllsch Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 119 #define XHCIHIST_FUNC() USBHIST_FUNC() 120 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 121 #define XHCIHIST_CALLARGS(FMT,A,B,C,D) \ 122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D) 123 124 #define XHCI_DCI_SLOT 0 125 #define XHCI_DCI_EP_CONTROL 1 126 127 #define XHCI_ICI_INPUT_CONTROL 0 128 129 struct xhci_pipe { 130 struct usbd_pipe xp_pipe; 131 struct usb_task xp_async_task; 132 }; 133 134 #define XHCI_COMMAND_RING_TRBS 256 135 #define XHCI_EVENT_RING_TRBS 256 136 #define XHCI_EVENT_RING_SEGMENTS 1 137 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 138 139 static usbd_status xhci_open(struct usbd_pipe *); 140 static void xhci_close_pipe(struct usbd_pipe *); 141 static int xhci_intr1(struct xhci_softc * const); 142 static void xhci_softintr(void *); 143 static void xhci_poll(struct usbd_bus *); 144 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 145 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 146 static void xhci_abortx(struct usbd_xfer *); 147 static bool xhci_dying(struct usbd_bus *); 148 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 149 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 150 struct usbd_port *); 151 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 152 void *, int); 153 154 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 155 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 156 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 157 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 158 159 static void xhci_host_dequeue(struct xhci_ring * const); 160 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 161 162 static usbd_status xhci_do_command(struct xhci_softc * const, 163 struct xhci_soft_trb * const, int); 164 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 165 struct xhci_soft_trb * const, int); 166 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 167 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *); 168 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 169 static usbd_status xhci_enable_slot(struct xhci_softc * const, 170 uint8_t * const); 171 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 172 static usbd_status xhci_address_device(struct xhci_softc * const, 173 uint64_t, uint8_t, bool); 174 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 175 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 176 struct xhci_slot * const, u_int); 177 static usbd_status xhci_ring_init(struct xhci_softc * const, 178 struct xhci_ring **, size_t, size_t); 179 static void xhci_ring_free(struct xhci_softc * const, 180 struct xhci_ring ** const); 181 182 static void xhci_setup_ctx(struct usbd_pipe *); 183 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 184 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 185 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 186 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 187 188 static void xhci_noop(struct usbd_pipe *); 189 190 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 191 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 192 static void xhci_root_intr_abort(struct usbd_xfer *); 193 static void xhci_root_intr_close(struct usbd_pipe *); 194 static void xhci_root_intr_done(struct usbd_xfer *); 195 196 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 197 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 198 static void xhci_device_ctrl_abort(struct usbd_xfer *); 199 static void xhci_device_ctrl_close(struct usbd_pipe *); 200 static void xhci_device_ctrl_done(struct usbd_xfer *); 201 202 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 203 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 204 static void xhci_device_intr_abort(struct usbd_xfer *); 205 static void xhci_device_intr_close(struct usbd_pipe *); 206 static void xhci_device_intr_done(struct usbd_xfer *); 207 208 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 209 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 210 static void xhci_device_bulk_abort(struct usbd_xfer *); 211 static void xhci_device_bulk_close(struct usbd_pipe *); 212 static void xhci_device_bulk_done(struct usbd_xfer *); 213 214 static const struct usbd_bus_methods xhci_bus_methods = { 215 .ubm_open = xhci_open, 216 .ubm_softint = xhci_softintr, 217 .ubm_dopoll = xhci_poll, 218 .ubm_allocx = xhci_allocx, 219 .ubm_freex = xhci_freex, 220 .ubm_abortx = xhci_abortx, 221 .ubm_dying = xhci_dying, 222 .ubm_getlock = xhci_get_lock, 223 .ubm_newdev = xhci_new_device, 224 .ubm_rhctrl = xhci_roothub_ctrl, 225 }; 226 227 static const struct usbd_pipe_methods xhci_root_intr_methods = { 228 .upm_transfer = xhci_root_intr_transfer, 229 .upm_start = xhci_root_intr_start, 230 .upm_abort = xhci_root_intr_abort, 231 .upm_close = xhci_root_intr_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_root_intr_done, 234 }; 235 236 237 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 238 .upm_transfer = xhci_device_ctrl_transfer, 239 .upm_start = xhci_device_ctrl_start, 240 .upm_abort = xhci_device_ctrl_abort, 241 .upm_close = xhci_device_ctrl_close, 242 .upm_cleartoggle = xhci_noop, 243 .upm_done = xhci_device_ctrl_done, 244 }; 245 246 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 247 .upm_cleartoggle = xhci_noop, 248 }; 249 250 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 251 .upm_transfer = xhci_device_bulk_transfer, 252 .upm_start = xhci_device_bulk_start, 253 .upm_abort = xhci_device_bulk_abort, 254 .upm_close = xhci_device_bulk_close, 255 .upm_cleartoggle = xhci_noop, 256 .upm_done = xhci_device_bulk_done, 257 }; 258 259 static const struct usbd_pipe_methods xhci_device_intr_methods = { 260 .upm_transfer = xhci_device_intr_transfer, 261 .upm_start = xhci_device_intr_start, 262 .upm_abort = xhci_device_intr_abort, 263 .upm_close = xhci_device_intr_close, 264 .upm_cleartoggle = xhci_noop, 265 .upm_done = xhci_device_intr_done, 266 }; 267 268 static inline uint32_t 269 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 270 { 271 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 272 } 273 274 static inline uint32_t 275 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 276 { 277 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 278 } 279 280 static inline void 281 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 282 uint32_t value) 283 { 284 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 285 } 286 287 #if 0 /* unused */ 288 static inline void 289 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 290 uint32_t value) 291 { 292 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 293 } 294 #endif /* unused */ 295 296 static inline uint32_t 297 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 298 { 299 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 300 } 301 302 static inline uint32_t 303 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 304 { 305 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 306 } 307 308 static inline void 309 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 310 uint32_t value) 311 { 312 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 313 } 314 315 static inline uint64_t 316 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 317 { 318 uint64_t value; 319 320 if (sc->sc_ac64) { 321 #ifdef XHCI_USE_BUS_SPACE_8 322 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 323 #else 324 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 325 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 326 offset + 4) << 32; 327 #endif 328 } else { 329 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 330 } 331 332 return value; 333 } 334 335 static inline void 336 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 337 uint64_t value) 338 { 339 if (sc->sc_ac64) { 340 #ifdef XHCI_USE_BUS_SPACE_8 341 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 342 #else 343 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 344 (value >> 0) & 0xffffffff); 345 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 346 (value >> 32) & 0xffffffff); 347 #endif 348 } else { 349 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 350 } 351 } 352 353 static inline void 354 xhci_op_barrier(const struct xhci_softc * const sc, bus_size_t offset, 355 bus_size_t len, int flags) 356 { 357 bus_space_barrier(sc->sc_iot, sc->sc_obh, offset, len, flags); 358 } 359 360 static inline uint32_t 361 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 362 { 363 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 364 } 365 366 static inline void 367 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 368 uint32_t value) 369 { 370 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 371 } 372 373 #if 0 /* unused */ 374 static inline uint64_t 375 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 376 { 377 uint64_t value; 378 379 if (sc->sc_ac64) { 380 #ifdef XHCI_USE_BUS_SPACE_8 381 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 382 #else 383 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 384 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 385 offset + 4) << 32; 386 #endif 387 } else { 388 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 389 } 390 391 return value; 392 } 393 #endif /* unused */ 394 395 static inline void 396 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 397 uint64_t value) 398 { 399 if (sc->sc_ac64) { 400 #ifdef XHCI_USE_BUS_SPACE_8 401 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 402 #else 403 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 404 (value >> 0) & 0xffffffff); 405 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 406 (value >> 32) & 0xffffffff); 407 #endif 408 } else { 409 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 410 } 411 } 412 413 #if 0 /* unused */ 414 static inline uint32_t 415 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 416 { 417 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 418 } 419 #endif /* unused */ 420 421 static inline void 422 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 423 uint32_t value) 424 { 425 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 426 } 427 428 /* --- */ 429 430 static inline uint8_t 431 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 432 { 433 u_int eptype = 0; 434 435 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 436 case UE_CONTROL: 437 eptype = 0x0; 438 break; 439 case UE_ISOCHRONOUS: 440 eptype = 0x1; 441 break; 442 case UE_BULK: 443 eptype = 0x2; 444 break; 445 case UE_INTERRUPT: 446 eptype = 0x3; 447 break; 448 } 449 450 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 451 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 452 return eptype | 0x4; 453 else 454 return eptype; 455 } 456 457 static u_int 458 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 459 { 460 /* xHCI 1.0 section 4.5.1 */ 461 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 462 u_int in = 0; 463 464 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 465 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 466 in = 1; 467 468 return epaddr * 2 + in; 469 } 470 471 static inline u_int 472 xhci_dci_to_ici(const u_int i) 473 { 474 return i + 1; 475 } 476 477 static inline void * 478 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 479 const u_int dci) 480 { 481 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 482 } 483 484 #if 0 /* unused */ 485 static inline bus_addr_t 486 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 487 const u_int dci) 488 { 489 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 490 } 491 #endif /* unused */ 492 493 static inline void * 494 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 495 const u_int ici) 496 { 497 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 498 } 499 500 static inline bus_addr_t 501 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 502 const u_int ici) 503 { 504 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 505 } 506 507 static inline struct xhci_trb * 508 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 509 { 510 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 511 } 512 513 static inline bus_addr_t 514 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 515 { 516 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 517 } 518 519 static inline void 520 xhci_xfer_put_trb(struct xhci_xfer * const xx, u_int idx, 521 uint64_t parameter, uint32_t status, uint32_t control) 522 { 523 KASSERTMSG(idx < xx->xx_ntrb, "idx=%u xx_ntrb=%u", idx, xx->xx_ntrb); 524 xx->xx_trb[idx].trb_0 = parameter; 525 xx->xx_trb[idx].trb_2 = status; 526 xx->xx_trb[idx].trb_3 = control; 527 } 528 529 static inline void 530 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 531 uint32_t control) 532 { 533 trb->trb_0 = htole64(parameter); 534 trb->trb_2 = htole32(status); 535 trb->trb_3 = htole32(control); 536 } 537 538 static int 539 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 540 { 541 /* base address of TRBs */ 542 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 543 544 /* trb_0 range sanity check */ 545 if (trb_0 == 0 || trb_0 < trbp || 546 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 547 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 548 return 1; 549 } 550 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 551 return 0; 552 } 553 554 static unsigned int 555 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 556 u_int dci) 557 { 558 uint32_t *cp; 559 560 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 561 cp = xhci_slot_get_dcv(sc, xs, dci); 562 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 563 } 564 565 static inline unsigned int 566 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 567 { 568 const unsigned int port = ctlrport - 1; 569 const uint8_t bit = __BIT(port % NBBY); 570 571 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 572 } 573 574 /* 575 * Return the roothub port for a controller port. Both are 1..n. 576 */ 577 static inline unsigned int 578 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 579 { 580 581 return sc->sc_ctlrportmap[ctrlport - 1]; 582 } 583 584 /* 585 * Return the controller port for a bus roothub port. Both are 1..n. 586 */ 587 static inline unsigned int 588 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 589 unsigned int rhport) 590 { 591 592 return sc->sc_rhportmap[bn][rhport - 1]; 593 } 594 595 /* --- */ 596 597 void 598 xhci_childdet(device_t self, device_t child) 599 { 600 struct xhci_softc * const sc = device_private(self); 601 602 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 603 if (child == sc->sc_child2) 604 sc->sc_child2 = NULL; 605 else if (child == sc->sc_child) 606 sc->sc_child = NULL; 607 } 608 609 int 610 xhci_detach(struct xhci_softc *sc, int flags) 611 { 612 int rv = 0; 613 614 if (sc->sc_child2 != NULL) { 615 rv = config_detach(sc->sc_child2, flags); 616 if (rv != 0) 617 return rv; 618 KASSERT(sc->sc_child2 == NULL); 619 } 620 621 if (sc->sc_child != NULL) { 622 rv = config_detach(sc->sc_child, flags); 623 if (rv != 0) 624 return rv; 625 KASSERT(sc->sc_child == NULL); 626 } 627 628 /* XXX unconfigure/free slots */ 629 630 /* verify: */ 631 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 632 xhci_op_write_4(sc, XHCI_USBCMD, 0); 633 /* do we need to wait for stop? */ 634 635 xhci_op_write_8(sc, XHCI_CRCR, 0); 636 xhci_ring_free(sc, &sc->sc_cr); 637 cv_destroy(&sc->sc_command_cv); 638 cv_destroy(&sc->sc_cmdbusy_cv); 639 640 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 641 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 642 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 643 xhci_ring_free(sc, &sc->sc_er); 644 645 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 646 647 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 648 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 649 650 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 651 652 kmem_free(sc->sc_ctlrportbus, 653 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 654 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 655 656 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 657 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 658 } 659 660 mutex_destroy(&sc->sc_lock); 661 mutex_destroy(&sc->sc_intr_lock); 662 663 pool_cache_destroy(sc->sc_xferpool); 664 665 return rv; 666 } 667 668 int 669 xhci_activate(device_t self, enum devact act) 670 { 671 struct xhci_softc * const sc = device_private(self); 672 673 switch (act) { 674 case DVACT_DEACTIVATE: 675 sc->sc_dying = true; 676 return 0; 677 default: 678 return EOPNOTSUPP; 679 } 680 } 681 682 bool 683 xhci_suspend(device_t dv, const pmf_qual_t *qual) 684 { 685 return false; 686 } 687 688 bool 689 xhci_resume(device_t dv, const pmf_qual_t *qual) 690 { 691 return false; 692 } 693 694 bool 695 xhci_shutdown(device_t self, int flags) 696 { 697 return false; 698 } 699 700 static int 701 xhci_hc_reset(struct xhci_softc * const sc) 702 { 703 uint32_t usbcmd, usbsts; 704 int i; 705 706 /* Check controller not ready */ 707 for (i = 0; i < XHCI_WAIT_CNR; i++) { 708 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 709 if ((usbsts & XHCI_STS_CNR) == 0) 710 break; 711 usb_delay_ms(&sc->sc_bus, 1); 712 } 713 if (i >= XHCI_WAIT_CNR) { 714 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 715 return EIO; 716 } 717 718 /* Halt controller */ 719 usbcmd = 0; 720 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 721 usb_delay_ms(&sc->sc_bus, 1); 722 723 /* Reset controller */ 724 usbcmd = XHCI_CMD_HCRST; 725 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 726 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 727 /* 728 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 729 * prevent system hang (Errata). 730 */ 731 usb_delay_ms(&sc->sc_bus, 1); 732 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 733 if ((usbcmd & XHCI_CMD_HCRST) == 0) 734 break; 735 } 736 if (i >= XHCI_WAIT_HCRST) { 737 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 738 return EIO; 739 } 740 741 /* Check controller not ready */ 742 for (i = 0; i < XHCI_WAIT_CNR; i++) { 743 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 744 if ((usbsts & XHCI_STS_CNR) == 0) 745 break; 746 usb_delay_ms(&sc->sc_bus, 1); 747 } 748 if (i >= XHCI_WAIT_CNR) { 749 aprint_error_dev(sc->sc_dev, 750 "controller not ready timeout after reset\n"); 751 return EIO; 752 } 753 754 return 0; 755 } 756 757 758 /* 7.2 xHCI Support Protocol Capability */ 759 static void 760 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 761 { 762 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 763 764 /* XXX Cache this lot */ 765 766 const uint32_t w0 = xhci_read_4(sc, ecp); 767 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 768 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 769 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 770 771 aprint_debug_dev(sc->sc_dev, 772 " SP: 0x%08x 0x%08x 0x%08x 0x%08x\n", w0, w4, w8, wc); 773 774 if (w4 != XHCI_XECP_USBID) 775 return; 776 777 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 778 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 779 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 780 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 781 782 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 783 switch (mm) { 784 case 0x0200: 785 case 0x0300: 786 case 0x0301: 787 case 0x0310: 788 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 789 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 790 break; 791 default: 792 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 793 major, minor); 794 return; 795 } 796 797 const size_t bus = (major == 3) ? 0 : 1; 798 799 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 800 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 801 if (sc->sc_ctlrportmap[cp] != 0) { 802 aprint_error_dev(sc->sc_dev, "controller port %zu " 803 "already assigned", cp); 804 continue; 805 } 806 807 sc->sc_ctlrportbus[cp / NBBY] |= 808 bus == 0 ? 0 : __BIT(cp % NBBY); 809 810 const size_t rhp = sc->sc_rhportcount[bus]++; 811 812 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 813 "bus %zu rhp %zu is %d", bus, rhp, 814 sc->sc_rhportmap[bus][rhp]); 815 816 sc->sc_rhportmap[bus][rhp] = cp + 1; 817 sc->sc_ctlrportmap[cp] = rhp + 1; 818 } 819 } 820 821 /* Process extended capabilities */ 822 static void 823 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 824 { 825 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 826 827 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 828 while (ecp != 0) { 829 uint32_t ecr = xhci_read_4(sc, ecp); 830 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 831 switch (XHCI_XECP_ID(ecr)) { 832 case XHCI_ID_PROTOCOLS: { 833 xhci_id_protocols(sc, ecp); 834 break; 835 } 836 case XHCI_ID_USB_LEGACY: { 837 uint8_t bios_sem; 838 839 /* Take host controller ownership from BIOS */ 840 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 841 if (bios_sem) { 842 /* sets xHCI to be owned by OS */ 843 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 844 aprint_debug_dev(sc->sc_dev, 845 "waiting for BIOS to give up control\n"); 846 for (int i = 0; i < 5000; i++) { 847 bios_sem = xhci_read_1(sc, ecp + 848 XHCI_XECP_BIOS_SEM); 849 if (bios_sem == 0) 850 break; 851 DELAY(1000); 852 } 853 if (bios_sem) { 854 aprint_error_dev(sc->sc_dev, 855 "timed out waiting for BIOS\n"); 856 } 857 } 858 break; 859 } 860 default: 861 break; 862 } 863 ecr = xhci_read_4(sc, ecp); 864 if (XHCI_XECP_NEXT(ecr) == 0) { 865 ecp = 0; 866 } else { 867 ecp += XHCI_XECP_NEXT(ecr) * 4; 868 } 869 } 870 } 871 872 #define XHCI_HCCPREV1_BITS \ 873 "\177\020" /* New bitmask */ \ 874 "f\020\020XECP\0" \ 875 "f\014\4MAXPSA\0" \ 876 "b\013CFC\0" \ 877 "b\012SEC\0" \ 878 "b\011SBD\0" \ 879 "b\010FSE\0" \ 880 "b\7NSS\0" \ 881 "b\6LTC\0" \ 882 "b\5LHRC\0" \ 883 "b\4PIND\0" \ 884 "b\3PPC\0" \ 885 "b\2CZC\0" \ 886 "b\1BNC\0" \ 887 "b\0AC64\0" \ 888 "\0" 889 #define XHCI_HCCV1_x_BITS \ 890 "\177\020" /* New bitmask */ \ 891 "f\020\020XECP\0" \ 892 "f\014\4MAXPSA\0" \ 893 "b\013CFC\0" \ 894 "b\012SEC\0" \ 895 "b\011SPC\0" \ 896 "b\010PAE\0" \ 897 "b\7NSS\0" \ 898 "b\6LTC\0" \ 899 "b\5LHRC\0" \ 900 "b\4PIND\0" \ 901 "b\3PPC\0" \ 902 "b\2CSZ\0" \ 903 "b\1BNC\0" \ 904 "b\0AC64\0" \ 905 "\0" 906 907 #define XHCI_HCC2_BITS \ 908 "\177\020" /* New bitmask */ \ 909 "b\7ETC_TSC\0" \ 910 "b\6ETC\0" \ 911 "b\5CIC\0" \ 912 "b\4LEC\0" \ 913 "b\3CTC\0" \ 914 "b\2FSC\0" \ 915 "b\1CMC\0" \ 916 "b\0U3C\0" \ 917 "\0" 918 919 void 920 xhci_start(struct xhci_softc *sc) 921 { 922 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 923 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 924 /* Intel xhci needs interrupt rate moderated. */ 925 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 926 else 927 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 928 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 929 xhci_rt_read_4(sc, XHCI_IMOD(0))); 930 931 /* Go! */ 932 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 933 aprint_debug_dev(sc->sc_dev, "USBCMD 0x%08"PRIx32"\n", 934 xhci_op_read_4(sc, XHCI_USBCMD)); 935 } 936 937 int 938 xhci_init(struct xhci_softc *sc) 939 { 940 bus_size_t bsz; 941 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff, hcc2; 942 uint32_t pagesize, config; 943 int i = 0; 944 uint16_t hciversion; 945 uint8_t caplength; 946 947 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 948 949 /* Set up the bus struct for the usb 3 and usb 2 buses */ 950 sc->sc_bus.ub_methods = &xhci_bus_methods; 951 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 952 sc->sc_bus.ub_usedma = true; 953 sc->sc_bus.ub_hcpriv = sc; 954 955 sc->sc_bus2.ub_methods = &xhci_bus_methods; 956 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 957 sc->sc_bus2.ub_revision = USBREV_2_0; 958 sc->sc_bus2.ub_usedma = true; 959 sc->sc_bus2.ub_hcpriv = sc; 960 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 961 962 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 963 caplength = XHCI_CAP_CAPLENGTH(cap); 964 hciversion = XHCI_CAP_HCIVERSION(cap); 965 966 if (hciversion < XHCI_HCIVERSION_0_96 || 967 hciversion >= 0x0200) { 968 aprint_normal_dev(sc->sc_dev, 969 "xHCI version %x.%x not known to be supported\n", 970 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 971 } else { 972 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 973 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 974 } 975 976 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 977 &sc->sc_cbh) != 0) { 978 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 979 return ENOMEM; 980 } 981 982 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 983 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 984 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 985 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 986 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 987 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 988 aprint_debug_dev(sc->sc_dev, 989 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 990 991 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 992 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 993 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 994 995 char sbuf[128]; 996 if (hciversion < XHCI_HCIVERSION_1_0) 997 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 998 else 999 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 1000 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 1001 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 1002 if (hciversion >= XHCI_HCIVERSION_1_1) { 1003 hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 1004 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, hcc2); 1005 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 1006 } 1007 1008 /* default all ports to bus 0, i.e. usb 3 */ 1009 sc->sc_ctlrportbus = kmem_zalloc( 1010 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 1011 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1012 1013 /* controller port to bus roothub port map */ 1014 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 1015 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1016 } 1017 1018 /* 1019 * Process all Extended Capabilities 1020 */ 1021 xhci_ecp(sc, hcc); 1022 1023 bsz = XHCI_PORTSC(sc->sc_maxports); 1024 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1025 &sc->sc_obh) != 0) { 1026 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1027 return ENOMEM; 1028 } 1029 1030 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1031 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1032 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1033 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1034 return ENOMEM; 1035 } 1036 1037 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1038 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1039 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1040 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1041 return ENOMEM; 1042 } 1043 1044 int rv; 1045 rv = xhci_hc_reset(sc); 1046 if (rv != 0) { 1047 return rv; 1048 } 1049 1050 if (sc->sc_vendor_init) 1051 sc->sc_vendor_init(sc); 1052 1053 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1054 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1055 pagesize = ffs(pagesize); 1056 if (pagesize == 0) { 1057 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1058 return EIO; 1059 } 1060 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1061 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1062 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1063 (uint32_t)sc->sc_maxslots); 1064 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1065 1066 usbd_status err; 1067 1068 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1069 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1070 if (sc->sc_maxspbuf != 0) { 1071 err = usb_allocmem(&sc->sc_bus, 1072 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1073 USBMALLOC_COHERENT, &sc->sc_spbufarray_dma); 1074 if (err) { 1075 aprint_error_dev(sc->sc_dev, 1076 "spbufarray init fail, err %d\n", err); 1077 return ENOMEM; 1078 } 1079 1080 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1081 sc->sc_maxspbuf, KM_SLEEP); 1082 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1083 for (i = 0; i < sc->sc_maxspbuf; i++) { 1084 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1085 /* allocate contexts */ 1086 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1087 sc->sc_pgsz, USBMALLOC_COHERENT, dma); 1088 if (err) { 1089 aprint_error_dev(sc->sc_dev, 1090 "spbufarray_dma init fail, err %d\n", err); 1091 rv = ENOMEM; 1092 goto bad1; 1093 } 1094 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1095 usb_syncmem(dma, 0, sc->sc_pgsz, 1096 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1097 } 1098 1099 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1100 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1101 } 1102 1103 config = xhci_op_read_4(sc, XHCI_CONFIG); 1104 config &= ~0xFF; 1105 config |= sc->sc_maxslots & 0xFF; 1106 xhci_op_write_4(sc, XHCI_CONFIG, config); 1107 1108 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1109 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1110 if (err) { 1111 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1112 err); 1113 rv = ENOMEM; 1114 goto bad1; 1115 } 1116 1117 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1118 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1119 if (err) { 1120 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1121 err); 1122 rv = ENOMEM; 1123 goto bad2; 1124 } 1125 1126 usb_dma_t *dma; 1127 size_t size; 1128 size_t align; 1129 1130 dma = &sc->sc_eventst_dma; 1131 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1132 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1133 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1134 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1135 err = usb_allocmem(&sc->sc_bus, size, align, USBMALLOC_COHERENT, dma); 1136 if (err) { 1137 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1138 err); 1139 rv = ENOMEM; 1140 goto bad3; 1141 } 1142 1143 memset(KERNADDR(dma, 0), 0, size); 1144 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1145 aprint_debug_dev(sc->sc_dev, "eventst: 0x%016jx %p %zx\n", 1146 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1147 KERNADDR(&sc->sc_eventst_dma, 0), 1148 sc->sc_eventst_dma.udma_block->size); 1149 1150 dma = &sc->sc_dcbaa_dma; 1151 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1152 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1153 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1154 err = usb_allocmem(&sc->sc_bus, size, align, USBMALLOC_COHERENT, dma); 1155 if (err) { 1156 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1157 rv = ENOMEM; 1158 goto bad4; 1159 } 1160 aprint_debug_dev(sc->sc_dev, "dcbaa: 0x%016jx %p %zx\n", 1161 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1162 KERNADDR(&sc->sc_dcbaa_dma, 0), 1163 sc->sc_dcbaa_dma.udma_block->size); 1164 1165 memset(KERNADDR(dma, 0), 0, size); 1166 if (sc->sc_maxspbuf != 0) { 1167 /* 1168 * DCBA entry 0 hold the scratchbuf array pointer. 1169 */ 1170 *(uint64_t *)KERNADDR(dma, 0) = 1171 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1172 } 1173 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1174 1175 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1176 KM_SLEEP); 1177 if (sc->sc_slots == NULL) { 1178 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1179 rv = ENOMEM; 1180 goto bad; 1181 } 1182 1183 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1184 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1185 if (sc->sc_xferpool == NULL) { 1186 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1187 err); 1188 rv = ENOMEM; 1189 goto bad; 1190 } 1191 1192 cv_init(&sc->sc_command_cv, "xhcicmd"); 1193 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1194 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1195 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1196 1197 struct xhci_erste *erst; 1198 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1199 erst[0].erste_0 = htole64(xhci_ring_trbp(sc->sc_er, 0)); 1200 erst[0].erste_2 = htole32(sc->sc_er->xr_ntrb); 1201 erst[0].erste_3 = htole32(0); 1202 usb_syncmem(&sc->sc_eventst_dma, 0, 1203 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1204 1205 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1206 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1207 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(sc->sc_er, 0) | 1208 XHCI_ERDP_LO_BUSY); 1209 1210 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1211 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) | 1212 sc->sc_cr->xr_cs); 1213 1214 xhci_op_barrier(sc, 0, 4, BUS_SPACE_BARRIER_WRITE); 1215 1216 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1217 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1218 1219 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1220 xhci_start(sc); 1221 1222 return 0; 1223 1224 bad: 1225 if (sc->sc_xferpool) { 1226 pool_cache_destroy(sc->sc_xferpool); 1227 sc->sc_xferpool = NULL; 1228 } 1229 1230 if (sc->sc_slots) { 1231 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1232 sc->sc_maxslots); 1233 sc->sc_slots = NULL; 1234 } 1235 1236 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1237 bad4: 1238 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1239 bad3: 1240 xhci_ring_free(sc, &sc->sc_er); 1241 bad2: 1242 xhci_ring_free(sc, &sc->sc_cr); 1243 i = sc->sc_maxspbuf; 1244 bad1: 1245 for (int j = 0; j < i; j++) 1246 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1247 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1248 1249 return rv; 1250 } 1251 1252 static inline bool 1253 xhci_polling_p(struct xhci_softc * const sc) 1254 { 1255 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1256 } 1257 1258 int 1259 xhci_intr(void *v) 1260 { 1261 struct xhci_softc * const sc = v; 1262 int ret = 0; 1263 1264 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1265 1266 if (sc == NULL) 1267 return 0; 1268 1269 mutex_spin_enter(&sc->sc_intr_lock); 1270 1271 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1272 goto done; 1273 1274 /* If we get an interrupt while polling, then just ignore it. */ 1275 if (xhci_polling_p(sc)) { 1276 #ifdef DIAGNOSTIC 1277 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1278 #endif 1279 goto done; 1280 } 1281 1282 ret = xhci_intr1(sc); 1283 if (ret) { 1284 KASSERT(sc->sc_child || sc->sc_child2); 1285 1286 /* 1287 * One of child busses could be already detached. It doesn't 1288 * matter on which of the two the softintr is scheduled. 1289 */ 1290 if (sc->sc_child) 1291 usb_schedsoftintr(&sc->sc_bus); 1292 else 1293 usb_schedsoftintr(&sc->sc_bus2); 1294 } 1295 done: 1296 mutex_spin_exit(&sc->sc_intr_lock); 1297 return ret; 1298 } 1299 1300 int 1301 xhci_intr1(struct xhci_softc * const sc) 1302 { 1303 uint32_t usbsts; 1304 uint32_t iman; 1305 1306 XHCIHIST_FUNC(); 1307 1308 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1309 XHCIHIST_CALLARGS("USBSTS 0x%08jx", usbsts, 0, 0, 0); 1310 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1311 XHCI_STS_HCE)) == 0) { 1312 DPRINTFN(16, "ignored intr not for %jd", 1313 device_unit(sc->sc_dev), 0, 0, 0); 1314 return 0; 1315 } 1316 1317 /* 1318 * Clear EINT and other transient flags, to not misenterpret 1319 * next shared interrupt. Also, to avoid race, EINT must be cleared 1320 * before XHCI_IMAN_INTR_PEND is cleared. 1321 */ 1322 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1323 1324 #ifdef XHCI_DEBUG 1325 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1326 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1327 #endif 1328 1329 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1330 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1331 iman |= XHCI_IMAN_INTR_PEND; 1332 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1333 1334 #ifdef XHCI_DEBUG 1335 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1336 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1337 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1338 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1339 #endif 1340 1341 return 1; 1342 } 1343 1344 /* 1345 * 3 port speed types used in USB stack 1346 * 1347 * usbdi speed 1348 * definition: USB_SPEED_* in usb.h 1349 * They are used in struct usbd_device in USB stack. 1350 * ioctl interface uses these values too. 1351 * port_status speed 1352 * definition: UPS_*_SPEED in usb.h 1353 * They are used in usb_port_status_t and valid only for USB 2.0. 1354 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1355 * of usb_port_status_ext_t indicates port speed. 1356 * Note that some 3.0 values overlap with 2.0 values. 1357 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1358 * means UPS_LOW_SPEED in HS.) 1359 * port status returned from hub also uses these values. 1360 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1361 * or more. 1362 * xspeed: 1363 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1364 * They are used in only slot context and PORTSC reg of xhci. 1365 * The difference between usbdi speed and xspeed is 1366 * that FS and LS values are swapped. 1367 */ 1368 1369 /* convert usbdi speed to xspeed */ 1370 static int 1371 xhci_speed2xspeed(int speed) 1372 { 1373 switch (speed) { 1374 case USB_SPEED_LOW: return 2; 1375 case USB_SPEED_FULL: return 1; 1376 default: return speed; 1377 } 1378 } 1379 1380 #if 0 1381 /* convert xspeed to usbdi speed */ 1382 static int 1383 xhci_xspeed2speed(int xspeed) 1384 { 1385 switch (xspeed) { 1386 case 1: return USB_SPEED_FULL; 1387 case 2: return USB_SPEED_LOW; 1388 default: return xspeed; 1389 } 1390 } 1391 #endif 1392 1393 /* convert xspeed to port status speed */ 1394 static int 1395 xhci_xspeed2psspeed(int xspeed) 1396 { 1397 switch (xspeed) { 1398 case 0: return 0; 1399 case 1: return UPS_FULL_SPEED; 1400 case 2: return UPS_LOW_SPEED; 1401 case 3: return UPS_HIGH_SPEED; 1402 default: return UPS_OTHER_SPEED; 1403 } 1404 } 1405 1406 /* 1407 * Construct input contexts and issue TRB to open pipe. 1408 */ 1409 static usbd_status 1410 xhci_configure_endpoint(struct usbd_pipe *pipe) 1411 { 1412 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1413 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1414 #ifdef USB_DEBUG 1415 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1416 #endif 1417 struct xhci_soft_trb trb; 1418 usbd_status err; 1419 1420 XHCIHIST_FUNC(); 1421 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1422 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1423 pipe->up_endpoint->ue_edesc->bmAttributes); 1424 1425 /* XXX ensure input context is available? */ 1426 1427 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1428 1429 /* set up context */ 1430 xhci_setup_ctx(pipe); 1431 1432 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1433 sc->sc_ctxsz * 1); 1434 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1435 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1436 1437 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1438 trb.trb_2 = 0; 1439 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1440 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1441 1442 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1443 1444 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1445 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1446 sc->sc_ctxsz * 1); 1447 1448 return err; 1449 } 1450 1451 #if 0 1452 static usbd_status 1453 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1454 { 1455 #ifdef USB_DEBUG 1456 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1457 #endif 1458 1459 XHCIHIST_FUNC(); 1460 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 1461 1462 return USBD_NORMAL_COMPLETION; 1463 } 1464 #endif 1465 1466 /* 4.6.8, 6.4.3.7 */ 1467 static usbd_status 1468 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1469 { 1470 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1471 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1472 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1473 struct xhci_soft_trb trb; 1474 usbd_status err; 1475 1476 XHCIHIST_FUNC(); 1477 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1478 1479 KASSERT(mutex_owned(&sc->sc_lock)); 1480 1481 trb.trb_0 = 0; 1482 trb.trb_2 = 0; 1483 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1484 XHCI_TRB_3_EP_SET(dci) | 1485 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1486 1487 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1488 1489 return err; 1490 } 1491 1492 static usbd_status 1493 xhci_reset_endpoint(struct usbd_pipe *pipe) 1494 { 1495 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1496 1497 mutex_enter(&sc->sc_lock); 1498 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1499 mutex_exit(&sc->sc_lock); 1500 1501 return ret; 1502 } 1503 1504 /* 1505 * 4.6.9, 6.4.3.8 1506 * Stop execution of TDs on xfer ring. 1507 * Should be called with sc_lock held. 1508 */ 1509 static usbd_status 1510 xhci_stop_endpoint(struct usbd_pipe *pipe) 1511 { 1512 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1513 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1514 struct xhci_soft_trb trb; 1515 usbd_status err; 1516 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1517 1518 XHCIHIST_FUNC(); 1519 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1520 1521 KASSERT(mutex_owned(&sc->sc_lock)); 1522 1523 trb.trb_0 = 0; 1524 trb.trb_2 = 0; 1525 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1526 XHCI_TRB_3_EP_SET(dci) | 1527 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1528 1529 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1530 1531 return err; 1532 } 1533 1534 /* 1535 * Set TR Dequeue Pointer. 1536 * xHCI 1.1 4.6.10 6.4.3.9 1537 * Purge all of the TRBs on ring and reinitialize ring. 1538 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1539 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1540 * error will be generated. 1541 */ 1542 static usbd_status 1543 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1544 { 1545 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1546 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1547 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1548 struct xhci_ring * const xr = xs->xs_xr[dci]; 1549 struct xhci_soft_trb trb; 1550 usbd_status err; 1551 1552 XHCIHIST_FUNC(); 1553 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1554 1555 KASSERT(mutex_owned(&sc->sc_lock)); 1556 KASSERT(xr != NULL); 1557 1558 xhci_host_dequeue(xr); 1559 1560 /* set DCS */ 1561 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1562 trb.trb_2 = 0; 1563 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1564 XHCI_TRB_3_EP_SET(dci) | 1565 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1566 1567 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1568 1569 return err; 1570 } 1571 1572 static usbd_status 1573 xhci_set_dequeue(struct usbd_pipe *pipe) 1574 { 1575 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1576 1577 mutex_enter(&sc->sc_lock); 1578 usbd_status ret = xhci_set_dequeue_locked(pipe); 1579 mutex_exit(&sc->sc_lock); 1580 1581 return ret; 1582 } 1583 1584 /* 1585 * Open new pipe: called from usbd_setup_pipe_flags. 1586 * Fills methods of pipe. 1587 * If pipe is not for ep0, calls configure_endpoint. 1588 */ 1589 static usbd_status 1590 xhci_open(struct usbd_pipe *pipe) 1591 { 1592 struct usbd_device * const dev = pipe->up_dev; 1593 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1594 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1595 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1596 const u_int dci = xhci_ep_get_dci(ed); 1597 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1598 usbd_status err; 1599 1600 XHCIHIST_FUNC(); 1601 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1602 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1603 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1604 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1605 ed->bmAttributes); 1606 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1607 ed->bInterval, 0, 0); 1608 1609 if (sc->sc_dying) 1610 return USBD_IOERROR; 1611 1612 /* Root Hub */ 1613 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1614 switch (ed->bEndpointAddress) { 1615 case USB_CONTROL_ENDPOINT: 1616 pipe->up_methods = &roothub_ctrl_methods; 1617 break; 1618 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1619 pipe->up_methods = &xhci_root_intr_methods; 1620 break; 1621 default: 1622 pipe->up_methods = NULL; 1623 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1624 ed->bEndpointAddress, 0, 0, 0); 1625 return USBD_INVAL; 1626 } 1627 return USBD_NORMAL_COMPLETION; 1628 } 1629 1630 switch (xfertype) { 1631 case UE_CONTROL: 1632 pipe->up_methods = &xhci_device_ctrl_methods; 1633 break; 1634 case UE_ISOCHRONOUS: 1635 pipe->up_methods = &xhci_device_isoc_methods; 1636 return USBD_INVAL; 1637 break; 1638 case UE_BULK: 1639 pipe->up_methods = &xhci_device_bulk_methods; 1640 break; 1641 case UE_INTERRUPT: 1642 pipe->up_methods = &xhci_device_intr_methods; 1643 break; 1644 default: 1645 return USBD_IOERROR; 1646 break; 1647 } 1648 1649 KASSERT(xs != NULL); 1650 KASSERT(xs->xs_xr[dci] == NULL); 1651 1652 /* allocate transfer ring */ 1653 err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS, 1654 XHCI_TRB_ALIGN); 1655 if (err) { 1656 DPRINTFN(1, "ring alloc failed %jd", err, 0, 0, 0); 1657 return err; 1658 } 1659 1660 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1661 return xhci_configure_endpoint(pipe); 1662 1663 return USBD_NORMAL_COMPLETION; 1664 } 1665 1666 /* 1667 * Closes pipe, called from usbd_kill_pipe via close methods. 1668 * If the endpoint to be closed is ep0, disable_slot. 1669 * Should be called with sc_lock held. 1670 */ 1671 static void 1672 xhci_close_pipe(struct usbd_pipe *pipe) 1673 { 1674 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1675 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1676 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1677 const u_int dci = xhci_ep_get_dci(ed); 1678 struct xhci_soft_trb trb; 1679 uint32_t *cp; 1680 1681 XHCIHIST_FUNC(); 1682 1683 if (sc->sc_dying) 1684 return; 1685 1686 /* xs is uninitialized before xhci_init_slot */ 1687 if (xs == NULL || xs->xs_idx == 0) 1688 return; 1689 1690 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 1691 (uintptr_t)pipe, xs->xs_idx, dci, 0); 1692 1693 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1694 KASSERT(mutex_owned(&sc->sc_lock)); 1695 1696 if (pipe->up_dev->ud_depth == 0) 1697 return; 1698 1699 if (dci == XHCI_DCI_EP_CONTROL) { 1700 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1701 /* This frees all rings */ 1702 xhci_disable_slot(sc, xs->xs_idx); 1703 return; 1704 } 1705 1706 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1707 (void)xhci_stop_endpoint(pipe); 1708 1709 /* 1710 * set appropriate bit to be dropped. 1711 * don't set DC bit to 1, otherwise all endpoints 1712 * would be deconfigured. 1713 */ 1714 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1715 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1716 cp[1] = htole32(0); 1717 1718 /* XXX should be most significant one, not dci? */ 1719 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1720 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1721 1722 /* configure ep context performs an implicit dequeue */ 1723 xhci_host_dequeue(xs->xs_xr[dci]); 1724 1725 /* sync input contexts before they are read from memory */ 1726 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1727 1728 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1729 trb.trb_2 = 0; 1730 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1731 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1732 1733 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1734 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1735 1736 xhci_ring_free(sc, &xs->xs_xr[dci]); 1737 } 1738 1739 /* 1740 * Abort transfer. 1741 * Should be called with sc_lock held. 1742 */ 1743 static void 1744 xhci_abortx(struct usbd_xfer *xfer) 1745 { 1746 XHCIHIST_FUNC(); 1747 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1748 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1749 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1750 1751 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx", 1752 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0); 1753 1754 KASSERT(mutex_owned(&sc->sc_lock)); 1755 ASSERT_SLEEPABLE(); 1756 1757 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 1758 xfer->ux_status == USBD_TIMEOUT), 1759 "bad abort status: %d", xfer->ux_status); 1760 1761 /* 1762 * If we're dying, skip the hardware action and just notify the 1763 * software that we're done. 1764 */ 1765 if (sc->sc_dying) { 1766 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1767 xfer->ux_status, 0, 0); 1768 goto dying; 1769 } 1770 1771 /* 1772 * HC Step 1: Stop execution of TD on the ring. 1773 */ 1774 switch (xhci_get_epstate(sc, xs, dci)) { 1775 case XHCI_EPSTATE_HALTED: 1776 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1777 break; 1778 case XHCI_EPSTATE_STOPPED: 1779 break; 1780 default: 1781 (void)xhci_stop_endpoint(xfer->ux_pipe); 1782 break; 1783 } 1784 #ifdef DIAGNOSTIC 1785 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1786 if (epst != XHCI_EPSTATE_STOPPED) 1787 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1788 #endif 1789 1790 /* 1791 * HC Step 2: Remove any vestiges of the xfer from the ring. 1792 */ 1793 xhci_set_dequeue_locked(xfer->ux_pipe); 1794 1795 /* 1796 * Final Step: Notify completion to waiting xfers. 1797 */ 1798 dying: 1799 usb_transfer_complete(xfer); 1800 DPRINTFN(14, "end", 0, 0, 0, 0); 1801 1802 KASSERT(mutex_owned(&sc->sc_lock)); 1803 } 1804 1805 static void 1806 xhci_host_dequeue(struct xhci_ring * const xr) 1807 { 1808 /* When dequeueing the controller, update our struct copy too */ 1809 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1810 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1811 BUS_DMASYNC_PREWRITE); 1812 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1813 1814 xr->xr_ep = 0; 1815 xr->xr_cs = 1; 1816 } 1817 1818 /* 1819 * Recover STALLed endpoint. 1820 * xHCI 1.1 sect 4.10.2.1 1821 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1822 * all transfers on transfer ring. 1823 * These are done in thread context asynchronously. 1824 */ 1825 static void 1826 xhci_clear_endpoint_stall_async_task(void *cookie) 1827 { 1828 struct usbd_xfer * const xfer = cookie; 1829 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1830 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1831 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1832 struct xhci_ring * const tr = xs->xs_xr[dci]; 1833 1834 XHCIHIST_FUNC(); 1835 XHCIHIST_CALLARGS("xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1836 dci, 0); 1837 1838 /* 1839 * XXXMRG: Stall task can run after slot is disabled when yanked. 1840 * This hack notices that the xs has been memset() in 1841 * xhci_disable_slot() and returns. Both xhci_reset_endpoint() 1842 * and xhci_set_dequeue() rely upon a valid ring setup for correct 1843 * operation, and the latter will fault, as would 1844 * usb_transfer_complete() if it got that far. 1845 */ 1846 if (xs->xs_idx == 0) { 1847 DPRINTFN(4, "ends xs_idx is 0", 0, 0, 0, 0); 1848 return; 1849 } 1850 1851 KASSERT(tr != NULL); 1852 1853 xhci_reset_endpoint(xfer->ux_pipe); 1854 xhci_set_dequeue(xfer->ux_pipe); 1855 1856 mutex_enter(&sc->sc_lock); 1857 tr->is_halted = false; 1858 usb_transfer_complete(xfer); 1859 mutex_exit(&sc->sc_lock); 1860 DPRINTFN(4, "ends", 0, 0, 0, 0); 1861 } 1862 1863 static usbd_status 1864 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1865 { 1866 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1867 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1868 1869 XHCIHIST_FUNC(); 1870 XHCIHIST_CALLARGS("xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1871 1872 if (sc->sc_dying) { 1873 return USBD_IOERROR; 1874 } 1875 1876 usb_init_task(&xp->xp_async_task, 1877 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1878 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1879 DPRINTFN(4, "ends", 0, 0, 0, 0); 1880 1881 return USBD_NORMAL_COMPLETION; 1882 } 1883 1884 /* Process roothub port status/change events and notify to uhub_intr. */ 1885 static void 1886 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1887 { 1888 XHCIHIST_FUNC(); 1889 XHCIHIST_CALLARGS("xhci%jd: port %ju status change", 1890 device_unit(sc->sc_dev), ctlrport, 0, 0); 1891 1892 if (ctlrport > sc->sc_maxports) 1893 return; 1894 1895 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1896 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1897 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1898 1899 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1900 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1901 1902 if (xfer == NULL) 1903 return; 1904 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1905 1906 uint8_t *p = xfer->ux_buf; 1907 memset(p, 0, xfer->ux_length); 1908 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1909 xfer->ux_actlen = xfer->ux_length; 1910 xfer->ux_status = USBD_NORMAL_COMPLETION; 1911 usb_transfer_complete(xfer); 1912 } 1913 1914 /* Process Transfer Events */ 1915 static void 1916 xhci_event_transfer(struct xhci_softc * const sc, 1917 const struct xhci_trb * const trb) 1918 { 1919 uint64_t trb_0; 1920 uint32_t trb_2, trb_3; 1921 uint8_t trbcode; 1922 u_int slot, dci; 1923 struct xhci_slot *xs; 1924 struct xhci_ring *xr; 1925 struct xhci_xfer *xx; 1926 struct usbd_xfer *xfer; 1927 usbd_status err; 1928 1929 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1930 1931 trb_0 = le64toh(trb->trb_0); 1932 trb_2 = le32toh(trb->trb_2); 1933 trb_3 = le32toh(trb->trb_3); 1934 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1935 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1936 dci = XHCI_TRB_3_EP_GET(trb_3); 1937 xs = &sc->sc_slots[slot]; 1938 xr = xs->xs_xr[dci]; 1939 1940 /* sanity check */ 1941 KASSERT(xr != NULL); 1942 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1943 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1944 1945 int idx = 0; 1946 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1947 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1948 DPRINTFN(0, "invalid trb_0 %#jx", trb_0, 0, 0, 0); 1949 return; 1950 } 1951 xx = xr->xr_cookies[idx]; 1952 1953 /* clear cookie of consumed TRB */ 1954 xr->xr_cookies[idx] = NULL; 1955 1956 /* 1957 * xx is NULL if pipe is opened but xfer is not started. 1958 * It happens when stopping idle pipe. 1959 */ 1960 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1961 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1962 idx, (uintptr_t)xx, trbcode, dci); 1963 DPRINTFN(1, " orig TRB %#jx type %ju", trb_0, 1964 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1965 0, 0); 1966 return; 1967 } 1968 } else { 1969 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1970 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1971 } 1972 /* XXX this may not happen */ 1973 if (xx == NULL) { 1974 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1975 return; 1976 } 1977 xfer = &xx->xx_xfer; 1978 /* XXX this may happen when detaching */ 1979 if (xfer == NULL) { 1980 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1981 (uintptr_t)xx, trb_0, 0, 0); 1982 return; 1983 } 1984 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1985 /* XXX I dunno why this happens */ 1986 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1987 1988 if (!xfer->ux_pipe->up_repeat && 1989 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1990 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1991 0, 0, 0); 1992 return; 1993 } 1994 1995 /* 1996 * Try to claim this xfer for completion. If it has already 1997 * completed or aborted, drop it on the floor. 1998 */ 1999 if (!usbd_xfer_trycomplete(xfer)) 2000 return; 2001 2002 /* 4.11.5.2 Event Data TRB */ 2003 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2004 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 2005 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 2006 if ((trb_0 & 0x3) == 0x3) { 2007 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 2008 } 2009 } 2010 2011 switch (trbcode) { 2012 case XHCI_TRB_ERROR_SHORT_PKT: 2013 case XHCI_TRB_ERROR_SUCCESS: 2014 /* 2015 * A ctrl transfer can generate two events if it has a Data 2016 * stage. A short data stage can be OK and should not 2017 * complete the transfer as the status stage needs to be 2018 * performed. 2019 * 2020 * Note: Data and Status stage events point at same xfer. 2021 * ux_actlen and ux_dmabuf will be passed to 2022 * usb_transfer_complete after the Status stage event. 2023 * 2024 * It can be distingished which stage generates the event: 2025 * + by checking least 3 bits of trb_0 if ED==1. 2026 * (see xhci_device_ctrl_start). 2027 * + by checking the type of original TRB if ED==0. 2028 * 2029 * In addition, intr, bulk, and isoc transfer currently 2030 * consists of single TD, so the "skip" is not needed. 2031 * ctrl xfer uses EVENT_DATA, and others do not. 2032 * Thus driver can switch the flow by checking ED bit. 2033 */ 2034 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2035 if (xfer->ux_actlen == 0) 2036 xfer->ux_actlen = xfer->ux_length - 2037 XHCI_TRB_2_REM_GET(trb_2); 2038 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 2039 == XHCI_TRB_TYPE_DATA_STAGE) { 2040 return; 2041 } 2042 } else if ((trb_0 & 0x3) == 0x3) { 2043 return; 2044 } 2045 err = USBD_NORMAL_COMPLETION; 2046 break; 2047 case XHCI_TRB_ERROR_STOPPED: 2048 case XHCI_TRB_ERROR_LENGTH: 2049 case XHCI_TRB_ERROR_STOPPED_SHORT: 2050 err = USBD_IOERROR; 2051 break; 2052 case XHCI_TRB_ERROR_STALL: 2053 case XHCI_TRB_ERROR_BABBLE: 2054 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2055 xr->is_halted = true; 2056 /* 2057 * Stalled endpoints can be recoverd by issuing 2058 * command TRB TYPE_RESET_EP on xHCI instead of 2059 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2060 * on the endpoint. However, this function may be 2061 * called from softint context (e.g. from umass), 2062 * in that case driver gets KASSERT in cv_timedwait 2063 * in xhci_do_command. 2064 * To avoid this, this runs reset_endpoint and 2065 * usb_transfer_complete in usb task thread 2066 * asynchronously (and then umass issues clear 2067 * UF_ENDPOINT_HALT). 2068 */ 2069 2070 /* Override the status. */ 2071 xfer->ux_status = USBD_STALLED; 2072 2073 xhci_clear_endpoint_stall_async(xfer); 2074 return; 2075 default: 2076 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2077 err = USBD_IOERROR; 2078 break; 2079 } 2080 2081 /* Set the status. */ 2082 xfer->ux_status = err; 2083 2084 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2085 (trb_0 & 0x3) == 0x0) { 2086 usb_transfer_complete(xfer); 2087 } 2088 } 2089 2090 /* Process Command complete events */ 2091 static void 2092 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2093 { 2094 uint64_t trb_0; 2095 uint32_t trb_2, trb_3; 2096 2097 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2098 2099 KASSERT(mutex_owned(&sc->sc_lock)); 2100 2101 trb_0 = le64toh(trb->trb_0); 2102 trb_2 = le32toh(trb->trb_2); 2103 trb_3 = le32toh(trb->trb_3); 2104 2105 if (trb_0 == sc->sc_command_addr) { 2106 sc->sc_resultpending = false; 2107 2108 sc->sc_result_trb.trb_0 = trb_0; 2109 sc->sc_result_trb.trb_2 = trb_2; 2110 sc->sc_result_trb.trb_3 = trb_3; 2111 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2112 XHCI_TRB_ERROR_SUCCESS) { 2113 DPRINTFN(1, "command completion " 2114 "failure: 0x%016jx 0x%08jx 0x%08jx", 2115 trb_0, trb_2, trb_3, 0); 2116 } 2117 cv_signal(&sc->sc_command_cv); 2118 } else { 2119 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2120 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2121 } 2122 } 2123 2124 /* 2125 * Process events. 2126 * called from xhci_softintr 2127 */ 2128 static void 2129 xhci_handle_event(struct xhci_softc * const sc, 2130 const struct xhci_trb * const trb) 2131 { 2132 uint64_t trb_0; 2133 uint32_t trb_2, trb_3; 2134 2135 XHCIHIST_FUNC(); 2136 2137 trb_0 = le64toh(trb->trb_0); 2138 trb_2 = le32toh(trb->trb_2); 2139 trb_3 = le32toh(trb->trb_3); 2140 2141 XHCIHIST_CALLARGS("event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2142 (uintptr_t)trb, trb_0, trb_2, trb_3); 2143 2144 /* 2145 * 4.11.3.1, 6.4.2.1 2146 * TRB Pointer is invalid for these completion codes. 2147 */ 2148 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2149 case XHCI_TRB_ERROR_RING_UNDERRUN: 2150 case XHCI_TRB_ERROR_RING_OVERRUN: 2151 case XHCI_TRB_ERROR_VF_RING_FULL: 2152 return; 2153 default: 2154 if (trb_0 == 0) { 2155 return; 2156 } 2157 break; 2158 } 2159 2160 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2161 case XHCI_TRB_EVENT_TRANSFER: 2162 xhci_event_transfer(sc, trb); 2163 break; 2164 case XHCI_TRB_EVENT_CMD_COMPLETE: 2165 xhci_event_cmd(sc, trb); 2166 break; 2167 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2168 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2169 break; 2170 default: 2171 break; 2172 } 2173 } 2174 2175 static void 2176 xhci_softintr(void *v) 2177 { 2178 struct usbd_bus * const bus = v; 2179 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2180 struct xhci_ring * const er = sc->sc_er; 2181 struct xhci_trb *trb; 2182 int i, j, k; 2183 2184 XHCIHIST_FUNC(); 2185 2186 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2187 2188 i = er->xr_ep; 2189 j = er->xr_cs; 2190 2191 XHCIHIST_CALLARGS("er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2192 2193 while (1) { 2194 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2195 BUS_DMASYNC_POSTREAD); 2196 trb = &er->xr_trb[i]; 2197 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2198 2199 if (j != k) 2200 break; 2201 2202 xhci_handle_event(sc, trb); 2203 2204 i++; 2205 if (i == er->xr_ntrb) { 2206 i = 0; 2207 j ^= 1; 2208 } 2209 } 2210 2211 er->xr_ep = i; 2212 er->xr_cs = j; 2213 2214 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2215 XHCI_ERDP_LO_BUSY); 2216 2217 DPRINTFN(16, "ends", 0, 0, 0, 0); 2218 2219 return; 2220 } 2221 2222 static void 2223 xhci_poll(struct usbd_bus *bus) 2224 { 2225 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2226 2227 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2228 2229 mutex_enter(&sc->sc_intr_lock); 2230 int ret = xhci_intr1(sc); 2231 if (ret) { 2232 xhci_softintr(bus); 2233 } 2234 mutex_exit(&sc->sc_intr_lock); 2235 2236 return; 2237 } 2238 2239 static struct usbd_xfer * 2240 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2241 { 2242 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2243 struct xhci_xfer *xx; 2244 u_int ntrbs; 2245 2246 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2247 2248 ntrbs = XHCI_XFER_NTRB; 2249 const size_t trbsz = sizeof(*xx->xx_trb) * ntrbs; 2250 2251 xx = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2252 if (xx != NULL) { 2253 memset(xx, 0, sizeof(*xx)); 2254 if (ntrbs > 0) { 2255 xx->xx_trb = kmem_alloc(trbsz, KM_SLEEP); 2256 xx->xx_ntrb = ntrbs; 2257 } 2258 #ifdef DIAGNOSTIC 2259 xx->xx_xfer.ux_state = XFER_BUSY; 2260 #endif 2261 } 2262 2263 return &xx->xx_xfer; 2264 } 2265 2266 static void 2267 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2268 { 2269 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2270 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 2271 2272 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2273 2274 #ifdef DIAGNOSTIC 2275 if (xfer->ux_state != XFER_BUSY && 2276 xfer->ux_status != USBD_NOT_STARTED) { 2277 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2278 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2279 } 2280 xfer->ux_state = XFER_FREE; 2281 #endif 2282 if (xx->xx_ntrb > 0) { 2283 kmem_free(xx->xx_trb, xx->xx_ntrb * sizeof(*xx->xx_trb)); 2284 xx->xx_trb = NULL; 2285 xx->xx_ntrb = 0; 2286 } 2287 pool_cache_put(sc->sc_xferpool, xx); 2288 } 2289 2290 static bool 2291 xhci_dying(struct usbd_bus *bus) 2292 { 2293 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2294 2295 return sc->sc_dying; 2296 } 2297 2298 static void 2299 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2300 { 2301 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2302 2303 *lock = &sc->sc_lock; 2304 } 2305 2306 extern uint32_t usb_cookie_no; 2307 2308 /* 2309 * xHCI 4.3 2310 * Called when uhub_explore finds a new device (via usbd_new_device). 2311 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2312 * This function does: 2313 * Allocate and construct dev structure of default endpoint (ep0). 2314 * Allocate and open pipe of ep0. 2315 * Enable slot and initialize slot context. 2316 * Set Address. 2317 * Read initial device descriptor. 2318 * Determine initial MaxPacketSize (mps) by speed. 2319 * Read full device descriptor. 2320 * Register this device. 2321 * Finally state of device transitions ADDRESSED. 2322 */ 2323 static usbd_status 2324 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2325 int speed, int port, struct usbd_port *up) 2326 { 2327 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2328 struct usbd_device *dev; 2329 usbd_status err; 2330 usb_device_descriptor_t *dd; 2331 struct xhci_slot *xs; 2332 uint32_t *cp; 2333 2334 XHCIHIST_FUNC(); 2335 XHCIHIST_CALLARGS("port %ju depth %ju speed %ju up %#jx", 2336 port, depth, speed, (uintptr_t)up); 2337 2338 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2339 dev->ud_bus = bus; 2340 dev->ud_quirks = &usbd_no_quirk; 2341 dev->ud_addr = 0; 2342 dev->ud_ddesc.bMaxPacketSize = 0; 2343 dev->ud_depth = depth; 2344 dev->ud_powersrc = up; 2345 dev->ud_myhub = up->up_parent; 2346 dev->ud_speed = speed; 2347 dev->ud_langid = USBD_NOLANG; 2348 dev->ud_cookie.cookie = ++usb_cookie_no; 2349 2350 /* Set up default endpoint handle. */ 2351 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2352 /* doesn't matter, just don't let it uninitialized */ 2353 dev->ud_ep0.ue_toggle = 0; 2354 2355 /* Set up default endpoint descriptor. */ 2356 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2357 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2358 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2359 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2360 dev->ud_ep0desc.bInterval = 0; 2361 2362 /* 4.3, 4.8.2.1 */ 2363 switch (speed) { 2364 case USB_SPEED_SUPER: 2365 case USB_SPEED_SUPER_PLUS: 2366 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2367 break; 2368 case USB_SPEED_FULL: 2369 /* XXX using 64 as initial mps of ep0 in FS */ 2370 case USB_SPEED_HIGH: 2371 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2372 break; 2373 case USB_SPEED_LOW: 2374 default: 2375 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2376 break; 2377 } 2378 2379 up->up_dev = dev; 2380 2381 dd = &dev->ud_ddesc; 2382 2383 if (depth == 0 && port == 0) { 2384 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2385 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2386 2387 /* Establish the default pipe. */ 2388 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2389 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2390 if (err) { 2391 DPRINTFN(1, "setup default pipe failed %jd", err,0,0,0); 2392 goto bad; 2393 } 2394 err = usbd_get_initial_ddesc(dev, dd); 2395 if (err) { 2396 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2397 goto bad; 2398 } 2399 } else { 2400 uint8_t slot = 0; 2401 2402 /* 4.3.2 */ 2403 err = xhci_enable_slot(sc, &slot); 2404 if (err) { 2405 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2406 goto bad; 2407 } 2408 2409 xs = &sc->sc_slots[slot]; 2410 dev->ud_hcpriv = xs; 2411 2412 /* 4.3.3 initialize slot structure */ 2413 err = xhci_init_slot(dev, slot); 2414 if (err) { 2415 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2416 dev->ud_hcpriv = NULL; 2417 /* 2418 * We have to disable_slot here because 2419 * xs->xs_idx == 0 when xhci_init_slot fails, 2420 * in that case usbd_remove_dev won't work. 2421 */ 2422 mutex_enter(&sc->sc_lock); 2423 xhci_disable_slot(sc, slot); 2424 mutex_exit(&sc->sc_lock); 2425 goto bad; 2426 } 2427 2428 /* 2429 * We have to establish the default pipe _after_ slot 2430 * structure has been prepared. 2431 */ 2432 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2433 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2434 if (err) { 2435 DPRINTFN(1, "setup default pipe failed %jd", err, 0, 0, 2436 0); 2437 goto bad; 2438 } 2439 2440 /* 4.3.4 Address Assignment */ 2441 err = xhci_set_address(dev, slot, false); 2442 if (err) { 2443 DPRINTFN(1, "failed! to set address: %ju", err, 0, 0, 0); 2444 goto bad; 2445 } 2446 2447 /* Allow device time to set new address */ 2448 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2449 2450 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2451 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2452 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2453 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2454 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2455 /* 2456 * XXX ensure we know when the hardware does something 2457 * we can't yet cope with 2458 */ 2459 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2460 dev->ud_addr = addr; 2461 2462 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2463 "addr %d already allocated", dev->ud_addr); 2464 /* 2465 * The root hub is given its own slot 2466 */ 2467 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2468 2469 err = usbd_get_initial_ddesc(dev, dd); 2470 if (err) { 2471 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2472 goto bad; 2473 } 2474 2475 /* 4.8.2.1 */ 2476 if (USB_IS_SS(speed)) { 2477 if (dd->bMaxPacketSize != 9) { 2478 printf("%s: invalid mps 2^%u for SS ep0," 2479 " using 512\n", 2480 device_xname(sc->sc_dev), 2481 dd->bMaxPacketSize); 2482 dd->bMaxPacketSize = 9; 2483 } 2484 USETW(dev->ud_ep0desc.wMaxPacketSize, 2485 (1 << dd->bMaxPacketSize)); 2486 } else 2487 USETW(dev->ud_ep0desc.wMaxPacketSize, 2488 dd->bMaxPacketSize); 2489 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2490 err = xhci_update_ep0_mps(sc, xs, 2491 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2492 if (err) { 2493 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2494 goto bad; 2495 } 2496 } 2497 2498 err = usbd_reload_device_desc(dev); 2499 if (err) { 2500 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2501 goto bad; 2502 } 2503 2504 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2505 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2506 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2507 dd->bDeviceClass, dd->bDeviceSubClass, 2508 dd->bDeviceProtocol, 0); 2509 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2510 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2511 dev->ud_speed); 2512 2513 usbd_get_device_strings(dev); 2514 2515 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2516 2517 if (depth == 0 && port == 0) { 2518 usbd_attach_roothub(parent, dev); 2519 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2520 return USBD_NORMAL_COMPLETION; 2521 } 2522 2523 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2524 bad: 2525 if (err != USBD_NORMAL_COMPLETION) { 2526 usbd_remove_device(dev, up); 2527 } 2528 2529 return err; 2530 } 2531 2532 static usbd_status 2533 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring **xrp, 2534 size_t ntrb, size_t align) 2535 { 2536 usbd_status err; 2537 size_t size = ntrb * XHCI_TRB_SIZE; 2538 struct xhci_ring *xr; 2539 2540 XHCIHIST_FUNC(); 2541 XHCIHIST_CALLARGS("xr %#jx ntrb %#jx align %#jx", 2542 (uintptr_t)*xrp, ntrb, align, 0); 2543 2544 xr = kmem_zalloc(sizeof(struct xhci_ring), KM_SLEEP); 2545 DPRINTFN(1, "ring %#jx", (uintptr_t)xr, 0, 0, 0); 2546 2547 err = usb_allocmem(&sc->sc_bus, size, align, USBMALLOC_COHERENT, 2548 &xr->xr_dma); 2549 if (err) { 2550 kmem_free(xr, sizeof(struct xhci_ring)); 2551 DPRINTFN(1, "alloc xr_dma failed %jd", err, 0, 0, 0); 2552 return err; 2553 } 2554 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2555 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2556 xr->xr_trb = xhci_ring_trbv(xr, 0); 2557 xr->xr_ntrb = ntrb; 2558 xr->is_halted = false; 2559 xhci_host_dequeue(xr); 2560 *xrp = xr; 2561 2562 return USBD_NORMAL_COMPLETION; 2563 } 2564 2565 static void 2566 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring ** const xr) 2567 { 2568 if (*xr == NULL) 2569 return; 2570 2571 usb_freemem(&sc->sc_bus, &(*xr)->xr_dma); 2572 mutex_destroy(&(*xr)->xr_lock); 2573 kmem_free((*xr)->xr_cookies, 2574 sizeof(*(*xr)->xr_cookies) * (*xr)->xr_ntrb); 2575 kmem_free(*xr, sizeof(struct xhci_ring)); 2576 *xr = NULL; 2577 } 2578 2579 static void 2580 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2581 void *cookie, struct xhci_soft_trb * const trbs, size_t ntrbs) 2582 { 2583 size_t i; 2584 u_int ri; 2585 u_int cs; 2586 uint64_t parameter; 2587 uint32_t status; 2588 uint32_t control; 2589 2590 XHCIHIST_FUNC(); 2591 XHCIHIST_CALLARGS("%#jx xr_ep %#jx xr_cs %ju", 2592 (uintptr_t)xr, xr->xr_ep, xr->xr_cs, 0); 2593 2594 KASSERTMSG(ntrbs < xr->xr_ntrb, "ntrbs %zu, xr->xr_ntrb %u", 2595 ntrbs, xr->xr_ntrb); 2596 for (i = 0; i < ntrbs; i++) { 2597 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2598 (uintptr_t)trbs, i, 0); 2599 DPRINTFN(12, " 0x%016jx 0x%08jx 0x%08jx", 2600 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2601 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2602 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2603 } 2604 2605 ri = xr->xr_ep; 2606 cs = xr->xr_cs; 2607 2608 /* 2609 * Although the xhci hardware can do scatter/gather dma from 2610 * arbitrary sized buffers, there is a non-obvious restriction 2611 * that a LINK trb is only allowed at the end of a burst of 2612 * transfers - which might be 16kB. 2613 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2614 * The simple solution is not to allow a LINK trb in the middle 2615 * of anything - as here. 2616 * XXX: (dsl) There are xhci controllers out there (eg some made by 2617 * ASMedia) that seem to lock up if they process a LINK trb but 2618 * cannot process the linked-to trb yet. 2619 * The code should write the 'cycle' bit on the link trb AFTER 2620 * adding the other trb. 2621 */ 2622 u_int firstep = xr->xr_ep; 2623 u_int firstcs = xr->xr_cs; 2624 2625 for (i = 0; i < ntrbs; ) { 2626 u_int oldri = ri; 2627 u_int oldcs = cs; 2628 2629 if (ri >= (xr->xr_ntrb - 1)) { 2630 /* Put Link TD at the end of ring */ 2631 parameter = xhci_ring_trbp(xr, 0); 2632 status = 0; 2633 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2634 XHCI_TRB_3_TC_BIT; 2635 xr->xr_cookies[ri] = NULL; 2636 xr->xr_ep = 0; 2637 xr->xr_cs ^= 1; 2638 ri = xr->xr_ep; 2639 cs = xr->xr_cs; 2640 } else { 2641 parameter = trbs[i].trb_0; 2642 status = trbs[i].trb_2; 2643 control = trbs[i].trb_3; 2644 2645 xr->xr_cookies[ri] = cookie; 2646 ri++; 2647 i++; 2648 } 2649 /* 2650 * If this is a first TRB, mark it invalid to prevent 2651 * xHC from running it immediately. 2652 */ 2653 if (oldri == firstep) { 2654 if (oldcs) { 2655 control &= ~XHCI_TRB_3_CYCLE_BIT; 2656 } else { 2657 control |= XHCI_TRB_3_CYCLE_BIT; 2658 } 2659 } else { 2660 if (oldcs) { 2661 control |= XHCI_TRB_3_CYCLE_BIT; 2662 } else { 2663 control &= ~XHCI_TRB_3_CYCLE_BIT; 2664 } 2665 } 2666 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2667 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2668 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2669 } 2670 2671 /* Now invert cycle bit of first TRB */ 2672 if (firstcs) { 2673 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2674 } else { 2675 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2676 } 2677 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2678 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2679 2680 xr->xr_ep = ri; 2681 xr->xr_cs = cs; 2682 2683 DPRINTFN(12, "%#jx xr_ep %#jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2684 xr->xr_cs, 0); 2685 } 2686 2687 static inline void 2688 xhci_ring_put_xfer(struct xhci_softc * const sc, struct xhci_ring * const tr, 2689 struct xhci_xfer *xx, u_int ntrb) 2690 { 2691 KASSERT(ntrb <= xx->xx_ntrb); 2692 xhci_ring_put(sc, tr, xx, xx->xx_trb, ntrb); 2693 } 2694 2695 /* 2696 * Stop execution commands, purge all commands on command ring, and 2697 * rewind dequeue pointer. 2698 */ 2699 static void 2700 xhci_abort_command(struct xhci_softc *sc) 2701 { 2702 struct xhci_ring * const cr = sc->sc_cr; 2703 uint64_t crcr; 2704 int i; 2705 2706 XHCIHIST_FUNC(); 2707 XHCIHIST_CALLARGS("command %#jx timeout, aborting", 2708 sc->sc_command_addr, 0, 0, 0); 2709 2710 mutex_enter(&cr->xr_lock); 2711 2712 /* 4.6.1.2 Aborting a Command */ 2713 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2714 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2715 2716 for (i = 0; i < 500; i++) { 2717 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2718 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2719 break; 2720 usb_delay_ms(&sc->sc_bus, 1); 2721 } 2722 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2723 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2724 /* reset HC here? */ 2725 } 2726 2727 /* reset command ring dequeue pointer */ 2728 cr->xr_ep = 0; 2729 cr->xr_cs = 1; 2730 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2731 2732 mutex_exit(&cr->xr_lock); 2733 } 2734 2735 /* 2736 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2737 * Command completion is notified by cv_signal from xhci_event_cmd() 2738 * (called from xhci_softint), or timed-out. 2739 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2740 * then do_command examines it. 2741 */ 2742 static usbd_status 2743 xhci_do_command_locked(struct xhci_softc * const sc, 2744 struct xhci_soft_trb * const trb, int timeout) 2745 { 2746 struct xhci_ring * const cr = sc->sc_cr; 2747 usbd_status err; 2748 2749 XHCIHIST_FUNC(); 2750 XHCIHIST_CALLARGS("input: 0x%016jx 0x%08jx 0x%08jx", 2751 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2752 2753 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2754 KASSERT(mutex_owned(&sc->sc_lock)); 2755 2756 while (sc->sc_command_addr != 0) 2757 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2758 2759 /* 2760 * If enqueue pointer points at last of ring, it's Link TRB, 2761 * command TRB will be stored in 0th TRB. 2762 */ 2763 if (cr->xr_ep == cr->xr_ntrb - 1) 2764 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2765 else 2766 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2767 2768 sc->sc_resultpending = true; 2769 2770 mutex_enter(&cr->xr_lock); 2771 xhci_ring_put(sc, cr, NULL, trb, 1); 2772 mutex_exit(&cr->xr_lock); 2773 2774 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2775 2776 while (sc->sc_resultpending) { 2777 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2778 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2779 xhci_abort_command(sc); 2780 err = USBD_TIMEOUT; 2781 goto timedout; 2782 } 2783 } 2784 2785 trb->trb_0 = sc->sc_result_trb.trb_0; 2786 trb->trb_2 = sc->sc_result_trb.trb_2; 2787 trb->trb_3 = sc->sc_result_trb.trb_3; 2788 2789 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2790 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2791 2792 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2793 case XHCI_TRB_ERROR_SUCCESS: 2794 err = USBD_NORMAL_COMPLETION; 2795 break; 2796 default: 2797 case 192 ... 223: 2798 DPRINTFN(5, "error %#jx", 2799 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0); 2800 err = USBD_IOERROR; 2801 break; 2802 case 224 ... 255: 2803 err = USBD_NORMAL_COMPLETION; 2804 break; 2805 } 2806 2807 timedout: 2808 sc->sc_resultpending = false; 2809 sc->sc_command_addr = 0; 2810 cv_broadcast(&sc->sc_cmdbusy_cv); 2811 2812 return err; 2813 } 2814 2815 static usbd_status 2816 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb, 2817 int timeout) 2818 { 2819 2820 mutex_enter(&sc->sc_lock); 2821 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2822 mutex_exit(&sc->sc_lock); 2823 2824 return ret; 2825 } 2826 2827 static usbd_status 2828 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2829 { 2830 struct xhci_soft_trb trb; 2831 usbd_status err; 2832 2833 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2834 2835 trb.trb_0 = 0; 2836 trb.trb_2 = 0; 2837 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2838 2839 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2840 if (err != USBD_NORMAL_COMPLETION) { 2841 return err; 2842 } 2843 2844 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2845 2846 return err; 2847 } 2848 2849 /* 2850 * xHCI 4.6.4 2851 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2852 * All endpoints in the slot should be stopped. 2853 * Should be called with sc_lock held. 2854 */ 2855 static usbd_status 2856 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2857 { 2858 struct xhci_soft_trb trb; 2859 struct xhci_slot *xs; 2860 usbd_status err; 2861 2862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2863 2864 if (sc->sc_dying) 2865 return USBD_IOERROR; 2866 2867 trb.trb_0 = 0; 2868 trb.trb_2 = 0; 2869 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) | 2870 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT); 2871 2872 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2873 2874 if (!err) { 2875 xs = &sc->sc_slots[slot]; 2876 if (xs->xs_idx != 0) { 2877 xhci_free_slot(sc, xs); 2878 xhci_set_dcba(sc, 0, slot); 2879 memset(xs, 0, sizeof(*xs)); 2880 } 2881 } 2882 2883 return err; 2884 } 2885 2886 /* 2887 * Set address of device and transition slot state from ENABLED to ADDRESSED 2888 * if Block Setaddress Request (BSR) is false. 2889 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2890 * see xHCI 1.1 4.5.3, 3.3.4 2891 * Should be called without sc_lock held. 2892 */ 2893 static usbd_status 2894 xhci_address_device(struct xhci_softc * const sc, 2895 uint64_t icp, uint8_t slot_id, bool bsr) 2896 { 2897 struct xhci_soft_trb trb; 2898 usbd_status err; 2899 2900 XHCIHIST_FUNC(); 2901 if (bsr) { 2902 XHCIHIST_CALLARGS("icp %#jx slot %#jx with bsr", 2903 icp, slot_id, 0, 0); 2904 } else { 2905 XHCIHIST_CALLARGS("icp %#jx slot %#jx nobsr", 2906 icp, slot_id, 0, 0); 2907 } 2908 2909 trb.trb_0 = icp; 2910 trb.trb_2 = 0; 2911 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2912 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2913 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2914 2915 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2916 2917 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2918 err = USBD_NO_ADDR; 2919 2920 return err; 2921 } 2922 2923 static usbd_status 2924 xhci_update_ep0_mps(struct xhci_softc * const sc, 2925 struct xhci_slot * const xs, u_int mps) 2926 { 2927 struct xhci_soft_trb trb; 2928 usbd_status err; 2929 uint32_t * cp; 2930 2931 XHCIHIST_FUNC(); 2932 XHCIHIST_CALLARGS("slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2933 2934 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2935 cp[0] = htole32(0); 2936 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2937 2938 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2939 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2940 2941 /* sync input contexts before they are read from memory */ 2942 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2943 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2944 sc->sc_ctxsz * 4); 2945 2946 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2947 trb.trb_2 = 0; 2948 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2949 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2950 2951 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2952 return err; 2953 } 2954 2955 static void 2956 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2957 { 2958 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2959 2960 XHCIHIST_FUNC(); 2961 XHCIHIST_CALLARGS("dcbaa %#jx dc 0x%016jx slot %jd", 2962 (uintptr_t)&dcbaa[si], dcba, si, 0); 2963 2964 dcbaa[si] = htole64(dcba); 2965 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2966 BUS_DMASYNC_PREWRITE); 2967 } 2968 2969 /* 2970 * Allocate device and input context DMA buffer, and 2971 * TRB DMA buffer for each endpoint. 2972 */ 2973 static usbd_status 2974 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2975 { 2976 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2977 struct xhci_slot *xs; 2978 usbd_status err; 2979 2980 XHCIHIST_FUNC(); 2981 XHCIHIST_CALLARGS("slot %ju", slot, 0, 0, 0); 2982 2983 xs = &sc->sc_slots[slot]; 2984 2985 /* allocate contexts */ 2986 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2987 USBMALLOC_COHERENT, &xs->xs_dc_dma); 2988 if (err) { 2989 DPRINTFN(1, "failed to allocmem output device context %jd", 2990 err, 0, 0, 0); 2991 return err; 2992 } 2993 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2994 2995 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2996 USBMALLOC_COHERENT, &xs->xs_ic_dma); 2997 if (err) { 2998 DPRINTFN(1, "failed to allocmem input device context %jd", 2999 err, 0, 0, 0); 3000 goto bad1; 3001 } 3002 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 3003 3004 memset(&xs->xs_xr[0], 0, sizeof(xs->xs_xr)); 3005 xs->xs_idx = slot; 3006 3007 return USBD_NORMAL_COMPLETION; 3008 3009 bad1: 3010 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3011 xs->xs_idx = 0; 3012 return err; 3013 } 3014 3015 static void 3016 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs) 3017 { 3018 u_int dci; 3019 3020 XHCIHIST_FUNC(); 3021 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 3022 3023 /* deallocate all allocated rings in the slot */ 3024 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 3025 if (xs->xs_xr[dci] != NULL) 3026 xhci_ring_free(sc, &xs->xs_xr[dci]); 3027 } 3028 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 3029 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3030 xs->xs_idx = 0; 3031 } 3032 3033 /* 3034 * Setup slot context, set Device Context Base Address, and issue 3035 * Set Address Device command. 3036 */ 3037 static usbd_status 3038 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 3039 { 3040 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3041 struct xhci_slot *xs; 3042 usbd_status err; 3043 3044 XHCIHIST_FUNC(); 3045 XHCIHIST_CALLARGS("slot %ju bsr %ju", slot, bsr, 0, 0); 3046 3047 xs = &sc->sc_slots[slot]; 3048 3049 xhci_setup_ctx(dev->ud_pipe0); 3050 3051 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3052 sc->sc_ctxsz * 3); 3053 3054 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3055 3056 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3057 3058 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3059 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 3060 sc->sc_ctxsz * 2); 3061 3062 return err; 3063 } 3064 3065 /* 3066 * 4.8.2, 6.2.3.2 3067 * construct slot/endpoint context parameters and do syncmem 3068 */ 3069 static void 3070 xhci_setup_ctx(struct usbd_pipe *pipe) 3071 { 3072 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3073 struct usbd_device *dev = pipe->up_dev; 3074 struct xhci_slot * const xs = dev->ud_hcpriv; 3075 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3076 const u_int dci = xhci_ep_get_dci(ed); 3077 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3078 uint32_t *cp; 3079 uint16_t mps = UGETW(ed->wMaxPacketSize); 3080 uint8_t speed = dev->ud_speed; 3081 uint8_t ival = ed->bInterval; 3082 3083 XHCIHIST_FUNC(); 3084 XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju", 3085 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3086 3087 /* set up initial input control context */ 3088 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3089 cp[0] = htole32(0); 3090 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3091 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3092 cp[7] = htole32(0); 3093 3094 /* set up input slot context */ 3095 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3096 cp[0] = 3097 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3098 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3099 cp[1] = 0; 3100 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3101 cp[3] = 0; 3102 xhci_setup_route(pipe, cp); 3103 xhci_setup_tthub(pipe, cp); 3104 3105 cp[0] = htole32(cp[0]); 3106 cp[1] = htole32(cp[1]); 3107 cp[2] = htole32(cp[2]); 3108 cp[3] = htole32(cp[3]); 3109 3110 /* set up input endpoint context */ 3111 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3112 cp[0] = 3113 XHCI_EPCTX_0_EPSTATE_SET(0) | 3114 XHCI_EPCTX_0_MULT_SET(0) | 3115 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3116 XHCI_EPCTX_0_LSA_SET(0) | 3117 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3118 cp[1] = 3119 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3120 XHCI_EPCTX_1_HID_SET(0) | 3121 XHCI_EPCTX_1_MAXB_SET(0); 3122 3123 if (xfertype != UE_ISOCHRONOUS) 3124 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3125 3126 if (xfertype == UE_CONTROL) 3127 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3128 else if (USB_IS_SS(speed)) 3129 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3130 else 3131 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3132 3133 xhci_setup_maxburst(pipe, cp); 3134 3135 switch (xfertype) { 3136 case UE_CONTROL: 3137 break; 3138 case UE_BULK: 3139 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3140 break; 3141 case UE_INTERRUPT: 3142 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3143 ival = pipe->up_interval; 3144 3145 ival = xhci_bival2ival(ival, speed); 3146 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3147 break; 3148 case UE_ISOCHRONOUS: 3149 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3150 ival = pipe->up_interval; 3151 3152 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3153 if (speed == USB_SPEED_FULL) 3154 ival += 3; /* 1ms -> 125us */ 3155 ival--; 3156 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3157 break; 3158 default: 3159 break; 3160 } 3161 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3162 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3163 3164 /* rewind TR dequeue pointer in xHC */ 3165 /* can't use xhci_ep_get_dci() yet? */ 3166 *(uint64_t *)(&cp[2]) = htole64( 3167 xhci_ring_trbp(xs->xs_xr[dci], 0) | 3168 XHCI_EPCTX_2_DCS_SET(1)); 3169 3170 cp[0] = htole32(cp[0]); 3171 cp[1] = htole32(cp[1]); 3172 cp[4] = htole32(cp[4]); 3173 3174 /* rewind TR dequeue pointer in driver */ 3175 struct xhci_ring *xr = xs->xs_xr[dci]; 3176 mutex_enter(&xr->xr_lock); 3177 xhci_host_dequeue(xr); 3178 mutex_exit(&xr->xr_lock); 3179 3180 /* sync input contexts before they are read from memory */ 3181 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3182 } 3183 3184 /* 3185 * Setup route string and roothub port of given device for slot context 3186 */ 3187 static void 3188 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3189 { 3190 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3191 struct usbd_device *dev = pipe->up_dev; 3192 struct usbd_port *up = dev->ud_powersrc; 3193 struct usbd_device *hub; 3194 struct usbd_device *adev; 3195 uint8_t rhport = 0; 3196 uint32_t route = 0; 3197 3198 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3199 3200 /* Locate root hub port and Determine route string */ 3201 /* 4.3.3 route string does not include roothub port */ 3202 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3203 uint32_t dep; 3204 3205 DPRINTFN(4, "hub %#jx depth %jd upport %#jx upportno %jd", 3206 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3207 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3208 -1); 3209 3210 if (hub->ud_powersrc == NULL) 3211 break; 3212 dep = hub->ud_depth; 3213 if (dep == 0) 3214 break; 3215 rhport = hub->ud_powersrc->up_portno; 3216 if (dep > USB_HUB_MAX_DEPTH) 3217 continue; 3218 3219 route |= 3220 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3221 << ((dep - 1) * 4); 3222 } 3223 route = route >> 4; 3224 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3225 3226 /* Locate port on upstream high speed hub */ 3227 for (adev = dev, hub = up->up_parent; 3228 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3229 adev = hub, hub = hub->ud_myhub) 3230 ; 3231 if (hub) { 3232 int p; 3233 for (p = 1; p <= hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3234 if (hub->ud_hub->uh_ports[p - 1].up_dev == adev) { 3235 dev->ud_myhsport = &hub->ud_hub->uh_ports[p - 1]; 3236 goto found; 3237 } 3238 } 3239 panic("%s: cannot find HS port", __func__); 3240 found: 3241 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3242 } else { 3243 dev->ud_myhsport = NULL; 3244 } 3245 3246 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3247 3248 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3249 ctlrport, route, (uintptr_t)hub); 3250 3251 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3252 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3253 } 3254 3255 /* 3256 * Setup whether device is hub, whether device uses MTT, and 3257 * TT informations if it uses MTT. 3258 */ 3259 static void 3260 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3261 { 3262 struct usbd_device *dev = pipe->up_dev; 3263 struct usbd_port *myhsport = dev->ud_myhsport; 3264 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3265 uint32_t speed = dev->ud_speed; 3266 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3267 uint8_t tthubslot, ttportnum; 3268 bool ishub; 3269 bool usemtt; 3270 3271 XHCIHIST_FUNC(); 3272 3273 /* 3274 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3275 * tthubslot: 3276 * This is the slot ID of parent HS hub 3277 * if LS/FS device is connected && connected through HS hub. 3278 * This is 0 if device is not LS/FS device || 3279 * parent hub is not HS hub || 3280 * attached to root hub. 3281 * ttportnum: 3282 * This is the downstream facing port of parent HS hub 3283 * if LS/FS device is connected. 3284 * This is 0 if device is not LS/FS device || 3285 * parent hub is not HS hub || 3286 * attached to root hub. 3287 */ 3288 if (myhsport && 3289 myhsport->up_parent->ud_addr != rhaddr && 3290 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3291 ttportnum = myhsport->up_portno; 3292 tthubslot = myhsport->up_parent->ud_addr; 3293 } else { 3294 ttportnum = 0; 3295 tthubslot = 0; 3296 } 3297 XHCIHIST_CALLARGS("myhsport %#jx ttportnum=%jd tthubslot=%jd", 3298 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3299 3300 /* ishub is valid after reading UDESC_DEVICE */ 3301 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3302 3303 /* dev->ud_hub is valid after reading UDESC_HUB */ 3304 if (ishub && dev->ud_hub) { 3305 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3306 uint8_t ttt = 3307 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3308 3309 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3310 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3311 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3312 } 3313 3314 #define IS_MTTHUB(dd) \ 3315 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3316 3317 /* 3318 * MTT flag is set if 3319 * 1. this is HS hub && MTTs are supported and enabled; or 3320 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3321 * are supported and enabled. 3322 * 3323 * XXX enabled is not tested yet 3324 */ 3325 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3326 usemtt = true; 3327 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3328 myhsport && 3329 myhsport->up_parent->ud_addr != rhaddr && 3330 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3331 usemtt = true; 3332 else 3333 usemtt = false; 3334 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3335 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3336 3337 #undef IS_MTTHUB 3338 3339 cp[0] |= 3340 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3341 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3342 cp[2] |= 3343 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3344 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3345 } 3346 3347 /* set up params for periodic endpoint */ 3348 static void 3349 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3350 { 3351 struct usbd_device *dev = pipe->up_dev; 3352 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3353 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3354 usbd_desc_iter_t iter; 3355 const usb_cdc_descriptor_t *cdcd; 3356 uint32_t maxb = 0; 3357 uint16_t mps = UGETW(ed->wMaxPacketSize); 3358 uint8_t speed = dev->ud_speed; 3359 uint8_t ep; 3360 3361 /* config desc is NULL when opening ep0 */ 3362 if (dev == NULL || dev->ud_cdesc == NULL) 3363 goto no_cdcd; 3364 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3365 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3366 if (cdcd == NULL) 3367 goto no_cdcd; 3368 usb_desc_iter_init(dev, &iter); 3369 iter.cur = (const void *)cdcd; 3370 3371 /* find endpoint_ss_comp desc for ep of this pipe */ 3372 for (ep = 0;;) { 3373 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3374 if (cdcd == NULL) 3375 break; 3376 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3377 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3378 bEndpointAddress; 3379 if (UE_GET_ADDR(ep) == 3380 UE_GET_ADDR(ed->bEndpointAddress)) { 3381 cdcd = (const usb_cdc_descriptor_t *) 3382 usb_desc_iter_next(&iter); 3383 break; 3384 } 3385 ep = 0; 3386 } 3387 } 3388 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3389 const usb_endpoint_ss_comp_descriptor_t * esscd = 3390 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3391 maxb = esscd->bMaxBurst; 3392 } 3393 3394 no_cdcd: 3395 /* 6.2.3.4, 4.8.2.4 */ 3396 if (USB_IS_SS(speed)) { 3397 /* USB 3.1 9.6.6 */ 3398 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3399 /* USB 3.1 9.6.7 */ 3400 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3401 #ifdef notyet 3402 if (xfertype == UE_ISOCHRONOUS) { 3403 } 3404 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3405 /* use ESIT */ 3406 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3407 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3408 3409 /* XXX if LEC = 1, set ESIT instead */ 3410 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3411 } else { 3412 /* use ival */ 3413 } 3414 #endif 3415 } else { 3416 /* USB 2.0 9.6.6 */ 3417 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3418 3419 /* 6.2.3.4 */ 3420 if (speed == USB_SPEED_HIGH && 3421 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3422 maxb = UE_GET_TRANS(mps); 3423 } else { 3424 /* LS/FS or HS CTRL or HS BULK */ 3425 maxb = 0; 3426 } 3427 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3428 } 3429 } 3430 3431 /* 3432 * Convert endpoint bInterval value to endpoint context interval value 3433 * for Interrupt pipe. 3434 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3435 */ 3436 static uint32_t 3437 xhci_bival2ival(uint32_t ival, uint32_t speed) 3438 { 3439 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3440 int i; 3441 3442 /* 3443 * round ival down to "the nearest base 2 multiple of 3444 * bInterval * 8". 3445 * bInterval is at most 255 as its type is uByte. 3446 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3447 */ 3448 for (i = 10; i > 0; i--) { 3449 if ((ival * 8) >= (1 << i)) 3450 break; 3451 } 3452 ival = i; 3453 } else { 3454 /* Interval = bInterval-1 for SS/HS */ 3455 ival--; 3456 } 3457 3458 return ival; 3459 } 3460 3461 /* ----- */ 3462 3463 static void 3464 xhci_noop(struct usbd_pipe *pipe) 3465 { 3466 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3467 } 3468 3469 /* 3470 * Process root hub request. 3471 */ 3472 static int 3473 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3474 void *buf, int buflen) 3475 { 3476 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3477 usb_port_status_t ps; 3478 int l, totlen = 0; 3479 uint16_t len, value, index; 3480 int port, i; 3481 uint32_t v; 3482 3483 XHCIHIST_FUNC(); 3484 3485 if (sc->sc_dying) 3486 return -1; 3487 3488 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3489 3490 len = UGETW(req->wLength); 3491 value = UGETW(req->wValue); 3492 index = UGETW(req->wIndex); 3493 3494 XHCIHIST_CALLARGS("rhreq: %04jx %04jx %04jx %04jx", 3495 req->bmRequestType | (req->bRequest << 8), value, index, len); 3496 3497 #define C(x,y) ((x) | ((y) << 8)) 3498 switch (C(req->bRequest, req->bmRequestType)) { 3499 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3500 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3501 if (len == 0) 3502 break; 3503 switch (value) { 3504 #define sd ((usb_string_descriptor_t *)buf) 3505 case C(2, UDESC_STRING): 3506 /* Product */ 3507 totlen = usb_makestrdesc(sd, len, "xHCI root hub"); 3508 break; 3509 #undef sd 3510 default: 3511 /* default from usbroothub */ 3512 return buflen; 3513 } 3514 break; 3515 3516 /* Hub requests */ 3517 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3518 break; 3519 /* Clear Port Feature request */ 3520 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3521 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3522 3523 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3524 index, value, bn, cp); 3525 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3526 return -1; 3527 } 3528 port = XHCI_PORTSC(cp); 3529 v = xhci_op_read_4(sc, port); 3530 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3531 v &= ~XHCI_PS_CLEAR; 3532 switch (value) { 3533 case UHF_PORT_ENABLE: 3534 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3535 break; 3536 case UHF_PORT_SUSPEND: 3537 return -1; 3538 case UHF_PORT_POWER: 3539 break; 3540 case UHF_PORT_TEST: 3541 case UHF_PORT_INDICATOR: 3542 return -1; 3543 case UHF_C_PORT_CONNECTION: 3544 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3545 break; 3546 case UHF_C_PORT_ENABLE: 3547 case UHF_C_PORT_SUSPEND: 3548 case UHF_C_PORT_OVER_CURRENT: 3549 return -1; 3550 case UHF_C_BH_PORT_RESET: 3551 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3552 break; 3553 case UHF_C_PORT_RESET: 3554 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3555 break; 3556 case UHF_C_PORT_LINK_STATE: 3557 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3558 break; 3559 case UHF_C_PORT_CONFIG_ERROR: 3560 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3561 break; 3562 default: 3563 return -1; 3564 } 3565 break; 3566 } 3567 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3568 if (len == 0) 3569 break; 3570 if ((value & 0xff) != 0) { 3571 return -1; 3572 } 3573 usb_hub_descriptor_t hubd; 3574 3575 totlen = uimin(buflen, sizeof(hubd)); 3576 memcpy(&hubd, buf, totlen); 3577 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3578 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3579 hubd.bPwrOn2PwrGood = 200; 3580 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3581 /* XXX can't find out? */ 3582 hubd.DeviceRemovable[i++] = 0; 3583 } 3584 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3585 totlen = uimin(totlen, hubd.bDescLength); 3586 memcpy(buf, &hubd, totlen); 3587 break; 3588 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3589 if (len != 4) { 3590 return -1; 3591 } 3592 memset(buf, 0, len); /* ? XXX */ 3593 totlen = len; 3594 break; 3595 /* Get Port Status request */ 3596 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3597 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3598 3599 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3600 bn, index, cp, 0); 3601 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3602 DPRINTFN(5, "bad get port status: index=%jd bn=%jd " 3603 "portcount=%jd", 3604 index, bn, sc->sc_rhportcount[bn], 0); 3605 return -1; 3606 } 3607 if (len != 4) { 3608 DPRINTFN(5, "bad get port status: len %jd != 4", 3609 len, 0, 0, 0); 3610 return -1; 3611 } 3612 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3613 DPRINTFN(4, "getrhportsc %jd 0x%08jx", cp, v, 0, 0); 3614 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3615 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3616 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3617 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3618 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3619 if (v & XHCI_PS_PR) i |= UPS_RESET; 3620 if (v & XHCI_PS_PP) { 3621 if (i & UPS_OTHER_SPEED) 3622 i |= UPS_PORT_POWER_SS; 3623 else 3624 i |= UPS_PORT_POWER; 3625 } 3626 if (i & UPS_OTHER_SPEED) 3627 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3628 if (sc->sc_vendor_port_status) 3629 i = sc->sc_vendor_port_status(sc, v, i); 3630 USETW(ps.wPortStatus, i); 3631 i = 0; 3632 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3633 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3634 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3635 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3636 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3637 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3638 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3639 USETW(ps.wPortChange, i); 3640 totlen = uimin(len, sizeof(ps)); 3641 memcpy(buf, &ps, totlen); 3642 DPRINTFN(5, "get port status: wPortStatus %#jx wPortChange %#jx" 3643 " totlen %jd", 3644 UGETW(ps.wPortStatus), UGETW(ps.wPortChange), totlen, 0); 3645 break; 3646 } 3647 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3648 return -1; 3649 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3650 break; 3651 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3652 break; 3653 /* Set Port Feature request */ 3654 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3655 int optval = (index >> 8) & 0xff; 3656 index &= 0xff; 3657 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3658 return -1; 3659 } 3660 3661 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3662 3663 port = XHCI_PORTSC(cp); 3664 v = xhci_op_read_4(sc, port); 3665 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3666 v &= ~XHCI_PS_CLEAR; 3667 switch (value) { 3668 case UHF_PORT_ENABLE: 3669 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3670 break; 3671 case UHF_PORT_SUSPEND: 3672 /* XXX suspend */ 3673 break; 3674 case UHF_PORT_RESET: 3675 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3676 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3677 /* Wait for reset to complete. */ 3678 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3679 if (sc->sc_dying) { 3680 return -1; 3681 } 3682 v = xhci_op_read_4(sc, port); 3683 if (v & XHCI_PS_PR) { 3684 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3685 usb_delay_ms(&sc->sc_bus, 10); 3686 /* XXX */ 3687 } 3688 break; 3689 case UHF_PORT_POWER: 3690 /* XXX power control */ 3691 break; 3692 /* XXX more */ 3693 case UHF_C_PORT_RESET: 3694 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3695 break; 3696 case UHF_PORT_U1_TIMEOUT: 3697 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3698 return -1; 3699 } 3700 port = XHCI_PORTPMSC(cp); 3701 v = xhci_op_read_4(sc, port); 3702 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3703 index, cp, v, 0); 3704 v &= ~XHCI_PM3_U1TO_SET(0xff); 3705 v |= XHCI_PM3_U1TO_SET(optval); 3706 xhci_op_write_4(sc, port, v); 3707 break; 3708 case UHF_PORT_U2_TIMEOUT: 3709 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3710 return -1; 3711 } 3712 port = XHCI_PORTPMSC(cp); 3713 v = xhci_op_read_4(sc, port); 3714 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3715 index, cp, v, 0); 3716 v &= ~XHCI_PM3_U2TO_SET(0xff); 3717 v |= XHCI_PM3_U2TO_SET(optval); 3718 xhci_op_write_4(sc, port, v); 3719 break; 3720 default: 3721 return -1; 3722 } 3723 } 3724 break; 3725 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3726 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3727 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3728 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3729 break; 3730 default: 3731 /* default from usbroothub */ 3732 return buflen; 3733 } 3734 3735 return totlen; 3736 } 3737 3738 /* root hub interrupt */ 3739 3740 static usbd_status 3741 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3742 { 3743 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3744 usbd_status err; 3745 3746 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3747 3748 /* Insert last in queue. */ 3749 mutex_enter(&sc->sc_lock); 3750 err = usb_insert_transfer(xfer); 3751 mutex_exit(&sc->sc_lock); 3752 if (err) 3753 return err; 3754 3755 /* Pipe isn't running, start first */ 3756 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3757 } 3758 3759 /* Wait for roothub port status/change */ 3760 static usbd_status 3761 xhci_root_intr_start(struct usbd_xfer *xfer) 3762 { 3763 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3764 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3765 const bool polling = xhci_polling_p(sc); 3766 3767 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3768 3769 if (sc->sc_dying) 3770 return USBD_IOERROR; 3771 3772 if (!polling) 3773 mutex_enter(&sc->sc_lock); 3774 KASSERT(sc->sc_intrxfer[bn] == NULL); 3775 sc->sc_intrxfer[bn] = xfer; 3776 xfer->ux_status = USBD_IN_PROGRESS; 3777 if (!polling) 3778 mutex_exit(&sc->sc_lock); 3779 3780 return USBD_IN_PROGRESS; 3781 } 3782 3783 static void 3784 xhci_root_intr_abort(struct usbd_xfer *xfer) 3785 { 3786 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3787 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3788 3789 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3790 3791 KASSERT(mutex_owned(&sc->sc_lock)); 3792 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3793 3794 /* If xfer has already completed, nothing to do here. */ 3795 if (sc->sc_intrxfer[bn] == NULL) 3796 return; 3797 3798 /* 3799 * Otherwise, sc->sc_intrxfer[bn] had better be this transfer. 3800 * Cancel it. 3801 */ 3802 KASSERT(sc->sc_intrxfer[bn] == xfer); 3803 xfer->ux_status = USBD_CANCELLED; 3804 usb_transfer_complete(xfer); 3805 } 3806 3807 static void 3808 xhci_root_intr_close(struct usbd_pipe *pipe) 3809 { 3810 struct xhci_softc * const sc __diagused = XHCI_PIPE2SC(pipe); 3811 const struct usbd_xfer *xfer __diagused = pipe->up_intrxfer; 3812 const size_t bn __diagused = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3813 3814 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3815 3816 KASSERT(mutex_owned(&sc->sc_lock)); 3817 3818 /* 3819 * Caller must guarantee the xfer has completed first, by 3820 * closing the pipe only after normal completion or an abort. 3821 */ 3822 KASSERT(sc->sc_intrxfer[bn] == NULL); 3823 } 3824 3825 static void 3826 xhci_root_intr_done(struct usbd_xfer *xfer) 3827 { 3828 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3829 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3830 3831 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3832 3833 KASSERT(mutex_owned(&sc->sc_lock)); 3834 3835 /* Claim the xfer so it doesn't get completed again. */ 3836 KASSERT(sc->sc_intrxfer[bn] == xfer); 3837 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 3838 sc->sc_intrxfer[bn] = NULL; 3839 } 3840 3841 /* -------------- */ 3842 /* device control */ 3843 3844 static usbd_status 3845 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3846 { 3847 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3848 usbd_status err; 3849 3850 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3851 3852 /* Insert last in queue. */ 3853 mutex_enter(&sc->sc_lock); 3854 err = usb_insert_transfer(xfer); 3855 mutex_exit(&sc->sc_lock); 3856 if (err) 3857 return err; 3858 3859 /* Pipe isn't running, start first */ 3860 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3861 } 3862 3863 static usbd_status 3864 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3865 { 3866 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3867 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3868 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3869 struct xhci_ring * const tr = xs->xs_xr[dci]; 3870 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3871 usb_device_request_t * const req = &xfer->ux_request; 3872 const bool isread = usbd_xfer_isread(xfer); 3873 const uint32_t len = UGETW(req->wLength); 3874 usb_dma_t * const dma = &xfer->ux_dmabuf; 3875 uint64_t parameter; 3876 uint32_t status; 3877 uint32_t control; 3878 u_int i; 3879 const bool polling = xhci_polling_p(sc); 3880 3881 XHCIHIST_FUNC(); 3882 XHCIHIST_CALLARGS("req: %04jx %04jx %04jx %04jx", 3883 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3884 UGETW(req->wIndex), UGETW(req->wLength)); 3885 3886 /* we rely on the bottom bits for extra info */ 3887 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3888 (uintptr_t) xfer); 3889 3890 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3891 3892 i = 0; 3893 3894 /* setup phase */ 3895 parameter = le64dec(req); /* to keep USB endian after xhci_trb_put() */ 3896 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3897 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3898 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3899 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3900 XHCI_TRB_3_IDT_BIT; 3901 xhci_xfer_put_trb(xx, i++, parameter, status, control); 3902 3903 if (len != 0) { 3904 /* data phase */ 3905 parameter = DMAADDR(dma, 0); 3906 KASSERTMSG(len <= 0x10000, "len %d", len); 3907 status = XHCI_TRB_2_IRQ_SET(0) | 3908 XHCI_TRB_2_TDSZ_SET(0) | 3909 XHCI_TRB_2_BYTES_SET(len); 3910 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3911 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3912 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 3913 XHCI_TRB_3_IOC_BIT; 3914 xhci_xfer_put_trb(xx, i++, parameter, status, control); 3915 3916 usb_syncmem(dma, 0, len, 3917 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3918 } 3919 3920 parameter = 0; 3921 status = XHCI_TRB_2_IRQ_SET(0); 3922 /* the status stage has inverted direction */ 3923 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3924 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3925 XHCI_TRB_3_IOC_BIT; 3926 xhci_xfer_put_trb(xx, i++, parameter, status, control); 3927 3928 if (!polling) 3929 mutex_enter(&tr->xr_lock); 3930 xhci_ring_put_xfer(sc, tr, xx, i); 3931 if (!polling) 3932 mutex_exit(&tr->xr_lock); 3933 3934 if (!polling) 3935 mutex_enter(&sc->sc_lock); 3936 xfer->ux_status = USBD_IN_PROGRESS; 3937 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3938 usbd_xfer_schedule_timeout(xfer); 3939 if (!polling) 3940 mutex_exit(&sc->sc_lock); 3941 3942 return USBD_IN_PROGRESS; 3943 } 3944 3945 static void 3946 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3947 { 3948 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3949 usb_device_request_t *req = &xfer->ux_request; 3950 int len = UGETW(req->wLength); 3951 int rd = req->bmRequestType & UT_READ; 3952 3953 if (len) 3954 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3955 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3956 } 3957 3958 static void 3959 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3960 { 3961 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3962 3963 usbd_xfer_abort(xfer); 3964 } 3965 3966 static void 3967 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3968 { 3969 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3970 3971 xhci_close_pipe(pipe); 3972 } 3973 3974 /* ------------------ */ 3975 /* device isochronous */ 3976 3977 /* ----------- */ 3978 /* device bulk */ 3979 3980 static usbd_status 3981 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3982 { 3983 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3984 usbd_status err; 3985 3986 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3987 3988 /* Insert last in queue. */ 3989 mutex_enter(&sc->sc_lock); 3990 err = usb_insert_transfer(xfer); 3991 mutex_exit(&sc->sc_lock); 3992 if (err) 3993 return err; 3994 3995 /* 3996 * Pipe isn't running (otherwise err would be USBD_INPROG), 3997 * so start it first. 3998 */ 3999 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4000 } 4001 4002 static usbd_status 4003 xhci_device_bulk_start(struct usbd_xfer *xfer) 4004 { 4005 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4006 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4007 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4008 struct xhci_ring * const tr = xs->xs_xr[dci]; 4009 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4010 const uint32_t len = xfer->ux_length; 4011 usb_dma_t * const dma = &xfer->ux_dmabuf; 4012 uint64_t parameter; 4013 uint32_t status; 4014 uint32_t control; 4015 u_int i = 0; 4016 const bool polling = xhci_polling_p(sc); 4017 4018 XHCIHIST_FUNC(); 4019 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4020 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4021 4022 if (sc->sc_dying) 4023 return USBD_IOERROR; 4024 4025 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4026 4027 parameter = DMAADDR(dma, 0); 4028 const bool isread = usbd_xfer_isread(xfer); 4029 if (len) 4030 usb_syncmem(dma, 0, len, 4031 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4032 4033 /* 4034 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 4035 * If the user supplied buffer crosses such a boundary then 2 4036 * (or more) TRB should be used. 4037 * If multiple TRB are used the td_size field must be set correctly. 4038 * For v1.0 devices (like ivy bridge) this is the number of usb data 4039 * blocks needed to complete the transfer. 4040 * Setting it to 1 in the last TRB causes an extra zero-length 4041 * data block be sent. 4042 * The earlier documentation differs, I don't know how it behaves. 4043 */ 4044 KASSERTMSG(len <= 0x10000, "len %d", len); 4045 status = XHCI_TRB_2_IRQ_SET(0) | 4046 XHCI_TRB_2_TDSZ_SET(0) | 4047 XHCI_TRB_2_BYTES_SET(len); 4048 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4049 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 4050 XHCI_TRB_3_IOC_BIT; 4051 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4052 4053 if (!polling) 4054 mutex_enter(&tr->xr_lock); 4055 xhci_ring_put_xfer(sc, tr, xx, i); 4056 if (!polling) 4057 mutex_exit(&tr->xr_lock); 4058 4059 if (!polling) 4060 mutex_enter(&sc->sc_lock); 4061 xfer->ux_status = USBD_IN_PROGRESS; 4062 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4063 usbd_xfer_schedule_timeout(xfer); 4064 if (!polling) 4065 mutex_exit(&sc->sc_lock); 4066 4067 return USBD_IN_PROGRESS; 4068 } 4069 4070 static void 4071 xhci_device_bulk_done(struct usbd_xfer *xfer) 4072 { 4073 #ifdef USB_DEBUG 4074 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4075 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4076 #endif 4077 const bool isread = usbd_xfer_isread(xfer); 4078 4079 XHCIHIST_FUNC(); 4080 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4081 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4082 4083 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4084 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4085 } 4086 4087 static void 4088 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4089 { 4090 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4091 4092 usbd_xfer_abort(xfer); 4093 } 4094 4095 static void 4096 xhci_device_bulk_close(struct usbd_pipe *pipe) 4097 { 4098 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4099 4100 xhci_close_pipe(pipe); 4101 } 4102 4103 /* ---------------- */ 4104 /* device interrupt */ 4105 4106 static usbd_status 4107 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4108 { 4109 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4110 usbd_status err; 4111 4112 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4113 4114 /* Insert last in queue. */ 4115 mutex_enter(&sc->sc_lock); 4116 err = usb_insert_transfer(xfer); 4117 mutex_exit(&sc->sc_lock); 4118 if (err) 4119 return err; 4120 4121 /* 4122 * Pipe isn't running (otherwise err would be USBD_INPROG), 4123 * so start it first. 4124 */ 4125 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4126 } 4127 4128 static usbd_status 4129 xhci_device_intr_start(struct usbd_xfer *xfer) 4130 { 4131 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4132 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4133 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4134 struct xhci_ring * const tr = xs->xs_xr[dci]; 4135 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4136 const uint32_t len = xfer->ux_length; 4137 const bool polling = xhci_polling_p(sc); 4138 usb_dma_t * const dma = &xfer->ux_dmabuf; 4139 uint64_t parameter; 4140 uint32_t status; 4141 uint32_t control; 4142 u_int i = 0; 4143 4144 XHCIHIST_FUNC(); 4145 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4146 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4147 4148 if (sc->sc_dying) 4149 return USBD_IOERROR; 4150 4151 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4152 4153 const bool isread = usbd_xfer_isread(xfer); 4154 if (len) 4155 usb_syncmem(dma, 0, len, 4156 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4157 4158 parameter = DMAADDR(dma, 0); 4159 KASSERTMSG(len <= 0x10000, "len %d", len); 4160 status = XHCI_TRB_2_IRQ_SET(0) | 4161 XHCI_TRB_2_TDSZ_SET(0) | 4162 XHCI_TRB_2_BYTES_SET(len); 4163 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4164 (isread ? XHCI_TRB_3_ISP_BIT : 0) | XHCI_TRB_3_IOC_BIT; 4165 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4166 4167 if (!polling) 4168 mutex_enter(&tr->xr_lock); 4169 xhci_ring_put_xfer(sc, tr, xx, i); 4170 if (!polling) 4171 mutex_exit(&tr->xr_lock); 4172 4173 if (!polling) 4174 mutex_enter(&sc->sc_lock); 4175 xfer->ux_status = USBD_IN_PROGRESS; 4176 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4177 usbd_xfer_schedule_timeout(xfer); 4178 if (!polling) 4179 mutex_exit(&sc->sc_lock); 4180 4181 return USBD_IN_PROGRESS; 4182 } 4183 4184 static void 4185 xhci_device_intr_done(struct usbd_xfer *xfer) 4186 { 4187 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4188 #ifdef USB_DEBUG 4189 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4190 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4191 #endif 4192 const bool isread = usbd_xfer_isread(xfer); 4193 4194 XHCIHIST_FUNC(); 4195 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4196 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4197 4198 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4199 4200 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4201 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4202 } 4203 4204 static void 4205 xhci_device_intr_abort(struct usbd_xfer *xfer) 4206 { 4207 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4208 4209 XHCIHIST_FUNC(); 4210 XHCIHIST_CALLARGS("%#jx", (uintptr_t)xfer, 0, 0, 0); 4211 4212 KASSERT(mutex_owned(&sc->sc_lock)); 4213 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4214 usbd_xfer_abort(xfer); 4215 } 4216 4217 static void 4218 xhci_device_intr_close(struct usbd_pipe *pipe) 4219 { 4220 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4221 4222 XHCIHIST_FUNC(); 4223 XHCIHIST_CALLARGS("%#jx", (uintptr_t)pipe, 0, 0, 0); 4224 4225 xhci_close_pipe(pipe); 4226 } 4227
Indexes created Wed Oct 01 18:09:54 GMT 2025