xhci.c revision 1.169
1 /* $NetBSD: xhci.c,v 1.169 2022/09/01 18:09:45 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.169 2022/09/01 18:09:45 riastradh Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 119 #define XHCIHIST_FUNC() USBHIST_FUNC() 120 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 121 #define XHCIHIST_CALLARGS(FMT,A,B,C,D) \ 122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D) 123 124 #define XHCI_DCI_SLOT 0 125 #define XHCI_DCI_EP_CONTROL 1 126 127 #define XHCI_ICI_INPUT_CONTROL 0 128 129 struct xhci_pipe { 130 struct usbd_pipe xp_pipe; 131 struct usb_task xp_async_task; 132 int16_t xp_isoc_next; /* next frame */ 133 uint8_t xp_maxb; /* max burst */ 134 uint8_t xp_mult; 135 }; 136 137 #define XHCI_COMMAND_RING_TRBS 256 138 #define XHCI_EVENT_RING_TRBS 256 139 #define XHCI_EVENT_RING_SEGMENTS 1 140 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 141 142 static usbd_status xhci_open(struct usbd_pipe *); 143 static void xhci_close_pipe(struct usbd_pipe *); 144 static int xhci_intr1(struct xhci_softc * const); 145 static void xhci_softintr(void *); 146 static void xhci_poll(struct usbd_bus *); 147 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 148 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 149 static void xhci_abortx(struct usbd_xfer *); 150 static bool xhci_dying(struct usbd_bus *); 151 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 152 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 153 struct usbd_port *); 154 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 155 void *, int); 156 157 static void xhci_pipe_restart(struct usbd_pipe *); 158 static void xhci_pipe_restart_async_task(void *); 159 static void xhci_pipe_restart_async(struct usbd_pipe *); 160 161 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 162 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 163 static void xhci_reset_endpoint(struct usbd_pipe *); 164 static usbd_status xhci_stop_endpoint_cmd(struct xhci_softc *, 165 struct xhci_slot *, u_int, uint32_t); 166 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 167 168 static void xhci_host_dequeue(struct xhci_ring * const); 169 static void xhci_set_dequeue(struct usbd_pipe *); 170 171 static usbd_status xhci_do_command(struct xhci_softc * const, 172 struct xhci_soft_trb * const, int); 173 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 174 struct xhci_soft_trb * const, int); 175 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 176 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *); 177 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 178 static usbd_status xhci_enable_slot(struct xhci_softc * const, 179 uint8_t * const); 180 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 181 static usbd_status xhci_address_device(struct xhci_softc * const, 182 uint64_t, uint8_t, bool); 183 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 184 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 185 struct xhci_slot * const, u_int); 186 static usbd_status xhci_ring_init(struct xhci_softc * const, 187 struct xhci_ring **, size_t, size_t); 188 static void xhci_ring_free(struct xhci_softc * const, 189 struct xhci_ring ** const); 190 191 static void xhci_setup_ctx(struct usbd_pipe *); 192 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 193 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 194 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 195 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 196 197 static void xhci_noop(struct usbd_pipe *); 198 199 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 200 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 201 static void xhci_root_intr_abort(struct usbd_xfer *); 202 static void xhci_root_intr_close(struct usbd_pipe *); 203 static void xhci_root_intr_done(struct usbd_xfer *); 204 205 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 206 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 207 static void xhci_device_ctrl_abort(struct usbd_xfer *); 208 static void xhci_device_ctrl_close(struct usbd_pipe *); 209 static void xhci_device_ctrl_done(struct usbd_xfer *); 210 211 static usbd_status xhci_device_isoc_transfer(struct usbd_xfer *); 212 static usbd_status xhci_device_isoc_enter(struct usbd_xfer *); 213 static void xhci_device_isoc_abort(struct usbd_xfer *); 214 static void xhci_device_isoc_close(struct usbd_pipe *); 215 static void xhci_device_isoc_done(struct usbd_xfer *); 216 217 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 218 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 219 static void xhci_device_intr_abort(struct usbd_xfer *); 220 static void xhci_device_intr_close(struct usbd_pipe *); 221 static void xhci_device_intr_done(struct usbd_xfer *); 222 223 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 224 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 225 static void xhci_device_bulk_abort(struct usbd_xfer *); 226 static void xhci_device_bulk_close(struct usbd_pipe *); 227 static void xhci_device_bulk_done(struct usbd_xfer *); 228 229 static const struct usbd_bus_methods xhci_bus_methods = { 230 .ubm_open = xhci_open, 231 .ubm_softint = xhci_softintr, 232 .ubm_dopoll = xhci_poll, 233 .ubm_allocx = xhci_allocx, 234 .ubm_freex = xhci_freex, 235 .ubm_abortx = xhci_abortx, 236 .ubm_dying = xhci_dying, 237 .ubm_getlock = xhci_get_lock, 238 .ubm_newdev = xhci_new_device, 239 .ubm_rhctrl = xhci_roothub_ctrl, 240 }; 241 242 static const struct usbd_pipe_methods xhci_root_intr_methods = { 243 .upm_transfer = xhci_root_intr_transfer, 244 .upm_start = xhci_root_intr_start, 245 .upm_abort = xhci_root_intr_abort, 246 .upm_close = xhci_root_intr_close, 247 .upm_cleartoggle = xhci_noop, 248 .upm_done = xhci_root_intr_done, 249 }; 250 251 252 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 253 .upm_transfer = xhci_device_ctrl_transfer, 254 .upm_start = xhci_device_ctrl_start, 255 .upm_abort = xhci_device_ctrl_abort, 256 .upm_close = xhci_device_ctrl_close, 257 .upm_cleartoggle = xhci_noop, 258 .upm_done = xhci_device_ctrl_done, 259 }; 260 261 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 262 .upm_transfer = xhci_device_isoc_transfer, 263 .upm_abort = xhci_device_isoc_abort, 264 .upm_close = xhci_device_isoc_close, 265 .upm_cleartoggle = xhci_noop, 266 .upm_done = xhci_device_isoc_done, 267 }; 268 269 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 270 .upm_transfer = xhci_device_bulk_transfer, 271 .upm_start = xhci_device_bulk_start, 272 .upm_abort = xhci_device_bulk_abort, 273 .upm_close = xhci_device_bulk_close, 274 .upm_cleartoggle = xhci_noop, 275 .upm_done = xhci_device_bulk_done, 276 }; 277 278 static const struct usbd_pipe_methods xhci_device_intr_methods = { 279 .upm_transfer = xhci_device_intr_transfer, 280 .upm_start = xhci_device_intr_start, 281 .upm_abort = xhci_device_intr_abort, 282 .upm_close = xhci_device_intr_close, 283 .upm_cleartoggle = xhci_noop, 284 .upm_done = xhci_device_intr_done, 285 }; 286 287 static inline uint32_t 288 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 289 { 290 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 291 } 292 293 static inline uint32_t 294 xhci_read_2(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, offset); 297 } 298 299 static inline uint32_t 300 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 301 { 302 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 303 } 304 305 static inline void 306 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 307 uint32_t value) 308 { 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 310 } 311 312 #if 0 /* unused */ 313 static inline void 314 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 315 uint32_t value) 316 { 317 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 318 } 319 #endif /* unused */ 320 321 static inline void 322 xhci_barrier(const struct xhci_softc * const sc, int flags) 323 { 324 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_ios, flags); 325 } 326 327 static inline uint32_t 328 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 329 { 330 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 331 } 332 333 static inline uint32_t 334 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 335 { 336 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 337 } 338 339 static inline void 340 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 341 uint32_t value) 342 { 343 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 344 } 345 346 static inline uint64_t 347 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 #ifdef XHCI_USE_BUS_SPACE_8 352 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 353 #else 354 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 355 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 356 offset + 4) << 32; 357 #endif 358 359 return value; 360 } 361 362 static inline void 363 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 364 uint64_t value) 365 { 366 #ifdef XHCI_USE_BUS_SPACE_8 367 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 368 #else 369 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 370 (value >> 0) & 0xffffffff); 371 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 372 (value >> 32) & 0xffffffff); 373 #endif 374 } 375 376 static inline uint32_t 377 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 378 { 379 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 380 } 381 382 static inline void 383 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 384 uint32_t value) 385 { 386 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 387 } 388 389 static inline uint64_t 390 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 391 { 392 uint64_t value; 393 394 #ifdef XHCI_USE_BUS_SPACE_8 395 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 396 #else 397 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 398 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 399 offset + 4) << 32; 400 #endif 401 402 return value; 403 } 404 405 static inline void 406 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 407 uint64_t value) 408 { 409 #ifdef XHCI_USE_BUS_SPACE_8 410 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 411 #else 412 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 413 (value >> 0) & 0xffffffff); 414 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 415 (value >> 32) & 0xffffffff); 416 #endif 417 } 418 419 #if 0 /* unused */ 420 static inline uint32_t 421 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 422 { 423 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 424 } 425 #endif /* unused */ 426 427 static inline void 428 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 429 uint32_t value) 430 { 431 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 432 } 433 434 /* --- */ 435 436 static inline uint8_t 437 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 438 { 439 u_int eptype = 0; 440 441 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 442 case UE_CONTROL: 443 eptype = 0x0; 444 break; 445 case UE_ISOCHRONOUS: 446 eptype = 0x1; 447 break; 448 case UE_BULK: 449 eptype = 0x2; 450 break; 451 case UE_INTERRUPT: 452 eptype = 0x3; 453 break; 454 } 455 456 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 457 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 458 return eptype | 0x4; 459 else 460 return eptype; 461 } 462 463 static u_int 464 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 465 { 466 /* xHCI 1.0 section 4.5.1 */ 467 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 468 u_int in = 0; 469 470 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 471 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 472 in = 1; 473 474 return epaddr * 2 + in; 475 } 476 477 static inline u_int 478 xhci_dci_to_ici(const u_int i) 479 { 480 return i + 1; 481 } 482 483 static inline void * 484 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 485 const u_int dci) 486 { 487 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 488 } 489 490 #if 0 /* unused */ 491 static inline bus_addr_t 492 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 493 const u_int dci) 494 { 495 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 496 } 497 #endif /* unused */ 498 499 static inline void * 500 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 501 const u_int ici) 502 { 503 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 504 } 505 506 static inline bus_addr_t 507 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 508 const u_int ici) 509 { 510 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 511 } 512 513 static inline struct xhci_trb * 514 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 515 { 516 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 517 } 518 519 static inline bus_addr_t 520 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 521 { 522 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 523 } 524 525 static inline void 526 xhci_xfer_put_trb(struct xhci_xfer * const xx, u_int idx, 527 uint64_t parameter, uint32_t status, uint32_t control) 528 { 529 KASSERTMSG(idx < xx->xx_ntrb, "idx=%u xx_ntrb=%u", idx, xx->xx_ntrb); 530 xx->xx_trb[idx].trb_0 = parameter; 531 xx->xx_trb[idx].trb_2 = status; 532 xx->xx_trb[idx].trb_3 = control; 533 } 534 535 static inline void 536 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 537 uint32_t control) 538 { 539 trb->trb_0 = htole64(parameter); 540 trb->trb_2 = htole32(status); 541 trb->trb_3 = htole32(control); 542 } 543 544 static int 545 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 546 { 547 /* base address of TRBs */ 548 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 549 550 /* trb_0 range sanity check */ 551 if (trb_0 == 0 || trb_0 < trbp || 552 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 553 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 554 return 1; 555 } 556 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 557 return 0; 558 } 559 560 static unsigned int 561 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 562 u_int dci) 563 { 564 uint32_t *cp; 565 566 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 567 cp = xhci_slot_get_dcv(sc, xs, dci); 568 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 569 } 570 571 static inline unsigned int 572 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 573 { 574 const unsigned int port = ctlrport - 1; 575 const uint8_t bit = __BIT(port % NBBY); 576 577 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 578 } 579 580 /* 581 * Return the roothub port for a controller port. Both are 1..n. 582 */ 583 static inline unsigned int 584 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 585 { 586 587 return sc->sc_ctlrportmap[ctrlport - 1]; 588 } 589 590 /* 591 * Return the controller port for a bus roothub port. Both are 1..n. 592 */ 593 static inline unsigned int 594 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 595 unsigned int rhport) 596 { 597 598 return sc->sc_rhportmap[bn][rhport - 1]; 599 } 600 601 /* --- */ 602 603 void 604 xhci_childdet(device_t self, device_t child) 605 { 606 struct xhci_softc * const sc = device_private(self); 607 608 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 609 if (child == sc->sc_child2) 610 sc->sc_child2 = NULL; 611 else if (child == sc->sc_child) 612 sc->sc_child = NULL; 613 } 614 615 int 616 xhci_detach(struct xhci_softc *sc, int flags) 617 { 618 int rv = 0; 619 620 if (sc->sc_child2 != NULL) { 621 rv = config_detach(sc->sc_child2, flags); 622 if (rv != 0) 623 return rv; 624 KASSERT(sc->sc_child2 == NULL); 625 } 626 627 if (sc->sc_child != NULL) { 628 rv = config_detach(sc->sc_child, flags); 629 if (rv != 0) 630 return rv; 631 KASSERT(sc->sc_child == NULL); 632 } 633 634 /* XXX unconfigure/free slots */ 635 636 /* verify: */ 637 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 638 xhci_op_write_4(sc, XHCI_USBCMD, 0); 639 /* do we need to wait for stop? */ 640 641 xhci_op_write_8(sc, XHCI_CRCR, 0); 642 xhci_ring_free(sc, &sc->sc_cr); 643 cv_destroy(&sc->sc_command_cv); 644 cv_destroy(&sc->sc_cmdbusy_cv); 645 646 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 647 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 648 xhci_rt_write_8(sc, XHCI_ERDP(0), 0 | XHCI_ERDP_BUSY); 649 xhci_ring_free(sc, &sc->sc_er); 650 651 usb_freemem(&sc->sc_eventst_dma); 652 653 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 654 usb_freemem(&sc->sc_dcbaa_dma); 655 656 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 657 658 kmem_free(sc->sc_ctlrportbus, 659 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 660 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 661 662 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 663 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 664 } 665 666 mutex_destroy(&sc->sc_rhlock); 667 mutex_destroy(&sc->sc_lock); 668 mutex_destroy(&sc->sc_intr_lock); 669 670 pool_cache_destroy(sc->sc_xferpool); 671 672 return rv; 673 } 674 675 int 676 xhci_activate(device_t self, enum devact act) 677 { 678 struct xhci_softc * const sc = device_private(self); 679 680 switch (act) { 681 case DVACT_DEACTIVATE: 682 sc->sc_dying = true; 683 return 0; 684 default: 685 return EOPNOTSUPP; 686 } 687 } 688 689 bool 690 xhci_suspend(device_t self, const pmf_qual_t *qual) 691 { 692 struct xhci_softc * const sc = device_private(self); 693 size_t i, j, bn, dci; 694 int port; 695 uint32_t v; 696 usbd_status err; 697 bool ok = false; 698 699 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 700 701 /* 702 * Block issuance of new commands, and wait for all pending 703 * commands to complete. 704 */ 705 mutex_enter(&sc->sc_lock); 706 KASSERT(sc->sc_suspender == NULL); 707 sc->sc_suspender = curlwp; 708 while (sc->sc_command_addr != 0) 709 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 710 mutex_exit(&sc->sc_lock); 711 712 /* 713 * Block roothub xfers which might touch portsc registers until 714 * we're done suspending. 715 */ 716 mutex_enter(&sc->sc_rhlock); 717 718 /* 719 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 720 * xHCI Power Management, p. 342 721 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=342 722 */ 723 724 /* 725 * `1. Stop all USB activity by issuing Stop Endpoint Commands 726 * for Busy endpoints in the Running state. If the Force 727 * Save Context Capability (FSC = ``0'') is not supported, 728 * then Stop Endpoint Commands shall be issued for all idle 729 * endpoints in the Running state as well. The Stop 730 * Endpoint Command causes the xHC to update the respective 731 * Endpoint or Stream Contexts in system memory, e.g. the 732 * TR Dequeue Pointer, DCS, etc. fields. Refer to 733 * Implementation Note "0".' 734 */ 735 for (i = 0; i < sc->sc_maxslots; i++) { 736 struct xhci_slot *xs = &sc->sc_slots[i]; 737 738 /* Skip if the slot is not in use. */ 739 if (xs->xs_idx == 0) 740 continue; 741 742 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 743 /* Skip if the endpoint is not Running. */ 744 /* XXX What about Busy? */ 745 if (xhci_get_epstate(sc, xs, dci) != 746 XHCI_EPSTATE_RUNNING) 747 continue; 748 749 /* Stop endpoint. */ 750 mutex_enter(&sc->sc_lock); 751 err = xhci_stop_endpoint_cmd(sc, xs, dci, 752 XHCI_TRB_3_SUSP_EP_BIT); 753 mutex_exit(&sc->sc_lock); 754 if (err) { 755 device_printf(self, "failed to stop endpoint" 756 " slot %zu dci %zu err %d\n", 757 i, dci, err); 758 goto out; 759 } 760 } 761 } 762 763 /* 764 * Next, suspend all the ports: 765 * 766 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.15: 767 * Suspend-Resume, pp. 276-283 768 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=276 769 */ 770 for (bn = 0; bn < 2; bn++) { 771 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 772 /* 4.15.1: Port Suspend. */ 773 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 774 775 /* 776 * `System software places individual ports 777 * into suspend mode by writing a ``3'' into 778 * the appropriate PORTSC register Port Link 779 * State (PLS) field (refer to Section 5.4.8). 780 * Software should only set the PLS field to 781 * ``3'' when the port is in the Enabled 782 * state.' 783 * 784 * `Software should not attempt to suspend a 785 * port unless the port reports that it is in 786 * the enabled (PED = ``1''; PLS < ``3'') 787 * state (refer to Section 5.4.8 for more 788 * information about PED and PLS).' 789 */ 790 v = xhci_op_read_4(sc, port); 791 if (((v & XHCI_PS_PED) == 0) || 792 XHCI_PS_PLS_GET(v) >= XHCI_PS_PLS_U3) 793 continue; 794 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 795 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU3); 796 xhci_op_write_4(sc, port, v); 797 798 /* 799 * `When the PLS field is written with U3 800 * (``3''), the status of the PLS bit will not 801 * change to the target U state U3 until the 802 * suspend signaling has completed to the 803 * attached device (which may be as long as 804 * 10ms.).' 805 * 806 * `Software is required to wait for U3 807 * transitions to complete before it puts the 808 * xHC into a low power state, and before 809 * resuming the port.' 810 * 811 * XXX Take advantage of the technique to 812 * reduce polling on host controllers that 813 * support the U3C capability. 814 */ 815 for (j = 0; j < XHCI_WAIT_PLS_U3; j++) { 816 v = xhci_op_read_4(sc, port); 817 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U3) 818 break; 819 usb_delay_ms(&sc->sc_bus, 1); 820 } 821 if (j == XHCI_WAIT_PLS_U3) { 822 device_printf(self, 823 "suspend timeout on bus %zu port %zu\n", 824 bn, i); 825 goto out; 826 } 827 } 828 } 829 830 /* 831 * `2. Ensure that the Command Ring is in the Stopped state 832 * (CRR = ``0'') or Idle (i.e. the Command Transfer Ring is 833 * empty), and all Command Completion Events associated 834 * with them have been received.' 835 * 836 * XXX 837 */ 838 839 /* `3. Stop the controller by setting Run/Stop (R/S) = ``0''.' */ 840 xhci_op_write_4(sc, XHCI_USBCMD, 841 xhci_op_read_4(sc, XHCI_USBCMD) & ~XHCI_CMD_RS); 842 843 /* 844 * `4. Read the Operational Runtime, and VTIO registers in the 845 * following order: USBCMD, DNCTRL, DCBAAP, CONFIG, ERSTSZ, 846 * ERSTBA, ERDP, IMAN, IMOD, and VTIO and save their 847 * state.' 848 * 849 * (We don't use VTIO here (XXX for now?).) 850 */ 851 sc->sc_regs.usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 852 sc->sc_regs.dnctrl = xhci_op_read_4(sc, XHCI_DNCTRL); 853 sc->sc_regs.dcbaap = xhci_op_read_8(sc, XHCI_DCBAAP); 854 sc->sc_regs.config = xhci_op_read_4(sc, XHCI_CONFIG); 855 sc->sc_regs.erstsz0 = xhci_rt_read_4(sc, XHCI_ERSTSZ(0)); 856 sc->sc_regs.erstba0 = xhci_rt_read_8(sc, XHCI_ERSTBA(0)); 857 sc->sc_regs.erdp0 = xhci_rt_read_8(sc, XHCI_ERDP(0)); 858 sc->sc_regs.iman0 = xhci_rt_read_4(sc, XHCI_IMAN(0)); 859 sc->sc_regs.imod0 = xhci_rt_read_4(sc, XHCI_IMOD(0)); 860 861 /* 862 * `5. Set the Controller Save State (CSS) flag in the USBCMD 863 * register (5.4.1)...' 864 */ 865 xhci_op_write_4(sc, XHCI_USBCMD, 866 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CSS); 867 868 /* 869 * `...and wait for the Save State Status (SSS) flag in the 870 * USBSTS register (5.4.2) to transition to ``0''.' 871 */ 872 for (i = 0; i < XHCI_WAIT_SSS; i++) { 873 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SSS) == 0) 874 break; 875 usb_delay_ms(&sc->sc_bus, 1); 876 } 877 if (i >= XHCI_WAIT_SSS) { 878 device_printf(self, "suspend timeout, USBSTS.SSS\n"); 879 /* 880 * Just optimistically go on and check SRE anyway -- 881 * what's the worst that could happen? 882 */ 883 } 884 885 /* 886 * `Note: After a Save or Restore operation completes, the 887 * Save/Restore Error (SRE) flag in the USBSTS register should 888 * be checked to ensure that the operation completed 889 * successfully.' 890 */ 891 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 892 device_printf(self, "suspend error, USBSTS.SRE\n"); 893 goto out; 894 } 895 896 /* Success! */ 897 ok = true; 898 899 out: mutex_exit(&sc->sc_rhlock); 900 if (!ok) { 901 /* 902 * If suspend failed, resume command issuance. 903 */ 904 mutex_enter(&sc->sc_lock); 905 KASSERT(sc->sc_suspender == curlwp); 906 sc->sc_suspender = NULL; 907 cv_broadcast(&sc->sc_cmdbusy_cv); 908 mutex_exit(&sc->sc_lock); 909 } 910 return ok; 911 } 912 913 bool 914 xhci_resume(device_t self, const pmf_qual_t *qual) 915 { 916 struct xhci_softc * const sc = device_private(self); 917 size_t i, j, bn, dci; 918 int port; 919 uint32_t v; 920 bool ok = false; 921 922 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 923 924 KASSERT(sc->sc_suspender); 925 926 /* 927 * Block roothub xfers which might touch portsc registers until 928 * we're done resuming. 929 */ 930 mutex_enter(&sc->sc_rhlock); 931 932 /* 933 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 934 * xHCI Power Management, p. 343 935 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=343 936 */ 937 938 /* 939 * `4. Restore the Operational Runtime, and VTIO registers with 940 * their previously saved state in the following order: 941 * DNCTRL, DCBAAP, CONFIG, ERSTSZ, ERSTBA, ERDP, IMAN, 942 * IMOD, and VTIO.' 943 * 944 * (We don't use VTIO here (for now?).) 945 */ 946 xhci_op_write_4(sc, XHCI_USBCMD, sc->sc_regs.usbcmd); 947 xhci_op_write_4(sc, XHCI_DNCTRL, sc->sc_regs.dnctrl); 948 xhci_op_write_8(sc, XHCI_DCBAAP, sc->sc_regs.dcbaap); 949 xhci_op_write_4(sc, XHCI_CONFIG, sc->sc_regs.config); 950 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), sc->sc_regs.erstsz0); 951 xhci_rt_write_8(sc, XHCI_ERSTBA(0), sc->sc_regs.erstba0); 952 xhci_rt_write_8(sc, XHCI_ERDP(0), sc->sc_regs.erdp0); 953 xhci_rt_write_4(sc, XHCI_IMAN(0), sc->sc_regs.iman0); 954 xhci_rt_write_4(sc, XHCI_IMOD(0), sc->sc_regs.imod0); 955 956 memset(&sc->sc_regs, 0, sizeof(sc->sc_regs)); /* paranoia */ 957 958 /* 959 * `5. Set the Controller Restore State (CRS) flag in the 960 * USBCMD register (5.4.1) to ``1''...' 961 */ 962 xhci_op_write_4(sc, XHCI_USBCMD, 963 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CRS); 964 965 /* 966 * `...and wait for the Restore State Status (RSS) in the 967 * USBSTS register (5.4.2) to transition to ``0''.' 968 */ 969 for (i = 0; i < XHCI_WAIT_RSS; i++) { 970 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_RSS) == 0) 971 break; 972 usb_delay_ms(&sc->sc_bus, 1); 973 } 974 if (i >= XHCI_WAIT_RSS) { 975 device_printf(self, "resume timeout, USBSTS.RSS\n"); 976 goto out; 977 } 978 979 /* 980 * `6. Reinitialize the Command Ring, i.e. so its Cycle bits 981 * are consistent with the RCS values to be written to the 982 * CRCR.' 983 * 984 * XXX Hope just zeroing it is good enough! 985 */ 986 xhci_host_dequeue(sc->sc_cr); 987 988 /* 989 * `7. Write the CRCR with the address and RCS value of the 990 * reinitialized Command Ring. Note that this write will 991 * cause the Command Ring to restart at the address 992 * specified by the CRCR.' 993 */ 994 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) | 995 sc->sc_cr->xr_cs); 996 997 /* 998 * `8. Enable the controller by setting Run/Stop (R/S) = 999 * ``1''.' 1000 */ 1001 xhci_op_write_4(sc, XHCI_USBCMD, 1002 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_RS); 1003 1004 /* 1005 * `9. Software shall walk the USB topology and initialize each 1006 * of the xHC PORTSC, PORTPMSC, and PORTLI registers, and 1007 * external hub ports attached to USB devices.' 1008 * 1009 * This follows the procedure in 4.15 `Suspend-Resume', 4.15.2 1010 * `Port Resume', 4.15.2.2 `Host Initiated'. 1011 * 1012 * XXX We should maybe batch up initiating the state 1013 * transitions, and then wait for them to complete all at once. 1014 */ 1015 for (bn = 0; bn < 2; bn++) { 1016 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 1017 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 1018 1019 /* `When a port is in the U3 state: ...' */ 1020 v = xhci_op_read_4(sc, port); 1021 if (XHCI_PS_PLS_GET(v) != XHCI_PS_PLS_U3) 1022 continue; 1023 1024 /* 1025 * `For a USB2 protocol port, software shall 1026 * write a ``15'' (Resume) to the PLS field to 1027 * initiate resume signaling. The port shall 1028 * transition to the Resume substate and the 1029 * xHC shall transmit the resume signaling 1030 * within 1ms (T_URSM). Software shall ensure 1031 * that resume is signaled for at least 20ms 1032 * (T_DRSMDN). Software shall start timing 1033 * T_DRSMDN from the write of ``15'' (Resume) 1034 * to PLS.' 1035 */ 1036 if (bn == 1) { 1037 KASSERT(sc->sc_bus2.ub_revision == USBREV_2_0); 1038 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1039 v |= XHCI_PS_LWS; 1040 v |= XHCI_PS_PLS_SET(XHCI_PS_PLS_SETRESUME); 1041 xhci_op_write_4(sc, port, v); 1042 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1043 } else { 1044 KASSERT(sc->sc_bus.ub_revision > USBREV_2_0); 1045 } 1046 1047 /* 1048 * `For a USB3 protocol port [and a USB2 1049 * protocol port after transitioning to 1050 * Resume], software shall write a ``0'' (U0) 1051 * to the PLS field...' 1052 */ 1053 v = xhci_op_read_4(sc, port); 1054 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1055 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU0); 1056 xhci_op_write_4(sc, port, v); 1057 1058 for (j = 0; j < XHCI_WAIT_PLS_U0; j++) { 1059 v = xhci_op_read_4(sc, port); 1060 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U0) 1061 break; 1062 usb_delay_ms(&sc->sc_bus, 1); 1063 } 1064 if (j == XHCI_WAIT_PLS_U0) { 1065 device_printf(self, 1066 "resume timeout on bus %zu port %zu\n", 1067 bn, i); 1068 goto out; 1069 } 1070 } 1071 } 1072 1073 /* 1074 * `10. Restart each of the previously Running endpoints by 1075 * ringing their doorbells.' 1076 */ 1077 for (i = 0; i < sc->sc_maxslots; i++) { 1078 struct xhci_slot *xs = &sc->sc_slots[i]; 1079 1080 /* Skip if the slot is not in use. */ 1081 if (xs->xs_idx == 0) 1082 continue; 1083 1084 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 1085 /* Skip if the endpoint is not Running. */ 1086 if (xhci_get_epstate(sc, xs, dci) != 1087 XHCI_EPSTATE_RUNNING) 1088 continue; 1089 1090 /* Ring the doorbell. */ 1091 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 1092 } 1093 } 1094 1095 /* 1096 * `Note: After a Save or Restore operation completes, the 1097 * Save/Restore Error (SRE) flag in the USBSTS register should 1098 * be checked to ensure that the operation completed 1099 * successfully.' 1100 */ 1101 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 1102 device_printf(self, "resume error, USBSTS.SRE\n"); 1103 goto out; 1104 } 1105 1106 /* Resume command issuance. */ 1107 mutex_enter(&sc->sc_lock); 1108 KASSERT(sc->sc_suspender); 1109 sc->sc_suspender = NULL; 1110 cv_broadcast(&sc->sc_cmdbusy_cv); 1111 mutex_exit(&sc->sc_lock); 1112 1113 /* Success! */ 1114 ok = true; 1115 1116 out: mutex_exit(&sc->sc_rhlock); 1117 return ok; 1118 } 1119 1120 bool 1121 xhci_shutdown(device_t self, int flags) 1122 { 1123 return false; 1124 } 1125 1126 static int 1127 xhci_hc_reset(struct xhci_softc * const sc) 1128 { 1129 uint32_t usbcmd, usbsts; 1130 int i; 1131 1132 /* Check controller not ready */ 1133 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1134 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1135 if ((usbsts & XHCI_STS_CNR) == 0) 1136 break; 1137 usb_delay_ms(&sc->sc_bus, 1); 1138 } 1139 if (i >= XHCI_WAIT_CNR) { 1140 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 1141 return EIO; 1142 } 1143 1144 /* Halt controller */ 1145 usbcmd = 0; 1146 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1147 usb_delay_ms(&sc->sc_bus, 1); 1148 1149 /* Reset controller */ 1150 usbcmd = XHCI_CMD_HCRST; 1151 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1152 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 1153 /* 1154 * Wait 1ms first. Existing Intel xHCI requires 1ms delay to 1155 * prevent system hang (Errata). 1156 */ 1157 usb_delay_ms(&sc->sc_bus, 1); 1158 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 1159 if ((usbcmd & XHCI_CMD_HCRST) == 0) 1160 break; 1161 } 1162 if (i >= XHCI_WAIT_HCRST) { 1163 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 1164 return EIO; 1165 } 1166 1167 /* Check controller not ready */ 1168 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1169 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1170 if ((usbsts & XHCI_STS_CNR) == 0) 1171 break; 1172 usb_delay_ms(&sc->sc_bus, 1); 1173 } 1174 if (i >= XHCI_WAIT_CNR) { 1175 aprint_error_dev(sc->sc_dev, 1176 "controller not ready timeout after reset\n"); 1177 return EIO; 1178 } 1179 1180 return 0; 1181 } 1182 1183 /* 7.2 xHCI Support Protocol Capability */ 1184 static void 1185 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 1186 { 1187 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1188 1189 /* XXX Cache this lot */ 1190 1191 const uint32_t w0 = xhci_read_4(sc, ecp); 1192 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 1193 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 1194 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 1195 1196 aprint_debug_dev(sc->sc_dev, 1197 " SP: 0x%08x 0x%08x 0x%08x 0x%08x\n", w0, w4, w8, wc); 1198 1199 if (w4 != XHCI_XECP_USBID) 1200 return; 1201 1202 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 1203 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 1204 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 1205 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 1206 1207 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 1208 switch (mm) { 1209 case 0x0200: 1210 case 0x0300: 1211 case 0x0301: 1212 case 0x0310: 1213 case 0x0320: 1214 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 1215 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 1216 break; 1217 default: 1218 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 1219 major, minor); 1220 return; 1221 } 1222 1223 const size_t bus = (major == 3) ? 0 : 1; 1224 1225 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 1226 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 1227 if (sc->sc_ctlrportmap[cp] != 0) { 1228 aprint_error_dev(sc->sc_dev, "controller port %zu " 1229 "already assigned", cp); 1230 continue; 1231 } 1232 1233 sc->sc_ctlrportbus[cp / NBBY] |= 1234 bus == 0 ? 0 : __BIT(cp % NBBY); 1235 1236 const size_t rhp = sc->sc_rhportcount[bus]++; 1237 1238 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 1239 "bus %zu rhp %zu is %d", bus, rhp, 1240 sc->sc_rhportmap[bus][rhp]); 1241 1242 sc->sc_rhportmap[bus][rhp] = cp + 1; 1243 sc->sc_ctlrportmap[cp] = rhp + 1; 1244 } 1245 } 1246 1247 /* Process extended capabilities */ 1248 static void 1249 xhci_ecp(struct xhci_softc *sc) 1250 { 1251 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1252 1253 bus_size_t ecp = XHCI_HCC_XECP(sc->sc_hcc) * 4; 1254 while (ecp != 0) { 1255 uint32_t ecr = xhci_read_4(sc, ecp); 1256 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 1257 switch (XHCI_XECP_ID(ecr)) { 1258 case XHCI_ID_PROTOCOLS: { 1259 xhci_id_protocols(sc, ecp); 1260 break; 1261 } 1262 case XHCI_ID_USB_LEGACY: { 1263 uint8_t bios_sem; 1264 1265 /* Take host controller ownership from BIOS */ 1266 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 1267 if (bios_sem) { 1268 /* sets xHCI to be owned by OS */ 1269 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 1270 aprint_debug_dev(sc->sc_dev, 1271 "waiting for BIOS to give up control\n"); 1272 for (int i = 0; i < 5000; i++) { 1273 bios_sem = xhci_read_1(sc, ecp + 1274 XHCI_XECP_BIOS_SEM); 1275 if (bios_sem == 0) 1276 break; 1277 DELAY(1000); 1278 } 1279 if (bios_sem) { 1280 aprint_error_dev(sc->sc_dev, 1281 "timed out waiting for BIOS\n"); 1282 } 1283 } 1284 break; 1285 } 1286 default: 1287 break; 1288 } 1289 ecr = xhci_read_4(sc, ecp); 1290 if (XHCI_XECP_NEXT(ecr) == 0) { 1291 ecp = 0; 1292 } else { 1293 ecp += XHCI_XECP_NEXT(ecr) * 4; 1294 } 1295 } 1296 } 1297 1298 #define XHCI_HCCPREV1_BITS \ 1299 "\177\020" /* New bitmask */ \ 1300 "f\020\020XECP\0" \ 1301 "f\014\4MAXPSA\0" \ 1302 "b\013CFC\0" \ 1303 "b\012SEC\0" \ 1304 "b\011SBD\0" \ 1305 "b\010FSE\0" \ 1306 "b\7NSS\0" \ 1307 "b\6LTC\0" \ 1308 "b\5LHRC\0" \ 1309 "b\4PIND\0" \ 1310 "b\3PPC\0" \ 1311 "b\2CZC\0" \ 1312 "b\1BNC\0" \ 1313 "b\0AC64\0" \ 1314 "\0" 1315 #define XHCI_HCCV1_x_BITS \ 1316 "\177\020" /* New bitmask */ \ 1317 "f\020\020XECP\0" \ 1318 "f\014\4MAXPSA\0" \ 1319 "b\013CFC\0" \ 1320 "b\012SEC\0" \ 1321 "b\011SPC\0" \ 1322 "b\010PAE\0" \ 1323 "b\7NSS\0" \ 1324 "b\6LTC\0" \ 1325 "b\5LHRC\0" \ 1326 "b\4PIND\0" \ 1327 "b\3PPC\0" \ 1328 "b\2CSZ\0" \ 1329 "b\1BNC\0" \ 1330 "b\0AC64\0" \ 1331 "\0" 1332 1333 #define XHCI_HCC2_BITS \ 1334 "\177\020" /* New bitmask */ \ 1335 "b\7ETC_TSC\0" \ 1336 "b\6ETC\0" \ 1337 "b\5CIC\0" \ 1338 "b\4LEC\0" \ 1339 "b\3CTC\0" \ 1340 "b\2FSC\0" \ 1341 "b\1CMC\0" \ 1342 "b\0U3C\0" \ 1343 "\0" 1344 1345 void 1346 xhci_start(struct xhci_softc *sc) 1347 { 1348 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1349 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1350 /* Intel xhci needs interrupt rate moderated. */ 1351 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1352 else 1353 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1354 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1355 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1356 1357 /* Go! */ 1358 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 1359 aprint_debug_dev(sc->sc_dev, "USBCMD 0x%08"PRIx32"\n", 1360 xhci_op_read_4(sc, XHCI_USBCMD)); 1361 } 1362 1363 int 1364 xhci_init(struct xhci_softc *sc) 1365 { 1366 bus_size_t bsz; 1367 uint32_t hcs1, hcs2, hcs3, dboff, rtsoff; 1368 uint32_t pagesize, config; 1369 int i = 0; 1370 uint16_t hciversion; 1371 uint8_t caplength; 1372 1373 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1374 1375 /* Set up the bus struct for the usb 3 and usb 2 buses */ 1376 sc->sc_bus.ub_methods = &xhci_bus_methods; 1377 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1378 sc->sc_bus.ub_usedma = true; 1379 sc->sc_bus.ub_hcpriv = sc; 1380 1381 sc->sc_bus2.ub_methods = &xhci_bus_methods; 1382 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 1383 sc->sc_bus2.ub_revision = USBREV_2_0; 1384 sc->sc_bus2.ub_usedma = true; 1385 sc->sc_bus2.ub_hcpriv = sc; 1386 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 1387 1388 caplength = xhci_read_1(sc, XHCI_CAPLENGTH); 1389 hciversion = xhci_read_2(sc, XHCI_HCIVERSION); 1390 1391 if (hciversion < XHCI_HCIVERSION_0_96 || 1392 hciversion >= 0x0200) { 1393 aprint_normal_dev(sc->sc_dev, 1394 "xHCI version %x.%x not known to be supported\n", 1395 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1396 } else { 1397 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 1398 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1399 } 1400 1401 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 1402 &sc->sc_cbh) != 0) { 1403 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 1404 return ENOMEM; 1405 } 1406 1407 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 1408 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 1409 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 1410 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 1411 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 1412 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 1413 aprint_debug_dev(sc->sc_dev, 1414 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 1415 1416 sc->sc_hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 1417 sc->sc_ctxsz = XHCI_HCC_CSZ(sc->sc_hcc) ? 64 : 32; 1418 1419 char sbuf[128]; 1420 if (hciversion < XHCI_HCIVERSION_1_0) 1421 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, sc->sc_hcc); 1422 else 1423 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, sc->sc_hcc); 1424 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 1425 aprint_debug_dev(sc->sc_dev, "xECP %" __PRIxBITS "\n", 1426 XHCI_HCC_XECP(sc->sc_hcc) * 4); 1427 if (hciversion >= XHCI_HCIVERSION_1_1) { 1428 sc->sc_hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 1429 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, sc->sc_hcc2); 1430 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 1431 } 1432 1433 /* default all ports to bus 0, i.e. usb 3 */ 1434 sc->sc_ctlrportbus = kmem_zalloc( 1435 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 1436 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1437 1438 /* controller port to bus roothub port map */ 1439 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 1440 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1441 } 1442 1443 /* 1444 * Process all Extended Capabilities 1445 */ 1446 xhci_ecp(sc); 1447 1448 bsz = XHCI_PORTSC(sc->sc_maxports); 1449 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1450 &sc->sc_obh) != 0) { 1451 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1452 return ENOMEM; 1453 } 1454 1455 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1456 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1457 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1458 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1459 return ENOMEM; 1460 } 1461 1462 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1463 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1464 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1465 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1466 return ENOMEM; 1467 } 1468 1469 int rv; 1470 rv = xhci_hc_reset(sc); 1471 if (rv != 0) { 1472 return rv; 1473 } 1474 1475 if (sc->sc_vendor_init) 1476 sc->sc_vendor_init(sc); 1477 1478 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1479 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1480 pagesize = ffs(pagesize); 1481 if (pagesize == 0) { 1482 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1483 return EIO; 1484 } 1485 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1486 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1487 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1488 (uint32_t)sc->sc_maxslots); 1489 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1490 1491 int err; 1492 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1493 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1494 if (sc->sc_maxspbuf != 0) { 1495 err = usb_allocmem(sc->sc_bus.ub_dmatag, 1496 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1497 USBMALLOC_COHERENT | USBMALLOC_ZERO, 1498 &sc->sc_spbufarray_dma); 1499 if (err) { 1500 aprint_error_dev(sc->sc_dev, 1501 "spbufarray init fail, err %d\n", err); 1502 return ENOMEM; 1503 } 1504 1505 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1506 sc->sc_maxspbuf, KM_SLEEP); 1507 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1508 for (i = 0; i < sc->sc_maxspbuf; i++) { 1509 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1510 /* allocate contexts */ 1511 err = usb_allocmem(sc->sc_bus.ub_dmatag, sc->sc_pgsz, 1512 sc->sc_pgsz, USBMALLOC_COHERENT | USBMALLOC_ZERO, 1513 dma); 1514 if (err) { 1515 aprint_error_dev(sc->sc_dev, 1516 "spbufarray_dma init fail, err %d\n", err); 1517 rv = ENOMEM; 1518 goto bad1; 1519 } 1520 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1521 usb_syncmem(dma, 0, sc->sc_pgsz, 1522 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1523 } 1524 1525 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1526 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1527 } 1528 1529 config = xhci_op_read_4(sc, XHCI_CONFIG); 1530 config &= ~0xFF; 1531 config |= sc->sc_maxslots & 0xFF; 1532 xhci_op_write_4(sc, XHCI_CONFIG, config); 1533 1534 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1535 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1536 if (err) { 1537 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1538 err); 1539 rv = ENOMEM; 1540 goto bad1; 1541 } 1542 1543 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1544 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1545 if (err) { 1546 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1547 err); 1548 rv = ENOMEM; 1549 goto bad2; 1550 } 1551 1552 usb_dma_t *dma; 1553 size_t size; 1554 size_t align; 1555 1556 dma = &sc->sc_eventst_dma; 1557 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1558 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1559 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1560 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1561 err = usb_allocmem(sc->sc_bus.ub_dmatag, size, align, 1562 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma); 1563 if (err) { 1564 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1565 err); 1566 rv = ENOMEM; 1567 goto bad3; 1568 } 1569 1570 aprint_debug_dev(sc->sc_dev, "eventst: 0x%016jx %p %zx\n", 1571 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1572 KERNADDR(&sc->sc_eventst_dma, 0), 1573 sc->sc_eventst_dma.udma_block->size); 1574 1575 dma = &sc->sc_dcbaa_dma; 1576 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1577 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1578 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1579 err = usb_allocmem(sc->sc_bus.ub_dmatag, size, align, 1580 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma); 1581 if (err) { 1582 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1583 rv = ENOMEM; 1584 goto bad4; 1585 } 1586 aprint_debug_dev(sc->sc_dev, "dcbaa: 0x%016jx %p %zx\n", 1587 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1588 KERNADDR(&sc->sc_dcbaa_dma, 0), 1589 sc->sc_dcbaa_dma.udma_block->size); 1590 1591 if (sc->sc_maxspbuf != 0) { 1592 /* 1593 * DCBA entry 0 hold the scratchbuf array pointer. 1594 */ 1595 *(uint64_t *)KERNADDR(dma, 0) = 1596 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1597 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1598 } 1599 1600 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1601 KM_SLEEP); 1602 if (sc->sc_slots == NULL) { 1603 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1604 rv = ENOMEM; 1605 goto bad; 1606 } 1607 1608 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1609 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1610 if (sc->sc_xferpool == NULL) { 1611 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1612 err); 1613 rv = ENOMEM; 1614 goto bad; 1615 } 1616 1617 cv_init(&sc->sc_command_cv, "xhcicmd"); 1618 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1619 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 1620 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1621 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1622 1623 struct xhci_erste *erst; 1624 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1625 erst[0].erste_0 = htole64(xhci_ring_trbp(sc->sc_er, 0)); 1626 erst[0].erste_2 = htole32(sc->sc_er->xr_ntrb); 1627 erst[0].erste_3 = htole32(0); 1628 usb_syncmem(&sc->sc_eventst_dma, 0, 1629 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1630 1631 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1632 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1633 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(sc->sc_er, 0) | 1634 XHCI_ERDP_BUSY); 1635 1636 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1637 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) | 1638 sc->sc_cr->xr_cs); 1639 1640 xhci_barrier(sc, BUS_SPACE_BARRIER_WRITE); 1641 1642 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1643 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1644 1645 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1646 xhci_start(sc); 1647 1648 return 0; 1649 1650 bad: 1651 if (sc->sc_xferpool) { 1652 pool_cache_destroy(sc->sc_xferpool); 1653 sc->sc_xferpool = NULL; 1654 } 1655 1656 if (sc->sc_slots) { 1657 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1658 sc->sc_maxslots); 1659 sc->sc_slots = NULL; 1660 } 1661 1662 usb_freemem(&sc->sc_dcbaa_dma); 1663 bad4: 1664 usb_freemem(&sc->sc_eventst_dma); 1665 bad3: 1666 xhci_ring_free(sc, &sc->sc_er); 1667 bad2: 1668 xhci_ring_free(sc, &sc->sc_cr); 1669 i = sc->sc_maxspbuf; 1670 bad1: 1671 for (int j = 0; j < i; j++) 1672 usb_freemem(&sc->sc_spbuf_dma[j]); 1673 usb_freemem(&sc->sc_spbufarray_dma); 1674 1675 return rv; 1676 } 1677 1678 static inline bool 1679 xhci_polling_p(struct xhci_softc * const sc) 1680 { 1681 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1682 } 1683 1684 int 1685 xhci_intr(void *v) 1686 { 1687 struct xhci_softc * const sc = v; 1688 int ret = 0; 1689 1690 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1691 1692 if (sc == NULL) 1693 return 0; 1694 1695 mutex_spin_enter(&sc->sc_intr_lock); 1696 1697 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1698 goto done; 1699 1700 /* If we get an interrupt while polling, then just ignore it. */ 1701 if (xhci_polling_p(sc)) { 1702 #ifdef DIAGNOSTIC 1703 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1704 #endif 1705 goto done; 1706 } 1707 1708 ret = xhci_intr1(sc); 1709 if (ret) { 1710 KASSERT(sc->sc_child || sc->sc_child2); 1711 1712 /* 1713 * One of child busses could be already detached. It doesn't 1714 * matter on which of the two the softintr is scheduled. 1715 */ 1716 if (sc->sc_child) 1717 usb_schedsoftintr(&sc->sc_bus); 1718 else 1719 usb_schedsoftintr(&sc->sc_bus2); 1720 } 1721 done: 1722 mutex_spin_exit(&sc->sc_intr_lock); 1723 return ret; 1724 } 1725 1726 int 1727 xhci_intr1(struct xhci_softc * const sc) 1728 { 1729 uint32_t usbsts; 1730 uint32_t iman; 1731 1732 XHCIHIST_FUNC(); 1733 1734 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1735 XHCIHIST_CALLARGS("USBSTS 0x%08jx", usbsts, 0, 0, 0); 1736 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1737 XHCI_STS_HCE)) == 0) { 1738 DPRINTFN(16, "ignored intr not for %jd", 1739 device_unit(sc->sc_dev), 0, 0, 0); 1740 return 0; 1741 } 1742 1743 /* 1744 * Clear EINT and other transient flags, to not misenterpret 1745 * next shared interrupt. Also, to avoid race, EINT must be cleared 1746 * before XHCI_IMAN_INTR_PEND is cleared. 1747 */ 1748 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1749 1750 #ifdef XHCI_DEBUG 1751 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1752 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1753 #endif 1754 1755 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1756 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1757 iman |= XHCI_IMAN_INTR_PEND; 1758 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1759 1760 #ifdef XHCI_DEBUG 1761 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1762 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1763 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1764 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1765 #endif 1766 1767 return 1; 1768 } 1769 1770 /* 1771 * 3 port speed types used in USB stack 1772 * 1773 * usbdi speed 1774 * definition: USB_SPEED_* in usb.h 1775 * They are used in struct usbd_device in USB stack. 1776 * ioctl interface uses these values too. 1777 * port_status speed 1778 * definition: UPS_*_SPEED in usb.h 1779 * They are used in usb_port_status_t and valid only for USB 2.0. 1780 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1781 * of usb_port_status_ext_t indicates port speed. 1782 * Note that some 3.0 values overlap with 2.0 values. 1783 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1784 * means UPS_LOW_SPEED in HS.) 1785 * port status returned from hub also uses these values. 1786 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1787 * or more. 1788 * xspeed: 1789 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1790 * They are used in only slot context and PORTSC reg of xhci. 1791 * The difference between usbdi speed and xspeed is 1792 * that FS and LS values are swapped. 1793 */ 1794 1795 /* convert usbdi speed to xspeed */ 1796 static int 1797 xhci_speed2xspeed(int speed) 1798 { 1799 switch (speed) { 1800 case USB_SPEED_LOW: return 2; 1801 case USB_SPEED_FULL: return 1; 1802 default: return speed; 1803 } 1804 } 1805 1806 #if 0 1807 /* convert xspeed to usbdi speed */ 1808 static int 1809 xhci_xspeed2speed(int xspeed) 1810 { 1811 switch (xspeed) { 1812 case 1: return USB_SPEED_FULL; 1813 case 2: return USB_SPEED_LOW; 1814 default: return xspeed; 1815 } 1816 } 1817 #endif 1818 1819 /* convert xspeed to port status speed */ 1820 static int 1821 xhci_xspeed2psspeed(int xspeed) 1822 { 1823 switch (xspeed) { 1824 case 0: return 0; 1825 case 1: return UPS_FULL_SPEED; 1826 case 2: return UPS_LOW_SPEED; 1827 case 3: return UPS_HIGH_SPEED; 1828 default: return UPS_OTHER_SPEED; 1829 } 1830 } 1831 1832 /* 1833 * Construct input contexts and issue TRB to open pipe. 1834 */ 1835 static usbd_status 1836 xhci_configure_endpoint(struct usbd_pipe *pipe) 1837 { 1838 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1839 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1840 #ifdef USB_DEBUG 1841 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1842 #endif 1843 struct xhci_soft_trb trb; 1844 usbd_status err; 1845 1846 XHCIHIST_FUNC(); 1847 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1848 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1849 pipe->up_endpoint->ue_edesc->bmAttributes); 1850 1851 /* XXX ensure input context is available? */ 1852 1853 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1854 1855 /* set up context */ 1856 xhci_setup_ctx(pipe); 1857 1858 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1859 sc->sc_ctxsz * 1); 1860 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1861 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1862 1863 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1864 trb.trb_2 = 0; 1865 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1866 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1867 1868 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1869 1870 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1871 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1872 sc->sc_ctxsz * 1); 1873 1874 return err; 1875 } 1876 1877 #if 0 1878 static usbd_status 1879 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1880 { 1881 #ifdef USB_DEBUG 1882 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1883 #endif 1884 1885 XHCIHIST_FUNC(); 1886 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 1887 1888 return USBD_NORMAL_COMPLETION; 1889 } 1890 #endif 1891 1892 /* 4.6.8, 6.4.3.7 */ 1893 static void 1894 xhci_reset_endpoint(struct usbd_pipe *pipe) 1895 { 1896 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1897 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1898 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1899 struct xhci_soft_trb trb; 1900 1901 XHCIHIST_FUNC(); 1902 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1903 1904 KASSERT(mutex_owned(&sc->sc_lock)); 1905 1906 trb.trb_0 = 0; 1907 trb.trb_2 = 0; 1908 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1909 XHCI_TRB_3_EP_SET(dci) | 1910 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1911 1912 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) { 1913 device_printf(sc->sc_dev, "%s: endpoint 0x%x: timed out\n", 1914 __func__, pipe->up_endpoint->ue_edesc->bEndpointAddress); 1915 } 1916 } 1917 1918 /* 1919 * 4.6.9, 6.4.3.8 1920 * Stop execution of TDs on xfer ring. 1921 * Should be called with sc_lock held. 1922 */ 1923 static usbd_status 1924 xhci_stop_endpoint_cmd(struct xhci_softc *sc, struct xhci_slot *xs, u_int dci, 1925 uint32_t trb3flags) 1926 { 1927 struct xhci_soft_trb trb; 1928 usbd_status err; 1929 1930 XHCIHIST_FUNC(); 1931 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1932 1933 KASSERT(mutex_owned(&sc->sc_lock)); 1934 1935 trb.trb_0 = 0; 1936 trb.trb_2 = 0; 1937 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1938 XHCI_TRB_3_EP_SET(dci) | 1939 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1940 trb3flags; 1941 1942 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1943 1944 return err; 1945 } 1946 1947 static usbd_status 1948 xhci_stop_endpoint(struct usbd_pipe *pipe) 1949 { 1950 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1951 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1952 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1953 1954 XHCIHIST_FUNC(); 1955 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1956 1957 KASSERT(mutex_owned(&sc->sc_lock)); 1958 1959 return xhci_stop_endpoint_cmd(sc, xs, dci, 0); 1960 } 1961 1962 /* 1963 * Set TR Dequeue Pointer. 1964 * xHCI 1.1 4.6.10 6.4.3.9 1965 * Purge all of the TRBs on ring and reinitialize ring. 1966 * Set TR dequeue Pointer to 0 and Cycle State to 1. 1967 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1968 * error will be generated. 1969 */ 1970 static void 1971 xhci_set_dequeue(struct usbd_pipe *pipe) 1972 { 1973 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1974 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1975 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1976 struct xhci_ring * const xr = xs->xs_xr[dci]; 1977 struct xhci_soft_trb trb; 1978 1979 XHCIHIST_FUNC(); 1980 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1981 1982 KASSERT(mutex_owned(&sc->sc_lock)); 1983 KASSERT(xr != NULL); 1984 1985 xhci_host_dequeue(xr); 1986 1987 /* set DCS */ 1988 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1989 trb.trb_2 = 0; 1990 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1991 XHCI_TRB_3_EP_SET(dci) | 1992 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1993 1994 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) { 1995 device_printf(sc->sc_dev, "%s: endpoint 0x%x: timed out\n", 1996 __func__, pipe->up_endpoint->ue_edesc->bEndpointAddress); 1997 } 1998 } 1999 2000 /* 2001 * Open new pipe: called from usbd_setup_pipe_flags. 2002 * Fills methods of pipe. 2003 * If pipe is not for ep0, calls configure_endpoint. 2004 */ 2005 static usbd_status 2006 xhci_open(struct usbd_pipe *pipe) 2007 { 2008 struct usbd_device * const dev = pipe->up_dev; 2009 struct xhci_pipe * const xpipe = (struct xhci_pipe *)pipe; 2010 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2011 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2012 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2013 const u_int dci = xhci_ep_get_dci(ed); 2014 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2015 usbd_status err; 2016 2017 XHCIHIST_FUNC(); 2018 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 2019 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 2020 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 2021 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 2022 ed->bmAttributes); 2023 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 2024 ed->bInterval, 0, 0); 2025 2026 if (sc->sc_dying) 2027 return USBD_IOERROR; 2028 2029 /* Root Hub */ 2030 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 2031 switch (ed->bEndpointAddress) { 2032 case USB_CONTROL_ENDPOINT: 2033 pipe->up_methods = &roothub_ctrl_methods; 2034 break; 2035 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2036 pipe->up_methods = &xhci_root_intr_methods; 2037 break; 2038 default: 2039 pipe->up_methods = NULL; 2040 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 2041 ed->bEndpointAddress, 0, 0, 0); 2042 return USBD_INVAL; 2043 } 2044 return USBD_NORMAL_COMPLETION; 2045 } 2046 2047 usb_init_task(&xpipe->xp_async_task, xhci_pipe_restart_async_task, 2048 pipe, USB_TASKQ_MPSAFE); 2049 2050 switch (xfertype) { 2051 case UE_CONTROL: 2052 pipe->up_methods = &xhci_device_ctrl_methods; 2053 break; 2054 case UE_ISOCHRONOUS: 2055 pipe->up_methods = &xhci_device_isoc_methods; 2056 pipe->up_serialise = false; 2057 xpipe->xp_isoc_next = -1; 2058 break; 2059 case UE_BULK: 2060 pipe->up_methods = &xhci_device_bulk_methods; 2061 break; 2062 case UE_INTERRUPT: 2063 pipe->up_methods = &xhci_device_intr_methods; 2064 break; 2065 default: 2066 return USBD_IOERROR; 2067 break; 2068 } 2069 2070 KASSERT(xs != NULL); 2071 KASSERT(xs->xs_xr[dci] == NULL); 2072 2073 /* allocate transfer ring */ 2074 err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS, 2075 XHCI_TRB_ALIGN); 2076 if (err) { 2077 DPRINTFN(1, "ring alloc failed %jd", err, 0, 0, 0); 2078 return err; 2079 } 2080 2081 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 2082 return xhci_configure_endpoint(pipe); 2083 2084 return USBD_NORMAL_COMPLETION; 2085 } 2086 2087 /* 2088 * Closes pipe, called from usbd_kill_pipe via close methods. 2089 * If the endpoint to be closed is ep0, disable_slot. 2090 * Should be called with sc_lock held. 2091 */ 2092 static void 2093 xhci_close_pipe(struct usbd_pipe *pipe) 2094 { 2095 struct xhci_pipe * const xp = 2096 container_of(pipe, struct xhci_pipe, xp_pipe); 2097 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2098 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2099 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2100 const u_int dci = xhci_ep_get_dci(ed); 2101 struct xhci_soft_trb trb; 2102 uint32_t *cp; 2103 2104 XHCIHIST_FUNC(); 2105 2106 usb_rem_task_wait(pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC, 2107 &sc->sc_lock); 2108 2109 if (sc->sc_dying) 2110 return; 2111 2112 /* xs is uninitialized before xhci_init_slot */ 2113 if (xs == NULL || xs->xs_idx == 0) 2114 return; 2115 2116 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 2117 (uintptr_t)pipe, xs->xs_idx, dci, 0); 2118 2119 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2120 KASSERT(mutex_owned(&sc->sc_lock)); 2121 2122 if (pipe->up_dev->ud_depth == 0) 2123 return; 2124 2125 if (dci == XHCI_DCI_EP_CONTROL) { 2126 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 2127 /* This frees all rings */ 2128 xhci_disable_slot(sc, xs->xs_idx); 2129 return; 2130 } 2131 2132 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 2133 (void)xhci_stop_endpoint(pipe); 2134 2135 /* 2136 * set appropriate bit to be dropped. 2137 * don't set DC bit to 1, otherwise all endpoints 2138 * would be deconfigured. 2139 */ 2140 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2141 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 2142 cp[1] = htole32(0); 2143 2144 /* XXX should be most significant one, not dci? */ 2145 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2146 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 2147 2148 /* configure ep context performs an implicit dequeue */ 2149 xhci_host_dequeue(xs->xs_xr[dci]); 2150 2151 /* sync input contexts before they are read from memory */ 2152 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2153 2154 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2155 trb.trb_2 = 0; 2156 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2157 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 2158 2159 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2160 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2161 2162 xhci_ring_free(sc, &xs->xs_xr[dci]); 2163 xs->xs_xr[dci] = NULL; 2164 } 2165 2166 /* 2167 * Abort transfer. Must be called with sc_lock held. Releases and 2168 * reacquires sc_lock to sleep until hardware acknowledges abort. 2169 */ 2170 static void 2171 xhci_abortx(struct usbd_xfer *xfer) 2172 { 2173 XHCIHIST_FUNC(); 2174 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2175 2176 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx", 2177 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0); 2178 2179 KASSERT(mutex_owned(&sc->sc_lock)); 2180 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2181 xfer->ux_status == USBD_TIMEOUT), 2182 "bad abort status: %d", xfer->ux_status); 2183 2184 xhci_pipe_restart(xfer->ux_pipe); 2185 2186 DPRINTFN(14, "end", 0, 0, 0, 0); 2187 } 2188 2189 static void 2190 xhci_host_dequeue(struct xhci_ring * const xr) 2191 { 2192 /* When dequeueing the controller, update our struct copy too */ 2193 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 2194 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 2195 BUS_DMASYNC_PREWRITE); 2196 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 2197 2198 xr->xr_ep = 0; 2199 xr->xr_cs = 1; 2200 } 2201 2202 /* 2203 * Recover STALLed endpoint, or stop endpoint to abort a pipe. 2204 * xHCI 1.1 sect 4.10.2.1 2205 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 2206 * all transfers on transfer ring. 2207 */ 2208 static void 2209 xhci_pipe_restart(struct usbd_pipe *pipe) 2210 { 2211 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2212 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2213 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 2214 2215 XHCIHIST_FUNC(); 2216 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 2217 (uintptr_t)pipe, xs->xs_idx, dci, 0); 2218 2219 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2220 2221 /* 2222 * - If the endpoint is halted, indicating a stall, reset it. 2223 * - If the endpoint is stopped, we're already good. 2224 * - Otherwise, someone wanted to abort the pipe, so stop the 2225 * endpoint. 2226 * 2227 * In any case, clear the ring. 2228 */ 2229 switch (xhci_get_epstate(sc, xs, dci)) { 2230 case XHCI_EPSTATE_HALTED: 2231 xhci_reset_endpoint(pipe); 2232 break; 2233 case XHCI_EPSTATE_STOPPED: 2234 break; 2235 default: 2236 xhci_stop_endpoint(pipe); 2237 break; 2238 } 2239 2240 switch (xhci_get_epstate(sc, xs, dci)) { 2241 case XHCI_EPSTATE_STOPPED: 2242 break; 2243 case XHCI_EPSTATE_ERROR: 2244 device_printf(sc->sc_dev, "endpoint 0x%x error\n", 2245 pipe->up_endpoint->ue_edesc->bEndpointAddress); 2246 break; 2247 default: 2248 device_printf(sc->sc_dev, "endpoint 0x%x failed to stop\n", 2249 pipe->up_endpoint->ue_edesc->bEndpointAddress); 2250 } 2251 2252 xhci_set_dequeue(pipe); 2253 2254 DPRINTFN(4, "ends", 0, 0, 0, 0); 2255 } 2256 2257 static void 2258 xhci_pipe_restart_async_task(void *cookie) 2259 { 2260 struct usbd_pipe * const pipe = cookie; 2261 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2262 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2263 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 2264 struct xhci_ring * const tr = xs->xs_xr[dci]; 2265 struct usbd_xfer *xfer; 2266 2267 XHCIHIST_FUNC(); 2268 XHCIHIST_CALLARGS("sc=%#jx pipe=%#jx", 2269 (uintptr_t)sc, (uintptr_t)pipe, 0, 0); 2270 2271 mutex_enter(&sc->sc_lock); 2272 2273 xhci_pipe_restart(pipe); 2274 2275 /* 2276 * We halted our own queue because it stalled. Mark it no 2277 * longer halted and start issuing queued transfers again. 2278 */ 2279 tr->is_halted = false; 2280 xfer = SIMPLEQ_FIRST(&pipe->up_queue); 2281 if (xfer) { 2282 /* 2283 * If the first xfer of the queue is not in progress, 2284 * though, there may be a concurrent software abort 2285 * that has already cancelled it and is now in the 2286 * middle of a concurrent xhci_pipe_restart waiting to 2287 * reacquire the pipe (bus) lock. So only restart the 2288 * xfer if it's still USBD_IN_PROGRESS. 2289 * 2290 * Either way, xfers on the queue can't be in 2291 * USBD_NOT_STARTED. 2292 */ 2293 KASSERT(xfer->ux_status != USBD_NOT_STARTED); 2294 if (xfer->ux_status == USBD_IN_PROGRESS) { 2295 (*pipe->up_methods->upm_start)(xfer); 2296 } else { 2297 DPRINTF("pipe restart race xfer=%#jx status=%jd", 2298 (uintptr_t)xfer, xfer->ux_status, 0, 0); 2299 } 2300 } 2301 2302 mutex_exit(&sc->sc_lock); 2303 } 2304 2305 static void 2306 xhci_pipe_restart_async(struct usbd_pipe *pipe) 2307 { 2308 struct xhci_pipe * const xp = 2309 container_of(pipe, struct xhci_pipe, xp_pipe); 2310 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2311 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2312 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 2313 struct xhci_ring * const tr = xs->xs_xr[dci]; 2314 2315 XHCIHIST_FUNC(); 2316 XHCIHIST_CALLARGS("pipe %#jx", (uintptr_t)pipe, 0, 0, 0); 2317 2318 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2319 2320 tr->is_halted = true; 2321 usb_add_task(pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 2322 2323 DPRINTFN(4, "ends", 0, 0, 0, 0); 2324 } 2325 2326 /* Process roothub port status/change events and notify to uhub_intr. */ 2327 static void 2328 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 2329 { 2330 XHCIHIST_FUNC(); 2331 XHCIHIST_CALLARGS("xhci%jd: port %ju status change", 2332 device_unit(sc->sc_dev), ctlrport, 0, 0); 2333 2334 if (ctlrport > sc->sc_maxports) 2335 return; 2336 2337 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 2338 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 2339 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 2340 2341 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 2342 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 2343 2344 if (xfer == NULL) 2345 return; 2346 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2347 2348 uint8_t *p = xfer->ux_buf; 2349 memset(p, 0, xfer->ux_length); 2350 p[rhp / NBBY] |= 1 << (rhp % NBBY); 2351 xfer->ux_actlen = xfer->ux_length; 2352 xfer->ux_status = USBD_NORMAL_COMPLETION; 2353 usb_transfer_complete(xfer); 2354 } 2355 2356 /* Process Transfer Events */ 2357 static void 2358 xhci_event_transfer(struct xhci_softc * const sc, 2359 const struct xhci_trb * const trb) 2360 { 2361 uint64_t trb_0; 2362 uint32_t trb_2, trb_3; 2363 uint8_t trbcode; 2364 u_int slot, dci; 2365 struct xhci_slot *xs; 2366 struct xhci_ring *xr; 2367 struct xhci_xfer *xx; 2368 struct usbd_xfer *xfer; 2369 usbd_status err; 2370 2371 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2372 2373 trb_0 = le64toh(trb->trb_0); 2374 trb_2 = le32toh(trb->trb_2); 2375 trb_3 = le32toh(trb->trb_3); 2376 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 2377 slot = XHCI_TRB_3_SLOT_GET(trb_3); 2378 dci = XHCI_TRB_3_EP_GET(trb_3); 2379 xs = &sc->sc_slots[slot]; 2380 xr = xs->xs_xr[dci]; 2381 2382 /* sanity check */ 2383 KASSERT(xr != NULL); 2384 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 2385 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 2386 2387 int idx = 0; 2388 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2389 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 2390 DPRINTFN(0, "invalid trb_0 %#jx", trb_0, 0, 0, 0); 2391 return; 2392 } 2393 xx = xr->xr_cookies[idx]; 2394 2395 /* clear cookie of consumed TRB */ 2396 xr->xr_cookies[idx] = NULL; 2397 2398 /* 2399 * xx is NULL if pipe is opened but xfer is not started. 2400 * It happens when stopping idle pipe. 2401 */ 2402 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 2403 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 2404 idx, (uintptr_t)xx, trbcode, dci); 2405 DPRINTFN(1, " orig TRB %#jx type %ju", trb_0, 2406 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 2407 0, 0); 2408 return; 2409 } 2410 } else { 2411 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 2412 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 2413 } 2414 /* XXX this may not happen */ 2415 if (xx == NULL) { 2416 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 2417 return; 2418 } 2419 xfer = &xx->xx_xfer; 2420 /* XXX this may happen when detaching */ 2421 if (xfer == NULL) { 2422 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 2423 (uintptr_t)xx, trb_0, 0, 0); 2424 return; 2425 } 2426 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 2427 /* XXX I dunno why this happens */ 2428 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 2429 2430 if (!xfer->ux_pipe->up_repeat && 2431 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 2432 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 2433 0, 0, 0); 2434 return; 2435 } 2436 2437 const uint8_t xfertype = 2438 UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 2439 2440 /* 4.11.5.2 Event Data TRB */ 2441 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2442 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 2443 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 2444 if ((trb_0 & 0x3) == 0x3) { 2445 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 2446 } 2447 } 2448 2449 switch (trbcode) { 2450 case XHCI_TRB_ERROR_SHORT_PKT: 2451 case XHCI_TRB_ERROR_SUCCESS: 2452 /* 2453 * A ctrl transfer can generate two events if it has a Data 2454 * stage. A short data stage can be OK and should not 2455 * complete the transfer as the status stage needs to be 2456 * performed. 2457 * 2458 * Note: Data and Status stage events point at same xfer. 2459 * ux_actlen and ux_dmabuf will be passed to 2460 * usb_transfer_complete after the Status stage event. 2461 * 2462 * It can be distinguished which stage generates the event: 2463 * + by checking least 3 bits of trb_0 if ED==1. 2464 * (see xhci_device_ctrl_start). 2465 * + by checking the type of original TRB if ED==0. 2466 * 2467 * In addition, intr, bulk, and isoc transfer currently 2468 * consists of single TD, so the "skip" is not needed. 2469 * ctrl xfer uses EVENT_DATA, and others do not. 2470 * Thus driver can switch the flow by checking ED bit. 2471 */ 2472 if (xfertype == UE_ISOCHRONOUS) { 2473 xfer->ux_frlengths[xx->xx_isoc_done] -= 2474 XHCI_TRB_2_REM_GET(trb_2); 2475 xfer->ux_actlen += xfer->ux_frlengths[xx->xx_isoc_done]; 2476 if (++xx->xx_isoc_done < xfer->ux_nframes) 2477 return; 2478 } else 2479 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2480 if (xfer->ux_actlen == 0) 2481 xfer->ux_actlen = xfer->ux_length - 2482 XHCI_TRB_2_REM_GET(trb_2); 2483 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 2484 == XHCI_TRB_TYPE_DATA_STAGE) { 2485 return; 2486 } 2487 } else if ((trb_0 & 0x3) == 0x3) { 2488 return; 2489 } 2490 err = USBD_NORMAL_COMPLETION; 2491 break; 2492 case XHCI_TRB_ERROR_STOPPED: 2493 case XHCI_TRB_ERROR_LENGTH: 2494 case XHCI_TRB_ERROR_STOPPED_SHORT: 2495 err = USBD_IOERROR; 2496 break; 2497 case XHCI_TRB_ERROR_STALL: 2498 case XHCI_TRB_ERROR_BABBLE: 2499 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2500 xhci_pipe_restart_async(xfer->ux_pipe); 2501 err = USBD_STALLED; 2502 break; 2503 default: 2504 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2505 err = USBD_IOERROR; 2506 break; 2507 } 2508 2509 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2510 (trb_0 & 0x3) == 0x0) { 2511 /* 2512 * Try to claim this xfer for completion. If it has 2513 * already completed or aborted, drop it on the floor. 2514 */ 2515 if (!usbd_xfer_trycomplete(xfer)) 2516 return; 2517 2518 /* Set the status. */ 2519 xfer->ux_status = err; 2520 2521 usb_transfer_complete(xfer); 2522 } 2523 } 2524 2525 /* Process Command complete events */ 2526 static void 2527 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2528 { 2529 uint64_t trb_0; 2530 uint32_t trb_2, trb_3; 2531 2532 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2533 2534 KASSERT(mutex_owned(&sc->sc_lock)); 2535 2536 trb_0 = le64toh(trb->trb_0); 2537 trb_2 = le32toh(trb->trb_2); 2538 trb_3 = le32toh(trb->trb_3); 2539 2540 if (trb_0 == sc->sc_command_addr) { 2541 sc->sc_resultpending = false; 2542 2543 sc->sc_result_trb.trb_0 = trb_0; 2544 sc->sc_result_trb.trb_2 = trb_2; 2545 sc->sc_result_trb.trb_3 = trb_3; 2546 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2547 XHCI_TRB_ERROR_SUCCESS) { 2548 DPRINTFN(1, "command completion " 2549 "failure: 0x%016jx 0x%08jx 0x%08jx", 2550 trb_0, trb_2, trb_3, 0); 2551 } 2552 cv_signal(&sc->sc_command_cv); 2553 } else { 2554 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2555 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2556 } 2557 } 2558 2559 /* 2560 * Process events. 2561 * called from xhci_softintr 2562 */ 2563 static void 2564 xhci_handle_event(struct xhci_softc * const sc, 2565 const struct xhci_trb * const trb) 2566 { 2567 uint64_t trb_0; 2568 uint32_t trb_2, trb_3; 2569 2570 XHCIHIST_FUNC(); 2571 2572 trb_0 = le64toh(trb->trb_0); 2573 trb_2 = le32toh(trb->trb_2); 2574 trb_3 = le32toh(trb->trb_3); 2575 2576 XHCIHIST_CALLARGS("event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2577 (uintptr_t)trb, trb_0, trb_2, trb_3); 2578 2579 /* 2580 * 4.11.3.1, 6.4.2.1 2581 * TRB Pointer is invalid for these completion codes. 2582 */ 2583 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2584 case XHCI_TRB_ERROR_RING_UNDERRUN: 2585 case XHCI_TRB_ERROR_RING_OVERRUN: 2586 case XHCI_TRB_ERROR_VF_RING_FULL: 2587 return; 2588 default: 2589 if (trb_0 == 0) { 2590 return; 2591 } 2592 break; 2593 } 2594 2595 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2596 case XHCI_TRB_EVENT_TRANSFER: 2597 xhci_event_transfer(sc, trb); 2598 break; 2599 case XHCI_TRB_EVENT_CMD_COMPLETE: 2600 xhci_event_cmd(sc, trb); 2601 break; 2602 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2603 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2604 break; 2605 default: 2606 break; 2607 } 2608 } 2609 2610 static void 2611 xhci_softintr(void *v) 2612 { 2613 struct usbd_bus * const bus = v; 2614 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2615 struct xhci_ring * const er = sc->sc_er; 2616 struct xhci_trb *trb; 2617 int i, j, k; 2618 2619 XHCIHIST_FUNC(); 2620 2621 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2622 2623 i = er->xr_ep; 2624 j = er->xr_cs; 2625 2626 XHCIHIST_CALLARGS("er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2627 2628 while (1) { 2629 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2630 BUS_DMASYNC_POSTREAD); 2631 trb = &er->xr_trb[i]; 2632 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2633 2634 if (j != k) 2635 break; 2636 2637 xhci_handle_event(sc, trb); 2638 2639 i++; 2640 if (i == er->xr_ntrb) { 2641 i = 0; 2642 j ^= 1; 2643 } 2644 } 2645 2646 er->xr_ep = i; 2647 er->xr_cs = j; 2648 2649 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2650 XHCI_ERDP_BUSY); 2651 2652 DPRINTFN(16, "ends", 0, 0, 0, 0); 2653 2654 return; 2655 } 2656 2657 static void 2658 xhci_poll(struct usbd_bus *bus) 2659 { 2660 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2661 2662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2663 2664 mutex_enter(&sc->sc_intr_lock); 2665 int ret = xhci_intr1(sc); 2666 if (ret) { 2667 xhci_softintr(bus); 2668 } 2669 mutex_exit(&sc->sc_intr_lock); 2670 2671 return; 2672 } 2673 2674 static struct usbd_xfer * 2675 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2676 { 2677 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2678 struct xhci_xfer *xx; 2679 u_int ntrbs; 2680 2681 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2682 2683 ntrbs = uimax(3, nframes); 2684 const size_t trbsz = sizeof(*xx->xx_trb) * ntrbs; 2685 2686 xx = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2687 if (xx != NULL) { 2688 memset(xx, 0, sizeof(*xx)); 2689 if (ntrbs > 0) { 2690 xx->xx_trb = kmem_alloc(trbsz, KM_SLEEP); 2691 xx->xx_ntrb = ntrbs; 2692 } 2693 #ifdef DIAGNOSTIC 2694 xx->xx_xfer.ux_state = XFER_BUSY; 2695 #endif 2696 } 2697 2698 return &xx->xx_xfer; 2699 } 2700 2701 static void 2702 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2703 { 2704 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2705 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 2706 2707 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2708 2709 #ifdef DIAGNOSTIC 2710 if (xfer->ux_state != XFER_BUSY && 2711 xfer->ux_status != USBD_NOT_STARTED) { 2712 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2713 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2714 } 2715 xfer->ux_state = XFER_FREE; 2716 #endif 2717 if (xx->xx_ntrb > 0) { 2718 kmem_free(xx->xx_trb, xx->xx_ntrb * sizeof(*xx->xx_trb)); 2719 xx->xx_trb = NULL; 2720 xx->xx_ntrb = 0; 2721 } 2722 pool_cache_put(sc->sc_xferpool, xx); 2723 } 2724 2725 static bool 2726 xhci_dying(struct usbd_bus *bus) 2727 { 2728 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2729 2730 return sc->sc_dying; 2731 } 2732 2733 static void 2734 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2735 { 2736 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2737 2738 *lock = &sc->sc_lock; 2739 } 2740 2741 extern uint32_t usb_cookie_no; 2742 2743 /* 2744 * xHCI 4.3 2745 * Called when uhub_explore finds a new device (via usbd_new_device). 2746 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2747 * This function does: 2748 * Allocate and construct dev structure of default endpoint (ep0). 2749 * Allocate and open pipe of ep0. 2750 * Enable slot and initialize slot context. 2751 * Set Address. 2752 * Read initial device descriptor. 2753 * Determine initial MaxPacketSize (mps) by speed. 2754 * Read full device descriptor. 2755 * Register this device. 2756 * Finally state of device transitions ADDRESSED. 2757 */ 2758 static usbd_status 2759 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2760 int speed, int port, struct usbd_port *up) 2761 { 2762 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2763 struct usbd_device *dev; 2764 usbd_status err; 2765 usb_device_descriptor_t *dd; 2766 struct xhci_slot *xs; 2767 uint32_t *cp; 2768 2769 XHCIHIST_FUNC(); 2770 XHCIHIST_CALLARGS("port %ju depth %ju speed %ju up %#jx", 2771 port, depth, speed, (uintptr_t)up); 2772 2773 KASSERT(KERNEL_LOCKED_P()); 2774 2775 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2776 dev->ud_bus = bus; 2777 dev->ud_quirks = &usbd_no_quirk; 2778 dev->ud_addr = 0; 2779 dev->ud_ddesc.bMaxPacketSize = 0; 2780 dev->ud_depth = depth; 2781 dev->ud_powersrc = up; 2782 dev->ud_myhub = up->up_parent; 2783 dev->ud_speed = speed; 2784 dev->ud_langid = USBD_NOLANG; 2785 dev->ud_cookie.cookie = ++usb_cookie_no; 2786 2787 /* Set up default endpoint handle. */ 2788 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2789 /* doesn't matter, just don't let it uninitialized */ 2790 dev->ud_ep0.ue_toggle = 0; 2791 2792 /* Set up default endpoint descriptor. */ 2793 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2794 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2795 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2796 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2797 dev->ud_ep0desc.bInterval = 0; 2798 2799 /* 4.3, 4.8.2.1 */ 2800 switch (speed) { 2801 case USB_SPEED_SUPER: 2802 case USB_SPEED_SUPER_PLUS: 2803 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2804 break; 2805 case USB_SPEED_FULL: 2806 /* XXX using 64 as initial mps of ep0 in FS */ 2807 case USB_SPEED_HIGH: 2808 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2809 break; 2810 case USB_SPEED_LOW: 2811 default: 2812 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2813 break; 2814 } 2815 2816 up->up_dev = dev; 2817 2818 dd = &dev->ud_ddesc; 2819 2820 if (depth == 0 && port == 0) { 2821 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2822 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2823 2824 /* Establish the default pipe. */ 2825 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2826 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2827 if (err) { 2828 DPRINTFN(1, "setup default pipe failed %jd", err,0,0,0); 2829 goto bad; 2830 } 2831 err = usbd_get_initial_ddesc(dev, dd); 2832 if (err) { 2833 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2834 goto bad; 2835 } 2836 } else { 2837 uint8_t slot = 0; 2838 2839 /* 4.3.2 */ 2840 err = xhci_enable_slot(sc, &slot); 2841 if (err) { 2842 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2843 goto bad; 2844 } 2845 2846 xs = &sc->sc_slots[slot]; 2847 dev->ud_hcpriv = xs; 2848 2849 /* 4.3.3 initialize slot structure */ 2850 err = xhci_init_slot(dev, slot); 2851 if (err) { 2852 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2853 dev->ud_hcpriv = NULL; 2854 /* 2855 * We have to disable_slot here because 2856 * xs->xs_idx == 0 when xhci_init_slot fails, 2857 * in that case usbd_remove_dev won't work. 2858 */ 2859 mutex_enter(&sc->sc_lock); 2860 xhci_disable_slot(sc, slot); 2861 mutex_exit(&sc->sc_lock); 2862 goto bad; 2863 } 2864 2865 /* 2866 * We have to establish the default pipe _after_ slot 2867 * structure has been prepared. 2868 */ 2869 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2870 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2871 if (err) { 2872 DPRINTFN(1, "setup default pipe failed %jd", err, 0, 0, 2873 0); 2874 goto bad; 2875 } 2876 2877 /* 4.3.4 Address Assignment */ 2878 err = xhci_set_address(dev, slot, false); 2879 if (err) { 2880 DPRINTFN(1, "failed! to set address: %ju", err, 0, 0, 0); 2881 goto bad; 2882 } 2883 2884 /* Allow device time to set new address */ 2885 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2886 2887 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2888 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2889 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2890 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2891 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2892 /* 2893 * XXX ensure we know when the hardware does something 2894 * we can't yet cope with 2895 */ 2896 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2897 dev->ud_addr = addr; 2898 2899 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2900 "addr %d already allocated", dev->ud_addr); 2901 /* 2902 * The root hub is given its own slot 2903 */ 2904 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2905 2906 err = usbd_get_initial_ddesc(dev, dd); 2907 if (err) { 2908 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2909 goto bad; 2910 } 2911 2912 /* 4.8.2.1 */ 2913 if (USB_IS_SS(speed)) { 2914 if (dd->bMaxPacketSize != 9) { 2915 printf("%s: invalid mps 2^%u for SS ep0," 2916 " using 512\n", 2917 device_xname(sc->sc_dev), 2918 dd->bMaxPacketSize); 2919 dd->bMaxPacketSize = 9; 2920 } 2921 USETW(dev->ud_ep0desc.wMaxPacketSize, 2922 (1 << dd->bMaxPacketSize)); 2923 } else 2924 USETW(dev->ud_ep0desc.wMaxPacketSize, 2925 dd->bMaxPacketSize); 2926 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2927 err = xhci_update_ep0_mps(sc, xs, 2928 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2929 if (err) { 2930 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2931 goto bad; 2932 } 2933 } 2934 2935 err = usbd_reload_device_desc(dev); 2936 if (err) { 2937 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2938 goto bad; 2939 } 2940 2941 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2942 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2943 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2944 dd->bDeviceClass, dd->bDeviceSubClass, 2945 dd->bDeviceProtocol, 0); 2946 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2947 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2948 dev->ud_speed); 2949 2950 usbd_get_device_strings(dev); 2951 2952 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2953 2954 if (depth == 0 && port == 0) { 2955 usbd_attach_roothub(parent, dev); 2956 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2957 return USBD_NORMAL_COMPLETION; 2958 } 2959 2960 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2961 bad: 2962 if (err != USBD_NORMAL_COMPLETION) { 2963 if (depth == 0 && port == 0 && dev->ud_pipe0) 2964 usbd_kill_pipe(dev->ud_pipe0); 2965 usbd_remove_device(dev, up); 2966 } 2967 2968 return err; 2969 } 2970 2971 static usbd_status 2972 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring **xrp, 2973 size_t ntrb, size_t align) 2974 { 2975 size_t size = ntrb * XHCI_TRB_SIZE; 2976 struct xhci_ring *xr; 2977 2978 XHCIHIST_FUNC(); 2979 XHCIHIST_CALLARGS("xr %#jx ntrb %#jx align %#jx", 2980 (uintptr_t)*xrp, ntrb, align, 0); 2981 2982 xr = kmem_zalloc(sizeof(struct xhci_ring), KM_SLEEP); 2983 DPRINTFN(1, "ring %#jx", (uintptr_t)xr, 0, 0, 0); 2984 2985 int err = usb_allocmem(sc->sc_bus.ub_dmatag, size, align, 2986 USBMALLOC_COHERENT | USBMALLOC_ZERO, &xr->xr_dma); 2987 if (err) { 2988 kmem_free(xr, sizeof(struct xhci_ring)); 2989 DPRINTFN(1, "alloc xr_dma failed %jd", err, 0, 0, 0); 2990 return err; 2991 } 2992 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2993 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2994 xr->xr_trb = xhci_ring_trbv(xr, 0); 2995 xr->xr_ntrb = ntrb; 2996 xr->is_halted = false; 2997 xhci_host_dequeue(xr); 2998 *xrp = xr; 2999 3000 return USBD_NORMAL_COMPLETION; 3001 } 3002 3003 static void 3004 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring ** const xr) 3005 { 3006 if (*xr == NULL) 3007 return; 3008 3009 usb_freemem(&(*xr)->xr_dma); 3010 mutex_destroy(&(*xr)->xr_lock); 3011 kmem_free((*xr)->xr_cookies, 3012 sizeof(*(*xr)->xr_cookies) * (*xr)->xr_ntrb); 3013 kmem_free(*xr, sizeof(struct xhci_ring)); 3014 *xr = NULL; 3015 } 3016 3017 static void 3018 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 3019 void *cookie, struct xhci_soft_trb * const trbs, size_t ntrbs) 3020 { 3021 size_t i; 3022 u_int ri; 3023 u_int cs; 3024 uint64_t parameter; 3025 uint32_t status; 3026 uint32_t control; 3027 3028 XHCIHIST_FUNC(); 3029 XHCIHIST_CALLARGS("%#jx xr_ep %#jx xr_cs %ju", 3030 (uintptr_t)xr, xr->xr_ep, xr->xr_cs, 0); 3031 3032 KASSERTMSG(ntrbs < xr->xr_ntrb, "ntrbs %zu, xr->xr_ntrb %u", 3033 ntrbs, xr->xr_ntrb); 3034 for (i = 0; i < ntrbs; i++) { 3035 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 3036 (uintptr_t)trbs, i, 0); 3037 DPRINTFN(12, " 0x%016jx 0x%08jx 0x%08jx", 3038 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 3039 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 3040 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 3041 } 3042 3043 ri = xr->xr_ep; 3044 cs = xr->xr_cs; 3045 3046 /* 3047 * Although the xhci hardware can do scatter/gather dma from 3048 * arbitrary sized buffers, there is a non-obvious restriction 3049 * that a LINK trb is only allowed at the end of a burst of 3050 * transfers - which might be 16kB. 3051 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 3052 * The simple solution is not to allow a LINK trb in the middle 3053 * of anything - as here. 3054 * XXX: (dsl) There are xhci controllers out there (eg some made by 3055 * ASMedia) that seem to lock up if they process a LINK trb but 3056 * cannot process the linked-to trb yet. 3057 * The code should write the 'cycle' bit on the link trb AFTER 3058 * adding the other trb. 3059 */ 3060 u_int firstep = xr->xr_ep; 3061 u_int firstcs = xr->xr_cs; 3062 3063 for (i = 0; i < ntrbs; ) { 3064 u_int oldri = ri; 3065 u_int oldcs = cs; 3066 3067 if (ri >= (xr->xr_ntrb - 1)) { 3068 /* Put Link TD at the end of ring */ 3069 parameter = xhci_ring_trbp(xr, 0); 3070 status = 0; 3071 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 3072 XHCI_TRB_3_TC_BIT; 3073 xr->xr_cookies[ri] = NULL; 3074 xr->xr_ep = 0; 3075 xr->xr_cs ^= 1; 3076 ri = xr->xr_ep; 3077 cs = xr->xr_cs; 3078 } else { 3079 parameter = trbs[i].trb_0; 3080 status = trbs[i].trb_2; 3081 control = trbs[i].trb_3; 3082 3083 xr->xr_cookies[ri] = cookie; 3084 ri++; 3085 i++; 3086 } 3087 /* 3088 * If this is a first TRB, mark it invalid to prevent 3089 * xHC from running it immediately. 3090 */ 3091 if (oldri == firstep) { 3092 if (oldcs) { 3093 control &= ~XHCI_TRB_3_CYCLE_BIT; 3094 } else { 3095 control |= XHCI_TRB_3_CYCLE_BIT; 3096 } 3097 } else { 3098 if (oldcs) { 3099 control |= XHCI_TRB_3_CYCLE_BIT; 3100 } else { 3101 control &= ~XHCI_TRB_3_CYCLE_BIT; 3102 } 3103 } 3104 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 3105 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 3106 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3107 } 3108 3109 /* Now invert cycle bit of first TRB */ 3110 if (firstcs) { 3111 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 3112 } else { 3113 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 3114 } 3115 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 3116 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3117 3118 xr->xr_ep = ri; 3119 xr->xr_cs = cs; 3120 3121 DPRINTFN(12, "%#jx xr_ep %#jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 3122 xr->xr_cs, 0); 3123 } 3124 3125 static inline void 3126 xhci_ring_put_xfer(struct xhci_softc * const sc, struct xhci_ring * const tr, 3127 struct xhci_xfer *xx, u_int ntrb) 3128 { 3129 KASSERT(ntrb <= xx->xx_ntrb); 3130 xhci_ring_put(sc, tr, xx, xx->xx_trb, ntrb); 3131 } 3132 3133 /* 3134 * Stop execution commands, purge all commands on command ring, and 3135 * rewind dequeue pointer. 3136 */ 3137 static void 3138 xhci_abort_command(struct xhci_softc *sc) 3139 { 3140 struct xhci_ring * const cr = sc->sc_cr; 3141 uint64_t crcr; 3142 int i; 3143 3144 XHCIHIST_FUNC(); 3145 XHCIHIST_CALLARGS("command %#jx timeout, aborting", 3146 sc->sc_command_addr, 0, 0, 0); 3147 3148 mutex_enter(&cr->xr_lock); 3149 3150 /* 4.6.1.2 Aborting a Command */ 3151 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3152 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 3153 3154 for (i = 0; i < 500; i++) { 3155 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3156 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 3157 break; 3158 usb_delay_ms(&sc->sc_bus, 1); 3159 } 3160 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 3161 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 3162 /* reset HC here? */ 3163 } 3164 3165 /* reset command ring dequeue pointer */ 3166 cr->xr_ep = 0; 3167 cr->xr_cs = 1; 3168 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 3169 3170 mutex_exit(&cr->xr_lock); 3171 } 3172 3173 /* 3174 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 3175 * Command completion is notified by cv_signal from xhci_event_cmd() 3176 * (called from xhci_softint), or timed-out. 3177 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 3178 * then do_command examines it. 3179 */ 3180 static usbd_status 3181 xhci_do_command_locked(struct xhci_softc * const sc, 3182 struct xhci_soft_trb * const trb, int timeout) 3183 { 3184 struct xhci_ring * const cr = sc->sc_cr; 3185 usbd_status err; 3186 3187 XHCIHIST_FUNC(); 3188 XHCIHIST_CALLARGS("input: 0x%016jx 0x%08jx 0x%08jx", 3189 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3190 3191 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 3192 KASSERT(mutex_owned(&sc->sc_lock)); 3193 3194 while (sc->sc_command_addr != 0 || 3195 (sc->sc_suspender != NULL && sc->sc_suspender != curlwp)) 3196 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 3197 3198 /* 3199 * If enqueue pointer points at last of ring, it's Link TRB, 3200 * command TRB will be stored in 0th TRB. 3201 */ 3202 if (cr->xr_ep == cr->xr_ntrb - 1) 3203 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 3204 else 3205 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 3206 3207 sc->sc_resultpending = true; 3208 3209 mutex_enter(&cr->xr_lock); 3210 xhci_ring_put(sc, cr, NULL, trb, 1); 3211 mutex_exit(&cr->xr_lock); 3212 3213 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 3214 3215 while (sc->sc_resultpending) { 3216 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 3217 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 3218 xhci_abort_command(sc); 3219 err = USBD_TIMEOUT; 3220 goto timedout; 3221 } 3222 } 3223 3224 trb->trb_0 = sc->sc_result_trb.trb_0; 3225 trb->trb_2 = sc->sc_result_trb.trb_2; 3226 trb->trb_3 = sc->sc_result_trb.trb_3; 3227 3228 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 3229 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3230 3231 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 3232 case XHCI_TRB_ERROR_SUCCESS: 3233 err = USBD_NORMAL_COMPLETION; 3234 break; 3235 default: 3236 case 192 ... 223: 3237 DPRINTFN(5, "error %#jx", 3238 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0); 3239 err = USBD_IOERROR; 3240 break; 3241 case 224 ... 255: 3242 err = USBD_NORMAL_COMPLETION; 3243 break; 3244 } 3245 3246 timedout: 3247 sc->sc_resultpending = false; 3248 sc->sc_command_addr = 0; 3249 cv_broadcast(&sc->sc_cmdbusy_cv); 3250 3251 return err; 3252 } 3253 3254 static usbd_status 3255 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb, 3256 int timeout) 3257 { 3258 3259 mutex_enter(&sc->sc_lock); 3260 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 3261 mutex_exit(&sc->sc_lock); 3262 3263 return ret; 3264 } 3265 3266 static usbd_status 3267 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 3268 { 3269 struct xhci_soft_trb trb; 3270 usbd_status err; 3271 3272 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3273 3274 trb.trb_0 = 0; 3275 trb.trb_2 = 0; 3276 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 3277 3278 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3279 if (err != USBD_NORMAL_COMPLETION) { 3280 return err; 3281 } 3282 3283 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 3284 3285 return err; 3286 } 3287 3288 /* 3289 * xHCI 4.6.4 3290 * Deallocate ring and device/input context DMA buffers, and disable_slot. 3291 * All endpoints in the slot should be stopped. 3292 * Should be called with sc_lock held. 3293 */ 3294 static usbd_status 3295 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 3296 { 3297 struct xhci_soft_trb trb; 3298 struct xhci_slot *xs; 3299 usbd_status err; 3300 3301 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3302 3303 if (sc->sc_dying) 3304 return USBD_IOERROR; 3305 3306 trb.trb_0 = 0; 3307 trb.trb_2 = 0; 3308 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) | 3309 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT); 3310 3311 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 3312 3313 if (!err) { 3314 xs = &sc->sc_slots[slot]; 3315 if (xs->xs_idx != 0) { 3316 xhci_free_slot(sc, xs); 3317 xhci_set_dcba(sc, 0, slot); 3318 memset(xs, 0, sizeof(*xs)); 3319 } 3320 } 3321 3322 return err; 3323 } 3324 3325 /* 3326 * Set address of device and transition slot state from ENABLED to ADDRESSED 3327 * if Block Setaddress Request (BSR) is false. 3328 * If BSR==true, transition slot state from ENABLED to DEFAULT. 3329 * see xHCI 1.1 4.5.3, 3.3.4 3330 * Should be called without sc_lock held. 3331 */ 3332 static usbd_status 3333 xhci_address_device(struct xhci_softc * const sc, 3334 uint64_t icp, uint8_t slot_id, bool bsr) 3335 { 3336 struct xhci_soft_trb trb; 3337 usbd_status err; 3338 3339 XHCIHIST_FUNC(); 3340 if (bsr) { 3341 XHCIHIST_CALLARGS("icp %#jx slot %#jx with bsr", 3342 icp, slot_id, 0, 0); 3343 } else { 3344 XHCIHIST_CALLARGS("icp %#jx slot %#jx nobsr", 3345 icp, slot_id, 0, 0); 3346 } 3347 3348 trb.trb_0 = icp; 3349 trb.trb_2 = 0; 3350 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 3351 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 3352 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 3353 3354 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3355 3356 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 3357 err = USBD_NO_ADDR; 3358 3359 return err; 3360 } 3361 3362 static usbd_status 3363 xhci_update_ep0_mps(struct xhci_softc * const sc, 3364 struct xhci_slot * const xs, u_int mps) 3365 { 3366 struct xhci_soft_trb trb; 3367 usbd_status err; 3368 uint32_t * cp; 3369 3370 XHCIHIST_FUNC(); 3371 XHCIHIST_CALLARGS("slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 3372 3373 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3374 cp[0] = htole32(0); 3375 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 3376 3377 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 3378 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 3379 3380 /* sync input contexts before they are read from memory */ 3381 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3382 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3383 sc->sc_ctxsz * 4); 3384 3385 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 3386 trb.trb_2 = 0; 3387 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 3388 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 3389 3390 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3391 return err; 3392 } 3393 3394 static void 3395 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 3396 { 3397 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 3398 3399 XHCIHIST_FUNC(); 3400 XHCIHIST_CALLARGS("dcbaa %#jx dc 0x%016jx slot %jd", 3401 (uintptr_t)&dcbaa[si], dcba, si, 0); 3402 3403 dcbaa[si] = htole64(dcba); 3404 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 3405 BUS_DMASYNC_PREWRITE); 3406 } 3407 3408 /* 3409 * Allocate device and input context DMA buffer, and 3410 * TRB DMA buffer for each endpoint. 3411 */ 3412 static usbd_status 3413 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 3414 { 3415 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3416 struct xhci_slot *xs; 3417 3418 XHCIHIST_FUNC(); 3419 XHCIHIST_CALLARGS("slot %ju", slot, 0, 0, 0); 3420 3421 xs = &sc->sc_slots[slot]; 3422 3423 /* allocate contexts */ 3424 int err = usb_allocmem(sc->sc_bus.ub_dmatag, sc->sc_pgsz, sc->sc_pgsz, 3425 USBMALLOC_COHERENT | USBMALLOC_ZERO, &xs->xs_dc_dma); 3426 if (err) { 3427 DPRINTFN(1, "failed to allocmem output device context %jd", 3428 err, 0, 0, 0); 3429 return USBD_NOMEM; 3430 } 3431 3432 err = usb_allocmem(sc->sc_bus.ub_dmatag, sc->sc_pgsz, sc->sc_pgsz, 3433 USBMALLOC_COHERENT | USBMALLOC_ZERO, &xs->xs_ic_dma); 3434 if (err) { 3435 DPRINTFN(1, "failed to allocmem input device context %jd", 3436 err, 0, 0, 0); 3437 goto bad1; 3438 } 3439 3440 memset(&xs->xs_xr[0], 0, sizeof(xs->xs_xr)); 3441 xs->xs_idx = slot; 3442 3443 return USBD_NORMAL_COMPLETION; 3444 3445 bad1: 3446 usb_freemem(&xs->xs_dc_dma); 3447 xs->xs_idx = 0; 3448 return USBD_NOMEM; 3449 } 3450 3451 static void 3452 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs) 3453 { 3454 u_int dci; 3455 3456 XHCIHIST_FUNC(); 3457 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 3458 3459 /* deallocate all allocated rings in the slot */ 3460 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 3461 if (xs->xs_xr[dci] != NULL) 3462 xhci_ring_free(sc, &xs->xs_xr[dci]); 3463 } 3464 usb_freemem(&xs->xs_ic_dma); 3465 usb_freemem(&xs->xs_dc_dma); 3466 xs->xs_idx = 0; 3467 } 3468 3469 /* 3470 * Setup slot context, set Device Context Base Address, and issue 3471 * Set Address Device command. 3472 */ 3473 static usbd_status 3474 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 3475 { 3476 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3477 struct xhci_slot *xs; 3478 usbd_status err; 3479 3480 XHCIHIST_FUNC(); 3481 XHCIHIST_CALLARGS("slot %ju bsr %ju", slot, bsr, 0, 0); 3482 3483 xs = &sc->sc_slots[slot]; 3484 3485 xhci_setup_ctx(dev->ud_pipe0); 3486 3487 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3488 sc->sc_ctxsz * 3); 3489 3490 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3491 3492 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3493 3494 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3495 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 3496 sc->sc_ctxsz * 2); 3497 3498 return err; 3499 } 3500 3501 /* 3502 * 4.8.2, 6.2.3.2 3503 * construct slot/endpoint context parameters and do syncmem 3504 */ 3505 static void 3506 xhci_setup_ctx(struct usbd_pipe *pipe) 3507 { 3508 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3509 struct usbd_device *dev = pipe->up_dev; 3510 struct xhci_slot * const xs = dev->ud_hcpriv; 3511 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3512 const u_int dci = xhci_ep_get_dci(ed); 3513 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3514 uint32_t *cp; 3515 uint16_t mps = UGETW(ed->wMaxPacketSize); 3516 uint8_t speed = dev->ud_speed; 3517 uint8_t ival = ed->bInterval; 3518 3519 XHCIHIST_FUNC(); 3520 XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju", 3521 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3522 3523 /* set up initial input control context */ 3524 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3525 cp[0] = htole32(0); 3526 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3527 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3528 cp[7] = htole32(0); 3529 3530 /* set up input slot context */ 3531 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3532 cp[0] = 3533 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3534 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3535 cp[1] = 0; 3536 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3537 cp[3] = 0; 3538 xhci_setup_route(pipe, cp); 3539 xhci_setup_tthub(pipe, cp); 3540 3541 cp[0] = htole32(cp[0]); 3542 cp[1] = htole32(cp[1]); 3543 cp[2] = htole32(cp[2]); 3544 cp[3] = htole32(cp[3]); 3545 3546 /* set up input endpoint context */ 3547 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3548 cp[0] = 3549 XHCI_EPCTX_0_EPSTATE_SET(0) | 3550 XHCI_EPCTX_0_MULT_SET(0) | 3551 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3552 XHCI_EPCTX_0_LSA_SET(0) | 3553 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3554 cp[1] = 3555 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3556 XHCI_EPCTX_1_HID_SET(0) | 3557 XHCI_EPCTX_1_MAXB_SET(0); 3558 3559 if (xfertype != UE_ISOCHRONOUS) 3560 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3561 3562 if (xfertype == UE_CONTROL) 3563 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3564 else if (USB_IS_SS(speed)) 3565 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3566 else 3567 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3568 3569 xhci_setup_maxburst(pipe, cp); 3570 3571 switch (xfertype) { 3572 case UE_CONTROL: 3573 break; 3574 case UE_BULK: 3575 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3576 break; 3577 case UE_INTERRUPT: 3578 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3579 ival = pipe->up_interval; 3580 3581 ival = xhci_bival2ival(ival, speed); 3582 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3583 break; 3584 case UE_ISOCHRONOUS: 3585 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3586 ival = pipe->up_interval; 3587 3588 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3589 if (speed == USB_SPEED_FULL) 3590 ival += 3; /* 1ms -> 125us */ 3591 ival--; 3592 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3593 break; 3594 default: 3595 break; 3596 } 3597 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3598 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3599 3600 /* rewind TR dequeue pointer in xHC */ 3601 /* can't use xhci_ep_get_dci() yet? */ 3602 *(uint64_t *)(&cp[2]) = htole64( 3603 xhci_ring_trbp(xs->xs_xr[dci], 0) | 3604 XHCI_EPCTX_2_DCS_SET(1)); 3605 3606 cp[0] = htole32(cp[0]); 3607 cp[1] = htole32(cp[1]); 3608 cp[4] = htole32(cp[4]); 3609 3610 /* rewind TR dequeue pointer in driver */ 3611 struct xhci_ring *xr = xs->xs_xr[dci]; 3612 mutex_enter(&xr->xr_lock); 3613 xhci_host_dequeue(xr); 3614 mutex_exit(&xr->xr_lock); 3615 3616 /* sync input contexts before they are read from memory */ 3617 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3618 } 3619 3620 /* 3621 * Setup route string and roothub port of given device for slot context 3622 */ 3623 static void 3624 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3625 { 3626 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3627 struct usbd_device *dev = pipe->up_dev; 3628 struct usbd_port *up = dev->ud_powersrc; 3629 struct usbd_device *hub; 3630 struct usbd_device *adev; 3631 uint8_t rhport = 0; 3632 uint32_t route = 0; 3633 3634 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3635 3636 /* Locate root hub port and Determine route string */ 3637 /* 4.3.3 route string does not include roothub port */ 3638 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3639 uint32_t dep; 3640 3641 DPRINTFN(4, "hub %#jx depth %jd upport %#jx upportno %jd", 3642 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3643 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3644 -1); 3645 3646 if (hub->ud_powersrc == NULL) 3647 break; 3648 dep = hub->ud_depth; 3649 if (dep == 0) 3650 break; 3651 rhport = hub->ud_powersrc->up_portno; 3652 if (dep > USB_HUB_MAX_DEPTH) 3653 continue; 3654 3655 route |= 3656 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3657 << ((dep - 1) * 4); 3658 } 3659 route = route >> 4; 3660 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3661 3662 /* Locate port on upstream high speed hub */ 3663 for (adev = dev, hub = up->up_parent; 3664 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3665 adev = hub, hub = hub->ud_myhub) 3666 ; 3667 if (hub) { 3668 int p; 3669 for (p = 1; p <= hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3670 if (hub->ud_hub->uh_ports[p - 1].up_dev == adev) { 3671 dev->ud_myhsport = &hub->ud_hub->uh_ports[p - 1]; 3672 goto found; 3673 } 3674 } 3675 panic("%s: cannot find HS port", __func__); 3676 found: 3677 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3678 } else { 3679 dev->ud_myhsport = NULL; 3680 } 3681 3682 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3683 3684 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3685 ctlrport, route, (uintptr_t)hub); 3686 3687 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3688 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3689 } 3690 3691 /* 3692 * Setup whether device is hub, whether device uses MTT, and 3693 * TT informations if it uses MTT. 3694 */ 3695 static void 3696 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3697 { 3698 struct usbd_device *dev = pipe->up_dev; 3699 struct usbd_port *myhsport = dev->ud_myhsport; 3700 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3701 uint32_t speed = dev->ud_speed; 3702 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3703 uint8_t tthubslot, ttportnum; 3704 bool ishub; 3705 bool usemtt; 3706 3707 XHCIHIST_FUNC(); 3708 3709 /* 3710 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3711 * tthubslot: 3712 * This is the slot ID of parent HS hub 3713 * if LS/FS device is connected && connected through HS hub. 3714 * This is 0 if device is not LS/FS device || 3715 * parent hub is not HS hub || 3716 * attached to root hub. 3717 * ttportnum: 3718 * This is the downstream facing port of parent HS hub 3719 * if LS/FS device is connected. 3720 * This is 0 if device is not LS/FS device || 3721 * parent hub is not HS hub || 3722 * attached to root hub. 3723 */ 3724 if (myhsport && 3725 myhsport->up_parent->ud_addr != rhaddr && 3726 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3727 ttportnum = myhsport->up_portno; 3728 tthubslot = myhsport->up_parent->ud_addr; 3729 } else { 3730 ttportnum = 0; 3731 tthubslot = 0; 3732 } 3733 XHCIHIST_CALLARGS("myhsport %#jx ttportnum=%jd tthubslot=%jd", 3734 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3735 3736 /* ishub is valid after reading UDESC_DEVICE */ 3737 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3738 3739 /* dev->ud_hub is valid after reading UDESC_HUB */ 3740 if (ishub && dev->ud_hub) { 3741 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3742 uint8_t ttt = 3743 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3744 3745 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3746 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3747 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3748 } 3749 3750 #define IS_MTTHUB(dd) \ 3751 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3752 3753 /* 3754 * MTT flag is set if 3755 * 1. this is HS hub && MTTs are supported and enabled; or 3756 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3757 * are supported and enabled. 3758 * 3759 * XXX enabled is not tested yet 3760 */ 3761 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3762 usemtt = true; 3763 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3764 myhsport && 3765 myhsport->up_parent->ud_addr != rhaddr && 3766 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3767 usemtt = true; 3768 else 3769 usemtt = false; 3770 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3771 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3772 3773 #undef IS_MTTHUB 3774 3775 cp[0] |= 3776 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3777 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3778 cp[2] |= 3779 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3780 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3781 } 3782 3783 /* set up params for periodic endpoint */ 3784 static void 3785 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3786 { 3787 struct xhci_pipe * const xpipe = (struct xhci_pipe *)pipe; 3788 struct usbd_device *dev = pipe->up_dev; 3789 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3790 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3791 usbd_desc_iter_t iter; 3792 const usb_cdc_descriptor_t *cdcd; 3793 uint32_t maxb = 0; 3794 uint16_t mps = UGETW(ed->wMaxPacketSize); 3795 uint8_t speed = dev->ud_speed; 3796 uint8_t mult = 0; 3797 uint8_t ep; 3798 3799 /* config desc is NULL when opening ep0 */ 3800 if (dev == NULL || dev->ud_cdesc == NULL) 3801 goto no_cdcd; 3802 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3803 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3804 if (cdcd == NULL) 3805 goto no_cdcd; 3806 usb_desc_iter_init(dev, &iter); 3807 iter.cur = (const void *)cdcd; 3808 3809 /* find endpoint_ss_comp desc for ep of this pipe */ 3810 for (ep = 0;;) { 3811 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3812 if (cdcd == NULL) 3813 break; 3814 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3815 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3816 bEndpointAddress; 3817 if (UE_GET_ADDR(ep) == 3818 UE_GET_ADDR(ed->bEndpointAddress)) { 3819 cdcd = (const usb_cdc_descriptor_t *) 3820 usb_desc_iter_next(&iter); 3821 break; 3822 } 3823 ep = 0; 3824 } 3825 } 3826 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3827 const usb_endpoint_ss_comp_descriptor_t * esscd = 3828 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3829 maxb = esscd->bMaxBurst; 3830 mult = UE_GET_SS_ISO_MULT(esscd->bmAttributes); 3831 } 3832 3833 no_cdcd: 3834 /* 6.2.3.4, 4.8.2.4 */ 3835 if (USB_IS_SS(speed)) { 3836 /* USB 3.1 9.6.6 */ 3837 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3838 /* USB 3.1 9.6.7 */ 3839 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3840 #ifdef notyet 3841 if (xfertype == UE_ISOCHRONOUS) { 3842 } 3843 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3844 /* use ESIT */ 3845 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3846 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3847 3848 /* XXX if LEC = 1, set ESIT instead */ 3849 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3850 } else { 3851 /* use ival */ 3852 } 3853 #endif 3854 } else { 3855 /* USB 2.0 9.6.6 */ 3856 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3857 3858 /* 6.2.3.4 */ 3859 if (speed == USB_SPEED_HIGH && 3860 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3861 maxb = UE_GET_TRANS(mps); 3862 } else { 3863 /* LS/FS or HS CTRL or HS BULK */ 3864 maxb = 0; 3865 } 3866 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3867 } 3868 xpipe->xp_maxb = maxb + 1; 3869 xpipe->xp_mult = mult + 1; 3870 } 3871 3872 /* 3873 * Convert endpoint bInterval value to endpoint context interval value 3874 * for Interrupt pipe. 3875 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3876 */ 3877 static uint32_t 3878 xhci_bival2ival(uint32_t ival, uint32_t speed) 3879 { 3880 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3881 int i; 3882 3883 /* 3884 * round ival down to "the nearest base 2 multiple of 3885 * bInterval * 8". 3886 * bInterval is at most 255 as its type is uByte. 3887 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3888 */ 3889 for (i = 10; i > 0; i--) { 3890 if ((ival * 8) >= (1 << i)) 3891 break; 3892 } 3893 ival = i; 3894 } else { 3895 /* Interval = bInterval-1 for SS/HS */ 3896 ival--; 3897 } 3898 3899 return ival; 3900 } 3901 3902 /* ----- */ 3903 3904 static void 3905 xhci_noop(struct usbd_pipe *pipe) 3906 { 3907 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3908 } 3909 3910 /* 3911 * Process root hub request. 3912 */ 3913 static int 3914 xhci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 3915 void *buf, int buflen) 3916 { 3917 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3918 usb_port_status_t ps; 3919 int l, totlen = 0; 3920 uint16_t len, value, index; 3921 int port, i; 3922 uint32_t v; 3923 3924 XHCIHIST_FUNC(); 3925 3926 KASSERT(mutex_owned(&sc->sc_rhlock)); 3927 3928 if (sc->sc_dying) 3929 return -1; 3930 3931 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3932 3933 len = UGETW(req->wLength); 3934 value = UGETW(req->wValue); 3935 index = UGETW(req->wIndex); 3936 3937 XHCIHIST_CALLARGS("rhreq: %04jx %04jx %04jx %04jx", 3938 req->bmRequestType | (req->bRequest << 8), value, index, len); 3939 3940 #define C(x,y) ((x) | ((y) << 8)) 3941 switch (C(req->bRequest, req->bmRequestType)) { 3942 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3943 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3944 if (len == 0) 3945 break; 3946 switch (value) { 3947 #define sd ((usb_string_descriptor_t *)buf) 3948 case C(2, UDESC_STRING): 3949 /* Product */ 3950 totlen = usb_makestrdesc(sd, len, "xHCI root hub"); 3951 break; 3952 #undef sd 3953 default: 3954 /* default from usbroothub */ 3955 return buflen; 3956 } 3957 break; 3958 3959 /* Hub requests */ 3960 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3961 break; 3962 /* Clear Port Feature request */ 3963 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3964 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3965 3966 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3967 index, value, bn, cp); 3968 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3969 return -1; 3970 } 3971 port = XHCI_PORTSC(cp); 3972 v = xhci_op_read_4(sc, port); 3973 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3974 v &= ~XHCI_PS_CLEAR; 3975 switch (value) { 3976 case UHF_PORT_ENABLE: 3977 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3978 break; 3979 case UHF_PORT_SUSPEND: 3980 return -1; 3981 case UHF_PORT_POWER: 3982 break; 3983 case UHF_PORT_TEST: 3984 case UHF_PORT_INDICATOR: 3985 return -1; 3986 case UHF_C_PORT_CONNECTION: 3987 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3988 break; 3989 case UHF_C_PORT_ENABLE: 3990 case UHF_C_PORT_SUSPEND: 3991 case UHF_C_PORT_OVER_CURRENT: 3992 return -1; 3993 case UHF_C_BH_PORT_RESET: 3994 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3995 break; 3996 case UHF_C_PORT_RESET: 3997 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3998 break; 3999 case UHF_C_PORT_LINK_STATE: 4000 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 4001 break; 4002 case UHF_C_PORT_CONFIG_ERROR: 4003 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 4004 break; 4005 default: 4006 return -1; 4007 } 4008 break; 4009 } 4010 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 4011 if (len == 0) 4012 break; 4013 if ((value & 0xff) != 0) { 4014 return -1; 4015 } 4016 usb_hub_descriptor_t hubd; 4017 4018 totlen = uimin(buflen, sizeof(hubd)); 4019 memcpy(&hubd, buf, totlen); 4020 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 4021 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 4022 hubd.bPwrOn2PwrGood = 200; 4023 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 4024 /* XXX can't find out? */ 4025 hubd.DeviceRemovable[i++] = 0; 4026 } 4027 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 4028 totlen = uimin(totlen, hubd.bDescLength); 4029 memcpy(buf, &hubd, totlen); 4030 break; 4031 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 4032 if (len != 4) { 4033 return -1; 4034 } 4035 memset(buf, 0, len); /* ? XXX */ 4036 totlen = len; 4037 break; 4038 /* Get Port Status request */ 4039 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 4040 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 4041 4042 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 4043 bn, index, cp, 0); 4044 if (index < 1 || index > sc->sc_rhportcount[bn]) { 4045 DPRINTFN(5, "bad get port status: index=%jd bn=%jd " 4046 "portcount=%jd", 4047 index, bn, sc->sc_rhportcount[bn], 0); 4048 return -1; 4049 } 4050 if (len != 4) { 4051 DPRINTFN(5, "bad get port status: len %jd != 4", 4052 len, 0, 0, 0); 4053 return -1; 4054 } 4055 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 4056 DPRINTFN(4, "getrhportsc %jd 0x%08jx", cp, v, 0, 0); 4057 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 4058 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 4059 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 4060 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 4061 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 4062 if (v & XHCI_PS_PR) i |= UPS_RESET; 4063 if (v & XHCI_PS_PP) { 4064 if (i & UPS_OTHER_SPEED) 4065 i |= UPS_PORT_POWER_SS; 4066 else 4067 i |= UPS_PORT_POWER; 4068 } 4069 if (i & UPS_OTHER_SPEED) 4070 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 4071 if (sc->sc_vendor_port_status) 4072 i = sc->sc_vendor_port_status(sc, v, i); 4073 USETW(ps.wPortStatus, i); 4074 i = 0; 4075 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 4076 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 4077 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 4078 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 4079 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 4080 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 4081 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 4082 USETW(ps.wPortChange, i); 4083 totlen = uimin(len, sizeof(ps)); 4084 memcpy(buf, &ps, totlen); 4085 DPRINTFN(5, "get port status: wPortStatus %#jx wPortChange %#jx" 4086 " totlen %jd", 4087 UGETW(ps.wPortStatus), UGETW(ps.wPortChange), totlen, 0); 4088 break; 4089 } 4090 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 4091 return -1; 4092 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 4093 break; 4094 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 4095 break; 4096 /* Set Port Feature request */ 4097 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 4098 int optval = (index >> 8) & 0xff; 4099 index &= 0xff; 4100 if (index < 1 || index > sc->sc_rhportcount[bn]) { 4101 return -1; 4102 } 4103 4104 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 4105 4106 port = XHCI_PORTSC(cp); 4107 v = xhci_op_read_4(sc, port); 4108 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 4109 v &= ~XHCI_PS_CLEAR; 4110 switch (value) { 4111 case UHF_PORT_ENABLE: 4112 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 4113 break; 4114 case UHF_PORT_SUSPEND: 4115 /* XXX suspend */ 4116 break; 4117 case UHF_PORT_RESET: 4118 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 4119 /* Wait for reset to complete. */ 4120 for (i = 0; i < USB_PORT_ROOT_RESET_DELAY / 10; i++) { 4121 if (sc->sc_dying) { 4122 return -1; 4123 } 4124 v = xhci_op_read_4(sc, port); 4125 if ((v & XHCI_PS_PR) == 0) { 4126 break; 4127 } 4128 usb_delay_ms(&sc->sc_bus, 10); 4129 } 4130 break; 4131 case UHF_PORT_POWER: 4132 /* XXX power control */ 4133 break; 4134 /* XXX more */ 4135 case UHF_C_PORT_RESET: 4136 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 4137 break; 4138 case UHF_PORT_U1_TIMEOUT: 4139 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4140 return -1; 4141 } 4142 port = XHCI_PORTPMSC(cp); 4143 v = xhci_op_read_4(sc, port); 4144 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4145 index, cp, v, 0); 4146 v &= ~XHCI_PM3_U1TO_SET(0xff); 4147 v |= XHCI_PM3_U1TO_SET(optval); 4148 xhci_op_write_4(sc, port, v); 4149 break; 4150 case UHF_PORT_U2_TIMEOUT: 4151 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4152 return -1; 4153 } 4154 port = XHCI_PORTPMSC(cp); 4155 v = xhci_op_read_4(sc, port); 4156 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4157 index, cp, v, 0); 4158 v &= ~XHCI_PM3_U2TO_SET(0xff); 4159 v |= XHCI_PM3_U2TO_SET(optval); 4160 xhci_op_write_4(sc, port, v); 4161 break; 4162 default: 4163 return -1; 4164 } 4165 } 4166 break; 4167 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 4168 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 4169 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 4170 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 4171 break; 4172 default: 4173 /* default from usbroothub */ 4174 return buflen; 4175 } 4176 4177 return totlen; 4178 } 4179 4180 static int 4181 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 4182 void *buf, int buflen) 4183 { 4184 struct xhci_softc *sc = XHCI_BUS2SC(bus); 4185 int actlen; 4186 4187 mutex_enter(&sc->sc_rhlock); 4188 actlen = xhci_roothub_ctrl_locked(bus, req, buf, buflen); 4189 mutex_exit(&sc->sc_rhlock); 4190 4191 return actlen; 4192 } 4193 4194 /* root hub interrupt */ 4195 4196 static usbd_status 4197 xhci_root_intr_transfer(struct usbd_xfer *xfer) 4198 { 4199 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4200 4201 /* Pipe isn't running, start first */ 4202 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4203 } 4204 4205 /* Wait for roothub port status/change */ 4206 static usbd_status 4207 xhci_root_intr_start(struct usbd_xfer *xfer) 4208 { 4209 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4210 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4211 4212 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4213 4214 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4215 4216 if (sc->sc_dying) 4217 return USBD_IOERROR; 4218 4219 KASSERT(sc->sc_intrxfer[bn] == NULL); 4220 sc->sc_intrxfer[bn] = xfer; 4221 xfer->ux_status = USBD_IN_PROGRESS; 4222 4223 return USBD_IN_PROGRESS; 4224 } 4225 4226 static void 4227 xhci_root_intr_abort(struct usbd_xfer *xfer) 4228 { 4229 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4230 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4231 4232 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4233 4234 KASSERT(mutex_owned(&sc->sc_lock)); 4235 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4236 4237 /* If xfer has already completed, nothing to do here. */ 4238 if (sc->sc_intrxfer[bn] == NULL) 4239 return; 4240 4241 /* 4242 * Otherwise, sc->sc_intrxfer[bn] had better be this transfer. 4243 * Cancel it. 4244 */ 4245 KASSERT(sc->sc_intrxfer[bn] == xfer); 4246 xfer->ux_status = USBD_CANCELLED; 4247 usb_transfer_complete(xfer); 4248 } 4249 4250 static void 4251 xhci_root_intr_close(struct usbd_pipe *pipe) 4252 { 4253 struct xhci_softc * const sc __diagused = XHCI_PIPE2SC(pipe); 4254 const struct usbd_xfer *xfer __diagused = pipe->up_intrxfer; 4255 const size_t bn __diagused = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4256 4257 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4258 4259 KASSERT(mutex_owned(&sc->sc_lock)); 4260 4261 /* 4262 * Caller must guarantee the xfer has completed first, by 4263 * closing the pipe only after normal completion or an abort. 4264 */ 4265 KASSERT(sc->sc_intrxfer[bn] == NULL); 4266 } 4267 4268 static void 4269 xhci_root_intr_done(struct usbd_xfer *xfer) 4270 { 4271 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4272 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4273 4274 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4275 4276 KASSERT(mutex_owned(&sc->sc_lock)); 4277 4278 /* Claim the xfer so it doesn't get completed again. */ 4279 KASSERT(sc->sc_intrxfer[bn] == xfer); 4280 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 4281 sc->sc_intrxfer[bn] = NULL; 4282 } 4283 4284 /* -------------- */ 4285 /* device control */ 4286 4287 static usbd_status 4288 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 4289 { 4290 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4291 4292 /* Pipe isn't running, start first */ 4293 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4294 } 4295 4296 static usbd_status 4297 xhci_device_ctrl_start(struct usbd_xfer *xfer) 4298 { 4299 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4300 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4301 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4302 struct xhci_ring * const tr = xs->xs_xr[dci]; 4303 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4304 usb_device_request_t * const req = &xfer->ux_request; 4305 const bool isread = usbd_xfer_isread(xfer); 4306 const uint32_t len = UGETW(req->wLength); 4307 usb_dma_t * const dma = &xfer->ux_dmabuf; 4308 uint64_t parameter; 4309 uint32_t status; 4310 uint32_t control; 4311 u_int i; 4312 const bool polling = xhci_polling_p(sc); 4313 4314 XHCIHIST_FUNC(); 4315 XHCIHIST_CALLARGS("req: %04jx %04jx %04jx %04jx", 4316 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 4317 UGETW(req->wIndex), UGETW(req->wLength)); 4318 4319 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4320 4321 /* we rely on the bottom bits for extra info */ 4322 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 4323 (uintptr_t) xfer); 4324 4325 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 4326 4327 if (tr->is_halted) 4328 goto out; 4329 4330 i = 0; 4331 4332 /* setup phase */ 4333 parameter = le64dec(req); /* to keep USB endian after xhci_trb_put() */ 4334 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 4335 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 4336 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 4337 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 4338 XHCI_TRB_3_IDT_BIT; 4339 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4340 4341 if (len != 0) { 4342 /* data phase */ 4343 parameter = DMAADDR(dma, 0); 4344 KASSERTMSG(len <= 0x10000, "len %d", len); 4345 status = XHCI_TRB_2_IRQ_SET(0) | 4346 XHCI_TRB_2_TDSZ_SET(0) | 4347 XHCI_TRB_2_BYTES_SET(len); 4348 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 4349 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 4350 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 4351 XHCI_TRB_3_IOC_BIT; 4352 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4353 4354 usb_syncmem(dma, 0, len, 4355 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4356 } 4357 4358 parameter = 0; 4359 status = XHCI_TRB_2_IRQ_SET(0); 4360 /* the status stage has inverted direction */ 4361 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 4362 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 4363 XHCI_TRB_3_IOC_BIT; 4364 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4365 4366 if (!polling) 4367 mutex_enter(&tr->xr_lock); 4368 xhci_ring_put_xfer(sc, tr, xx, i); 4369 if (!polling) 4370 mutex_exit(&tr->xr_lock); 4371 4372 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4373 4374 out: if (xfer->ux_status == USBD_NOT_STARTED) { 4375 usbd_xfer_schedule_timeout(xfer); 4376 xfer->ux_status = USBD_IN_PROGRESS; 4377 } else { 4378 /* 4379 * We must be coming from xhci_pipe_restart -- timeout 4380 * already set up, nothing to do. 4381 */ 4382 } 4383 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 4384 4385 return USBD_IN_PROGRESS; 4386 } 4387 4388 static void 4389 xhci_device_ctrl_done(struct usbd_xfer *xfer) 4390 { 4391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4392 usb_device_request_t *req = &xfer->ux_request; 4393 int len = UGETW(req->wLength); 4394 int rd = req->bmRequestType & UT_READ; 4395 4396 if (len) 4397 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4398 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4399 } 4400 4401 static void 4402 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 4403 { 4404 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4405 4406 usbd_xfer_abort(xfer); 4407 } 4408 4409 static void 4410 xhci_device_ctrl_close(struct usbd_pipe *pipe) 4411 { 4412 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4413 4414 xhci_close_pipe(pipe); 4415 } 4416 4417 /* ------------------ */ 4418 /* device isochronous */ 4419 4420 static usbd_status 4421 xhci_device_isoc_transfer(struct usbd_xfer *xfer) 4422 { 4423 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4424 4425 return xhci_device_isoc_enter(xfer); 4426 } 4427 4428 static usbd_status 4429 xhci_device_isoc_enter(struct usbd_xfer *xfer) 4430 { 4431 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4432 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4433 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4434 struct xhci_ring * const tr = xs->xs_xr[dci]; 4435 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4436 struct xhci_pipe * const xpipe = (struct xhci_pipe *)xfer->ux_pipe; 4437 uint32_t len = xfer->ux_length; 4438 usb_dma_t * const dma = &xfer->ux_dmabuf; 4439 uint64_t parameter; 4440 uint32_t status; 4441 uint32_t control; 4442 uint32_t mfindex; 4443 uint32_t offs; 4444 int i, ival; 4445 const bool polling = xhci_polling_p(sc); 4446 const uint16_t MPS = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 4447 const uint16_t mps = UE_GET_SIZE(MPS); 4448 const uint8_t maxb = xpipe->xp_maxb; 4449 u_int tdpc, tbc, tlbpc; 4450 4451 XHCIHIST_FUNC(); 4452 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4453 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4454 4455 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4456 4457 if (sc->sc_dying) 4458 return USBD_IOERROR; 4459 4460 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4461 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4462 4463 const bool isread = usbd_xfer_isread(xfer); 4464 if (xfer->ux_length) 4465 usb_syncmem(dma, 0, xfer->ux_length, 4466 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4467 4468 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 4469 if (ival >= 1 && ival <= 16) 4470 ival = 1 << (ival - 1); 4471 else 4472 ival = 1; /* fake something up */ 4473 4474 if (xpipe->xp_isoc_next == -1) { 4475 mfindex = xhci_rt_read_4(sc, XHCI_MFINDEX); 4476 DPRINTF("mfindex %jx", (uintmax_t)mfindex, 0, 0, 0); 4477 mfindex = XHCI_MFINDEX_GET(mfindex + 1); 4478 mfindex /= USB_UFRAMES_PER_FRAME; 4479 mfindex += 7; /* 7 frames is max possible IST */ 4480 xpipe->xp_isoc_next = roundup2(mfindex, ival); 4481 } 4482 4483 offs = 0; 4484 for (i = 0; i < xfer->ux_nframes; i++) { 4485 len = xfer->ux_frlengths[i]; 4486 4487 tdpc = howmany(len, mps); 4488 tbc = howmany(tdpc, maxb) - 1; 4489 tlbpc = tdpc % maxb; 4490 tlbpc = tlbpc ? tlbpc - 1 : maxb - 1; 4491 4492 KASSERTMSG(len <= 0x10000, "len %d", len); 4493 parameter = DMAADDR(dma, offs); 4494 status = XHCI_TRB_2_IRQ_SET(0) | 4495 XHCI_TRB_2_TDSZ_SET(0) | 4496 XHCI_TRB_2_BYTES_SET(len); 4497 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 4498 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 4499 XHCI_TRB_3_TBC_SET(tbc) | 4500 XHCI_TRB_3_TLBPC_SET(tlbpc) | 4501 XHCI_TRB_3_IOC_BIT; 4502 if (XHCI_HCC_CFC(sc->sc_hcc)) { 4503 control |= XHCI_TRB_3_FRID_SET(xpipe->xp_isoc_next); 4504 #if 0 4505 } else if (xpipe->xp_isoc_next == -1) { 4506 control |= XHCI_TRB_3_FRID_SET(xpipe->xp_isoc_next); 4507 #endif 4508 } else { 4509 control |= XHCI_TRB_3_ISO_SIA_BIT; 4510 } 4511 #if 0 4512 if (i != xfer->ux_nframes - 1) 4513 control |= XHCI_TRB_3_BEI_BIT; 4514 #endif 4515 xhci_xfer_put_trb(xx, i, parameter, status, control); 4516 4517 xpipe->xp_isoc_next += ival; 4518 offs += len; 4519 } 4520 4521 xx->xx_isoc_done = 0; 4522 4523 if (!polling) 4524 mutex_enter(&tr->xr_lock); 4525 xhci_ring_put_xfer(sc, tr, xx, i); 4526 if (!polling) 4527 mutex_exit(&tr->xr_lock); 4528 4529 xfer->ux_status = USBD_IN_PROGRESS; 4530 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4531 usbd_xfer_schedule_timeout(xfer); 4532 4533 return USBD_IN_PROGRESS; 4534 } 4535 4536 static void 4537 xhci_device_isoc_abort(struct usbd_xfer *xfer) 4538 { 4539 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4540 4541 usbd_xfer_abort(xfer); 4542 } 4543 4544 static void 4545 xhci_device_isoc_close(struct usbd_pipe *pipe) 4546 { 4547 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4548 4549 xhci_close_pipe(pipe); 4550 } 4551 4552 static void 4553 xhci_device_isoc_done(struct usbd_xfer *xfer) 4554 { 4555 #ifdef USB_DEBUG 4556 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4557 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4558 #endif 4559 const bool isread = usbd_xfer_isread(xfer); 4560 4561 XHCIHIST_FUNC(); 4562 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4563 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4564 4565 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4566 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4567 } 4568 4569 /* ----------- */ 4570 /* device bulk */ 4571 4572 static usbd_status 4573 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 4574 { 4575 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4576 4577 /* Pipe isn't running, so start it first. */ 4578 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4579 } 4580 4581 static usbd_status 4582 xhci_device_bulk_start(struct usbd_xfer *xfer) 4583 { 4584 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4585 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4586 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4587 struct xhci_ring * const tr = xs->xs_xr[dci]; 4588 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4589 const uint32_t len = xfer->ux_length; 4590 usb_dma_t * const dma = &xfer->ux_dmabuf; 4591 uint64_t parameter; 4592 uint32_t status; 4593 uint32_t control; 4594 u_int i = 0; 4595 const bool polling = xhci_polling_p(sc); 4596 4597 XHCIHIST_FUNC(); 4598 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4599 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4600 4601 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4602 4603 if (sc->sc_dying) 4604 return USBD_IOERROR; 4605 4606 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4607 4608 if (tr->is_halted) 4609 goto out; 4610 4611 parameter = DMAADDR(dma, 0); 4612 const bool isread = usbd_xfer_isread(xfer); 4613 if (len) 4614 usb_syncmem(dma, 0, len, 4615 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4616 4617 /* 4618 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 4619 * If the user supplied buffer crosses such a boundary then 2 4620 * (or more) TRB should be used. 4621 * If multiple TRB are used the td_size field must be set correctly. 4622 * For v1.0 devices (like ivy bridge) this is the number of usb data 4623 * blocks needed to complete the transfer. 4624 * Setting it to 1 in the last TRB causes an extra zero-length 4625 * data block be sent. 4626 * The earlier documentation differs, I don't know how it behaves. 4627 */ 4628 KASSERTMSG(len <= 0x10000, "len %d", len); 4629 status = XHCI_TRB_2_IRQ_SET(0) | 4630 XHCI_TRB_2_TDSZ_SET(0) | 4631 XHCI_TRB_2_BYTES_SET(len); 4632 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4633 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 4634 XHCI_TRB_3_IOC_BIT; 4635 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4636 4637 if (!polling) 4638 mutex_enter(&tr->xr_lock); 4639 xhci_ring_put_xfer(sc, tr, xx, i); 4640 if (!polling) 4641 mutex_exit(&tr->xr_lock); 4642 4643 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4644 4645 out: if (xfer->ux_status == USBD_NOT_STARTED) { 4646 xfer->ux_status = USBD_IN_PROGRESS; 4647 usbd_xfer_schedule_timeout(xfer); 4648 } else { 4649 /* 4650 * We must be coming from xhci_pipe_restart -- timeout 4651 * already set up, nothing to do. 4652 */ 4653 } 4654 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 4655 4656 return USBD_IN_PROGRESS; 4657 } 4658 4659 static void 4660 xhci_device_bulk_done(struct usbd_xfer *xfer) 4661 { 4662 #ifdef USB_DEBUG 4663 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4664 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4665 #endif 4666 const bool isread = usbd_xfer_isread(xfer); 4667 4668 XHCIHIST_FUNC(); 4669 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4670 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4671 4672 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4673 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4674 } 4675 4676 static void 4677 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4678 { 4679 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4680 4681 usbd_xfer_abort(xfer); 4682 } 4683 4684 static void 4685 xhci_device_bulk_close(struct usbd_pipe *pipe) 4686 { 4687 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4688 4689 xhci_close_pipe(pipe); 4690 } 4691 4692 /* ---------------- */ 4693 /* device interrupt */ 4694 4695 static usbd_status 4696 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4697 { 4698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4699 4700 /* Pipe isn't running, so start it first. */ 4701 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4702 } 4703 4704 static usbd_status 4705 xhci_device_intr_start(struct usbd_xfer *xfer) 4706 { 4707 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4708 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4709 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4710 struct xhci_ring * const tr = xs->xs_xr[dci]; 4711 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4712 const uint32_t len = xfer->ux_length; 4713 const bool polling = xhci_polling_p(sc); 4714 usb_dma_t * const dma = &xfer->ux_dmabuf; 4715 uint64_t parameter; 4716 uint32_t status; 4717 uint32_t control; 4718 u_int i = 0; 4719 4720 XHCIHIST_FUNC(); 4721 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4722 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4723 4724 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4725 4726 if (sc->sc_dying) 4727 return USBD_IOERROR; 4728 4729 if (tr->is_halted) 4730 goto out; 4731 4732 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4733 4734 const bool isread = usbd_xfer_isread(xfer); 4735 if (len) 4736 usb_syncmem(dma, 0, len, 4737 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4738 4739 parameter = DMAADDR(dma, 0); 4740 KASSERTMSG(len <= 0x10000, "len %d", len); 4741 status = XHCI_TRB_2_IRQ_SET(0) | 4742 XHCI_TRB_2_TDSZ_SET(0) | 4743 XHCI_TRB_2_BYTES_SET(len); 4744 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4745 (isread ? XHCI_TRB_3_ISP_BIT : 0) | XHCI_TRB_3_IOC_BIT; 4746 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4747 4748 if (!polling) 4749 mutex_enter(&tr->xr_lock); 4750 xhci_ring_put_xfer(sc, tr, xx, i); 4751 if (!polling) 4752 mutex_exit(&tr->xr_lock); 4753 4754 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4755 4756 out: if (xfer->ux_status == USBD_NOT_STARTED) { 4757 xfer->ux_status = USBD_IN_PROGRESS; 4758 usbd_xfer_schedule_timeout(xfer); 4759 } else { 4760 /* 4761 * We must be coming from xhci_pipe_restart -- timeout 4762 * already set up, nothing to do. 4763 */ 4764 } 4765 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 4766 4767 return USBD_IN_PROGRESS; 4768 } 4769 4770 static void 4771 xhci_device_intr_done(struct usbd_xfer *xfer) 4772 { 4773 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4774 #ifdef USB_DEBUG 4775 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4776 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4777 #endif 4778 const bool isread = usbd_xfer_isread(xfer); 4779 4780 XHCIHIST_FUNC(); 4781 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4782 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4783 4784 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4785 4786 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4787 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4788 } 4789 4790 static void 4791 xhci_device_intr_abort(struct usbd_xfer *xfer) 4792 { 4793 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4794 4795 XHCIHIST_FUNC(); 4796 XHCIHIST_CALLARGS("%#jx", (uintptr_t)xfer, 0, 0, 0); 4797 4798 KASSERT(mutex_owned(&sc->sc_lock)); 4799 usbd_xfer_abort(xfer); 4800 } 4801 4802 static void 4803 xhci_device_intr_close(struct usbd_pipe *pipe) 4804 { 4805 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4806 4807 XHCIHIST_FUNC(); 4808 XHCIHIST_CALLARGS("%#jx", (uintptr_t)pipe, 0, 0, 0); 4809 4810 xhci_close_pipe(pipe); 4811 } 4812
Indexes created Wed Oct 01 18:09:54 GMT 2025