xhci.c revision 1.175.2.1
1 /* $NetBSD: xhci.c,v 1.175.2.1 2023/08/01 13:43:34 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.175.2.1 2023/08/01 13:43:34 martin Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(xhcidebug,FMT,A,B,C,D) 118 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 119 #define XHCIHIST_FUNC() USBHIST_FUNC() 120 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 121 #define XHCIHIST_CALLARGS(FMT,A,B,C,D) \ 122 USBHIST_CALLARGS(xhcidebug,FMT,A,B,C,D) 123 124 #define XHCI_DCI_SLOT 0 125 #define XHCI_DCI_EP_CONTROL 1 126 127 #define XHCI_ICI_INPUT_CONTROL 0 128 129 struct xhci_pipe { 130 struct usbd_pipe xp_pipe; 131 struct usb_task xp_async_task; 132 int16_t xp_isoc_next; /* next frame */ 133 uint8_t xp_maxb; /* max burst */ 134 uint8_t xp_mult; 135 }; 136 137 #define XHCI_COMMAND_RING_TRBS 256 138 #define XHCI_EVENT_RING_TRBS 256 139 #define XHCI_EVENT_RING_SEGMENTS 1 140 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 141 142 static usbd_status xhci_open(struct usbd_pipe *); 143 static void xhci_close_pipe(struct usbd_pipe *); 144 static int xhci_intr1(struct xhci_softc * const); 145 static void xhci_softintr(void *); 146 static void xhci_poll(struct usbd_bus *); 147 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 148 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 149 static void xhci_abortx(struct usbd_xfer *); 150 static bool xhci_dying(struct usbd_bus *); 151 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 152 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 153 struct usbd_port *); 154 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 155 void *, int); 156 157 static void xhci_pipe_restart(struct usbd_pipe *); 158 static void xhci_pipe_restart_async_task(void *); 159 static void xhci_pipe_restart_async(struct usbd_pipe *); 160 161 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 162 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 163 static void xhci_reset_endpoint(struct usbd_pipe *); 164 static usbd_status xhci_stop_endpoint_cmd(struct xhci_softc *, 165 struct xhci_slot *, u_int, uint32_t); 166 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 167 168 static void xhci_host_dequeue(struct xhci_ring * const); 169 static void xhci_set_dequeue(struct usbd_pipe *); 170 171 static usbd_status xhci_do_command(struct xhci_softc * const, 172 struct xhci_soft_trb * const, int); 173 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 174 struct xhci_soft_trb * const, int); 175 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 176 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *); 177 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 178 static usbd_status xhci_enable_slot(struct xhci_softc * const, 179 uint8_t * const); 180 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 181 static usbd_status xhci_address_device(struct xhci_softc * const, 182 uint64_t, uint8_t, bool); 183 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 184 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 185 struct xhci_slot * const, u_int); 186 static usbd_status xhci_ring_init(struct xhci_softc * const, 187 struct xhci_ring **, size_t, size_t); 188 static void xhci_ring_free(struct xhci_softc * const, 189 struct xhci_ring ** const); 190 191 static void xhci_setup_ctx(struct usbd_pipe *); 192 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 193 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 194 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 195 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 196 197 static void xhci_noop(struct usbd_pipe *); 198 199 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 200 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 201 static void xhci_root_intr_abort(struct usbd_xfer *); 202 static void xhci_root_intr_close(struct usbd_pipe *); 203 static void xhci_root_intr_done(struct usbd_xfer *); 204 205 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 206 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 207 static void xhci_device_ctrl_abort(struct usbd_xfer *); 208 static void xhci_device_ctrl_close(struct usbd_pipe *); 209 static void xhci_device_ctrl_done(struct usbd_xfer *); 210 211 static usbd_status xhci_device_isoc_transfer(struct usbd_xfer *); 212 static usbd_status xhci_device_isoc_enter(struct usbd_xfer *); 213 static void xhci_device_isoc_abort(struct usbd_xfer *); 214 static void xhci_device_isoc_close(struct usbd_pipe *); 215 static void xhci_device_isoc_done(struct usbd_xfer *); 216 217 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 218 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 219 static void xhci_device_intr_abort(struct usbd_xfer *); 220 static void xhci_device_intr_close(struct usbd_pipe *); 221 static void xhci_device_intr_done(struct usbd_xfer *); 222 223 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 224 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 225 static void xhci_device_bulk_abort(struct usbd_xfer *); 226 static void xhci_device_bulk_close(struct usbd_pipe *); 227 static void xhci_device_bulk_done(struct usbd_xfer *); 228 229 static const struct usbd_bus_methods xhci_bus_methods = { 230 .ubm_open = xhci_open, 231 .ubm_softint = xhci_softintr, 232 .ubm_dopoll = xhci_poll, 233 .ubm_allocx = xhci_allocx, 234 .ubm_freex = xhci_freex, 235 .ubm_abortx = xhci_abortx, 236 .ubm_dying = xhci_dying, 237 .ubm_getlock = xhci_get_lock, 238 .ubm_newdev = xhci_new_device, 239 .ubm_rhctrl = xhci_roothub_ctrl, 240 }; 241 242 static const struct usbd_pipe_methods xhci_root_intr_methods = { 243 .upm_transfer = xhci_root_intr_transfer, 244 .upm_start = xhci_root_intr_start, 245 .upm_abort = xhci_root_intr_abort, 246 .upm_close = xhci_root_intr_close, 247 .upm_cleartoggle = xhci_noop, 248 .upm_done = xhci_root_intr_done, 249 }; 250 251 252 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 253 .upm_transfer = xhci_device_ctrl_transfer, 254 .upm_start = xhci_device_ctrl_start, 255 .upm_abort = xhci_device_ctrl_abort, 256 .upm_close = xhci_device_ctrl_close, 257 .upm_cleartoggle = xhci_noop, 258 .upm_done = xhci_device_ctrl_done, 259 }; 260 261 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 262 .upm_transfer = xhci_device_isoc_transfer, 263 .upm_abort = xhci_device_isoc_abort, 264 .upm_close = xhci_device_isoc_close, 265 .upm_cleartoggle = xhci_noop, 266 .upm_done = xhci_device_isoc_done, 267 }; 268 269 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 270 .upm_transfer = xhci_device_bulk_transfer, 271 .upm_start = xhci_device_bulk_start, 272 .upm_abort = xhci_device_bulk_abort, 273 .upm_close = xhci_device_bulk_close, 274 .upm_cleartoggle = xhci_noop, 275 .upm_done = xhci_device_bulk_done, 276 }; 277 278 static const struct usbd_pipe_methods xhci_device_intr_methods = { 279 .upm_transfer = xhci_device_intr_transfer, 280 .upm_start = xhci_device_intr_start, 281 .upm_abort = xhci_device_intr_abort, 282 .upm_close = xhci_device_intr_close, 283 .upm_cleartoggle = xhci_noop, 284 .upm_done = xhci_device_intr_done, 285 }; 286 287 static inline uint32_t 288 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 289 { 290 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 291 } 292 293 static inline uint32_t 294 xhci_read_2(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, offset); 297 } 298 299 static inline uint32_t 300 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 301 { 302 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 303 } 304 305 static inline void 306 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 307 uint32_t value) 308 { 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 310 } 311 312 #if 0 /* unused */ 313 static inline void 314 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 315 uint32_t value) 316 { 317 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 318 } 319 #endif /* unused */ 320 321 static inline uint32_t 322 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 323 { 324 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 325 } 326 327 static inline uint32_t 328 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 329 { 330 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 331 } 332 333 static inline void 334 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 335 uint32_t value) 336 { 337 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 338 } 339 340 static inline uint64_t 341 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 342 { 343 uint64_t value; 344 345 #ifdef XHCI_USE_BUS_SPACE_8 346 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 347 #else 348 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 349 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 350 offset + 4) << 32; 351 #endif 352 353 return value; 354 } 355 356 static inline void 357 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 358 uint64_t value) 359 { 360 #ifdef XHCI_USE_BUS_SPACE_8 361 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 362 #else 363 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 364 (value >> 0) & 0xffffffff); 365 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 366 (value >> 32) & 0xffffffff); 367 #endif 368 } 369 370 static inline uint32_t 371 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 372 { 373 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 374 } 375 376 static inline void 377 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 378 uint32_t value) 379 { 380 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 381 } 382 383 static inline uint64_t 384 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 385 { 386 uint64_t value; 387 388 #ifdef XHCI_USE_BUS_SPACE_8 389 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 390 #else 391 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 392 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 393 offset + 4) << 32; 394 #endif 395 396 return value; 397 } 398 399 static inline void 400 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 401 uint64_t value) 402 { 403 #ifdef XHCI_USE_BUS_SPACE_8 404 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 405 #else 406 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 407 (value >> 0) & 0xffffffff); 408 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 409 (value >> 32) & 0xffffffff); 410 #endif 411 } 412 413 #if 0 /* unused */ 414 static inline uint32_t 415 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 416 { 417 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 418 } 419 #endif /* unused */ 420 421 static inline void 422 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 423 uint32_t value) 424 { 425 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 426 } 427 428 /* --- */ 429 430 static inline uint8_t 431 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 432 { 433 u_int eptype = 0; 434 435 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 436 case UE_CONTROL: 437 eptype = 0x0; 438 break; 439 case UE_ISOCHRONOUS: 440 eptype = 0x1; 441 break; 442 case UE_BULK: 443 eptype = 0x2; 444 break; 445 case UE_INTERRUPT: 446 eptype = 0x3; 447 break; 448 } 449 450 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 451 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 452 return eptype | 0x4; 453 else 454 return eptype; 455 } 456 457 static u_int 458 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 459 { 460 /* xHCI 1.0 section 4.5.1 */ 461 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 462 u_int in = 0; 463 464 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 465 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 466 in = 1; 467 468 return epaddr * 2 + in; 469 } 470 471 static inline u_int 472 xhci_dci_to_ici(const u_int i) 473 { 474 return i + 1; 475 } 476 477 static inline void * 478 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 479 const u_int dci) 480 { 481 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 482 } 483 484 #if 0 /* unused */ 485 static inline bus_addr_t 486 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 487 const u_int dci) 488 { 489 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 490 } 491 #endif /* unused */ 492 493 static inline void * 494 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 495 const u_int ici) 496 { 497 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 498 } 499 500 static inline bus_addr_t 501 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 502 const u_int ici) 503 { 504 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 505 } 506 507 static inline struct xhci_trb * 508 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 509 { 510 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 511 } 512 513 static inline bus_addr_t 514 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 515 { 516 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 517 } 518 519 static inline void 520 xhci_xfer_put_trb(struct xhci_xfer * const xx, u_int idx, 521 uint64_t parameter, uint32_t status, uint32_t control) 522 { 523 KASSERTMSG(idx < xx->xx_ntrb, "idx=%u xx_ntrb=%u", idx, xx->xx_ntrb); 524 xx->xx_trb[idx].trb_0 = parameter; 525 xx->xx_trb[idx].trb_2 = status; 526 xx->xx_trb[idx].trb_3 = control; 527 } 528 529 static inline void 530 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 531 uint32_t control) 532 { 533 trb->trb_0 = htole64(parameter); 534 trb->trb_2 = htole32(status); 535 trb->trb_3 = htole32(control); 536 } 537 538 static int 539 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 540 { 541 /* base address of TRBs */ 542 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 543 544 /* trb_0 range sanity check */ 545 if (trb_0 == 0 || trb_0 < trbp || 546 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 547 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 548 return 1; 549 } 550 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 551 return 0; 552 } 553 554 static unsigned int 555 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 556 u_int dci) 557 { 558 uint32_t *cp; 559 560 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 561 cp = xhci_slot_get_dcv(sc, xs, dci); 562 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 563 } 564 565 static inline unsigned int 566 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 567 { 568 const unsigned int port = ctlrport - 1; 569 const uint8_t bit = __BIT(port % NBBY); 570 571 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 572 } 573 574 /* 575 * Return the roothub port for a controller port. Both are 1..n. 576 */ 577 static inline unsigned int 578 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 579 { 580 581 return sc->sc_ctlrportmap[ctrlport - 1]; 582 } 583 584 /* 585 * Return the controller port for a bus roothub port. Both are 1..n. 586 */ 587 static inline unsigned int 588 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 589 unsigned int rhport) 590 { 591 592 return sc->sc_rhportmap[bn][rhport - 1]; 593 } 594 595 /* --- */ 596 597 void 598 xhci_childdet(device_t self, device_t child) 599 { 600 struct xhci_softc * const sc = device_private(self); 601 602 mutex_enter(&sc->sc_intr_lock); 603 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 604 if (child == sc->sc_child2) 605 sc->sc_child2 = NULL; 606 else if (child == sc->sc_child) 607 sc->sc_child = NULL; 608 mutex_exit(&sc->sc_intr_lock); 609 } 610 611 int 612 xhci_detach(struct xhci_softc *sc, int flags) 613 { 614 int rv = 0; 615 616 if (sc->sc_child2 != NULL) { 617 rv = config_detach(sc->sc_child2, flags); 618 if (rv != 0) 619 return rv; 620 KASSERT(sc->sc_child2 == NULL); 621 } 622 623 if (sc->sc_child != NULL) { 624 rv = config_detach(sc->sc_child, flags); 625 if (rv != 0) 626 return rv; 627 KASSERT(sc->sc_child == NULL); 628 } 629 630 /* XXX unconfigure/free slots */ 631 632 /* verify: */ 633 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 634 xhci_op_write_4(sc, XHCI_USBCMD, 0); 635 /* do we need to wait for stop? */ 636 637 xhci_op_write_8(sc, XHCI_CRCR, 0); 638 xhci_ring_free(sc, &sc->sc_cr); 639 cv_destroy(&sc->sc_command_cv); 640 cv_destroy(&sc->sc_cmdbusy_cv); 641 642 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 643 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 644 xhci_rt_write_8(sc, XHCI_ERDP(0), 0 | XHCI_ERDP_BUSY); 645 xhci_ring_free(sc, &sc->sc_er); 646 647 usb_freemem(&sc->sc_eventst_dma); 648 649 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 650 usb_freemem(&sc->sc_dcbaa_dma); 651 652 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 653 654 kmem_free(sc->sc_ctlrportbus, 655 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 656 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 657 658 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 659 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 660 } 661 662 mutex_destroy(&sc->sc_rhlock); 663 mutex_destroy(&sc->sc_lock); 664 mutex_destroy(&sc->sc_intr_lock); 665 666 pool_cache_destroy(sc->sc_xferpool); 667 668 return rv; 669 } 670 671 int 672 xhci_activate(device_t self, enum devact act) 673 { 674 struct xhci_softc * const sc = device_private(self); 675 676 switch (act) { 677 case DVACT_DEACTIVATE: 678 sc->sc_dying = true; 679 return 0; 680 default: 681 return EOPNOTSUPP; 682 } 683 } 684 685 bool 686 xhci_suspend(device_t self, const pmf_qual_t *qual) 687 { 688 struct xhci_softc * const sc = device_private(self); 689 size_t i, j, bn, dci; 690 int port; 691 uint32_t v; 692 usbd_status err; 693 bool ok = false; 694 695 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 696 697 /* 698 * Block issuance of new commands, and wait for all pending 699 * commands to complete. 700 */ 701 mutex_enter(&sc->sc_lock); 702 KASSERT(sc->sc_suspender == NULL); 703 sc->sc_suspender = curlwp; 704 while (sc->sc_command_addr != 0) 705 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 706 mutex_exit(&sc->sc_lock); 707 708 /* 709 * Block roothub xfers which might touch portsc registers until 710 * we're done suspending. 711 */ 712 mutex_enter(&sc->sc_rhlock); 713 714 /* 715 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 716 * xHCI Power Management, p. 342 717 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=342 718 */ 719 720 /* 721 * `1. Stop all USB activity by issuing Stop Endpoint Commands 722 * for Busy endpoints in the Running state. If the Force 723 * Save Context Capability (FSC = ``0'') is not supported, 724 * then Stop Endpoint Commands shall be issued for all idle 725 * endpoints in the Running state as well. The Stop 726 * Endpoint Command causes the xHC to update the respective 727 * Endpoint or Stream Contexts in system memory, e.g. the 728 * TR Dequeue Pointer, DCS, etc. fields. Refer to 729 * Implementation Note "0".' 730 */ 731 for (i = 0; i < sc->sc_maxslots; i++) { 732 struct xhci_slot *xs = &sc->sc_slots[i]; 733 734 /* Skip if the slot is not in use. */ 735 if (xs->xs_idx == 0) 736 continue; 737 738 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 739 /* Skip if the endpoint is not Running. */ 740 /* XXX What about Busy? */ 741 if (xhci_get_epstate(sc, xs, dci) != 742 XHCI_EPSTATE_RUNNING) 743 continue; 744 745 /* Stop endpoint. */ 746 mutex_enter(&sc->sc_lock); 747 err = xhci_stop_endpoint_cmd(sc, xs, dci, 748 XHCI_TRB_3_SUSP_EP_BIT); 749 mutex_exit(&sc->sc_lock); 750 if (err) { 751 device_printf(self, "failed to stop endpoint" 752 " slot %zu dci %zu err %d\n", 753 i, dci, err); 754 goto out; 755 } 756 } 757 } 758 759 /* 760 * Next, suspend all the ports: 761 * 762 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.15: 763 * Suspend-Resume, pp. 276-283 764 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=276 765 */ 766 for (bn = 0; bn < 2; bn++) { 767 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 768 /* 4.15.1: Port Suspend. */ 769 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 770 771 /* 772 * `System software places individual ports 773 * into suspend mode by writing a ``3'' into 774 * the appropriate PORTSC register Port Link 775 * State (PLS) field (refer to Section 5.4.8). 776 * Software should only set the PLS field to 777 * ``3'' when the port is in the Enabled 778 * state.' 779 * 780 * `Software should not attempt to suspend a 781 * port unless the port reports that it is in 782 * the enabled (PED = ``1''; PLS < ``3'') 783 * state (refer to Section 5.4.8 for more 784 * information about PED and PLS).' 785 */ 786 v = xhci_op_read_4(sc, port); 787 if (((v & XHCI_PS_PED) == 0) || 788 XHCI_PS_PLS_GET(v) >= XHCI_PS_PLS_U3) 789 continue; 790 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 791 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU3); 792 xhci_op_write_4(sc, port, v); 793 794 /* 795 * `When the PLS field is written with U3 796 * (``3''), the status of the PLS bit will not 797 * change to the target U state U3 until the 798 * suspend signaling has completed to the 799 * attached device (which may be as long as 800 * 10ms.).' 801 * 802 * `Software is required to wait for U3 803 * transitions to complete before it puts the 804 * xHC into a low power state, and before 805 * resuming the port.' 806 * 807 * XXX Take advantage of the technique to 808 * reduce polling on host controllers that 809 * support the U3C capability. 810 */ 811 for (j = 0; j < XHCI_WAIT_PLS_U3; j++) { 812 v = xhci_op_read_4(sc, port); 813 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U3) 814 break; 815 usb_delay_ms(&sc->sc_bus, 1); 816 } 817 if (j == XHCI_WAIT_PLS_U3) { 818 device_printf(self, 819 "suspend timeout on bus %zu port %zu\n", 820 bn, i); 821 goto out; 822 } 823 } 824 } 825 826 /* 827 * `2. Ensure that the Command Ring is in the Stopped state 828 * (CRR = ``0'') or Idle (i.e. the Command Transfer Ring is 829 * empty), and all Command Completion Events associated 830 * with them have been received.' 831 * 832 * XXX 833 */ 834 835 /* `3. Stop the controller by setting Run/Stop (R/S) = ``0''.' */ 836 xhci_op_write_4(sc, XHCI_USBCMD, 837 xhci_op_read_4(sc, XHCI_USBCMD) & ~XHCI_CMD_RS); 838 839 /* 840 * `4. Read the Operational Runtime, and VTIO registers in the 841 * following order: USBCMD, DNCTRL, DCBAAP, CONFIG, ERSTSZ, 842 * ERSTBA, ERDP, IMAN, IMOD, and VTIO and save their 843 * state.' 844 * 845 * (We don't use VTIO here (XXX for now?).) 846 */ 847 sc->sc_regs.usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 848 sc->sc_regs.dnctrl = xhci_op_read_4(sc, XHCI_DNCTRL); 849 sc->sc_regs.dcbaap = xhci_op_read_8(sc, XHCI_DCBAAP); 850 sc->sc_regs.config = xhci_op_read_4(sc, XHCI_CONFIG); 851 sc->sc_regs.erstsz0 = xhci_rt_read_4(sc, XHCI_ERSTSZ(0)); 852 sc->sc_regs.erstba0 = xhci_rt_read_8(sc, XHCI_ERSTBA(0)); 853 sc->sc_regs.erdp0 = xhci_rt_read_8(sc, XHCI_ERDP(0)); 854 sc->sc_regs.iman0 = xhci_rt_read_4(sc, XHCI_IMAN(0)); 855 sc->sc_regs.imod0 = xhci_rt_read_4(sc, XHCI_IMOD(0)); 856 857 /* 858 * `5. Set the Controller Save State (CSS) flag in the USBCMD 859 * register (5.4.1)...' 860 */ 861 xhci_op_write_4(sc, XHCI_USBCMD, 862 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CSS); 863 864 /* 865 * `...and wait for the Save State Status (SSS) flag in the 866 * USBSTS register (5.4.2) to transition to ``0''.' 867 */ 868 for (i = 0; i < XHCI_WAIT_SSS; i++) { 869 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SSS) == 0) 870 break; 871 usb_delay_ms(&sc->sc_bus, 1); 872 } 873 if (i >= XHCI_WAIT_SSS) { 874 device_printf(self, "suspend timeout, USBSTS.SSS\n"); 875 /* 876 * Just optimistically go on and check SRE anyway -- 877 * what's the worst that could happen? 878 */ 879 } 880 881 /* 882 * `Note: After a Save or Restore operation completes, the 883 * Save/Restore Error (SRE) flag in the USBSTS register should 884 * be checked to ensure that the operation completed 885 * successfully.' 886 */ 887 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 888 device_printf(self, "suspend error, USBSTS.SRE\n"); 889 goto out; 890 } 891 892 /* Success! */ 893 ok = true; 894 895 out: mutex_exit(&sc->sc_rhlock); 896 if (!ok) { 897 /* 898 * If suspend failed, resume command issuance. 899 */ 900 mutex_enter(&sc->sc_lock); 901 KASSERT(sc->sc_suspender == curlwp); 902 sc->sc_suspender = NULL; 903 cv_broadcast(&sc->sc_cmdbusy_cv); 904 mutex_exit(&sc->sc_lock); 905 } 906 return ok; 907 } 908 909 bool 910 xhci_resume(device_t self, const pmf_qual_t *qual) 911 { 912 struct xhci_softc * const sc = device_private(self); 913 size_t i, j, bn, dci; 914 int port; 915 uint32_t v; 916 bool ok = false; 917 918 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 919 920 KASSERT(sc->sc_suspender); 921 922 /* 923 * Block roothub xfers which might touch portsc registers until 924 * we're done resuming. 925 */ 926 mutex_enter(&sc->sc_rhlock); 927 928 /* 929 * xHCI Requirements Specification 1.2, May 2019, Sec. 4.23.2: 930 * xHCI Power Management, p. 343 931 * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf#page=343 932 */ 933 934 /* 935 * `4. Restore the Operational Runtime, and VTIO registers with 936 * their previously saved state in the following order: 937 * DNCTRL, DCBAAP, CONFIG, ERSTSZ, ERSTBA, ERDP, IMAN, 938 * IMOD, and VTIO.' 939 * 940 * (We don't use VTIO here (for now?).) 941 */ 942 xhci_op_write_4(sc, XHCI_USBCMD, sc->sc_regs.usbcmd); 943 xhci_op_write_4(sc, XHCI_DNCTRL, sc->sc_regs.dnctrl); 944 xhci_op_write_8(sc, XHCI_DCBAAP, sc->sc_regs.dcbaap); 945 xhci_op_write_4(sc, XHCI_CONFIG, sc->sc_regs.config); 946 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), sc->sc_regs.erstsz0); 947 xhci_rt_write_8(sc, XHCI_ERSTBA(0), sc->sc_regs.erstba0); 948 xhci_rt_write_8(sc, XHCI_ERDP(0), sc->sc_regs.erdp0); 949 xhci_rt_write_4(sc, XHCI_IMAN(0), sc->sc_regs.iman0); 950 xhci_rt_write_4(sc, XHCI_IMOD(0), sc->sc_regs.imod0); 951 952 memset(&sc->sc_regs, 0, sizeof(sc->sc_regs)); /* paranoia */ 953 954 /* 955 * `5. Set the Controller Restore State (CRS) flag in the 956 * USBCMD register (5.4.1) to ``1''...' 957 */ 958 xhci_op_write_4(sc, XHCI_USBCMD, 959 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_CRS); 960 961 /* 962 * `...and wait for the Restore State Status (RSS) in the 963 * USBSTS register (5.4.2) to transition to ``0''.' 964 */ 965 for (i = 0; i < XHCI_WAIT_RSS; i++) { 966 if ((xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_RSS) == 0) 967 break; 968 usb_delay_ms(&sc->sc_bus, 1); 969 } 970 if (i >= XHCI_WAIT_RSS) { 971 device_printf(self, "resume timeout, USBSTS.RSS\n"); 972 goto out; 973 } 974 975 /* 976 * `6. Reinitialize the Command Ring, i.e. so its Cycle bits 977 * are consistent with the RCS values to be written to the 978 * CRCR.' 979 * 980 * XXX Hope just zeroing it is good enough! 981 */ 982 xhci_host_dequeue(sc->sc_cr); 983 984 /* 985 * `7. Write the CRCR with the address and RCS value of the 986 * reinitialized Command Ring. Note that this write will 987 * cause the Command Ring to restart at the address 988 * specified by the CRCR.' 989 */ 990 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) | 991 sc->sc_cr->xr_cs); 992 993 /* 994 * `8. Enable the controller by setting Run/Stop (R/S) = 995 * ``1''.' 996 */ 997 xhci_op_write_4(sc, XHCI_USBCMD, 998 xhci_op_read_4(sc, XHCI_USBCMD) | XHCI_CMD_RS); 999 1000 /* 1001 * `9. Software shall walk the USB topology and initialize each 1002 * of the xHC PORTSC, PORTPMSC, and PORTLI registers, and 1003 * external hub ports attached to USB devices.' 1004 * 1005 * This follows the procedure in 4.15 `Suspend-Resume', 4.15.2 1006 * `Port Resume', 4.15.2.2 `Host Initiated'. 1007 * 1008 * XXX We should maybe batch up initiating the state 1009 * transitions, and then wait for them to complete all at once. 1010 */ 1011 for (bn = 0; bn < 2; bn++) { 1012 for (i = 1; i <= sc->sc_rhportcount[bn]; i++) { 1013 port = XHCI_PORTSC(xhci_rhport2ctlrport(sc, bn, i)); 1014 1015 /* `When a port is in the U3 state: ...' */ 1016 v = xhci_op_read_4(sc, port); 1017 if (XHCI_PS_PLS_GET(v) != XHCI_PS_PLS_U3) 1018 continue; 1019 1020 /* 1021 * `For a USB2 protocol port, software shall 1022 * write a ``15'' (Resume) to the PLS field to 1023 * initiate resume signaling. The port shall 1024 * transition to the Resume substate and the 1025 * xHC shall transmit the resume signaling 1026 * within 1ms (T_URSM). Software shall ensure 1027 * that resume is signaled for at least 20ms 1028 * (T_DRSMDN). Software shall start timing 1029 * T_DRSMDN from the write of ``15'' (Resume) 1030 * to PLS.' 1031 */ 1032 if (bn == 1) { 1033 KASSERT(sc->sc_bus2.ub_revision == USBREV_2_0); 1034 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1035 v |= XHCI_PS_LWS; 1036 v |= XHCI_PS_PLS_SET(XHCI_PS_PLS_SETRESUME); 1037 xhci_op_write_4(sc, port, v); 1038 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1039 } else { 1040 KASSERT(sc->sc_bus.ub_revision > USBREV_2_0); 1041 } 1042 1043 /* 1044 * `For a USB3 protocol port [and a USB2 1045 * protocol port after transitioning to 1046 * Resume], software shall write a ``0'' (U0) 1047 * to the PLS field...' 1048 */ 1049 v = xhci_op_read_4(sc, port); 1050 v &= ~(XHCI_PS_PLS_MASK | XHCI_PS_CLEAR); 1051 v |= XHCI_PS_LWS | XHCI_PS_PLS_SET(XHCI_PS_PLS_SETU0); 1052 xhci_op_write_4(sc, port, v); 1053 1054 for (j = 0; j < XHCI_WAIT_PLS_U0; j++) { 1055 v = xhci_op_read_4(sc, port); 1056 if (XHCI_PS_PLS_GET(v) == XHCI_PS_PLS_U0) 1057 break; 1058 usb_delay_ms(&sc->sc_bus, 1); 1059 } 1060 if (j == XHCI_WAIT_PLS_U0) { 1061 device_printf(self, 1062 "resume timeout on bus %zu port %zu\n", 1063 bn, i); 1064 goto out; 1065 } 1066 } 1067 } 1068 1069 /* 1070 * `10. Restart each of the previously Running endpoints by 1071 * ringing their doorbells.' 1072 */ 1073 for (i = 0; i < sc->sc_maxslots; i++) { 1074 struct xhci_slot *xs = &sc->sc_slots[i]; 1075 1076 /* Skip if the slot is not in use. */ 1077 if (xs->xs_idx == 0) 1078 continue; 1079 1080 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 1081 /* Skip if the endpoint is not Running. */ 1082 if (xhci_get_epstate(sc, xs, dci) != 1083 XHCI_EPSTATE_RUNNING) 1084 continue; 1085 1086 /* Ring the doorbell. */ 1087 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 1088 } 1089 } 1090 1091 /* 1092 * `Note: After a Save or Restore operation completes, the 1093 * Save/Restore Error (SRE) flag in the USBSTS register should 1094 * be checked to ensure that the operation completed 1095 * successfully.' 1096 */ 1097 if (xhci_op_read_4(sc, XHCI_USBSTS) & XHCI_STS_SRE) { 1098 device_printf(self, "resume error, USBSTS.SRE\n"); 1099 goto out; 1100 } 1101 1102 /* Success! */ 1103 ok = true; 1104 1105 out: /* 1106 * Resume command issuance. If the hardware failed to resume, 1107 * well, tough -- deadlocking because everything is held up on 1108 * the suspension, with no opportunity to detach, isn't better 1109 * than timing out waiting for dead hardware. 1110 */ 1111 mutex_enter(&sc->sc_lock); 1112 KASSERT(sc->sc_suspender); 1113 sc->sc_suspender = NULL; 1114 cv_broadcast(&sc->sc_cmdbusy_cv); 1115 mutex_exit(&sc->sc_lock); 1116 1117 mutex_exit(&sc->sc_rhlock); 1118 return ok; 1119 } 1120 1121 bool 1122 xhci_shutdown(device_t self, int flags) 1123 { 1124 return false; 1125 } 1126 1127 static int 1128 xhci_hc_reset(struct xhci_softc * const sc) 1129 { 1130 uint32_t usbcmd, usbsts; 1131 int i; 1132 1133 /* Check controller not ready */ 1134 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1135 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1136 if ((usbsts & XHCI_STS_CNR) == 0) 1137 break; 1138 usb_delay_ms(&sc->sc_bus, 1); 1139 } 1140 if (i >= XHCI_WAIT_CNR) { 1141 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 1142 return EIO; 1143 } 1144 1145 /* Halt controller */ 1146 usbcmd = 0; 1147 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1148 usb_delay_ms(&sc->sc_bus, 1); 1149 1150 /* Reset controller */ 1151 usbcmd = XHCI_CMD_HCRST; 1152 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 1153 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 1154 /* 1155 * Wait 1ms first. Existing Intel xHCI requires 1ms delay to 1156 * prevent system hang (Errata). 1157 */ 1158 usb_delay_ms(&sc->sc_bus, 1); 1159 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 1160 if ((usbcmd & XHCI_CMD_HCRST) == 0) 1161 break; 1162 } 1163 if (i >= XHCI_WAIT_HCRST) { 1164 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 1165 return EIO; 1166 } 1167 1168 /* Check controller not ready */ 1169 for (i = 0; i < XHCI_WAIT_CNR; i++) { 1170 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1171 if ((usbsts & XHCI_STS_CNR) == 0) 1172 break; 1173 usb_delay_ms(&sc->sc_bus, 1); 1174 } 1175 if (i >= XHCI_WAIT_CNR) { 1176 aprint_error_dev(sc->sc_dev, 1177 "controller not ready timeout after reset\n"); 1178 return EIO; 1179 } 1180 1181 return 0; 1182 } 1183 1184 /* 7.2 xHCI Support Protocol Capability */ 1185 static void 1186 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 1187 { 1188 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1189 1190 /* XXX Cache this lot */ 1191 1192 const uint32_t w0 = xhci_read_4(sc, ecp); 1193 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 1194 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 1195 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 1196 1197 aprint_debug_dev(sc->sc_dev, 1198 " SP: 0x%08x 0x%08x 0x%08x 0x%08x\n", w0, w4, w8, wc); 1199 1200 if (w4 != XHCI_XECP_USBID) 1201 return; 1202 1203 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 1204 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 1205 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 1206 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 1207 1208 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 1209 switch (mm) { 1210 case 0x0200: 1211 case 0x0300: 1212 case 0x0301: 1213 case 0x0310: 1214 case 0x0320: 1215 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 1216 major == 3 ? "ss" : "hs", cpo, cpo + cpc - 1); 1217 if (major == 3) 1218 sc->sc_usb3nports += cpo + cpc - 1; 1219 else 1220 sc->sc_usb2nports += cpo + cpc - 1; 1221 break; 1222 default: 1223 aprint_error_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 1224 major, minor); 1225 return; 1226 } 1227 1228 const size_t bus = (major == 3) ? 0 : 1; 1229 1230 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 1231 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 1232 if (sc->sc_ctlrportmap[cp] != 0) { 1233 aprint_error_dev(sc->sc_dev, "controller port %zu " 1234 "already assigned", cp); 1235 continue; 1236 } 1237 1238 sc->sc_ctlrportbus[cp / NBBY] |= 1239 bus == 0 ? 0 : __BIT(cp % NBBY); 1240 1241 const size_t rhp = sc->sc_rhportcount[bus]++; 1242 1243 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 1244 "bus %zu rhp %zu is %d", bus, rhp, 1245 sc->sc_rhportmap[bus][rhp]); 1246 1247 sc->sc_rhportmap[bus][rhp] = cp + 1; 1248 sc->sc_ctlrportmap[cp] = rhp + 1; 1249 } 1250 } 1251 1252 /* Process extended capabilities */ 1253 static void 1254 xhci_ecp(struct xhci_softc *sc) 1255 { 1256 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1257 1258 bus_size_t ecp = XHCI_HCC_XECP(sc->sc_hcc) * 4; 1259 while (ecp != 0) { 1260 uint32_t ecr = xhci_read_4(sc, ecp); 1261 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 1262 switch (XHCI_XECP_ID(ecr)) { 1263 case XHCI_ID_PROTOCOLS: { 1264 xhci_id_protocols(sc, ecp); 1265 break; 1266 } 1267 case XHCI_ID_USB_LEGACY: { 1268 uint8_t bios_sem; 1269 1270 /* Take host controller ownership from BIOS */ 1271 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 1272 if (bios_sem) { 1273 /* sets xHCI to be owned by OS */ 1274 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 1275 aprint_debug_dev(sc->sc_dev, 1276 "waiting for BIOS to give up control\n"); 1277 for (int i = 0; i < 5000; i++) { 1278 bios_sem = xhci_read_1(sc, ecp + 1279 XHCI_XECP_BIOS_SEM); 1280 if (bios_sem == 0) 1281 break; 1282 DELAY(1000); 1283 } 1284 if (bios_sem) { 1285 aprint_error_dev(sc->sc_dev, 1286 "timed out waiting for BIOS\n"); 1287 } 1288 } 1289 break; 1290 } 1291 default: 1292 break; 1293 } 1294 ecr = xhci_read_4(sc, ecp); 1295 if (XHCI_XECP_NEXT(ecr) == 0) { 1296 ecp = 0; 1297 } else { 1298 ecp += XHCI_XECP_NEXT(ecr) * 4; 1299 } 1300 } 1301 } 1302 1303 #define XHCI_HCCPREV1_BITS \ 1304 "\177\020" /* New bitmask */ \ 1305 "f\020\020XECP\0" \ 1306 "f\014\4MAXPSA\0" \ 1307 "b\013CFC\0" \ 1308 "b\012SEC\0" \ 1309 "b\011SBD\0" \ 1310 "b\010FSE\0" \ 1311 "b\7NSS\0" \ 1312 "b\6LTC\0" \ 1313 "b\5LHRC\0" \ 1314 "b\4PIND\0" \ 1315 "b\3PPC\0" \ 1316 "b\2CZC\0" \ 1317 "b\1BNC\0" \ 1318 "b\0AC64\0" \ 1319 "\0" 1320 #define XHCI_HCCV1_x_BITS \ 1321 "\177\020" /* New bitmask */ \ 1322 "f\020\020XECP\0" \ 1323 "f\014\4MAXPSA\0" \ 1324 "b\013CFC\0" \ 1325 "b\012SEC\0" \ 1326 "b\011SPC\0" \ 1327 "b\010PAE\0" \ 1328 "b\7NSS\0" \ 1329 "b\6LTC\0" \ 1330 "b\5LHRC\0" \ 1331 "b\4PIND\0" \ 1332 "b\3PPC\0" \ 1333 "b\2CSZ\0" \ 1334 "b\1BNC\0" \ 1335 "b\0AC64\0" \ 1336 "\0" 1337 1338 #define XHCI_HCC2_BITS \ 1339 "\177\020" /* New bitmask */ \ 1340 "b\7ETC_TSC\0" \ 1341 "b\6ETC\0" \ 1342 "b\5CIC\0" \ 1343 "b\4LEC\0" \ 1344 "b\3CTC\0" \ 1345 "b\2FSC\0" \ 1346 "b\1CMC\0" \ 1347 "b\0U3C\0" \ 1348 "\0" 1349 1350 void 1351 xhci_start(struct xhci_softc *sc) 1352 { 1353 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1354 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1355 /* Intel xhci needs interrupt rate moderated. */ 1356 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1357 else 1358 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1359 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1360 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1361 1362 /* Go! */ 1363 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); 1364 aprint_debug_dev(sc->sc_dev, "USBCMD 0x%08"PRIx32"\n", 1365 xhci_op_read_4(sc, XHCI_USBCMD)); 1366 } 1367 1368 int 1369 xhci_init(struct xhci_softc *sc) 1370 { 1371 bus_size_t bsz; 1372 uint32_t hcs1, hcs2, hcs3, dboff, rtsoff; 1373 uint32_t pagesize, config; 1374 int i = 0; 1375 uint16_t hciversion; 1376 uint8_t caplength; 1377 1378 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1379 1380 /* Set up the bus struct for the usb 3 and usb 2 buses */ 1381 sc->sc_bus.ub_methods = &xhci_bus_methods; 1382 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1383 sc->sc_bus.ub_usedma = true; 1384 sc->sc_bus.ub_hcpriv = sc; 1385 1386 sc->sc_bus2.ub_methods = &xhci_bus_methods; 1387 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 1388 sc->sc_bus2.ub_revision = USBREV_2_0; 1389 sc->sc_bus2.ub_usedma = true; 1390 sc->sc_bus2.ub_hcpriv = sc; 1391 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 1392 1393 caplength = xhci_read_1(sc, XHCI_CAPLENGTH); 1394 hciversion = xhci_read_2(sc, XHCI_HCIVERSION); 1395 1396 if (hciversion < XHCI_HCIVERSION_0_96 || 1397 hciversion >= 0x0200) { 1398 aprint_normal_dev(sc->sc_dev, 1399 "xHCI version %x.%x not known to be supported\n", 1400 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1401 } else { 1402 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 1403 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 1404 } 1405 1406 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 1407 &sc->sc_cbh) != 0) { 1408 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 1409 return ENOMEM; 1410 } 1411 1412 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 1413 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 1414 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 1415 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 1416 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 1417 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 1418 aprint_debug_dev(sc->sc_dev, 1419 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 1420 1421 sc->sc_hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 1422 sc->sc_ctxsz = XHCI_HCC_CSZ(sc->sc_hcc) ? 64 : 32; 1423 1424 char sbuf[128]; 1425 if (hciversion < XHCI_HCIVERSION_1_0) 1426 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, sc->sc_hcc); 1427 else 1428 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, sc->sc_hcc); 1429 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 1430 aprint_debug_dev(sc->sc_dev, "xECP %" __PRIxBITS "\n", 1431 XHCI_HCC_XECP(sc->sc_hcc) * 4); 1432 if (hciversion >= XHCI_HCIVERSION_1_1) { 1433 sc->sc_hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 1434 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, sc->sc_hcc2); 1435 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 1436 } 1437 1438 /* default all ports to bus 0, i.e. usb 3 */ 1439 sc->sc_ctlrportbus = kmem_zalloc( 1440 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 1441 sc->sc_ctlrportmap = 1442 kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1443 1444 /* controller port to bus roothub port map */ 1445 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 1446 sc->sc_rhportmap[j] = 1447 kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1448 } 1449 1450 /* 1451 * Process all Extended Capabilities 1452 */ 1453 xhci_ecp(sc); 1454 1455 bsz = XHCI_PORTSC(sc->sc_maxports); 1456 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1457 &sc->sc_obh) != 0) { 1458 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1459 return ENOMEM; 1460 } 1461 1462 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1463 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1464 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1465 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1466 return ENOMEM; 1467 } 1468 1469 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1470 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1471 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1472 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1473 return ENOMEM; 1474 } 1475 1476 int rv; 1477 rv = xhci_hc_reset(sc); 1478 if (rv != 0) { 1479 return rv; 1480 } 1481 1482 if (sc->sc_vendor_init) 1483 sc->sc_vendor_init(sc); 1484 1485 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1486 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1487 pagesize = ffs(pagesize); 1488 if (pagesize == 0) { 1489 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1490 return EIO; 1491 } 1492 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1493 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1494 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1495 (uint32_t)sc->sc_maxslots); 1496 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1497 1498 int err; 1499 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1500 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1501 if (sc->sc_maxspbuf != 0) { 1502 err = usb_allocmem(sc->sc_bus.ub_dmatag, 1503 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1504 USBMALLOC_COHERENT | USBMALLOC_ZERO, 1505 &sc->sc_spbufarray_dma); 1506 if (err) { 1507 aprint_error_dev(sc->sc_dev, 1508 "spbufarray init fail, err %d\n", err); 1509 return ENOMEM; 1510 } 1511 1512 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1513 sc->sc_maxspbuf, KM_SLEEP); 1514 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1515 for (i = 0; i < sc->sc_maxspbuf; i++) { 1516 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1517 /* allocate contexts */ 1518 err = usb_allocmem(sc->sc_bus.ub_dmatag, sc->sc_pgsz, 1519 sc->sc_pgsz, USBMALLOC_COHERENT | USBMALLOC_ZERO, 1520 dma); 1521 if (err) { 1522 aprint_error_dev(sc->sc_dev, 1523 "spbufarray_dma init fail, err %d\n", err); 1524 rv = ENOMEM; 1525 goto bad1; 1526 } 1527 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1528 usb_syncmem(dma, 0, sc->sc_pgsz, 1529 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1530 } 1531 1532 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1533 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1534 } 1535 1536 config = xhci_op_read_4(sc, XHCI_CONFIG); 1537 config &= ~0xFF; 1538 config |= sc->sc_maxslots & 0xFF; 1539 xhci_op_write_4(sc, XHCI_CONFIG, config); 1540 1541 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1542 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1543 if (err) { 1544 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1545 err); 1546 rv = ENOMEM; 1547 goto bad1; 1548 } 1549 1550 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1551 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1552 if (err) { 1553 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1554 err); 1555 rv = ENOMEM; 1556 goto bad2; 1557 } 1558 1559 usb_dma_t *dma; 1560 size_t size; 1561 size_t align; 1562 1563 dma = &sc->sc_eventst_dma; 1564 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1565 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1566 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1567 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1568 err = usb_allocmem(sc->sc_bus.ub_dmatag, size, align, 1569 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma); 1570 if (err) { 1571 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1572 err); 1573 rv = ENOMEM; 1574 goto bad3; 1575 } 1576 1577 aprint_debug_dev(sc->sc_dev, "eventst: 0x%016jx %p %zx\n", 1578 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1579 KERNADDR(&sc->sc_eventst_dma, 0), 1580 sc->sc_eventst_dma.udma_block->size); 1581 1582 dma = &sc->sc_dcbaa_dma; 1583 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1584 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1585 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1586 err = usb_allocmem(sc->sc_bus.ub_dmatag, size, align, 1587 USBMALLOC_COHERENT | USBMALLOC_ZERO, dma); 1588 if (err) { 1589 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1590 rv = ENOMEM; 1591 goto bad4; 1592 } 1593 aprint_debug_dev(sc->sc_dev, "dcbaa: 0x%016jx %p %zx\n", 1594 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1595 KERNADDR(&sc->sc_dcbaa_dma, 0), 1596 sc->sc_dcbaa_dma.udma_block->size); 1597 1598 if (sc->sc_maxspbuf != 0) { 1599 /* 1600 * DCBA entry 0 hold the scratchbuf array pointer. 1601 */ 1602 *(uint64_t *)KERNADDR(dma, 0) = 1603 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1604 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1605 } 1606 1607 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1608 KM_SLEEP); 1609 if (sc->sc_slots == NULL) { 1610 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1611 rv = ENOMEM; 1612 goto bad; 1613 } 1614 1615 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1616 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1617 if (sc->sc_xferpool == NULL) { 1618 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1619 err); 1620 rv = ENOMEM; 1621 goto bad; 1622 } 1623 1624 cv_init(&sc->sc_command_cv, "xhcicmd"); 1625 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1626 mutex_init(&sc->sc_rhlock, MUTEX_DEFAULT, IPL_NONE); 1627 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1628 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1629 1630 struct xhci_erste *erst; 1631 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1632 erst[0].erste_0 = htole64(xhci_ring_trbp(sc->sc_er, 0)); 1633 erst[0].erste_2 = htole32(sc->sc_er->xr_ntrb); 1634 erst[0].erste_3 = htole32(0); 1635 usb_syncmem(&sc->sc_eventst_dma, 0, 1636 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1637 1638 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1639 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1640 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(sc->sc_er, 0) | 1641 XHCI_ERDP_BUSY); 1642 1643 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1644 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(sc->sc_cr, 0) | 1645 sc->sc_cr->xr_cs); 1646 1647 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1648 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1649 1650 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1651 xhci_start(sc); 1652 1653 return 0; 1654 1655 bad: 1656 if (sc->sc_xferpool) { 1657 pool_cache_destroy(sc->sc_xferpool); 1658 sc->sc_xferpool = NULL; 1659 } 1660 1661 if (sc->sc_slots) { 1662 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1663 sc->sc_maxslots); 1664 sc->sc_slots = NULL; 1665 } 1666 1667 usb_freemem(&sc->sc_dcbaa_dma); 1668 bad4: 1669 usb_freemem(&sc->sc_eventst_dma); 1670 bad3: 1671 xhci_ring_free(sc, &sc->sc_er); 1672 bad2: 1673 xhci_ring_free(sc, &sc->sc_cr); 1674 i = sc->sc_maxspbuf; 1675 bad1: 1676 for (int j = 0; j < i; j++) 1677 usb_freemem(&sc->sc_spbuf_dma[j]); 1678 usb_freemem(&sc->sc_spbufarray_dma); 1679 1680 return rv; 1681 } 1682 1683 static inline bool 1684 xhci_polling_p(struct xhci_softc * const sc) 1685 { 1686 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1687 } 1688 1689 int 1690 xhci_intr(void *v) 1691 { 1692 struct xhci_softc * const sc = v; 1693 int ret = 0; 1694 1695 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1696 1697 if (sc == NULL) 1698 return 0; 1699 1700 mutex_spin_enter(&sc->sc_intr_lock); 1701 1702 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1703 goto done; 1704 1705 /* If we get an interrupt while polling, then just ignore it. */ 1706 if (xhci_polling_p(sc)) { 1707 #ifdef DIAGNOSTIC 1708 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1709 #endif 1710 goto done; 1711 } 1712 1713 ret = xhci_intr1(sc); 1714 if (ret) { 1715 KASSERT(sc->sc_child || sc->sc_child2); 1716 1717 /* 1718 * One of child busses could be already detached. It doesn't 1719 * matter on which of the two the softintr is scheduled. 1720 */ 1721 if (sc->sc_child) 1722 usb_schedsoftintr(&sc->sc_bus); 1723 else 1724 usb_schedsoftintr(&sc->sc_bus2); 1725 } 1726 done: 1727 mutex_spin_exit(&sc->sc_intr_lock); 1728 return ret; 1729 } 1730 1731 int 1732 xhci_intr1(struct xhci_softc * const sc) 1733 { 1734 uint32_t usbsts; 1735 uint32_t iman; 1736 1737 XHCIHIST_FUNC(); 1738 1739 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1740 XHCIHIST_CALLARGS("USBSTS 0x%08jx", usbsts, 0, 0, 0); 1741 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1742 XHCI_STS_HCE)) == 0) { 1743 DPRINTFN(16, "ignored intr not for %jd", 1744 device_unit(sc->sc_dev), 0, 0, 0); 1745 return 0; 1746 } 1747 1748 /* 1749 * Clear EINT and other transient flags, to not misenterpret 1750 * next shared interrupt. Also, to avoid race, EINT must be cleared 1751 * before XHCI_IMAN_INTR_PEND is cleared. 1752 */ 1753 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1754 1755 #ifdef XHCI_DEBUG 1756 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1757 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1758 #endif 1759 1760 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1761 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1762 iman |= XHCI_IMAN_INTR_PEND; 1763 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1764 1765 #ifdef XHCI_DEBUG 1766 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1767 DPRINTFN(16, "IMAN0 0x%08jx", iman, 0, 0, 0); 1768 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1769 DPRINTFN(16, "USBSTS 0x%08jx", usbsts, 0, 0, 0); 1770 #endif 1771 1772 return 1; 1773 } 1774 1775 /* 1776 * 3 port speed types used in USB stack 1777 * 1778 * usbdi speed 1779 * definition: USB_SPEED_* in usb.h 1780 * They are used in struct usbd_device in USB stack. 1781 * ioctl interface uses these values too. 1782 * port_status speed 1783 * definition: UPS_*_SPEED in usb.h 1784 * They are used in usb_port_status_t and valid only for USB 2.0. 1785 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1786 * of usb_port_status_ext_t indicates port speed. 1787 * Note that some 3.0 values overlap with 2.0 values. 1788 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1789 * means UPS_LOW_SPEED in HS.) 1790 * port status returned from hub also uses these values. 1791 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1792 * or more. 1793 * xspeed: 1794 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1795 * They are used in only slot context and PORTSC reg of xhci. 1796 * The difference between usbdi speed and xspeed is 1797 * that FS and LS values are swapped. 1798 */ 1799 1800 /* convert usbdi speed to xspeed */ 1801 static int 1802 xhci_speed2xspeed(int speed) 1803 { 1804 switch (speed) { 1805 case USB_SPEED_LOW: return 2; 1806 case USB_SPEED_FULL: return 1; 1807 default: return speed; 1808 } 1809 } 1810 1811 #if 0 1812 /* convert xspeed to usbdi speed */ 1813 static int 1814 xhci_xspeed2speed(int xspeed) 1815 { 1816 switch (xspeed) { 1817 case 1: return USB_SPEED_FULL; 1818 case 2: return USB_SPEED_LOW; 1819 default: return xspeed; 1820 } 1821 } 1822 #endif 1823 1824 /* convert xspeed to port status speed */ 1825 static int 1826 xhci_xspeed2psspeed(int xspeed) 1827 { 1828 switch (xspeed) { 1829 case 0: return 0; 1830 case 1: return UPS_FULL_SPEED; 1831 case 2: return UPS_LOW_SPEED; 1832 case 3: return UPS_HIGH_SPEED; 1833 default: return UPS_OTHER_SPEED; 1834 } 1835 } 1836 1837 /* 1838 * Construct input contexts and issue TRB to open pipe. 1839 */ 1840 static usbd_status 1841 xhci_configure_endpoint(struct usbd_pipe *pipe) 1842 { 1843 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1844 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1845 #ifdef USB_DEBUG 1846 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1847 #endif 1848 struct xhci_soft_trb trb; 1849 usbd_status err; 1850 1851 XHCIHIST_FUNC(); 1852 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1853 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1854 pipe->up_endpoint->ue_edesc->bmAttributes); 1855 1856 /* XXX ensure input context is available? */ 1857 1858 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1859 1860 /* set up context */ 1861 xhci_setup_ctx(pipe); 1862 1863 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1864 sc->sc_ctxsz * 1); 1865 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1866 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1867 1868 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1869 trb.trb_2 = 0; 1870 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1871 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1872 1873 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1874 1875 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1876 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1877 sc->sc_ctxsz * 1); 1878 1879 return err; 1880 } 1881 1882 #if 0 1883 static usbd_status 1884 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1885 { 1886 #ifdef USB_DEBUG 1887 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1888 #endif 1889 1890 XHCIHIST_FUNC(); 1891 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 1892 1893 return USBD_NORMAL_COMPLETION; 1894 } 1895 #endif 1896 1897 /* 4.6.8, 6.4.3.7 */ 1898 static void 1899 xhci_reset_endpoint(struct usbd_pipe *pipe) 1900 { 1901 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1902 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1903 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1904 struct xhci_soft_trb trb; 1905 1906 XHCIHIST_FUNC(); 1907 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1908 1909 KASSERT(mutex_owned(&sc->sc_lock)); 1910 1911 trb.trb_0 = 0; 1912 trb.trb_2 = 0; 1913 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1914 XHCI_TRB_3_EP_SET(dci) | 1915 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1916 1917 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) { 1918 device_printf(sc->sc_dev, "%s: endpoint 0x%x: timed out\n", 1919 __func__, pipe->up_endpoint->ue_edesc->bEndpointAddress); 1920 } 1921 } 1922 1923 /* 1924 * 4.6.9, 6.4.3.8 1925 * Stop execution of TDs on xfer ring. 1926 * Should be called with sc_lock held. 1927 */ 1928 static usbd_status 1929 xhci_stop_endpoint_cmd(struct xhci_softc *sc, struct xhci_slot *xs, u_int dci, 1930 uint32_t trb3flags) 1931 { 1932 struct xhci_soft_trb trb; 1933 usbd_status err; 1934 1935 XHCIHIST_FUNC(); 1936 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1937 1938 KASSERT(mutex_owned(&sc->sc_lock)); 1939 1940 trb.trb_0 = 0; 1941 trb.trb_2 = 0; 1942 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1943 XHCI_TRB_3_EP_SET(dci) | 1944 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1945 trb3flags; 1946 1947 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1948 1949 return err; 1950 } 1951 1952 static usbd_status 1953 xhci_stop_endpoint(struct usbd_pipe *pipe) 1954 { 1955 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1956 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1957 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1958 1959 XHCIHIST_FUNC(); 1960 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1961 1962 KASSERT(mutex_owned(&sc->sc_lock)); 1963 1964 return xhci_stop_endpoint_cmd(sc, xs, dci, 0); 1965 } 1966 1967 /* 1968 * Set TR Dequeue Pointer. 1969 * xHCI 1.1 4.6.10 6.4.3.9 1970 * Purge all of the TRBs on ring and reinitialize ring. 1971 * Set TR dequeue Pointer to 0 and Cycle State to 1. 1972 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1973 * error will be generated. 1974 */ 1975 static void 1976 xhci_set_dequeue(struct usbd_pipe *pipe) 1977 { 1978 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1979 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1980 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1981 struct xhci_ring * const xr = xs->xs_xr[dci]; 1982 struct xhci_soft_trb trb; 1983 1984 XHCIHIST_FUNC(); 1985 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1986 1987 KASSERT(mutex_owned(&sc->sc_lock)); 1988 KASSERT(xr != NULL); 1989 1990 xhci_host_dequeue(xr); 1991 1992 /* set DCS */ 1993 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1994 trb.trb_2 = 0; 1995 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1996 XHCI_TRB_3_EP_SET(dci) | 1997 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1998 1999 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) { 2000 device_printf(sc->sc_dev, "%s: endpoint 0x%x: timed out\n", 2001 __func__, pipe->up_endpoint->ue_edesc->bEndpointAddress); 2002 } 2003 } 2004 2005 /* 2006 * Open new pipe: called from usbd_setup_pipe_flags. 2007 * Fills methods of pipe. 2008 * If pipe is not for ep0, calls configure_endpoint. 2009 */ 2010 static usbd_status 2011 xhci_open(struct usbd_pipe *pipe) 2012 { 2013 struct usbd_device * const dev = pipe->up_dev; 2014 struct xhci_pipe * const xpipe = (struct xhci_pipe *)pipe; 2015 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2016 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2017 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2018 const u_int dci = xhci_ep_get_dci(ed); 2019 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2020 usbd_status err; 2021 2022 XHCIHIST_FUNC(); 2023 XHCIHIST_CALLARGS("addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 2024 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 2025 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 2026 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 2027 ed->bmAttributes); 2028 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 2029 ed->bInterval, 0, 0); 2030 2031 if (sc->sc_dying) 2032 return USBD_IOERROR; 2033 2034 /* Root Hub */ 2035 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 2036 switch (ed->bEndpointAddress) { 2037 case USB_CONTROL_ENDPOINT: 2038 pipe->up_methods = &roothub_ctrl_methods; 2039 break; 2040 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2041 pipe->up_methods = &xhci_root_intr_methods; 2042 break; 2043 default: 2044 pipe->up_methods = NULL; 2045 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 2046 ed->bEndpointAddress, 0, 0, 0); 2047 return USBD_INVAL; 2048 } 2049 return USBD_NORMAL_COMPLETION; 2050 } 2051 2052 usb_init_task(&xpipe->xp_async_task, xhci_pipe_restart_async_task, 2053 pipe, USB_TASKQ_MPSAFE); 2054 2055 switch (xfertype) { 2056 case UE_CONTROL: 2057 pipe->up_methods = &xhci_device_ctrl_methods; 2058 break; 2059 case UE_ISOCHRONOUS: 2060 pipe->up_methods = &xhci_device_isoc_methods; 2061 pipe->up_serialise = false; 2062 xpipe->xp_isoc_next = -1; 2063 break; 2064 case UE_BULK: 2065 pipe->up_methods = &xhci_device_bulk_methods; 2066 break; 2067 case UE_INTERRUPT: 2068 pipe->up_methods = &xhci_device_intr_methods; 2069 break; 2070 default: 2071 return USBD_IOERROR; 2072 break; 2073 } 2074 2075 KASSERT(xs != NULL); 2076 KASSERT(xs->xs_xr[dci] == NULL); 2077 2078 /* allocate transfer ring */ 2079 err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS, 2080 XHCI_TRB_ALIGN); 2081 if (err) { 2082 DPRINTFN(1, "ring alloc failed %jd", err, 0, 0, 0); 2083 return err; 2084 } 2085 2086 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 2087 return xhci_configure_endpoint(pipe); 2088 2089 return USBD_NORMAL_COMPLETION; 2090 } 2091 2092 /* 2093 * Closes pipe, called from usbd_kill_pipe via close methods. 2094 * If the endpoint to be closed is ep0, disable_slot. 2095 * Should be called with sc_lock held. 2096 */ 2097 static void 2098 xhci_close_pipe(struct usbd_pipe *pipe) 2099 { 2100 struct xhci_pipe * const xp = 2101 container_of(pipe, struct xhci_pipe, xp_pipe); 2102 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2103 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2104 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2105 const u_int dci = xhci_ep_get_dci(ed); 2106 struct xhci_soft_trb trb; 2107 uint32_t *cp; 2108 2109 XHCIHIST_FUNC(); 2110 2111 usb_rem_task_wait(pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC, 2112 &sc->sc_lock); 2113 2114 if (sc->sc_dying) 2115 return; 2116 2117 /* xs is uninitialized before xhci_init_slot */ 2118 if (xs == NULL || xs->xs_idx == 0) 2119 return; 2120 2121 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 2122 (uintptr_t)pipe, xs->xs_idx, dci, 0); 2123 2124 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2125 KASSERT(mutex_owned(&sc->sc_lock)); 2126 2127 if (pipe->up_dev->ud_depth == 0) 2128 return; 2129 2130 if (dci == XHCI_DCI_EP_CONTROL) { 2131 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 2132 /* This frees all rings */ 2133 xhci_disable_slot(sc, xs->xs_idx); 2134 return; 2135 } 2136 2137 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 2138 (void)xhci_stop_endpoint(pipe); 2139 2140 /* 2141 * set appropriate bit to be dropped. 2142 * don't set DC bit to 1, otherwise all endpoints 2143 * would be deconfigured. 2144 */ 2145 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2146 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 2147 cp[1] = htole32(0); 2148 2149 /* XXX should be most significant one, not dci? */ 2150 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2151 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 2152 2153 /* configure ep context performs an implicit dequeue */ 2154 xhci_host_dequeue(xs->xs_xr[dci]); 2155 2156 /* sync input contexts before they are read from memory */ 2157 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2158 2159 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2160 trb.trb_2 = 0; 2161 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2162 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 2163 2164 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2165 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2166 2167 xhci_ring_free(sc, &xs->xs_xr[dci]); 2168 xs->xs_xr[dci] = NULL; 2169 } 2170 2171 /* 2172 * Abort transfer. Must be called with sc_lock held. Releases and 2173 * reacquires sc_lock to sleep until hardware acknowledges abort. 2174 */ 2175 static void 2176 xhci_abortx(struct usbd_xfer *xfer) 2177 { 2178 XHCIHIST_FUNC(); 2179 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 2180 2181 XHCIHIST_CALLARGS("xfer %#jx pipe %#jx", 2182 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, 0, 0); 2183 2184 KASSERT(mutex_owned(&sc->sc_lock)); 2185 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2186 xfer->ux_status == USBD_TIMEOUT), 2187 "bad abort status: %d", xfer->ux_status); 2188 2189 xhci_pipe_restart(xfer->ux_pipe); 2190 2191 DPRINTFN(14, "end", 0, 0, 0, 0); 2192 } 2193 2194 static void 2195 xhci_host_dequeue(struct xhci_ring * const xr) 2196 { 2197 /* When dequeueing the controller, update our struct copy too */ 2198 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 2199 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 2200 BUS_DMASYNC_PREWRITE); 2201 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 2202 2203 xr->xr_ep = 0; 2204 xr->xr_cs = 1; 2205 } 2206 2207 /* 2208 * Recover STALLed endpoint, or stop endpoint to abort a pipe. 2209 * xHCI 1.1 sect 4.10.2.1 2210 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 2211 * all transfers on transfer ring. 2212 */ 2213 static void 2214 xhci_pipe_restart(struct usbd_pipe *pipe) 2215 { 2216 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2217 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2218 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 2219 2220 XHCIHIST_FUNC(); 2221 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju", 2222 (uintptr_t)pipe, xs->xs_idx, dci, 0); 2223 2224 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2225 2226 /* 2227 * - If the endpoint is halted, indicating a stall, reset it. 2228 * - If the endpoint is stopped, we're already good. 2229 * - Otherwise, someone wanted to abort the pipe, so stop the 2230 * endpoint. 2231 * 2232 * In any case, clear the ring. 2233 */ 2234 switch (xhci_get_epstate(sc, xs, dci)) { 2235 case XHCI_EPSTATE_HALTED: 2236 xhci_reset_endpoint(pipe); 2237 break; 2238 case XHCI_EPSTATE_STOPPED: 2239 break; 2240 default: 2241 xhci_stop_endpoint(pipe); 2242 break; 2243 } 2244 2245 switch (xhci_get_epstate(sc, xs, dci)) { 2246 case XHCI_EPSTATE_STOPPED: 2247 break; 2248 case XHCI_EPSTATE_ERROR: 2249 device_printf(sc->sc_dev, "endpoint 0x%x error\n", 2250 pipe->up_endpoint->ue_edesc->bEndpointAddress); 2251 break; 2252 default: 2253 device_printf(sc->sc_dev, "endpoint 0x%x failed to stop\n", 2254 pipe->up_endpoint->ue_edesc->bEndpointAddress); 2255 } 2256 2257 xhci_set_dequeue(pipe); 2258 2259 DPRINTFN(4, "ends", 0, 0, 0, 0); 2260 } 2261 2262 static void 2263 xhci_pipe_restart_async_task(void *cookie) 2264 { 2265 struct usbd_pipe * const pipe = cookie; 2266 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2267 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2268 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 2269 struct xhci_ring * const tr = xs->xs_xr[dci]; 2270 struct usbd_xfer *xfer; 2271 2272 XHCIHIST_FUNC(); 2273 XHCIHIST_CALLARGS("sc=%#jx pipe=%#jx", 2274 (uintptr_t)sc, (uintptr_t)pipe, 0, 0); 2275 2276 mutex_enter(&sc->sc_lock); 2277 2278 xhci_pipe_restart(pipe); 2279 2280 /* 2281 * We halted our own queue because it stalled. Mark it no 2282 * longer halted and start issuing queued transfers again. 2283 */ 2284 tr->is_halted = false; 2285 xfer = SIMPLEQ_FIRST(&pipe->up_queue); 2286 if (xfer) { 2287 /* 2288 * If the first xfer of the queue is not in progress, 2289 * though, there may be a concurrent software abort 2290 * that has already cancelled it and is now in the 2291 * middle of a concurrent xhci_pipe_restart waiting to 2292 * reacquire the pipe (bus) lock. So only restart the 2293 * xfer if it's still USBD_IN_PROGRESS. 2294 * 2295 * Either way, xfers on the queue can't be in 2296 * USBD_NOT_STARTED. 2297 */ 2298 KASSERT(xfer->ux_status != USBD_NOT_STARTED); 2299 if (xfer->ux_status == USBD_IN_PROGRESS) { 2300 (*pipe->up_methods->upm_start)(xfer); 2301 } else { 2302 DPRINTF("pipe restart race xfer=%#jx status=%jd", 2303 (uintptr_t)xfer, xfer->ux_status, 0, 0); 2304 } 2305 } 2306 2307 mutex_exit(&sc->sc_lock); 2308 } 2309 2310 static void 2311 xhci_pipe_restart_async(struct usbd_pipe *pipe) 2312 { 2313 struct xhci_pipe * const xp = 2314 container_of(pipe, struct xhci_pipe, xp_pipe); 2315 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2316 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 2317 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 2318 struct xhci_ring * const tr = xs->xs_xr[dci]; 2319 2320 XHCIHIST_FUNC(); 2321 XHCIHIST_CALLARGS("pipe %#jx", (uintptr_t)pipe, 0, 0, 0); 2322 2323 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2324 2325 tr->is_halted = true; 2326 usb_add_task(pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 2327 2328 DPRINTFN(4, "ends", 0, 0, 0, 0); 2329 } 2330 2331 /* Process roothub port status/change events and notify to uhub_intr. */ 2332 static void 2333 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 2334 { 2335 XHCIHIST_FUNC(); 2336 XHCIHIST_CALLARGS("xhci%jd: port %ju status change", 2337 device_unit(sc->sc_dev), ctlrport, 0, 0); 2338 2339 if (ctlrport > sc->sc_maxports) 2340 return; 2341 2342 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 2343 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 2344 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 2345 2346 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 2347 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 2348 2349 if (xfer == NULL) 2350 return; 2351 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2352 2353 uint8_t *p = xfer->ux_buf; 2354 if (!xhci_polling_p(sc) || !sc->sc_intrxfer_deferred[bn]) 2355 memset(p, 0, xfer->ux_length); 2356 p[rhp / NBBY] |= 1 << (rhp % NBBY); 2357 xfer->ux_actlen = xfer->ux_length; 2358 xfer->ux_status = USBD_NORMAL_COMPLETION; 2359 if (xhci_polling_p(sc)) 2360 sc->sc_intrxfer_deferred[bn] = true; 2361 else 2362 usb_transfer_complete(xfer); 2363 } 2364 2365 /* Process Transfer Events */ 2366 static void 2367 xhci_event_transfer(struct xhci_softc * const sc, 2368 const struct xhci_trb * const trb) 2369 { 2370 uint64_t trb_0; 2371 uint32_t trb_2, trb_3; 2372 uint8_t trbcode; 2373 u_int slot, dci; 2374 struct xhci_slot *xs; 2375 struct xhci_ring *xr; 2376 struct xhci_xfer *xx; 2377 struct usbd_xfer *xfer; 2378 usbd_status err; 2379 2380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2381 2382 trb_0 = le64toh(trb->trb_0); 2383 trb_2 = le32toh(trb->trb_2); 2384 trb_3 = le32toh(trb->trb_3); 2385 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 2386 slot = XHCI_TRB_3_SLOT_GET(trb_3); 2387 dci = XHCI_TRB_3_EP_GET(trb_3); 2388 xs = &sc->sc_slots[slot]; 2389 xr = xs->xs_xr[dci]; 2390 2391 /* sanity check */ 2392 KASSERT(xr != NULL); 2393 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 2394 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 2395 2396 int idx = 0; 2397 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2398 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 2399 DPRINTFN(0, "invalid trb_0 %#jx", trb_0, 0, 0, 0); 2400 return; 2401 } 2402 xx = xr->xr_cookies[idx]; 2403 2404 /* clear cookie of consumed TRB */ 2405 xr->xr_cookies[idx] = NULL; 2406 2407 /* 2408 * xx is NULL if pipe is opened but xfer is not started. 2409 * It happens when stopping idle pipe. 2410 */ 2411 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 2412 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 2413 idx, (uintptr_t)xx, trbcode, dci); 2414 DPRINTFN(1, " orig TRB %#jx type %ju", trb_0, 2415 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 2416 0, 0); 2417 return; 2418 } 2419 } else { 2420 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 2421 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 2422 } 2423 /* XXX this may not happen */ 2424 if (xx == NULL) { 2425 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 2426 return; 2427 } 2428 xfer = &xx->xx_xfer; 2429 /* XXX this may happen when detaching */ 2430 if (xfer == NULL) { 2431 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 2432 (uintptr_t)xx, trb_0, 0, 0); 2433 return; 2434 } 2435 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 2436 /* XXX I dunno why this happens */ 2437 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 2438 2439 if (!xfer->ux_pipe->up_repeat && 2440 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 2441 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 2442 0, 0, 0); 2443 return; 2444 } 2445 2446 const uint8_t xfertype = 2447 UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 2448 2449 /* 4.11.5.2 Event Data TRB */ 2450 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2451 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 2452 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 2453 if ((trb_0 & 0x3) == 0x3) { 2454 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 2455 } 2456 } 2457 2458 switch (trbcode) { 2459 case XHCI_TRB_ERROR_SHORT_PKT: 2460 case XHCI_TRB_ERROR_SUCCESS: 2461 /* 2462 * A ctrl transfer can generate two events if it has a Data 2463 * stage. A short data stage can be OK and should not 2464 * complete the transfer as the status stage needs to be 2465 * performed. 2466 * 2467 * Note: Data and Status stage events point at same xfer. 2468 * ux_actlen and ux_dmabuf will be passed to 2469 * usb_transfer_complete after the Status stage event. 2470 * 2471 * It can be distinguished which stage generates the event: 2472 * + by checking least 3 bits of trb_0 if ED==1. 2473 * (see xhci_device_ctrl_start). 2474 * + by checking the type of original TRB if ED==0. 2475 * 2476 * In addition, intr, bulk, and isoc transfer currently 2477 * consists of single TD, so the "skip" is not needed. 2478 * ctrl xfer uses EVENT_DATA, and others do not. 2479 * Thus driver can switch the flow by checking ED bit. 2480 */ 2481 if (xfertype == UE_ISOCHRONOUS) { 2482 xfer->ux_frlengths[xx->xx_isoc_done] -= 2483 XHCI_TRB_2_REM_GET(trb_2); 2484 xfer->ux_actlen += xfer->ux_frlengths[xx->xx_isoc_done]; 2485 if (++xx->xx_isoc_done < xfer->ux_nframes) 2486 return; 2487 } else 2488 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2489 if (xfer->ux_actlen == 0) 2490 xfer->ux_actlen = xfer->ux_length - 2491 XHCI_TRB_2_REM_GET(trb_2); 2492 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 2493 == XHCI_TRB_TYPE_DATA_STAGE) { 2494 return; 2495 } 2496 } else if ((trb_0 & 0x3) == 0x3) { 2497 return; 2498 } 2499 err = USBD_NORMAL_COMPLETION; 2500 break; 2501 case XHCI_TRB_ERROR_STOPPED: 2502 case XHCI_TRB_ERROR_LENGTH: 2503 case XHCI_TRB_ERROR_STOPPED_SHORT: 2504 err = USBD_IOERROR; 2505 break; 2506 case XHCI_TRB_ERROR_STALL: 2507 case XHCI_TRB_ERROR_BABBLE: 2508 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2509 xhci_pipe_restart_async(xfer->ux_pipe); 2510 err = USBD_STALLED; 2511 break; 2512 default: 2513 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2514 err = USBD_IOERROR; 2515 break; 2516 } 2517 2518 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2519 (trb_0 & 0x3) == 0x0) { 2520 /* 2521 * Try to claim this xfer for completion. If it has 2522 * already completed or aborted, drop it on the floor. 2523 */ 2524 if (!usbd_xfer_trycomplete(xfer)) 2525 return; 2526 2527 /* Set the status. */ 2528 xfer->ux_status = err; 2529 2530 usb_transfer_complete(xfer); 2531 } 2532 } 2533 2534 /* Process Command complete events */ 2535 static void 2536 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2537 { 2538 uint64_t trb_0; 2539 uint32_t trb_2, trb_3; 2540 2541 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2542 2543 KASSERT(mutex_owned(&sc->sc_lock)); 2544 2545 trb_0 = le64toh(trb->trb_0); 2546 trb_2 = le32toh(trb->trb_2); 2547 trb_3 = le32toh(trb->trb_3); 2548 2549 if (trb_0 == sc->sc_command_addr) { 2550 sc->sc_resultpending = false; 2551 2552 sc->sc_result_trb.trb_0 = trb_0; 2553 sc->sc_result_trb.trb_2 = trb_2; 2554 sc->sc_result_trb.trb_3 = trb_3; 2555 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2556 XHCI_TRB_ERROR_SUCCESS) { 2557 DPRINTFN(1, "command completion " 2558 "failure: 0x%016jx 0x%08jx 0x%08jx", 2559 trb_0, trb_2, trb_3, 0); 2560 } 2561 cv_signal(&sc->sc_command_cv); 2562 } else { 2563 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2564 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2565 } 2566 } 2567 2568 /* 2569 * Process events. 2570 * called from xhci_softintr 2571 */ 2572 static void 2573 xhci_handle_event(struct xhci_softc * const sc, 2574 const struct xhci_trb * const trb) 2575 { 2576 uint64_t trb_0; 2577 uint32_t trb_2, trb_3; 2578 2579 XHCIHIST_FUNC(); 2580 2581 trb_0 = le64toh(trb->trb_0); 2582 trb_2 = le32toh(trb->trb_2); 2583 trb_3 = le32toh(trb->trb_3); 2584 2585 XHCIHIST_CALLARGS("event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2586 (uintptr_t)trb, trb_0, trb_2, trb_3); 2587 2588 /* 2589 * 4.11.3.1, 6.4.2.1 2590 * TRB Pointer is invalid for these completion codes. 2591 */ 2592 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2593 case XHCI_TRB_ERROR_RING_UNDERRUN: 2594 case XHCI_TRB_ERROR_RING_OVERRUN: 2595 case XHCI_TRB_ERROR_VF_RING_FULL: 2596 return; 2597 default: 2598 if (trb_0 == 0) { 2599 return; 2600 } 2601 break; 2602 } 2603 2604 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2605 case XHCI_TRB_EVENT_TRANSFER: 2606 xhci_event_transfer(sc, trb); 2607 break; 2608 case XHCI_TRB_EVENT_CMD_COMPLETE: 2609 xhci_event_cmd(sc, trb); 2610 break; 2611 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2612 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2613 break; 2614 default: 2615 break; 2616 } 2617 } 2618 2619 static void 2620 xhci_softintr(void *v) 2621 { 2622 struct usbd_bus * const bus = v; 2623 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2624 struct xhci_ring * const er = sc->sc_er; 2625 struct xhci_trb *trb; 2626 int i, j, k, bn; 2627 2628 XHCIHIST_FUNC(); 2629 2630 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2631 2632 i = er->xr_ep; 2633 j = er->xr_cs; 2634 2635 XHCIHIST_CALLARGS("er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2636 2637 /* 2638 * Handle deferred root intr xfer, in case we just switched off 2639 * polling. It's not safe to complete root intr xfers while 2640 * polling -- too much kernel machinery gets involved. 2641 */ 2642 if (!xhci_polling_p(sc)) { 2643 for (bn = 0; bn < 2; bn++) { 2644 if (__predict_false(sc->sc_intrxfer_deferred[bn])) { 2645 sc->sc_intrxfer_deferred[bn] = false; 2646 usb_transfer_complete(sc->sc_intrxfer[bn]); 2647 } 2648 } 2649 } 2650 2651 while (1) { 2652 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2653 BUS_DMASYNC_POSTREAD); 2654 trb = &er->xr_trb[i]; 2655 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2656 2657 if (j != k) 2658 break; 2659 2660 xhci_handle_event(sc, trb); 2661 2662 i++; 2663 if (i == er->xr_ntrb) { 2664 i = 0; 2665 j ^= 1; 2666 } 2667 } 2668 2669 er->xr_ep = i; 2670 er->xr_cs = j; 2671 2672 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2673 XHCI_ERDP_BUSY); 2674 2675 DPRINTFN(16, "ends", 0, 0, 0, 0); 2676 2677 return; 2678 } 2679 2680 static void 2681 xhci_poll(struct usbd_bus *bus) 2682 { 2683 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2684 2685 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2686 2687 mutex_enter(&sc->sc_intr_lock); 2688 int ret = xhci_intr1(sc); 2689 if (ret) { 2690 xhci_softintr(bus); 2691 } 2692 mutex_exit(&sc->sc_intr_lock); 2693 2694 return; 2695 } 2696 2697 static struct usbd_xfer * 2698 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2699 { 2700 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2701 struct xhci_xfer *xx; 2702 u_int ntrbs; 2703 2704 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2705 2706 ntrbs = uimax(3, nframes); 2707 const size_t trbsz = sizeof(*xx->xx_trb) * ntrbs; 2708 2709 xx = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2710 if (xx != NULL) { 2711 memset(xx, 0, sizeof(*xx)); 2712 if (ntrbs > 0) { 2713 xx->xx_trb = kmem_alloc(trbsz, KM_SLEEP); 2714 xx->xx_ntrb = ntrbs; 2715 } 2716 #ifdef DIAGNOSTIC 2717 xx->xx_xfer.ux_state = XFER_BUSY; 2718 #endif 2719 } 2720 2721 return &xx->xx_xfer; 2722 } 2723 2724 static void 2725 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2726 { 2727 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2728 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 2729 2730 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2731 2732 #ifdef DIAGNOSTIC 2733 if (xfer->ux_state != XFER_BUSY && 2734 xfer->ux_status != USBD_NOT_STARTED) { 2735 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2736 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2737 } 2738 xfer->ux_state = XFER_FREE; 2739 #endif 2740 if (xx->xx_ntrb > 0) { 2741 kmem_free(xx->xx_trb, xx->xx_ntrb * sizeof(*xx->xx_trb)); 2742 xx->xx_trb = NULL; 2743 xx->xx_ntrb = 0; 2744 } 2745 pool_cache_put(sc->sc_xferpool, xx); 2746 } 2747 2748 static bool 2749 xhci_dying(struct usbd_bus *bus) 2750 { 2751 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2752 2753 return sc->sc_dying; 2754 } 2755 2756 static void 2757 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2758 { 2759 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2760 2761 *lock = &sc->sc_lock; 2762 } 2763 2764 extern uint32_t usb_cookie_no; 2765 2766 /* 2767 * xHCI 4.3 2768 * Called when uhub_explore finds a new device (via usbd_new_device). 2769 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2770 * This function does: 2771 * Allocate and construct dev structure of default endpoint (ep0). 2772 * Allocate and open pipe of ep0. 2773 * Enable slot and initialize slot context. 2774 * Set Address. 2775 * Read initial device descriptor. 2776 * Determine initial MaxPacketSize (mps) by speed. 2777 * Read full device descriptor. 2778 * Register this device. 2779 * Finally state of device transitions ADDRESSED. 2780 */ 2781 static usbd_status 2782 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2783 int speed, int port, struct usbd_port *up) 2784 { 2785 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2786 struct usbd_device *dev; 2787 usbd_status err; 2788 usb_device_descriptor_t *dd; 2789 struct xhci_slot *xs; 2790 uint32_t *cp; 2791 2792 XHCIHIST_FUNC(); 2793 XHCIHIST_CALLARGS("port %ju depth %ju speed %ju up %#jx", 2794 port, depth, speed, (uintptr_t)up); 2795 2796 KASSERT(KERNEL_LOCKED_P()); 2797 2798 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2799 dev->ud_bus = bus; 2800 dev->ud_quirks = &usbd_no_quirk; 2801 dev->ud_addr = 0; 2802 dev->ud_ddesc.bMaxPacketSize = 0; 2803 dev->ud_depth = depth; 2804 dev->ud_powersrc = up; 2805 dev->ud_myhub = up->up_parent; 2806 dev->ud_speed = speed; 2807 dev->ud_langid = USBD_NOLANG; 2808 dev->ud_cookie.cookie = ++usb_cookie_no; 2809 2810 /* Set up default endpoint handle. */ 2811 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2812 /* doesn't matter, just don't let it uninitialized */ 2813 dev->ud_ep0.ue_toggle = 0; 2814 2815 /* Set up default endpoint descriptor. */ 2816 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2817 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2818 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2819 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2820 dev->ud_ep0desc.bInterval = 0; 2821 2822 /* 4.3, 4.8.2.1 */ 2823 switch (speed) { 2824 case USB_SPEED_SUPER: 2825 case USB_SPEED_SUPER_PLUS: 2826 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2827 break; 2828 case USB_SPEED_FULL: 2829 /* XXX using 64 as initial mps of ep0 in FS */ 2830 case USB_SPEED_HIGH: 2831 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2832 break; 2833 case USB_SPEED_LOW: 2834 default: 2835 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2836 break; 2837 } 2838 2839 up->up_dev = dev; 2840 2841 dd = &dev->ud_ddesc; 2842 2843 if (depth == 0 && port == 0) { 2844 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2845 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2846 2847 /* Establish the default pipe. */ 2848 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2849 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2850 if (err) { 2851 DPRINTFN(1, "setup default pipe failed %jd", err,0,0,0); 2852 goto bad; 2853 } 2854 err = usbd_get_initial_ddesc(dev, dd); 2855 if (err) { 2856 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2857 goto bad; 2858 } 2859 } else { 2860 uint8_t slot = 0; 2861 2862 /* 4.3.2 */ 2863 err = xhci_enable_slot(sc, &slot); 2864 if (err) { 2865 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2866 goto bad; 2867 } 2868 2869 xs = &sc->sc_slots[slot]; 2870 dev->ud_hcpriv = xs; 2871 2872 /* 4.3.3 initialize slot structure */ 2873 err = xhci_init_slot(dev, slot); 2874 if (err) { 2875 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2876 dev->ud_hcpriv = NULL; 2877 /* 2878 * We have to disable_slot here because 2879 * xs->xs_idx == 0 when xhci_init_slot fails, 2880 * in that case usbd_remove_dev won't work. 2881 */ 2882 mutex_enter(&sc->sc_lock); 2883 xhci_disable_slot(sc, slot); 2884 mutex_exit(&sc->sc_lock); 2885 goto bad; 2886 } 2887 2888 /* 2889 * We have to establish the default pipe _after_ slot 2890 * structure has been prepared. 2891 */ 2892 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2893 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2894 if (err) { 2895 DPRINTFN(1, "setup default pipe failed %jd", err, 0, 0, 2896 0); 2897 goto bad; 2898 } 2899 2900 /* 4.3.4 Address Assignment */ 2901 err = xhci_set_address(dev, slot, false); 2902 if (err) { 2903 DPRINTFN(1, "failed! to set address: %ju", err, 0, 0, 0); 2904 goto bad; 2905 } 2906 2907 /* Allow device time to set new address */ 2908 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2909 2910 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2911 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2912 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2913 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2914 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2915 /* 2916 * XXX ensure we know when the hardware does something 2917 * we can't yet cope with 2918 */ 2919 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2920 dev->ud_addr = addr; 2921 2922 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2923 "addr %d already allocated", dev->ud_addr); 2924 /* 2925 * The root hub is given its own slot 2926 */ 2927 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2928 2929 err = usbd_get_initial_ddesc(dev, dd); 2930 if (err) { 2931 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2932 goto bad; 2933 } 2934 2935 /* 4.8.2.1 */ 2936 if (USB_IS_SS(speed)) { 2937 if (dd->bMaxPacketSize != 9) { 2938 printf("%s: invalid mps 2^%u for SS ep0," 2939 " using 512\n", 2940 device_xname(sc->sc_dev), 2941 dd->bMaxPacketSize); 2942 dd->bMaxPacketSize = 9; 2943 } 2944 USETW(dev->ud_ep0desc.wMaxPacketSize, 2945 (1 << dd->bMaxPacketSize)); 2946 } else 2947 USETW(dev->ud_ep0desc.wMaxPacketSize, 2948 dd->bMaxPacketSize); 2949 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2950 err = xhci_update_ep0_mps(sc, xs, 2951 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2952 if (err) { 2953 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2954 goto bad; 2955 } 2956 } 2957 2958 err = usbd_reload_device_desc(dev); 2959 if (err) { 2960 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2961 goto bad; 2962 } 2963 2964 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2965 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2966 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2967 dd->bDeviceClass, dd->bDeviceSubClass, 2968 dd->bDeviceProtocol, 0); 2969 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2970 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2971 dev->ud_speed); 2972 2973 usbd_get_device_strings(dev); 2974 2975 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2976 2977 if (depth == 0 && port == 0) { 2978 usbd_attach_roothub(parent, dev); 2979 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2980 return USBD_NORMAL_COMPLETION; 2981 } 2982 2983 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2984 bad: 2985 if (err != USBD_NORMAL_COMPLETION) { 2986 if (depth == 0 && port == 0 && dev->ud_pipe0) 2987 usbd_kill_pipe(dev->ud_pipe0); 2988 usbd_remove_device(dev, up); 2989 } 2990 2991 return err; 2992 } 2993 2994 static usbd_status 2995 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring **xrp, 2996 size_t ntrb, size_t align) 2997 { 2998 size_t size = ntrb * XHCI_TRB_SIZE; 2999 struct xhci_ring *xr; 3000 3001 XHCIHIST_FUNC(); 3002 XHCIHIST_CALLARGS("xr %#jx ntrb %#jx align %#jx", 3003 (uintptr_t)*xrp, ntrb, align, 0); 3004 3005 xr = kmem_zalloc(sizeof(struct xhci_ring), KM_SLEEP); 3006 DPRINTFN(1, "ring %#jx", (uintptr_t)xr, 0, 0, 0); 3007 3008 int err = usb_allocmem(sc->sc_bus.ub_dmatag, size, align, 3009 USBMALLOC_COHERENT | USBMALLOC_ZERO, &xr->xr_dma); 3010 if (err) { 3011 kmem_free(xr, sizeof(struct xhci_ring)); 3012 DPRINTFN(1, "alloc xr_dma failed %jd", err, 0, 0, 0); 3013 return err; 3014 } 3015 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 3016 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 3017 xr->xr_trb = xhci_ring_trbv(xr, 0); 3018 xr->xr_ntrb = ntrb; 3019 xr->is_halted = false; 3020 xhci_host_dequeue(xr); 3021 *xrp = xr; 3022 3023 return USBD_NORMAL_COMPLETION; 3024 } 3025 3026 static void 3027 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring ** const xr) 3028 { 3029 if (*xr == NULL) 3030 return; 3031 3032 usb_freemem(&(*xr)->xr_dma); 3033 mutex_destroy(&(*xr)->xr_lock); 3034 kmem_free((*xr)->xr_cookies, 3035 sizeof(*(*xr)->xr_cookies) * (*xr)->xr_ntrb); 3036 kmem_free(*xr, sizeof(struct xhci_ring)); 3037 *xr = NULL; 3038 } 3039 3040 static void 3041 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 3042 void *cookie, struct xhci_soft_trb * const trbs, size_t ntrbs) 3043 { 3044 size_t i; 3045 u_int ri; 3046 u_int cs; 3047 uint64_t parameter; 3048 uint32_t status; 3049 uint32_t control; 3050 3051 XHCIHIST_FUNC(); 3052 XHCIHIST_CALLARGS("%#jx xr_ep %#jx xr_cs %ju", 3053 (uintptr_t)xr, xr->xr_ep, xr->xr_cs, 0); 3054 3055 KASSERTMSG(ntrbs < xr->xr_ntrb, "ntrbs %zu, xr->xr_ntrb %u", 3056 ntrbs, xr->xr_ntrb); 3057 for (i = 0; i < ntrbs; i++) { 3058 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 3059 (uintptr_t)trbs, i, 0); 3060 DPRINTFN(12, " 0x%016jx 0x%08jx 0x%08jx", 3061 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 3062 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 3063 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 3064 } 3065 3066 ri = xr->xr_ep; 3067 cs = xr->xr_cs; 3068 3069 /* 3070 * Although the xhci hardware can do scatter/gather dma from 3071 * arbitrary sized buffers, there is a non-obvious restriction 3072 * that a LINK trb is only allowed at the end of a burst of 3073 * transfers - which might be 16kB. 3074 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 3075 * The simple solution is not to allow a LINK trb in the middle 3076 * of anything - as here. 3077 * XXX: (dsl) There are xhci controllers out there (eg some made by 3078 * ASMedia) that seem to lock up if they process a LINK trb but 3079 * cannot process the linked-to trb yet. 3080 * The code should write the 'cycle' bit on the link trb AFTER 3081 * adding the other trb. 3082 */ 3083 u_int firstep = xr->xr_ep; 3084 u_int firstcs = xr->xr_cs; 3085 3086 for (i = 0; i < ntrbs; ) { 3087 u_int oldri = ri; 3088 u_int oldcs = cs; 3089 3090 if (ri >= (xr->xr_ntrb - 1)) { 3091 /* Put Link TD at the end of ring */ 3092 parameter = xhci_ring_trbp(xr, 0); 3093 status = 0; 3094 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 3095 XHCI_TRB_3_TC_BIT; 3096 xr->xr_cookies[ri] = NULL; 3097 xr->xr_ep = 0; 3098 xr->xr_cs ^= 1; 3099 ri = xr->xr_ep; 3100 cs = xr->xr_cs; 3101 } else { 3102 parameter = trbs[i].trb_0; 3103 status = trbs[i].trb_2; 3104 control = trbs[i].trb_3; 3105 3106 xr->xr_cookies[ri] = cookie; 3107 ri++; 3108 i++; 3109 } 3110 /* 3111 * If this is a first TRB, mark it invalid to prevent 3112 * xHC from running it immediately. 3113 */ 3114 if (oldri == firstep) { 3115 if (oldcs) { 3116 control &= ~XHCI_TRB_3_CYCLE_BIT; 3117 } else { 3118 control |= XHCI_TRB_3_CYCLE_BIT; 3119 } 3120 } else { 3121 if (oldcs) { 3122 control |= XHCI_TRB_3_CYCLE_BIT; 3123 } else { 3124 control &= ~XHCI_TRB_3_CYCLE_BIT; 3125 } 3126 } 3127 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 3128 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 3129 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3130 } 3131 3132 /* Now invert cycle bit of first TRB */ 3133 if (firstcs) { 3134 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 3135 } else { 3136 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 3137 } 3138 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 3139 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 3140 3141 xr->xr_ep = ri; 3142 xr->xr_cs = cs; 3143 3144 DPRINTFN(12, "%#jx xr_ep %#jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 3145 xr->xr_cs, 0); 3146 } 3147 3148 static inline void 3149 xhci_ring_put_xfer(struct xhci_softc * const sc, struct xhci_ring * const tr, 3150 struct xhci_xfer *xx, u_int ntrb) 3151 { 3152 KASSERT(ntrb <= xx->xx_ntrb); 3153 xhci_ring_put(sc, tr, xx, xx->xx_trb, ntrb); 3154 } 3155 3156 /* 3157 * Stop execution commands, purge all commands on command ring, and 3158 * rewind dequeue pointer. 3159 */ 3160 static void 3161 xhci_abort_command(struct xhci_softc *sc) 3162 { 3163 struct xhci_ring * const cr = sc->sc_cr; 3164 uint64_t crcr; 3165 int i; 3166 3167 XHCIHIST_FUNC(); 3168 XHCIHIST_CALLARGS("command %#jx timeout, aborting", 3169 sc->sc_command_addr, 0, 0, 0); 3170 3171 mutex_enter(&cr->xr_lock); 3172 3173 /* 4.6.1.2 Aborting a Command */ 3174 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3175 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 3176 3177 for (i = 0; i < 500; i++) { 3178 crcr = xhci_op_read_8(sc, XHCI_CRCR); 3179 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 3180 break; 3181 usb_delay_ms(&sc->sc_bus, 1); 3182 } 3183 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 3184 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 3185 /* reset HC here? */ 3186 } 3187 3188 /* reset command ring dequeue pointer */ 3189 cr->xr_ep = 0; 3190 cr->xr_cs = 1; 3191 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 3192 3193 mutex_exit(&cr->xr_lock); 3194 } 3195 3196 /* 3197 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 3198 * Command completion is notified by cv_signal from xhci_event_cmd() 3199 * (called from xhci_softint), or timed-out. 3200 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 3201 * then do_command examines it. 3202 */ 3203 static usbd_status 3204 xhci_do_command_locked(struct xhci_softc * const sc, 3205 struct xhci_soft_trb * const trb, int timeout) 3206 { 3207 struct xhci_ring * const cr = sc->sc_cr; 3208 usbd_status err; 3209 3210 XHCIHIST_FUNC(); 3211 XHCIHIST_CALLARGS("input: 0x%016jx 0x%08jx 0x%08jx", 3212 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3213 3214 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 3215 KASSERT(mutex_owned(&sc->sc_lock)); 3216 3217 while (sc->sc_command_addr != 0 || 3218 (sc->sc_suspender != NULL && sc->sc_suspender != curlwp)) 3219 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 3220 3221 /* 3222 * If enqueue pointer points at last of ring, it's Link TRB, 3223 * command TRB will be stored in 0th TRB. 3224 */ 3225 if (cr->xr_ep == cr->xr_ntrb - 1) 3226 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 3227 else 3228 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 3229 3230 sc->sc_resultpending = true; 3231 3232 mutex_enter(&cr->xr_lock); 3233 xhci_ring_put(sc, cr, NULL, trb, 1); 3234 mutex_exit(&cr->xr_lock); 3235 3236 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 3237 3238 while (sc->sc_resultpending) { 3239 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 3240 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 3241 xhci_abort_command(sc); 3242 err = USBD_TIMEOUT; 3243 goto timedout; 3244 } 3245 } 3246 3247 trb->trb_0 = sc->sc_result_trb.trb_0; 3248 trb->trb_2 = sc->sc_result_trb.trb_2; 3249 trb->trb_3 = sc->sc_result_trb.trb_3; 3250 3251 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 3252 trb->trb_0, trb->trb_2, trb->trb_3, 0); 3253 3254 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 3255 case XHCI_TRB_ERROR_SUCCESS: 3256 err = USBD_NORMAL_COMPLETION; 3257 break; 3258 default: 3259 case 192 ... 223: 3260 DPRINTFN(5, "error %#jx", 3261 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0); 3262 err = USBD_IOERROR; 3263 break; 3264 case 224 ... 255: 3265 err = USBD_NORMAL_COMPLETION; 3266 break; 3267 } 3268 3269 timedout: 3270 sc->sc_resultpending = false; 3271 sc->sc_command_addr = 0; 3272 cv_broadcast(&sc->sc_cmdbusy_cv); 3273 3274 return err; 3275 } 3276 3277 static usbd_status 3278 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb, 3279 int timeout) 3280 { 3281 3282 mutex_enter(&sc->sc_lock); 3283 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 3284 mutex_exit(&sc->sc_lock); 3285 3286 return ret; 3287 } 3288 3289 static usbd_status 3290 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 3291 { 3292 struct xhci_soft_trb trb; 3293 usbd_status err; 3294 3295 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3296 3297 trb.trb_0 = 0; 3298 trb.trb_2 = 0; 3299 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 3300 3301 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3302 if (err != USBD_NORMAL_COMPLETION) { 3303 return err; 3304 } 3305 3306 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 3307 3308 return err; 3309 } 3310 3311 /* 3312 * xHCI 4.6.4 3313 * Deallocate ring and device/input context DMA buffers, and disable_slot. 3314 * All endpoints in the slot should be stopped. 3315 * Should be called with sc_lock held. 3316 */ 3317 static usbd_status 3318 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 3319 { 3320 struct xhci_soft_trb trb; 3321 struct xhci_slot *xs; 3322 usbd_status err; 3323 3324 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3325 3326 if (sc->sc_dying) 3327 return USBD_IOERROR; 3328 3329 trb.trb_0 = 0; 3330 trb.trb_2 = 0; 3331 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) | 3332 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT); 3333 3334 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 3335 3336 if (!err) { 3337 xs = &sc->sc_slots[slot]; 3338 if (xs->xs_idx != 0) { 3339 xhci_free_slot(sc, xs); 3340 xhci_set_dcba(sc, 0, slot); 3341 memset(xs, 0, sizeof(*xs)); 3342 } 3343 } 3344 3345 return err; 3346 } 3347 3348 /* 3349 * Set address of device and transition slot state from ENABLED to ADDRESSED 3350 * if Block Setaddress Request (BSR) is false. 3351 * If BSR==true, transition slot state from ENABLED to DEFAULT. 3352 * see xHCI 1.1 4.5.3, 3.3.4 3353 * Should be called without sc_lock held. 3354 */ 3355 static usbd_status 3356 xhci_address_device(struct xhci_softc * const sc, 3357 uint64_t icp, uint8_t slot_id, bool bsr) 3358 { 3359 struct xhci_soft_trb trb; 3360 usbd_status err; 3361 3362 XHCIHIST_FUNC(); 3363 if (bsr) { 3364 XHCIHIST_CALLARGS("icp %#jx slot %#jx with bsr", 3365 icp, slot_id, 0, 0); 3366 } else { 3367 XHCIHIST_CALLARGS("icp %#jx slot %#jx nobsr", 3368 icp, slot_id, 0, 0); 3369 } 3370 3371 trb.trb_0 = icp; 3372 trb.trb_2 = 0; 3373 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 3374 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 3375 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 3376 3377 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3378 3379 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 3380 err = USBD_NO_ADDR; 3381 3382 return err; 3383 } 3384 3385 static usbd_status 3386 xhci_update_ep0_mps(struct xhci_softc * const sc, 3387 struct xhci_slot * const xs, u_int mps) 3388 { 3389 struct xhci_soft_trb trb; 3390 usbd_status err; 3391 uint32_t * cp; 3392 3393 XHCIHIST_FUNC(); 3394 XHCIHIST_CALLARGS("slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 3395 3396 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3397 cp[0] = htole32(0); 3398 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 3399 3400 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 3401 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 3402 3403 /* sync input contexts before they are read from memory */ 3404 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3405 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3406 sc->sc_ctxsz * 4); 3407 3408 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 3409 trb.trb_2 = 0; 3410 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 3411 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 3412 3413 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 3414 return err; 3415 } 3416 3417 static void 3418 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 3419 { 3420 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 3421 3422 XHCIHIST_FUNC(); 3423 XHCIHIST_CALLARGS("dcbaa %#jx dc 0x%016jx slot %jd", 3424 (uintptr_t)&dcbaa[si], dcba, si, 0); 3425 3426 dcbaa[si] = htole64(dcba); 3427 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 3428 BUS_DMASYNC_PREWRITE); 3429 } 3430 3431 /* 3432 * Allocate device and input context DMA buffer, and 3433 * TRB DMA buffer for each endpoint. 3434 */ 3435 static usbd_status 3436 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 3437 { 3438 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3439 struct xhci_slot *xs; 3440 3441 XHCIHIST_FUNC(); 3442 XHCIHIST_CALLARGS("slot %ju", slot, 0, 0, 0); 3443 3444 xs = &sc->sc_slots[slot]; 3445 3446 /* allocate contexts */ 3447 int err = usb_allocmem(sc->sc_bus.ub_dmatag, sc->sc_pgsz, sc->sc_pgsz, 3448 USBMALLOC_COHERENT | USBMALLOC_ZERO, &xs->xs_dc_dma); 3449 if (err) { 3450 DPRINTFN(1, "failed to allocmem output device context %jd", 3451 err, 0, 0, 0); 3452 return USBD_NOMEM; 3453 } 3454 3455 err = usb_allocmem(sc->sc_bus.ub_dmatag, sc->sc_pgsz, sc->sc_pgsz, 3456 USBMALLOC_COHERENT | USBMALLOC_ZERO, &xs->xs_ic_dma); 3457 if (err) { 3458 DPRINTFN(1, "failed to allocmem input device context %jd", 3459 err, 0, 0, 0); 3460 goto bad1; 3461 } 3462 3463 memset(&xs->xs_xr[0], 0, sizeof(xs->xs_xr)); 3464 xs->xs_idx = slot; 3465 3466 return USBD_NORMAL_COMPLETION; 3467 3468 bad1: 3469 usb_freemem(&xs->xs_dc_dma); 3470 xs->xs_idx = 0; 3471 return USBD_NOMEM; 3472 } 3473 3474 static void 3475 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs) 3476 { 3477 u_int dci; 3478 3479 XHCIHIST_FUNC(); 3480 XHCIHIST_CALLARGS("slot %ju", xs->xs_idx, 0, 0, 0); 3481 3482 /* deallocate all allocated rings in the slot */ 3483 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) { 3484 if (xs->xs_xr[dci] != NULL) 3485 xhci_ring_free(sc, &xs->xs_xr[dci]); 3486 } 3487 usb_freemem(&xs->xs_ic_dma); 3488 usb_freemem(&xs->xs_dc_dma); 3489 xs->xs_idx = 0; 3490 } 3491 3492 /* 3493 * Setup slot context, set Device Context Base Address, and issue 3494 * Set Address Device command. 3495 */ 3496 static usbd_status 3497 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 3498 { 3499 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3500 struct xhci_slot *xs; 3501 usbd_status err; 3502 3503 XHCIHIST_FUNC(); 3504 XHCIHIST_CALLARGS("slot %ju bsr %ju", slot, bsr, 0, 0); 3505 3506 xs = &sc->sc_slots[slot]; 3507 3508 xhci_setup_ctx(dev->ud_pipe0); 3509 3510 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 3511 sc->sc_ctxsz * 3); 3512 3513 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3514 3515 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3516 3517 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3518 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 3519 sc->sc_ctxsz * 2); 3520 3521 return err; 3522 } 3523 3524 /* 3525 * 4.8.2, 6.2.3.2 3526 * construct slot/endpoint context parameters and do syncmem 3527 */ 3528 static void 3529 xhci_setup_ctx(struct usbd_pipe *pipe) 3530 { 3531 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3532 struct usbd_device *dev = pipe->up_dev; 3533 struct xhci_slot * const xs = dev->ud_hcpriv; 3534 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3535 const u_int dci = xhci_ep_get_dci(ed); 3536 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3537 uint32_t *cp; 3538 uint16_t mps = UGETW(ed->wMaxPacketSize); 3539 uint8_t speed = dev->ud_speed; 3540 uint8_t ival = ed->bInterval; 3541 3542 XHCIHIST_FUNC(); 3543 XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju", 3544 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3545 3546 /* set up initial input control context */ 3547 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3548 cp[0] = htole32(0); 3549 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3550 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3551 cp[7] = htole32(0); 3552 3553 /* set up input slot context */ 3554 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3555 cp[0] = 3556 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3557 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3558 cp[1] = 0; 3559 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3560 cp[3] = 0; 3561 xhci_setup_route(pipe, cp); 3562 xhci_setup_tthub(pipe, cp); 3563 3564 cp[0] = htole32(cp[0]); 3565 cp[1] = htole32(cp[1]); 3566 cp[2] = htole32(cp[2]); 3567 cp[3] = htole32(cp[3]); 3568 3569 /* set up input endpoint context */ 3570 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3571 cp[0] = 3572 XHCI_EPCTX_0_EPSTATE_SET(0) | 3573 XHCI_EPCTX_0_MULT_SET(0) | 3574 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3575 XHCI_EPCTX_0_LSA_SET(0) | 3576 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3577 cp[1] = 3578 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3579 XHCI_EPCTX_1_HID_SET(0) | 3580 XHCI_EPCTX_1_MAXB_SET(0); 3581 3582 if (xfertype != UE_ISOCHRONOUS) 3583 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3584 3585 if (xfertype == UE_CONTROL) 3586 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3587 else if (USB_IS_SS(speed)) 3588 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3589 else 3590 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3591 3592 xhci_setup_maxburst(pipe, cp); 3593 3594 switch (xfertype) { 3595 case UE_CONTROL: 3596 break; 3597 case UE_BULK: 3598 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3599 break; 3600 case UE_INTERRUPT: 3601 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3602 ival = pipe->up_interval; 3603 3604 ival = xhci_bival2ival(ival, speed); 3605 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3606 break; 3607 case UE_ISOCHRONOUS: 3608 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3609 ival = pipe->up_interval; 3610 3611 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3612 if (speed == USB_SPEED_FULL) 3613 ival += 3; /* 1ms -> 125us */ 3614 ival--; 3615 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3616 break; 3617 default: 3618 break; 3619 } 3620 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3621 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3622 3623 /* rewind TR dequeue pointer in xHC */ 3624 /* can't use xhci_ep_get_dci() yet? */ 3625 *(uint64_t *)(&cp[2]) = htole64( 3626 xhci_ring_trbp(xs->xs_xr[dci], 0) | 3627 XHCI_EPCTX_2_DCS_SET(1)); 3628 3629 cp[0] = htole32(cp[0]); 3630 cp[1] = htole32(cp[1]); 3631 cp[4] = htole32(cp[4]); 3632 3633 /* rewind TR dequeue pointer in driver */ 3634 struct xhci_ring *xr = xs->xs_xr[dci]; 3635 mutex_enter(&xr->xr_lock); 3636 xhci_host_dequeue(xr); 3637 mutex_exit(&xr->xr_lock); 3638 3639 /* sync input contexts before they are read from memory */ 3640 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3641 } 3642 3643 /* 3644 * Setup route string and roothub port of given device for slot context 3645 */ 3646 static void 3647 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3648 { 3649 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3650 struct usbd_device *dev = pipe->up_dev; 3651 struct usbd_port *up = dev->ud_powersrc; 3652 struct usbd_device *hub; 3653 struct usbd_device *adev; 3654 uint8_t rhport = 0; 3655 uint32_t route = 0; 3656 3657 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3658 3659 /* Locate root hub port and Determine route string */ 3660 /* 4.3.3 route string does not include roothub port */ 3661 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3662 uint32_t dep; 3663 3664 DPRINTFN(4, "hub %#jx depth %jd upport %#jx upportno %jd", 3665 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3666 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3667 -1); 3668 3669 if (hub->ud_powersrc == NULL) 3670 break; 3671 dep = hub->ud_depth; 3672 if (dep == 0) 3673 break; 3674 rhport = hub->ud_powersrc->up_portno; 3675 if (dep > USB_HUB_MAX_DEPTH) 3676 continue; 3677 3678 route |= 3679 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3680 << ((dep - 1) * 4); 3681 } 3682 route = route >> 4; 3683 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3684 3685 /* Locate port on upstream high speed hub */ 3686 for (adev = dev, hub = up->up_parent; 3687 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3688 adev = hub, hub = hub->ud_myhub) 3689 ; 3690 if (hub) { 3691 int p; 3692 for (p = 1; p <= hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3693 if (hub->ud_hub->uh_ports[p - 1].up_dev == adev) { 3694 dev->ud_myhsport = &hub->ud_hub->uh_ports[p - 1]; 3695 goto found; 3696 } 3697 } 3698 panic("%s: cannot find HS port", __func__); 3699 found: 3700 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3701 } else { 3702 dev->ud_myhsport = NULL; 3703 } 3704 3705 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3706 3707 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3708 ctlrport, route, (uintptr_t)hub); 3709 3710 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3711 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3712 } 3713 3714 /* 3715 * Setup whether device is hub, whether device uses MTT, and 3716 * TT informations if it uses MTT. 3717 */ 3718 static void 3719 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3720 { 3721 struct usbd_device *dev = pipe->up_dev; 3722 struct usbd_port *myhsport = dev->ud_myhsport; 3723 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3724 uint32_t speed = dev->ud_speed; 3725 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3726 uint8_t tthubslot, ttportnum; 3727 bool ishub; 3728 bool usemtt; 3729 3730 XHCIHIST_FUNC(); 3731 3732 /* 3733 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3734 * tthubslot: 3735 * This is the slot ID of parent HS hub 3736 * if LS/FS device is connected && connected through HS hub. 3737 * This is 0 if device is not LS/FS device || 3738 * parent hub is not HS hub || 3739 * attached to root hub. 3740 * ttportnum: 3741 * This is the downstream facing port of parent HS hub 3742 * if LS/FS device is connected. 3743 * This is 0 if device is not LS/FS device || 3744 * parent hub is not HS hub || 3745 * attached to root hub. 3746 */ 3747 if (myhsport && 3748 myhsport->up_parent->ud_addr != rhaddr && 3749 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3750 ttportnum = myhsport->up_portno; 3751 tthubslot = myhsport->up_parent->ud_addr; 3752 } else { 3753 ttportnum = 0; 3754 tthubslot = 0; 3755 } 3756 XHCIHIST_CALLARGS("myhsport %#jx ttportnum=%jd tthubslot=%jd", 3757 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3758 3759 /* ishub is valid after reading UDESC_DEVICE */ 3760 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3761 3762 /* dev->ud_hub is valid after reading UDESC_HUB */ 3763 if (ishub && dev->ud_hub) { 3764 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3765 uint8_t ttt = 3766 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3767 3768 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3769 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3770 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3771 } 3772 3773 #define IS_MTTHUB(dd) \ 3774 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3775 3776 /* 3777 * MTT flag is set if 3778 * 1. this is HS hub && MTTs are supported and enabled; or 3779 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3780 * are supported and enabled. 3781 * 3782 * XXX enabled is not tested yet 3783 */ 3784 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3785 usemtt = true; 3786 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3787 myhsport && 3788 myhsport->up_parent->ud_addr != rhaddr && 3789 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3790 usemtt = true; 3791 else 3792 usemtt = false; 3793 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3794 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3795 3796 #undef IS_MTTHUB 3797 3798 cp[0] |= 3799 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3800 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3801 cp[2] |= 3802 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3803 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3804 } 3805 3806 /* set up params for periodic endpoint */ 3807 static void 3808 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3809 { 3810 struct xhci_pipe * const xpipe = (struct xhci_pipe *)pipe; 3811 struct usbd_device *dev = pipe->up_dev; 3812 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3813 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3814 usbd_desc_iter_t iter; 3815 const usb_cdc_descriptor_t *cdcd; 3816 uint32_t maxb = 0; 3817 uint16_t mps = UGETW(ed->wMaxPacketSize); 3818 uint8_t speed = dev->ud_speed; 3819 uint8_t mult = 0; 3820 uint8_t ep; 3821 3822 /* config desc is NULL when opening ep0 */ 3823 if (dev == NULL || dev->ud_cdesc == NULL) 3824 goto no_cdcd; 3825 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3826 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3827 if (cdcd == NULL) 3828 goto no_cdcd; 3829 usb_desc_iter_init(dev, &iter); 3830 iter.cur = (const void *)cdcd; 3831 3832 /* find endpoint_ss_comp desc for ep of this pipe */ 3833 for (ep = 0;;) { 3834 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3835 if (cdcd == NULL) 3836 break; 3837 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3838 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3839 bEndpointAddress; 3840 if (UE_GET_ADDR(ep) == 3841 UE_GET_ADDR(ed->bEndpointAddress)) { 3842 cdcd = (const usb_cdc_descriptor_t *) 3843 usb_desc_iter_next(&iter); 3844 break; 3845 } 3846 ep = 0; 3847 } 3848 } 3849 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3850 const usb_endpoint_ss_comp_descriptor_t * esscd = 3851 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3852 maxb = esscd->bMaxBurst; 3853 mult = UE_GET_SS_ISO_MULT(esscd->bmAttributes); 3854 } 3855 3856 no_cdcd: 3857 /* 6.2.3.4, 4.8.2.4 */ 3858 if (USB_IS_SS(speed)) { 3859 /* USB 3.1 9.6.6 */ 3860 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3861 /* USB 3.1 9.6.7 */ 3862 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3863 #ifdef notyet 3864 if (xfertype == UE_ISOCHRONOUS) { 3865 } 3866 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3867 /* use ESIT */ 3868 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3869 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3870 3871 /* XXX if LEC = 1, set ESIT instead */ 3872 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3873 } else { 3874 /* use ival */ 3875 } 3876 #endif 3877 } else { 3878 /* USB 2.0 9.6.6 */ 3879 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3880 3881 /* 6.2.3.4 */ 3882 if (speed == USB_SPEED_HIGH && 3883 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3884 maxb = UE_GET_TRANS(mps); 3885 } else { 3886 /* LS/FS or HS CTRL or HS BULK */ 3887 maxb = 0; 3888 } 3889 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3890 } 3891 xpipe->xp_maxb = maxb + 1; 3892 xpipe->xp_mult = mult + 1; 3893 } 3894 3895 /* 3896 * Convert endpoint bInterval value to endpoint context interval value 3897 * for Interrupt pipe. 3898 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3899 */ 3900 static uint32_t 3901 xhci_bival2ival(uint32_t ival, uint32_t speed) 3902 { 3903 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3904 int i; 3905 3906 /* 3907 * round ival down to "the nearest base 2 multiple of 3908 * bInterval * 8". 3909 * bInterval is at most 255 as its type is uByte. 3910 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3911 */ 3912 for (i = 10; i > 0; i--) { 3913 if ((ival * 8) >= (1 << i)) 3914 break; 3915 } 3916 ival = i; 3917 } else { 3918 /* Interval = bInterval-1 for SS/HS */ 3919 ival--; 3920 } 3921 3922 return ival; 3923 } 3924 3925 /* ----- */ 3926 3927 static void 3928 xhci_noop(struct usbd_pipe *pipe) 3929 { 3930 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3931 } 3932 3933 /* 3934 * Process root hub request. 3935 */ 3936 static int 3937 xhci_roothub_ctrl_locked(struct usbd_bus *bus, usb_device_request_t *req, 3938 void *buf, int buflen) 3939 { 3940 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3941 usb_port_status_t ps; 3942 int l, totlen = 0; 3943 uint16_t len, value, index; 3944 int port, i; 3945 uint32_t v; 3946 3947 XHCIHIST_FUNC(); 3948 3949 KASSERT(mutex_owned(&sc->sc_rhlock)); 3950 3951 if (sc->sc_dying) 3952 return -1; 3953 3954 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3955 3956 len = UGETW(req->wLength); 3957 value = UGETW(req->wValue); 3958 index = UGETW(req->wIndex); 3959 3960 XHCIHIST_CALLARGS("rhreq: %04jx %04jx %04jx %04jx", 3961 req->bmRequestType | (req->bRequest << 8), value, index, len); 3962 3963 #define C(x,y) ((x) | ((y) << 8)) 3964 switch (C(req->bRequest, req->bmRequestType)) { 3965 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3966 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3967 if (len == 0) 3968 break; 3969 switch (value) { 3970 #define sd ((usb_string_descriptor_t *)buf) 3971 case C(2, UDESC_STRING): 3972 /* Product */ 3973 totlen = usb_makestrdesc(sd, len, "xHCI root hub"); 3974 break; 3975 #undef sd 3976 default: 3977 /* default from usbroothub */ 3978 return buflen; 3979 } 3980 break; 3981 3982 /* Hub requests */ 3983 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3984 break; 3985 /* Clear Port Feature request */ 3986 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3987 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3988 3989 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3990 index, value, bn, cp); 3991 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3992 return -1; 3993 } 3994 port = XHCI_PORTSC(cp); 3995 v = xhci_op_read_4(sc, port); 3996 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3997 v &= ~XHCI_PS_CLEAR; 3998 switch (value) { 3999 case UHF_PORT_ENABLE: 4000 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 4001 break; 4002 case UHF_PORT_SUSPEND: 4003 return -1; 4004 case UHF_PORT_POWER: 4005 break; 4006 case UHF_PORT_TEST: 4007 case UHF_PORT_INDICATOR: 4008 return -1; 4009 case UHF_C_PORT_CONNECTION: 4010 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 4011 break; 4012 case UHF_C_PORT_ENABLE: 4013 case UHF_C_PORT_SUSPEND: 4014 case UHF_C_PORT_OVER_CURRENT: 4015 return -1; 4016 case UHF_C_BH_PORT_RESET: 4017 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 4018 break; 4019 case UHF_C_PORT_RESET: 4020 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 4021 break; 4022 case UHF_C_PORT_LINK_STATE: 4023 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 4024 break; 4025 case UHF_C_PORT_CONFIG_ERROR: 4026 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 4027 break; 4028 default: 4029 return -1; 4030 } 4031 break; 4032 } 4033 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 4034 if (len == 0) 4035 break; 4036 if ((value & 0xff) != 0) { 4037 return -1; 4038 } 4039 usb_hub_descriptor_t hubd; 4040 4041 totlen = uimin(buflen, sizeof(hubd)); 4042 memcpy(&hubd, buf, totlen); 4043 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 4044 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 4045 hubd.bPwrOn2PwrGood = 200; 4046 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 4047 /* XXX can't find out? */ 4048 hubd.DeviceRemovable[i++] = 0; 4049 } 4050 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 4051 totlen = uimin(totlen, hubd.bDescLength); 4052 memcpy(buf, &hubd, totlen); 4053 break; 4054 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 4055 if (len != 4) { 4056 return -1; 4057 } 4058 memset(buf, 0, len); /* ? XXX */ 4059 totlen = len; 4060 break; 4061 /* Get Port Status request */ 4062 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 4063 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 4064 4065 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 4066 bn, index, cp, 0); 4067 if (index < 1 || index > sc->sc_rhportcount[bn]) { 4068 DPRINTFN(5, "bad get port status: index=%jd bn=%jd " 4069 "portcount=%jd", 4070 index, bn, sc->sc_rhportcount[bn], 0); 4071 return -1; 4072 } 4073 if (len != 4) { 4074 DPRINTFN(5, "bad get port status: len %jd != 4", 4075 len, 0, 0, 0); 4076 return -1; 4077 } 4078 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 4079 DPRINTFN(4, "getrhportsc %jd 0x%08jx", cp, v, 0, 0); 4080 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 4081 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 4082 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 4083 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 4084 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 4085 if (v & XHCI_PS_PR) i |= UPS_RESET; 4086 if (v & XHCI_PS_PP) { 4087 if (i & UPS_OTHER_SPEED) 4088 i |= UPS_PORT_POWER_SS; 4089 else 4090 i |= UPS_PORT_POWER; 4091 } 4092 if (i & UPS_OTHER_SPEED) 4093 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 4094 if (sc->sc_vendor_port_status) 4095 i = sc->sc_vendor_port_status(sc, v, i); 4096 USETW(ps.wPortStatus, i); 4097 i = 0; 4098 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 4099 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 4100 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 4101 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 4102 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 4103 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 4104 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 4105 USETW(ps.wPortChange, i); 4106 totlen = uimin(len, sizeof(ps)); 4107 memcpy(buf, &ps, totlen); 4108 DPRINTFN(5, "get port status: wPortStatus %#jx wPortChange %#jx" 4109 " totlen %jd", 4110 UGETW(ps.wPortStatus), UGETW(ps.wPortChange), totlen, 0); 4111 break; 4112 } 4113 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 4114 return -1; 4115 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 4116 break; 4117 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 4118 break; 4119 /* Set Port Feature request */ 4120 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 4121 int optval = (index >> 8) & 0xff; 4122 index &= 0xff; 4123 if (index < 1 || index > sc->sc_rhportcount[bn]) { 4124 return -1; 4125 } 4126 4127 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 4128 4129 port = XHCI_PORTSC(cp); 4130 v = xhci_op_read_4(sc, port); 4131 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 4132 v &= ~XHCI_PS_CLEAR; 4133 switch (value) { 4134 case UHF_PORT_ENABLE: 4135 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 4136 break; 4137 case UHF_PORT_SUSPEND: 4138 /* XXX suspend */ 4139 break; 4140 case UHF_PORT_RESET: 4141 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 4142 /* Wait for reset to complete. */ 4143 for (i = 0; i < USB_PORT_ROOT_RESET_DELAY / 10; i++) { 4144 if (sc->sc_dying) { 4145 return -1; 4146 } 4147 v = xhci_op_read_4(sc, port); 4148 if ((v & XHCI_PS_PR) == 0) { 4149 break; 4150 } 4151 usb_delay_ms(&sc->sc_bus, 10); 4152 } 4153 break; 4154 case UHF_PORT_POWER: 4155 /* XXX power control */ 4156 break; 4157 /* XXX more */ 4158 case UHF_C_PORT_RESET: 4159 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 4160 break; 4161 case UHF_PORT_U1_TIMEOUT: 4162 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4163 return -1; 4164 } 4165 port = XHCI_PORTPMSC(cp); 4166 v = xhci_op_read_4(sc, port); 4167 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4168 index, cp, v, 0); 4169 v &= ~XHCI_PM3_U1TO_SET(0xff); 4170 v |= XHCI_PM3_U1TO_SET(optval); 4171 xhci_op_write_4(sc, port, v); 4172 break; 4173 case UHF_PORT_U2_TIMEOUT: 4174 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 4175 return -1; 4176 } 4177 port = XHCI_PORTPMSC(cp); 4178 v = xhci_op_read_4(sc, port); 4179 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 4180 index, cp, v, 0); 4181 v &= ~XHCI_PM3_U2TO_SET(0xff); 4182 v |= XHCI_PM3_U2TO_SET(optval); 4183 xhci_op_write_4(sc, port, v); 4184 break; 4185 default: 4186 return -1; 4187 } 4188 } 4189 break; 4190 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 4191 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 4192 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 4193 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 4194 break; 4195 default: 4196 /* default from usbroothub */ 4197 return buflen; 4198 } 4199 4200 return totlen; 4201 } 4202 4203 static int 4204 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 4205 void *buf, int buflen) 4206 { 4207 struct xhci_softc *sc = XHCI_BUS2SC(bus); 4208 int actlen; 4209 4210 mutex_enter(&sc->sc_rhlock); 4211 actlen = xhci_roothub_ctrl_locked(bus, req, buf, buflen); 4212 mutex_exit(&sc->sc_rhlock); 4213 4214 return actlen; 4215 } 4216 4217 /* root hub interrupt */ 4218 4219 static usbd_status 4220 xhci_root_intr_transfer(struct usbd_xfer *xfer) 4221 { 4222 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4223 4224 /* Pipe isn't running, start first */ 4225 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4226 } 4227 4228 /* Wait for roothub port status/change */ 4229 static usbd_status 4230 xhci_root_intr_start(struct usbd_xfer *xfer) 4231 { 4232 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4233 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4234 4235 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4236 4237 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4238 4239 if (sc->sc_dying) 4240 return USBD_IOERROR; 4241 4242 KASSERT(sc->sc_intrxfer[bn] == NULL); 4243 sc->sc_intrxfer[bn] = xfer; 4244 xfer->ux_status = USBD_IN_PROGRESS; 4245 4246 return USBD_IN_PROGRESS; 4247 } 4248 4249 static void 4250 xhci_root_intr_abort(struct usbd_xfer *xfer) 4251 { 4252 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4253 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4254 4255 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4256 4257 KASSERT(mutex_owned(&sc->sc_lock)); 4258 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4259 4260 /* If xfer has already completed, nothing to do here. */ 4261 if (sc->sc_intrxfer[bn] == NULL) 4262 return; 4263 4264 /* 4265 * Otherwise, sc->sc_intrxfer[bn] had better be this transfer. 4266 * Cancel it. 4267 */ 4268 KASSERT(sc->sc_intrxfer[bn] == xfer); 4269 xfer->ux_status = USBD_CANCELLED; 4270 usb_transfer_complete(xfer); 4271 } 4272 4273 static void 4274 xhci_root_intr_close(struct usbd_pipe *pipe) 4275 { 4276 struct xhci_softc * const sc __diagused = XHCI_PIPE2SC(pipe); 4277 const struct usbd_xfer *xfer __diagused = pipe->up_intrxfer; 4278 const size_t bn __diagused = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4279 4280 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4281 4282 KASSERT(mutex_owned(&sc->sc_lock)); 4283 4284 /* 4285 * Caller must guarantee the xfer has completed first, by 4286 * closing the pipe only after normal completion or an abort. 4287 */ 4288 KASSERT(sc->sc_intrxfer[bn] == NULL); 4289 } 4290 4291 static void 4292 xhci_root_intr_done(struct usbd_xfer *xfer) 4293 { 4294 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4295 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 4296 4297 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4298 4299 KASSERT(mutex_owned(&sc->sc_lock)); 4300 4301 /* Claim the xfer so it doesn't get completed again. */ 4302 KASSERT(sc->sc_intrxfer[bn] == xfer); 4303 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 4304 sc->sc_intrxfer[bn] = NULL; 4305 } 4306 4307 /* -------------- */ 4308 /* device control */ 4309 4310 static usbd_status 4311 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 4312 { 4313 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4314 4315 /* Pipe isn't running, start first */ 4316 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4317 } 4318 4319 static usbd_status 4320 xhci_device_ctrl_start(struct usbd_xfer *xfer) 4321 { 4322 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4323 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4324 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4325 struct xhci_ring * const tr = xs->xs_xr[dci]; 4326 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4327 usb_device_request_t * const req = &xfer->ux_request; 4328 const bool isread = usbd_xfer_isread(xfer); 4329 const uint32_t len = UGETW(req->wLength); 4330 usb_dma_t * const dma = &xfer->ux_dmabuf; 4331 uint64_t parameter; 4332 uint32_t status; 4333 uint32_t control; 4334 u_int i; 4335 const bool polling = xhci_polling_p(sc); 4336 4337 XHCIHIST_FUNC(); 4338 XHCIHIST_CALLARGS("req: %04jx %04jx %04jx %04jx", 4339 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 4340 UGETW(req->wIndex), UGETW(req->wLength)); 4341 4342 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4343 4344 /* we rely on the bottom bits for extra info */ 4345 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 4346 (uintptr_t) xfer); 4347 4348 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 4349 4350 if (tr->is_halted) 4351 goto out; 4352 4353 i = 0; 4354 4355 /* setup phase */ 4356 parameter = le64dec(req); /* to keep USB endian after xhci_trb_put() */ 4357 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 4358 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 4359 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 4360 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 4361 XHCI_TRB_3_IDT_BIT; 4362 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4363 4364 if (len != 0) { 4365 /* data phase */ 4366 parameter = DMAADDR(dma, 0); 4367 KASSERTMSG(len <= 0x10000, "len %d", len); 4368 status = XHCI_TRB_2_IRQ_SET(0) | 4369 XHCI_TRB_2_TDSZ_SET(0) | 4370 XHCI_TRB_2_BYTES_SET(len); 4371 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 4372 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 4373 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 4374 XHCI_TRB_3_IOC_BIT; 4375 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4376 4377 usb_syncmem(dma, 0, len, 4378 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4379 } 4380 4381 parameter = 0; 4382 status = XHCI_TRB_2_IRQ_SET(0); 4383 /* the status stage has inverted direction */ 4384 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 4385 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 4386 XHCI_TRB_3_IOC_BIT; 4387 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4388 4389 if (!polling) 4390 mutex_enter(&tr->xr_lock); 4391 xhci_ring_put_xfer(sc, tr, xx, i); 4392 if (!polling) 4393 mutex_exit(&tr->xr_lock); 4394 4395 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4396 4397 out: if (xfer->ux_status == USBD_NOT_STARTED) { 4398 usbd_xfer_schedule_timeout(xfer); 4399 xfer->ux_status = USBD_IN_PROGRESS; 4400 } else { 4401 /* 4402 * We must be coming from xhci_pipe_restart -- timeout 4403 * already set up, nothing to do. 4404 */ 4405 } 4406 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 4407 4408 return USBD_IN_PROGRESS; 4409 } 4410 4411 static void 4412 xhci_device_ctrl_done(struct usbd_xfer *xfer) 4413 { 4414 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4415 usb_device_request_t *req = &xfer->ux_request; 4416 int len = UGETW(req->wLength); 4417 int rd = req->bmRequestType & UT_READ; 4418 4419 if (len) 4420 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4421 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4422 } 4423 4424 static void 4425 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 4426 { 4427 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4428 4429 usbd_xfer_abort(xfer); 4430 } 4431 4432 static void 4433 xhci_device_ctrl_close(struct usbd_pipe *pipe) 4434 { 4435 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4436 4437 xhci_close_pipe(pipe); 4438 } 4439 4440 /* ------------------ */ 4441 /* device isochronous */ 4442 4443 static usbd_status 4444 xhci_device_isoc_transfer(struct usbd_xfer *xfer) 4445 { 4446 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4447 4448 return xhci_device_isoc_enter(xfer); 4449 } 4450 4451 static usbd_status 4452 xhci_device_isoc_enter(struct usbd_xfer *xfer) 4453 { 4454 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4455 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4456 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4457 struct xhci_ring * const tr = xs->xs_xr[dci]; 4458 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4459 struct xhci_pipe * const xpipe = (struct xhci_pipe *)xfer->ux_pipe; 4460 uint32_t len = xfer->ux_length; 4461 usb_dma_t * const dma = &xfer->ux_dmabuf; 4462 uint64_t parameter; 4463 uint32_t status; 4464 uint32_t control; 4465 uint32_t mfindex; 4466 uint32_t offs; 4467 int i, ival; 4468 const bool polling = xhci_polling_p(sc); 4469 const uint16_t MPS = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 4470 const uint16_t mps = UE_GET_SIZE(MPS); 4471 const uint8_t maxb = xpipe->xp_maxb; 4472 u_int tdpc, tbc, tlbpc; 4473 4474 XHCIHIST_FUNC(); 4475 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4476 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4477 4478 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4479 4480 if (sc->sc_dying) 4481 return USBD_IOERROR; 4482 4483 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4484 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4485 4486 const bool isread = usbd_xfer_isread(xfer); 4487 if (xfer->ux_length) 4488 usb_syncmem(dma, 0, xfer->ux_length, 4489 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4490 4491 ival = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 4492 if (ival >= 1 && ival <= 16) 4493 ival = 1 << (ival - 1); 4494 else 4495 ival = 1; /* fake something up */ 4496 4497 if (xpipe->xp_isoc_next == -1) { 4498 mfindex = xhci_rt_read_4(sc, XHCI_MFINDEX); 4499 DPRINTF("mfindex %jx", (uintmax_t)mfindex, 0, 0, 0); 4500 mfindex = XHCI_MFINDEX_GET(mfindex + 1); 4501 mfindex /= USB_UFRAMES_PER_FRAME; 4502 mfindex += 7; /* 7 frames is max possible IST */ 4503 xpipe->xp_isoc_next = roundup2(mfindex, ival); 4504 } 4505 4506 offs = 0; 4507 for (i = 0; i < xfer->ux_nframes; i++) { 4508 len = xfer->ux_frlengths[i]; 4509 4510 tdpc = howmany(len, mps); 4511 tbc = howmany(tdpc, maxb) - 1; 4512 tlbpc = tdpc % maxb; 4513 tlbpc = tlbpc ? tlbpc - 1 : maxb - 1; 4514 4515 KASSERTMSG(len <= 0x10000, "len %d", len); 4516 parameter = DMAADDR(dma, offs); 4517 status = XHCI_TRB_2_IRQ_SET(0) | 4518 XHCI_TRB_2_TDSZ_SET(0) | 4519 XHCI_TRB_2_BYTES_SET(len); 4520 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 4521 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 4522 XHCI_TRB_3_TBC_SET(tbc) | 4523 XHCI_TRB_3_TLBPC_SET(tlbpc) | 4524 XHCI_TRB_3_IOC_BIT; 4525 if (XHCI_HCC_CFC(sc->sc_hcc)) { 4526 control |= XHCI_TRB_3_FRID_SET(xpipe->xp_isoc_next); 4527 #if 0 4528 } else if (xpipe->xp_isoc_next == -1) { 4529 control |= XHCI_TRB_3_FRID_SET(xpipe->xp_isoc_next); 4530 #endif 4531 } else { 4532 control |= XHCI_TRB_3_ISO_SIA_BIT; 4533 } 4534 #if 0 4535 if (i != xfer->ux_nframes - 1) 4536 control |= XHCI_TRB_3_BEI_BIT; 4537 #endif 4538 xhci_xfer_put_trb(xx, i, parameter, status, control); 4539 4540 xpipe->xp_isoc_next += ival; 4541 offs += len; 4542 } 4543 4544 xx->xx_isoc_done = 0; 4545 4546 if (!polling) 4547 mutex_enter(&tr->xr_lock); 4548 xhci_ring_put_xfer(sc, tr, xx, i); 4549 if (!polling) 4550 mutex_exit(&tr->xr_lock); 4551 4552 xfer->ux_status = USBD_IN_PROGRESS; 4553 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4554 usbd_xfer_schedule_timeout(xfer); 4555 4556 return USBD_IN_PROGRESS; 4557 } 4558 4559 static void 4560 xhci_device_isoc_abort(struct usbd_xfer *xfer) 4561 { 4562 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4563 4564 usbd_xfer_abort(xfer); 4565 } 4566 4567 static void 4568 xhci_device_isoc_close(struct usbd_pipe *pipe) 4569 { 4570 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4571 4572 xhci_close_pipe(pipe); 4573 } 4574 4575 static void 4576 xhci_device_isoc_done(struct usbd_xfer *xfer) 4577 { 4578 #ifdef USB_DEBUG 4579 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4580 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4581 #endif 4582 const bool isread = usbd_xfer_isread(xfer); 4583 4584 XHCIHIST_FUNC(); 4585 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4586 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4587 4588 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4589 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4590 } 4591 4592 /* ----------- */ 4593 /* device bulk */ 4594 4595 static usbd_status 4596 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 4597 { 4598 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4599 4600 /* Pipe isn't running, so start it first. */ 4601 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4602 } 4603 4604 static usbd_status 4605 xhci_device_bulk_start(struct usbd_xfer *xfer) 4606 { 4607 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4608 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4609 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4610 struct xhci_ring * const tr = xs->xs_xr[dci]; 4611 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4612 const uint32_t len = xfer->ux_length; 4613 usb_dma_t * const dma = &xfer->ux_dmabuf; 4614 uint64_t parameter; 4615 uint32_t status; 4616 uint32_t control; 4617 u_int i = 0; 4618 const bool polling = xhci_polling_p(sc); 4619 4620 XHCIHIST_FUNC(); 4621 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4622 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4623 4624 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4625 4626 if (sc->sc_dying) 4627 return USBD_IOERROR; 4628 4629 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4630 4631 if (tr->is_halted) 4632 goto out; 4633 4634 parameter = DMAADDR(dma, 0); 4635 const bool isread = usbd_xfer_isread(xfer); 4636 if (len) 4637 usb_syncmem(dma, 0, len, 4638 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4639 4640 /* 4641 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 4642 * If the user supplied buffer crosses such a boundary then 2 4643 * (or more) TRB should be used. 4644 * If multiple TRB are used the td_size field must be set correctly. 4645 * For v1.0 devices (like ivy bridge) this is the number of usb data 4646 * blocks needed to complete the transfer. 4647 * Setting it to 1 in the last TRB causes an extra zero-length 4648 * data block be sent. 4649 * The earlier documentation differs, I don't know how it behaves. 4650 */ 4651 KASSERTMSG(len <= 0x10000, "len %d", len); 4652 status = XHCI_TRB_2_IRQ_SET(0) | 4653 XHCI_TRB_2_TDSZ_SET(0) | 4654 XHCI_TRB_2_BYTES_SET(len); 4655 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4656 (isread ? XHCI_TRB_3_ISP_BIT : 0) | 4657 XHCI_TRB_3_IOC_BIT; 4658 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4659 4660 if (!polling) 4661 mutex_enter(&tr->xr_lock); 4662 xhci_ring_put_xfer(sc, tr, xx, i); 4663 if (!polling) 4664 mutex_exit(&tr->xr_lock); 4665 4666 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4667 4668 out: if (xfer->ux_status == USBD_NOT_STARTED) { 4669 xfer->ux_status = USBD_IN_PROGRESS; 4670 usbd_xfer_schedule_timeout(xfer); 4671 } else { 4672 /* 4673 * We must be coming from xhci_pipe_restart -- timeout 4674 * already set up, nothing to do. 4675 */ 4676 } 4677 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 4678 4679 return USBD_IN_PROGRESS; 4680 } 4681 4682 static void 4683 xhci_device_bulk_done(struct usbd_xfer *xfer) 4684 { 4685 #ifdef USB_DEBUG 4686 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4687 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4688 #endif 4689 const bool isread = usbd_xfer_isread(xfer); 4690 4691 XHCIHIST_FUNC(); 4692 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4693 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4694 4695 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4696 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4697 } 4698 4699 static void 4700 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4701 { 4702 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4703 4704 usbd_xfer_abort(xfer); 4705 } 4706 4707 static void 4708 xhci_device_bulk_close(struct usbd_pipe *pipe) 4709 { 4710 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4711 4712 xhci_close_pipe(pipe); 4713 } 4714 4715 /* ---------------- */ 4716 /* device interrupt */ 4717 4718 static usbd_status 4719 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4720 { 4721 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4722 4723 /* Pipe isn't running, so start it first. */ 4724 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4725 } 4726 4727 static usbd_status 4728 xhci_device_intr_start(struct usbd_xfer *xfer) 4729 { 4730 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4731 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4732 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4733 struct xhci_ring * const tr = xs->xs_xr[dci]; 4734 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4735 const uint32_t len = xfer->ux_length; 4736 const bool polling = xhci_polling_p(sc); 4737 usb_dma_t * const dma = &xfer->ux_dmabuf; 4738 uint64_t parameter; 4739 uint32_t status; 4740 uint32_t control; 4741 u_int i = 0; 4742 4743 XHCIHIST_FUNC(); 4744 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4745 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4746 4747 KASSERT(polling || mutex_owned(&sc->sc_lock)); 4748 4749 if (sc->sc_dying) 4750 return USBD_IOERROR; 4751 4752 if (tr->is_halted) 4753 goto out; 4754 4755 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4756 4757 const bool isread = usbd_xfer_isread(xfer); 4758 if (len) 4759 usb_syncmem(dma, 0, len, 4760 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4761 4762 parameter = DMAADDR(dma, 0); 4763 KASSERTMSG(len <= 0x10000, "len %d", len); 4764 status = XHCI_TRB_2_IRQ_SET(0) | 4765 XHCI_TRB_2_TDSZ_SET(0) | 4766 XHCI_TRB_2_BYTES_SET(len); 4767 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4768 (isread ? XHCI_TRB_3_ISP_BIT : 0) | XHCI_TRB_3_IOC_BIT; 4769 xhci_xfer_put_trb(xx, i++, parameter, status, control); 4770 4771 if (!polling) 4772 mutex_enter(&tr->xr_lock); 4773 xhci_ring_put_xfer(sc, tr, xx, i); 4774 if (!polling) 4775 mutex_exit(&tr->xr_lock); 4776 4777 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4778 4779 out: if (xfer->ux_status == USBD_NOT_STARTED) { 4780 xfer->ux_status = USBD_IN_PROGRESS; 4781 usbd_xfer_schedule_timeout(xfer); 4782 } else { 4783 /* 4784 * We must be coming from xhci_pipe_restart -- timeout 4785 * already set up, nothing to do. 4786 */ 4787 } 4788 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 4789 4790 return USBD_IN_PROGRESS; 4791 } 4792 4793 static void 4794 xhci_device_intr_done(struct usbd_xfer *xfer) 4795 { 4796 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4797 #ifdef USB_DEBUG 4798 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4799 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4800 #endif 4801 const bool isread = usbd_xfer_isread(xfer); 4802 4803 XHCIHIST_FUNC(); 4804 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju", 4805 (uintptr_t)xfer, xs->xs_idx, dci, 0); 4806 4807 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4808 4809 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4810 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4811 } 4812 4813 static void 4814 xhci_device_intr_abort(struct usbd_xfer *xfer) 4815 { 4816 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4817 4818 XHCIHIST_FUNC(); 4819 XHCIHIST_CALLARGS("%#jx", (uintptr_t)xfer, 0, 0, 0); 4820 4821 KASSERT(mutex_owned(&sc->sc_lock)); 4822 usbd_xfer_abort(xfer); 4823 } 4824 4825 static void 4826 xhci_device_intr_close(struct usbd_pipe *pipe) 4827 { 4828 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4829 4830 XHCIHIST_FUNC(); 4831 XHCIHIST_CALLARGS("%#jx", (uintptr_t)pipe, 0, 0, 0); 4832 4833 xhci_close_pipe(pipe); 4834 } 4835
Indexes created Wed Oct 01 18:09:54 GMT 2025