xhci.c revision 1.20
1 /* $NetBSD: xhci.c,v 1.20 2014/07/26 00:17:57 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.20 2014/07/26 00:17:57 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/kmem.h> 36 #include <sys/malloc.h> 37 #include <sys/device.h> 38 #include <sys/select.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 #include <sys/cpu.h> 45 46 #include <machine/endian.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 #include <dev/usb/usb_quirks.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 #include <dev/usb/usbroothub_subr.h> 57 58 #ifdef XHCI_DEBUG 59 int xhcidebug = 0; 60 #define DPRINTF(x) do { if (xhcidebug) printf x; } while(0) 61 #define DPRINTFN(n,x) do { if (xhcidebug>(n)) printf x; } while (0) 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #define XHCI_DCI_SLOT 0 68 #define XHCI_DCI_EP_CONTROL 1 69 70 #define XHCI_ICI_INPUT_CONTROL 0 71 72 struct xhci_pipe { 73 struct usbd_pipe xp_pipe; 74 }; 75 76 #define XHCI_INTR_ENDPT 1 77 #define XHCI_COMMAND_RING_TRBS 256 78 #define XHCI_EVENT_RING_TRBS 256 79 #define XHCI_EVENT_RING_SEGMENTS 1 80 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 81 82 static usbd_status xhci_open(usbd_pipe_handle); 83 static int xhci_intr1(struct xhci_softc * const); 84 static void xhci_softintr(void *); 85 static void xhci_poll(struct usbd_bus *); 86 static usbd_status xhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 87 static void xhci_freem(struct usbd_bus *, usb_dma_t *); 88 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 89 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 90 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 91 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 92 struct usbd_port *); 93 94 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 95 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 96 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 97 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 98 99 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 100 101 static usbd_status xhci_do_command(struct xhci_softc * const, 102 struct xhci_trb * const, int); 103 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 104 int, int, int, int); 105 static usbd_status xhci_enable_slot(struct xhci_softc * const, 106 uint8_t * const); 107 static usbd_status xhci_address_device(struct xhci_softc * const, 108 uint64_t, uint8_t, bool); 109 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 110 struct xhci_slot * const, u_int); 111 static usbd_status xhci_ring_init(struct xhci_softc * const, 112 struct xhci_ring * const, size_t, size_t); 113 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 114 115 static void xhci_noop(usbd_pipe_handle); 116 117 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 118 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 119 static void xhci_root_ctrl_abort(usbd_xfer_handle); 120 static void xhci_root_ctrl_close(usbd_pipe_handle); 121 static void xhci_root_ctrl_done(usbd_xfer_handle); 122 123 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 124 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 125 static void xhci_root_intr_abort(usbd_xfer_handle); 126 static void xhci_root_intr_close(usbd_pipe_handle); 127 static void xhci_root_intr_done(usbd_xfer_handle); 128 129 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 130 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 131 static void xhci_device_ctrl_abort(usbd_xfer_handle); 132 static void xhci_device_ctrl_close(usbd_pipe_handle); 133 static void xhci_device_ctrl_done(usbd_xfer_handle); 134 135 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 136 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 137 static void xhci_device_intr_abort(usbd_xfer_handle); 138 static void xhci_device_intr_close(usbd_pipe_handle); 139 static void xhci_device_intr_done(usbd_xfer_handle); 140 141 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 142 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 143 static void xhci_device_bulk_abort(usbd_xfer_handle); 144 static void xhci_device_bulk_close(usbd_pipe_handle); 145 static void xhci_device_bulk_done(usbd_xfer_handle); 146 147 static void xhci_timeout(void *); 148 static void xhci_timeout_task(void *); 149 150 static const struct usbd_bus_methods xhci_bus_methods = { 151 .open_pipe = xhci_open, 152 .soft_intr = xhci_softintr, 153 .do_poll = xhci_poll, 154 .allocm = xhci_allocm, 155 .freem = xhci_freem, 156 .allocx = xhci_allocx, 157 .freex = xhci_freex, 158 .get_lock = xhci_get_lock, 159 .new_device = xhci_new_device, 160 }; 161 162 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 163 .transfer = xhci_root_ctrl_transfer, 164 .start = xhci_root_ctrl_start, 165 .abort = xhci_root_ctrl_abort, 166 .close = xhci_root_ctrl_close, 167 .cleartoggle = xhci_noop, 168 .done = xhci_root_ctrl_done, 169 }; 170 171 static const struct usbd_pipe_methods xhci_root_intr_methods = { 172 .transfer = xhci_root_intr_transfer, 173 .start = xhci_root_intr_start, 174 .abort = xhci_root_intr_abort, 175 .close = xhci_root_intr_close, 176 .cleartoggle = xhci_noop, 177 .done = xhci_root_intr_done, 178 }; 179 180 181 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 182 .transfer = xhci_device_ctrl_transfer, 183 .start = xhci_device_ctrl_start, 184 .abort = xhci_device_ctrl_abort, 185 .close = xhci_device_ctrl_close, 186 .cleartoggle = xhci_noop, 187 .done = xhci_device_ctrl_done, 188 }; 189 190 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 191 .cleartoggle = xhci_noop, 192 }; 193 194 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 195 .transfer = xhci_device_bulk_transfer, 196 .start = xhci_device_bulk_start, 197 .abort = xhci_device_bulk_abort, 198 .close = xhci_device_bulk_close, 199 .cleartoggle = xhci_noop, 200 .done = xhci_device_bulk_done, 201 }; 202 203 static const struct usbd_pipe_methods xhci_device_intr_methods = { 204 .transfer = xhci_device_intr_transfer, 205 .start = xhci_device_intr_start, 206 .abort = xhci_device_intr_abort, 207 .close = xhci_device_intr_close, 208 .cleartoggle = xhci_noop, 209 .done = xhci_device_intr_done, 210 }; 211 212 static inline uint32_t 213 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 214 { 215 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 216 } 217 218 #if 0 /* unused */ 219 static inline void 220 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 221 uint32_t value) 222 { 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 224 } 225 #endif /* unused */ 226 227 static inline uint32_t 228 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 229 { 230 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 231 } 232 233 static inline uint32_t 234 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 235 { 236 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 237 } 238 239 static inline void 240 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 241 uint32_t value) 242 { 243 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 244 } 245 246 #if 0 /* unused */ 247 static inline uint64_t 248 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 249 { 250 uint64_t value; 251 252 if (sc->sc_ac64) { 253 #ifdef XHCI_USE_BUS_SPACE_8 254 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 255 #else 256 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 257 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 258 offset + 4) << 32; 259 #endif 260 } else { 261 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 262 } 263 264 return value; 265 } 266 #endif /* unused */ 267 268 static inline void 269 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 270 uint64_t value) 271 { 272 if (sc->sc_ac64) { 273 #ifdef XHCI_USE_BUS_SPACE_8 274 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 275 #else 276 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 277 (value >> 0) & 0xffffffff); 278 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 279 (value >> 32) & 0xffffffff); 280 #endif 281 } else { 282 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 283 } 284 } 285 286 static inline uint32_t 287 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 288 { 289 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 290 } 291 292 static inline void 293 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 294 uint32_t value) 295 { 296 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 297 } 298 299 #if 0 /* unused */ 300 static inline uint64_t 301 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 302 { 303 uint64_t value; 304 305 if (sc->sc_ac64) { 306 #ifdef XHCI_USE_BUS_SPACE_8 307 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 308 #else 309 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 310 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 311 offset + 4) << 32; 312 #endif 313 } else { 314 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 315 } 316 317 return value; 318 } 319 #endif /* unused */ 320 321 static inline void 322 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 336 } 337 } 338 339 #if 0 /* unused */ 340 static inline uint32_t 341 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 342 { 343 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 344 } 345 #endif /* unused */ 346 347 static inline void 348 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 349 uint32_t value) 350 { 351 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 352 } 353 354 /* --- */ 355 356 static inline uint8_t 357 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 358 { 359 u_int eptype; 360 361 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 362 case UE_CONTROL: 363 eptype = 0x0; 364 break; 365 case UE_ISOCHRONOUS: 366 eptype = 0x1; 367 break; 368 case UE_BULK: 369 eptype = 0x2; 370 break; 371 case UE_INTERRUPT: 372 eptype = 0x3; 373 break; 374 } 375 376 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 377 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 378 return eptype | 0x4; 379 else 380 return eptype; 381 } 382 383 static u_int 384 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 385 { 386 /* xHCI 1.0 section 4.5.1 */ 387 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 388 u_int in = 0; 389 390 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 391 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 392 in = 1; 393 394 return epaddr * 2 + in; 395 } 396 397 static inline u_int 398 xhci_dci_to_ici(const u_int i) 399 { 400 return i + 1; 401 } 402 403 static inline void * 404 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 405 const u_int dci) 406 { 407 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 408 } 409 410 #if 0 /* unused */ 411 static inline bus_addr_t 412 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 413 const u_int dci) 414 { 415 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 416 } 417 #endif /* unused */ 418 419 static inline void * 420 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 421 const u_int ici) 422 { 423 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 424 } 425 426 static inline bus_addr_t 427 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 428 const u_int ici) 429 { 430 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 431 } 432 433 static inline struct xhci_trb * 434 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 435 { 436 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 437 } 438 439 static inline bus_addr_t 440 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 441 { 442 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 443 } 444 445 static inline void 446 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 447 uint32_t control) 448 { 449 trb->trb_0 = parameter; 450 trb->trb_2 = status; 451 trb->trb_3 = control; 452 } 453 454 /* --- */ 455 456 void 457 xhci_childdet(device_t self, device_t child) 458 { 459 struct xhci_softc * const sc = device_private(self); 460 461 KASSERT(sc->sc_child == child); 462 if (child == sc->sc_child) 463 sc->sc_child = NULL; 464 } 465 466 int 467 xhci_detach(struct xhci_softc *sc, int flags) 468 { 469 int rv = 0; 470 471 if (sc->sc_child != NULL) 472 rv = config_detach(sc->sc_child, flags); 473 474 if (rv != 0) 475 return (rv); 476 477 /* XXX unconfigure/free slots */ 478 479 /* verify: */ 480 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 481 xhci_op_write_4(sc, XHCI_USBCMD, 0); 482 /* do we need to wait for stop? */ 483 484 xhci_op_write_8(sc, XHCI_CRCR, 0); 485 xhci_ring_free(sc, &sc->sc_cr); 486 cv_destroy(&sc->sc_command_cv); 487 488 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 489 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 490 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 491 xhci_ring_free(sc, &sc->sc_er); 492 493 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 494 495 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 496 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 497 498 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 499 500 mutex_destroy(&sc->sc_lock); 501 mutex_destroy(&sc->sc_intr_lock); 502 503 pool_cache_destroy(sc->sc_xferpool); 504 505 return rv; 506 } 507 508 int 509 xhci_activate(device_t self, enum devact act) 510 { 511 struct xhci_softc * const sc = device_private(self); 512 513 switch (act) { 514 case DVACT_DEACTIVATE: 515 sc->sc_dying = true; 516 return 0; 517 default: 518 return EOPNOTSUPP; 519 } 520 } 521 522 bool 523 xhci_suspend(device_t dv, const pmf_qual_t *qual) 524 { 525 return false; 526 } 527 528 bool 529 xhci_resume(device_t dv, const pmf_qual_t *qual) 530 { 531 return false; 532 } 533 534 bool 535 xhci_shutdown(device_t self, int flags) 536 { 537 return false; 538 } 539 540 541 static void 542 hexdump(const char *msg, const void *base, size_t len) 543 { 544 #if 0 545 size_t cnt; 546 const uint32_t *p; 547 extern paddr_t vtophys(vaddr_t); 548 549 p = base; 550 cnt = 0; 551 552 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 553 (void *)vtophys((vaddr_t)base)); 554 555 while (cnt < len) { 556 if (cnt % 16 == 0) 557 printf("%p: ", p); 558 else if (cnt % 8 == 0) 559 printf(" |"); 560 printf(" %08x", *p++); 561 cnt += 4; 562 if (cnt % 16 == 0) 563 printf("\n"); 564 } 565 #endif 566 } 567 568 569 int 570 xhci_init(struct xhci_softc *sc) 571 { 572 bus_size_t bsz; 573 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 574 uint32_t ecp, ecr; 575 uint32_t usbcmd, usbsts, pagesize, config; 576 int i; 577 uint16_t hciversion; 578 uint8_t caplength; 579 580 DPRINTF(("%s\n", __func__)); 581 582 /* XXX Low/Full/High speeds for now */ 583 sc->sc_bus.usbrev = USBREV_2_0; 584 585 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 586 caplength = XHCI_CAP_CAPLENGTH(cap); 587 hciversion = XHCI_CAP_HCIVERSION(cap); 588 589 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 590 aprint_normal_dev(sc->sc_dev, 591 "xHCI version %x.%x not known to be supported\n", 592 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 593 } else { 594 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 595 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 596 } 597 598 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 599 &sc->sc_cbh) != 0) { 600 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 601 return ENOMEM; 602 } 603 604 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 605 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 606 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 607 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 608 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 609 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 610 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 611 612 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 613 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 614 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 615 sc->sc_ctxsz); 616 617 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 618 ecp = XHCI_HCC_XECP(hcc) * 4; 619 while (ecp != 0) { 620 ecr = xhci_read_4(sc, ecp); 621 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 622 switch (XHCI_XECP_ID(ecr)) { 623 case XHCI_ID_PROTOCOLS: { 624 uint32_t w0, w4, w8; 625 uint16_t w2; 626 w0 = xhci_read_4(sc, ecp + 0); 627 w2 = (w0 >> 16) & 0xffff; 628 w4 = xhci_read_4(sc, ecp + 4); 629 w8 = xhci_read_4(sc, ecp + 8); 630 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 631 w0, w4, w8); 632 if (w4 == 0x20425355 && w2 == 0x0300) { 633 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 634 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 635 } 636 if (w4 == 0x20425355 && w2 == 0x0200) { 637 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 638 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 639 } 640 break; 641 } 642 default: 643 break; 644 } 645 ecr = xhci_read_4(sc, ecp); 646 if (XHCI_XECP_NEXT(ecr) == 0) { 647 ecp = 0; 648 } else { 649 ecp += XHCI_XECP_NEXT(ecr) * 4; 650 } 651 } 652 653 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 654 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 655 &sc->sc_obh) != 0) { 656 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 657 return ENOMEM; 658 } 659 660 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 661 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 662 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 663 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 664 return ENOMEM; 665 } 666 667 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 668 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 669 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 670 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 671 return ENOMEM; 672 } 673 674 for (i = 0; i < 100; i++) { 675 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 676 if ((usbsts & XHCI_STS_CNR) == 0) 677 break; 678 usb_delay_ms(&sc->sc_bus, 1); 679 } 680 if (i >= 100) 681 return EIO; 682 683 usbcmd = 0; 684 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 685 usb_delay_ms(&sc->sc_bus, 1); 686 687 usbcmd = XHCI_CMD_HCRST; 688 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 689 for (i = 0; i < 100; i++) { 690 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 691 if ((usbcmd & XHCI_CMD_HCRST) == 0) 692 break; 693 usb_delay_ms(&sc->sc_bus, 1); 694 } 695 if (i >= 100) 696 return EIO; 697 698 for (i = 0; i < 100; i++) { 699 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 700 if ((usbsts & XHCI_STS_CNR) == 0) 701 break; 702 usb_delay_ms(&sc->sc_bus, 1); 703 } 704 if (i >= 100) 705 return EIO; 706 707 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 708 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 709 pagesize = ffs(pagesize); 710 if (pagesize == 0) 711 return EIO; 712 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 713 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 714 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 715 (uint32_t)sc->sc_maxslots); 716 717 usbd_status err; 718 719 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 720 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 721 if (sc->sc_maxspbuf != 0) { 722 err = usb_allocmem(&sc->sc_bus, 723 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 724 &sc->sc_spbufarray_dma); 725 if (err) 726 return err; 727 728 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 729 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 730 for (i = 0; i < sc->sc_maxspbuf; i++) { 731 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 732 /* allocate contexts */ 733 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 734 sc->sc_pgsz, dma); 735 if (err) 736 return err; 737 spbufarray[i] = htole64(DMAADDR(dma, 0)); 738 usb_syncmem(dma, 0, sc->sc_pgsz, 739 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 740 } 741 742 usb_syncmem(&sc->sc_spbufarray_dma, 0, 743 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 744 } 745 746 config = xhci_op_read_4(sc, XHCI_CONFIG); 747 config &= ~0xFF; 748 config |= sc->sc_maxslots & 0xFF; 749 xhci_op_write_4(sc, XHCI_CONFIG, config); 750 751 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 752 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 753 if (err) { 754 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 755 return err; 756 } 757 758 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 759 XHCI_EVENT_RING_SEGMENTS_ALIGN); 760 if (err) { 761 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 762 return err; 763 } 764 765 usb_dma_t *dma; 766 size_t size; 767 size_t align; 768 769 dma = &sc->sc_eventst_dma; 770 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 771 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 772 KASSERT(size <= (512 * 1024)); 773 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 774 err = usb_allocmem(&sc->sc_bus, size, align, dma); 775 776 memset(KERNADDR(dma, 0), 0, size); 777 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 778 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 779 usbd_errstr(err), 780 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 781 KERNADDR(&sc->sc_eventst_dma, 0), 782 sc->sc_eventst_dma.block->size); 783 784 dma = &sc->sc_dcbaa_dma; 785 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 786 KASSERT(size <= 2048); 787 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 788 err = usb_allocmem(&sc->sc_bus, size, align, dma); 789 790 memset(KERNADDR(dma, 0), 0, size); 791 if (sc->sc_maxspbuf != 0) { 792 /* 793 * DCBA entry 0 hold the scratchbuf array pointer. 794 */ 795 *(uint64_t *)KERNADDR(dma, 0) = 796 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 797 } 798 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 799 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 800 usbd_errstr(err), 801 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 802 KERNADDR(&sc->sc_dcbaa_dma, 0), 803 sc->sc_dcbaa_dma.block->size); 804 805 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 806 KM_SLEEP); 807 808 cv_init(&sc->sc_command_cv, "xhcicmd"); 809 810 struct xhci_erste *erst; 811 erst = KERNADDR(&sc->sc_eventst_dma, 0); 812 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 813 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 814 erst[0].erste_3 = htole32(0); 815 usb_syncmem(&sc->sc_eventst_dma, 0, 816 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 817 818 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 819 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 820 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 821 XHCI_ERDP_LO_BUSY); 822 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 823 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 824 sc->sc_cr.xr_cs); 825 826 #if 0 827 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 828 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 829 #endif 830 831 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 832 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 833 834 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 835 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 836 xhci_op_read_4(sc, XHCI_USBCMD)); 837 838 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 839 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 840 cv_init(&sc->sc_softwake_cv, "xhciab"); 841 842 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 843 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 844 845 /* Set up the bus struct. */ 846 sc->sc_bus.methods = &xhci_bus_methods; 847 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 848 849 return USBD_NORMAL_COMPLETION; 850 } 851 852 int 853 xhci_intr(void *v) 854 { 855 struct xhci_softc * const sc = v; 856 857 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 858 return 0; 859 860 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 861 862 /* If we get an interrupt while polling, then just ignore it. */ 863 if (sc->sc_bus.use_polling) { 864 #ifdef DIAGNOSTIC 865 DPRINTFN(16, ("xhci_intr: ignored interrupt while polling\n")); 866 #endif 867 return 0; 868 } 869 870 return xhci_intr1(sc); 871 } 872 873 int 874 xhci_intr1(struct xhci_softc * const sc) 875 { 876 uint32_t usbsts; 877 uint32_t iman; 878 879 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 880 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 881 #if 0 882 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 883 return 0; 884 } 885 #endif 886 xhci_op_write_4(sc, XHCI_USBSTS, 887 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 888 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 889 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 890 891 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 892 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 893 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 894 return 0; 895 } 896 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 897 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 898 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 899 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 900 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 901 902 sc->sc_bus.no_intrs++; 903 usb_schedsoftintr(&sc->sc_bus); 904 905 return 1; 906 } 907 908 static usbd_status 909 xhci_configure_endpoint(usbd_pipe_handle pipe) 910 { 911 struct xhci_softc * const sc = pipe->device->bus->hci_private; 912 struct xhci_slot * const xs = pipe->device->hci_private; 913 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 914 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 915 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 916 struct xhci_trb trb; 917 usbd_status err; 918 uint32_t *cp; 919 920 device_printf(sc->sc_dev, "%s dci %u (0x%x)\n", __func__, dci, 921 pipe->endpoint->edesc->bEndpointAddress); 922 923 /* XXX ensure input context is available? */ 924 925 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 926 927 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 928 cp[0] = htole32(0); 929 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 930 931 /* set up input slot context */ 932 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 933 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 934 cp[1] = htole32(0); 935 cp[2] = htole32(0); 936 cp[3] = htole32(0); 937 938 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 939 if (xfertype == UE_INTERRUPT) { 940 cp[0] = htole32( 941 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 942 ); 943 cp[1] = htole32( 944 XHCI_EPCTX_1_CERR_SET(3) | 945 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 946 XHCI_EPCTX_1_MAXB_SET(0) | 947 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 948 ); 949 cp[4] = htole32( 950 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 951 ); 952 } else { 953 cp[0] = htole32(0); 954 cp[1] = htole32( 955 XHCI_EPCTX_1_CERR_SET(3) | 956 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 957 XHCI_EPCTX_1_MAXB_SET(0) | 958 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 959 ); 960 } 961 *(uint64_t *)(&cp[2]) = htole64( 962 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 963 XHCI_EPCTX_2_DCS_SET(1)); 964 965 /* sync input contexts before they are read from memory */ 966 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 967 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 968 sc->sc_ctxsz * 1); 969 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 970 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 971 972 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 973 trb.trb_2 = 0; 974 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 975 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 976 977 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 978 979 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 980 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 981 sc->sc_ctxsz * 1); 982 983 return err; 984 } 985 986 static usbd_status 987 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 988 { 989 return USBD_NORMAL_COMPLETION; 990 } 991 992 static usbd_status 993 xhci_reset_endpoint(usbd_pipe_handle pipe) 994 { 995 struct xhci_softc * const sc = pipe->device->bus->hci_private; 996 struct xhci_slot * const xs = pipe->device->hci_private; 997 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 998 struct xhci_trb trb; 999 usbd_status err; 1000 1001 device_printf(sc->sc_dev, "%s\n", __func__); 1002 1003 trb.trb_0 = 0; 1004 trb.trb_2 = 0; 1005 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1006 XHCI_TRB_3_EP_SET(dci) | 1007 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1008 1009 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1010 1011 return err; 1012 } 1013 1014 #if 0 1015 static usbd_status 1016 xhci_stop_endpoint(usbd_pipe_handle pipe) 1017 { 1018 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1019 struct xhci_slot * const xs = pipe->device->hci_private; 1020 struct xhci_trb trb; 1021 usbd_status err; 1022 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1023 1024 device_printf(sc->sc_dev, "%s\n", __func__); 1025 1026 trb.trb_0 = 0; 1027 trb.trb_2 = 0; 1028 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1029 XHCI_TRB_3_EP_SET(dci) | 1030 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1031 1032 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1033 1034 return err; 1035 } 1036 #endif 1037 1038 static usbd_status 1039 xhci_set_dequeue(usbd_pipe_handle pipe) 1040 { 1041 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1042 struct xhci_slot * const xs = pipe->device->hci_private; 1043 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1044 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1045 struct xhci_trb trb; 1046 usbd_status err; 1047 1048 device_printf(sc->sc_dev, "%s\n", __func__); 1049 1050 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1051 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1052 BUS_DMASYNC_PREWRITE); 1053 1054 xr->xr_ep = 0; 1055 xr->xr_cs = 1; 1056 1057 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1058 trb.trb_2 = 0; 1059 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1060 XHCI_TRB_3_EP_SET(dci) | 1061 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1062 1063 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1064 1065 return err; 1066 } 1067 1068 static usbd_status 1069 xhci_open(usbd_pipe_handle pipe) 1070 { 1071 usbd_device_handle const dev = pipe->device; 1072 struct xhci_softc * const sc = dev->bus->hci_private; 1073 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 1074 const int8_t addr = dev->address; 1075 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1076 1077 DPRINTF(("%s\n", __func__)); 1078 DPRINTF(("addr %d\n", addr)); 1079 device_printf(sc->sc_dev, "%s addr %d depth %d port %d speed %d\n", 1080 __func__, addr, dev->depth, dev->powersrc->portno, dev->speed); 1081 1082 if (sc->sc_dying) 1083 return USBD_IOERROR; 1084 1085 /* Root Hub */ 1086 if (dev->depth == 0 && dev->powersrc->portno == 0 && 1087 dev->speed != USB_SPEED_SUPER) { 1088 switch (ed->bEndpointAddress) { 1089 case USB_CONTROL_ENDPOINT: 1090 pipe->methods = &xhci_root_ctrl_methods; 1091 break; 1092 case UE_DIR_IN | XHCI_INTR_ENDPT: 1093 pipe->methods = &xhci_root_intr_methods; 1094 break; 1095 default: 1096 pipe->methods = NULL; 1097 DPRINTF(("xhci_open: bad bEndpointAddress 0x%02x\n", 1098 ed->bEndpointAddress)); 1099 return USBD_INVAL; 1100 } 1101 return USBD_NORMAL_COMPLETION; 1102 } 1103 1104 switch (xfertype) { 1105 case UE_CONTROL: 1106 pipe->methods = &xhci_device_ctrl_methods; 1107 break; 1108 case UE_ISOCHRONOUS: 1109 pipe->methods = &xhci_device_isoc_methods; 1110 return USBD_INVAL; 1111 break; 1112 case UE_BULK: 1113 pipe->methods = &xhci_device_bulk_methods; 1114 break; 1115 case UE_INTERRUPT: 1116 pipe->methods = &xhci_device_intr_methods; 1117 break; 1118 default: 1119 return USBD_IOERROR; 1120 break; 1121 } 1122 1123 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1124 xhci_configure_endpoint(pipe); 1125 1126 return USBD_NORMAL_COMPLETION; 1127 } 1128 1129 static void 1130 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1131 { 1132 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1133 uint8_t *p; 1134 1135 device_printf(sc->sc_dev, "port %u status change\n", port); 1136 1137 if (xfer == NULL) 1138 return; 1139 1140 if (!(port >= sc->sc_hs_port_start && 1141 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1142 return; 1143 1144 port -= sc->sc_hs_port_start; 1145 port += 1; 1146 device_printf(sc->sc_dev, "hs port %u status change\n", port); 1147 1148 p = KERNADDR(&xfer->dmabuf, 0); 1149 memset(p, 0, xfer->length); 1150 p[port/NBBY] |= 1 << (port%NBBY); 1151 xfer->actlen = xfer->length; 1152 xfer->status = USBD_NORMAL_COMPLETION; 1153 usb_transfer_complete(xfer); 1154 } 1155 1156 static void 1157 xhci_handle_event(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1158 { 1159 uint64_t trb_0; 1160 uint32_t trb_2, trb_3; 1161 1162 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1163 1164 trb_0 = le64toh(trb->trb_0); 1165 trb_2 = le32toh(trb->trb_2); 1166 trb_3 = le32toh(trb->trb_3); 1167 1168 #if 0 1169 device_printf(sc->sc_dev, 1170 "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", trb, 1171 trb_0, trb_2, trb_3); 1172 #endif 1173 1174 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1175 case XHCI_TRB_EVENT_TRANSFER: { 1176 u_int slot, dci; 1177 struct xhci_slot *xs; 1178 struct xhci_ring *xr; 1179 struct xhci_xfer *xx; 1180 usbd_xfer_handle xfer; 1181 usbd_status err; 1182 1183 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1184 dci = XHCI_TRB_3_EP_GET(trb_3); 1185 1186 xs = &sc->sc_slots[slot]; 1187 xr = &xs->xs_ep[dci].xe_tr; 1188 1189 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1190 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1191 sizeof(struct xhci_trb)]; 1192 } else { 1193 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1194 } 1195 xfer = &xx->xx_xfer; 1196 #if 0 1197 device_printf(sc->sc_dev, "%s xfer %p\n", __func__, xfer); 1198 #endif 1199 1200 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1201 #if 0 1202 device_printf(sc->sc_dev, "transfer event data: " 1203 "0x%016"PRIx64" 0x%08"PRIx32" %02x\n", 1204 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1205 XHCI_TRB_2_ERROR_GET(trb_2)); 1206 #endif 1207 if ((trb_0 & 0x3) == 0x3) { 1208 xfer->actlen = XHCI_TRB_2_REM_GET(trb_2); 1209 } 1210 } 1211 1212 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1213 XHCI_TRB_ERROR_SUCCESS) { 1214 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1215 err = USBD_NORMAL_COMPLETION; 1216 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1217 XHCI_TRB_ERROR_SHORT_PKT) { 1218 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1219 err = USBD_NORMAL_COMPLETION; 1220 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1221 XHCI_TRB_ERROR_STALL) { 1222 err = USBD_STALLED; 1223 xr->is_halted = true; 1224 } else { 1225 err = USBD_IOERROR; 1226 } 1227 xfer->status = err; 1228 1229 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1230 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1231 if ((trb_0 & 0x3) == 0x0) { 1232 usb_transfer_complete(xfer); 1233 } 1234 } else { 1235 usb_transfer_complete(xfer); 1236 } 1237 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1238 1239 } 1240 break; 1241 case XHCI_TRB_EVENT_CMD_COMPLETE: 1242 if (trb_0 == sc->sc_command_addr) { 1243 sc->sc_result_trb.trb_0 = trb_0; 1244 sc->sc_result_trb.trb_2 = trb_2; 1245 sc->sc_result_trb.trb_3 = trb_3; 1246 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1247 XHCI_TRB_ERROR_SUCCESS) { 1248 device_printf(sc->sc_dev, "command completion " 1249 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1250 "0x%08"PRIx32"\n", trb_0, trb_2, trb_3); 1251 } 1252 cv_signal(&sc->sc_command_cv); 1253 } else { 1254 device_printf(sc->sc_dev, "event: %p 0x%016"PRIx64" " 1255 "0x%08"PRIx32" 0x%08"PRIx32"\n", trb, trb_0, 1256 trb_2, trb_3); 1257 } 1258 break; 1259 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1260 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1261 break; 1262 default: 1263 break; 1264 } 1265 } 1266 1267 static void 1268 xhci_softintr(void *v) 1269 { 1270 struct usbd_bus * const bus = v; 1271 struct xhci_softc * const sc = bus->hci_private; 1272 struct xhci_ring * const er = &sc->sc_er; 1273 struct xhci_trb *trb; 1274 int i, j, k; 1275 1276 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1277 1278 i = er->xr_ep; 1279 j = er->xr_cs; 1280 1281 while (1) { 1282 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1283 BUS_DMASYNC_POSTREAD); 1284 trb = &er->xr_trb[i]; 1285 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1286 1287 if (j != k) 1288 break; 1289 1290 xhci_handle_event(sc, trb); 1291 1292 i++; 1293 if (i == XHCI_EVENT_RING_TRBS) { 1294 i = 0; 1295 j ^= 1; 1296 } 1297 } 1298 1299 er->xr_ep = i; 1300 er->xr_cs = j; 1301 1302 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1303 XHCI_ERDP_LO_BUSY); 1304 1305 DPRINTF(("%s: %s ends\n", __func__, device_xname(sc->sc_dev))); 1306 1307 return; 1308 } 1309 1310 static void 1311 xhci_poll(struct usbd_bus *bus) 1312 { 1313 struct xhci_softc * const sc = bus->hci_private; 1314 1315 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1316 1317 xhci_intr1(sc); 1318 1319 return; 1320 } 1321 1322 static usbd_status 1323 xhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1324 { 1325 struct xhci_softc * const sc = bus->hci_private; 1326 usbd_status err; 1327 1328 DPRINTF(("%s\n", __func__)); 1329 1330 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, 0); 1331 #if 0 1332 if (err == USBD_NOMEM) 1333 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1334 #endif 1335 #ifdef XHCI_DEBUG 1336 if (err) 1337 device_printf(sc->sc_dev, "xhci_allocm: usb_allocmem()=%d\n", 1338 err); 1339 #endif 1340 1341 return err; 1342 } 1343 1344 static void 1345 xhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1346 { 1347 struct xhci_softc * const sc = bus->hci_private; 1348 1349 // DPRINTF(("%s\n", __func__)); 1350 1351 #if 0 1352 if (dma->block->flags & USB_DMA_RESERVE) { 1353 usb_reserve_freem(&sc->sc_dma_reserve, dma); 1354 return; 1355 } 1356 #endif 1357 usb_freemem(&sc->sc_bus, dma); 1358 } 1359 1360 static usbd_xfer_handle 1361 xhci_allocx(struct usbd_bus *bus) 1362 { 1363 struct xhci_softc * const sc = bus->hci_private; 1364 usbd_xfer_handle xfer; 1365 1366 // DPRINTF(("%s\n", __func__)); 1367 1368 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1369 if (xfer != NULL) { 1370 memset(xfer, 0, sizeof(struct xhci_xfer)); 1371 #ifdef DIAGNOSTIC 1372 xfer->busy_free = XFER_BUSY; 1373 #endif 1374 } 1375 1376 return xfer; 1377 } 1378 1379 static void 1380 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1381 { 1382 struct xhci_softc * const sc = bus->hci_private; 1383 1384 // DPRINTF(("%s\n", __func__)); 1385 1386 #ifdef DIAGNOSTIC 1387 if (xfer->busy_free != XFER_BUSY) { 1388 device_printf(sc->sc_dev, "xhci_freex: xfer=%p " 1389 "not busy, 0x%08x\n", xfer, xfer->busy_free); 1390 } 1391 xfer->busy_free = XFER_FREE; 1392 #endif 1393 pool_cache_put(sc->sc_xferpool, xfer); 1394 } 1395 1396 static void 1397 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1398 { 1399 struct xhci_softc * const sc = bus->hci_private; 1400 1401 *lock = &sc->sc_lock; 1402 } 1403 1404 extern u_int32_t usb_cookie_no; 1405 1406 static usbd_status 1407 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1408 int speed, int port, struct usbd_port *up) 1409 { 1410 struct xhci_softc * const sc = bus->hci_private; 1411 usbd_device_handle dev; 1412 usbd_status err; 1413 usb_device_descriptor_t *dd; 1414 struct usbd_device *hub; 1415 struct usbd_device *adev; 1416 int rhport = 0; 1417 struct xhci_slot *xs; 1418 uint32_t *cp; 1419 uint8_t slot; 1420 uint8_t addr; 1421 1422 dev = malloc(sizeof *dev, M_USB, M_NOWAIT|M_ZERO); 1423 if (dev == NULL) 1424 return USBD_NOMEM; 1425 1426 dev->bus = bus; 1427 1428 /* Set up default endpoint handle. */ 1429 dev->def_ep.edesc = &dev->def_ep_desc; 1430 1431 /* Set up default endpoint descriptor. */ 1432 dev->def_ep_desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1433 dev->def_ep_desc.bDescriptorType = UDESC_ENDPOINT; 1434 dev->def_ep_desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1435 dev->def_ep_desc.bmAttributes = UE_CONTROL; 1436 /* XXX */ 1437 USETW(dev->def_ep_desc.wMaxPacketSize, 64); 1438 dev->def_ep_desc.bInterval = 0; 1439 1440 /* doesn't matter, just don't let it uninitialized */ 1441 dev->def_ep.datatoggle = 0; 1442 1443 device_printf(sc->sc_dev, "%s up %p portno %d\n", __func__, up, 1444 up->portno); 1445 1446 dev->quirks = &usbd_no_quirk; 1447 dev->address = 0; 1448 dev->ddesc.bMaxPacketSize = 0; 1449 dev->depth = depth; 1450 dev->powersrc = up; 1451 dev->myhub = up->parent; 1452 1453 up->device = dev; 1454 1455 /* Locate root hub port */ 1456 for (adev = dev, hub = dev; 1457 hub != NULL; 1458 adev = hub, hub = hub->myhub) { 1459 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1460 } 1461 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1462 1463 if (hub != NULL) { 1464 for (int p = 0; p < hub->hub->hubdesc.bNbrPorts; p++) { 1465 if (hub->hub->ports[p].device == adev) { 1466 rhport = p; 1467 } 1468 } 1469 } else { 1470 rhport = port; 1471 } 1472 if (speed == USB_SPEED_SUPER) { 1473 rhport += sc->sc_ss_port_start - 1; 1474 } else { 1475 rhport += sc->sc_hs_port_start - 1; 1476 } 1477 device_printf(sc->sc_dev, "%s rhport %d\n", __func__, rhport); 1478 1479 dev->speed = speed; 1480 dev->langid = USBD_NOLANG; 1481 dev->cookie.cookie = ++usb_cookie_no; 1482 1483 /* Establish the default pipe. */ 1484 err = usbd_setup_pipe(dev, 0, &dev->def_ep, USBD_DEFAULT_INTERVAL, 1485 &dev->default_pipe); 1486 if (err) { 1487 usbd_remove_device(dev, up); 1488 return (err); 1489 } 1490 1491 dd = &dev->ddesc; 1492 1493 if ((depth == 0) && (port == 0)) { 1494 KASSERT(bus->devices[dev->address] == NULL); 1495 bus->devices[dev->address] = dev; 1496 err = usbd_get_initial_ddesc(dev, dd); 1497 if (err) 1498 return err; 1499 err = usbd_reload_device_desc(dev); 1500 if (err) 1501 return err; 1502 } else { 1503 err = xhci_enable_slot(sc, &slot); 1504 if (err) 1505 return err; 1506 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1507 if (err) 1508 return err; 1509 xs = &sc->sc_slots[slot]; 1510 dev->hci_private = xs; 1511 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1512 //hexdump("slot context", cp, sc->sc_ctxsz); 1513 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1514 device_printf(sc->sc_dev, "%s device address %u\n", 1515 __func__, addr); 1516 /* XXX ensure we know when the hardware does something 1517 we can't yet cope with */ 1518 KASSERT(addr >= 1 && addr <= 127); 1519 dev->address = addr; 1520 /* XXX dev->address not necessarily unique on bus */ 1521 KASSERT(bus->devices[dev->address] == NULL); 1522 bus->devices[dev->address] = dev; 1523 1524 err = usbd_get_initial_ddesc(dev, dd); 1525 if (err) 1526 return err; 1527 USETW(dev->def_ep_desc.wMaxPacketSize, dd->bMaxPacketSize); 1528 device_printf(sc->sc_dev, "%s bMaxPacketSize %u\n", __func__, 1529 dd->bMaxPacketSize); 1530 xhci_update_ep0_mps(sc, xs, dd->bMaxPacketSize); 1531 err = usbd_reload_device_desc(dev); 1532 if (err) 1533 return err; 1534 1535 usbd_kill_pipe(dev->default_pipe); 1536 err = usbd_setup_pipe(dev, 0, &dev->def_ep, 1537 USBD_DEFAULT_INTERVAL, &dev->default_pipe); 1538 } 1539 1540 DPRINTF(("usbd_new_device: adding unit addr=%d, rev=%02x, class=%d, " 1541 "subclass=%d, protocol=%d, maxpacket=%d, len=%d, noconf=%d, " 1542 "speed=%d\n", dev->address,UGETW(dd->bcdUSB), 1543 dd->bDeviceClass, dd->bDeviceSubClass, dd->bDeviceProtocol, 1544 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1545 dev->speed)); 1546 1547 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1548 1549 if ((depth == 0) && (port == 0)) { 1550 usbd_attach_roothub(parent, dev); 1551 device_printf(sc->sc_dev, "root_hub %p\n", bus->root_hub); 1552 return USBD_NORMAL_COMPLETION; 1553 } 1554 1555 1556 err = usbd_probe_and_attach(parent, dev, port, dev->address); 1557 if (err) { 1558 usbd_remove_device(dev, up); 1559 return (err); 1560 } 1561 1562 return USBD_NORMAL_COMPLETION; 1563 } 1564 1565 static usbd_status 1566 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1567 size_t ntrb, size_t align) 1568 { 1569 usbd_status err; 1570 size_t size = ntrb * XHCI_TRB_SIZE; 1571 1572 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1573 if (err) 1574 return err; 1575 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1576 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1577 xr->xr_trb = xhci_ring_trbv(xr, 0); 1578 xr->xr_ntrb = ntrb; 1579 xr->xr_ep = 0; 1580 xr->xr_cs = 1; 1581 memset(xr->xr_trb, 0, size); 1582 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1583 xr->is_halted = false; 1584 1585 return USBD_NORMAL_COMPLETION; 1586 } 1587 1588 static void 1589 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1590 { 1591 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1592 mutex_destroy(&xr->xr_lock); 1593 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1594 } 1595 1596 static void 1597 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1598 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1599 { 1600 size_t i; 1601 u_int ri; 1602 u_int cs; 1603 uint64_t parameter; 1604 uint32_t status; 1605 uint32_t control; 1606 1607 for (i = 0; i < ntrbs; i++) { 1608 #if 0 1609 device_printf(sc->sc_dev, "%s %p %p %zu " 1610 "%016"PRIx64" %08"PRIx32" %08"PRIx32"\n", __func__, xr, 1611 trbs, i, trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3); 1612 #endif 1613 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1614 XHCI_TRB_TYPE_LINK); 1615 } 1616 1617 #if 0 1618 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1619 xr, xr->xr_ep, xr->xr_cs); 1620 #endif 1621 1622 ri = xr->xr_ep; 1623 cs = xr->xr_cs; 1624 1625 /* 1626 * Although the xhci hardware can do scatter/gather dma from 1627 * arbitrary sized buffers, there is a non-obvious restriction 1628 * that a LINK trb is only allowed at the end of a burst of 1629 * transfers - which might be 16kB. 1630 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 1631 * The simple solution is not to allow a LINK trb in the middle 1632 * of anything - as here. 1633 * XXX: (dsl) There are xhci controllers out there (eg some made by 1634 * ASMedia) that seem to lock up if they process a LINK trb but 1635 * cannot process the linked-to trb yet. 1636 * The code should write the 'cycle' bit on the link trb AFTER 1637 * adding the other trb. 1638 */ 1639 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1640 parameter = xhci_ring_trbp(xr, 0); 1641 status = 0; 1642 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1643 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1644 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1645 htole32(status), htole32(control)); 1646 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1647 BUS_DMASYNC_PREWRITE); 1648 xr->xr_cookies[ri] = NULL; 1649 xr->xr_ep = 0; 1650 xr->xr_cs ^= 1; 1651 ri = xr->xr_ep; 1652 cs = xr->xr_cs; 1653 } 1654 1655 ri++; 1656 1657 /* Write any subsequent TRB first */ 1658 for (i = 1; i < ntrbs; i++) { 1659 parameter = trbs[i].trb_0; 1660 status = trbs[i].trb_2; 1661 control = trbs[i].trb_3; 1662 1663 if (cs) { 1664 control |= XHCI_TRB_3_CYCLE_BIT; 1665 } else { 1666 control &= ~XHCI_TRB_3_CYCLE_BIT; 1667 } 1668 1669 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1670 htole32(status), htole32(control)); 1671 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1672 BUS_DMASYNC_PREWRITE); 1673 xr->xr_cookies[ri] = cookie; 1674 ri++; 1675 } 1676 1677 /* Write the first TRB last */ 1678 i = 0; 1679 { 1680 parameter = trbs[i].trb_0; 1681 status = trbs[i].trb_2; 1682 control = trbs[i].trb_3; 1683 1684 if (xr->xr_cs) { 1685 control |= XHCI_TRB_3_CYCLE_BIT; 1686 } else { 1687 control &= ~XHCI_TRB_3_CYCLE_BIT; 1688 } 1689 1690 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1691 htole32(status), htole32(control)); 1692 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1693 BUS_DMASYNC_PREWRITE); 1694 xr->xr_cookies[xr->xr_ep] = cookie; 1695 } 1696 1697 xr->xr_ep = ri; 1698 xr->xr_cs = cs; 1699 1700 #if 0 1701 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1702 xr, xr->xr_ep, xr->xr_cs); 1703 #endif 1704 } 1705 1706 static usbd_status 1707 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1708 int timeout) 1709 { 1710 struct xhci_ring * const cr = &sc->sc_cr; 1711 usbd_status err; 1712 1713 device_printf(sc->sc_dev, "%s input: " 1714 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1715 trb->trb_0, trb->trb_2, trb->trb_3); 1716 1717 mutex_enter(&sc->sc_lock); 1718 1719 KASSERT(sc->sc_command_addr == 0); 1720 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1721 1722 mutex_enter(&cr->xr_lock); 1723 xhci_ring_put(sc, cr, NULL, trb, 1); 1724 mutex_exit(&cr->xr_lock); 1725 1726 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1727 1728 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1729 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1730 err = USBD_TIMEOUT; 1731 goto timedout; 1732 } 1733 1734 trb->trb_0 = sc->sc_result_trb.trb_0; 1735 trb->trb_2 = sc->sc_result_trb.trb_2; 1736 trb->trb_3 = sc->sc_result_trb.trb_3; 1737 1738 device_printf(sc->sc_dev, "%s output: " 1739 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1740 trb->trb_0, trb->trb_2, trb->trb_3); 1741 1742 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1743 case XHCI_TRB_ERROR_SUCCESS: 1744 err = USBD_NORMAL_COMPLETION; 1745 break; 1746 default: 1747 case 192 ... 223: 1748 err = USBD_IOERROR; 1749 break; 1750 case 224 ... 255: 1751 err = USBD_NORMAL_COMPLETION; 1752 break; 1753 } 1754 1755 timedout: 1756 sc->sc_command_addr = 0; 1757 mutex_exit(&sc->sc_lock); 1758 return err; 1759 } 1760 1761 static usbd_status 1762 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1763 { 1764 struct xhci_trb trb; 1765 usbd_status err; 1766 1767 trb.trb_0 = 0; 1768 trb.trb_2 = 0; 1769 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1770 1771 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1772 if (err != USBD_NORMAL_COMPLETION) { 1773 return err; 1774 } 1775 1776 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1777 1778 return err; 1779 } 1780 1781 static usbd_status 1782 xhci_address_device(struct xhci_softc * const sc, 1783 uint64_t icp, uint8_t slot_id, bool bsr) 1784 { 1785 struct xhci_trb trb; 1786 usbd_status err; 1787 1788 trb.trb_0 = icp; 1789 trb.trb_2 = 0; 1790 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1791 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1792 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1793 1794 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1795 return err; 1796 } 1797 1798 static usbd_status 1799 xhci_update_ep0_mps(struct xhci_softc * const sc, 1800 struct xhci_slot * const xs, u_int mps) 1801 { 1802 struct xhci_trb trb; 1803 usbd_status err; 1804 uint32_t * cp; 1805 1806 device_printf(sc->sc_dev, "%s\n", __func__); 1807 1808 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1809 cp[0] = htole32(0); 1810 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1811 1812 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1813 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1814 1815 /* sync input contexts before they are read from memory */ 1816 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1817 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1818 sc->sc_ctxsz * 4); 1819 1820 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1821 trb.trb_2 = 0; 1822 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1823 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1824 1825 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1826 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1827 return err; 1828 } 1829 1830 static void 1831 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1832 { 1833 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1834 1835 device_printf(sc->sc_dev, "dcbaa %p dc %016"PRIx64" slot %d\n", 1836 &dcbaa[si], dcba, si); 1837 1838 dcbaa[si] = htole64(dcba); 1839 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1840 BUS_DMASYNC_PREWRITE); 1841 } 1842 1843 static usbd_status 1844 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1845 int speed, int port, int rhport) 1846 { 1847 struct xhci_slot *xs; 1848 usbd_status err; 1849 u_int dci; 1850 uint32_t *cp; 1851 uint32_t mps; 1852 uint32_t xspeed; 1853 1854 switch (speed) { 1855 case USB_SPEED_LOW: 1856 xspeed = 2; 1857 mps = USB_MAX_IPACKET; 1858 break; 1859 case USB_SPEED_FULL: 1860 xspeed = 1; 1861 mps = 64; 1862 break; 1863 case USB_SPEED_HIGH: 1864 xspeed = 3; 1865 mps = USB_2_MAX_CTRL_PACKET; 1866 break; 1867 case USB_SPEED_SUPER: 1868 xspeed = 4; 1869 mps = USB_3_MAX_CTRL_PACKET; 1870 break; 1871 default: 1872 device_printf(sc->sc_dev, "%s: impossible speed: %x", 1873 __func__, speed); 1874 return USBD_INVAL; 1875 } 1876 1877 xs = &sc->sc_slots[slot]; 1878 xs->xs_idx = slot; 1879 1880 /* allocate contexts */ 1881 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1882 &xs->xs_dc_dma); 1883 if (err) 1884 return err; 1885 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1886 1887 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1888 &xs->xs_ic_dma); 1889 if (err) 1890 return err; 1891 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1892 1893 for (dci = 0; dci < 32; dci++) { 1894 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1895 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1896 if (dci == XHCI_DCI_SLOT) 1897 continue; 1898 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1899 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1900 if (err) { 1901 device_printf(sc->sc_dev, "ring init failure\n"); 1902 return err; 1903 } 1904 } 1905 1906 /* set up initial input control context */ 1907 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1908 cp[0] = htole32(0); 1909 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1910 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1911 1912 /* set up input slot context */ 1913 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1914 cp[0] = htole32( 1915 XHCI_SCTX_0_CTX_NUM_SET(1) | 1916 XHCI_SCTX_0_SPEED_SET(xspeed) 1917 ); 1918 cp[1] = htole32( 1919 XHCI_SCTX_1_RH_PORT_SET(rhport) 1920 ); 1921 cp[2] = htole32( 1922 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1923 ); 1924 cp[3] = htole32(0); 1925 1926 /* set up input EP0 context */ 1927 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1928 cp[0] = htole32(0); 1929 cp[1] = htole32( 1930 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1931 XHCI_EPCTX_1_EPTYPE_SET(4) | 1932 XHCI_EPCTX_1_CERR_SET(3) 1933 ); 1934 /* can't use xhci_ep_get_dci() yet? */ 1935 *(uint64_t *)(&cp[2]) = htole64( 1936 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1937 XHCI_EPCTX_2_DCS_SET(1)); 1938 cp[4] = htole32( 1939 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1940 ); 1941 1942 /* sync input contexts before they are read from memory */ 1943 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1944 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1945 sc->sc_ctxsz * 3); 1946 1947 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1948 1949 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1950 false); 1951 1952 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1953 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1954 sc->sc_ctxsz * 2); 1955 1956 return err; 1957 } 1958 1959 /* ----- */ 1960 1961 static void 1962 xhci_noop(usbd_pipe_handle pipe) 1963 { 1964 DPRINTF(("%s\n", __func__)); 1965 } 1966 1967 /* root hub descriptors */ 1968 1969 static const usb_device_descriptor_t xhci_devd = { 1970 USB_DEVICE_DESCRIPTOR_SIZE, 1971 UDESC_DEVICE, /* type */ 1972 {0x00, 0x02}, /* USB version */ 1973 UDCLASS_HUB, /* class */ 1974 UDSUBCLASS_HUB, /* subclass */ 1975 UDPROTO_HSHUBSTT, /* protocol */ 1976 64, /* max packet */ 1977 {0},{0},{0x00,0x01}, /* device id */ 1978 1,2,0, /* string indexes */ 1979 1 /* # of configurations */ 1980 }; 1981 1982 static const usb_device_qualifier_t xhci_odevd = { 1983 USB_DEVICE_DESCRIPTOR_SIZE, 1984 UDESC_DEVICE_QUALIFIER, /* type */ 1985 {0x00, 0x02}, /* USB version */ 1986 UDCLASS_HUB, /* class */ 1987 UDSUBCLASS_HUB, /* subclass */ 1988 UDPROTO_FSHUB, /* protocol */ 1989 64, /* max packet */ 1990 1, /* # of configurations */ 1991 0 1992 }; 1993 1994 static const usb_config_descriptor_t xhci_confd = { 1995 USB_CONFIG_DESCRIPTOR_SIZE, 1996 UDESC_CONFIG, 1997 {USB_CONFIG_DESCRIPTOR_SIZE + 1998 USB_INTERFACE_DESCRIPTOR_SIZE + 1999 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2000 1, 2001 1, 2002 0, 2003 UC_ATTR_MBO | UC_SELF_POWERED, 2004 0 /* max power */ 2005 }; 2006 2007 static const usb_interface_descriptor_t xhci_ifcd = { 2008 USB_INTERFACE_DESCRIPTOR_SIZE, 2009 UDESC_INTERFACE, 2010 0, 2011 0, 2012 1, 2013 UICLASS_HUB, 2014 UISUBCLASS_HUB, 2015 UIPROTO_HSHUBSTT, 2016 0 2017 }; 2018 2019 static const usb_endpoint_descriptor_t xhci_endpd = { 2020 USB_ENDPOINT_DESCRIPTOR_SIZE, 2021 UDESC_ENDPOINT, 2022 UE_DIR_IN | XHCI_INTR_ENDPT, 2023 UE_INTERRUPT, 2024 {8, 0}, /* max packet */ 2025 12 2026 }; 2027 2028 static const usb_hub_descriptor_t xhci_hubd = { 2029 USB_HUB_DESCRIPTOR_SIZE, 2030 UDESC_HUB, 2031 0, 2032 {0,0}, 2033 0, 2034 0, 2035 {""}, 2036 {""}, 2037 }; 2038 2039 /* root hub control */ 2040 2041 static usbd_status 2042 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 2043 { 2044 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2045 usbd_status err; 2046 2047 DPRINTF(("%s\n", __func__)); 2048 2049 /* Insert last in queue. */ 2050 mutex_enter(&sc->sc_lock); 2051 err = usb_insert_transfer(xfer); 2052 mutex_exit(&sc->sc_lock); 2053 if (err) 2054 return err; 2055 2056 /* Pipe isn't running, start first */ 2057 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2058 } 2059 2060 static usbd_status 2061 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2062 { 2063 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2064 usb_port_status_t ps; 2065 usb_device_request_t *req; 2066 void *buf = NULL; 2067 usb_hub_descriptor_t hubd; 2068 usbd_status err; 2069 int len, value, index; 2070 int l, totlen = 0; 2071 int port, i; 2072 uint32_t v; 2073 2074 DPRINTF(("%s\n", __func__)); 2075 2076 if (sc->sc_dying) 2077 return USBD_IOERROR; 2078 2079 req = &xfer->request; 2080 2081 value = UGETW(req->wValue); 2082 index = UGETW(req->wIndex); 2083 len = UGETW(req->wLength); 2084 2085 if (len != 0) 2086 buf = KERNADDR(&xfer->dmabuf, 0); 2087 2088 DPRINTF(("root req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2089 req->bRequest, value, index, len)); 2090 2091 #define C(x,y) ((x) | ((y) << 8)) 2092 switch(C(req->bRequest, req->bmRequestType)) { 2093 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2094 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2095 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2096 /* 2097 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2098 * for the integrated root hub. 2099 */ 2100 break; 2101 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2102 if (len > 0) { 2103 *(uint8_t *)buf = sc->sc_conf; 2104 totlen = 1; 2105 } 2106 break; 2107 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2108 DPRINTFN(8,("xhci_root_ctrl_start: wValue=0x%04x\n", value)); 2109 if (len == 0) 2110 break; 2111 switch(value >> 8) { 2112 case UDESC_DEVICE: 2113 if ((value & 0xff) != 0) { 2114 err = USBD_IOERROR; 2115 goto ret; 2116 } 2117 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2118 memcpy(buf, &xhci_devd, min(l, sizeof(xhci_devd))); 2119 break; 2120 case UDESC_DEVICE_QUALIFIER: 2121 if ((value & 0xff) != 0) { 2122 } 2123 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2124 memcpy(buf, &xhci_odevd, min(l, sizeof(xhci_odevd))); 2125 break; 2126 case UDESC_OTHER_SPEED_CONFIGURATION: 2127 case UDESC_CONFIG: 2128 if ((value & 0xff) != 0) { 2129 err = USBD_IOERROR; 2130 goto ret; 2131 } 2132 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2133 memcpy(buf, &xhci_confd, min(l, sizeof(xhci_confd))); 2134 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2135 value >> 8; 2136 buf = (char *)buf + l; 2137 len -= l; 2138 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2139 totlen += l; 2140 memcpy(buf, &xhci_ifcd, min(l, sizeof(xhci_ifcd))); 2141 buf = (char *)buf + l; 2142 len -= l; 2143 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2144 totlen += l; 2145 memcpy(buf, &xhci_endpd, min(l, sizeof(xhci_endpd))); 2146 break; 2147 case UDESC_STRING: 2148 #define sd ((usb_string_descriptor_t *)buf) 2149 switch (value & 0xff) { 2150 case 0: /* Language table */ 2151 totlen = usb_makelangtbl(sd, len); 2152 break; 2153 case 1: /* Vendor */ 2154 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2155 break; 2156 case 2: /* Product */ 2157 totlen = usb_makestrdesc(sd, len, 2158 "xHCI Root Hub"); 2159 break; 2160 } 2161 #undef sd 2162 break; 2163 default: 2164 err = USBD_IOERROR; 2165 goto ret; 2166 } 2167 break; 2168 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2169 if (len > 0) { 2170 *(uint8_t *)buf = 0; 2171 totlen = 1; 2172 } 2173 break; 2174 case C(UR_GET_STATUS, UT_READ_DEVICE): 2175 if (len > 1) { 2176 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2177 totlen = 2; 2178 } 2179 break; 2180 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2181 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2182 if (len > 1) { 2183 USETW(((usb_status_t *)buf)->wStatus, 0); 2184 totlen = 2; 2185 } 2186 break; 2187 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2188 if (value >= USB_MAX_DEVICES) { 2189 err = USBD_IOERROR; 2190 goto ret; 2191 } 2192 //sc->sc_addr = value; 2193 break; 2194 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2195 if (value != 0 && value != 1) { 2196 err = USBD_IOERROR; 2197 goto ret; 2198 } 2199 sc->sc_conf = value; 2200 break; 2201 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2202 break; 2203 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2204 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2205 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2206 err = USBD_IOERROR; 2207 goto ret; 2208 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2209 break; 2210 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2211 break; 2212 /* Hub requests */ 2213 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2214 break; 2215 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2216 DPRINTFN(4, ("xhci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2217 "port=%d feature=%d\n", 2218 index, value)); 2219 if (index < 1 || index > sc->sc_hs_port_count) { 2220 err = USBD_IOERROR; 2221 goto ret; 2222 } 2223 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2224 v = xhci_op_read_4(sc, port); 2225 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2226 v &= ~XHCI_PS_CLEAR; 2227 switch (value) { 2228 case UHF_PORT_ENABLE: 2229 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2230 break; 2231 case UHF_PORT_SUSPEND: 2232 err = USBD_IOERROR; 2233 goto ret; 2234 case UHF_PORT_POWER: 2235 break; 2236 case UHF_PORT_TEST: 2237 case UHF_PORT_INDICATOR: 2238 err = USBD_IOERROR; 2239 goto ret; 2240 case UHF_C_PORT_CONNECTION: 2241 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2242 break; 2243 case UHF_C_PORT_ENABLE: 2244 case UHF_C_PORT_SUSPEND: 2245 case UHF_C_PORT_OVER_CURRENT: 2246 err = USBD_IOERROR; 2247 goto ret; 2248 case UHF_C_PORT_RESET: 2249 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2250 break; 2251 default: 2252 err = USBD_IOERROR; 2253 goto ret; 2254 } 2255 2256 break; 2257 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2258 if (len == 0) 2259 break; 2260 if ((value & 0xff) != 0) { 2261 err = USBD_IOERROR; 2262 goto ret; 2263 } 2264 hubd = xhci_hubd; 2265 hubd.bNbrPorts = sc->sc_hs_port_count; 2266 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2267 hubd.bPwrOn2PwrGood = 200; 2268 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2269 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2270 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2271 l = min(len, hubd.bDescLength); 2272 totlen = l; 2273 memcpy(buf, &hubd, l); 2274 break; 2275 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2276 if (len != 4) { 2277 err = USBD_IOERROR; 2278 goto ret; 2279 } 2280 memset(buf, 0, len); /* ? XXX */ 2281 totlen = len; 2282 break; 2283 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2284 DPRINTFN(8,("xhci_root_ctrl_start: get port status i=%d\n", 2285 index)); 2286 if (index < 1 || index > sc->sc_maxports) { 2287 err = USBD_IOERROR; 2288 goto ret; 2289 } 2290 if (len != 4) { 2291 err = USBD_IOERROR; 2292 goto ret; 2293 } 2294 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2295 index)); 2296 DPRINTF(("%s READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x\n", 2297 __func__, index, sc->sc_hs_port_start - 1 + index, v)); 2298 switch (XHCI_PS_SPEED_GET(v)) { 2299 case 1: 2300 i = UPS_FULL_SPEED; 2301 break; 2302 case 2: 2303 i = UPS_LOW_SPEED; 2304 break; 2305 case 3: 2306 i = UPS_HIGH_SPEED; 2307 break; 2308 default: 2309 i = 0; 2310 break; 2311 } 2312 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2313 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2314 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2315 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2316 if (v & XHCI_PS_PR) i |= UPS_RESET; 2317 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2318 USETW(ps.wPortStatus, i); 2319 i = 0; 2320 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2321 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2322 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2323 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2324 USETW(ps.wPortChange, i); 2325 l = min(len, sizeof ps); 2326 memcpy(buf, &ps, l); 2327 totlen = l; 2328 break; 2329 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2330 err = USBD_IOERROR; 2331 goto ret; 2332 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2333 break; 2334 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2335 if (index < 1 || index > sc->sc_hs_port_count) { 2336 err = USBD_IOERROR; 2337 goto ret; 2338 } 2339 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2340 v = xhci_op_read_4(sc, port); 2341 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2342 v &= ~XHCI_PS_CLEAR; 2343 switch (value) { 2344 case UHF_PORT_ENABLE: 2345 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2346 break; 2347 case UHF_PORT_SUSPEND: 2348 /* XXX suspend */ 2349 break; 2350 case UHF_PORT_RESET: 2351 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2352 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2353 /* Wait for reset to complete. */ 2354 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2355 if (sc->sc_dying) { 2356 err = USBD_IOERROR; 2357 goto ret; 2358 } 2359 v = xhci_op_read_4(sc, port); 2360 if (v & XHCI_PS_PR) { 2361 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2362 usb_delay_ms(&sc->sc_bus, 10); 2363 /* XXX */ 2364 } 2365 break; 2366 case UHF_PORT_POWER: 2367 /* XXX power control */ 2368 break; 2369 /* XXX more */ 2370 case UHF_C_PORT_RESET: 2371 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2372 break; 2373 default: 2374 err = USBD_IOERROR; 2375 goto ret; 2376 } 2377 break; 2378 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2379 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2380 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2381 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2382 break; 2383 default: 2384 err = USBD_IOERROR; 2385 goto ret; 2386 } 2387 xfer->actlen = totlen; 2388 err = USBD_NORMAL_COMPLETION; 2389 ret: 2390 xfer->status = err; 2391 mutex_enter(&sc->sc_lock); 2392 usb_transfer_complete(xfer); 2393 mutex_exit(&sc->sc_lock); 2394 return USBD_IN_PROGRESS; 2395 } 2396 2397 2398 static void 2399 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2400 { 2401 /* Nothing to do, all transfers are synchronous. */ 2402 } 2403 2404 2405 static void 2406 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2407 { 2408 DPRINTF(("%s\n", __func__)); 2409 /* Nothing to do. */ 2410 } 2411 2412 static void 2413 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2414 { 2415 xfer->hcpriv = NULL; 2416 } 2417 2418 /* root hub intrerrupt */ 2419 2420 static usbd_status 2421 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2422 { 2423 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2424 usbd_status err; 2425 2426 /* Insert last in queue. */ 2427 mutex_enter(&sc->sc_lock); 2428 err = usb_insert_transfer(xfer); 2429 mutex_exit(&sc->sc_lock); 2430 if (err) 2431 return err; 2432 2433 /* Pipe isn't running, start first */ 2434 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2435 } 2436 2437 static usbd_status 2438 xhci_root_intr_start(usbd_xfer_handle xfer) 2439 { 2440 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2441 2442 if (sc->sc_dying) 2443 return USBD_IOERROR; 2444 2445 mutex_enter(&sc->sc_lock); 2446 sc->sc_intrxfer = xfer; 2447 mutex_exit(&sc->sc_lock); 2448 2449 return USBD_IN_PROGRESS; 2450 } 2451 2452 static void 2453 xhci_root_intr_abort(usbd_xfer_handle xfer) 2454 { 2455 #ifdef DIAGNOSTIC 2456 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2457 #endif 2458 2459 KASSERT(mutex_owned(&sc->sc_lock)); 2460 if (xfer->pipe->intrxfer == xfer) { 2461 DPRINTF(("%s: remove\n", __func__)); 2462 xfer->pipe->intrxfer = NULL; 2463 } 2464 xfer->status = USBD_CANCELLED; 2465 usb_transfer_complete(xfer); 2466 } 2467 2468 static void 2469 xhci_root_intr_close(usbd_pipe_handle pipe) 2470 { 2471 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2472 2473 KASSERT(mutex_owned(&sc->sc_lock)); 2474 2475 DPRINTF(("%s\n", __func__)); 2476 2477 sc->sc_intrxfer = NULL; 2478 } 2479 2480 static void 2481 xhci_root_intr_done(usbd_xfer_handle xfer) 2482 { 2483 xfer->hcpriv = NULL; 2484 } 2485 2486 /* -------------- */ 2487 /* device control */ 2488 2489 static usbd_status 2490 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2491 { 2492 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2493 usbd_status err; 2494 2495 /* Insert last in queue. */ 2496 mutex_enter(&sc->sc_lock); 2497 err = usb_insert_transfer(xfer); 2498 mutex_exit(&sc->sc_lock); 2499 if (err) 2500 return (err); 2501 2502 /* Pipe isn't running, start first */ 2503 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2504 } 2505 2506 static usbd_status 2507 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2508 { 2509 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2510 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2511 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2512 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2513 struct xhci_xfer * const xx = (void *)xfer; 2514 usb_device_request_t * const req = &xfer->request; 2515 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2516 const uint32_t len = UGETW(req->wLength); 2517 usb_dma_t * const dma = &xfer->dmabuf; 2518 uint64_t parameter; 2519 uint32_t status; 2520 uint32_t control; 2521 u_int i; 2522 2523 DPRINTF(("%s\n", __func__)); 2524 DPRINTF(("req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2525 req->bRequest, UGETW(req->wValue), UGETW(req->wIndex), 2526 UGETW(req->wLength))); 2527 2528 /* XXX */ 2529 if (tr->is_halted) { 2530 xhci_reset_endpoint(xfer->pipe); 2531 tr->is_halted = false; 2532 xhci_set_dequeue(xfer->pipe); 2533 } 2534 2535 /* we rely on the bottom bits for extra info */ 2536 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2537 2538 KASSERT((xfer->rqflags & URQ_REQUEST) != 0); 2539 2540 i = 0; 2541 2542 /* setup phase */ 2543 memcpy(¶meter, req, sizeof(*req)); 2544 parameter = le64toh(parameter); 2545 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2546 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2547 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2548 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2549 XHCI_TRB_3_IDT_BIT; 2550 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2551 2552 if (len == 0) 2553 goto no_data; 2554 2555 /* data phase */ 2556 parameter = DMAADDR(dma, 0); 2557 KASSERT(len <= 0x10000); 2558 status = XHCI_TRB_2_IRQ_SET(0) | 2559 XHCI_TRB_2_TDSZ_SET(1) | 2560 XHCI_TRB_2_BYTES_SET(len); 2561 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2562 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2563 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2564 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2565 2566 parameter = (uintptr_t)xfer | 0x3; 2567 status = XHCI_TRB_2_IRQ_SET(0); 2568 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2569 XHCI_TRB_3_IOC_BIT; 2570 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2571 2572 no_data: 2573 parameter = 0; 2574 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_TDSZ_SET(1); 2575 /* the status stage has inverted direction */ 2576 control = (isread ? 0 : XHCI_TRB_3_DIR_IN) | 2577 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2578 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2579 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2580 2581 parameter = (uintptr_t)xfer | 0x0; 2582 status = XHCI_TRB_2_IRQ_SET(0); 2583 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2584 XHCI_TRB_3_IOC_BIT; 2585 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2586 2587 mutex_enter(&tr->xr_lock); 2588 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2589 mutex_exit(&tr->xr_lock); 2590 2591 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2592 2593 if (xfer->timeout && !sc->sc_bus.use_polling) { 2594 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2595 xhci_timeout, xfer); 2596 } 2597 2598 if (sc->sc_bus.use_polling) { 2599 device_printf(sc->sc_dev, "%s polling\n", __func__); 2600 //xhci_waitintr(sc, xfer); 2601 } 2602 2603 return USBD_IN_PROGRESS; 2604 } 2605 2606 static void 2607 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2608 { 2609 DPRINTF(("%s\n", __func__)); 2610 2611 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2612 2613 } 2614 2615 static void 2616 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2617 { 2618 DPRINTF(("%s\n", __func__)); 2619 } 2620 2621 static void 2622 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2623 { 2624 DPRINTF(("%s\n", __func__)); 2625 } 2626 2627 /* ----------------- */ 2628 /* device isochronus */ 2629 2630 /* ----------- */ 2631 /* device bulk */ 2632 2633 static usbd_status 2634 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2635 { 2636 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2637 usbd_status err; 2638 2639 /* Insert last in queue. */ 2640 mutex_enter(&sc->sc_lock); 2641 err = usb_insert_transfer(xfer); 2642 mutex_exit(&sc->sc_lock); 2643 if (err) 2644 return err; 2645 2646 /* 2647 * Pipe isn't running (otherwise err would be USBD_INPROG), 2648 * so start it first. 2649 */ 2650 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2651 } 2652 2653 static usbd_status 2654 xhci_device_bulk_start(usbd_xfer_handle xfer) 2655 { 2656 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2657 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2658 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2659 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2660 struct xhci_xfer * const xx = (void *)xfer; 2661 const uint32_t len = xfer->length; 2662 usb_dma_t * const dma = &xfer->dmabuf; 2663 uint64_t parameter; 2664 uint32_t status; 2665 uint32_t control; 2666 u_int i = 0; 2667 2668 #if 0 2669 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2670 xs->xs_idx, dci); 2671 #endif 2672 2673 if (sc->sc_dying) 2674 return USBD_IOERROR; 2675 2676 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2677 2678 parameter = DMAADDR(dma, 0); 2679 /* 2680 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 2681 * If the user supplied buffer crosses such a boundary then 2 2682 * (or more) TRB should be used. 2683 * If multiple TRB are used the td_size field must be set correctly. 2684 * For v1.0 devices (like ivy bridge) this is the number of usb data 2685 * blocks needed to complete the transfer. 2686 * Setting it to 1 in the last TRB causes an extra zero-length 2687 * data block be sent. 2688 * The earlier documentation differs, I don't know how it behaves. 2689 */ 2690 KASSERT(len <= 0x10000); 2691 status = XHCI_TRB_2_IRQ_SET(0) | 2692 XHCI_TRB_2_TDSZ_SET(1) | 2693 XHCI_TRB_2_BYTES_SET(len); 2694 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2695 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2696 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2697 2698 mutex_enter(&tr->xr_lock); 2699 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2700 mutex_exit(&tr->xr_lock); 2701 2702 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2703 2704 if (sc->sc_bus.use_polling) { 2705 device_printf(sc->sc_dev, "%s polling\n", __func__); 2706 //xhci_waitintr(sc, xfer); 2707 } 2708 2709 return USBD_IN_PROGRESS; 2710 } 2711 2712 static void 2713 xhci_device_bulk_done(usbd_xfer_handle xfer) 2714 { 2715 //struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2716 //struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2717 //const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2718 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2719 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2720 2721 DPRINTF(("%s\n", __func__)); 2722 2723 #if 0 2724 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2725 xs->xs_idx, dci); 2726 #endif 2727 2728 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2729 2730 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2731 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2732 2733 2734 } 2735 2736 static void 2737 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2738 { 2739 DPRINTF(("%s\n", __func__)); 2740 } 2741 2742 static void 2743 xhci_device_bulk_close(usbd_pipe_handle pipe) 2744 { 2745 DPRINTF(("%s\n", __func__)); 2746 } 2747 2748 /* --------------- */ 2749 /* device intrrupt */ 2750 2751 static usbd_status 2752 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2753 { 2754 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2755 usbd_status err; 2756 2757 /* Insert last in queue. */ 2758 mutex_enter(&sc->sc_lock); 2759 err = usb_insert_transfer(xfer); 2760 mutex_exit(&sc->sc_lock); 2761 if (err) 2762 return err; 2763 2764 /* 2765 * Pipe isn't running (otherwise err would be USBD_INPROG), 2766 * so start it first. 2767 */ 2768 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2769 } 2770 2771 static usbd_status 2772 xhci_device_intr_start(usbd_xfer_handle xfer) 2773 { 2774 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2775 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2776 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2777 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2778 struct xhci_xfer * const xx = (void *)xfer; 2779 const uint32_t len = xfer->length; 2780 usb_dma_t * const dma = &xfer->dmabuf; 2781 uint64_t parameter; 2782 uint32_t status; 2783 uint32_t control; 2784 u_int i = 0; 2785 2786 #if 0 2787 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2788 xs->xs_idx, dci); 2789 #endif 2790 2791 if (sc->sc_dying) 2792 return USBD_IOERROR; 2793 2794 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2795 2796 parameter = DMAADDR(dma, 0); 2797 KASSERT(len <= 0x10000); 2798 status = XHCI_TRB_2_IRQ_SET(0) | 2799 XHCI_TRB_2_TDSZ_SET(1) | 2800 XHCI_TRB_2_BYTES_SET(len); 2801 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2802 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2803 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2804 2805 mutex_enter(&tr->xr_lock); 2806 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2807 mutex_exit(&tr->xr_lock); 2808 2809 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2810 2811 if (sc->sc_bus.use_polling) { 2812 #ifdef XHCI_DEBUG 2813 device_printf(sc->sc_dev, "%s polling\n", __func__); 2814 #endif 2815 //xhci_waitintr(sc, xfer); 2816 } 2817 2818 return USBD_IN_PROGRESS; 2819 } 2820 2821 static void 2822 xhci_device_intr_done(usbd_xfer_handle xfer) 2823 { 2824 struct xhci_softc * const sc __diagused = 2825 xfer->pipe->device->bus->hci_private; 2826 #ifdef XHCI_DEBUG 2827 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2828 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2829 #endif 2830 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2831 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2832 DPRINTF(("%s\n", __func__)); 2833 2834 #ifdef XHCI_DEBUG 2835 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2836 xs->xs_idx, dci); 2837 #endif 2838 2839 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2840 2841 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2842 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2843 2844 #if 0 2845 device_printf(sc->sc_dev, ""); 2846 for (size_t i = 0; i < xfer->length; i++) { 2847 printf(" %02x", ((uint8_t const *)xfer->buffer)[i]); 2848 } 2849 printf("\n"); 2850 #endif 2851 2852 if (xfer->pipe->repeat) { 2853 xfer->status = xhci_device_intr_start(xfer); 2854 } else { 2855 callout_stop(&xfer->timeout_handle); /* XXX */ 2856 } 2857 2858 } 2859 2860 static void 2861 xhci_device_intr_abort(usbd_xfer_handle xfer) 2862 { 2863 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2864 DPRINTF(("%s\n", __func__)); 2865 2866 KASSERT(mutex_owned(&sc->sc_lock)); 2867 device_printf(sc->sc_dev, "%s %p\n", __func__, xfer); 2868 /* XXX */ 2869 if (xfer->pipe->intrxfer == xfer) { 2870 xfer->pipe->intrxfer = NULL; 2871 } 2872 xfer->status = USBD_CANCELLED; 2873 usb_transfer_complete(xfer); 2874 } 2875 2876 static void 2877 xhci_device_intr_close(usbd_pipe_handle pipe) 2878 { 2879 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2880 DPRINTF(("%s\n", __func__)); 2881 device_printf(sc->sc_dev, "%s %p\n", __func__, pipe); 2882 xhci_unconfigure_endpoint(pipe); 2883 } 2884 2885 /* ------------ */ 2886 2887 static void 2888 xhci_timeout(void *addr) 2889 { 2890 struct xhci_xfer * const xx = addr; 2891 usbd_xfer_handle const xfer = &xx->xx_xfer; 2892 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2893 2894 if (sc->sc_dying) { 2895 return; 2896 } 2897 2898 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2899 USB_TASKQ_MPSAFE); 2900 usb_add_task(xx->xx_xfer.pipe->device, &xx->xx_abort_task, 2901 USB_TASKQ_HC); 2902 } 2903 2904 static void 2905 xhci_timeout_task(void *addr) 2906 { 2907 usbd_xfer_handle const xfer = addr; 2908 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2909 2910 mutex_enter(&sc->sc_lock); 2911 #if 0 2912 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2913 #else 2914 xfer->status = USBD_TIMEOUT; 2915 usb_transfer_complete(xfer); 2916 #endif 2917 mutex_exit(&sc->sc_lock); 2918 } 2919
Indexes created Tue Sep 23 02:09:52 GMT 2025