xhci.c revision 1.23.2.2
1 /* $NetBSD: xhci.c,v 1.23.2.2 2014/08/13 21:47:18 riz Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.23.2.2 2014/08/13 21:47:18 riz Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/kmem.h> 36 #include <sys/malloc.h> 37 #include <sys/device.h> 38 #include <sys/select.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 #include <sys/cpu.h> 45 46 #include <machine/endian.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 #include <dev/usb/usb_quirks.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 #include <dev/usb/usbroothub_subr.h> 57 58 #ifdef XHCI_DEBUG 59 int xhcidebug = 0; 60 #define DPRINTF(x) do { if (xhcidebug) printf x; } while(0) 61 #define DPRINTFN(n,x) do { if (xhcidebug>(n)) printf x; } while (0) 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #define XHCI_DCI_SLOT 0 68 #define XHCI_DCI_EP_CONTROL 1 69 70 #define XHCI_ICI_INPUT_CONTROL 0 71 72 struct xhci_pipe { 73 struct usbd_pipe xp_pipe; 74 }; 75 76 #define XHCI_INTR_ENDPT 1 77 #define XHCI_COMMAND_RING_TRBS 256 78 #define XHCI_EVENT_RING_TRBS 256 79 #define XHCI_EVENT_RING_SEGMENTS 1 80 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 81 82 static usbd_status xhci_open(usbd_pipe_handle); 83 static int xhci_intr1(struct xhci_softc * const); 84 static void xhci_softintr(void *); 85 static void xhci_poll(struct usbd_bus *); 86 static usbd_status xhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 87 static void xhci_freem(struct usbd_bus *, usb_dma_t *); 88 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 89 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 90 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 91 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 92 struct usbd_port *); 93 94 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 95 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 96 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 97 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 98 99 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 100 101 static usbd_status xhci_do_command(struct xhci_softc * const, 102 struct xhci_trb * const, int); 103 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 104 int, int, int, int); 105 static usbd_status xhci_enable_slot(struct xhci_softc * const, 106 uint8_t * const); 107 static usbd_status xhci_address_device(struct xhci_softc * const, 108 uint64_t, uint8_t, bool); 109 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 110 struct xhci_slot * const, u_int); 111 static usbd_status xhci_ring_init(struct xhci_softc * const, 112 struct xhci_ring * const, size_t, size_t); 113 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 114 115 static void xhci_noop(usbd_pipe_handle); 116 117 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 118 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 119 static void xhci_root_ctrl_abort(usbd_xfer_handle); 120 static void xhci_root_ctrl_close(usbd_pipe_handle); 121 static void xhci_root_ctrl_done(usbd_xfer_handle); 122 123 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 124 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 125 static void xhci_root_intr_abort(usbd_xfer_handle); 126 static void xhci_root_intr_close(usbd_pipe_handle); 127 static void xhci_root_intr_done(usbd_xfer_handle); 128 129 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 130 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 131 static void xhci_device_ctrl_abort(usbd_xfer_handle); 132 static void xhci_device_ctrl_close(usbd_pipe_handle); 133 static void xhci_device_ctrl_done(usbd_xfer_handle); 134 135 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 136 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 137 static void xhci_device_intr_abort(usbd_xfer_handle); 138 static void xhci_device_intr_close(usbd_pipe_handle); 139 static void xhci_device_intr_done(usbd_xfer_handle); 140 141 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 142 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 143 static void xhci_device_bulk_abort(usbd_xfer_handle); 144 static void xhci_device_bulk_close(usbd_pipe_handle); 145 static void xhci_device_bulk_done(usbd_xfer_handle); 146 147 static void xhci_timeout(void *); 148 static void xhci_timeout_task(void *); 149 150 static const struct usbd_bus_methods xhci_bus_methods = { 151 .open_pipe = xhci_open, 152 .soft_intr = xhci_softintr, 153 .do_poll = xhci_poll, 154 .allocm = xhci_allocm, 155 .freem = xhci_freem, 156 .allocx = xhci_allocx, 157 .freex = xhci_freex, 158 .get_lock = xhci_get_lock, 159 .new_device = xhci_new_device, 160 }; 161 162 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 163 .transfer = xhci_root_ctrl_transfer, 164 .start = xhci_root_ctrl_start, 165 .abort = xhci_root_ctrl_abort, 166 .close = xhci_root_ctrl_close, 167 .cleartoggle = xhci_noop, 168 .done = xhci_root_ctrl_done, 169 }; 170 171 static const struct usbd_pipe_methods xhci_root_intr_methods = { 172 .transfer = xhci_root_intr_transfer, 173 .start = xhci_root_intr_start, 174 .abort = xhci_root_intr_abort, 175 .close = xhci_root_intr_close, 176 .cleartoggle = xhci_noop, 177 .done = xhci_root_intr_done, 178 }; 179 180 181 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 182 .transfer = xhci_device_ctrl_transfer, 183 .start = xhci_device_ctrl_start, 184 .abort = xhci_device_ctrl_abort, 185 .close = xhci_device_ctrl_close, 186 .cleartoggle = xhci_noop, 187 .done = xhci_device_ctrl_done, 188 }; 189 190 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 191 .cleartoggle = xhci_noop, 192 }; 193 194 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 195 .transfer = xhci_device_bulk_transfer, 196 .start = xhci_device_bulk_start, 197 .abort = xhci_device_bulk_abort, 198 .close = xhci_device_bulk_close, 199 .cleartoggle = xhci_noop, 200 .done = xhci_device_bulk_done, 201 }; 202 203 static const struct usbd_pipe_methods xhci_device_intr_methods = { 204 .transfer = xhci_device_intr_transfer, 205 .start = xhci_device_intr_start, 206 .abort = xhci_device_intr_abort, 207 .close = xhci_device_intr_close, 208 .cleartoggle = xhci_noop, 209 .done = xhci_device_intr_done, 210 }; 211 212 static inline uint32_t 213 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 214 { 215 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 216 } 217 218 #if 0 /* unused */ 219 static inline void 220 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 221 uint32_t value) 222 { 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 224 } 225 #endif /* unused */ 226 227 static inline uint32_t 228 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 229 { 230 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 231 } 232 233 static inline uint32_t 234 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 235 { 236 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 237 } 238 239 static inline void 240 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 241 uint32_t value) 242 { 243 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 244 } 245 246 #if 0 /* unused */ 247 static inline uint64_t 248 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 249 { 250 uint64_t value; 251 252 if (sc->sc_ac64) { 253 #ifdef XHCI_USE_BUS_SPACE_8 254 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 255 #else 256 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 257 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 258 offset + 4) << 32; 259 #endif 260 } else { 261 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 262 } 263 264 return value; 265 } 266 #endif /* unused */ 267 268 static inline void 269 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 270 uint64_t value) 271 { 272 if (sc->sc_ac64) { 273 #ifdef XHCI_USE_BUS_SPACE_8 274 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 275 #else 276 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 277 (value >> 0) & 0xffffffff); 278 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 279 (value >> 32) & 0xffffffff); 280 #endif 281 } else { 282 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 283 } 284 } 285 286 static inline uint32_t 287 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 288 { 289 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 290 } 291 292 static inline void 293 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 294 uint32_t value) 295 { 296 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 297 } 298 299 #if 0 /* unused */ 300 static inline uint64_t 301 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 302 { 303 uint64_t value; 304 305 if (sc->sc_ac64) { 306 #ifdef XHCI_USE_BUS_SPACE_8 307 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 308 #else 309 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 310 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 311 offset + 4) << 32; 312 #endif 313 } else { 314 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 315 } 316 317 return value; 318 } 319 #endif /* unused */ 320 321 static inline void 322 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 336 } 337 } 338 339 #if 0 /* unused */ 340 static inline uint32_t 341 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 342 { 343 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 344 } 345 #endif /* unused */ 346 347 static inline void 348 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 349 uint32_t value) 350 { 351 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 352 } 353 354 /* --- */ 355 356 static inline uint8_t 357 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 358 { 359 u_int eptype; 360 361 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 362 case UE_CONTROL: 363 eptype = 0x0; 364 break; 365 case UE_ISOCHRONOUS: 366 eptype = 0x1; 367 break; 368 case UE_BULK: 369 eptype = 0x2; 370 break; 371 case UE_INTERRUPT: 372 eptype = 0x3; 373 break; 374 } 375 376 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 377 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 378 return eptype | 0x4; 379 else 380 return eptype; 381 } 382 383 static u_int 384 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 385 { 386 /* xHCI 1.0 section 4.5.1 */ 387 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 388 u_int in = 0; 389 390 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 391 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 392 in = 1; 393 394 return epaddr * 2 + in; 395 } 396 397 static inline u_int 398 xhci_dci_to_ici(const u_int i) 399 { 400 return i + 1; 401 } 402 403 static inline void * 404 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 405 const u_int dci) 406 { 407 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 408 } 409 410 #if 0 /* unused */ 411 static inline bus_addr_t 412 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 413 const u_int dci) 414 { 415 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 416 } 417 #endif /* unused */ 418 419 static inline void * 420 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 421 const u_int ici) 422 { 423 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 424 } 425 426 static inline bus_addr_t 427 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 428 const u_int ici) 429 { 430 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 431 } 432 433 static inline struct xhci_trb * 434 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 435 { 436 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 437 } 438 439 static inline bus_addr_t 440 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 441 { 442 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 443 } 444 445 static inline void 446 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 447 uint32_t control) 448 { 449 trb->trb_0 = parameter; 450 trb->trb_2 = status; 451 trb->trb_3 = control; 452 } 453 454 /* --- */ 455 456 void 457 xhci_childdet(device_t self, device_t child) 458 { 459 struct xhci_softc * const sc = device_private(self); 460 461 KASSERT(sc->sc_child == child); 462 if (child == sc->sc_child) 463 sc->sc_child = NULL; 464 } 465 466 int 467 xhci_detach(struct xhci_softc *sc, int flags) 468 { 469 int rv = 0; 470 471 if (sc->sc_child != NULL) 472 rv = config_detach(sc->sc_child, flags); 473 474 if (rv != 0) 475 return (rv); 476 477 /* XXX unconfigure/free slots */ 478 479 /* verify: */ 480 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 481 xhci_op_write_4(sc, XHCI_USBCMD, 0); 482 /* do we need to wait for stop? */ 483 484 xhci_op_write_8(sc, XHCI_CRCR, 0); 485 xhci_ring_free(sc, &sc->sc_cr); 486 cv_destroy(&sc->sc_command_cv); 487 488 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 489 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 490 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 491 xhci_ring_free(sc, &sc->sc_er); 492 493 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 494 495 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 496 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 497 498 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 499 500 mutex_destroy(&sc->sc_lock); 501 mutex_destroy(&sc->sc_intr_lock); 502 503 pool_cache_destroy(sc->sc_xferpool); 504 505 return rv; 506 } 507 508 int 509 xhci_activate(device_t self, enum devact act) 510 { 511 struct xhci_softc * const sc = device_private(self); 512 513 switch (act) { 514 case DVACT_DEACTIVATE: 515 sc->sc_dying = true; 516 return 0; 517 default: 518 return EOPNOTSUPP; 519 } 520 } 521 522 bool 523 xhci_suspend(device_t dv, const pmf_qual_t *qual) 524 { 525 return false; 526 } 527 528 bool 529 xhci_resume(device_t dv, const pmf_qual_t *qual) 530 { 531 return false; 532 } 533 534 bool 535 xhci_shutdown(device_t self, int flags) 536 { 537 return false; 538 } 539 540 541 static void 542 hexdump(const char *msg, const void *base, size_t len) 543 { 544 #if 0 545 size_t cnt; 546 const uint32_t *p; 547 extern paddr_t vtophys(vaddr_t); 548 549 p = base; 550 cnt = 0; 551 552 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 553 (void *)vtophys((vaddr_t)base)); 554 555 while (cnt < len) { 556 if (cnt % 16 == 0) 557 printf("%p: ", p); 558 else if (cnt % 8 == 0) 559 printf(" |"); 560 printf(" %08x", *p++); 561 cnt += 4; 562 if (cnt % 16 == 0) 563 printf("\n"); 564 } 565 #endif 566 } 567 568 569 int 570 xhci_init(struct xhci_softc *sc) 571 { 572 bus_size_t bsz; 573 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 574 uint32_t ecp, ecr; 575 uint32_t usbcmd, usbsts, pagesize, config; 576 int i; 577 uint16_t hciversion; 578 uint8_t caplength; 579 580 DPRINTF(("%s\n", __func__)); 581 582 /* XXX Low/Full/High speeds for now */ 583 sc->sc_bus.usbrev = USBREV_2_0; 584 585 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 586 caplength = XHCI_CAP_CAPLENGTH(cap); 587 hciversion = XHCI_CAP_HCIVERSION(cap); 588 589 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 590 aprint_normal_dev(sc->sc_dev, 591 "xHCI version %x.%x not known to be supported\n", 592 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 593 } else { 594 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 595 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 596 } 597 598 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 599 &sc->sc_cbh) != 0) { 600 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 601 return ENOMEM; 602 } 603 604 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 605 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 606 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 607 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 608 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 609 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 610 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 611 612 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 613 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 614 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 615 sc->sc_ctxsz); 616 617 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 618 ecp = XHCI_HCC_XECP(hcc) * 4; 619 while (ecp != 0) { 620 ecr = xhci_read_4(sc, ecp); 621 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 622 switch (XHCI_XECP_ID(ecr)) { 623 case XHCI_ID_PROTOCOLS: { 624 uint32_t w0, w4, w8; 625 uint16_t w2; 626 w0 = xhci_read_4(sc, ecp + 0); 627 w2 = (w0 >> 16) & 0xffff; 628 w4 = xhci_read_4(sc, ecp + 4); 629 w8 = xhci_read_4(sc, ecp + 8); 630 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 631 w0, w4, w8); 632 if (w4 == 0x20425355 && w2 == 0x0300) { 633 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 634 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 635 } 636 if (w4 == 0x20425355 && w2 == 0x0200) { 637 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 638 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 639 } 640 break; 641 } 642 default: 643 break; 644 } 645 ecr = xhci_read_4(sc, ecp); 646 if (XHCI_XECP_NEXT(ecr) == 0) { 647 ecp = 0; 648 } else { 649 ecp += XHCI_XECP_NEXT(ecr) * 4; 650 } 651 } 652 653 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 654 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 655 &sc->sc_obh) != 0) { 656 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 657 return ENOMEM; 658 } 659 660 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 661 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 662 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 663 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 664 return ENOMEM; 665 } 666 667 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 668 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 669 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 670 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 671 return ENOMEM; 672 } 673 674 for (i = 0; i < 100; i++) { 675 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 676 if ((usbsts & XHCI_STS_CNR) == 0) 677 break; 678 usb_delay_ms(&sc->sc_bus, 1); 679 } 680 if (i >= 100) 681 return EIO; 682 683 usbcmd = 0; 684 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 685 usb_delay_ms(&sc->sc_bus, 1); 686 687 usbcmd = XHCI_CMD_HCRST; 688 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 689 for (i = 0; i < 100; i++) { 690 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 691 if ((usbcmd & XHCI_CMD_HCRST) == 0) 692 break; 693 usb_delay_ms(&sc->sc_bus, 1); 694 } 695 if (i >= 100) 696 return EIO; 697 698 for (i = 0; i < 100; i++) { 699 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 700 if ((usbsts & XHCI_STS_CNR) == 0) 701 break; 702 usb_delay_ms(&sc->sc_bus, 1); 703 } 704 if (i >= 100) 705 return EIO; 706 707 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 708 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 709 pagesize = ffs(pagesize); 710 if (pagesize == 0) 711 return EIO; 712 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 713 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 714 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 715 (uint32_t)sc->sc_maxslots); 716 717 usbd_status err; 718 719 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 720 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 721 if (sc->sc_maxspbuf != 0) { 722 err = usb_allocmem(&sc->sc_bus, 723 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 724 &sc->sc_spbufarray_dma); 725 if (err) 726 return err; 727 728 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 729 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 730 for (i = 0; i < sc->sc_maxspbuf; i++) { 731 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 732 /* allocate contexts */ 733 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 734 sc->sc_pgsz, dma); 735 if (err) 736 return err; 737 spbufarray[i] = htole64(DMAADDR(dma, 0)); 738 usb_syncmem(dma, 0, sc->sc_pgsz, 739 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 740 } 741 742 usb_syncmem(&sc->sc_spbufarray_dma, 0, 743 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 744 } 745 746 config = xhci_op_read_4(sc, XHCI_CONFIG); 747 config &= ~0xFF; 748 config |= sc->sc_maxslots & 0xFF; 749 xhci_op_write_4(sc, XHCI_CONFIG, config); 750 751 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 752 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 753 if (err) { 754 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 755 return err; 756 } 757 758 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 759 XHCI_EVENT_RING_SEGMENTS_ALIGN); 760 if (err) { 761 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 762 return err; 763 } 764 765 usb_dma_t *dma; 766 size_t size; 767 size_t align; 768 769 dma = &sc->sc_eventst_dma; 770 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 771 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 772 KASSERT(size <= (512 * 1024)); 773 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 774 err = usb_allocmem(&sc->sc_bus, size, align, dma); 775 776 memset(KERNADDR(dma, 0), 0, size); 777 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 778 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 779 usbd_errstr(err), 780 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 781 KERNADDR(&sc->sc_eventst_dma, 0), 782 sc->sc_eventst_dma.block->size); 783 784 dma = &sc->sc_dcbaa_dma; 785 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 786 KASSERT(size <= 2048); 787 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 788 err = usb_allocmem(&sc->sc_bus, size, align, dma); 789 790 memset(KERNADDR(dma, 0), 0, size); 791 if (sc->sc_maxspbuf != 0) { 792 /* 793 * DCBA entry 0 hold the scratchbuf array pointer. 794 */ 795 *(uint64_t *)KERNADDR(dma, 0) = 796 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 797 } 798 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 799 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 800 usbd_errstr(err), 801 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 802 KERNADDR(&sc->sc_dcbaa_dma, 0), 803 sc->sc_dcbaa_dma.block->size); 804 805 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 806 KM_SLEEP); 807 808 cv_init(&sc->sc_command_cv, "xhcicmd"); 809 810 struct xhci_erste *erst; 811 erst = KERNADDR(&sc->sc_eventst_dma, 0); 812 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 813 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 814 erst[0].erste_3 = htole32(0); 815 usb_syncmem(&sc->sc_eventst_dma, 0, 816 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 817 818 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 819 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 820 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 821 XHCI_ERDP_LO_BUSY); 822 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 823 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 824 sc->sc_cr.xr_cs); 825 826 #if 0 827 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 828 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 829 #endif 830 831 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 832 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 833 834 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 835 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 836 xhci_op_read_4(sc, XHCI_USBCMD)); 837 838 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 839 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 840 cv_init(&sc->sc_softwake_cv, "xhciab"); 841 842 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 843 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 844 845 /* Set up the bus struct. */ 846 sc->sc_bus.methods = &xhci_bus_methods; 847 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 848 849 return USBD_NORMAL_COMPLETION; 850 } 851 852 int 853 xhci_intr(void *v) 854 { 855 struct xhci_softc * const sc = v; 856 int ret = 0; 857 858 if (sc == NULL) 859 return 0; 860 861 mutex_spin_enter(&sc->sc_intr_lock); 862 863 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 864 goto done; 865 866 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 867 868 /* If we get an interrupt while polling, then just ignore it. */ 869 if (sc->sc_bus.use_polling) { 870 #ifdef DIAGNOSTIC 871 DPRINTFN(16, ("xhci_intr: ignored interrupt while polling\n")); 872 #endif 873 goto done; 874 } 875 876 ret = xhci_intr1(sc); 877 done: 878 mutex_spin_exit(&sc->sc_intr_lock); 879 return ret; 880 } 881 882 int 883 xhci_intr1(struct xhci_softc * const sc) 884 { 885 uint32_t usbsts; 886 uint32_t iman; 887 888 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 889 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 890 #if 0 891 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 892 return 0; 893 } 894 #endif 895 xhci_op_write_4(sc, XHCI_USBSTS, 896 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 897 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 898 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 899 900 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 901 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 902 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 903 return 0; 904 } 905 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 906 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 907 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 908 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 909 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 910 911 sc->sc_bus.no_intrs++; 912 usb_schedsoftintr(&sc->sc_bus); 913 914 return 1; 915 } 916 917 static usbd_status 918 xhci_configure_endpoint(usbd_pipe_handle pipe) 919 { 920 struct xhci_softc * const sc = pipe->device->bus->hci_private; 921 struct xhci_slot * const xs = pipe->device->hci_private; 922 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 923 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 924 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 925 struct xhci_trb trb; 926 usbd_status err; 927 uint32_t *cp; 928 929 device_printf(sc->sc_dev, "%s dci %u (0x%x)\n", __func__, dci, 930 pipe->endpoint->edesc->bEndpointAddress); 931 932 /* XXX ensure input context is available? */ 933 934 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 935 936 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 937 cp[0] = htole32(0); 938 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 939 940 /* set up input slot context */ 941 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 942 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 943 cp[1] = htole32(0); 944 cp[2] = htole32(0); 945 cp[3] = htole32(0); 946 947 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 948 if (xfertype == UE_INTERRUPT) { 949 cp[0] = htole32( 950 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 951 ); 952 cp[1] = htole32( 953 XHCI_EPCTX_1_CERR_SET(3) | 954 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 955 XHCI_EPCTX_1_MAXB_SET(0) | 956 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 957 ); 958 cp[4] = htole32( 959 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 960 ); 961 } else { 962 cp[0] = htole32(0); 963 cp[1] = htole32( 964 XHCI_EPCTX_1_CERR_SET(3) | 965 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 966 XHCI_EPCTX_1_MAXB_SET(0) | 967 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 968 ); 969 } 970 *(uint64_t *)(&cp[2]) = htole64( 971 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 972 XHCI_EPCTX_2_DCS_SET(1)); 973 974 /* sync input contexts before they are read from memory */ 975 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 976 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 977 sc->sc_ctxsz * 1); 978 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 979 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 980 981 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 982 trb.trb_2 = 0; 983 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 984 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 985 986 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 987 988 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 989 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 990 sc->sc_ctxsz * 1); 991 992 return err; 993 } 994 995 static usbd_status 996 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 997 { 998 return USBD_NORMAL_COMPLETION; 999 } 1000 1001 static usbd_status 1002 xhci_reset_endpoint(usbd_pipe_handle pipe) 1003 { 1004 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1005 struct xhci_slot * const xs = pipe->device->hci_private; 1006 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1007 struct xhci_trb trb; 1008 usbd_status err; 1009 1010 device_printf(sc->sc_dev, "%s\n", __func__); 1011 1012 trb.trb_0 = 0; 1013 trb.trb_2 = 0; 1014 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1015 XHCI_TRB_3_EP_SET(dci) | 1016 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1017 1018 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1019 1020 return err; 1021 } 1022 1023 #if 0 1024 static usbd_status 1025 xhci_stop_endpoint(usbd_pipe_handle pipe) 1026 { 1027 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1028 struct xhci_slot * const xs = pipe->device->hci_private; 1029 struct xhci_trb trb; 1030 usbd_status err; 1031 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1032 1033 device_printf(sc->sc_dev, "%s\n", __func__); 1034 1035 trb.trb_0 = 0; 1036 trb.trb_2 = 0; 1037 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1038 XHCI_TRB_3_EP_SET(dci) | 1039 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1040 1041 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1042 1043 return err; 1044 } 1045 #endif 1046 1047 static usbd_status 1048 xhci_set_dequeue(usbd_pipe_handle pipe) 1049 { 1050 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1051 struct xhci_slot * const xs = pipe->device->hci_private; 1052 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1053 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1054 struct xhci_trb trb; 1055 usbd_status err; 1056 1057 device_printf(sc->sc_dev, "%s\n", __func__); 1058 1059 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1060 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1061 BUS_DMASYNC_PREWRITE); 1062 1063 xr->xr_ep = 0; 1064 xr->xr_cs = 1; 1065 1066 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1067 trb.trb_2 = 0; 1068 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1069 XHCI_TRB_3_EP_SET(dci) | 1070 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1071 1072 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1073 1074 return err; 1075 } 1076 1077 static usbd_status 1078 xhci_open(usbd_pipe_handle pipe) 1079 { 1080 usbd_device_handle const dev = pipe->device; 1081 struct xhci_softc * const sc = dev->bus->hci_private; 1082 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 1083 const int8_t addr = dev->address; 1084 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1085 1086 DPRINTF(("%s\n", __func__)); 1087 DPRINTF(("addr %d\n", addr)); 1088 device_printf(sc->sc_dev, "%s addr %d depth %d port %d speed %d\n", 1089 __func__, addr, dev->depth, dev->powersrc->portno, dev->speed); 1090 1091 if (sc->sc_dying) 1092 return USBD_IOERROR; 1093 1094 /* Root Hub */ 1095 if (dev->depth == 0 && dev->powersrc->portno == 0 && 1096 dev->speed != USB_SPEED_SUPER) { 1097 switch (ed->bEndpointAddress) { 1098 case USB_CONTROL_ENDPOINT: 1099 pipe->methods = &xhci_root_ctrl_methods; 1100 break; 1101 case UE_DIR_IN | XHCI_INTR_ENDPT: 1102 pipe->methods = &xhci_root_intr_methods; 1103 break; 1104 default: 1105 pipe->methods = NULL; 1106 DPRINTF(("xhci_open: bad bEndpointAddress 0x%02x\n", 1107 ed->bEndpointAddress)); 1108 return USBD_INVAL; 1109 } 1110 return USBD_NORMAL_COMPLETION; 1111 } 1112 1113 switch (xfertype) { 1114 case UE_CONTROL: 1115 pipe->methods = &xhci_device_ctrl_methods; 1116 break; 1117 case UE_ISOCHRONOUS: 1118 pipe->methods = &xhci_device_isoc_methods; 1119 return USBD_INVAL; 1120 break; 1121 case UE_BULK: 1122 pipe->methods = &xhci_device_bulk_methods; 1123 break; 1124 case UE_INTERRUPT: 1125 pipe->methods = &xhci_device_intr_methods; 1126 break; 1127 default: 1128 return USBD_IOERROR; 1129 break; 1130 } 1131 1132 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1133 xhci_configure_endpoint(pipe); 1134 1135 return USBD_NORMAL_COMPLETION; 1136 } 1137 1138 static void 1139 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1140 { 1141 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1142 uint8_t *p; 1143 1144 device_printf(sc->sc_dev, "port %u status change\n", port); 1145 1146 if (xfer == NULL) 1147 return; 1148 1149 if (!(port >= sc->sc_hs_port_start && 1150 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1151 return; 1152 1153 port -= sc->sc_hs_port_start; 1154 port += 1; 1155 device_printf(sc->sc_dev, "hs port %u status change\n", port); 1156 1157 p = KERNADDR(&xfer->dmabuf, 0); 1158 memset(p, 0, xfer->length); 1159 p[port/NBBY] |= 1 << (port%NBBY); 1160 xfer->actlen = xfer->length; 1161 xfer->status = USBD_NORMAL_COMPLETION; 1162 usb_transfer_complete(xfer); 1163 } 1164 1165 static void 1166 xhci_handle_event(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1167 { 1168 uint64_t trb_0; 1169 uint32_t trb_2, trb_3; 1170 1171 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1172 1173 trb_0 = le64toh(trb->trb_0); 1174 trb_2 = le32toh(trb->trb_2); 1175 trb_3 = le32toh(trb->trb_3); 1176 1177 #if 0 1178 device_printf(sc->sc_dev, 1179 "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", trb, 1180 trb_0, trb_2, trb_3); 1181 #endif 1182 1183 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1184 case XHCI_TRB_EVENT_TRANSFER: { 1185 u_int slot, dci; 1186 struct xhci_slot *xs; 1187 struct xhci_ring *xr; 1188 struct xhci_xfer *xx; 1189 usbd_xfer_handle xfer; 1190 usbd_status err; 1191 1192 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1193 dci = XHCI_TRB_3_EP_GET(trb_3); 1194 1195 xs = &sc->sc_slots[slot]; 1196 xr = &xs->xs_ep[dci].xe_tr; 1197 1198 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1199 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1200 sizeof(struct xhci_trb)]; 1201 } else { 1202 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1203 } 1204 xfer = &xx->xx_xfer; 1205 #if 0 1206 device_printf(sc->sc_dev, "%s xfer %p\n", __func__, xfer); 1207 #endif 1208 1209 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1210 #if 0 1211 device_printf(sc->sc_dev, "transfer event data: " 1212 "0x%016"PRIx64" 0x%08"PRIx32" %02x\n", 1213 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1214 XHCI_TRB_2_ERROR_GET(trb_2)); 1215 #endif 1216 if ((trb_0 & 0x3) == 0x3) { 1217 xfer->actlen = XHCI_TRB_2_REM_GET(trb_2); 1218 } 1219 } 1220 1221 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1222 XHCI_TRB_ERROR_SUCCESS) { 1223 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1224 err = USBD_NORMAL_COMPLETION; 1225 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1226 XHCI_TRB_ERROR_SHORT_PKT) { 1227 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1228 err = USBD_NORMAL_COMPLETION; 1229 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1230 XHCI_TRB_ERROR_STALL) { 1231 err = USBD_STALLED; 1232 xr->is_halted = true; 1233 } else { 1234 err = USBD_IOERROR; 1235 } 1236 xfer->status = err; 1237 1238 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1239 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1240 if ((trb_0 & 0x3) == 0x0) { 1241 usb_transfer_complete(xfer); 1242 } 1243 } else { 1244 usb_transfer_complete(xfer); 1245 } 1246 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1247 1248 } 1249 break; 1250 case XHCI_TRB_EVENT_CMD_COMPLETE: 1251 if (trb_0 == sc->sc_command_addr) { 1252 sc->sc_result_trb.trb_0 = trb_0; 1253 sc->sc_result_trb.trb_2 = trb_2; 1254 sc->sc_result_trb.trb_3 = trb_3; 1255 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1256 XHCI_TRB_ERROR_SUCCESS) { 1257 device_printf(sc->sc_dev, "command completion " 1258 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1259 "0x%08"PRIx32"\n", trb_0, trb_2, trb_3); 1260 } 1261 cv_signal(&sc->sc_command_cv); 1262 } else { 1263 device_printf(sc->sc_dev, "event: %p 0x%016"PRIx64" " 1264 "0x%08"PRIx32" 0x%08"PRIx32"\n", trb, trb_0, 1265 trb_2, trb_3); 1266 } 1267 break; 1268 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1269 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1270 break; 1271 default: 1272 break; 1273 } 1274 } 1275 1276 static void 1277 xhci_softintr(void *v) 1278 { 1279 struct usbd_bus * const bus = v; 1280 struct xhci_softc * const sc = bus->hci_private; 1281 struct xhci_ring * const er = &sc->sc_er; 1282 struct xhci_trb *trb; 1283 int i, j, k; 1284 1285 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1286 1287 i = er->xr_ep; 1288 j = er->xr_cs; 1289 1290 while (1) { 1291 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1292 BUS_DMASYNC_POSTREAD); 1293 trb = &er->xr_trb[i]; 1294 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1295 1296 if (j != k) 1297 break; 1298 1299 xhci_handle_event(sc, trb); 1300 1301 i++; 1302 if (i == XHCI_EVENT_RING_TRBS) { 1303 i = 0; 1304 j ^= 1; 1305 } 1306 } 1307 1308 er->xr_ep = i; 1309 er->xr_cs = j; 1310 1311 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1312 XHCI_ERDP_LO_BUSY); 1313 1314 DPRINTF(("%s: %s ends\n", __func__, device_xname(sc->sc_dev))); 1315 1316 return; 1317 } 1318 1319 static void 1320 xhci_poll(struct usbd_bus *bus) 1321 { 1322 struct xhci_softc * const sc = bus->hci_private; 1323 1324 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1325 1326 mutex_spin_enter(&sc->sc_intr_lock); 1327 xhci_intr1(sc); 1328 mutex_spin_exit(&sc->sc_intr_lock); 1329 1330 return; 1331 } 1332 1333 static usbd_status 1334 xhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1335 { 1336 struct xhci_softc * const sc = bus->hci_private; 1337 usbd_status err; 1338 1339 DPRINTF(("%s\n", __func__)); 1340 1341 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, 0); 1342 #if 0 1343 if (err == USBD_NOMEM) 1344 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1345 #endif 1346 #ifdef XHCI_DEBUG 1347 if (err) 1348 device_printf(sc->sc_dev, "xhci_allocm: usb_allocmem()=%d\n", 1349 err); 1350 #endif 1351 1352 return err; 1353 } 1354 1355 static void 1356 xhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1357 { 1358 struct xhci_softc * const sc = bus->hci_private; 1359 1360 // DPRINTF(("%s\n", __func__)); 1361 1362 #if 0 1363 if (dma->block->flags & USB_DMA_RESERVE) { 1364 usb_reserve_freem(&sc->sc_dma_reserve, dma); 1365 return; 1366 } 1367 #endif 1368 usb_freemem(&sc->sc_bus, dma); 1369 } 1370 1371 static usbd_xfer_handle 1372 xhci_allocx(struct usbd_bus *bus) 1373 { 1374 struct xhci_softc * const sc = bus->hci_private; 1375 usbd_xfer_handle xfer; 1376 1377 // DPRINTF(("%s\n", __func__)); 1378 1379 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1380 if (xfer != NULL) { 1381 memset(xfer, 0, sizeof(struct xhci_xfer)); 1382 #ifdef DIAGNOSTIC 1383 xfer->busy_free = XFER_BUSY; 1384 #endif 1385 } 1386 1387 return xfer; 1388 } 1389 1390 static void 1391 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1392 { 1393 struct xhci_softc * const sc = bus->hci_private; 1394 1395 // DPRINTF(("%s\n", __func__)); 1396 1397 #ifdef DIAGNOSTIC 1398 if (xfer->busy_free != XFER_BUSY) { 1399 device_printf(sc->sc_dev, "xhci_freex: xfer=%p " 1400 "not busy, 0x%08x\n", xfer, xfer->busy_free); 1401 } 1402 xfer->busy_free = XFER_FREE; 1403 #endif 1404 pool_cache_put(sc->sc_xferpool, xfer); 1405 } 1406 1407 static void 1408 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1409 { 1410 struct xhci_softc * const sc = bus->hci_private; 1411 1412 *lock = &sc->sc_lock; 1413 } 1414 1415 extern u_int32_t usb_cookie_no; 1416 1417 static usbd_status 1418 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1419 int speed, int port, struct usbd_port *up) 1420 { 1421 struct xhci_softc * const sc = bus->hci_private; 1422 usbd_device_handle dev; 1423 usbd_status err; 1424 usb_device_descriptor_t *dd; 1425 struct usbd_device *hub; 1426 struct usbd_device *adev; 1427 int rhport = 0; 1428 struct xhci_slot *xs; 1429 uint32_t *cp; 1430 uint8_t slot; 1431 uint8_t addr; 1432 1433 dev = malloc(sizeof *dev, M_USB, M_NOWAIT|M_ZERO); 1434 if (dev == NULL) 1435 return USBD_NOMEM; 1436 1437 dev->bus = bus; 1438 1439 /* Set up default endpoint handle. */ 1440 dev->def_ep.edesc = &dev->def_ep_desc; 1441 1442 /* Set up default endpoint descriptor. */ 1443 dev->def_ep_desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1444 dev->def_ep_desc.bDescriptorType = UDESC_ENDPOINT; 1445 dev->def_ep_desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1446 dev->def_ep_desc.bmAttributes = UE_CONTROL; 1447 /* XXX */ 1448 USETW(dev->def_ep_desc.wMaxPacketSize, 64); 1449 dev->def_ep_desc.bInterval = 0; 1450 1451 /* doesn't matter, just don't let it uninitialized */ 1452 dev->def_ep.datatoggle = 0; 1453 1454 device_printf(sc->sc_dev, "%s up %p portno %d\n", __func__, up, 1455 up->portno); 1456 1457 dev->quirks = &usbd_no_quirk; 1458 dev->address = 0; 1459 dev->ddesc.bMaxPacketSize = 0; 1460 dev->depth = depth; 1461 dev->powersrc = up; 1462 dev->myhub = up->parent; 1463 1464 up->device = dev; 1465 1466 /* Locate root hub port */ 1467 for (adev = dev, hub = dev; 1468 hub != NULL; 1469 adev = hub, hub = hub->myhub) { 1470 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1471 } 1472 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1473 1474 if (hub != NULL) { 1475 for (int p = 0; p < hub->hub->hubdesc.bNbrPorts; p++) { 1476 if (hub->hub->ports[p].device == adev) { 1477 rhport = p; 1478 } 1479 } 1480 } else { 1481 rhport = port; 1482 } 1483 if (speed == USB_SPEED_SUPER) { 1484 rhport += sc->sc_ss_port_start - 1; 1485 } else { 1486 rhport += sc->sc_hs_port_start - 1; 1487 } 1488 device_printf(sc->sc_dev, "%s rhport %d\n", __func__, rhport); 1489 1490 dev->speed = speed; 1491 dev->langid = USBD_NOLANG; 1492 dev->cookie.cookie = ++usb_cookie_no; 1493 1494 /* Establish the default pipe. */ 1495 err = usbd_setup_pipe(dev, 0, &dev->def_ep, USBD_DEFAULT_INTERVAL, 1496 &dev->default_pipe); 1497 if (err) { 1498 usbd_remove_device(dev, up); 1499 return (err); 1500 } 1501 1502 dd = &dev->ddesc; 1503 1504 if ((depth == 0) && (port == 0)) { 1505 KASSERT(bus->devices[dev->address] == NULL); 1506 bus->devices[dev->address] = dev; 1507 err = usbd_get_initial_ddesc(dev, dd); 1508 if (err) 1509 return err; 1510 err = usbd_reload_device_desc(dev); 1511 if (err) 1512 return err; 1513 } else { 1514 err = xhci_enable_slot(sc, &slot); 1515 if (err) 1516 return err; 1517 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1518 if (err) 1519 return err; 1520 xs = &sc->sc_slots[slot]; 1521 dev->hci_private = xs; 1522 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1523 //hexdump("slot context", cp, sc->sc_ctxsz); 1524 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1525 device_printf(sc->sc_dev, "%s device address %u\n", 1526 __func__, addr); 1527 /* XXX ensure we know when the hardware does something 1528 we can't yet cope with */ 1529 KASSERT(addr >= 1 && addr <= 127); 1530 dev->address = addr; 1531 /* XXX dev->address not necessarily unique on bus */ 1532 KASSERT(bus->devices[dev->address] == NULL); 1533 bus->devices[dev->address] = dev; 1534 1535 err = usbd_get_initial_ddesc(dev, dd); 1536 if (err) 1537 return err; 1538 /* 4.8.2.1 */ 1539 if (speed == USB_SPEED_SUPER) 1540 USETW(dev->def_ep_desc.wMaxPacketSize, 1541 (1 << dd->bMaxPacketSize)); 1542 else 1543 USETW(dev->def_ep_desc.wMaxPacketSize, 1544 dd->bMaxPacketSize); 1545 device_printf(sc->sc_dev, "%s bMaxPacketSize %u\n", __func__, 1546 dd->bMaxPacketSize); 1547 xhci_update_ep0_mps(sc, xs, 1548 UGETW(dev->def_ep_desc.wMaxPacketSize)); 1549 err = usbd_reload_device_desc(dev); 1550 if (err) 1551 return err; 1552 1553 usbd_kill_pipe(dev->default_pipe); 1554 err = usbd_setup_pipe(dev, 0, &dev->def_ep, 1555 USBD_DEFAULT_INTERVAL, &dev->default_pipe); 1556 } 1557 1558 DPRINTF(("usbd_new_device: adding unit addr=%d, rev=%02x, class=%d, " 1559 "subclass=%d, protocol=%d, maxpacket=%d, len=%d, noconf=%d, " 1560 "speed=%d\n", dev->address,UGETW(dd->bcdUSB), 1561 dd->bDeviceClass, dd->bDeviceSubClass, dd->bDeviceProtocol, 1562 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1563 dev->speed)); 1564 1565 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1566 1567 if ((depth == 0) && (port == 0)) { 1568 usbd_attach_roothub(parent, dev); 1569 device_printf(sc->sc_dev, "root_hub %p\n", bus->root_hub); 1570 return USBD_NORMAL_COMPLETION; 1571 } 1572 1573 1574 err = usbd_probe_and_attach(parent, dev, port, dev->address); 1575 if (err) { 1576 usbd_remove_device(dev, up); 1577 return (err); 1578 } 1579 1580 return USBD_NORMAL_COMPLETION; 1581 } 1582 1583 static usbd_status 1584 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1585 size_t ntrb, size_t align) 1586 { 1587 usbd_status err; 1588 size_t size = ntrb * XHCI_TRB_SIZE; 1589 1590 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1591 if (err) 1592 return err; 1593 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1594 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1595 xr->xr_trb = xhci_ring_trbv(xr, 0); 1596 xr->xr_ntrb = ntrb; 1597 xr->xr_ep = 0; 1598 xr->xr_cs = 1; 1599 memset(xr->xr_trb, 0, size); 1600 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1601 xr->is_halted = false; 1602 1603 return USBD_NORMAL_COMPLETION; 1604 } 1605 1606 static void 1607 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1608 { 1609 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1610 mutex_destroy(&xr->xr_lock); 1611 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1612 } 1613 1614 static void 1615 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1616 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1617 { 1618 size_t i; 1619 u_int ri; 1620 u_int cs; 1621 uint64_t parameter; 1622 uint32_t status; 1623 uint32_t control; 1624 1625 for (i = 0; i < ntrbs; i++) { 1626 #if 0 1627 device_printf(sc->sc_dev, "%s %p %p %zu " 1628 "%016"PRIx64" %08"PRIx32" %08"PRIx32"\n", __func__, xr, 1629 trbs, i, trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3); 1630 #endif 1631 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1632 XHCI_TRB_TYPE_LINK); 1633 } 1634 1635 #if 0 1636 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1637 xr, xr->xr_ep, xr->xr_cs); 1638 #endif 1639 1640 ri = xr->xr_ep; 1641 cs = xr->xr_cs; 1642 1643 /* 1644 * Although the xhci hardware can do scatter/gather dma from 1645 * arbitrary sized buffers, there is a non-obvious restriction 1646 * that a LINK trb is only allowed at the end of a burst of 1647 * transfers - which might be 16kB. 1648 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 1649 * The simple solution is not to allow a LINK trb in the middle 1650 * of anything - as here. 1651 * XXX: (dsl) There are xhci controllers out there (eg some made by 1652 * ASMedia) that seem to lock up if they process a LINK trb but 1653 * cannot process the linked-to trb yet. 1654 * The code should write the 'cycle' bit on the link trb AFTER 1655 * adding the other trb. 1656 */ 1657 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1658 parameter = xhci_ring_trbp(xr, 0); 1659 status = 0; 1660 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1661 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1662 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1663 htole32(status), htole32(control)); 1664 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1665 BUS_DMASYNC_PREWRITE); 1666 xr->xr_cookies[ri] = NULL; 1667 xr->xr_ep = 0; 1668 xr->xr_cs ^= 1; 1669 ri = xr->xr_ep; 1670 cs = xr->xr_cs; 1671 } 1672 1673 ri++; 1674 1675 /* Write any subsequent TRB first */ 1676 for (i = 1; i < ntrbs; i++) { 1677 parameter = trbs[i].trb_0; 1678 status = trbs[i].trb_2; 1679 control = trbs[i].trb_3; 1680 1681 if (cs) { 1682 control |= XHCI_TRB_3_CYCLE_BIT; 1683 } else { 1684 control &= ~XHCI_TRB_3_CYCLE_BIT; 1685 } 1686 1687 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1688 htole32(status), htole32(control)); 1689 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1690 BUS_DMASYNC_PREWRITE); 1691 xr->xr_cookies[ri] = cookie; 1692 ri++; 1693 } 1694 1695 /* Write the first TRB last */ 1696 i = 0; 1697 { 1698 parameter = trbs[i].trb_0; 1699 status = trbs[i].trb_2; 1700 control = trbs[i].trb_3; 1701 1702 if (xr->xr_cs) { 1703 control |= XHCI_TRB_3_CYCLE_BIT; 1704 } else { 1705 control &= ~XHCI_TRB_3_CYCLE_BIT; 1706 } 1707 1708 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1709 htole32(status), htole32(control)); 1710 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1711 BUS_DMASYNC_PREWRITE); 1712 xr->xr_cookies[xr->xr_ep] = cookie; 1713 } 1714 1715 xr->xr_ep = ri; 1716 xr->xr_cs = cs; 1717 1718 #if 0 1719 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1720 xr, xr->xr_ep, xr->xr_cs); 1721 #endif 1722 } 1723 1724 static usbd_status 1725 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1726 int timeout) 1727 { 1728 struct xhci_ring * const cr = &sc->sc_cr; 1729 usbd_status err; 1730 1731 device_printf(sc->sc_dev, "%s input: " 1732 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1733 trb->trb_0, trb->trb_2, trb->trb_3); 1734 1735 mutex_enter(&sc->sc_lock); 1736 1737 KASSERT(sc->sc_command_addr == 0); 1738 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1739 1740 mutex_enter(&cr->xr_lock); 1741 xhci_ring_put(sc, cr, NULL, trb, 1); 1742 mutex_exit(&cr->xr_lock); 1743 1744 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1745 1746 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1747 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1748 err = USBD_TIMEOUT; 1749 goto timedout; 1750 } 1751 1752 trb->trb_0 = sc->sc_result_trb.trb_0; 1753 trb->trb_2 = sc->sc_result_trb.trb_2; 1754 trb->trb_3 = sc->sc_result_trb.trb_3; 1755 1756 device_printf(sc->sc_dev, "%s output: " 1757 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1758 trb->trb_0, trb->trb_2, trb->trb_3); 1759 1760 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1761 case XHCI_TRB_ERROR_SUCCESS: 1762 err = USBD_NORMAL_COMPLETION; 1763 break; 1764 default: 1765 case 192 ... 223: 1766 err = USBD_IOERROR; 1767 break; 1768 case 224 ... 255: 1769 err = USBD_NORMAL_COMPLETION; 1770 break; 1771 } 1772 1773 timedout: 1774 sc->sc_command_addr = 0; 1775 mutex_exit(&sc->sc_lock); 1776 return err; 1777 } 1778 1779 static usbd_status 1780 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1781 { 1782 struct xhci_trb trb; 1783 usbd_status err; 1784 1785 trb.trb_0 = 0; 1786 trb.trb_2 = 0; 1787 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1788 1789 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1790 if (err != USBD_NORMAL_COMPLETION) { 1791 return err; 1792 } 1793 1794 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1795 1796 return err; 1797 } 1798 1799 static usbd_status 1800 xhci_address_device(struct xhci_softc * const sc, 1801 uint64_t icp, uint8_t slot_id, bool bsr) 1802 { 1803 struct xhci_trb trb; 1804 usbd_status err; 1805 1806 trb.trb_0 = icp; 1807 trb.trb_2 = 0; 1808 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1809 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1810 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1811 1812 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1813 return err; 1814 } 1815 1816 static usbd_status 1817 xhci_update_ep0_mps(struct xhci_softc * const sc, 1818 struct xhci_slot * const xs, u_int mps) 1819 { 1820 struct xhci_trb trb; 1821 usbd_status err; 1822 uint32_t * cp; 1823 1824 device_printf(sc->sc_dev, "%s\n", __func__); 1825 1826 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1827 cp[0] = htole32(0); 1828 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1829 1830 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1831 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1832 1833 /* sync input contexts before they are read from memory */ 1834 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1835 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1836 sc->sc_ctxsz * 4); 1837 1838 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1839 trb.trb_2 = 0; 1840 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1841 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1842 1843 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1844 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1845 return err; 1846 } 1847 1848 static void 1849 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1850 { 1851 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1852 1853 device_printf(sc->sc_dev, "dcbaa %p dc %016"PRIx64" slot %d\n", 1854 &dcbaa[si], dcba, si); 1855 1856 dcbaa[si] = htole64(dcba); 1857 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1858 BUS_DMASYNC_PREWRITE); 1859 } 1860 1861 static usbd_status 1862 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1863 int speed, int port, int rhport) 1864 { 1865 struct xhci_slot *xs; 1866 usbd_status err; 1867 u_int dci; 1868 uint32_t *cp; 1869 uint32_t mps; 1870 uint32_t xspeed; 1871 1872 switch (speed) { 1873 case USB_SPEED_LOW: 1874 xspeed = 2; 1875 mps = USB_MAX_IPACKET; 1876 break; 1877 case USB_SPEED_FULL: 1878 xspeed = 1; 1879 mps = 64; 1880 break; 1881 case USB_SPEED_HIGH: 1882 xspeed = 3; 1883 mps = USB_2_MAX_CTRL_PACKET; 1884 break; 1885 case USB_SPEED_SUPER: 1886 xspeed = 4; 1887 mps = USB_3_MAX_CTRL_PACKET; 1888 break; 1889 default: 1890 device_printf(sc->sc_dev, "%s: impossible speed: %x", 1891 __func__, speed); 1892 return USBD_INVAL; 1893 } 1894 1895 xs = &sc->sc_slots[slot]; 1896 xs->xs_idx = slot; 1897 1898 /* allocate contexts */ 1899 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1900 &xs->xs_dc_dma); 1901 if (err) 1902 return err; 1903 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1904 1905 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1906 &xs->xs_ic_dma); 1907 if (err) 1908 return err; 1909 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1910 1911 for (dci = 0; dci < 32; dci++) { 1912 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1913 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1914 if (dci == XHCI_DCI_SLOT) 1915 continue; 1916 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1917 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1918 if (err) { 1919 device_printf(sc->sc_dev, "ring init failure\n"); 1920 return err; 1921 } 1922 } 1923 1924 /* set up initial input control context */ 1925 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1926 cp[0] = htole32(0); 1927 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1928 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1929 1930 /* set up input slot context */ 1931 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1932 cp[0] = htole32( 1933 XHCI_SCTX_0_CTX_NUM_SET(1) | 1934 XHCI_SCTX_0_SPEED_SET(xspeed) 1935 ); 1936 cp[1] = htole32( 1937 XHCI_SCTX_1_RH_PORT_SET(rhport) 1938 ); 1939 cp[2] = htole32( 1940 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1941 ); 1942 cp[3] = htole32(0); 1943 1944 /* set up input EP0 context */ 1945 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1946 cp[0] = htole32(0); 1947 cp[1] = htole32( 1948 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1949 XHCI_EPCTX_1_EPTYPE_SET(4) | 1950 XHCI_EPCTX_1_CERR_SET(3) 1951 ); 1952 /* can't use xhci_ep_get_dci() yet? */ 1953 *(uint64_t *)(&cp[2]) = htole64( 1954 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1955 XHCI_EPCTX_2_DCS_SET(1)); 1956 cp[4] = htole32( 1957 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1958 ); 1959 1960 /* sync input contexts before they are read from memory */ 1961 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1962 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1963 sc->sc_ctxsz * 3); 1964 1965 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1966 1967 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1968 false); 1969 1970 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1971 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1972 sc->sc_ctxsz * 2); 1973 1974 return err; 1975 } 1976 1977 /* ----- */ 1978 1979 static void 1980 xhci_noop(usbd_pipe_handle pipe) 1981 { 1982 DPRINTF(("%s\n", __func__)); 1983 } 1984 1985 /* root hub descriptors */ 1986 1987 static const usb_device_descriptor_t xhci_devd = { 1988 USB_DEVICE_DESCRIPTOR_SIZE, 1989 UDESC_DEVICE, /* type */ 1990 {0x00, 0x02}, /* USB version */ 1991 UDCLASS_HUB, /* class */ 1992 UDSUBCLASS_HUB, /* subclass */ 1993 UDPROTO_HSHUBSTT, /* protocol */ 1994 64, /* max packet */ 1995 {0},{0},{0x00,0x01}, /* device id */ 1996 1,2,0, /* string indexes */ 1997 1 /* # of configurations */ 1998 }; 1999 2000 static const usb_device_qualifier_t xhci_odevd = { 2001 USB_DEVICE_DESCRIPTOR_SIZE, 2002 UDESC_DEVICE_QUALIFIER, /* type */ 2003 {0x00, 0x02}, /* USB version */ 2004 UDCLASS_HUB, /* class */ 2005 UDSUBCLASS_HUB, /* subclass */ 2006 UDPROTO_FSHUB, /* protocol */ 2007 64, /* max packet */ 2008 1, /* # of configurations */ 2009 0 2010 }; 2011 2012 static const usb_config_descriptor_t xhci_confd = { 2013 USB_CONFIG_DESCRIPTOR_SIZE, 2014 UDESC_CONFIG, 2015 {USB_CONFIG_DESCRIPTOR_SIZE + 2016 USB_INTERFACE_DESCRIPTOR_SIZE + 2017 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2018 1, 2019 1, 2020 0, 2021 UC_ATTR_MBO | UC_SELF_POWERED, 2022 0 /* max power */ 2023 }; 2024 2025 static const usb_interface_descriptor_t xhci_ifcd = { 2026 USB_INTERFACE_DESCRIPTOR_SIZE, 2027 UDESC_INTERFACE, 2028 0, 2029 0, 2030 1, 2031 UICLASS_HUB, 2032 UISUBCLASS_HUB, 2033 UIPROTO_HSHUBSTT, 2034 0 2035 }; 2036 2037 static const usb_endpoint_descriptor_t xhci_endpd = { 2038 USB_ENDPOINT_DESCRIPTOR_SIZE, 2039 UDESC_ENDPOINT, 2040 UE_DIR_IN | XHCI_INTR_ENDPT, 2041 UE_INTERRUPT, 2042 {8, 0}, /* max packet */ 2043 12 2044 }; 2045 2046 static const usb_hub_descriptor_t xhci_hubd = { 2047 USB_HUB_DESCRIPTOR_SIZE, 2048 UDESC_HUB, 2049 0, 2050 {0,0}, 2051 0, 2052 0, 2053 {""}, 2054 {""}, 2055 }; 2056 2057 /* root hub control */ 2058 2059 static usbd_status 2060 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 2061 { 2062 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2063 usbd_status err; 2064 2065 DPRINTF(("%s\n", __func__)); 2066 2067 /* Insert last in queue. */ 2068 mutex_enter(&sc->sc_lock); 2069 err = usb_insert_transfer(xfer); 2070 mutex_exit(&sc->sc_lock); 2071 if (err) 2072 return err; 2073 2074 /* Pipe isn't running, start first */ 2075 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2076 } 2077 2078 static usbd_status 2079 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2080 { 2081 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2082 usb_port_status_t ps; 2083 usb_device_request_t *req; 2084 void *buf = NULL; 2085 usb_hub_descriptor_t hubd; 2086 usbd_status err; 2087 int len, value, index; 2088 int l, totlen = 0; 2089 int port, i; 2090 uint32_t v; 2091 2092 DPRINTF(("%s\n", __func__)); 2093 2094 if (sc->sc_dying) 2095 return USBD_IOERROR; 2096 2097 req = &xfer->request; 2098 2099 value = UGETW(req->wValue); 2100 index = UGETW(req->wIndex); 2101 len = UGETW(req->wLength); 2102 2103 if (len != 0) 2104 buf = KERNADDR(&xfer->dmabuf, 0); 2105 2106 DPRINTF(("root req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2107 req->bRequest, value, index, len)); 2108 2109 #define C(x,y) ((x) | ((y) << 8)) 2110 switch(C(req->bRequest, req->bmRequestType)) { 2111 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2112 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2113 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2114 /* 2115 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2116 * for the integrated root hub. 2117 */ 2118 break; 2119 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2120 if (len > 0) { 2121 *(uint8_t *)buf = sc->sc_conf; 2122 totlen = 1; 2123 } 2124 break; 2125 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2126 DPRINTFN(8,("xhci_root_ctrl_start: wValue=0x%04x\n", value)); 2127 if (len == 0) 2128 break; 2129 switch(value >> 8) { 2130 case UDESC_DEVICE: 2131 if ((value & 0xff) != 0) { 2132 err = USBD_IOERROR; 2133 goto ret; 2134 } 2135 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2136 memcpy(buf, &xhci_devd, min(l, sizeof(xhci_devd))); 2137 break; 2138 case UDESC_DEVICE_QUALIFIER: 2139 if ((value & 0xff) != 0) { 2140 } 2141 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2142 memcpy(buf, &xhci_odevd, min(l, sizeof(xhci_odevd))); 2143 break; 2144 case UDESC_OTHER_SPEED_CONFIGURATION: 2145 case UDESC_CONFIG: 2146 if ((value & 0xff) != 0) { 2147 err = USBD_IOERROR; 2148 goto ret; 2149 } 2150 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2151 memcpy(buf, &xhci_confd, min(l, sizeof(xhci_confd))); 2152 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2153 value >> 8; 2154 buf = (char *)buf + l; 2155 len -= l; 2156 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2157 totlen += l; 2158 memcpy(buf, &xhci_ifcd, min(l, sizeof(xhci_ifcd))); 2159 buf = (char *)buf + l; 2160 len -= l; 2161 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2162 totlen += l; 2163 memcpy(buf, &xhci_endpd, min(l, sizeof(xhci_endpd))); 2164 break; 2165 case UDESC_STRING: 2166 #define sd ((usb_string_descriptor_t *)buf) 2167 switch (value & 0xff) { 2168 case 0: /* Language table */ 2169 totlen = usb_makelangtbl(sd, len); 2170 break; 2171 case 1: /* Vendor */ 2172 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2173 break; 2174 case 2: /* Product */ 2175 totlen = usb_makestrdesc(sd, len, 2176 "xHCI Root Hub"); 2177 break; 2178 } 2179 #undef sd 2180 break; 2181 default: 2182 err = USBD_IOERROR; 2183 goto ret; 2184 } 2185 break; 2186 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2187 if (len > 0) { 2188 *(uint8_t *)buf = 0; 2189 totlen = 1; 2190 } 2191 break; 2192 case C(UR_GET_STATUS, UT_READ_DEVICE): 2193 if (len > 1) { 2194 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2195 totlen = 2; 2196 } 2197 break; 2198 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2199 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2200 if (len > 1) { 2201 USETW(((usb_status_t *)buf)->wStatus, 0); 2202 totlen = 2; 2203 } 2204 break; 2205 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2206 if (value >= USB_MAX_DEVICES) { 2207 err = USBD_IOERROR; 2208 goto ret; 2209 } 2210 //sc->sc_addr = value; 2211 break; 2212 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2213 if (value != 0 && value != 1) { 2214 err = USBD_IOERROR; 2215 goto ret; 2216 } 2217 sc->sc_conf = value; 2218 break; 2219 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2220 break; 2221 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2222 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2223 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2224 err = USBD_IOERROR; 2225 goto ret; 2226 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2227 break; 2228 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2229 break; 2230 /* Hub requests */ 2231 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2232 break; 2233 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2234 DPRINTFN(4, ("xhci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2235 "port=%d feature=%d\n", 2236 index, value)); 2237 if (index < 1 || index > sc->sc_hs_port_count) { 2238 err = USBD_IOERROR; 2239 goto ret; 2240 } 2241 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2242 v = xhci_op_read_4(sc, port); 2243 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2244 v &= ~XHCI_PS_CLEAR; 2245 switch (value) { 2246 case UHF_PORT_ENABLE: 2247 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2248 break; 2249 case UHF_PORT_SUSPEND: 2250 err = USBD_IOERROR; 2251 goto ret; 2252 case UHF_PORT_POWER: 2253 break; 2254 case UHF_PORT_TEST: 2255 case UHF_PORT_INDICATOR: 2256 err = USBD_IOERROR; 2257 goto ret; 2258 case UHF_C_PORT_CONNECTION: 2259 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2260 break; 2261 case UHF_C_PORT_ENABLE: 2262 case UHF_C_PORT_SUSPEND: 2263 case UHF_C_PORT_OVER_CURRENT: 2264 err = USBD_IOERROR; 2265 goto ret; 2266 case UHF_C_PORT_RESET: 2267 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2268 break; 2269 default: 2270 err = USBD_IOERROR; 2271 goto ret; 2272 } 2273 2274 break; 2275 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2276 if (len == 0) 2277 break; 2278 if ((value & 0xff) != 0) { 2279 err = USBD_IOERROR; 2280 goto ret; 2281 } 2282 hubd = xhci_hubd; 2283 hubd.bNbrPorts = sc->sc_hs_port_count; 2284 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2285 hubd.bPwrOn2PwrGood = 200; 2286 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2287 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2288 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2289 l = min(len, hubd.bDescLength); 2290 totlen = l; 2291 memcpy(buf, &hubd, l); 2292 break; 2293 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2294 if (len != 4) { 2295 err = USBD_IOERROR; 2296 goto ret; 2297 } 2298 memset(buf, 0, len); /* ? XXX */ 2299 totlen = len; 2300 break; 2301 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2302 DPRINTFN(8,("xhci_root_ctrl_start: get port status i=%d\n", 2303 index)); 2304 if (index < 1 || index > sc->sc_maxports) { 2305 err = USBD_IOERROR; 2306 goto ret; 2307 } 2308 if (len != 4) { 2309 err = USBD_IOERROR; 2310 goto ret; 2311 } 2312 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2313 index)); 2314 DPRINTF(("%s READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x\n", 2315 __func__, index, sc->sc_hs_port_start - 1 + index, v)); 2316 switch (XHCI_PS_SPEED_GET(v)) { 2317 case 1: 2318 i = UPS_FULL_SPEED; 2319 break; 2320 case 2: 2321 i = UPS_LOW_SPEED; 2322 break; 2323 case 3: 2324 i = UPS_HIGH_SPEED; 2325 break; 2326 default: 2327 i = 0; 2328 break; 2329 } 2330 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2331 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2332 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2333 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2334 if (v & XHCI_PS_PR) i |= UPS_RESET; 2335 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2336 USETW(ps.wPortStatus, i); 2337 i = 0; 2338 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2339 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2340 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2341 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2342 USETW(ps.wPortChange, i); 2343 l = min(len, sizeof ps); 2344 memcpy(buf, &ps, l); 2345 totlen = l; 2346 break; 2347 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2348 err = USBD_IOERROR; 2349 goto ret; 2350 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2351 break; 2352 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2353 if (index < 1 || index > sc->sc_hs_port_count) { 2354 err = USBD_IOERROR; 2355 goto ret; 2356 } 2357 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2358 v = xhci_op_read_4(sc, port); 2359 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2360 v &= ~XHCI_PS_CLEAR; 2361 switch (value) { 2362 case UHF_PORT_ENABLE: 2363 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2364 break; 2365 case UHF_PORT_SUSPEND: 2366 /* XXX suspend */ 2367 break; 2368 case UHF_PORT_RESET: 2369 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2370 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2371 /* Wait for reset to complete. */ 2372 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2373 if (sc->sc_dying) { 2374 err = USBD_IOERROR; 2375 goto ret; 2376 } 2377 v = xhci_op_read_4(sc, port); 2378 if (v & XHCI_PS_PR) { 2379 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2380 usb_delay_ms(&sc->sc_bus, 10); 2381 /* XXX */ 2382 } 2383 break; 2384 case UHF_PORT_POWER: 2385 /* XXX power control */ 2386 break; 2387 /* XXX more */ 2388 case UHF_C_PORT_RESET: 2389 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2390 break; 2391 default: 2392 err = USBD_IOERROR; 2393 goto ret; 2394 } 2395 break; 2396 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2397 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2398 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2399 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2400 break; 2401 default: 2402 err = USBD_IOERROR; 2403 goto ret; 2404 } 2405 xfer->actlen = totlen; 2406 err = USBD_NORMAL_COMPLETION; 2407 ret: 2408 xfer->status = err; 2409 mutex_enter(&sc->sc_lock); 2410 usb_transfer_complete(xfer); 2411 mutex_exit(&sc->sc_lock); 2412 return USBD_IN_PROGRESS; 2413 } 2414 2415 2416 static void 2417 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2418 { 2419 /* Nothing to do, all transfers are synchronous. */ 2420 } 2421 2422 2423 static void 2424 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2425 { 2426 DPRINTF(("%s\n", __func__)); 2427 /* Nothing to do. */ 2428 } 2429 2430 static void 2431 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2432 { 2433 xfer->hcpriv = NULL; 2434 } 2435 2436 /* root hub intrerrupt */ 2437 2438 static usbd_status 2439 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2440 { 2441 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2442 usbd_status err; 2443 2444 /* Insert last in queue. */ 2445 mutex_enter(&sc->sc_lock); 2446 err = usb_insert_transfer(xfer); 2447 mutex_exit(&sc->sc_lock); 2448 if (err) 2449 return err; 2450 2451 /* Pipe isn't running, start first */ 2452 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2453 } 2454 2455 static usbd_status 2456 xhci_root_intr_start(usbd_xfer_handle xfer) 2457 { 2458 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2459 2460 if (sc->sc_dying) 2461 return USBD_IOERROR; 2462 2463 mutex_enter(&sc->sc_lock); 2464 sc->sc_intrxfer = xfer; 2465 mutex_exit(&sc->sc_lock); 2466 2467 return USBD_IN_PROGRESS; 2468 } 2469 2470 static void 2471 xhci_root_intr_abort(usbd_xfer_handle xfer) 2472 { 2473 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2474 2475 KASSERT(mutex_owned(&sc->sc_lock)); 2476 KASSERT(xfer->pipe->intrxfer == xfer); 2477 2478 DPRINTF(("%s: remove\n", __func__)); 2479 2480 sc->sc_intrxfer = NULL; 2481 2482 xfer->status = USBD_CANCELLED; 2483 usb_transfer_complete(xfer); 2484 } 2485 2486 static void 2487 xhci_root_intr_close(usbd_pipe_handle pipe) 2488 { 2489 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2490 2491 KASSERT(mutex_owned(&sc->sc_lock)); 2492 2493 DPRINTF(("%s\n", __func__)); 2494 2495 sc->sc_intrxfer = NULL; 2496 } 2497 2498 static void 2499 xhci_root_intr_done(usbd_xfer_handle xfer) 2500 { 2501 xfer->hcpriv = NULL; 2502 } 2503 2504 /* -------------- */ 2505 /* device control */ 2506 2507 static usbd_status 2508 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2509 { 2510 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2511 usbd_status err; 2512 2513 /* Insert last in queue. */ 2514 mutex_enter(&sc->sc_lock); 2515 err = usb_insert_transfer(xfer); 2516 mutex_exit(&sc->sc_lock); 2517 if (err) 2518 return (err); 2519 2520 /* Pipe isn't running, start first */ 2521 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2522 } 2523 2524 static usbd_status 2525 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2526 { 2527 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2528 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2529 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2530 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2531 struct xhci_xfer * const xx = (void *)xfer; 2532 usb_device_request_t * const req = &xfer->request; 2533 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2534 const uint32_t len = UGETW(req->wLength); 2535 usb_dma_t * const dma = &xfer->dmabuf; 2536 uint64_t parameter; 2537 uint32_t status; 2538 uint32_t control; 2539 u_int i; 2540 2541 DPRINTF(("%s\n", __func__)); 2542 DPRINTF(("req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2543 req->bRequest, UGETW(req->wValue), UGETW(req->wIndex), 2544 UGETW(req->wLength))); 2545 2546 /* XXX */ 2547 if (tr->is_halted) { 2548 xhci_reset_endpoint(xfer->pipe); 2549 tr->is_halted = false; 2550 xhci_set_dequeue(xfer->pipe); 2551 } 2552 2553 /* we rely on the bottom bits for extra info */ 2554 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2555 2556 KASSERT((xfer->rqflags & URQ_REQUEST) != 0); 2557 2558 i = 0; 2559 2560 /* setup phase */ 2561 memcpy(¶meter, req, sizeof(*req)); 2562 parameter = le64toh(parameter); 2563 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2564 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2565 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2566 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2567 XHCI_TRB_3_IDT_BIT; 2568 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2569 2570 if (len == 0) 2571 goto no_data; 2572 2573 /* data phase */ 2574 parameter = DMAADDR(dma, 0); 2575 KASSERT(len <= 0x10000); 2576 status = XHCI_TRB_2_IRQ_SET(0) | 2577 XHCI_TRB_2_TDSZ_SET(1) | 2578 XHCI_TRB_2_BYTES_SET(len); 2579 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2580 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2581 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2582 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2583 2584 parameter = (uintptr_t)xfer | 0x3; 2585 status = XHCI_TRB_2_IRQ_SET(0); 2586 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2587 XHCI_TRB_3_IOC_BIT; 2588 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2589 2590 no_data: 2591 parameter = 0; 2592 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_TDSZ_SET(1); 2593 /* the status stage has inverted direction */ 2594 control = (isread ? 0 : XHCI_TRB_3_DIR_IN) | 2595 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2596 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2597 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2598 2599 parameter = (uintptr_t)xfer | 0x0; 2600 status = XHCI_TRB_2_IRQ_SET(0); 2601 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2602 XHCI_TRB_3_IOC_BIT; 2603 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2604 2605 mutex_enter(&tr->xr_lock); 2606 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2607 mutex_exit(&tr->xr_lock); 2608 2609 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2610 2611 if (xfer->timeout && !sc->sc_bus.use_polling) { 2612 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2613 xhci_timeout, xfer); 2614 } 2615 2616 if (sc->sc_bus.use_polling) { 2617 device_printf(sc->sc_dev, "%s polling\n", __func__); 2618 //xhci_waitintr(sc, xfer); 2619 } 2620 2621 return USBD_IN_PROGRESS; 2622 } 2623 2624 static void 2625 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2626 { 2627 DPRINTF(("%s\n", __func__)); 2628 2629 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2630 2631 } 2632 2633 static void 2634 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2635 { 2636 DPRINTF(("%s\n", __func__)); 2637 } 2638 2639 static void 2640 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2641 { 2642 DPRINTF(("%s\n", __func__)); 2643 } 2644 2645 /* ----------------- */ 2646 /* device isochronus */ 2647 2648 /* ----------- */ 2649 /* device bulk */ 2650 2651 static usbd_status 2652 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2653 { 2654 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2655 usbd_status err; 2656 2657 /* Insert last in queue. */ 2658 mutex_enter(&sc->sc_lock); 2659 err = usb_insert_transfer(xfer); 2660 mutex_exit(&sc->sc_lock); 2661 if (err) 2662 return err; 2663 2664 /* 2665 * Pipe isn't running (otherwise err would be USBD_INPROG), 2666 * so start it first. 2667 */ 2668 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2669 } 2670 2671 static usbd_status 2672 xhci_device_bulk_start(usbd_xfer_handle xfer) 2673 { 2674 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2675 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2676 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2677 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2678 struct xhci_xfer * const xx = (void *)xfer; 2679 const uint32_t len = xfer->length; 2680 usb_dma_t * const dma = &xfer->dmabuf; 2681 uint64_t parameter; 2682 uint32_t status; 2683 uint32_t control; 2684 u_int i = 0; 2685 2686 #if 0 2687 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2688 xs->xs_idx, dci); 2689 #endif 2690 2691 if (sc->sc_dying) 2692 return USBD_IOERROR; 2693 2694 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2695 2696 parameter = DMAADDR(dma, 0); 2697 /* 2698 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 2699 * If the user supplied buffer crosses such a boundary then 2 2700 * (or more) TRB should be used. 2701 * If multiple TRB are used the td_size field must be set correctly. 2702 * For v1.0 devices (like ivy bridge) this is the number of usb data 2703 * blocks needed to complete the transfer. 2704 * Setting it to 1 in the last TRB causes an extra zero-length 2705 * data block be sent. 2706 * The earlier documentation differs, I don't know how it behaves. 2707 */ 2708 KASSERT(len <= 0x10000); 2709 status = XHCI_TRB_2_IRQ_SET(0) | 2710 XHCI_TRB_2_TDSZ_SET(1) | 2711 XHCI_TRB_2_BYTES_SET(len); 2712 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2713 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2714 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2715 2716 mutex_enter(&tr->xr_lock); 2717 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2718 mutex_exit(&tr->xr_lock); 2719 2720 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2721 2722 if (sc->sc_bus.use_polling) { 2723 device_printf(sc->sc_dev, "%s polling\n", __func__); 2724 //xhci_waitintr(sc, xfer); 2725 } 2726 2727 return USBD_IN_PROGRESS; 2728 } 2729 2730 static void 2731 xhci_device_bulk_done(usbd_xfer_handle xfer) 2732 { 2733 //struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2734 //struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2735 //const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2736 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2737 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2738 2739 DPRINTF(("%s\n", __func__)); 2740 2741 #if 0 2742 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2743 xs->xs_idx, dci); 2744 #endif 2745 2746 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2747 2748 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2749 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2750 2751 2752 } 2753 2754 static void 2755 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2756 { 2757 DPRINTF(("%s\n", __func__)); 2758 } 2759 2760 static void 2761 xhci_device_bulk_close(usbd_pipe_handle pipe) 2762 { 2763 DPRINTF(("%s\n", __func__)); 2764 } 2765 2766 /* --------------- */ 2767 /* device intrrupt */ 2768 2769 static usbd_status 2770 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2771 { 2772 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2773 usbd_status err; 2774 2775 /* Insert last in queue. */ 2776 mutex_enter(&sc->sc_lock); 2777 err = usb_insert_transfer(xfer); 2778 mutex_exit(&sc->sc_lock); 2779 if (err) 2780 return err; 2781 2782 /* 2783 * Pipe isn't running (otherwise err would be USBD_INPROG), 2784 * so start it first. 2785 */ 2786 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2787 } 2788 2789 static usbd_status 2790 xhci_device_intr_start(usbd_xfer_handle xfer) 2791 { 2792 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2793 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2794 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2795 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2796 struct xhci_xfer * const xx = (void *)xfer; 2797 const uint32_t len = xfer->length; 2798 usb_dma_t * const dma = &xfer->dmabuf; 2799 uint64_t parameter; 2800 uint32_t status; 2801 uint32_t control; 2802 u_int i = 0; 2803 2804 #if 0 2805 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2806 xs->xs_idx, dci); 2807 #endif 2808 2809 if (sc->sc_dying) 2810 return USBD_IOERROR; 2811 2812 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2813 2814 parameter = DMAADDR(dma, 0); 2815 KASSERT(len <= 0x10000); 2816 status = XHCI_TRB_2_IRQ_SET(0) | 2817 XHCI_TRB_2_TDSZ_SET(1) | 2818 XHCI_TRB_2_BYTES_SET(len); 2819 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2820 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2821 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2822 2823 mutex_enter(&tr->xr_lock); 2824 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2825 mutex_exit(&tr->xr_lock); 2826 2827 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2828 2829 if (sc->sc_bus.use_polling) { 2830 #ifdef XHCI_DEBUG 2831 device_printf(sc->sc_dev, "%s polling\n", __func__); 2832 #endif 2833 //xhci_waitintr(sc, xfer); 2834 } 2835 2836 return USBD_IN_PROGRESS; 2837 } 2838 2839 static void 2840 xhci_device_intr_done(usbd_xfer_handle xfer) 2841 { 2842 struct xhci_softc * const sc __diagused = 2843 xfer->pipe->device->bus->hci_private; 2844 #ifdef XHCI_DEBUG 2845 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2846 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2847 #endif 2848 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2849 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2850 DPRINTF(("%s\n", __func__)); 2851 2852 #ifdef XHCI_DEBUG 2853 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2854 xs->xs_idx, dci); 2855 #endif 2856 2857 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2858 2859 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2860 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2861 2862 #if 0 2863 device_printf(sc->sc_dev, ""); 2864 for (size_t i = 0; i < xfer->length; i++) { 2865 printf(" %02x", ((uint8_t const *)xfer->buffer)[i]); 2866 } 2867 printf("\n"); 2868 #endif 2869 2870 if (xfer->pipe->repeat) { 2871 xfer->status = xhci_device_intr_start(xfer); 2872 } else { 2873 callout_stop(&xfer->timeout_handle); /* XXX */ 2874 } 2875 2876 } 2877 2878 static void 2879 xhci_device_intr_abort(usbd_xfer_handle xfer) 2880 { 2881 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2882 DPRINTF(("%s\n", __func__)); 2883 2884 KASSERT(mutex_owned(&sc->sc_lock)); 2885 device_printf(sc->sc_dev, "%s %p\n", __func__, xfer); 2886 KASSERT(xfer->pipe->intrxfer == xfer); 2887 xfer->status = USBD_CANCELLED; 2888 usb_transfer_complete(xfer); 2889 } 2890 2891 static void 2892 xhci_device_intr_close(usbd_pipe_handle pipe) 2893 { 2894 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2895 DPRINTF(("%s\n", __func__)); 2896 device_printf(sc->sc_dev, "%s %p\n", __func__, pipe); 2897 xhci_unconfigure_endpoint(pipe); 2898 } 2899 2900 /* ------------ */ 2901 2902 static void 2903 xhci_timeout(void *addr) 2904 { 2905 struct xhci_xfer * const xx = addr; 2906 usbd_xfer_handle const xfer = &xx->xx_xfer; 2907 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2908 2909 if (sc->sc_dying) { 2910 return; 2911 } 2912 2913 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2914 USB_TASKQ_MPSAFE); 2915 usb_add_task(xx->xx_xfer.pipe->device, &xx->xx_abort_task, 2916 USB_TASKQ_HC); 2917 } 2918 2919 static void 2920 xhci_timeout_task(void *addr) 2921 { 2922 usbd_xfer_handle const xfer = addr; 2923 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2924 2925 mutex_enter(&sc->sc_lock); 2926 #if 0 2927 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2928 #else 2929 xfer->status = USBD_TIMEOUT; 2930 usb_transfer_complete(xfer); 2931 #endif 2932 mutex_exit(&sc->sc_lock); 2933 } 2934
Indexes created Wed Oct 01 18:09:54 GMT 2025