xhci.c revision 1.23.2.4
1 /* $NetBSD: xhci.c,v 1.23.2.4 2016/02/06 20:58:13 snj Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.23.2.4 2016/02/06 20:58:13 snj Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/kmem.h> 36 #include <sys/malloc.h> 37 #include <sys/device.h> 38 #include <sys/select.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 #include <sys/cpu.h> 45 46 #include <machine/endian.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 #include <dev/usb/usb_quirks.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 #include <dev/usb/usbroothub_subr.h> 57 58 #ifdef XHCI_DEBUG 59 int xhcidebug = 0; 60 #define DPRINTF(x) do { if (xhcidebug) printf x; } while(0) 61 #define DPRINTFN(n,x) do { if (xhcidebug>(n)) printf x; } while (0) 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #define XHCI_DCI_SLOT 0 68 #define XHCI_DCI_EP_CONTROL 1 69 70 #define XHCI_ICI_INPUT_CONTROL 0 71 72 struct xhci_pipe { 73 struct usbd_pipe xp_pipe; 74 }; 75 76 #define XHCI_INTR_ENDPT 1 77 #define XHCI_COMMAND_RING_TRBS 256 78 #define XHCI_EVENT_RING_TRBS 256 79 #define XHCI_EVENT_RING_SEGMENTS 1 80 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 81 82 static usbd_status xhci_open(usbd_pipe_handle); 83 static int xhci_intr1(struct xhci_softc * const); 84 static void xhci_softintr(void *); 85 static void xhci_poll(struct usbd_bus *); 86 static usbd_status xhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 87 static void xhci_freem(struct usbd_bus *, usb_dma_t *); 88 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 89 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 90 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 91 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 92 struct usbd_port *); 93 94 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 95 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 96 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 97 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 98 99 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 100 101 static usbd_status xhci_do_command(struct xhci_softc * const, 102 struct xhci_trb * const, int); 103 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 104 int, int, int, int); 105 static usbd_status xhci_enable_slot(struct xhci_softc * const, 106 uint8_t * const); 107 static usbd_status xhci_address_device(struct xhci_softc * const, 108 uint64_t, uint8_t, bool); 109 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 110 struct xhci_slot * const, u_int); 111 static usbd_status xhci_ring_init(struct xhci_softc * const, 112 struct xhci_ring * const, size_t, size_t); 113 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 114 115 static void xhci_noop(usbd_pipe_handle); 116 117 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 118 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 119 static void xhci_root_ctrl_abort(usbd_xfer_handle); 120 static void xhci_root_ctrl_close(usbd_pipe_handle); 121 static void xhci_root_ctrl_done(usbd_xfer_handle); 122 123 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 124 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 125 static void xhci_root_intr_abort(usbd_xfer_handle); 126 static void xhci_root_intr_close(usbd_pipe_handle); 127 static void xhci_root_intr_done(usbd_xfer_handle); 128 129 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 130 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 131 static void xhci_device_ctrl_abort(usbd_xfer_handle); 132 static void xhci_device_ctrl_close(usbd_pipe_handle); 133 static void xhci_device_ctrl_done(usbd_xfer_handle); 134 135 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 136 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 137 static void xhci_device_intr_abort(usbd_xfer_handle); 138 static void xhci_device_intr_close(usbd_pipe_handle); 139 static void xhci_device_intr_done(usbd_xfer_handle); 140 141 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 142 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 143 static void xhci_device_bulk_abort(usbd_xfer_handle); 144 static void xhci_device_bulk_close(usbd_pipe_handle); 145 static void xhci_device_bulk_done(usbd_xfer_handle); 146 147 static void xhci_timeout(void *); 148 static void xhci_timeout_task(void *); 149 150 static const struct usbd_bus_methods xhci_bus_methods = { 151 .open_pipe = xhci_open, 152 .soft_intr = xhci_softintr, 153 .do_poll = xhci_poll, 154 .allocm = xhci_allocm, 155 .freem = xhci_freem, 156 .allocx = xhci_allocx, 157 .freex = xhci_freex, 158 .get_lock = xhci_get_lock, 159 .new_device = xhci_new_device, 160 }; 161 162 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 163 .transfer = xhci_root_ctrl_transfer, 164 .start = xhci_root_ctrl_start, 165 .abort = xhci_root_ctrl_abort, 166 .close = xhci_root_ctrl_close, 167 .cleartoggle = xhci_noop, 168 .done = xhci_root_ctrl_done, 169 }; 170 171 static const struct usbd_pipe_methods xhci_root_intr_methods = { 172 .transfer = xhci_root_intr_transfer, 173 .start = xhci_root_intr_start, 174 .abort = xhci_root_intr_abort, 175 .close = xhci_root_intr_close, 176 .cleartoggle = xhci_noop, 177 .done = xhci_root_intr_done, 178 }; 179 180 181 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 182 .transfer = xhci_device_ctrl_transfer, 183 .start = xhci_device_ctrl_start, 184 .abort = xhci_device_ctrl_abort, 185 .close = xhci_device_ctrl_close, 186 .cleartoggle = xhci_noop, 187 .done = xhci_device_ctrl_done, 188 }; 189 190 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 191 .cleartoggle = xhci_noop, 192 }; 193 194 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 195 .transfer = xhci_device_bulk_transfer, 196 .start = xhci_device_bulk_start, 197 .abort = xhci_device_bulk_abort, 198 .close = xhci_device_bulk_close, 199 .cleartoggle = xhci_noop, 200 .done = xhci_device_bulk_done, 201 }; 202 203 static const struct usbd_pipe_methods xhci_device_intr_methods = { 204 .transfer = xhci_device_intr_transfer, 205 .start = xhci_device_intr_start, 206 .abort = xhci_device_intr_abort, 207 .close = xhci_device_intr_close, 208 .cleartoggle = xhci_noop, 209 .done = xhci_device_intr_done, 210 }; 211 212 static inline uint32_t 213 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 214 { 215 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 216 } 217 218 #if 0 /* unused */ 219 static inline void 220 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 221 uint32_t value) 222 { 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 224 } 225 #endif /* unused */ 226 227 static inline uint32_t 228 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 229 { 230 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 231 } 232 233 static inline uint32_t 234 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 235 { 236 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 237 } 238 239 static inline void 240 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 241 uint32_t value) 242 { 243 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 244 } 245 246 #if 0 /* unused */ 247 static inline uint64_t 248 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 249 { 250 uint64_t value; 251 252 if (sc->sc_ac64) { 253 #ifdef XHCI_USE_BUS_SPACE_8 254 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 255 #else 256 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 257 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 258 offset + 4) << 32; 259 #endif 260 } else { 261 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 262 } 263 264 return value; 265 } 266 #endif /* unused */ 267 268 static inline void 269 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 270 uint64_t value) 271 { 272 if (sc->sc_ac64) { 273 #ifdef XHCI_USE_BUS_SPACE_8 274 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 275 #else 276 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 277 (value >> 0) & 0xffffffff); 278 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 279 (value >> 32) & 0xffffffff); 280 #endif 281 } else { 282 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 283 } 284 } 285 286 static inline uint32_t 287 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 288 { 289 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 290 } 291 292 static inline void 293 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 294 uint32_t value) 295 { 296 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 297 } 298 299 #if 0 /* unused */ 300 static inline uint64_t 301 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 302 { 303 uint64_t value; 304 305 if (sc->sc_ac64) { 306 #ifdef XHCI_USE_BUS_SPACE_8 307 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 308 #else 309 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 310 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 311 offset + 4) << 32; 312 #endif 313 } else { 314 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 315 } 316 317 return value; 318 } 319 #endif /* unused */ 320 321 static inline void 322 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 336 } 337 } 338 339 #if 0 /* unused */ 340 static inline uint32_t 341 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 342 { 343 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 344 } 345 #endif /* unused */ 346 347 static inline void 348 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 349 uint32_t value) 350 { 351 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 352 } 353 354 /* --- */ 355 356 static inline uint8_t 357 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 358 { 359 u_int eptype; 360 361 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 362 case UE_CONTROL: 363 eptype = 0x0; 364 break; 365 case UE_ISOCHRONOUS: 366 eptype = 0x1; 367 break; 368 case UE_BULK: 369 eptype = 0x2; 370 break; 371 case UE_INTERRUPT: 372 eptype = 0x3; 373 break; 374 } 375 376 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 377 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 378 return eptype | 0x4; 379 else 380 return eptype; 381 } 382 383 static u_int 384 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 385 { 386 /* xHCI 1.0 section 4.5.1 */ 387 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 388 u_int in = 0; 389 390 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 391 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 392 in = 1; 393 394 return epaddr * 2 + in; 395 } 396 397 static inline u_int 398 xhci_dci_to_ici(const u_int i) 399 { 400 return i + 1; 401 } 402 403 static inline void * 404 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 405 const u_int dci) 406 { 407 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 408 } 409 410 #if 0 /* unused */ 411 static inline bus_addr_t 412 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 413 const u_int dci) 414 { 415 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 416 } 417 #endif /* unused */ 418 419 static inline void * 420 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 421 const u_int ici) 422 { 423 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 424 } 425 426 static inline bus_addr_t 427 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 428 const u_int ici) 429 { 430 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 431 } 432 433 static inline struct xhci_trb * 434 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 435 { 436 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 437 } 438 439 static inline bus_addr_t 440 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 441 { 442 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 443 } 444 445 static inline void 446 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 447 uint32_t control) 448 { 449 trb->trb_0 = parameter; 450 trb->trb_2 = status; 451 trb->trb_3 = control; 452 } 453 454 /* --- */ 455 456 void 457 xhci_childdet(device_t self, device_t child) 458 { 459 struct xhci_softc * const sc = device_private(self); 460 461 KASSERT(sc->sc_child == child); 462 if (child == sc->sc_child) 463 sc->sc_child = NULL; 464 } 465 466 int 467 xhci_detach(struct xhci_softc *sc, int flags) 468 { 469 int rv = 0; 470 471 if (sc->sc_child != NULL) 472 rv = config_detach(sc->sc_child, flags); 473 474 if (rv != 0) 475 return (rv); 476 477 /* XXX unconfigure/free slots */ 478 479 /* verify: */ 480 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 481 xhci_op_write_4(sc, XHCI_USBCMD, 0); 482 /* do we need to wait for stop? */ 483 484 xhci_op_write_8(sc, XHCI_CRCR, 0); 485 xhci_ring_free(sc, &sc->sc_cr); 486 cv_destroy(&sc->sc_command_cv); 487 488 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 489 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 490 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 491 xhci_ring_free(sc, &sc->sc_er); 492 493 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 494 495 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 496 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 497 498 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 499 500 mutex_destroy(&sc->sc_lock); 501 mutex_destroy(&sc->sc_intr_lock); 502 503 pool_cache_destroy(sc->sc_xferpool); 504 505 return rv; 506 } 507 508 int 509 xhci_activate(device_t self, enum devact act) 510 { 511 struct xhci_softc * const sc = device_private(self); 512 513 switch (act) { 514 case DVACT_DEACTIVATE: 515 sc->sc_dying = true; 516 return 0; 517 default: 518 return EOPNOTSUPP; 519 } 520 } 521 522 bool 523 xhci_suspend(device_t dv, const pmf_qual_t *qual) 524 { 525 return false; 526 } 527 528 bool 529 xhci_resume(device_t dv, const pmf_qual_t *qual) 530 { 531 return false; 532 } 533 534 bool 535 xhci_shutdown(device_t self, int flags) 536 { 537 return false; 538 } 539 540 541 static void 542 hexdump(const char *msg, const void *base, size_t len) 543 { 544 #if 0 545 size_t cnt; 546 const uint32_t *p; 547 extern paddr_t vtophys(vaddr_t); 548 549 p = base; 550 cnt = 0; 551 552 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 553 (void *)vtophys((vaddr_t)base)); 554 555 while (cnt < len) { 556 if (cnt % 16 == 0) 557 printf("%p: ", p); 558 else if (cnt % 8 == 0) 559 printf(" |"); 560 printf(" %08x", *p++); 561 cnt += 4; 562 if (cnt % 16 == 0) 563 printf("\n"); 564 } 565 #endif 566 } 567 568 569 int 570 xhci_init(struct xhci_softc *sc) 571 { 572 bus_size_t bsz; 573 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 574 uint32_t ecp, ecr; 575 uint32_t usbcmd, usbsts, pagesize, config; 576 int i; 577 uint16_t hciversion; 578 uint8_t caplength; 579 580 DPRINTF(("%s\n", __func__)); 581 582 /* XXX Low/Full/High speeds for now */ 583 sc->sc_bus.usbrev = USBREV_2_0; 584 585 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 586 caplength = XHCI_CAP_CAPLENGTH(cap); 587 hciversion = XHCI_CAP_HCIVERSION(cap); 588 589 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 590 aprint_normal_dev(sc->sc_dev, 591 "xHCI version %x.%x not known to be supported\n", 592 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 593 } else { 594 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 595 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 596 } 597 598 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 599 &sc->sc_cbh) != 0) { 600 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 601 return ENOMEM; 602 } 603 604 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 605 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 606 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 607 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 608 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 609 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 610 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 611 612 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 613 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 614 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 615 sc->sc_ctxsz); 616 617 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 618 ecp = XHCI_HCC_XECP(hcc) * 4; 619 while (ecp != 0) { 620 ecr = xhci_read_4(sc, ecp); 621 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 622 switch (XHCI_XECP_ID(ecr)) { 623 case XHCI_ID_PROTOCOLS: { 624 uint32_t w0, w4, w8; 625 uint16_t w2; 626 w0 = xhci_read_4(sc, ecp + 0); 627 w2 = (w0 >> 16) & 0xffff; 628 w4 = xhci_read_4(sc, ecp + 4); 629 w8 = xhci_read_4(sc, ecp + 8); 630 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 631 w0, w4, w8); 632 if (w4 == 0x20425355 && w2 == 0x0300) { 633 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 634 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 635 } 636 if (w4 == 0x20425355 && w2 == 0x0200) { 637 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 638 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 639 } 640 break; 641 } 642 default: 643 break; 644 } 645 ecr = xhci_read_4(sc, ecp); 646 if (XHCI_XECP_NEXT(ecr) == 0) { 647 ecp = 0; 648 } else { 649 ecp += XHCI_XECP_NEXT(ecr) * 4; 650 } 651 } 652 653 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 654 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 655 &sc->sc_obh) != 0) { 656 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 657 return ENOMEM; 658 } 659 660 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 661 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 662 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 663 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 664 return ENOMEM; 665 } 666 667 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 668 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 669 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 670 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 671 return ENOMEM; 672 } 673 674 for (i = 0; i < 100; i++) { 675 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 676 if ((usbsts & XHCI_STS_CNR) == 0) 677 break; 678 usb_delay_ms(&sc->sc_bus, 1); 679 } 680 if (i >= 100) 681 return EIO; 682 683 usbcmd = 0; 684 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 685 usb_delay_ms(&sc->sc_bus, 1); 686 687 usbcmd = XHCI_CMD_HCRST; 688 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 689 for (i = 0; i < 100; i++) { 690 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 691 if ((usbcmd & XHCI_CMD_HCRST) == 0) 692 break; 693 usb_delay_ms(&sc->sc_bus, 1); 694 } 695 if (i >= 100) 696 return EIO; 697 698 for (i = 0; i < 100; i++) { 699 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 700 if ((usbsts & XHCI_STS_CNR) == 0) 701 break; 702 usb_delay_ms(&sc->sc_bus, 1); 703 } 704 if (i >= 100) 705 return EIO; 706 707 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 708 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 709 pagesize = ffs(pagesize); 710 if (pagesize == 0) 711 return EIO; 712 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 713 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 714 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 715 (uint32_t)sc->sc_maxslots); 716 717 usbd_status err; 718 719 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 720 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 721 if (sc->sc_maxspbuf != 0) { 722 err = usb_allocmem(&sc->sc_bus, 723 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 724 &sc->sc_spbufarray_dma); 725 if (err) 726 return err; 727 728 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 729 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 730 for (i = 0; i < sc->sc_maxspbuf; i++) { 731 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 732 /* allocate contexts */ 733 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 734 sc->sc_pgsz, dma); 735 if (err) 736 return err; 737 spbufarray[i] = htole64(DMAADDR(dma, 0)); 738 usb_syncmem(dma, 0, sc->sc_pgsz, 739 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 740 } 741 742 usb_syncmem(&sc->sc_spbufarray_dma, 0, 743 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 744 } 745 746 config = xhci_op_read_4(sc, XHCI_CONFIG); 747 config &= ~0xFF; 748 config |= sc->sc_maxslots & 0xFF; 749 xhci_op_write_4(sc, XHCI_CONFIG, config); 750 751 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 752 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 753 if (err) { 754 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 755 return err; 756 } 757 758 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 759 XHCI_EVENT_RING_SEGMENTS_ALIGN); 760 if (err) { 761 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 762 return err; 763 } 764 765 usb_dma_t *dma; 766 size_t size; 767 size_t align; 768 769 dma = &sc->sc_eventst_dma; 770 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 771 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 772 KASSERT(size <= (512 * 1024)); 773 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 774 err = usb_allocmem(&sc->sc_bus, size, align, dma); 775 776 memset(KERNADDR(dma, 0), 0, size); 777 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 778 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 779 usbd_errstr(err), 780 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 781 KERNADDR(&sc->sc_eventst_dma, 0), 782 sc->sc_eventst_dma.block->size); 783 784 dma = &sc->sc_dcbaa_dma; 785 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 786 KASSERT(size <= 2048); 787 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 788 err = usb_allocmem(&sc->sc_bus, size, align, dma); 789 790 memset(KERNADDR(dma, 0), 0, size); 791 if (sc->sc_maxspbuf != 0) { 792 /* 793 * DCBA entry 0 hold the scratchbuf array pointer. 794 */ 795 *(uint64_t *)KERNADDR(dma, 0) = 796 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 797 } 798 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 799 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 800 usbd_errstr(err), 801 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 802 KERNADDR(&sc->sc_dcbaa_dma, 0), 803 sc->sc_dcbaa_dma.block->size); 804 805 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 806 KM_SLEEP); 807 808 cv_init(&sc->sc_command_cv, "xhcicmd"); 809 810 struct xhci_erste *erst; 811 erst = KERNADDR(&sc->sc_eventst_dma, 0); 812 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 813 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 814 erst[0].erste_3 = htole32(0); 815 usb_syncmem(&sc->sc_eventst_dma, 0, 816 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 817 818 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 819 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 820 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 821 XHCI_ERDP_LO_BUSY); 822 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 823 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 824 sc->sc_cr.xr_cs); 825 826 #if 0 827 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 828 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 829 #endif 830 831 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 832 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 833 834 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 835 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 836 xhci_op_read_4(sc, XHCI_USBCMD)); 837 838 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 839 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 840 cv_init(&sc->sc_softwake_cv, "xhciab"); 841 842 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 843 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 844 845 /* Set up the bus struct. */ 846 sc->sc_bus.methods = &xhci_bus_methods; 847 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 848 849 return USBD_NORMAL_COMPLETION; 850 } 851 852 int 853 xhci_intr(void *v) 854 { 855 struct xhci_softc * const sc = v; 856 int ret = 0; 857 858 if (sc == NULL) 859 return 0; 860 861 mutex_spin_enter(&sc->sc_intr_lock); 862 863 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 864 goto done; 865 866 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 867 868 /* If we get an interrupt while polling, then just ignore it. */ 869 if (sc->sc_bus.use_polling) { 870 #ifdef DIAGNOSTIC 871 DPRINTFN(16, ("xhci_intr: ignored interrupt while polling\n")); 872 #endif 873 goto done; 874 } 875 876 ret = xhci_intr1(sc); 877 done: 878 mutex_spin_exit(&sc->sc_intr_lock); 879 return ret; 880 } 881 882 int 883 xhci_intr1(struct xhci_softc * const sc) 884 { 885 uint32_t usbsts; 886 uint32_t iman; 887 888 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 889 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 890 #if 0 891 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 892 return 0; 893 } 894 #endif 895 xhci_op_write_4(sc, XHCI_USBSTS, 896 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 897 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 898 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 899 900 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 901 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 902 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 903 return 0; 904 } 905 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 906 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 907 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 908 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 909 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 910 911 sc->sc_bus.no_intrs++; 912 usb_schedsoftintr(&sc->sc_bus); 913 914 return 1; 915 } 916 917 static usbd_status 918 xhci_configure_endpoint(usbd_pipe_handle pipe) 919 { 920 struct xhci_softc * const sc = pipe->device->bus->hci_private; 921 struct xhci_slot * const xs = pipe->device->hci_private; 922 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 923 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 924 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 925 struct xhci_trb trb; 926 usbd_status err; 927 uint32_t *cp; 928 929 device_printf(sc->sc_dev, "%s dci %u (0x%x)\n", __func__, dci, 930 pipe->endpoint->edesc->bEndpointAddress); 931 932 /* XXX ensure input context is available? */ 933 934 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 935 936 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 937 cp[0] = htole32(0); 938 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 939 940 /* set up input slot context */ 941 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 942 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 943 cp[1] = htole32(0); 944 cp[2] = htole32(0); 945 cp[3] = htole32(0); 946 947 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 948 if (xfertype == UE_INTERRUPT) { 949 cp[0] = htole32( 950 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 951 ); 952 cp[1] = htole32( 953 XHCI_EPCTX_1_CERR_SET(3) | 954 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 955 XHCI_EPCTX_1_MAXB_SET(0) | 956 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 957 ); 958 cp[4] = htole32( 959 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 960 ); 961 } else { 962 cp[0] = htole32(0); 963 cp[1] = htole32( 964 XHCI_EPCTX_1_CERR_SET(3) | 965 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 966 XHCI_EPCTX_1_MAXB_SET(0) | 967 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 968 ); 969 } 970 *(uint64_t *)(&cp[2]) = htole64( 971 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 972 XHCI_EPCTX_2_DCS_SET(1)); 973 974 /* sync input contexts before they are read from memory */ 975 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 976 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 977 sc->sc_ctxsz * 1); 978 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 979 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 980 981 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 982 trb.trb_2 = 0; 983 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 984 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 985 986 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 987 988 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 989 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 990 sc->sc_ctxsz * 1); 991 992 return err; 993 } 994 995 static usbd_status 996 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 997 { 998 return USBD_NORMAL_COMPLETION; 999 } 1000 1001 static usbd_status 1002 xhci_reset_endpoint(usbd_pipe_handle pipe) 1003 { 1004 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1005 struct xhci_slot * const xs = pipe->device->hci_private; 1006 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1007 struct xhci_trb trb; 1008 usbd_status err; 1009 1010 device_printf(sc->sc_dev, "%s\n", __func__); 1011 1012 trb.trb_0 = 0; 1013 trb.trb_2 = 0; 1014 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1015 XHCI_TRB_3_EP_SET(dci) | 1016 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1017 1018 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1019 1020 return err; 1021 } 1022 1023 #if 0 1024 static usbd_status 1025 xhci_stop_endpoint(usbd_pipe_handle pipe) 1026 { 1027 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1028 struct xhci_slot * const xs = pipe->device->hci_private; 1029 struct xhci_trb trb; 1030 usbd_status err; 1031 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1032 1033 device_printf(sc->sc_dev, "%s\n", __func__); 1034 1035 trb.trb_0 = 0; 1036 trb.trb_2 = 0; 1037 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1038 XHCI_TRB_3_EP_SET(dci) | 1039 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1040 1041 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1042 1043 return err; 1044 } 1045 #endif 1046 1047 static usbd_status 1048 xhci_set_dequeue(usbd_pipe_handle pipe) 1049 { 1050 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1051 struct xhci_slot * const xs = pipe->device->hci_private; 1052 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1053 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1054 struct xhci_trb trb; 1055 usbd_status err; 1056 1057 device_printf(sc->sc_dev, "%s\n", __func__); 1058 1059 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1060 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1061 BUS_DMASYNC_PREWRITE); 1062 1063 xr->xr_ep = 0; 1064 xr->xr_cs = 1; 1065 1066 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1067 trb.trb_2 = 0; 1068 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1069 XHCI_TRB_3_EP_SET(dci) | 1070 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1071 1072 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1073 1074 return err; 1075 } 1076 1077 static usbd_status 1078 xhci_open(usbd_pipe_handle pipe) 1079 { 1080 usbd_device_handle const dev = pipe->device; 1081 struct xhci_softc * const sc = dev->bus->hci_private; 1082 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 1083 const int8_t addr = dev->address; 1084 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1085 1086 DPRINTF(("%s\n", __func__)); 1087 DPRINTF(("addr %d\n", addr)); 1088 device_printf(sc->sc_dev, "%s addr %d depth %d port %d speed %d\n", 1089 __func__, addr, dev->depth, dev->powersrc->portno, dev->speed); 1090 1091 if (sc->sc_dying) 1092 return USBD_IOERROR; 1093 1094 /* Root Hub */ 1095 if (dev->depth == 0 && dev->powersrc->portno == 0 && 1096 dev->speed != USB_SPEED_SUPER) { 1097 switch (ed->bEndpointAddress) { 1098 case USB_CONTROL_ENDPOINT: 1099 pipe->methods = &xhci_root_ctrl_methods; 1100 break; 1101 case UE_DIR_IN | XHCI_INTR_ENDPT: 1102 pipe->methods = &xhci_root_intr_methods; 1103 break; 1104 default: 1105 pipe->methods = NULL; 1106 DPRINTF(("xhci_open: bad bEndpointAddress 0x%02x\n", 1107 ed->bEndpointAddress)); 1108 return USBD_INVAL; 1109 } 1110 return USBD_NORMAL_COMPLETION; 1111 } 1112 1113 switch (xfertype) { 1114 case UE_CONTROL: 1115 pipe->methods = &xhci_device_ctrl_methods; 1116 break; 1117 case UE_ISOCHRONOUS: 1118 pipe->methods = &xhci_device_isoc_methods; 1119 return USBD_INVAL; 1120 break; 1121 case UE_BULK: 1122 pipe->methods = &xhci_device_bulk_methods; 1123 break; 1124 case UE_INTERRUPT: 1125 pipe->methods = &xhci_device_intr_methods; 1126 break; 1127 default: 1128 return USBD_IOERROR; 1129 break; 1130 } 1131 1132 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1133 xhci_configure_endpoint(pipe); 1134 1135 return USBD_NORMAL_COMPLETION; 1136 } 1137 1138 static void 1139 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1140 { 1141 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1142 uint8_t *p; 1143 1144 device_printf(sc->sc_dev, "port %u status change\n", port); 1145 1146 if (xfer == NULL) 1147 return; 1148 1149 if (!(port >= sc->sc_hs_port_start && 1150 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1151 return; 1152 1153 port -= sc->sc_hs_port_start; 1154 port += 1; 1155 device_printf(sc->sc_dev, "hs port %u status change\n", port); 1156 1157 p = KERNADDR(&xfer->dmabuf, 0); 1158 memset(p, 0, xfer->length); 1159 p[port/NBBY] |= 1 << (port%NBBY); 1160 xfer->actlen = xfer->length; 1161 xfer->status = USBD_NORMAL_COMPLETION; 1162 usb_transfer_complete(xfer); 1163 } 1164 1165 static void 1166 xhci_handle_event(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1167 { 1168 uint64_t trb_0; 1169 uint32_t trb_2, trb_3; 1170 1171 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1172 1173 trb_0 = le64toh(trb->trb_0); 1174 trb_2 = le32toh(trb->trb_2); 1175 trb_3 = le32toh(trb->trb_3); 1176 1177 #if 0 1178 device_printf(sc->sc_dev, 1179 "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", trb, 1180 trb_0, trb_2, trb_3); 1181 #endif 1182 1183 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1184 case XHCI_TRB_EVENT_TRANSFER: { 1185 u_int slot, dci; 1186 struct xhci_slot *xs; 1187 struct xhci_ring *xr; 1188 struct xhci_xfer *xx; 1189 usbd_xfer_handle xfer; 1190 usbd_status err; 1191 1192 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1193 dci = XHCI_TRB_3_EP_GET(trb_3); 1194 1195 xs = &sc->sc_slots[slot]; 1196 xr = &xs->xs_ep[dci].xe_tr; 1197 1198 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1199 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1200 sizeof(struct xhci_trb)]; 1201 } else { 1202 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1203 } 1204 xfer = &xx->xx_xfer; 1205 #if 0 1206 device_printf(sc->sc_dev, "%s xfer %p\n", __func__, xfer); 1207 #endif 1208 1209 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1210 #if 0 1211 device_printf(sc->sc_dev, "transfer event data: " 1212 "0x%016"PRIx64" 0x%08"PRIx32" %02x\n", 1213 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1214 XHCI_TRB_2_ERROR_GET(trb_2)); 1215 #endif 1216 if ((trb_0 & 0x3) == 0x3) { 1217 xfer->actlen = XHCI_TRB_2_REM_GET(trb_2); 1218 } 1219 } 1220 1221 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1222 XHCI_TRB_ERROR_SUCCESS) { 1223 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1224 err = USBD_NORMAL_COMPLETION; 1225 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1226 XHCI_TRB_ERROR_SHORT_PKT) { 1227 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1228 err = USBD_NORMAL_COMPLETION; 1229 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1230 XHCI_TRB_ERROR_STALL) { 1231 err = USBD_STALLED; 1232 xr->is_halted = true; 1233 } else { 1234 err = USBD_IOERROR; 1235 } 1236 xfer->status = err; 1237 1238 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1239 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1240 if ((trb_0 & 0x3) == 0x0) { 1241 usb_transfer_complete(xfer); 1242 } 1243 } else { 1244 usb_transfer_complete(xfer); 1245 } 1246 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1247 1248 } 1249 break; 1250 case XHCI_TRB_EVENT_CMD_COMPLETE: 1251 if (trb_0 == sc->sc_command_addr) { 1252 sc->sc_result_trb.trb_0 = trb_0; 1253 sc->sc_result_trb.trb_2 = trb_2; 1254 sc->sc_result_trb.trb_3 = trb_3; 1255 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1256 XHCI_TRB_ERROR_SUCCESS) { 1257 device_printf(sc->sc_dev, "command completion " 1258 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1259 "0x%08"PRIx32"\n", trb_0, trb_2, trb_3); 1260 } 1261 cv_signal(&sc->sc_command_cv); 1262 } else { 1263 device_printf(sc->sc_dev, "event: %p 0x%016"PRIx64" " 1264 "0x%08"PRIx32" 0x%08"PRIx32"\n", trb, trb_0, 1265 trb_2, trb_3); 1266 } 1267 break; 1268 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1269 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1270 break; 1271 default: 1272 break; 1273 } 1274 } 1275 1276 static void 1277 xhci_softintr(void *v) 1278 { 1279 struct usbd_bus * const bus = v; 1280 struct xhci_softc * const sc = bus->hci_private; 1281 struct xhci_ring * const er = &sc->sc_er; 1282 struct xhci_trb *trb; 1283 int i, j, k; 1284 1285 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1286 1287 i = er->xr_ep; 1288 j = er->xr_cs; 1289 1290 while (1) { 1291 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1292 BUS_DMASYNC_POSTREAD); 1293 trb = &er->xr_trb[i]; 1294 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1295 1296 if (j != k) 1297 break; 1298 1299 xhci_handle_event(sc, trb); 1300 1301 i++; 1302 if (i == XHCI_EVENT_RING_TRBS) { 1303 i = 0; 1304 j ^= 1; 1305 } 1306 } 1307 1308 er->xr_ep = i; 1309 er->xr_cs = j; 1310 1311 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1312 XHCI_ERDP_LO_BUSY); 1313 1314 DPRINTF(("%s: %s ends\n", __func__, device_xname(sc->sc_dev))); 1315 1316 return; 1317 } 1318 1319 static void 1320 xhci_poll(struct usbd_bus *bus) 1321 { 1322 struct xhci_softc * const sc = bus->hci_private; 1323 1324 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1325 1326 mutex_spin_enter(&sc->sc_intr_lock); 1327 xhci_intr1(sc); 1328 mutex_spin_exit(&sc->sc_intr_lock); 1329 1330 return; 1331 } 1332 1333 static usbd_status 1334 xhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1335 { 1336 struct xhci_softc * const sc = bus->hci_private; 1337 usbd_status err; 1338 1339 DPRINTF(("%s\n", __func__)); 1340 1341 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1342 #if 0 1343 if (err == USBD_NOMEM) 1344 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1345 #endif 1346 #ifdef XHCI_DEBUG 1347 if (err) 1348 device_printf(sc->sc_dev, "xhci_allocm: usb_allocmem()=%d\n", 1349 err); 1350 #endif 1351 1352 return err; 1353 } 1354 1355 static void 1356 xhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1357 { 1358 struct xhci_softc * const sc = bus->hci_private; 1359 1360 // DPRINTF(("%s\n", __func__)); 1361 1362 #if 0 1363 if (dma->block->flags & USB_DMA_RESERVE) { 1364 usb_reserve_freem(&sc->sc_dma_reserve, dma); 1365 return; 1366 } 1367 #endif 1368 usb_freemem(&sc->sc_bus, dma); 1369 } 1370 1371 static usbd_xfer_handle 1372 xhci_allocx(struct usbd_bus *bus) 1373 { 1374 struct xhci_softc * const sc = bus->hci_private; 1375 usbd_xfer_handle xfer; 1376 1377 // DPRINTF(("%s\n", __func__)); 1378 1379 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1380 if (xfer != NULL) { 1381 memset(xfer, 0, sizeof(struct xhci_xfer)); 1382 #ifdef DIAGNOSTIC 1383 xfer->busy_free = XFER_BUSY; 1384 #endif 1385 } 1386 1387 return xfer; 1388 } 1389 1390 static void 1391 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1392 { 1393 struct xhci_softc * const sc = bus->hci_private; 1394 1395 // DPRINTF(("%s\n", __func__)); 1396 1397 #ifdef DIAGNOSTIC 1398 if (xfer->busy_free != XFER_BUSY) { 1399 device_printf(sc->sc_dev, "xhci_freex: xfer=%p " 1400 "not busy, 0x%08x\n", xfer, xfer->busy_free); 1401 } 1402 xfer->busy_free = XFER_FREE; 1403 #endif 1404 pool_cache_put(sc->sc_xferpool, xfer); 1405 } 1406 1407 static void 1408 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1409 { 1410 struct xhci_softc * const sc = bus->hci_private; 1411 1412 *lock = &sc->sc_lock; 1413 } 1414 1415 extern u_int32_t usb_cookie_no; 1416 1417 static usbd_status 1418 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1419 int speed, int port, struct usbd_port *up) 1420 { 1421 struct xhci_softc * const sc = bus->hci_private; 1422 usbd_device_handle dev; 1423 usbd_status err; 1424 usb_device_descriptor_t *dd; 1425 struct usbd_device *hub; 1426 struct usbd_device *adev; 1427 int rhport = 0; 1428 struct xhci_slot *xs; 1429 uint32_t *cp; 1430 uint8_t slot; 1431 uint8_t addr; 1432 1433 dev = malloc(sizeof *dev, M_USB, M_NOWAIT|M_ZERO); 1434 if (dev == NULL) 1435 return USBD_NOMEM; 1436 1437 dev->bus = bus; 1438 1439 /* Set up default endpoint handle. */ 1440 dev->def_ep.edesc = &dev->def_ep_desc; 1441 1442 /* Set up default endpoint descriptor. */ 1443 dev->def_ep_desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1444 dev->def_ep_desc.bDescriptorType = UDESC_ENDPOINT; 1445 dev->def_ep_desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1446 dev->def_ep_desc.bmAttributes = UE_CONTROL; 1447 /* XXX */ 1448 USETW(dev->def_ep_desc.wMaxPacketSize, 64); 1449 dev->def_ep_desc.bInterval = 0; 1450 1451 /* doesn't matter, just don't let it uninitialized */ 1452 dev->def_ep.datatoggle = 0; 1453 1454 device_printf(sc->sc_dev, "%s up %p portno %d\n", __func__, up, 1455 up->portno); 1456 1457 dev->quirks = &usbd_no_quirk; 1458 dev->address = 0; 1459 dev->ddesc.bMaxPacketSize = 0; 1460 dev->depth = depth; 1461 dev->powersrc = up; 1462 dev->myhub = up->parent; 1463 1464 up->device = dev; 1465 1466 /* Locate root hub port */ 1467 for (adev = dev, hub = dev; 1468 hub != NULL; 1469 adev = hub, hub = hub->myhub) { 1470 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1471 } 1472 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1473 1474 if (hub != NULL) { 1475 for (int p = 0; p < hub->hub->hubdesc.bNbrPorts; p++) { 1476 if (hub->hub->ports[p].device == adev) { 1477 rhport = p; 1478 } 1479 } 1480 } else { 1481 rhport = port; 1482 } 1483 if (speed == USB_SPEED_SUPER) { 1484 rhport += sc->sc_ss_port_start - 1; 1485 } else { 1486 rhport += sc->sc_hs_port_start - 1; 1487 } 1488 device_printf(sc->sc_dev, "%s rhport %d\n", __func__, rhport); 1489 1490 dev->speed = speed; 1491 dev->langid = USBD_NOLANG; 1492 dev->cookie.cookie = ++usb_cookie_no; 1493 1494 /* Establish the default pipe. */ 1495 err = usbd_setup_pipe(dev, 0, &dev->def_ep, USBD_DEFAULT_INTERVAL, 1496 &dev->default_pipe); 1497 if (err) { 1498 usbd_remove_device(dev, up); 1499 return (err); 1500 } 1501 1502 dd = &dev->ddesc; 1503 1504 if ((depth == 0) && (port == 0)) { 1505 KASSERT(bus->devices[dev->address] == NULL); 1506 bus->devices[dev->address] = dev; 1507 err = usbd_get_initial_ddesc(dev, dd); 1508 if (err) 1509 return err; 1510 err = usbd_reload_device_desc(dev); 1511 if (err) 1512 return err; 1513 } else { 1514 err = xhci_enable_slot(sc, &slot); 1515 if (err) 1516 return err; 1517 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1518 if (err) 1519 return err; 1520 xs = &sc->sc_slots[slot]; 1521 dev->hci_private = xs; 1522 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1523 //hexdump("slot context", cp, sc->sc_ctxsz); 1524 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1525 device_printf(sc->sc_dev, "%s device address %u\n", 1526 __func__, addr); 1527 /* XXX ensure we know when the hardware does something 1528 we can't yet cope with */ 1529 KASSERT(addr >= 1 && addr <= 127); 1530 dev->address = addr; 1531 /* XXX dev->address not necessarily unique on bus */ 1532 KASSERT(bus->devices[dev->address] == NULL); 1533 bus->devices[dev->address] = dev; 1534 1535 err = usbd_get_initial_ddesc(dev, dd); 1536 if (err) 1537 return err; 1538 /* 4.8.2.1 */ 1539 if (speed == USB_SPEED_SUPER) 1540 USETW(dev->def_ep_desc.wMaxPacketSize, 1541 (1 << dd->bMaxPacketSize)); 1542 else 1543 USETW(dev->def_ep_desc.wMaxPacketSize, 1544 dd->bMaxPacketSize); 1545 device_printf(sc->sc_dev, "%s bMaxPacketSize %u\n", __func__, 1546 dd->bMaxPacketSize); 1547 xhci_update_ep0_mps(sc, xs, 1548 UGETW(dev->def_ep_desc.wMaxPacketSize)); 1549 err = usbd_reload_device_desc(dev); 1550 if (err) 1551 return err; 1552 1553 usbd_kill_pipe(dev->default_pipe); 1554 err = usbd_setup_pipe(dev, 0, &dev->def_ep, 1555 USBD_DEFAULT_INTERVAL, &dev->default_pipe); 1556 } 1557 1558 DPRINTF(("usbd_new_device: adding unit addr=%d, rev=%02x, class=%d, " 1559 "subclass=%d, protocol=%d, maxpacket=%d, len=%d, noconf=%d, " 1560 "speed=%d\n", dev->address,UGETW(dd->bcdUSB), 1561 dd->bDeviceClass, dd->bDeviceSubClass, dd->bDeviceProtocol, 1562 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1563 dev->speed)); 1564 1565 usbd_get_device_strings(dev); 1566 1567 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1568 1569 if ((depth == 0) && (port == 0)) { 1570 usbd_attach_roothub(parent, dev); 1571 device_printf(sc->sc_dev, "root_hub %p\n", bus->root_hub); 1572 return USBD_NORMAL_COMPLETION; 1573 } 1574 1575 1576 err = usbd_probe_and_attach(parent, dev, port, dev->address); 1577 if (err) { 1578 usbd_remove_device(dev, up); 1579 return (err); 1580 } 1581 1582 return USBD_NORMAL_COMPLETION; 1583 } 1584 1585 static usbd_status 1586 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1587 size_t ntrb, size_t align) 1588 { 1589 usbd_status err; 1590 size_t size = ntrb * XHCI_TRB_SIZE; 1591 1592 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1593 if (err) 1594 return err; 1595 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1596 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1597 xr->xr_trb = xhci_ring_trbv(xr, 0); 1598 xr->xr_ntrb = ntrb; 1599 xr->xr_ep = 0; 1600 xr->xr_cs = 1; 1601 memset(xr->xr_trb, 0, size); 1602 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1603 xr->is_halted = false; 1604 1605 return USBD_NORMAL_COMPLETION; 1606 } 1607 1608 static void 1609 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1610 { 1611 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1612 mutex_destroy(&xr->xr_lock); 1613 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1614 } 1615 1616 static void 1617 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1618 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1619 { 1620 size_t i; 1621 u_int ri; 1622 u_int cs; 1623 uint64_t parameter; 1624 uint32_t status; 1625 uint32_t control; 1626 1627 for (i = 0; i < ntrbs; i++) { 1628 #if 0 1629 device_printf(sc->sc_dev, "%s %p %p %zu " 1630 "%016"PRIx64" %08"PRIx32" %08"PRIx32"\n", __func__, xr, 1631 trbs, i, trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3); 1632 #endif 1633 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1634 XHCI_TRB_TYPE_LINK); 1635 } 1636 1637 #if 0 1638 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1639 xr, xr->xr_ep, xr->xr_cs); 1640 #endif 1641 1642 ri = xr->xr_ep; 1643 cs = xr->xr_cs; 1644 1645 /* 1646 * Although the xhci hardware can do scatter/gather dma from 1647 * arbitrary sized buffers, there is a non-obvious restriction 1648 * that a LINK trb is only allowed at the end of a burst of 1649 * transfers - which might be 16kB. 1650 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 1651 * The simple solution is not to allow a LINK trb in the middle 1652 * of anything - as here. 1653 * XXX: (dsl) There are xhci controllers out there (eg some made by 1654 * ASMedia) that seem to lock up if they process a LINK trb but 1655 * cannot process the linked-to trb yet. 1656 * The code should write the 'cycle' bit on the link trb AFTER 1657 * adding the other trb. 1658 */ 1659 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1660 parameter = xhci_ring_trbp(xr, 0); 1661 status = 0; 1662 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1663 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1664 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1665 htole32(status), htole32(control)); 1666 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1667 BUS_DMASYNC_PREWRITE); 1668 xr->xr_cookies[ri] = NULL; 1669 xr->xr_ep = 0; 1670 xr->xr_cs ^= 1; 1671 ri = xr->xr_ep; 1672 cs = xr->xr_cs; 1673 } 1674 1675 ri++; 1676 1677 /* Write any subsequent TRB first */ 1678 for (i = 1; i < ntrbs; i++) { 1679 parameter = trbs[i].trb_0; 1680 status = trbs[i].trb_2; 1681 control = trbs[i].trb_3; 1682 1683 if (cs) { 1684 control |= XHCI_TRB_3_CYCLE_BIT; 1685 } else { 1686 control &= ~XHCI_TRB_3_CYCLE_BIT; 1687 } 1688 1689 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1690 htole32(status), htole32(control)); 1691 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1692 BUS_DMASYNC_PREWRITE); 1693 xr->xr_cookies[ri] = cookie; 1694 ri++; 1695 } 1696 1697 /* Write the first TRB last */ 1698 i = 0; 1699 { 1700 parameter = trbs[i].trb_0; 1701 status = trbs[i].trb_2; 1702 control = trbs[i].trb_3; 1703 1704 if (xr->xr_cs) { 1705 control |= XHCI_TRB_3_CYCLE_BIT; 1706 } else { 1707 control &= ~XHCI_TRB_3_CYCLE_BIT; 1708 } 1709 1710 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1711 htole32(status), htole32(control)); 1712 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1713 BUS_DMASYNC_PREWRITE); 1714 xr->xr_cookies[xr->xr_ep] = cookie; 1715 } 1716 1717 xr->xr_ep = ri; 1718 xr->xr_cs = cs; 1719 1720 #if 0 1721 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1722 xr, xr->xr_ep, xr->xr_cs); 1723 #endif 1724 } 1725 1726 static usbd_status 1727 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1728 int timeout) 1729 { 1730 struct xhci_ring * const cr = &sc->sc_cr; 1731 usbd_status err; 1732 1733 device_printf(sc->sc_dev, "%s input: " 1734 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1735 trb->trb_0, trb->trb_2, trb->trb_3); 1736 1737 mutex_enter(&sc->sc_lock); 1738 1739 KASSERT(sc->sc_command_addr == 0); 1740 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1741 1742 mutex_enter(&cr->xr_lock); 1743 xhci_ring_put(sc, cr, NULL, trb, 1); 1744 mutex_exit(&cr->xr_lock); 1745 1746 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1747 1748 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1749 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1750 err = USBD_TIMEOUT; 1751 goto timedout; 1752 } 1753 1754 trb->trb_0 = sc->sc_result_trb.trb_0; 1755 trb->trb_2 = sc->sc_result_trb.trb_2; 1756 trb->trb_3 = sc->sc_result_trb.trb_3; 1757 1758 device_printf(sc->sc_dev, "%s output: " 1759 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1760 trb->trb_0, trb->trb_2, trb->trb_3); 1761 1762 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1763 case XHCI_TRB_ERROR_SUCCESS: 1764 err = USBD_NORMAL_COMPLETION; 1765 break; 1766 default: 1767 case 192 ... 223: 1768 err = USBD_IOERROR; 1769 break; 1770 case 224 ... 255: 1771 err = USBD_NORMAL_COMPLETION; 1772 break; 1773 } 1774 1775 timedout: 1776 sc->sc_command_addr = 0; 1777 mutex_exit(&sc->sc_lock); 1778 return err; 1779 } 1780 1781 static usbd_status 1782 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1783 { 1784 struct xhci_trb trb; 1785 usbd_status err; 1786 1787 trb.trb_0 = 0; 1788 trb.trb_2 = 0; 1789 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1790 1791 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1792 if (err != USBD_NORMAL_COMPLETION) { 1793 return err; 1794 } 1795 1796 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1797 1798 return err; 1799 } 1800 1801 static usbd_status 1802 xhci_address_device(struct xhci_softc * const sc, 1803 uint64_t icp, uint8_t slot_id, bool bsr) 1804 { 1805 struct xhci_trb trb; 1806 usbd_status err; 1807 1808 trb.trb_0 = icp; 1809 trb.trb_2 = 0; 1810 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1811 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1812 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1813 1814 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1815 return err; 1816 } 1817 1818 static usbd_status 1819 xhci_update_ep0_mps(struct xhci_softc * const sc, 1820 struct xhci_slot * const xs, u_int mps) 1821 { 1822 struct xhci_trb trb; 1823 usbd_status err; 1824 uint32_t * cp; 1825 1826 device_printf(sc->sc_dev, "%s\n", __func__); 1827 1828 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1829 cp[0] = htole32(0); 1830 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1831 1832 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1833 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1834 1835 /* sync input contexts before they are read from memory */ 1836 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1837 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1838 sc->sc_ctxsz * 4); 1839 1840 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1841 trb.trb_2 = 0; 1842 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1843 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1844 1845 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1846 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1847 return err; 1848 } 1849 1850 static void 1851 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1852 { 1853 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1854 1855 device_printf(sc->sc_dev, "dcbaa %p dc %016"PRIx64" slot %d\n", 1856 &dcbaa[si], dcba, si); 1857 1858 dcbaa[si] = htole64(dcba); 1859 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1860 BUS_DMASYNC_PREWRITE); 1861 } 1862 1863 static usbd_status 1864 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1865 int speed, int port, int rhport) 1866 { 1867 struct xhci_slot *xs; 1868 usbd_status err; 1869 u_int dci; 1870 uint32_t *cp; 1871 uint32_t mps; 1872 uint32_t xspeed; 1873 1874 switch (speed) { 1875 case USB_SPEED_LOW: 1876 xspeed = 2; 1877 mps = USB_MAX_IPACKET; 1878 break; 1879 case USB_SPEED_FULL: 1880 xspeed = 1; 1881 mps = 64; 1882 break; 1883 case USB_SPEED_HIGH: 1884 xspeed = 3; 1885 mps = USB_2_MAX_CTRL_PACKET; 1886 break; 1887 case USB_SPEED_SUPER: 1888 xspeed = 4; 1889 mps = USB_3_MAX_CTRL_PACKET; 1890 break; 1891 default: 1892 device_printf(sc->sc_dev, "%s: impossible speed: %x", 1893 __func__, speed); 1894 return USBD_INVAL; 1895 } 1896 1897 xs = &sc->sc_slots[slot]; 1898 xs->xs_idx = slot; 1899 1900 /* allocate contexts */ 1901 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1902 &xs->xs_dc_dma); 1903 if (err) 1904 return err; 1905 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1906 1907 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1908 &xs->xs_ic_dma); 1909 if (err) 1910 return err; 1911 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1912 1913 for (dci = 0; dci < 32; dci++) { 1914 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1915 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1916 if (dci == XHCI_DCI_SLOT) 1917 continue; 1918 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1919 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1920 if (err) { 1921 device_printf(sc->sc_dev, "ring init failure\n"); 1922 return err; 1923 } 1924 } 1925 1926 /* set up initial input control context */ 1927 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1928 cp[0] = htole32(0); 1929 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1930 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1931 1932 /* set up input slot context */ 1933 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1934 cp[0] = htole32( 1935 XHCI_SCTX_0_CTX_NUM_SET(1) | 1936 XHCI_SCTX_0_SPEED_SET(xspeed) 1937 ); 1938 cp[1] = htole32( 1939 XHCI_SCTX_1_RH_PORT_SET(rhport) 1940 ); 1941 cp[2] = htole32( 1942 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1943 ); 1944 cp[3] = htole32(0); 1945 1946 /* set up input EP0 context */ 1947 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1948 cp[0] = htole32(0); 1949 cp[1] = htole32( 1950 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1951 XHCI_EPCTX_1_EPTYPE_SET(4) | 1952 XHCI_EPCTX_1_CERR_SET(3) 1953 ); 1954 /* can't use xhci_ep_get_dci() yet? */ 1955 *(uint64_t *)(&cp[2]) = htole64( 1956 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1957 XHCI_EPCTX_2_DCS_SET(1)); 1958 cp[4] = htole32( 1959 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1960 ); 1961 1962 /* sync input contexts before they are read from memory */ 1963 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1964 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1965 sc->sc_ctxsz * 3); 1966 1967 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1968 1969 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1970 false); 1971 1972 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1973 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1974 sc->sc_ctxsz * 2); 1975 1976 return err; 1977 } 1978 1979 /* ----- */ 1980 1981 static void 1982 xhci_noop(usbd_pipe_handle pipe) 1983 { 1984 DPRINTF(("%s\n", __func__)); 1985 } 1986 1987 /* root hub descriptors */ 1988 1989 static const usb_device_descriptor_t xhci_devd = { 1990 USB_DEVICE_DESCRIPTOR_SIZE, 1991 UDESC_DEVICE, /* type */ 1992 {0x00, 0x02}, /* USB version */ 1993 UDCLASS_HUB, /* class */ 1994 UDSUBCLASS_HUB, /* subclass */ 1995 UDPROTO_HSHUBSTT, /* protocol */ 1996 64, /* max packet */ 1997 {0},{0},{0x00,0x01}, /* device id */ 1998 1,2,0, /* string indexes */ 1999 1 /* # of configurations */ 2000 }; 2001 2002 static const usb_device_qualifier_t xhci_odevd = { 2003 USB_DEVICE_DESCRIPTOR_SIZE, 2004 UDESC_DEVICE_QUALIFIER, /* type */ 2005 {0x00, 0x02}, /* USB version */ 2006 UDCLASS_HUB, /* class */ 2007 UDSUBCLASS_HUB, /* subclass */ 2008 UDPROTO_FSHUB, /* protocol */ 2009 64, /* max packet */ 2010 1, /* # of configurations */ 2011 0 2012 }; 2013 2014 static const usb_config_descriptor_t xhci_confd = { 2015 USB_CONFIG_DESCRIPTOR_SIZE, 2016 UDESC_CONFIG, 2017 {USB_CONFIG_DESCRIPTOR_SIZE + 2018 USB_INTERFACE_DESCRIPTOR_SIZE + 2019 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2020 1, 2021 1, 2022 0, 2023 UC_ATTR_MBO | UC_SELF_POWERED, 2024 0 /* max power */ 2025 }; 2026 2027 static const usb_interface_descriptor_t xhci_ifcd = { 2028 USB_INTERFACE_DESCRIPTOR_SIZE, 2029 UDESC_INTERFACE, 2030 0, 2031 0, 2032 1, 2033 UICLASS_HUB, 2034 UISUBCLASS_HUB, 2035 UIPROTO_HSHUBSTT, 2036 0 2037 }; 2038 2039 static const usb_endpoint_descriptor_t xhci_endpd = { 2040 USB_ENDPOINT_DESCRIPTOR_SIZE, 2041 UDESC_ENDPOINT, 2042 UE_DIR_IN | XHCI_INTR_ENDPT, 2043 UE_INTERRUPT, 2044 {8, 0}, /* max packet */ 2045 12 2046 }; 2047 2048 static const usb_hub_descriptor_t xhci_hubd = { 2049 USB_HUB_DESCRIPTOR_SIZE, 2050 UDESC_HUB, 2051 0, 2052 {0,0}, 2053 0, 2054 0, 2055 {""}, 2056 {""}, 2057 }; 2058 2059 /* root hub control */ 2060 2061 static usbd_status 2062 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 2063 { 2064 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2065 usbd_status err; 2066 2067 DPRINTF(("%s\n", __func__)); 2068 2069 /* Insert last in queue. */ 2070 mutex_enter(&sc->sc_lock); 2071 err = usb_insert_transfer(xfer); 2072 mutex_exit(&sc->sc_lock); 2073 if (err) 2074 return err; 2075 2076 /* Pipe isn't running, start first */ 2077 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2078 } 2079 2080 static usbd_status 2081 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2082 { 2083 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2084 usb_port_status_t ps; 2085 usb_device_request_t *req; 2086 void *buf = NULL; 2087 usb_hub_descriptor_t hubd; 2088 usbd_status err; 2089 int len, value, index; 2090 int l, totlen = 0; 2091 int port, i; 2092 uint32_t v; 2093 2094 DPRINTF(("%s\n", __func__)); 2095 2096 if (sc->sc_dying) 2097 return USBD_IOERROR; 2098 2099 req = &xfer->request; 2100 2101 value = UGETW(req->wValue); 2102 index = UGETW(req->wIndex); 2103 len = UGETW(req->wLength); 2104 2105 if (len != 0) 2106 buf = KERNADDR(&xfer->dmabuf, 0); 2107 2108 DPRINTF(("root req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2109 req->bRequest, value, index, len)); 2110 2111 #define C(x,y) ((x) | ((y) << 8)) 2112 switch(C(req->bRequest, req->bmRequestType)) { 2113 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2114 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2115 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2116 /* 2117 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2118 * for the integrated root hub. 2119 */ 2120 break; 2121 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2122 if (len > 0) { 2123 *(uint8_t *)buf = sc->sc_conf; 2124 totlen = 1; 2125 } 2126 break; 2127 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2128 DPRINTFN(8,("xhci_root_ctrl_start: wValue=0x%04x\n", value)); 2129 if (len == 0) 2130 break; 2131 switch(value >> 8) { 2132 case UDESC_DEVICE: 2133 if ((value & 0xff) != 0) { 2134 err = USBD_IOERROR; 2135 goto ret; 2136 } 2137 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2138 memcpy(buf, &xhci_devd, min(l, sizeof(xhci_devd))); 2139 break; 2140 case UDESC_DEVICE_QUALIFIER: 2141 if ((value & 0xff) != 0) { 2142 } 2143 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2144 memcpy(buf, &xhci_odevd, min(l, sizeof(xhci_odevd))); 2145 break; 2146 case UDESC_OTHER_SPEED_CONFIGURATION: 2147 case UDESC_CONFIG: 2148 if ((value & 0xff) != 0) { 2149 err = USBD_IOERROR; 2150 goto ret; 2151 } 2152 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2153 memcpy(buf, &xhci_confd, min(l, sizeof(xhci_confd))); 2154 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2155 value >> 8; 2156 buf = (char *)buf + l; 2157 len -= l; 2158 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2159 totlen += l; 2160 memcpy(buf, &xhci_ifcd, min(l, sizeof(xhci_ifcd))); 2161 buf = (char *)buf + l; 2162 len -= l; 2163 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2164 totlen += l; 2165 memcpy(buf, &xhci_endpd, min(l, sizeof(xhci_endpd))); 2166 break; 2167 case UDESC_STRING: 2168 #define sd ((usb_string_descriptor_t *)buf) 2169 switch (value & 0xff) { 2170 case 0: /* Language table */ 2171 totlen = usb_makelangtbl(sd, len); 2172 break; 2173 case 1: /* Vendor */ 2174 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2175 break; 2176 case 2: /* Product */ 2177 totlen = usb_makestrdesc(sd, len, 2178 "xHCI Root Hub"); 2179 break; 2180 } 2181 #undef sd 2182 break; 2183 default: 2184 err = USBD_IOERROR; 2185 goto ret; 2186 } 2187 break; 2188 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2189 if (len > 0) { 2190 *(uint8_t *)buf = 0; 2191 totlen = 1; 2192 } 2193 break; 2194 case C(UR_GET_STATUS, UT_READ_DEVICE): 2195 if (len > 1) { 2196 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2197 totlen = 2; 2198 } 2199 break; 2200 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2201 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2202 if (len > 1) { 2203 USETW(((usb_status_t *)buf)->wStatus, 0); 2204 totlen = 2; 2205 } 2206 break; 2207 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2208 if (value >= USB_MAX_DEVICES) { 2209 err = USBD_IOERROR; 2210 goto ret; 2211 } 2212 //sc->sc_addr = value; 2213 break; 2214 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2215 if (value != 0 && value != 1) { 2216 err = USBD_IOERROR; 2217 goto ret; 2218 } 2219 sc->sc_conf = value; 2220 break; 2221 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2222 break; 2223 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2224 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2225 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2226 err = USBD_IOERROR; 2227 goto ret; 2228 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2229 break; 2230 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2231 break; 2232 /* Hub requests */ 2233 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2234 break; 2235 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2236 DPRINTFN(4, ("xhci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2237 "port=%d feature=%d\n", 2238 index, value)); 2239 if (index < 1 || index > sc->sc_hs_port_count) { 2240 err = USBD_IOERROR; 2241 goto ret; 2242 } 2243 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2244 v = xhci_op_read_4(sc, port); 2245 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2246 v &= ~XHCI_PS_CLEAR; 2247 switch (value) { 2248 case UHF_PORT_ENABLE: 2249 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2250 break; 2251 case UHF_PORT_SUSPEND: 2252 err = USBD_IOERROR; 2253 goto ret; 2254 case UHF_PORT_POWER: 2255 break; 2256 case UHF_PORT_TEST: 2257 case UHF_PORT_INDICATOR: 2258 err = USBD_IOERROR; 2259 goto ret; 2260 case UHF_C_PORT_CONNECTION: 2261 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2262 break; 2263 case UHF_C_PORT_ENABLE: 2264 case UHF_C_PORT_SUSPEND: 2265 case UHF_C_PORT_OVER_CURRENT: 2266 err = USBD_IOERROR; 2267 goto ret; 2268 case UHF_C_PORT_RESET: 2269 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2270 break; 2271 default: 2272 err = USBD_IOERROR; 2273 goto ret; 2274 } 2275 2276 break; 2277 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2278 if (len == 0) 2279 break; 2280 if ((value & 0xff) != 0) { 2281 err = USBD_IOERROR; 2282 goto ret; 2283 } 2284 hubd = xhci_hubd; 2285 hubd.bNbrPorts = sc->sc_hs_port_count; 2286 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2287 hubd.bPwrOn2PwrGood = 200; 2288 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2289 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2290 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2291 l = min(len, hubd.bDescLength); 2292 totlen = l; 2293 memcpy(buf, &hubd, l); 2294 break; 2295 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2296 if (len != 4) { 2297 err = USBD_IOERROR; 2298 goto ret; 2299 } 2300 memset(buf, 0, len); /* ? XXX */ 2301 totlen = len; 2302 break; 2303 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2304 DPRINTFN(8,("xhci_root_ctrl_start: get port status i=%d\n", 2305 index)); 2306 if (index < 1 || index > sc->sc_maxports) { 2307 err = USBD_IOERROR; 2308 goto ret; 2309 } 2310 if (len != 4) { 2311 err = USBD_IOERROR; 2312 goto ret; 2313 } 2314 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2315 index)); 2316 DPRINTF(("%s READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x\n", 2317 __func__, index, sc->sc_hs_port_start - 1 + index, v)); 2318 switch (XHCI_PS_SPEED_GET(v)) { 2319 case 1: 2320 i = UPS_FULL_SPEED; 2321 break; 2322 case 2: 2323 i = UPS_LOW_SPEED; 2324 break; 2325 case 3: 2326 i = UPS_HIGH_SPEED; 2327 break; 2328 default: 2329 i = 0; 2330 break; 2331 } 2332 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2333 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2334 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2335 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2336 if (v & XHCI_PS_PR) i |= UPS_RESET; 2337 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2338 USETW(ps.wPortStatus, i); 2339 i = 0; 2340 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2341 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2342 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2343 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2344 USETW(ps.wPortChange, i); 2345 l = min(len, sizeof ps); 2346 memcpy(buf, &ps, l); 2347 totlen = l; 2348 break; 2349 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2350 err = USBD_IOERROR; 2351 goto ret; 2352 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2353 break; 2354 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2355 if (index < 1 || index > sc->sc_hs_port_count) { 2356 err = USBD_IOERROR; 2357 goto ret; 2358 } 2359 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2360 v = xhci_op_read_4(sc, port); 2361 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2362 v &= ~XHCI_PS_CLEAR; 2363 switch (value) { 2364 case UHF_PORT_ENABLE: 2365 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2366 break; 2367 case UHF_PORT_SUSPEND: 2368 /* XXX suspend */ 2369 break; 2370 case UHF_PORT_RESET: 2371 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2372 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2373 /* Wait for reset to complete. */ 2374 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2375 if (sc->sc_dying) { 2376 err = USBD_IOERROR; 2377 goto ret; 2378 } 2379 v = xhci_op_read_4(sc, port); 2380 if (v & XHCI_PS_PR) { 2381 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2382 usb_delay_ms(&sc->sc_bus, 10); 2383 /* XXX */ 2384 } 2385 break; 2386 case UHF_PORT_POWER: 2387 /* XXX power control */ 2388 break; 2389 /* XXX more */ 2390 case UHF_C_PORT_RESET: 2391 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2392 break; 2393 default: 2394 err = USBD_IOERROR; 2395 goto ret; 2396 } 2397 break; 2398 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2399 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2400 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2401 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2402 break; 2403 default: 2404 err = USBD_IOERROR; 2405 goto ret; 2406 } 2407 xfer->actlen = totlen; 2408 err = USBD_NORMAL_COMPLETION; 2409 ret: 2410 xfer->status = err; 2411 mutex_enter(&sc->sc_lock); 2412 usb_transfer_complete(xfer); 2413 mutex_exit(&sc->sc_lock); 2414 return USBD_IN_PROGRESS; 2415 } 2416 2417 2418 static void 2419 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2420 { 2421 /* Nothing to do, all transfers are synchronous. */ 2422 } 2423 2424 2425 static void 2426 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2427 { 2428 DPRINTF(("%s\n", __func__)); 2429 /* Nothing to do. */ 2430 } 2431 2432 static void 2433 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2434 { 2435 xfer->hcpriv = NULL; 2436 } 2437 2438 /* root hub interrupt */ 2439 2440 static usbd_status 2441 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2442 { 2443 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2444 usbd_status err; 2445 2446 /* Insert last in queue. */ 2447 mutex_enter(&sc->sc_lock); 2448 err = usb_insert_transfer(xfer); 2449 mutex_exit(&sc->sc_lock); 2450 if (err) 2451 return err; 2452 2453 /* Pipe isn't running, start first */ 2454 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2455 } 2456 2457 static usbd_status 2458 xhci_root_intr_start(usbd_xfer_handle xfer) 2459 { 2460 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2461 2462 if (sc->sc_dying) 2463 return USBD_IOERROR; 2464 2465 mutex_enter(&sc->sc_lock); 2466 sc->sc_intrxfer = xfer; 2467 mutex_exit(&sc->sc_lock); 2468 2469 return USBD_IN_PROGRESS; 2470 } 2471 2472 static void 2473 xhci_root_intr_abort(usbd_xfer_handle xfer) 2474 { 2475 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2476 2477 KASSERT(mutex_owned(&sc->sc_lock)); 2478 KASSERT(xfer->pipe->intrxfer == xfer); 2479 2480 DPRINTF(("%s: remove\n", __func__)); 2481 2482 sc->sc_intrxfer = NULL; 2483 2484 xfer->status = USBD_CANCELLED; 2485 usb_transfer_complete(xfer); 2486 } 2487 2488 static void 2489 xhci_root_intr_close(usbd_pipe_handle pipe) 2490 { 2491 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2492 2493 KASSERT(mutex_owned(&sc->sc_lock)); 2494 2495 DPRINTF(("%s\n", __func__)); 2496 2497 sc->sc_intrxfer = NULL; 2498 } 2499 2500 static void 2501 xhci_root_intr_done(usbd_xfer_handle xfer) 2502 { 2503 xfer->hcpriv = NULL; 2504 } 2505 2506 /* -------------- */ 2507 /* device control */ 2508 2509 static usbd_status 2510 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2511 { 2512 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2513 usbd_status err; 2514 2515 /* Insert last in queue. */ 2516 mutex_enter(&sc->sc_lock); 2517 err = usb_insert_transfer(xfer); 2518 mutex_exit(&sc->sc_lock); 2519 if (err) 2520 return (err); 2521 2522 /* Pipe isn't running, start first */ 2523 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2524 } 2525 2526 static usbd_status 2527 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2528 { 2529 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2530 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2531 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2532 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2533 struct xhci_xfer * const xx = (void *)xfer; 2534 usb_device_request_t * const req = &xfer->request; 2535 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2536 const uint32_t len = UGETW(req->wLength); 2537 usb_dma_t * const dma = &xfer->dmabuf; 2538 uint64_t parameter; 2539 uint32_t status; 2540 uint32_t control; 2541 u_int i; 2542 2543 DPRINTF(("%s\n", __func__)); 2544 DPRINTF(("req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2545 req->bRequest, UGETW(req->wValue), UGETW(req->wIndex), 2546 UGETW(req->wLength))); 2547 2548 /* XXX */ 2549 if (tr->is_halted) { 2550 xhci_reset_endpoint(xfer->pipe); 2551 tr->is_halted = false; 2552 xhci_set_dequeue(xfer->pipe); 2553 } 2554 2555 /* we rely on the bottom bits for extra info */ 2556 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2557 2558 KASSERT((xfer->rqflags & URQ_REQUEST) != 0); 2559 2560 i = 0; 2561 2562 /* setup phase */ 2563 memcpy(¶meter, req, sizeof(*req)); 2564 parameter = le64toh(parameter); 2565 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2566 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2567 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2568 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2569 XHCI_TRB_3_IDT_BIT; 2570 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2571 2572 if (len == 0) 2573 goto no_data; 2574 2575 /* data phase */ 2576 parameter = DMAADDR(dma, 0); 2577 KASSERT(len <= 0x10000); 2578 status = XHCI_TRB_2_IRQ_SET(0) | 2579 XHCI_TRB_2_TDSZ_SET(1) | 2580 XHCI_TRB_2_BYTES_SET(len); 2581 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2582 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2583 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2584 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2585 2586 parameter = (uintptr_t)xfer | 0x3; 2587 status = XHCI_TRB_2_IRQ_SET(0); 2588 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2589 XHCI_TRB_3_IOC_BIT; 2590 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2591 2592 no_data: 2593 parameter = 0; 2594 status = XHCI_TRB_2_IRQ_SET(0); 2595 /* the status stage has inverted direction */ 2596 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 2597 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2598 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2599 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2600 2601 parameter = (uintptr_t)xfer | 0x0; 2602 status = XHCI_TRB_2_IRQ_SET(0); 2603 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2604 XHCI_TRB_3_IOC_BIT; 2605 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2606 2607 mutex_enter(&tr->xr_lock); 2608 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2609 mutex_exit(&tr->xr_lock); 2610 2611 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2612 2613 if (xfer->timeout && !sc->sc_bus.use_polling) { 2614 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2615 xhci_timeout, xfer); 2616 } 2617 2618 if (sc->sc_bus.use_polling) { 2619 device_printf(sc->sc_dev, "%s polling\n", __func__); 2620 //xhci_waitintr(sc, xfer); 2621 } 2622 2623 return USBD_IN_PROGRESS; 2624 } 2625 2626 static void 2627 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2628 { 2629 DPRINTF(("%s\n", __func__)); 2630 2631 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2632 2633 } 2634 2635 static void 2636 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2637 { 2638 DPRINTF(("%s\n", __func__)); 2639 } 2640 2641 static void 2642 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2643 { 2644 DPRINTF(("%s\n", __func__)); 2645 } 2646 2647 /* ----------------- */ 2648 /* device isochronus */ 2649 2650 /* ----------- */ 2651 /* device bulk */ 2652 2653 static usbd_status 2654 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2655 { 2656 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2657 usbd_status err; 2658 2659 /* Insert last in queue. */ 2660 mutex_enter(&sc->sc_lock); 2661 err = usb_insert_transfer(xfer); 2662 mutex_exit(&sc->sc_lock); 2663 if (err) 2664 return err; 2665 2666 /* 2667 * Pipe isn't running (otherwise err would be USBD_INPROG), 2668 * so start it first. 2669 */ 2670 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2671 } 2672 2673 static usbd_status 2674 xhci_device_bulk_start(usbd_xfer_handle xfer) 2675 { 2676 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2677 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2678 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2679 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2680 struct xhci_xfer * const xx = (void *)xfer; 2681 const uint32_t len = xfer->length; 2682 usb_dma_t * const dma = &xfer->dmabuf; 2683 uint64_t parameter; 2684 uint32_t status; 2685 uint32_t control; 2686 u_int i = 0; 2687 2688 #if 0 2689 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2690 xs->xs_idx, dci); 2691 #endif 2692 2693 if (sc->sc_dying) 2694 return USBD_IOERROR; 2695 2696 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2697 2698 parameter = DMAADDR(dma, 0); 2699 /* 2700 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 2701 * If the user supplied buffer crosses such a boundary then 2 2702 * (or more) TRB should be used. 2703 * If multiple TRB are used the td_size field must be set correctly. 2704 * For v1.0 devices (like ivy bridge) this is the number of usb data 2705 * blocks needed to complete the transfer. 2706 * Setting it to 1 in the last TRB causes an extra zero-length 2707 * data block be sent. 2708 * The earlier documentation differs, I don't know how it behaves. 2709 */ 2710 KASSERT(len <= 0x10000); 2711 status = XHCI_TRB_2_IRQ_SET(0) | 2712 XHCI_TRB_2_TDSZ_SET(1) | 2713 XHCI_TRB_2_BYTES_SET(len); 2714 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2715 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2716 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2717 2718 mutex_enter(&tr->xr_lock); 2719 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2720 mutex_exit(&tr->xr_lock); 2721 2722 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2723 2724 if (sc->sc_bus.use_polling) { 2725 device_printf(sc->sc_dev, "%s polling\n", __func__); 2726 //xhci_waitintr(sc, xfer); 2727 } 2728 2729 return USBD_IN_PROGRESS; 2730 } 2731 2732 static void 2733 xhci_device_bulk_done(usbd_xfer_handle xfer) 2734 { 2735 //struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2736 //struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2737 //const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2738 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2739 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2740 2741 DPRINTF(("%s\n", __func__)); 2742 2743 #if 0 2744 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2745 xs->xs_idx, dci); 2746 #endif 2747 2748 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2749 2750 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2751 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2752 2753 2754 } 2755 2756 static void 2757 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2758 { 2759 DPRINTF(("%s\n", __func__)); 2760 } 2761 2762 static void 2763 xhci_device_bulk_close(usbd_pipe_handle pipe) 2764 { 2765 DPRINTF(("%s\n", __func__)); 2766 } 2767 2768 /* --------------- */ 2769 /* device intrrupt */ 2770 2771 static usbd_status 2772 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2773 { 2774 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2775 usbd_status err; 2776 2777 /* Insert last in queue. */ 2778 mutex_enter(&sc->sc_lock); 2779 err = usb_insert_transfer(xfer); 2780 mutex_exit(&sc->sc_lock); 2781 if (err) 2782 return err; 2783 2784 /* 2785 * Pipe isn't running (otherwise err would be USBD_INPROG), 2786 * so start it first. 2787 */ 2788 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2789 } 2790 2791 static usbd_status 2792 xhci_device_intr_start(usbd_xfer_handle xfer) 2793 { 2794 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2795 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2796 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2797 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2798 struct xhci_xfer * const xx = (void *)xfer; 2799 const uint32_t len = xfer->length; 2800 usb_dma_t * const dma = &xfer->dmabuf; 2801 uint64_t parameter; 2802 uint32_t status; 2803 uint32_t control; 2804 u_int i = 0; 2805 2806 #if 0 2807 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2808 xs->xs_idx, dci); 2809 #endif 2810 2811 if (sc->sc_dying) 2812 return USBD_IOERROR; 2813 2814 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2815 2816 parameter = DMAADDR(dma, 0); 2817 KASSERT(len <= 0x10000); 2818 status = XHCI_TRB_2_IRQ_SET(0) | 2819 XHCI_TRB_2_TDSZ_SET(1) | 2820 XHCI_TRB_2_BYTES_SET(len); 2821 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2822 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2823 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2824 2825 mutex_enter(&tr->xr_lock); 2826 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2827 mutex_exit(&tr->xr_lock); 2828 2829 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2830 2831 if (sc->sc_bus.use_polling) { 2832 #ifdef XHCI_DEBUG 2833 device_printf(sc->sc_dev, "%s polling\n", __func__); 2834 #endif 2835 //xhci_waitintr(sc, xfer); 2836 } 2837 2838 return USBD_IN_PROGRESS; 2839 } 2840 2841 static void 2842 xhci_device_intr_done(usbd_xfer_handle xfer) 2843 { 2844 struct xhci_softc * const sc __diagused = 2845 xfer->pipe->device->bus->hci_private; 2846 #ifdef XHCI_DEBUG 2847 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2848 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2849 #endif 2850 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2851 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2852 DPRINTF(("%s\n", __func__)); 2853 2854 #ifdef XHCI_DEBUG 2855 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2856 xs->xs_idx, dci); 2857 #endif 2858 2859 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2860 2861 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2862 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2863 2864 #if 0 2865 device_printf(sc->sc_dev, ""); 2866 for (size_t i = 0; i < xfer->length; i++) { 2867 printf(" %02x", ((uint8_t const *)xfer->buffer)[i]); 2868 } 2869 printf("\n"); 2870 #endif 2871 2872 if (xfer->pipe->repeat) { 2873 xfer->status = xhci_device_intr_start(xfer); 2874 } else { 2875 callout_stop(&xfer->timeout_handle); /* XXX */ 2876 } 2877 2878 } 2879 2880 static void 2881 xhci_device_intr_abort(usbd_xfer_handle xfer) 2882 { 2883 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2884 DPRINTF(("%s\n", __func__)); 2885 2886 KASSERT(mutex_owned(&sc->sc_lock)); 2887 device_printf(sc->sc_dev, "%s %p\n", __func__, xfer); 2888 KASSERT(xfer->pipe->intrxfer == xfer); 2889 xfer->status = USBD_CANCELLED; 2890 usb_transfer_complete(xfer); 2891 } 2892 2893 static void 2894 xhci_device_intr_close(usbd_pipe_handle pipe) 2895 { 2896 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2897 DPRINTF(("%s\n", __func__)); 2898 device_printf(sc->sc_dev, "%s %p\n", __func__, pipe); 2899 xhci_unconfigure_endpoint(pipe); 2900 } 2901 2902 /* ------------ */ 2903 2904 static void 2905 xhci_timeout(void *addr) 2906 { 2907 struct xhci_xfer * const xx = addr; 2908 usbd_xfer_handle const xfer = &xx->xx_xfer; 2909 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2910 2911 if (sc->sc_dying) { 2912 return; 2913 } 2914 2915 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2916 USB_TASKQ_MPSAFE); 2917 usb_add_task(xx->xx_xfer.pipe->device, &xx->xx_abort_task, 2918 USB_TASKQ_HC); 2919 } 2920 2921 static void 2922 xhci_timeout_task(void *addr) 2923 { 2924 usbd_xfer_handle const xfer = addr; 2925 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2926 2927 mutex_enter(&sc->sc_lock); 2928 #if 0 2929 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2930 #else 2931 xfer->status = USBD_TIMEOUT; 2932 usb_transfer_complete(xfer); 2933 #endif 2934 mutex_exit(&sc->sc_lock); 2935 } 2936
Indexes created Wed Oct 01 18:09:54 GMT 2025