xhci.c revision 1.23.2.7
1 /* $NetBSD: xhci.c,v 1.23.2.7 2018/01/03 20:02:37 snj Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.23.2.7 2018/01/03 20:02:37 snj Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 /* 693 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 694 * prevent system hang (Errata). 695 */ 696 usb_delay_ms(&sc->sc_bus, 1); 697 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 698 if ((usbcmd & XHCI_CMD_HCRST) == 0) 699 break; 700 } 701 if (i >= XHCI_WAIT_HCRST) { 702 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 703 return EIO; 704 } 705 706 /* Check controller not ready */ 707 for (i = 0; i < XHCI_WAIT_CNR; i++) { 708 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 709 if ((usbsts & XHCI_STS_CNR) == 0) 710 break; 711 usb_delay_ms(&sc->sc_bus, 1); 712 } 713 if (i >= XHCI_WAIT_CNR) { 714 aprint_error_dev(sc->sc_dev, 715 "controller not ready timeout after reset\n"); 716 return EIO; 717 } 718 719 return 0; 720 } 721 722 723 static void 724 hexdump(const char *msg, const void *base, size_t len) 725 { 726 #if 0 727 size_t cnt; 728 const uint32_t *p; 729 extern paddr_t vtophys(vaddr_t); 730 731 p = base; 732 cnt = 0; 733 734 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 735 (void *)vtophys((vaddr_t)base)); 736 737 while (cnt < len) { 738 if (cnt % 16 == 0) 739 printf("%p: ", p); 740 else if (cnt % 8 == 0) 741 printf(" |"); 742 printf(" %08x", *p++); 743 cnt += 4; 744 if (cnt % 16 == 0) 745 printf("\n"); 746 } 747 if (cnt % 16 != 0) 748 printf("\n"); 749 #endif 750 } 751 752 /* 7.2 xHCI Support Protocol Capability */ 753 static void 754 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 755 { 756 /* XXX Cache this lot */ 757 758 const uint32_t w0 = xhci_read_4(sc, ecp); 759 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 760 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 761 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 762 763 aprint_debug_dev(sc->sc_dev, 764 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 765 766 if (w4 != XHCI_XECP_USBID) 767 return; 768 769 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 770 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 771 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 772 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 773 774 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 775 switch (mm) { 776 case 0x0200: 777 case 0x0300: 778 case 0x0301: 779 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 780 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 781 break; 782 default: 783 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 784 major, minor); 785 return; 786 } 787 788 const size_t bus = (major == 3) ? 0 : 1; 789 790 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 791 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 792 if (sc->sc_ctlrportmap[cp] != 0) { 793 aprint_error_dev(sc->sc_dev, "contoller port %zu " 794 "already assigned", cp); 795 continue; 796 } 797 798 sc->sc_ctlrportbus[cp / NBBY] |= 799 bus == 0 ? 0 : __BIT(cp % NBBY); 800 801 const size_t rhp = sc->sc_rhportcount[bus]++; 802 803 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 804 "bus %zu rhp %zu is %d", bus, rhp, 805 sc->sc_rhportmap[bus][rhp]); 806 807 sc->sc_rhportmap[bus][rhp] = cp + 1; 808 sc->sc_ctlrportmap[cp] = rhp + 1; 809 } 810 } 811 812 /* Process extended capabilities */ 813 static void 814 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 815 { 816 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 817 818 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 819 while (ecp != 0) { 820 uint32_t ecr = xhci_read_4(sc, ecp); 821 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 822 switch (XHCI_XECP_ID(ecr)) { 823 case XHCI_ID_PROTOCOLS: { 824 xhci_id_protocols(sc, ecp); 825 break; 826 } 827 case XHCI_ID_USB_LEGACY: { 828 uint8_t bios_sem; 829 830 /* Take host controller ownership from BIOS */ 831 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 832 if (bios_sem) { 833 /* sets xHCI to be owned by OS */ 834 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 835 aprint_debug_dev(sc->sc_dev, 836 "waiting for BIOS to give up control\n"); 837 for (int i = 0; i < 5000; i++) { 838 bios_sem = xhci_read_1(sc, ecp + 839 XHCI_XECP_BIOS_SEM); 840 if (bios_sem == 0) 841 break; 842 DELAY(1000); 843 } 844 if (bios_sem) { 845 aprint_error_dev(sc->sc_dev, 846 "timed out waiting for BIOS\n"); 847 } 848 } 849 break; 850 } 851 default: 852 break; 853 } 854 ecr = xhci_read_4(sc, ecp); 855 if (XHCI_XECP_NEXT(ecr) == 0) { 856 ecp = 0; 857 } else { 858 ecp += XHCI_XECP_NEXT(ecr) * 4; 859 } 860 } 861 } 862 863 #define XHCI_HCCPREV1_BITS \ 864 "\177\020" /* New bitmask */ \ 865 "f\020\020XECP\0" \ 866 "f\014\4MAXPSA\0" \ 867 "b\013CFC\0" \ 868 "b\012SEC\0" \ 869 "b\011SBD\0" \ 870 "b\010FSE\0" \ 871 "b\7NSS\0" \ 872 "b\6LTC\0" \ 873 "b\5LHRC\0" \ 874 "b\4PIND\0" \ 875 "b\3PPC\0" \ 876 "b\2CZC\0" \ 877 "b\1BNC\0" \ 878 "b\0AC64\0" \ 879 "\0" 880 #define XHCI_HCCV1_x_BITS \ 881 "\177\020" /* New bitmask */ \ 882 "f\020\020XECP\0" \ 883 "f\014\4MAXPSA\0" \ 884 "b\013CFC\0" \ 885 "b\012SEC\0" \ 886 "b\011SPC\0" \ 887 "b\010PAE\0" \ 888 "b\7NSS\0" \ 889 "b\6LTC\0" \ 890 "b\5LHRC\0" \ 891 "b\4PIND\0" \ 892 "b\3PPC\0" \ 893 "b\2CSZ\0" \ 894 "b\1BNC\0" \ 895 "b\0AC64\0" \ 896 "\0" 897 898 int 899 xhci_init(struct xhci_softc *sc) 900 { 901 bus_size_t bsz; 902 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 903 uint32_t pagesize, config; 904 int i = 0; 905 uint16_t hciversion; 906 uint8_t caplength; 907 908 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 909 910 /* Set up the bus struct for the usb 3 and usb 2 buses */ 911 sc->sc_bus.ub_methods = &xhci_bus_methods; 912 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 913 sc->sc_bus.ub_revision = USBREV_3_0; 914 sc->sc_bus.ub_usedma = true; 915 sc->sc_bus.ub_hcpriv = sc; 916 917 sc->sc_bus2.ub_methods = &xhci_bus_methods; 918 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 919 sc->sc_bus2.ub_revision = USBREV_2_0; 920 sc->sc_bus2.ub_usedma = true; 921 sc->sc_bus2.ub_hcpriv = sc; 922 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 923 924 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 925 caplength = XHCI_CAP_CAPLENGTH(cap); 926 hciversion = XHCI_CAP_HCIVERSION(cap); 927 928 if (hciversion < XHCI_HCIVERSION_0_96 || 929 hciversion > XHCI_HCIVERSION_1_0) { 930 aprint_normal_dev(sc->sc_dev, 931 "xHCI version %x.%x not known to be supported\n", 932 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 933 } else { 934 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 935 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 936 } 937 938 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 939 &sc->sc_cbh) != 0) { 940 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 941 return ENOMEM; 942 } 943 944 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 945 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 946 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 947 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 948 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 949 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 950 aprint_debug_dev(sc->sc_dev, 951 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 952 953 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 954 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 955 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 956 957 char sbuf[128]; 958 if (hciversion < XHCI_HCIVERSION_1_0) 959 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 960 else 961 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 962 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 963 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 964 965 /* default all ports to bus 0, i.e. usb 3 */ 966 sc->sc_ctlrportbus = kmem_zalloc( 967 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 968 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 969 970 /* controller port to bus roothub port map */ 971 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 972 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 973 } 974 975 /* 976 * Process all Extended Capabilities 977 */ 978 xhci_ecp(sc, hcc); 979 980 bsz = XHCI_PORTSC(sc->sc_maxports); 981 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 982 &sc->sc_obh) != 0) { 983 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 984 return ENOMEM; 985 } 986 987 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 988 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 989 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 990 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 991 return ENOMEM; 992 } 993 994 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 995 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 996 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 997 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 998 return ENOMEM; 999 } 1000 1001 int rv; 1002 rv = xhci_hc_reset(sc); 1003 if (rv != 0) { 1004 return rv; 1005 } 1006 1007 if (sc->sc_vendor_init) 1008 sc->sc_vendor_init(sc); 1009 1010 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1011 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1012 pagesize = ffs(pagesize); 1013 if (pagesize == 0) { 1014 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1015 return EIO; 1016 } 1017 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1018 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1019 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1020 (uint32_t)sc->sc_maxslots); 1021 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1022 1023 usbd_status err; 1024 1025 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1026 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1027 if (sc->sc_maxspbuf != 0) { 1028 err = usb_allocmem(&sc->sc_bus, 1029 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1030 &sc->sc_spbufarray_dma); 1031 if (err) { 1032 aprint_error_dev(sc->sc_dev, 1033 "spbufarray init fail, err %d\n", err); 1034 return ENOMEM; 1035 } 1036 1037 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1038 sc->sc_maxspbuf, KM_SLEEP); 1039 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1040 for (i = 0; i < sc->sc_maxspbuf; i++) { 1041 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1042 /* allocate contexts */ 1043 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1044 sc->sc_pgsz, dma); 1045 if (err) { 1046 aprint_error_dev(sc->sc_dev, 1047 "spbufarray_dma init fail, err %d\n", err); 1048 rv = ENOMEM; 1049 goto bad1; 1050 } 1051 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1052 usb_syncmem(dma, 0, sc->sc_pgsz, 1053 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1054 } 1055 1056 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1057 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1058 } 1059 1060 config = xhci_op_read_4(sc, XHCI_CONFIG); 1061 config &= ~0xFF; 1062 config |= sc->sc_maxslots & 0xFF; 1063 xhci_op_write_4(sc, XHCI_CONFIG, config); 1064 1065 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1066 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1067 if (err) { 1068 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1069 err); 1070 rv = ENOMEM; 1071 goto bad1; 1072 } 1073 1074 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1075 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1076 if (err) { 1077 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1078 err); 1079 rv = ENOMEM; 1080 goto bad2; 1081 } 1082 1083 usb_dma_t *dma; 1084 size_t size; 1085 size_t align; 1086 1087 dma = &sc->sc_eventst_dma; 1088 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1089 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1090 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1091 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1092 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1093 if (err) { 1094 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1095 err); 1096 rv = ENOMEM; 1097 goto bad3; 1098 } 1099 1100 memset(KERNADDR(dma, 0), 0, size); 1101 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1102 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1103 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1104 KERNADDR(&sc->sc_eventst_dma, 0), 1105 sc->sc_eventst_dma.udma_block->size); 1106 1107 dma = &sc->sc_dcbaa_dma; 1108 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1109 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1110 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1111 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1112 if (err) { 1113 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1114 rv = ENOMEM; 1115 goto bad4; 1116 } 1117 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1118 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1119 KERNADDR(&sc->sc_dcbaa_dma, 0), 1120 sc->sc_dcbaa_dma.udma_block->size); 1121 1122 memset(KERNADDR(dma, 0), 0, size); 1123 if (sc->sc_maxspbuf != 0) { 1124 /* 1125 * DCBA entry 0 hold the scratchbuf array pointer. 1126 */ 1127 *(uint64_t *)KERNADDR(dma, 0) = 1128 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1129 } 1130 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1131 1132 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1133 KM_SLEEP); 1134 if (sc->sc_slots == NULL) { 1135 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1136 rv = ENOMEM; 1137 goto bad; 1138 } 1139 1140 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1141 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1142 if (sc->sc_xferpool == NULL) { 1143 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1144 err); 1145 rv = ENOMEM; 1146 goto bad; 1147 } 1148 1149 cv_init(&sc->sc_command_cv, "xhcicmd"); 1150 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1151 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1152 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1153 1154 struct xhci_erste *erst; 1155 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1156 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1157 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1158 erst[0].erste_3 = htole32(0); 1159 usb_syncmem(&sc->sc_eventst_dma, 0, 1160 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1161 1162 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1163 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1164 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1165 XHCI_ERDP_LO_BUSY); 1166 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1167 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1168 sc->sc_cr.xr_cs); 1169 1170 #if 0 1171 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1172 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1173 #endif 1174 1175 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1176 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1177 /* Intel xhci needs interrupt rate moderated. */ 1178 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1179 else 1180 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1181 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1182 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1183 1184 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1185 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1186 xhci_op_read_4(sc, XHCI_USBCMD)); 1187 1188 return 0; 1189 1190 bad: 1191 if (sc->sc_xferpool) { 1192 pool_cache_destroy(sc->sc_xferpool); 1193 sc->sc_xferpool = NULL; 1194 } 1195 1196 if (sc->sc_slots) { 1197 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1198 sc->sc_maxslots); 1199 sc->sc_slots = NULL; 1200 } 1201 1202 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1203 bad4: 1204 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1205 bad3: 1206 xhci_ring_free(sc, &sc->sc_er); 1207 bad2: 1208 xhci_ring_free(sc, &sc->sc_cr); 1209 i = sc->sc_maxspbuf; 1210 bad1: 1211 for (int j = 0; j < i; j++) 1212 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1213 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1214 1215 return rv; 1216 } 1217 1218 int 1219 xhci_intr(void *v) 1220 { 1221 struct xhci_softc * const sc = v; 1222 int ret = 0; 1223 1224 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1225 1226 if (sc == NULL) 1227 return 0; 1228 1229 mutex_spin_enter(&sc->sc_intr_lock); 1230 1231 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1232 goto done; 1233 1234 /* If we get an interrupt while polling, then just ignore it. */ 1235 if (sc->sc_bus.ub_usepolling) { 1236 #ifdef DIAGNOSTIC 1237 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1238 #endif 1239 goto done; 1240 } 1241 1242 ret = xhci_intr1(sc); 1243 done: 1244 mutex_spin_exit(&sc->sc_intr_lock); 1245 return ret; 1246 } 1247 1248 int 1249 xhci_intr1(struct xhci_softc * const sc) 1250 { 1251 uint32_t usbsts; 1252 uint32_t iman; 1253 1254 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1255 1256 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1257 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1258 #if 0 1259 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1260 return 0; 1261 } 1262 #endif 1263 xhci_op_write_4(sc, XHCI_USBSTS, 1264 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1265 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1266 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1267 1268 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1269 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1270 iman |= XHCI_IMAN_INTR_PEND; 1271 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1272 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1273 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1274 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1275 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1276 1277 usb_schedsoftintr(&sc->sc_bus); 1278 1279 return 1; 1280 } 1281 1282 /* 1283 * 3 port speed types used in USB stack 1284 * 1285 * usbdi speed 1286 * definition: USB_SPEED_* in usb.h 1287 * They are used in struct usbd_device in USB stack. 1288 * ioctl interface uses these values too. 1289 * port_status speed 1290 * definition: UPS_*_SPEED in usb.h 1291 * They are used in usb_port_status_t and valid only for USB 2.0. 1292 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1293 * of usb_port_status_ext_t indicates port speed. 1294 * Note that some 3.0 values overlap with 2.0 values. 1295 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1296 * means UPS_LOW_SPEED in HS.) 1297 * port status returned from hub also uses these values. 1298 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1299 * or more. 1300 * xspeed: 1301 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1302 * They are used in only slot context and PORTSC reg of xhci. 1303 * The difference between usbdi speed and xspeed is 1304 * that FS and LS values are swapped. 1305 */ 1306 1307 /* convert usbdi speed to xspeed */ 1308 static int 1309 xhci_speed2xspeed(int speed) 1310 { 1311 switch (speed) { 1312 case USB_SPEED_LOW: return 2; 1313 case USB_SPEED_FULL: return 1; 1314 default: return speed; 1315 } 1316 } 1317 1318 #if 0 1319 /* convert xspeed to usbdi speed */ 1320 static int 1321 xhci_xspeed2speed(int xspeed) 1322 { 1323 switch (xspeed) { 1324 case 1: return USB_SPEED_FULL; 1325 case 2: return USB_SPEED_LOW; 1326 default: return xspeed; 1327 } 1328 } 1329 #endif 1330 1331 /* convert xspeed to port status speed */ 1332 static int 1333 xhci_xspeed2psspeed(int xspeed) 1334 { 1335 switch (xspeed) { 1336 case 0: return 0; 1337 case 1: return UPS_FULL_SPEED; 1338 case 2: return UPS_LOW_SPEED; 1339 case 3: return UPS_HIGH_SPEED; 1340 default: return UPS_OTHER_SPEED; 1341 } 1342 } 1343 1344 /* 1345 * Construct input contexts and issue TRB to open pipe. 1346 */ 1347 static usbd_status 1348 xhci_configure_endpoint(struct usbd_pipe *pipe) 1349 { 1350 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1351 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1352 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1353 struct xhci_trb trb; 1354 usbd_status err; 1355 1356 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1357 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1358 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1359 pipe->up_endpoint->ue_edesc->bmAttributes); 1360 1361 /* XXX ensure input context is available? */ 1362 1363 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1364 1365 /* set up context */ 1366 xhci_setup_ctx(pipe); 1367 1368 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1369 sc->sc_ctxsz * 1); 1370 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1371 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1372 1373 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1374 trb.trb_2 = 0; 1375 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1376 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1377 1378 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1379 1380 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1381 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1382 sc->sc_ctxsz * 1); 1383 1384 return err; 1385 } 1386 1387 #if 0 1388 static usbd_status 1389 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1390 { 1391 #ifdef USB_DEBUG 1392 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1393 #endif 1394 1395 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1396 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1397 1398 return USBD_NORMAL_COMPLETION; 1399 } 1400 #endif 1401 1402 /* 4.6.8, 6.4.3.7 */ 1403 static usbd_status 1404 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1405 { 1406 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1407 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1408 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1409 struct xhci_trb trb; 1410 usbd_status err; 1411 1412 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1413 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1414 1415 KASSERT(mutex_owned(&sc->sc_lock)); 1416 1417 trb.trb_0 = 0; 1418 trb.trb_2 = 0; 1419 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1420 XHCI_TRB_3_EP_SET(dci) | 1421 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1422 1423 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1424 1425 return err; 1426 } 1427 1428 static usbd_status 1429 xhci_reset_endpoint(struct usbd_pipe *pipe) 1430 { 1431 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1432 1433 mutex_enter(&sc->sc_lock); 1434 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1435 mutex_exit(&sc->sc_lock); 1436 1437 return ret; 1438 } 1439 1440 /* 1441 * 4.6.9, 6.4.3.8 1442 * Stop execution of TDs on xfer ring. 1443 * Should be called with sc_lock held. 1444 */ 1445 static usbd_status 1446 xhci_stop_endpoint(struct usbd_pipe *pipe) 1447 { 1448 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1449 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1450 struct xhci_trb trb; 1451 usbd_status err; 1452 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1453 1454 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1455 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1456 1457 KASSERT(mutex_owned(&sc->sc_lock)); 1458 1459 trb.trb_0 = 0; 1460 trb.trb_2 = 0; 1461 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1462 XHCI_TRB_3_EP_SET(dci) | 1463 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1464 1465 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1466 1467 return err; 1468 } 1469 1470 /* 1471 * Set TR Dequeue Pointer. 1472 * xHCI 1.1 4.6.10 6.4.3.9 1473 * Purge all of the TRBs on ring and reinitialize ring. 1474 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1475 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1476 * error will be generated. 1477 */ 1478 static usbd_status 1479 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1480 { 1481 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1482 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1483 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1484 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1485 struct xhci_trb trb; 1486 usbd_status err; 1487 1488 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1489 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1490 1491 KASSERT(mutex_owned(&sc->sc_lock)); 1492 1493 xhci_host_dequeue(xr); 1494 1495 /* set DCS */ 1496 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1497 trb.trb_2 = 0; 1498 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1499 XHCI_TRB_3_EP_SET(dci) | 1500 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1501 1502 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1503 1504 return err; 1505 } 1506 1507 static usbd_status 1508 xhci_set_dequeue(struct usbd_pipe *pipe) 1509 { 1510 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1511 1512 mutex_enter(&sc->sc_lock); 1513 usbd_status ret = xhci_set_dequeue_locked(pipe); 1514 mutex_exit(&sc->sc_lock); 1515 1516 return ret; 1517 } 1518 1519 /* 1520 * Open new pipe: called from usbd_setup_pipe_flags. 1521 * Fills methods of pipe. 1522 * If pipe is not for ep0, calls configure_endpoint. 1523 */ 1524 static usbd_status 1525 xhci_open(struct usbd_pipe *pipe) 1526 { 1527 struct usbd_device * const dev = pipe->up_dev; 1528 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1529 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1530 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1531 1532 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1533 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1534 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1535 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1536 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1537 ed->bmAttributes); 1538 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1539 0, 0); 1540 1541 if (sc->sc_dying) 1542 return USBD_IOERROR; 1543 1544 /* Root Hub */ 1545 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1546 switch (ed->bEndpointAddress) { 1547 case USB_CONTROL_ENDPOINT: 1548 pipe->up_methods = &roothub_ctrl_methods; 1549 break; 1550 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1551 pipe->up_methods = &xhci_root_intr_methods; 1552 break; 1553 default: 1554 pipe->up_methods = NULL; 1555 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1556 ed->bEndpointAddress, 0, 0, 0); 1557 return USBD_INVAL; 1558 } 1559 return USBD_NORMAL_COMPLETION; 1560 } 1561 1562 switch (xfertype) { 1563 case UE_CONTROL: 1564 pipe->up_methods = &xhci_device_ctrl_methods; 1565 break; 1566 case UE_ISOCHRONOUS: 1567 pipe->up_methods = &xhci_device_isoc_methods; 1568 return USBD_INVAL; 1569 break; 1570 case UE_BULK: 1571 pipe->up_methods = &xhci_device_bulk_methods; 1572 break; 1573 case UE_INTERRUPT: 1574 pipe->up_methods = &xhci_device_intr_methods; 1575 break; 1576 default: 1577 return USBD_IOERROR; 1578 break; 1579 } 1580 1581 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1582 return xhci_configure_endpoint(pipe); 1583 1584 return USBD_NORMAL_COMPLETION; 1585 } 1586 1587 /* 1588 * Closes pipe, called from usbd_kill_pipe via close methods. 1589 * If the endpoint to be closed is ep0, disable_slot. 1590 * Should be called with sc_lock held. 1591 */ 1592 static void 1593 xhci_close_pipe(struct usbd_pipe *pipe) 1594 { 1595 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1596 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1597 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1598 const u_int dci = xhci_ep_get_dci(ed); 1599 struct xhci_trb trb; 1600 uint32_t *cp; 1601 1602 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1603 1604 if (sc->sc_dying) 1605 return; 1606 1607 /* xs is uninitialized before xhci_init_slot */ 1608 if (xs == NULL || xs->xs_idx == 0) 1609 return; 1610 1611 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1612 1613 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1614 KASSERT(mutex_owned(&sc->sc_lock)); 1615 1616 if (pipe->up_dev->ud_depth == 0) 1617 return; 1618 1619 if (dci == XHCI_DCI_EP_CONTROL) { 1620 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1621 xhci_disable_slot(sc, xs->xs_idx); 1622 return; 1623 } 1624 1625 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1626 (void)xhci_stop_endpoint(pipe); 1627 1628 /* 1629 * set appropriate bit to be dropped. 1630 * don't set DC bit to 1, otherwise all endpoints 1631 * would be deconfigured. 1632 */ 1633 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1634 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1635 cp[1] = htole32(0); 1636 1637 /* XXX should be most significant one, not dci? */ 1638 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1639 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1640 1641 /* configure ep context performs an implicit dequeue */ 1642 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1643 1644 /* sync input contexts before they are read from memory */ 1645 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1646 1647 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1648 trb.trb_2 = 0; 1649 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1650 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1651 1652 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1653 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1654 } 1655 1656 /* 1657 * Abort transfer. 1658 * Should be called with sc_lock held. 1659 */ 1660 static void 1661 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1662 { 1663 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1664 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1665 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1666 1667 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1668 DPRINTFN(4, "xfer %p pipe %p status %d", 1669 xfer, xfer->ux_pipe, status, 0); 1670 1671 KASSERT(mutex_owned(&sc->sc_lock)); 1672 1673 if (sc->sc_dying) { 1674 /* If we're dying, just do the software part. */ 1675 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1676 xfer->ux_status = status; 1677 callout_stop(&xfer->ux_callout); 1678 usb_transfer_complete(xfer); 1679 return; 1680 } 1681 1682 /* 1683 * If an abort is already in progress then just wait for it to 1684 * complete and return. 1685 */ 1686 if (xfer->ux_hcflags & UXFER_ABORTING) { 1687 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1688 #ifdef DIAGNOSTIC 1689 if (status == USBD_TIMEOUT) 1690 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1691 #endif 1692 /* Override the status which might be USBD_TIMEOUT. */ 1693 xfer->ux_status = status; 1694 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1695 0); 1696 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1697 while (xfer->ux_hcflags & UXFER_ABORTING) 1698 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1699 return; 1700 } 1701 xfer->ux_hcflags |= UXFER_ABORTING; 1702 1703 /* 1704 * Step 1: Stop xfer timeout timer. 1705 */ 1706 xfer->ux_status = status; 1707 callout_stop(&xfer->ux_callout); 1708 1709 /* 1710 * Step 2: Stop execution of TD on the ring. 1711 */ 1712 switch (xhci_get_epstate(sc, xs, dci)) { 1713 case XHCI_EPSTATE_HALTED: 1714 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1715 break; 1716 case XHCI_EPSTATE_STOPPED: 1717 break; 1718 default: 1719 (void)xhci_stop_endpoint(xfer->ux_pipe); 1720 break; 1721 } 1722 #ifdef DIAGNOSTIC 1723 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1724 if (epst != XHCI_EPSTATE_STOPPED) 1725 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1726 #endif 1727 1728 /* 1729 * Step 3: Remove any vestiges of the xfer from the ring. 1730 */ 1731 xhci_set_dequeue_locked(xfer->ux_pipe); 1732 1733 /* 1734 * Step 4: Notify completion to waiting xfers. 1735 */ 1736 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1737 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1738 usb_transfer_complete(xfer); 1739 if (wake) { 1740 cv_broadcast(&xfer->ux_hccv); 1741 } 1742 DPRINTFN(14, "end", 0, 0, 0, 0); 1743 1744 KASSERT(mutex_owned(&sc->sc_lock)); 1745 } 1746 1747 static void 1748 xhci_host_dequeue(struct xhci_ring * const xr) 1749 { 1750 /* When dequeueing the controller, update our struct copy too */ 1751 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1752 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1753 BUS_DMASYNC_PREWRITE); 1754 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1755 1756 xr->xr_ep = 0; 1757 xr->xr_cs = 1; 1758 } 1759 1760 /* 1761 * Recover STALLed endpoint. 1762 * xHCI 1.1 sect 4.10.2.1 1763 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1764 * all transfers on transfer ring. 1765 * These are done in thread context asynchronously. 1766 */ 1767 static void 1768 xhci_clear_endpoint_stall_async_task(void *cookie) 1769 { 1770 struct usbd_xfer * const xfer = cookie; 1771 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1772 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1773 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1774 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1775 1776 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1777 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1778 1779 xhci_reset_endpoint(xfer->ux_pipe); 1780 xhci_set_dequeue(xfer->ux_pipe); 1781 1782 mutex_enter(&sc->sc_lock); 1783 tr->is_halted = false; 1784 usb_transfer_complete(xfer); 1785 mutex_exit(&sc->sc_lock); 1786 DPRINTFN(4, "ends", 0, 0, 0, 0); 1787 } 1788 1789 static usbd_status 1790 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1791 { 1792 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1793 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1794 1795 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1796 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1797 1798 if (sc->sc_dying) { 1799 return USBD_IOERROR; 1800 } 1801 1802 usb_init_task(&xp->xp_async_task, 1803 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1804 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1805 DPRINTFN(4, "ends", 0, 0, 0, 0); 1806 1807 return USBD_NORMAL_COMPLETION; 1808 } 1809 1810 /* Process roothub port status/change events and notify to uhub_intr. */ 1811 static void 1812 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1813 { 1814 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1815 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1816 ctlrport, 0, 0); 1817 1818 if (ctlrport > sc->sc_maxports) 1819 return; 1820 1821 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1822 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1823 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1824 1825 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1826 device_unit(sc->sc_dev), bn, rhp, xfer); 1827 1828 if (xfer == NULL) 1829 return; 1830 1831 uint8_t *p = xfer->ux_buf; 1832 memset(p, 0, xfer->ux_length); 1833 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1834 xfer->ux_actlen = xfer->ux_length; 1835 xfer->ux_status = USBD_NORMAL_COMPLETION; 1836 usb_transfer_complete(xfer); 1837 } 1838 1839 /* Process Transfer Events */ 1840 static void 1841 xhci_event_transfer(struct xhci_softc * const sc, 1842 const struct xhci_trb * const trb) 1843 { 1844 uint64_t trb_0; 1845 uint32_t trb_2, trb_3; 1846 uint8_t trbcode; 1847 u_int slot, dci; 1848 struct xhci_slot *xs; 1849 struct xhci_ring *xr; 1850 struct xhci_xfer *xx; 1851 struct usbd_xfer *xfer; 1852 usbd_status err; 1853 1854 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1855 1856 trb_0 = le64toh(trb->trb_0); 1857 trb_2 = le32toh(trb->trb_2); 1858 trb_3 = le32toh(trb->trb_3); 1859 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1860 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1861 dci = XHCI_TRB_3_EP_GET(trb_3); 1862 xs = &sc->sc_slots[slot]; 1863 xr = &xs->xs_ep[dci].xe_tr; 1864 1865 /* sanity check */ 1866 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1867 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1868 1869 int idx = 0; 1870 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1871 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1872 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1873 return; 1874 } 1875 xx = xr->xr_cookies[idx]; 1876 1877 /* clear cookie of consumed TRB */ 1878 xr->xr_cookies[idx] = NULL; 1879 1880 /* 1881 * xx is NULL if pipe is opened but xfer is not started. 1882 * It happens when stopping idle pipe. 1883 */ 1884 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1885 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1886 idx, xx, trbcode, dci); 1887 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1888 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1889 0, 0); 1890 return; 1891 } 1892 } else { 1893 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1894 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1895 } 1896 /* XXX this may not happen */ 1897 if (xx == NULL) { 1898 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1899 return; 1900 } 1901 xfer = &xx->xx_xfer; 1902 /* XXX this may happen when detaching */ 1903 if (xfer == NULL) { 1904 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1905 xx, trb_0, 0, 0); 1906 return; 1907 } 1908 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1909 /* XXX I dunno why this happens */ 1910 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1911 1912 if (!xfer->ux_pipe->up_repeat && 1913 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1914 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1915 return; 1916 } 1917 1918 /* 4.11.5.2 Event Data TRB */ 1919 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1920 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1921 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1922 if ((trb_0 & 0x3) == 0x3) { 1923 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1924 } 1925 } 1926 1927 switch (trbcode) { 1928 case XHCI_TRB_ERROR_SHORT_PKT: 1929 case XHCI_TRB_ERROR_SUCCESS: 1930 /* 1931 * A ctrl transfer can generate two events if it has a Data 1932 * stage. A short data stage can be OK and should not 1933 * complete the transfer as the status stage needs to be 1934 * performed. 1935 * 1936 * Note: Data and Status stage events point at same xfer. 1937 * ux_actlen and ux_dmabuf will be passed to 1938 * usb_transfer_complete after the Status stage event. 1939 * 1940 * It can be distingished which stage generates the event: 1941 * + by checking least 3 bits of trb_0 if ED==1. 1942 * (see xhci_device_ctrl_start). 1943 * + by checking the type of original TRB if ED==0. 1944 * 1945 * In addition, intr, bulk, and isoc transfer currently 1946 * consists of single TD, so the "skip" is not needed. 1947 * ctrl xfer uses EVENT_DATA, and others do not. 1948 * Thus driver can switch the flow by checking ED bit. 1949 */ 1950 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1951 if (xfer->ux_actlen == 0) 1952 xfer->ux_actlen = xfer->ux_length - 1953 XHCI_TRB_2_REM_GET(trb_2); 1954 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1955 == XHCI_TRB_TYPE_DATA_STAGE) { 1956 return; 1957 } 1958 } else if ((trb_0 & 0x3) == 0x3) { 1959 return; 1960 } 1961 err = USBD_NORMAL_COMPLETION; 1962 break; 1963 case XHCI_TRB_ERROR_STOPPED: 1964 case XHCI_TRB_ERROR_LENGTH: 1965 case XHCI_TRB_ERROR_STOPPED_SHORT: 1966 /* 1967 * don't complete the transfer being aborted 1968 * as abort_xfer does instead. 1969 */ 1970 if (xfer->ux_hcflags & UXFER_ABORTING) { 1971 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1972 return; 1973 } 1974 err = USBD_CANCELLED; 1975 break; 1976 case XHCI_TRB_ERROR_STALL: 1977 case XHCI_TRB_ERROR_BABBLE: 1978 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1979 xr->is_halted = true; 1980 err = USBD_STALLED; 1981 /* 1982 * Stalled endpoints can be recoverd by issuing 1983 * command TRB TYPE_RESET_EP on xHCI instead of 1984 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1985 * on the endpoint. However, this function may be 1986 * called from softint context (e.g. from umass), 1987 * in that case driver gets KASSERT in cv_timedwait 1988 * in xhci_do_command. 1989 * To avoid this, this runs reset_endpoint and 1990 * usb_transfer_complete in usb task thread 1991 * asynchronously (and then umass issues clear 1992 * UF_ENDPOINT_HALT). 1993 */ 1994 xfer->ux_status = err; 1995 callout_stop(&xfer->ux_callout); 1996 xhci_clear_endpoint_stall_async(xfer); 1997 return; 1998 default: 1999 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 2000 err = USBD_IOERROR; 2001 break; 2002 } 2003 xfer->ux_status = err; 2004 2005 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2006 if ((trb_0 & 0x3) == 0x0) { 2007 callout_stop(&xfer->ux_callout); 2008 usb_transfer_complete(xfer); 2009 } 2010 } else { 2011 callout_stop(&xfer->ux_callout); 2012 usb_transfer_complete(xfer); 2013 } 2014 } 2015 2016 /* Process Command complete events */ 2017 static void 2018 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2019 { 2020 uint64_t trb_0; 2021 uint32_t trb_2, trb_3; 2022 2023 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2024 2025 KASSERT(mutex_owned(&sc->sc_lock)); 2026 2027 trb_0 = le64toh(trb->trb_0); 2028 trb_2 = le32toh(trb->trb_2); 2029 trb_3 = le32toh(trb->trb_3); 2030 2031 if (trb_0 == sc->sc_command_addr) { 2032 sc->sc_resultpending = false; 2033 2034 sc->sc_result_trb.trb_0 = trb_0; 2035 sc->sc_result_trb.trb_2 = trb_2; 2036 sc->sc_result_trb.trb_3 = trb_3; 2037 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2038 XHCI_TRB_ERROR_SUCCESS) { 2039 DPRINTFN(1, "command completion " 2040 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2041 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2042 } 2043 cv_signal(&sc->sc_command_cv); 2044 } else { 2045 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2046 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2047 trb_2, trb_3); 2048 } 2049 } 2050 2051 /* 2052 * Process events. 2053 * called from xhci_softintr 2054 */ 2055 static void 2056 xhci_handle_event(struct xhci_softc * const sc, 2057 const struct xhci_trb * const trb) 2058 { 2059 uint64_t trb_0; 2060 uint32_t trb_2, trb_3; 2061 2062 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2063 2064 trb_0 = le64toh(trb->trb_0); 2065 trb_2 = le32toh(trb->trb_2); 2066 trb_3 = le32toh(trb->trb_3); 2067 2068 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2069 trb, trb_0, trb_2, trb_3); 2070 2071 /* 2072 * 4.11.3.1, 6.4.2.1 2073 * TRB Pointer is invalid for these completion codes. 2074 */ 2075 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2076 case XHCI_TRB_ERROR_RING_UNDERRUN: 2077 case XHCI_TRB_ERROR_RING_OVERRUN: 2078 case XHCI_TRB_ERROR_VF_RING_FULL: 2079 return; 2080 default: 2081 if (trb_0 == 0) { 2082 return; 2083 } 2084 break; 2085 } 2086 2087 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2088 case XHCI_TRB_EVENT_TRANSFER: 2089 xhci_event_transfer(sc, trb); 2090 break; 2091 case XHCI_TRB_EVENT_CMD_COMPLETE: 2092 xhci_event_cmd(sc, trb); 2093 break; 2094 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2095 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2096 break; 2097 default: 2098 break; 2099 } 2100 } 2101 2102 static void 2103 xhci_softintr(void *v) 2104 { 2105 struct usbd_bus * const bus = v; 2106 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2107 struct xhci_ring * const er = &sc->sc_er; 2108 struct xhci_trb *trb; 2109 int i, j, k; 2110 2111 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2112 2113 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2114 2115 i = er->xr_ep; 2116 j = er->xr_cs; 2117 2118 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2119 2120 while (1) { 2121 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2122 BUS_DMASYNC_POSTREAD); 2123 trb = &er->xr_trb[i]; 2124 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2125 2126 if (j != k) 2127 break; 2128 2129 xhci_handle_event(sc, trb); 2130 2131 i++; 2132 if (i == er->xr_ntrb) { 2133 i = 0; 2134 j ^= 1; 2135 } 2136 } 2137 2138 er->xr_ep = i; 2139 er->xr_cs = j; 2140 2141 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2142 XHCI_ERDP_LO_BUSY); 2143 2144 DPRINTFN(16, "ends", 0, 0, 0, 0); 2145 2146 return; 2147 } 2148 2149 static void 2150 xhci_poll(struct usbd_bus *bus) 2151 { 2152 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2153 2154 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2155 2156 mutex_spin_enter(&sc->sc_intr_lock); 2157 xhci_intr1(sc); 2158 mutex_spin_exit(&sc->sc_intr_lock); 2159 2160 return; 2161 } 2162 2163 static struct usbd_xfer * 2164 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2165 { 2166 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2167 struct usbd_xfer *xfer; 2168 2169 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2170 2171 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2172 if (xfer != NULL) { 2173 memset(xfer, 0, sizeof(struct xhci_xfer)); 2174 #ifdef DIAGNOSTIC 2175 xfer->ux_state = XFER_BUSY; 2176 #endif 2177 } 2178 2179 return xfer; 2180 } 2181 2182 static void 2183 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2184 { 2185 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2186 2187 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2188 2189 #ifdef DIAGNOSTIC 2190 if (xfer->ux_state != XFER_BUSY) { 2191 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2192 xfer, xfer->ux_state, 0, 0); 2193 } 2194 xfer->ux_state = XFER_FREE; 2195 #endif 2196 pool_cache_put(sc->sc_xferpool, xfer); 2197 } 2198 2199 static void 2200 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2201 { 2202 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2203 2204 *lock = &sc->sc_lock; 2205 } 2206 2207 extern uint32_t usb_cookie_no; 2208 2209 /* 2210 * xHCI 4.3 2211 * Called when uhub_explore finds a new device (via usbd_new_device). 2212 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2213 * This function does: 2214 * Allocate and construct dev structure of default endpoint (ep0). 2215 * Allocate and open pipe of ep0. 2216 * Enable slot and initialize slot context. 2217 * Set Address. 2218 * Read initial device descriptor. 2219 * Determine initial MaxPacketSize (mps) by speed. 2220 * Read full device descriptor. 2221 * Register this device. 2222 * Finally state of device transitions ADDRESSED. 2223 */ 2224 static usbd_status 2225 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2226 int speed, int port, struct usbd_port *up) 2227 { 2228 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2229 struct usbd_device *dev; 2230 usbd_status err; 2231 usb_device_descriptor_t *dd; 2232 struct xhci_slot *xs; 2233 uint32_t *cp; 2234 2235 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2236 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2237 2238 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2239 if (dev == NULL) 2240 return USBD_NOMEM; 2241 2242 dev->ud_bus = bus; 2243 dev->ud_quirks = &usbd_no_quirk; 2244 dev->ud_addr = 0; 2245 dev->ud_ddesc.bMaxPacketSize = 0; 2246 dev->ud_depth = depth; 2247 dev->ud_powersrc = up; 2248 dev->ud_myhub = up->up_parent; 2249 dev->ud_speed = speed; 2250 dev->ud_langid = USBD_NOLANG; 2251 dev->ud_cookie.cookie = ++usb_cookie_no; 2252 2253 /* Set up default endpoint handle. */ 2254 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2255 /* doesn't matter, just don't let it uninitialized */ 2256 dev->ud_ep0.ue_toggle = 0; 2257 2258 /* Set up default endpoint descriptor. */ 2259 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2260 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2261 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2262 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2263 dev->ud_ep0desc.bInterval = 0; 2264 2265 /* 4.3, 4.8.2.1 */ 2266 switch (speed) { 2267 case USB_SPEED_SUPER: 2268 case USB_SPEED_SUPER_PLUS: 2269 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2270 break; 2271 case USB_SPEED_FULL: 2272 /* XXX using 64 as initial mps of ep0 in FS */ 2273 case USB_SPEED_HIGH: 2274 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2275 break; 2276 case USB_SPEED_LOW: 2277 default: 2278 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2279 break; 2280 } 2281 2282 up->up_dev = dev; 2283 2284 /* Establish the default pipe. */ 2285 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2286 &dev->ud_pipe0); 2287 if (err) { 2288 goto bad; 2289 } 2290 2291 dd = &dev->ud_ddesc; 2292 2293 if (depth == 0 && port == 0) { 2294 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2295 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2296 err = usbd_get_initial_ddesc(dev, dd); 2297 if (err) { 2298 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2299 goto bad; 2300 } 2301 2302 err = usbd_reload_device_desc(dev); 2303 if (err) { 2304 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2305 goto bad; 2306 } 2307 } else { 2308 uint8_t slot = 0; 2309 2310 /* 4.3.2 */ 2311 err = xhci_enable_slot(sc, &slot); 2312 if (err) { 2313 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2314 goto bad; 2315 } 2316 2317 xs = &sc->sc_slots[slot]; 2318 dev->ud_hcpriv = xs; 2319 2320 /* 4.3.3 initialize slot structure */ 2321 err = xhci_init_slot(dev, slot); 2322 if (err) { 2323 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2324 dev->ud_hcpriv = NULL; 2325 /* 2326 * We have to disable_slot here because 2327 * xs->xs_idx == 0 when xhci_init_slot fails, 2328 * in that case usbd_remove_dev won't work. 2329 */ 2330 mutex_enter(&sc->sc_lock); 2331 xhci_disable_slot(sc, slot); 2332 mutex_exit(&sc->sc_lock); 2333 goto bad; 2334 } 2335 2336 /* 4.3.4 Address Assignment */ 2337 err = xhci_set_address(dev, slot, false); 2338 if (err) { 2339 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2340 goto bad; 2341 } 2342 2343 /* Allow device time to set new address */ 2344 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2345 2346 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2347 //hexdump("slot context", cp, sc->sc_ctxsz); 2348 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2349 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2350 /* 2351 * XXX ensure we know when the hardware does something 2352 * we can't yet cope with 2353 */ 2354 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2355 dev->ud_addr = addr; 2356 2357 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2358 "addr %d already allocated", dev->ud_addr); 2359 /* 2360 * The root hub is given its own slot 2361 */ 2362 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2363 2364 err = usbd_get_initial_ddesc(dev, dd); 2365 if (err) { 2366 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2367 goto bad; 2368 } 2369 2370 /* 4.8.2.1 */ 2371 if (USB_IS_SS(speed)) { 2372 if (dd->bMaxPacketSize != 9) { 2373 printf("%s: invalid mps 2^%u for SS ep0," 2374 " using 512\n", 2375 device_xname(sc->sc_dev), 2376 dd->bMaxPacketSize); 2377 dd->bMaxPacketSize = 9; 2378 } 2379 USETW(dev->ud_ep0desc.wMaxPacketSize, 2380 (1 << dd->bMaxPacketSize)); 2381 } else 2382 USETW(dev->ud_ep0desc.wMaxPacketSize, 2383 dd->bMaxPacketSize); 2384 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2385 err = xhci_update_ep0_mps(sc, xs, 2386 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2387 if (err) { 2388 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2389 goto bad; 2390 } 2391 2392 err = usbd_reload_device_desc(dev); 2393 if (err) { 2394 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2395 goto bad; 2396 } 2397 } 2398 2399 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2400 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2401 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2402 dd->bDeviceClass, dd->bDeviceSubClass, 2403 dd->bDeviceProtocol, 0); 2404 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2405 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2406 dev->ud_speed); 2407 2408 usbd_get_device_strings(dev); 2409 2410 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2411 2412 if (depth == 0 && port == 0) { 2413 usbd_attach_roothub(parent, dev); 2414 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2415 return USBD_NORMAL_COMPLETION; 2416 } 2417 2418 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2419 bad: 2420 if (err != USBD_NORMAL_COMPLETION) { 2421 usbd_remove_device(dev, up); 2422 } 2423 2424 return err; 2425 } 2426 2427 static usbd_status 2428 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2429 size_t ntrb, size_t align) 2430 { 2431 usbd_status err; 2432 size_t size = ntrb * XHCI_TRB_SIZE; 2433 2434 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2435 2436 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2437 if (err) 2438 return err; 2439 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2440 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2441 xr->xr_trb = xhci_ring_trbv(xr, 0); 2442 xr->xr_ntrb = ntrb; 2443 xr->is_halted = false; 2444 xhci_host_dequeue(xr); 2445 2446 return USBD_NORMAL_COMPLETION; 2447 } 2448 2449 static void 2450 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2451 { 2452 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2453 mutex_destroy(&xr->xr_lock); 2454 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2455 } 2456 2457 static void 2458 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2459 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2460 { 2461 size_t i; 2462 u_int ri; 2463 u_int cs; 2464 uint64_t parameter; 2465 uint32_t status; 2466 uint32_t control; 2467 2468 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2469 2470 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2471 for (i = 0; i < ntrbs; i++) { 2472 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2473 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2474 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2475 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2476 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2477 } 2478 2479 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2480 2481 ri = xr->xr_ep; 2482 cs = xr->xr_cs; 2483 2484 /* 2485 * Although the xhci hardware can do scatter/gather dma from 2486 * arbitrary sized buffers, there is a non-obvious restriction 2487 * that a LINK trb is only allowed at the end of a burst of 2488 * transfers - which might be 16kB. 2489 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2490 * The simple solution is not to allow a LINK trb in the middle 2491 * of anything - as here. 2492 * XXX: (dsl) There are xhci controllers out there (eg some made by 2493 * ASMedia) that seem to lock up if they process a LINK trb but 2494 * cannot process the linked-to trb yet. 2495 * The code should write the 'cycle' bit on the link trb AFTER 2496 * adding the other trb. 2497 */ 2498 u_int firstep = xr->xr_ep; 2499 u_int firstcs = xr->xr_cs; 2500 2501 for (i = 0; i < ntrbs; ) { 2502 u_int oldri = ri; 2503 u_int oldcs = cs; 2504 2505 if (ri >= (xr->xr_ntrb - 1)) { 2506 /* Put Link TD at the end of ring */ 2507 parameter = xhci_ring_trbp(xr, 0); 2508 status = 0; 2509 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2510 XHCI_TRB_3_TC_BIT; 2511 xr->xr_cookies[ri] = NULL; 2512 xr->xr_ep = 0; 2513 xr->xr_cs ^= 1; 2514 ri = xr->xr_ep; 2515 cs = xr->xr_cs; 2516 } else { 2517 parameter = trbs[i].trb_0; 2518 status = trbs[i].trb_2; 2519 control = trbs[i].trb_3; 2520 2521 xr->xr_cookies[ri] = cookie; 2522 ri++; 2523 i++; 2524 } 2525 /* 2526 * If this is a first TRB, mark it invalid to prevent 2527 * xHC from running it immediately. 2528 */ 2529 if (oldri == firstep) { 2530 if (oldcs) { 2531 control &= ~XHCI_TRB_3_CYCLE_BIT; 2532 } else { 2533 control |= XHCI_TRB_3_CYCLE_BIT; 2534 } 2535 } else { 2536 if (oldcs) { 2537 control |= XHCI_TRB_3_CYCLE_BIT; 2538 } else { 2539 control &= ~XHCI_TRB_3_CYCLE_BIT; 2540 } 2541 } 2542 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2543 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2544 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2545 } 2546 2547 /* Now invert cycle bit of first TRB */ 2548 if (firstcs) { 2549 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2550 } else { 2551 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2552 } 2553 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2554 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2555 2556 xr->xr_ep = ri; 2557 xr->xr_cs = cs; 2558 2559 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2560 } 2561 2562 /* 2563 * Stop execution commands, purge all commands on command ring, and 2564 * rewind dequeue pointer. 2565 */ 2566 static void 2567 xhci_abort_command(struct xhci_softc *sc) 2568 { 2569 struct xhci_ring * const cr = &sc->sc_cr; 2570 uint64_t crcr; 2571 int i; 2572 2573 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2574 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2575 sc->sc_command_addr, 0, 0, 0); 2576 2577 mutex_enter(&cr->xr_lock); 2578 2579 /* 4.6.1.2 Aborting a Command */ 2580 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2581 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2582 2583 for (i = 0; i < 500; i++) { 2584 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2585 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2586 break; 2587 usb_delay_ms(&sc->sc_bus, 1); 2588 } 2589 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2590 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2591 /* reset HC here? */ 2592 } 2593 2594 /* reset command ring dequeue pointer */ 2595 cr->xr_ep = 0; 2596 cr->xr_cs = 1; 2597 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2598 2599 mutex_exit(&cr->xr_lock); 2600 } 2601 2602 /* 2603 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2604 * Command completion is notified by cv_signal from xhci_event_cmd() 2605 * (called from xhci_softint), or timed-out. 2606 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2607 * then do_command examines it. 2608 */ 2609 static usbd_status 2610 xhci_do_command_locked(struct xhci_softc * const sc, 2611 struct xhci_trb * const trb, int timeout) 2612 { 2613 struct xhci_ring * const cr = &sc->sc_cr; 2614 usbd_status err; 2615 2616 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2617 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2618 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2619 2620 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2621 KASSERT(mutex_owned(&sc->sc_lock)); 2622 2623 while (sc->sc_command_addr != 0) 2624 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2625 2626 /* 2627 * If enqueue pointer points at last of ring, it's Link TRB, 2628 * command TRB will be stored in 0th TRB. 2629 */ 2630 if (cr->xr_ep == cr->xr_ntrb - 1) 2631 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2632 else 2633 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2634 2635 sc->sc_resultpending = true; 2636 2637 mutex_enter(&cr->xr_lock); 2638 xhci_ring_put(sc, cr, NULL, trb, 1); 2639 mutex_exit(&cr->xr_lock); 2640 2641 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2642 2643 while (sc->sc_resultpending) { 2644 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2645 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2646 xhci_abort_command(sc); 2647 err = USBD_TIMEOUT; 2648 goto timedout; 2649 } 2650 } 2651 2652 trb->trb_0 = sc->sc_result_trb.trb_0; 2653 trb->trb_2 = sc->sc_result_trb.trb_2; 2654 trb->trb_3 = sc->sc_result_trb.trb_3; 2655 2656 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2657 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2658 2659 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2660 case XHCI_TRB_ERROR_SUCCESS: 2661 err = USBD_NORMAL_COMPLETION; 2662 break; 2663 default: 2664 case 192 ... 223: 2665 err = USBD_IOERROR; 2666 break; 2667 case 224 ... 255: 2668 err = USBD_NORMAL_COMPLETION; 2669 break; 2670 } 2671 2672 timedout: 2673 sc->sc_resultpending = false; 2674 sc->sc_command_addr = 0; 2675 cv_broadcast(&sc->sc_cmdbusy_cv); 2676 2677 return err; 2678 } 2679 2680 static usbd_status 2681 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2682 int timeout) 2683 { 2684 2685 mutex_enter(&sc->sc_lock); 2686 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2687 mutex_exit(&sc->sc_lock); 2688 2689 return ret; 2690 } 2691 2692 static usbd_status 2693 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2694 { 2695 struct xhci_trb trb; 2696 usbd_status err; 2697 2698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2699 2700 trb.trb_0 = 0; 2701 trb.trb_2 = 0; 2702 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2703 2704 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2705 if (err != USBD_NORMAL_COMPLETION) { 2706 return err; 2707 } 2708 2709 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2710 2711 return err; 2712 } 2713 2714 /* 2715 * xHCI 4.6.4 2716 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2717 * All endpoints in the slot should be stopped. 2718 * Should be called with sc_lock held. 2719 */ 2720 static usbd_status 2721 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2722 { 2723 struct xhci_trb trb; 2724 struct xhci_slot *xs; 2725 usbd_status err; 2726 2727 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2728 2729 if (sc->sc_dying) 2730 return USBD_IOERROR; 2731 2732 trb.trb_0 = 0; 2733 trb.trb_2 = 0; 2734 trb.trb_3 = htole32( 2735 XHCI_TRB_3_SLOT_SET(slot) | 2736 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2737 2738 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2739 2740 if (!err) { 2741 xs = &sc->sc_slots[slot]; 2742 if (xs->xs_idx != 0) { 2743 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2744 xhci_set_dcba(sc, 0, slot); 2745 memset(xs, 0, sizeof(*xs)); 2746 } 2747 } 2748 2749 return err; 2750 } 2751 2752 /* 2753 * Set address of device and transition slot state from ENABLED to ADDRESSED 2754 * if Block Setaddress Request (BSR) is false. 2755 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2756 * see xHCI 1.1 4.5.3, 3.3.4 2757 * Should be called without sc_lock held. 2758 */ 2759 static usbd_status 2760 xhci_address_device(struct xhci_softc * const sc, 2761 uint64_t icp, uint8_t slot_id, bool bsr) 2762 { 2763 struct xhci_trb trb; 2764 usbd_status err; 2765 2766 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2767 2768 trb.trb_0 = icp; 2769 trb.trb_2 = 0; 2770 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2771 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2772 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2773 2774 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2775 2776 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2777 err = USBD_NO_ADDR; 2778 2779 return err; 2780 } 2781 2782 static usbd_status 2783 xhci_update_ep0_mps(struct xhci_softc * const sc, 2784 struct xhci_slot * const xs, u_int mps) 2785 { 2786 struct xhci_trb trb; 2787 usbd_status err; 2788 uint32_t * cp; 2789 2790 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2791 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2792 2793 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2794 cp[0] = htole32(0); 2795 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2796 2797 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2798 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2799 2800 /* sync input contexts before they are read from memory */ 2801 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2802 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2803 sc->sc_ctxsz * 4); 2804 2805 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2806 trb.trb_2 = 0; 2807 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2808 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2809 2810 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2811 return err; 2812 } 2813 2814 static void 2815 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2816 { 2817 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2818 2819 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2820 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2821 &dcbaa[si], dcba, si, 0); 2822 2823 dcbaa[si] = htole64(dcba); 2824 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2825 BUS_DMASYNC_PREWRITE); 2826 } 2827 2828 /* 2829 * Allocate device and input context DMA buffer, and 2830 * TRB DMA buffer for each endpoint. 2831 */ 2832 static usbd_status 2833 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2834 { 2835 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2836 struct xhci_slot *xs; 2837 usbd_status err; 2838 u_int dci; 2839 2840 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2841 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2842 2843 xs = &sc->sc_slots[slot]; 2844 2845 /* allocate contexts */ 2846 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2847 &xs->xs_dc_dma); 2848 if (err) 2849 return err; 2850 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2851 2852 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2853 &xs->xs_ic_dma); 2854 if (err) 2855 goto bad1; 2856 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2857 2858 for (dci = 0; dci < 32; dci++) { 2859 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2860 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2861 if (dci == XHCI_DCI_SLOT) 2862 continue; 2863 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2864 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2865 if (err) { 2866 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2867 goto bad2; 2868 } 2869 } 2870 2871 bad2: 2872 if (err == USBD_NORMAL_COMPLETION) { 2873 xs->xs_idx = slot; 2874 } else { 2875 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2876 } 2877 2878 return err; 2879 2880 bad1: 2881 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2882 xs->xs_idx = 0; 2883 return err; 2884 } 2885 2886 static void 2887 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2888 int end_dci) 2889 { 2890 u_int dci; 2891 2892 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2893 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2894 0); 2895 2896 for (dci = start_dci; dci < end_dci; dci++) { 2897 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2898 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2899 } 2900 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2901 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2902 xs->xs_idx = 0; 2903 } 2904 2905 /* 2906 * Setup slot context, set Device Context Base Address, and issue 2907 * Set Address Device command. 2908 */ 2909 static usbd_status 2910 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2911 { 2912 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2913 struct xhci_slot *xs; 2914 usbd_status err; 2915 2916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2917 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2918 2919 xs = &sc->sc_slots[slot]; 2920 2921 xhci_setup_ctx(dev->ud_pipe0); 2922 2923 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2924 sc->sc_ctxsz * 3); 2925 2926 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2927 2928 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2929 2930 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2931 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2932 sc->sc_ctxsz * 2); 2933 2934 return err; 2935 } 2936 2937 /* 2938 * 4.8.2, 6.2.3.2 2939 * construct slot/endpoint context parameters and do syncmem 2940 */ 2941 static void 2942 xhci_setup_ctx(struct usbd_pipe *pipe) 2943 { 2944 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2945 struct usbd_device *dev = pipe->up_dev; 2946 struct xhci_slot * const xs = dev->ud_hcpriv; 2947 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2948 const u_int dci = xhci_ep_get_dci(ed); 2949 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2950 uint32_t *cp; 2951 uint16_t mps = UGETW(ed->wMaxPacketSize); 2952 uint8_t speed = dev->ud_speed; 2953 uint8_t ival = ed->bInterval; 2954 2955 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2956 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2957 speed); 2958 2959 /* set up initial input control context */ 2960 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2961 cp[0] = htole32(0); 2962 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2963 if (dci == XHCI_DCI_EP_CONTROL) 2964 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2965 cp[7] = htole32(0); 2966 2967 /* set up input slot context */ 2968 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2969 cp[0] = 2970 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2971 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2972 cp[1] = 0; 2973 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2974 cp[3] = 0; 2975 xhci_setup_route(pipe, cp); 2976 xhci_setup_tthub(pipe, cp); 2977 2978 cp[0] = htole32(cp[0]); 2979 cp[1] = htole32(cp[1]); 2980 cp[2] = htole32(cp[2]); 2981 cp[3] = htole32(cp[3]); 2982 2983 /* set up input endpoint context */ 2984 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2985 cp[0] = 2986 XHCI_EPCTX_0_EPSTATE_SET(0) | 2987 XHCI_EPCTX_0_MULT_SET(0) | 2988 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2989 XHCI_EPCTX_0_LSA_SET(0) | 2990 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2991 cp[1] = 2992 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2993 XHCI_EPCTX_1_HID_SET(0) | 2994 XHCI_EPCTX_1_MAXB_SET(0); 2995 2996 if (xfertype != UE_ISOCHRONOUS) 2997 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2998 2999 if (xfertype == UE_CONTROL) 3000 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3001 else if (USB_IS_SS(speed)) 3002 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3003 else 3004 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3005 3006 xhci_setup_maxburst(pipe, cp); 3007 3008 switch (xfertype) { 3009 case UE_CONTROL: 3010 break; 3011 case UE_BULK: 3012 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3013 break; 3014 case UE_INTERRUPT: 3015 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3016 ival = pipe->up_interval; 3017 3018 ival = xhci_bival2ival(ival, speed); 3019 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3020 break; 3021 case UE_ISOCHRONOUS: 3022 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3023 ival = pipe->up_interval; 3024 3025 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3026 if (speed == USB_SPEED_FULL) 3027 ival += 3; /* 1ms -> 125us */ 3028 ival--; 3029 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3030 break; 3031 default: 3032 break; 3033 } 3034 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3035 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3036 3037 /* rewind TR dequeue pointer in xHC */ 3038 /* can't use xhci_ep_get_dci() yet? */ 3039 *(uint64_t *)(&cp[2]) = htole64( 3040 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3041 XHCI_EPCTX_2_DCS_SET(1)); 3042 3043 cp[0] = htole32(cp[0]); 3044 cp[1] = htole32(cp[1]); 3045 cp[4] = htole32(cp[4]); 3046 3047 /* rewind TR dequeue pointer in driver */ 3048 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3049 mutex_enter(&xr->xr_lock); 3050 xhci_host_dequeue(xr); 3051 mutex_exit(&xr->xr_lock); 3052 3053 /* sync input contexts before they are read from memory */ 3054 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3055 } 3056 3057 /* 3058 * Setup route string and roothub port of given device for slot context 3059 */ 3060 static void 3061 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3062 { 3063 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3064 struct usbd_device *dev = pipe->up_dev; 3065 struct usbd_port *up = dev->ud_powersrc; 3066 struct usbd_device *hub; 3067 struct usbd_device *adev; 3068 uint8_t rhport = 0; 3069 uint32_t route = 0; 3070 3071 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3072 3073 /* Locate root hub port and Determine route string */ 3074 /* 4.3.3 route string does not include roothub port */ 3075 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3076 uint32_t dep; 3077 3078 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3079 hub, hub->ud_depth, hub->ud_powersrc, 3080 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3081 3082 if (hub->ud_powersrc == NULL) 3083 break; 3084 dep = hub->ud_depth; 3085 if (dep == 0) 3086 break; 3087 rhport = hub->ud_powersrc->up_portno; 3088 if (dep > USB_HUB_MAX_DEPTH) 3089 continue; 3090 3091 route |= 3092 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3093 << ((dep - 1) * 4); 3094 } 3095 route = route >> 4; 3096 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3097 3098 /* Locate port on upstream high speed hub */ 3099 for (adev = dev, hub = up->up_parent; 3100 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3101 adev = hub, hub = hub->ud_myhub) 3102 ; 3103 if (hub) { 3104 int p; 3105 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3106 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3107 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3108 goto found; 3109 } 3110 } 3111 panic("%s: cannot find HS port", __func__); 3112 found: 3113 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3114 } else { 3115 dev->ud_myhsport = NULL; 3116 } 3117 3118 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3119 3120 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3121 ctlrport, route, hub); 3122 3123 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3124 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3125 } 3126 3127 /* 3128 * Setup whether device is hub, whether device uses MTT, and 3129 * TT informations if it uses MTT. 3130 */ 3131 static void 3132 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3133 { 3134 struct usbd_device *dev = pipe->up_dev; 3135 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3136 uint32_t speed = dev->ud_speed; 3137 uint8_t tthubslot, ttportnum; 3138 bool ishub; 3139 bool usemtt; 3140 3141 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3142 3143 /* 3144 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3145 * tthubslot: 3146 * This is the slot ID of parent HS hub 3147 * if LS/FS device is connected && connected through HS hub. 3148 * This is 0 if device is not LS/FS device || 3149 * parent hub is not HS hub || 3150 * attached to root hub. 3151 * ttportnum: 3152 * This is the downstream facing port of parent HS hub 3153 * if LS/FS device is connected. 3154 * This is 0 if device is not LS/FS device || 3155 * parent hub is not HS hub || 3156 * attached to root hub. 3157 */ 3158 if (dev->ud_myhsport != NULL && 3159 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3160 (dev->ud_myhub != NULL && 3161 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3162 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3163 ttportnum = dev->ud_myhsport->up_portno; 3164 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3165 } else { 3166 ttportnum = 0; 3167 tthubslot = 0; 3168 } 3169 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3170 dev->ud_myhsport, ttportnum, tthubslot, 0); 3171 3172 /* ishub is valid after reading UDESC_DEVICE */ 3173 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3174 3175 /* dev->ud_hub is valid after reading UDESC_HUB */ 3176 if (ishub && dev->ud_hub) { 3177 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3178 uint8_t ttt = 3179 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3180 3181 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3182 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3183 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3184 } 3185 3186 #define IS_TTHUB(dd) \ 3187 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3188 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3189 3190 /* 3191 * MTT flag is set if 3192 * 1. this is HS hub && MTT is enabled 3193 * or 3194 * 2. this is not hub && this is LS or FS device && 3195 * MTT of parent HS hub (and its parent, too) is enabled 3196 */ 3197 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3198 usemtt = true; 3199 else if (!ishub && 3200 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3201 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3202 (dev->ud_myhub != NULL && 3203 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3204 dev->ud_myhsport != NULL && 3205 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3206 usemtt = true; 3207 else 3208 usemtt = false; 3209 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3210 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3211 3212 #undef IS_TTHUB 3213 3214 cp[0] |= 3215 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3216 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3217 cp[2] |= 3218 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3219 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3220 } 3221 3222 /* set up params for periodic endpoint */ 3223 static void 3224 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3225 { 3226 struct usbd_device *dev = pipe->up_dev; 3227 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3228 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3229 usbd_desc_iter_t iter; 3230 const usb_cdc_descriptor_t *cdcd; 3231 uint32_t maxb = 0; 3232 uint16_t mps = UGETW(ed->wMaxPacketSize); 3233 uint8_t speed = dev->ud_speed; 3234 uint8_t ep; 3235 3236 /* config desc is NULL when opening ep0 */ 3237 if (dev == NULL || dev->ud_cdesc == NULL) 3238 goto no_cdcd; 3239 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3240 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3241 if (cdcd == NULL) 3242 goto no_cdcd; 3243 usb_desc_iter_init(dev, &iter); 3244 iter.cur = (const void *)cdcd; 3245 3246 /* find endpoint_ss_comp desc for ep of this pipe */ 3247 for (ep = 0;;) { 3248 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3249 if (cdcd == NULL) 3250 break; 3251 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3252 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3253 bEndpointAddress; 3254 if (UE_GET_ADDR(ep) == 3255 UE_GET_ADDR(ed->bEndpointAddress)) { 3256 cdcd = (const usb_cdc_descriptor_t *) 3257 usb_desc_iter_next(&iter); 3258 break; 3259 } 3260 ep = 0; 3261 } 3262 } 3263 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3264 const usb_endpoint_ss_comp_descriptor_t * esscd = 3265 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3266 maxb = esscd->bMaxBurst; 3267 } 3268 3269 no_cdcd: 3270 /* 6.2.3.4, 4.8.2.4 */ 3271 if (USB_IS_SS(speed)) { 3272 /* USB 3.1 9.6.6 */ 3273 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3274 /* USB 3.1 9.6.7 */ 3275 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3276 #ifdef notyet 3277 if (xfertype == UE_ISOCHRONOUS) { 3278 } 3279 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3280 /* use ESIT */ 3281 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3282 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3283 3284 /* XXX if LEC = 1, set ESIT instead */ 3285 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3286 } else { 3287 /* use ival */ 3288 } 3289 #endif 3290 } else { 3291 /* USB 2.0 9.6.6 */ 3292 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3293 3294 /* 6.2.3.4 */ 3295 if (speed == USB_SPEED_HIGH && 3296 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3297 maxb = UE_GET_TRANS(mps); 3298 } else { 3299 /* LS/FS or HS CTRL or HS BULK */ 3300 maxb = 0; 3301 } 3302 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3303 } 3304 } 3305 3306 /* 3307 * Convert endpoint bInterval value to endpoint context interval value 3308 * for Interrupt pipe. 3309 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3310 */ 3311 static uint32_t 3312 xhci_bival2ival(uint32_t ival, uint32_t speed) 3313 { 3314 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3315 int i; 3316 3317 /* 3318 * round ival down to "the nearest base 2 multiple of 3319 * bInterval * 8". 3320 * bInterval is at most 255 as its type is uByte. 3321 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3322 */ 3323 for (i = 10; i > 0; i--) { 3324 if ((ival * 8) >= (1 << i)) 3325 break; 3326 } 3327 ival = i; 3328 } else { 3329 /* Interval = bInterval-1 for SS/HS */ 3330 ival--; 3331 } 3332 3333 return ival; 3334 } 3335 3336 /* ----- */ 3337 3338 static void 3339 xhci_noop(struct usbd_pipe *pipe) 3340 { 3341 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3342 } 3343 3344 /* 3345 * Process root hub request. 3346 */ 3347 static int 3348 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3349 void *buf, int buflen) 3350 { 3351 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3352 usb_port_status_t ps; 3353 int l, totlen = 0; 3354 uint16_t len, value, index; 3355 int port, i; 3356 uint32_t v; 3357 3358 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3359 3360 if (sc->sc_dying) 3361 return -1; 3362 3363 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3364 3365 len = UGETW(req->wLength); 3366 value = UGETW(req->wValue); 3367 index = UGETW(req->wIndex); 3368 3369 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3370 req->bmRequestType | (req->bRequest << 8), value, index, len); 3371 3372 #define C(x,y) ((x) | ((y) << 8)) 3373 switch (C(req->bRequest, req->bmRequestType)) { 3374 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3375 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3376 if (len == 0) 3377 break; 3378 switch (value) { 3379 case C(0, UDESC_DEVICE): { 3380 usb_device_descriptor_t devd; 3381 totlen = min(buflen, sizeof(devd)); 3382 memcpy(&devd, buf, totlen); 3383 USETW(devd.idVendor, sc->sc_id_vendor); 3384 memcpy(buf, &devd, totlen); 3385 break; 3386 } 3387 #define sd ((usb_string_descriptor_t *)buf) 3388 case C(1, UDESC_STRING): 3389 /* Vendor */ 3390 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3391 break; 3392 case C(2, UDESC_STRING): 3393 /* Product */ 3394 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3395 break; 3396 #undef sd 3397 default: 3398 /* default from usbroothub */ 3399 return buflen; 3400 } 3401 break; 3402 3403 /* Hub requests */ 3404 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3405 break; 3406 /* Clear Port Feature request */ 3407 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3408 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3409 3410 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3411 index, value, bn, cp); 3412 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3413 return -1; 3414 } 3415 port = XHCI_PORTSC(cp); 3416 v = xhci_op_read_4(sc, port); 3417 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3418 v &= ~XHCI_PS_CLEAR; 3419 switch (value) { 3420 case UHF_PORT_ENABLE: 3421 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3422 break; 3423 case UHF_PORT_SUSPEND: 3424 return -1; 3425 case UHF_PORT_POWER: 3426 break; 3427 case UHF_PORT_TEST: 3428 case UHF_PORT_INDICATOR: 3429 return -1; 3430 case UHF_C_PORT_CONNECTION: 3431 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3432 break; 3433 case UHF_C_PORT_ENABLE: 3434 case UHF_C_PORT_SUSPEND: 3435 case UHF_C_PORT_OVER_CURRENT: 3436 return -1; 3437 case UHF_C_BH_PORT_RESET: 3438 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3439 break; 3440 case UHF_C_PORT_RESET: 3441 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3442 break; 3443 case UHF_C_PORT_LINK_STATE: 3444 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3445 break; 3446 case UHF_C_PORT_CONFIG_ERROR: 3447 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3448 break; 3449 default: 3450 return -1; 3451 } 3452 break; 3453 } 3454 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3455 if (len == 0) 3456 break; 3457 if ((value & 0xff) != 0) { 3458 return -1; 3459 } 3460 usb_hub_descriptor_t hubd; 3461 3462 totlen = min(buflen, sizeof(hubd)); 3463 memcpy(&hubd, buf, totlen); 3464 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3465 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3466 hubd.bPwrOn2PwrGood = 200; 3467 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3468 /* XXX can't find out? */ 3469 hubd.DeviceRemovable[i++] = 0; 3470 } 3471 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3472 totlen = min(totlen, hubd.bDescLength); 3473 memcpy(buf, &hubd, totlen); 3474 break; 3475 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3476 if (len != 4) { 3477 return -1; 3478 } 3479 memset(buf, 0, len); /* ? XXX */ 3480 totlen = len; 3481 break; 3482 /* Get Port Status request */ 3483 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3484 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3485 3486 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3487 0); 3488 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3489 return -1; 3490 } 3491 if (len != 4) { 3492 return -1; 3493 } 3494 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3495 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3496 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3497 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3498 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3499 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3500 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3501 if (v & XHCI_PS_PR) i |= UPS_RESET; 3502 if (v & XHCI_PS_PP) { 3503 if (i & UPS_OTHER_SPEED) 3504 i |= UPS_PORT_POWER_SS; 3505 else 3506 i |= UPS_PORT_POWER; 3507 } 3508 if (i & UPS_OTHER_SPEED) 3509 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3510 if (sc->sc_vendor_port_status) 3511 i = sc->sc_vendor_port_status(sc, v, i); 3512 USETW(ps.wPortStatus, i); 3513 i = 0; 3514 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3515 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3516 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3517 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3518 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3519 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3520 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3521 USETW(ps.wPortChange, i); 3522 totlen = min(len, sizeof(ps)); 3523 memcpy(buf, &ps, totlen); 3524 break; 3525 } 3526 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3527 return -1; 3528 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3529 break; 3530 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3531 break; 3532 /* Set Port Feature request */ 3533 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3534 int optval = (index >> 8) & 0xff; 3535 index &= 0xff; 3536 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3537 return -1; 3538 } 3539 3540 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3541 3542 port = XHCI_PORTSC(cp); 3543 v = xhci_op_read_4(sc, port); 3544 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3545 v &= ~XHCI_PS_CLEAR; 3546 switch (value) { 3547 case UHF_PORT_ENABLE: 3548 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3549 break; 3550 case UHF_PORT_SUSPEND: 3551 /* XXX suspend */ 3552 break; 3553 case UHF_PORT_RESET: 3554 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3555 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3556 /* Wait for reset to complete. */ 3557 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3558 if (sc->sc_dying) { 3559 return -1; 3560 } 3561 v = xhci_op_read_4(sc, port); 3562 if (v & XHCI_PS_PR) { 3563 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3564 usb_delay_ms(&sc->sc_bus, 10); 3565 /* XXX */ 3566 } 3567 break; 3568 case UHF_PORT_POWER: 3569 /* XXX power control */ 3570 break; 3571 /* XXX more */ 3572 case UHF_C_PORT_RESET: 3573 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3574 break; 3575 case UHF_PORT_U1_TIMEOUT: 3576 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3577 return -1; 3578 } 3579 port = XHCI_PORTPMSC(cp); 3580 v = xhci_op_read_4(sc, port); 3581 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3582 v &= ~XHCI_PM3_U1TO_SET(0xff); 3583 v |= XHCI_PM3_U1TO_SET(optval); 3584 xhci_op_write_4(sc, port, v); 3585 break; 3586 case UHF_PORT_U2_TIMEOUT: 3587 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3588 return -1; 3589 } 3590 port = XHCI_PORTPMSC(cp); 3591 v = xhci_op_read_4(sc, port); 3592 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3593 v &= ~XHCI_PM3_U2TO_SET(0xff); 3594 v |= XHCI_PM3_U2TO_SET(optval); 3595 xhci_op_write_4(sc, port, v); 3596 break; 3597 default: 3598 return -1; 3599 } 3600 } 3601 break; 3602 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3603 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3604 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3605 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3606 break; 3607 default: 3608 /* default from usbroothub */ 3609 return buflen; 3610 } 3611 3612 return totlen; 3613 } 3614 3615 /* root hub interrupt */ 3616 3617 static usbd_status 3618 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3619 { 3620 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3621 usbd_status err; 3622 3623 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3624 3625 /* Insert last in queue. */ 3626 mutex_enter(&sc->sc_lock); 3627 err = usb_insert_transfer(xfer); 3628 mutex_exit(&sc->sc_lock); 3629 if (err) 3630 return err; 3631 3632 /* Pipe isn't running, start first */ 3633 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3634 } 3635 3636 /* Wait for roothub port status/change */ 3637 static usbd_status 3638 xhci_root_intr_start(struct usbd_xfer *xfer) 3639 { 3640 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3641 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3642 3643 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3644 3645 if (sc->sc_dying) 3646 return USBD_IOERROR; 3647 3648 mutex_enter(&sc->sc_lock); 3649 sc->sc_intrxfer[bn] = xfer; 3650 mutex_exit(&sc->sc_lock); 3651 3652 return USBD_IN_PROGRESS; 3653 } 3654 3655 static void 3656 xhci_root_intr_abort(struct usbd_xfer *xfer) 3657 { 3658 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3659 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3660 3661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3662 3663 KASSERT(mutex_owned(&sc->sc_lock)); 3664 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3665 3666 sc->sc_intrxfer[bn] = NULL; 3667 3668 xfer->ux_status = USBD_CANCELLED; 3669 usb_transfer_complete(xfer); 3670 } 3671 3672 static void 3673 xhci_root_intr_close(struct usbd_pipe *pipe) 3674 { 3675 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3676 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3677 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3678 3679 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3680 3681 KASSERT(mutex_owned(&sc->sc_lock)); 3682 3683 sc->sc_intrxfer[bn] = NULL; 3684 } 3685 3686 static void 3687 xhci_root_intr_done(struct usbd_xfer *xfer) 3688 { 3689 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3690 3691 } 3692 3693 /* -------------- */ 3694 /* device control */ 3695 3696 static usbd_status 3697 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3698 { 3699 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3700 usbd_status err; 3701 3702 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3703 3704 /* Insert last in queue. */ 3705 mutex_enter(&sc->sc_lock); 3706 err = usb_insert_transfer(xfer); 3707 mutex_exit(&sc->sc_lock); 3708 if (err) 3709 return err; 3710 3711 /* Pipe isn't running, start first */ 3712 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3713 } 3714 3715 static usbd_status 3716 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3717 { 3718 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3719 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3720 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3721 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3722 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3723 usb_device_request_t * const req = &xfer->ux_request; 3724 const int isread = usbd_xfer_isread(xfer); 3725 const uint32_t len = UGETW(req->wLength); 3726 usb_dma_t * const dma = &xfer->ux_dmabuf; 3727 uint64_t parameter; 3728 uint32_t status; 3729 uint32_t control; 3730 u_int i; 3731 3732 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3733 DPRINTFN(12, "req: %04x %04x %04x %04x", 3734 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3735 UGETW(req->wIndex), UGETW(req->wLength)); 3736 3737 /* we rely on the bottom bits for extra info */ 3738 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3739 (uintptr_t) xfer); 3740 3741 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3742 3743 i = 0; 3744 3745 /* setup phase */ 3746 memcpy(¶meter, req, sizeof(parameter)); 3747 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3748 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3749 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3750 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3751 XHCI_TRB_3_IDT_BIT; 3752 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3753 3754 if (len != 0) { 3755 /* data phase */ 3756 parameter = DMAADDR(dma, 0); 3757 KASSERTMSG(len <= 0x10000, "len %d", len); 3758 status = XHCI_TRB_2_IRQ_SET(0) | 3759 XHCI_TRB_2_TDSZ_SET(1) | 3760 XHCI_TRB_2_BYTES_SET(len); 3761 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3762 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3763 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3764 XHCI_TRB_3_IOC_BIT; 3765 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3766 } 3767 3768 parameter = 0; 3769 status = XHCI_TRB_2_IRQ_SET(0); 3770 /* the status stage has inverted direction */ 3771 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3772 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3773 XHCI_TRB_3_IOC_BIT; 3774 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3775 3776 mutex_enter(&tr->xr_lock); 3777 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3778 mutex_exit(&tr->xr_lock); 3779 3780 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3781 3782 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3783 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3784 xhci_timeout, xfer); 3785 } 3786 3787 return USBD_IN_PROGRESS; 3788 } 3789 3790 static void 3791 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3792 { 3793 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3794 usb_device_request_t *req = &xfer->ux_request; 3795 int len = UGETW(req->wLength); 3796 int rd = req->bmRequestType & UT_READ; 3797 3798 if (len) 3799 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3800 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3801 } 3802 3803 static void 3804 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3805 { 3806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3807 3808 xhci_abort_xfer(xfer, USBD_CANCELLED); 3809 } 3810 3811 static void 3812 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3813 { 3814 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3815 3816 xhci_close_pipe(pipe); 3817 } 3818 3819 /* ------------------ */ 3820 /* device isochronous */ 3821 3822 /* ----------- */ 3823 /* device bulk */ 3824 3825 static usbd_status 3826 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3827 { 3828 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3829 usbd_status err; 3830 3831 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3832 3833 /* Insert last in queue. */ 3834 mutex_enter(&sc->sc_lock); 3835 err = usb_insert_transfer(xfer); 3836 mutex_exit(&sc->sc_lock); 3837 if (err) 3838 return err; 3839 3840 /* 3841 * Pipe isn't running (otherwise err would be USBD_INPROG), 3842 * so start it first. 3843 */ 3844 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3845 } 3846 3847 static usbd_status 3848 xhci_device_bulk_start(struct usbd_xfer *xfer) 3849 { 3850 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3851 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3852 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3853 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3854 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3855 const uint32_t len = xfer->ux_length; 3856 usb_dma_t * const dma = &xfer->ux_dmabuf; 3857 uint64_t parameter; 3858 uint32_t status; 3859 uint32_t control; 3860 u_int i = 0; 3861 3862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3863 3864 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3865 3866 if (sc->sc_dying) 3867 return USBD_IOERROR; 3868 3869 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3870 3871 parameter = DMAADDR(dma, 0); 3872 /* 3873 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3874 * If the user supplied buffer crosses such a boundary then 2 3875 * (or more) TRB should be used. 3876 * If multiple TRB are used the td_size field must be set correctly. 3877 * For v1.0 devices (like ivy bridge) this is the number of usb data 3878 * blocks needed to complete the transfer. 3879 * Setting it to 1 in the last TRB causes an extra zero-length 3880 * data block be sent. 3881 * The earlier documentation differs, I don't know how it behaves. 3882 */ 3883 KASSERTMSG(len <= 0x10000, "len %d", len); 3884 status = XHCI_TRB_2_IRQ_SET(0) | 3885 XHCI_TRB_2_TDSZ_SET(1) | 3886 XHCI_TRB_2_BYTES_SET(len); 3887 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3888 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3889 XHCI_TRB_3_IOC_BIT; 3890 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3891 3892 mutex_enter(&tr->xr_lock); 3893 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3894 mutex_exit(&tr->xr_lock); 3895 3896 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3897 3898 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3899 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3900 xhci_timeout, xfer); 3901 } 3902 3903 return USBD_IN_PROGRESS; 3904 } 3905 3906 static void 3907 xhci_device_bulk_done(struct usbd_xfer *xfer) 3908 { 3909 #ifdef USB_DEBUG 3910 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3911 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3912 #endif 3913 const int isread = usbd_xfer_isread(xfer); 3914 3915 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3916 3917 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3918 3919 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3920 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3921 } 3922 3923 static void 3924 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3925 { 3926 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3927 3928 xhci_abort_xfer(xfer, USBD_CANCELLED); 3929 } 3930 3931 static void 3932 xhci_device_bulk_close(struct usbd_pipe *pipe) 3933 { 3934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3935 3936 xhci_close_pipe(pipe); 3937 } 3938 3939 /* ---------------- */ 3940 /* device interrupt */ 3941 3942 static usbd_status 3943 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3944 { 3945 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3946 usbd_status err; 3947 3948 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3949 3950 /* Insert last in queue. */ 3951 mutex_enter(&sc->sc_lock); 3952 err = usb_insert_transfer(xfer); 3953 mutex_exit(&sc->sc_lock); 3954 if (err) 3955 return err; 3956 3957 /* 3958 * Pipe isn't running (otherwise err would be USBD_INPROG), 3959 * so start it first. 3960 */ 3961 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3962 } 3963 3964 static usbd_status 3965 xhci_device_intr_start(struct usbd_xfer *xfer) 3966 { 3967 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3968 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3969 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3970 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3971 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3972 const uint32_t len = xfer->ux_length; 3973 usb_dma_t * const dma = &xfer->ux_dmabuf; 3974 uint64_t parameter; 3975 uint32_t status; 3976 uint32_t control; 3977 u_int i = 0; 3978 3979 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3980 3981 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3982 3983 if (sc->sc_dying) 3984 return USBD_IOERROR; 3985 3986 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3987 3988 parameter = DMAADDR(dma, 0); 3989 KASSERTMSG(len <= 0x10000, "len %d", len); 3990 status = XHCI_TRB_2_IRQ_SET(0) | 3991 XHCI_TRB_2_TDSZ_SET(1) | 3992 XHCI_TRB_2_BYTES_SET(len); 3993 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3994 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3995 XHCI_TRB_3_IOC_BIT; 3996 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3997 3998 mutex_enter(&tr->xr_lock); 3999 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4000 mutex_exit(&tr->xr_lock); 4001 4002 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4003 4004 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4005 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4006 xhci_timeout, xfer); 4007 } 4008 4009 return USBD_IN_PROGRESS; 4010 } 4011 4012 static void 4013 xhci_device_intr_done(struct usbd_xfer *xfer) 4014 { 4015 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4016 #ifdef USB_DEBUG 4017 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4018 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4019 #endif 4020 const int isread = usbd_xfer_isread(xfer); 4021 4022 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4023 4024 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4025 4026 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4027 4028 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4029 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4030 } 4031 4032 static void 4033 xhci_device_intr_abort(struct usbd_xfer *xfer) 4034 { 4035 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4036 4037 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4038 4039 KASSERT(mutex_owned(&sc->sc_lock)); 4040 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4041 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4042 xhci_abort_xfer(xfer, USBD_CANCELLED); 4043 } 4044 4045 static void 4046 xhci_device_intr_close(struct usbd_pipe *pipe) 4047 { 4048 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4049 4050 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4051 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4052 4053 xhci_close_pipe(pipe); 4054 } 4055 4056 /* ------------ */ 4057 4058 static void 4059 xhci_timeout(void *addr) 4060 { 4061 struct xhci_xfer * const xx = addr; 4062 struct usbd_xfer * const xfer = &xx->xx_xfer; 4063 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4064 4065 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4066 4067 if (sc->sc_dying) { 4068 return; 4069 } 4070 4071 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4072 USB_TASKQ_MPSAFE); 4073 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4074 USB_TASKQ_HC); 4075 } 4076 4077 static void 4078 xhci_timeout_task(void *addr) 4079 { 4080 struct usbd_xfer * const xfer = addr; 4081 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4082 4083 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4084 4085 mutex_enter(&sc->sc_lock); 4086 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4087 mutex_exit(&sc->sc_lock); 4088 } 4089
Indexes created Wed Oct 01 18:09:54 GMT 2025