xhci.c revision 1.23.2.9
1 /* $NetBSD: xhci.c,v 1.23.2.9 2019/09/17 18:04:15 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.23.2.9 2019/09/17 18:04:15 martin Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 /* 693 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 694 * prevent system hang (Errata). 695 */ 696 usb_delay_ms(&sc->sc_bus, 1); 697 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 698 if ((usbcmd & XHCI_CMD_HCRST) == 0) 699 break; 700 } 701 if (i >= XHCI_WAIT_HCRST) { 702 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 703 return EIO; 704 } 705 706 /* Check controller not ready */ 707 for (i = 0; i < XHCI_WAIT_CNR; i++) { 708 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 709 if ((usbsts & XHCI_STS_CNR) == 0) 710 break; 711 usb_delay_ms(&sc->sc_bus, 1); 712 } 713 if (i >= XHCI_WAIT_CNR) { 714 aprint_error_dev(sc->sc_dev, 715 "controller not ready timeout after reset\n"); 716 return EIO; 717 } 718 719 return 0; 720 } 721 722 723 static void 724 hexdump(const char *msg, const void *base, size_t len) 725 { 726 #if 0 727 size_t cnt; 728 const uint32_t *p; 729 extern paddr_t vtophys(vaddr_t); 730 731 p = base; 732 cnt = 0; 733 734 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 735 (void *)vtophys((vaddr_t)base)); 736 737 while (cnt < len) { 738 if (cnt % 16 == 0) 739 printf("%p: ", p); 740 else if (cnt % 8 == 0) 741 printf(" |"); 742 printf(" %08x", *p++); 743 cnt += 4; 744 if (cnt % 16 == 0) 745 printf("\n"); 746 } 747 if (cnt % 16 != 0) 748 printf("\n"); 749 #endif 750 } 751 752 /* 7.2 xHCI Support Protocol Capability */ 753 static void 754 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 755 { 756 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 757 758 /* XXX Cache this lot */ 759 760 const uint32_t w0 = xhci_read_4(sc, ecp); 761 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 762 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 763 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 764 765 aprint_debug_dev(sc->sc_dev, 766 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 767 768 if (w4 != XHCI_XECP_USBID) 769 return; 770 771 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 772 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 773 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 774 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 775 776 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 777 switch (mm) { 778 case 0x0200: 779 case 0x0300: 780 case 0x0301: 781 case 0x0310: 782 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 783 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 784 break; 785 default: 786 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 787 major, minor); 788 return; 789 } 790 791 const size_t bus = (major == 3) ? 0 : 1; 792 793 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 794 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 795 if (sc->sc_ctlrportmap[cp] != 0) { 796 aprint_error_dev(sc->sc_dev, "contoller port %zu " 797 "already assigned", cp); 798 continue; 799 } 800 801 sc->sc_ctlrportbus[cp / NBBY] |= 802 bus == 0 ? 0 : __BIT(cp % NBBY); 803 804 const size_t rhp = sc->sc_rhportcount[bus]++; 805 806 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 807 "bus %zu rhp %zu is %d", bus, rhp, 808 sc->sc_rhportmap[bus][rhp]); 809 810 sc->sc_rhportmap[bus][rhp] = cp + 1; 811 sc->sc_ctlrportmap[cp] = rhp + 1; 812 } 813 } 814 815 /* Process extended capabilities */ 816 static void 817 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 818 { 819 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 820 821 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 822 while (ecp != 0) { 823 uint32_t ecr = xhci_read_4(sc, ecp); 824 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 825 switch (XHCI_XECP_ID(ecr)) { 826 case XHCI_ID_PROTOCOLS: { 827 xhci_id_protocols(sc, ecp); 828 break; 829 } 830 case XHCI_ID_USB_LEGACY: { 831 uint8_t bios_sem; 832 833 /* Take host controller ownership from BIOS */ 834 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 835 if (bios_sem) { 836 /* sets xHCI to be owned by OS */ 837 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 838 aprint_debug_dev(sc->sc_dev, 839 "waiting for BIOS to give up control\n"); 840 for (int i = 0; i < 5000; i++) { 841 bios_sem = xhci_read_1(sc, ecp + 842 XHCI_XECP_BIOS_SEM); 843 if (bios_sem == 0) 844 break; 845 DELAY(1000); 846 } 847 if (bios_sem) { 848 aprint_error_dev(sc->sc_dev, 849 "timed out waiting for BIOS\n"); 850 } 851 } 852 break; 853 } 854 default: 855 break; 856 } 857 ecr = xhci_read_4(sc, ecp); 858 if (XHCI_XECP_NEXT(ecr) == 0) { 859 ecp = 0; 860 } else { 861 ecp += XHCI_XECP_NEXT(ecr) * 4; 862 } 863 } 864 } 865 866 #define XHCI_HCCPREV1_BITS \ 867 "\177\020" /* New bitmask */ \ 868 "f\020\020XECP\0" \ 869 "f\014\4MAXPSA\0" \ 870 "b\013CFC\0" \ 871 "b\012SEC\0" \ 872 "b\011SBD\0" \ 873 "b\010FSE\0" \ 874 "b\7NSS\0" \ 875 "b\6LTC\0" \ 876 "b\5LHRC\0" \ 877 "b\4PIND\0" \ 878 "b\3PPC\0" \ 879 "b\2CZC\0" \ 880 "b\1BNC\0" \ 881 "b\0AC64\0" \ 882 "\0" 883 #define XHCI_HCCV1_x_BITS \ 884 "\177\020" /* New bitmask */ \ 885 "f\020\020XECP\0" \ 886 "f\014\4MAXPSA\0" \ 887 "b\013CFC\0" \ 888 "b\012SEC\0" \ 889 "b\011SPC\0" \ 890 "b\010PAE\0" \ 891 "b\7NSS\0" \ 892 "b\6LTC\0" \ 893 "b\5LHRC\0" \ 894 "b\4PIND\0" \ 895 "b\3PPC\0" \ 896 "b\2CSZ\0" \ 897 "b\1BNC\0" \ 898 "b\0AC64\0" \ 899 "\0" 900 901 int 902 xhci_init(struct xhci_softc *sc) 903 { 904 bus_size_t bsz; 905 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 906 uint32_t pagesize, config; 907 int i = 0; 908 uint16_t hciversion; 909 uint8_t caplength; 910 911 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 912 913 /* Set up the bus struct for the usb 3 and usb 2 buses */ 914 sc->sc_bus.ub_methods = &xhci_bus_methods; 915 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 916 sc->sc_bus.ub_revision = USBREV_3_0; 917 sc->sc_bus.ub_usedma = true; 918 sc->sc_bus.ub_hcpriv = sc; 919 920 sc->sc_bus2.ub_methods = &xhci_bus_methods; 921 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 922 sc->sc_bus2.ub_revision = USBREV_2_0; 923 sc->sc_bus2.ub_usedma = true; 924 sc->sc_bus2.ub_hcpriv = sc; 925 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 926 927 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 928 caplength = XHCI_CAP_CAPLENGTH(cap); 929 hciversion = XHCI_CAP_HCIVERSION(cap); 930 931 if (hciversion < XHCI_HCIVERSION_0_96 || 932 hciversion > XHCI_HCIVERSION_1_0) { 933 aprint_normal_dev(sc->sc_dev, 934 "xHCI version %x.%x not known to be supported\n", 935 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 936 } else { 937 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 938 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 939 } 940 941 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 942 &sc->sc_cbh) != 0) { 943 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 944 return ENOMEM; 945 } 946 947 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 948 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 949 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 950 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 951 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 952 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 953 aprint_debug_dev(sc->sc_dev, 954 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 955 956 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 957 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 958 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 959 960 char sbuf[128]; 961 if (hciversion < XHCI_HCIVERSION_1_0) 962 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 963 else 964 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 965 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 966 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 967 968 /* default all ports to bus 0, i.e. usb 3 */ 969 sc->sc_ctlrportbus = kmem_zalloc( 970 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 971 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 972 973 /* controller port to bus roothub port map */ 974 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 975 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 976 } 977 978 /* 979 * Process all Extended Capabilities 980 */ 981 xhci_ecp(sc, hcc); 982 983 bsz = XHCI_PORTSC(sc->sc_maxports); 984 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 985 &sc->sc_obh) != 0) { 986 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 987 return ENOMEM; 988 } 989 990 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 991 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 992 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 993 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 994 return ENOMEM; 995 } 996 997 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 998 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 999 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1000 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1001 return ENOMEM; 1002 } 1003 1004 int rv; 1005 rv = xhci_hc_reset(sc); 1006 if (rv != 0) { 1007 return rv; 1008 } 1009 1010 if (sc->sc_vendor_init) 1011 sc->sc_vendor_init(sc); 1012 1013 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1014 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1015 pagesize = ffs(pagesize); 1016 if (pagesize == 0) { 1017 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1018 return EIO; 1019 } 1020 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1021 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1022 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1023 (uint32_t)sc->sc_maxslots); 1024 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1025 1026 usbd_status err; 1027 1028 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1029 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1030 if (sc->sc_maxspbuf != 0) { 1031 err = usb_allocmem(&sc->sc_bus, 1032 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1033 &sc->sc_spbufarray_dma); 1034 if (err) { 1035 aprint_error_dev(sc->sc_dev, 1036 "spbufarray init fail, err %d\n", err); 1037 return ENOMEM; 1038 } 1039 1040 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1041 sc->sc_maxspbuf, KM_SLEEP); 1042 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1043 for (i = 0; i < sc->sc_maxspbuf; i++) { 1044 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1045 /* allocate contexts */ 1046 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1047 sc->sc_pgsz, dma); 1048 if (err) { 1049 aprint_error_dev(sc->sc_dev, 1050 "spbufarray_dma init fail, err %d\n", err); 1051 rv = ENOMEM; 1052 goto bad1; 1053 } 1054 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1055 usb_syncmem(dma, 0, sc->sc_pgsz, 1056 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1057 } 1058 1059 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1060 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1061 } 1062 1063 config = xhci_op_read_4(sc, XHCI_CONFIG); 1064 config &= ~0xFF; 1065 config |= sc->sc_maxslots & 0xFF; 1066 xhci_op_write_4(sc, XHCI_CONFIG, config); 1067 1068 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1069 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1070 if (err) { 1071 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1072 err); 1073 rv = ENOMEM; 1074 goto bad1; 1075 } 1076 1077 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1078 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1079 if (err) { 1080 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1081 err); 1082 rv = ENOMEM; 1083 goto bad2; 1084 } 1085 1086 usb_dma_t *dma; 1087 size_t size; 1088 size_t align; 1089 1090 dma = &sc->sc_eventst_dma; 1091 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1092 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1093 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1094 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1095 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1096 if (err) { 1097 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1098 err); 1099 rv = ENOMEM; 1100 goto bad3; 1101 } 1102 1103 memset(KERNADDR(dma, 0), 0, size); 1104 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1105 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1106 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1107 KERNADDR(&sc->sc_eventst_dma, 0), 1108 sc->sc_eventst_dma.udma_block->size); 1109 1110 dma = &sc->sc_dcbaa_dma; 1111 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1112 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1113 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1114 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1115 if (err) { 1116 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1117 rv = ENOMEM; 1118 goto bad4; 1119 } 1120 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1121 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1122 KERNADDR(&sc->sc_dcbaa_dma, 0), 1123 sc->sc_dcbaa_dma.udma_block->size); 1124 1125 memset(KERNADDR(dma, 0), 0, size); 1126 if (sc->sc_maxspbuf != 0) { 1127 /* 1128 * DCBA entry 0 hold the scratchbuf array pointer. 1129 */ 1130 *(uint64_t *)KERNADDR(dma, 0) = 1131 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1132 } 1133 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1134 1135 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1136 KM_SLEEP); 1137 if (sc->sc_slots == NULL) { 1138 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1139 rv = ENOMEM; 1140 goto bad; 1141 } 1142 1143 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1144 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1145 if (sc->sc_xferpool == NULL) { 1146 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1147 err); 1148 rv = ENOMEM; 1149 goto bad; 1150 } 1151 1152 cv_init(&sc->sc_command_cv, "xhcicmd"); 1153 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1154 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1155 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1156 1157 struct xhci_erste *erst; 1158 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1159 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1160 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1161 erst[0].erste_3 = htole32(0); 1162 usb_syncmem(&sc->sc_eventst_dma, 0, 1163 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1164 1165 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1166 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1167 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1168 XHCI_ERDP_LO_BUSY); 1169 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1170 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1171 sc->sc_cr.xr_cs); 1172 1173 #if 0 1174 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1175 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1176 #endif 1177 1178 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1179 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1180 /* Intel xhci needs interrupt rate moderated. */ 1181 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1182 else 1183 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1184 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1185 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1186 1187 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1188 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1189 xhci_op_read_4(sc, XHCI_USBCMD)); 1190 1191 return 0; 1192 1193 bad: 1194 if (sc->sc_xferpool) { 1195 pool_cache_destroy(sc->sc_xferpool); 1196 sc->sc_xferpool = NULL; 1197 } 1198 1199 if (sc->sc_slots) { 1200 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1201 sc->sc_maxslots); 1202 sc->sc_slots = NULL; 1203 } 1204 1205 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1206 bad4: 1207 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1208 bad3: 1209 xhci_ring_free(sc, &sc->sc_er); 1210 bad2: 1211 xhci_ring_free(sc, &sc->sc_cr); 1212 i = sc->sc_maxspbuf; 1213 bad1: 1214 for (int j = 0; j < i; j++) 1215 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1216 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1217 1218 return rv; 1219 } 1220 1221 int 1222 xhci_intr(void *v) 1223 { 1224 struct xhci_softc * const sc = v; 1225 int ret = 0; 1226 1227 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1228 1229 if (sc == NULL) 1230 return 0; 1231 1232 mutex_spin_enter(&sc->sc_intr_lock); 1233 1234 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1235 goto done; 1236 1237 /* If we get an interrupt while polling, then just ignore it. */ 1238 if (sc->sc_bus.ub_usepolling) { 1239 #ifdef DIAGNOSTIC 1240 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1241 #endif 1242 goto done; 1243 } 1244 1245 ret = xhci_intr1(sc); 1246 done: 1247 mutex_spin_exit(&sc->sc_intr_lock); 1248 return ret; 1249 } 1250 1251 int 1252 xhci_intr1(struct xhci_softc * const sc) 1253 { 1254 uint32_t usbsts; 1255 uint32_t iman; 1256 1257 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1258 1259 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1260 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1261 #if 0 1262 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1263 return 0; 1264 } 1265 #endif 1266 xhci_op_write_4(sc, XHCI_USBSTS, 1267 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1268 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1269 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1270 1271 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1272 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1273 iman |= XHCI_IMAN_INTR_PEND; 1274 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1275 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1276 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1277 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1278 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1279 1280 usb_schedsoftintr(&sc->sc_bus); 1281 1282 return 1; 1283 } 1284 1285 /* 1286 * 3 port speed types used in USB stack 1287 * 1288 * usbdi speed 1289 * definition: USB_SPEED_* in usb.h 1290 * They are used in struct usbd_device in USB stack. 1291 * ioctl interface uses these values too. 1292 * port_status speed 1293 * definition: UPS_*_SPEED in usb.h 1294 * They are used in usb_port_status_t and valid only for USB 2.0. 1295 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1296 * of usb_port_status_ext_t indicates port speed. 1297 * Note that some 3.0 values overlap with 2.0 values. 1298 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1299 * means UPS_LOW_SPEED in HS.) 1300 * port status returned from hub also uses these values. 1301 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1302 * or more. 1303 * xspeed: 1304 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1305 * They are used in only slot context and PORTSC reg of xhci. 1306 * The difference between usbdi speed and xspeed is 1307 * that FS and LS values are swapped. 1308 */ 1309 1310 /* convert usbdi speed to xspeed */ 1311 static int 1312 xhci_speed2xspeed(int speed) 1313 { 1314 switch (speed) { 1315 case USB_SPEED_LOW: return 2; 1316 case USB_SPEED_FULL: return 1; 1317 default: return speed; 1318 } 1319 } 1320 1321 #if 0 1322 /* convert xspeed to usbdi speed */ 1323 static int 1324 xhci_xspeed2speed(int xspeed) 1325 { 1326 switch (xspeed) { 1327 case 1: return USB_SPEED_FULL; 1328 case 2: return USB_SPEED_LOW; 1329 default: return xspeed; 1330 } 1331 } 1332 #endif 1333 1334 /* convert xspeed to port status speed */ 1335 static int 1336 xhci_xspeed2psspeed(int xspeed) 1337 { 1338 switch (xspeed) { 1339 case 0: return 0; 1340 case 1: return UPS_FULL_SPEED; 1341 case 2: return UPS_LOW_SPEED; 1342 case 3: return UPS_HIGH_SPEED; 1343 default: return UPS_OTHER_SPEED; 1344 } 1345 } 1346 1347 /* 1348 * Construct input contexts and issue TRB to open pipe. 1349 */ 1350 static usbd_status 1351 xhci_configure_endpoint(struct usbd_pipe *pipe) 1352 { 1353 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1354 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1355 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1356 struct xhci_trb trb; 1357 usbd_status err; 1358 1359 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1360 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1361 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1362 pipe->up_endpoint->ue_edesc->bmAttributes); 1363 1364 /* XXX ensure input context is available? */ 1365 1366 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1367 1368 /* set up context */ 1369 xhci_setup_ctx(pipe); 1370 1371 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1372 sc->sc_ctxsz * 1); 1373 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1374 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1375 1376 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1377 trb.trb_2 = 0; 1378 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1379 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1380 1381 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1382 1383 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1384 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1385 sc->sc_ctxsz * 1); 1386 1387 return err; 1388 } 1389 1390 #if 0 1391 static usbd_status 1392 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1393 { 1394 #ifdef USB_DEBUG 1395 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1396 #endif 1397 1398 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1399 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1400 1401 return USBD_NORMAL_COMPLETION; 1402 } 1403 #endif 1404 1405 /* 4.6.8, 6.4.3.7 */ 1406 static usbd_status 1407 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1408 { 1409 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1410 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1411 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1412 struct xhci_trb trb; 1413 usbd_status err; 1414 1415 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1416 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1417 1418 KASSERT(mutex_owned(&sc->sc_lock)); 1419 1420 trb.trb_0 = 0; 1421 trb.trb_2 = 0; 1422 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1423 XHCI_TRB_3_EP_SET(dci) | 1424 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1425 1426 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1427 1428 return err; 1429 } 1430 1431 static usbd_status 1432 xhci_reset_endpoint(struct usbd_pipe *pipe) 1433 { 1434 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1435 1436 mutex_enter(&sc->sc_lock); 1437 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1438 mutex_exit(&sc->sc_lock); 1439 1440 return ret; 1441 } 1442 1443 /* 1444 * 4.6.9, 6.4.3.8 1445 * Stop execution of TDs on xfer ring. 1446 * Should be called with sc_lock held. 1447 */ 1448 static usbd_status 1449 xhci_stop_endpoint(struct usbd_pipe *pipe) 1450 { 1451 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1452 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1453 struct xhci_trb trb; 1454 usbd_status err; 1455 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1456 1457 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1458 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1459 1460 KASSERT(mutex_owned(&sc->sc_lock)); 1461 1462 trb.trb_0 = 0; 1463 trb.trb_2 = 0; 1464 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1465 XHCI_TRB_3_EP_SET(dci) | 1466 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1467 1468 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1469 1470 return err; 1471 } 1472 1473 /* 1474 * Set TR Dequeue Pointer. 1475 * xHCI 1.1 4.6.10 6.4.3.9 1476 * Purge all of the TRBs on ring and reinitialize ring. 1477 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1478 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1479 * error will be generated. 1480 */ 1481 static usbd_status 1482 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1483 { 1484 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1485 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1486 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1487 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1488 struct xhci_trb trb; 1489 usbd_status err; 1490 1491 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1492 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1493 1494 KASSERT(mutex_owned(&sc->sc_lock)); 1495 1496 xhci_host_dequeue(xr); 1497 1498 /* set DCS */ 1499 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1500 trb.trb_2 = 0; 1501 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1502 XHCI_TRB_3_EP_SET(dci) | 1503 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1504 1505 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1506 1507 return err; 1508 } 1509 1510 static usbd_status 1511 xhci_set_dequeue(struct usbd_pipe *pipe) 1512 { 1513 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1514 1515 mutex_enter(&sc->sc_lock); 1516 usbd_status ret = xhci_set_dequeue_locked(pipe); 1517 mutex_exit(&sc->sc_lock); 1518 1519 return ret; 1520 } 1521 1522 /* 1523 * Open new pipe: called from usbd_setup_pipe_flags. 1524 * Fills methods of pipe. 1525 * If pipe is not for ep0, calls configure_endpoint. 1526 */ 1527 static usbd_status 1528 xhci_open(struct usbd_pipe *pipe) 1529 { 1530 struct usbd_device * const dev = pipe->up_dev; 1531 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1532 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1533 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1534 1535 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1536 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1537 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1538 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1539 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1540 ed->bmAttributes); 1541 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1542 0, 0); 1543 1544 if (sc->sc_dying) 1545 return USBD_IOERROR; 1546 1547 /* Root Hub */ 1548 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1549 switch (ed->bEndpointAddress) { 1550 case USB_CONTROL_ENDPOINT: 1551 pipe->up_methods = &roothub_ctrl_methods; 1552 break; 1553 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1554 pipe->up_methods = &xhci_root_intr_methods; 1555 break; 1556 default: 1557 pipe->up_methods = NULL; 1558 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1559 ed->bEndpointAddress, 0, 0, 0); 1560 return USBD_INVAL; 1561 } 1562 return USBD_NORMAL_COMPLETION; 1563 } 1564 1565 switch (xfertype) { 1566 case UE_CONTROL: 1567 pipe->up_methods = &xhci_device_ctrl_methods; 1568 break; 1569 case UE_ISOCHRONOUS: 1570 pipe->up_methods = &xhci_device_isoc_methods; 1571 return USBD_INVAL; 1572 break; 1573 case UE_BULK: 1574 pipe->up_methods = &xhci_device_bulk_methods; 1575 break; 1576 case UE_INTERRUPT: 1577 pipe->up_methods = &xhci_device_intr_methods; 1578 break; 1579 default: 1580 return USBD_IOERROR; 1581 break; 1582 } 1583 1584 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1585 return xhci_configure_endpoint(pipe); 1586 1587 return USBD_NORMAL_COMPLETION; 1588 } 1589 1590 /* 1591 * Closes pipe, called from usbd_kill_pipe via close methods. 1592 * If the endpoint to be closed is ep0, disable_slot. 1593 * Should be called with sc_lock held. 1594 */ 1595 static void 1596 xhci_close_pipe(struct usbd_pipe *pipe) 1597 { 1598 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1599 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1600 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1601 const u_int dci = xhci_ep_get_dci(ed); 1602 struct xhci_trb trb; 1603 uint32_t *cp; 1604 1605 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1606 1607 if (sc->sc_dying) 1608 return; 1609 1610 /* xs is uninitialized before xhci_init_slot */ 1611 if (xs == NULL || xs->xs_idx == 0) 1612 return; 1613 1614 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1615 1616 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1617 KASSERT(mutex_owned(&sc->sc_lock)); 1618 1619 if (pipe->up_dev->ud_depth == 0) 1620 return; 1621 1622 if (dci == XHCI_DCI_EP_CONTROL) { 1623 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1624 xhci_disable_slot(sc, xs->xs_idx); 1625 return; 1626 } 1627 1628 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1629 (void)xhci_stop_endpoint(pipe); 1630 1631 /* 1632 * set appropriate bit to be dropped. 1633 * don't set DC bit to 1, otherwise all endpoints 1634 * would be deconfigured. 1635 */ 1636 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1637 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1638 cp[1] = htole32(0); 1639 1640 /* XXX should be most significant one, not dci? */ 1641 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1642 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1643 1644 /* configure ep context performs an implicit dequeue */ 1645 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1646 1647 /* sync input contexts before they are read from memory */ 1648 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1649 1650 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1651 trb.trb_2 = 0; 1652 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1653 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1654 1655 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1656 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1657 } 1658 1659 /* 1660 * Abort transfer. 1661 * Should be called with sc_lock held. 1662 */ 1663 static void 1664 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1665 { 1666 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1667 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1668 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1669 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1670 1671 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 1672 "invalid status for abort: %d", (int)status); 1673 1674 DPRINTFN(4, "xfer %p pipe %p status %d", 1675 xfer, xfer->ux_pipe, status, 0); 1676 1677 KASSERT(mutex_owned(&sc->sc_lock)); 1678 ASSERT_SLEEPABLE(); 1679 1680 if (status == USBD_CANCELLED) { 1681 /* 1682 * We are synchronously aborting. Try to stop the 1683 * callout and task, but if we can't, wait for them to 1684 * complete. 1685 */ 1686 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1687 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 1688 USB_TASKQ_HC, &sc->sc_lock); 1689 } else { 1690 /* Otherwise, we are timing out. */ 1691 KASSERT(status == USBD_TIMEOUT); 1692 } 1693 1694 /* 1695 * The xfer cannot have been cancelled already. It is the 1696 * responsibility of the caller of usbd_abort_pipe not to try 1697 * to abort a pipe multiple times, whether concurrently or 1698 * sequentially. 1699 */ 1700 KASSERT(xfer->ux_status != USBD_CANCELLED); 1701 1702 /* Only the timeout, which runs only once, can time it out. */ 1703 KASSERT(xfer->ux_status != USBD_TIMEOUT); 1704 1705 /* If anyone else beat us, we're done. */ 1706 if (xfer->ux_status != USBD_IN_PROGRESS) 1707 return; 1708 1709 /* We beat everyone else. Claim the status. */ 1710 xfer->ux_status = status; 1711 1712 /* 1713 * If we're dying, skip the hardware action and just notify the 1714 * software that we're done. 1715 */ 1716 if (sc->sc_dying) { 1717 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1718 xfer->ux_status, 0, 0); 1719 goto dying; 1720 } 1721 1722 /* 1723 * HC Step 1: Stop execution of TD on the ring. 1724 */ 1725 switch (xhci_get_epstate(sc, xs, dci)) { 1726 case XHCI_EPSTATE_HALTED: 1727 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1728 break; 1729 case XHCI_EPSTATE_STOPPED: 1730 break; 1731 default: 1732 (void)xhci_stop_endpoint(xfer->ux_pipe); 1733 break; 1734 } 1735 #ifdef DIAGNOSTIC 1736 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1737 if (epst != XHCI_EPSTATE_STOPPED) 1738 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1739 #endif 1740 1741 /* 1742 * HC Step 2: Remove any vestiges of the xfer from the ring. 1743 */ 1744 xhci_set_dequeue_locked(xfer->ux_pipe); 1745 1746 /* 1747 * Final Step: Notify completion to waiting xfers. 1748 */ 1749 dying: 1750 usb_transfer_complete(xfer); 1751 DPRINTFN(14, "end", 0, 0, 0, 0); 1752 1753 KASSERT(mutex_owned(&sc->sc_lock)); 1754 } 1755 1756 static void 1757 xhci_host_dequeue(struct xhci_ring * const xr) 1758 { 1759 /* When dequeueing the controller, update our struct copy too */ 1760 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1761 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1762 BUS_DMASYNC_PREWRITE); 1763 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1764 1765 xr->xr_ep = 0; 1766 xr->xr_cs = 1; 1767 } 1768 1769 /* 1770 * Recover STALLed endpoint. 1771 * xHCI 1.1 sect 4.10.2.1 1772 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1773 * all transfers on transfer ring. 1774 * These are done in thread context asynchronously. 1775 */ 1776 static void 1777 xhci_clear_endpoint_stall_async_task(void *cookie) 1778 { 1779 struct usbd_xfer * const xfer = cookie; 1780 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1781 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1782 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1783 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1784 1785 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1786 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1787 1788 xhci_reset_endpoint(xfer->ux_pipe); 1789 xhci_set_dequeue(xfer->ux_pipe); 1790 1791 mutex_enter(&sc->sc_lock); 1792 tr->is_halted = false; 1793 usb_transfer_complete(xfer); 1794 mutex_exit(&sc->sc_lock); 1795 DPRINTFN(4, "ends", 0, 0, 0, 0); 1796 } 1797 1798 static usbd_status 1799 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1800 { 1801 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1802 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1803 1804 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1805 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1806 1807 if (sc->sc_dying) { 1808 return USBD_IOERROR; 1809 } 1810 1811 usb_init_task(&xp->xp_async_task, 1812 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1813 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1814 DPRINTFN(4, "ends", 0, 0, 0, 0); 1815 1816 return USBD_NORMAL_COMPLETION; 1817 } 1818 1819 /* Process roothub port status/change events and notify to uhub_intr. */ 1820 static void 1821 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1822 { 1823 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1824 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1825 ctlrport, 0, 0); 1826 1827 if (ctlrport > sc->sc_maxports) 1828 return; 1829 1830 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1831 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1832 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1833 1834 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1835 device_unit(sc->sc_dev), bn, rhp, xfer); 1836 1837 if (xfer == NULL) 1838 return; 1839 1840 uint8_t *p = xfer->ux_buf; 1841 memset(p, 0, xfer->ux_length); 1842 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1843 xfer->ux_actlen = xfer->ux_length; 1844 xfer->ux_status = USBD_NORMAL_COMPLETION; 1845 usb_transfer_complete(xfer); 1846 } 1847 1848 /* Process Transfer Events */ 1849 static void 1850 xhci_event_transfer(struct xhci_softc * const sc, 1851 const struct xhci_trb * const trb) 1852 { 1853 uint64_t trb_0; 1854 uint32_t trb_2, trb_3; 1855 uint8_t trbcode; 1856 u_int slot, dci; 1857 struct xhci_slot *xs; 1858 struct xhci_ring *xr; 1859 struct xhci_xfer *xx; 1860 struct usbd_xfer *xfer; 1861 usbd_status err; 1862 1863 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1864 1865 trb_0 = le64toh(trb->trb_0); 1866 trb_2 = le32toh(trb->trb_2); 1867 trb_3 = le32toh(trb->trb_3); 1868 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1869 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1870 dci = XHCI_TRB_3_EP_GET(trb_3); 1871 xs = &sc->sc_slots[slot]; 1872 xr = &xs->xs_ep[dci].xe_tr; 1873 1874 /* sanity check */ 1875 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1876 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1877 1878 int idx = 0; 1879 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1880 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1881 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1882 return; 1883 } 1884 xx = xr->xr_cookies[idx]; 1885 1886 /* clear cookie of consumed TRB */ 1887 xr->xr_cookies[idx] = NULL; 1888 1889 /* 1890 * xx is NULL if pipe is opened but xfer is not started. 1891 * It happens when stopping idle pipe. 1892 */ 1893 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1894 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1895 idx, xx, trbcode, dci); 1896 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1897 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1898 0, 0); 1899 return; 1900 } 1901 } else { 1902 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1903 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1904 } 1905 /* XXX this may not happen */ 1906 if (xx == NULL) { 1907 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1908 return; 1909 } 1910 xfer = &xx->xx_xfer; 1911 /* XXX this may happen when detaching */ 1912 if (xfer == NULL) { 1913 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1914 xx, trb_0, 0, 0); 1915 return; 1916 } 1917 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1918 /* XXX I dunno why this happens */ 1919 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1920 1921 if (!xfer->ux_pipe->up_repeat && 1922 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1923 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1924 return; 1925 } 1926 1927 /* 4.11.5.2 Event Data TRB */ 1928 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1929 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1930 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1931 if ((trb_0 & 0x3) == 0x3) { 1932 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1933 } 1934 } 1935 1936 switch (trbcode) { 1937 case XHCI_TRB_ERROR_SHORT_PKT: 1938 case XHCI_TRB_ERROR_SUCCESS: 1939 /* 1940 * A ctrl transfer can generate two events if it has a Data 1941 * stage. A short data stage can be OK and should not 1942 * complete the transfer as the status stage needs to be 1943 * performed. 1944 * 1945 * Note: Data and Status stage events point at same xfer. 1946 * ux_actlen and ux_dmabuf will be passed to 1947 * usb_transfer_complete after the Status stage event. 1948 * 1949 * It can be distingished which stage generates the event: 1950 * + by checking least 3 bits of trb_0 if ED==1. 1951 * (see xhci_device_ctrl_start). 1952 * + by checking the type of original TRB if ED==0. 1953 * 1954 * In addition, intr, bulk, and isoc transfer currently 1955 * consists of single TD, so the "skip" is not needed. 1956 * ctrl xfer uses EVENT_DATA, and others do not. 1957 * Thus driver can switch the flow by checking ED bit. 1958 */ 1959 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1960 if (xfer->ux_actlen == 0) 1961 xfer->ux_actlen = xfer->ux_length - 1962 XHCI_TRB_2_REM_GET(trb_2); 1963 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1964 == XHCI_TRB_TYPE_DATA_STAGE) { 1965 return; 1966 } 1967 } else if ((trb_0 & 0x3) == 0x3) { 1968 return; 1969 } 1970 err = USBD_NORMAL_COMPLETION; 1971 break; 1972 case XHCI_TRB_ERROR_STOPPED: 1973 case XHCI_TRB_ERROR_LENGTH: 1974 case XHCI_TRB_ERROR_STOPPED_SHORT: 1975 /* 1976 * don't complete the transfer being aborted 1977 * as abort_xfer does instead. 1978 */ 1979 if (xfer->ux_status == USBD_CANCELLED || 1980 xfer->ux_status == USBD_TIMEOUT) { 1981 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1982 return; 1983 } 1984 err = USBD_CANCELLED; 1985 break; 1986 case XHCI_TRB_ERROR_STALL: 1987 case XHCI_TRB_ERROR_BABBLE: 1988 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1989 xr->is_halted = true; 1990 /* 1991 * Stalled endpoints can be recoverd by issuing 1992 * command TRB TYPE_RESET_EP on xHCI instead of 1993 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1994 * on the endpoint. However, this function may be 1995 * called from softint context (e.g. from umass), 1996 * in that case driver gets KASSERT in cv_timedwait 1997 * in xhci_do_command. 1998 * To avoid this, this runs reset_endpoint and 1999 * usb_transfer_complete in usb task thread 2000 * asynchronously (and then umass issues clear 2001 * UF_ENDPOINT_HALT). 2002 */ 2003 2004 /* Override the status. */ 2005 xfer->ux_status = USBD_STALLED; 2006 2007 /* 2008 * Cancel the timeout and the task, which have not yet 2009 * run. If they have already fired, at worst they are 2010 * waiting for the lock. They will see that the xfer 2011 * is no longer in progress and give up. 2012 */ 2013 callout_stop(&xfer->ux_callout); 2014 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 2015 2016 xhci_clear_endpoint_stall_async(xfer); 2017 return; 2018 default: 2019 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 2020 err = USBD_IOERROR; 2021 break; 2022 } 2023 2024 /* 2025 * If software has completed it, either by cancellation 2026 * or timeout, drop it on the floor. 2027 */ 2028 if (xfer->ux_status != USBD_IN_PROGRESS) { 2029 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2030 xfer->ux_status == USBD_TIMEOUT), 2031 "xfer %p status %x", xfer, xfer->ux_status); 2032 return;; 2033 } 2034 2035 /* Otherwise, set the status. */ 2036 xfer->ux_status = err; 2037 2038 /* 2039 * Cancel the timeout and the task, which have not yet 2040 * run. If they have already fired, at worst they are 2041 * waiting for the lock. They will see that the xfer 2042 * is no longer in progress and give up. 2043 */ 2044 callout_stop(&xfer->ux_callout); 2045 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 2046 2047 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2048 (trb_0 & 0x3) == 0x0) { 2049 usb_transfer_complete(xfer); 2050 } 2051 } 2052 2053 /* Process Command complete events */ 2054 static void 2055 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2056 { 2057 uint64_t trb_0; 2058 uint32_t trb_2, trb_3; 2059 2060 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2061 2062 KASSERT(mutex_owned(&sc->sc_lock)); 2063 2064 trb_0 = le64toh(trb->trb_0); 2065 trb_2 = le32toh(trb->trb_2); 2066 trb_3 = le32toh(trb->trb_3); 2067 2068 if (trb_0 == sc->sc_command_addr) { 2069 sc->sc_resultpending = false; 2070 2071 sc->sc_result_trb.trb_0 = trb_0; 2072 sc->sc_result_trb.trb_2 = trb_2; 2073 sc->sc_result_trb.trb_3 = trb_3; 2074 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2075 XHCI_TRB_ERROR_SUCCESS) { 2076 DPRINTFN(1, "command completion " 2077 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2078 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2079 } 2080 cv_signal(&sc->sc_command_cv); 2081 } else { 2082 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2083 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2084 trb_2, trb_3); 2085 } 2086 } 2087 2088 /* 2089 * Process events. 2090 * called from xhci_softintr 2091 */ 2092 static void 2093 xhci_handle_event(struct xhci_softc * const sc, 2094 const struct xhci_trb * const trb) 2095 { 2096 uint64_t trb_0; 2097 uint32_t trb_2, trb_3; 2098 2099 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2100 2101 trb_0 = le64toh(trb->trb_0); 2102 trb_2 = le32toh(trb->trb_2); 2103 trb_3 = le32toh(trb->trb_3); 2104 2105 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2106 trb, trb_0, trb_2, trb_3); 2107 2108 /* 2109 * 4.11.3.1, 6.4.2.1 2110 * TRB Pointer is invalid for these completion codes. 2111 */ 2112 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2113 case XHCI_TRB_ERROR_RING_UNDERRUN: 2114 case XHCI_TRB_ERROR_RING_OVERRUN: 2115 case XHCI_TRB_ERROR_VF_RING_FULL: 2116 return; 2117 default: 2118 if (trb_0 == 0) { 2119 return; 2120 } 2121 break; 2122 } 2123 2124 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2125 case XHCI_TRB_EVENT_TRANSFER: 2126 xhci_event_transfer(sc, trb); 2127 break; 2128 case XHCI_TRB_EVENT_CMD_COMPLETE: 2129 xhci_event_cmd(sc, trb); 2130 break; 2131 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2132 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2133 break; 2134 default: 2135 break; 2136 } 2137 } 2138 2139 static void 2140 xhci_softintr(void *v) 2141 { 2142 struct usbd_bus * const bus = v; 2143 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2144 struct xhci_ring * const er = &sc->sc_er; 2145 struct xhci_trb *trb; 2146 int i, j, k; 2147 2148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2149 2150 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2151 2152 i = er->xr_ep; 2153 j = er->xr_cs; 2154 2155 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2156 2157 while (1) { 2158 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2159 BUS_DMASYNC_POSTREAD); 2160 trb = &er->xr_trb[i]; 2161 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2162 2163 if (j != k) 2164 break; 2165 2166 xhci_handle_event(sc, trb); 2167 2168 i++; 2169 if (i == er->xr_ntrb) { 2170 i = 0; 2171 j ^= 1; 2172 } 2173 } 2174 2175 er->xr_ep = i; 2176 er->xr_cs = j; 2177 2178 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2179 XHCI_ERDP_LO_BUSY); 2180 2181 DPRINTFN(16, "ends", 0, 0, 0, 0); 2182 2183 return; 2184 } 2185 2186 static void 2187 xhci_poll(struct usbd_bus *bus) 2188 { 2189 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2190 2191 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2192 2193 mutex_spin_enter(&sc->sc_intr_lock); 2194 xhci_intr1(sc); 2195 mutex_spin_exit(&sc->sc_intr_lock); 2196 2197 return; 2198 } 2199 2200 static struct usbd_xfer * 2201 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2202 { 2203 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2204 struct usbd_xfer *xfer; 2205 2206 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2207 2208 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2209 if (xfer != NULL) { 2210 memset(xfer, 0, sizeof(struct xhci_xfer)); 2211 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, xfer, 2212 USB_TASKQ_MPSAFE); 2213 #ifdef DIAGNOSTIC 2214 xfer->ux_state = XFER_BUSY; 2215 #endif 2216 } 2217 2218 return xfer; 2219 } 2220 2221 static void 2222 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2223 { 2224 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2225 2226 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2227 2228 #ifdef DIAGNOSTIC 2229 if (xfer->ux_state != XFER_BUSY) { 2230 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2231 xfer, xfer->ux_state, 0, 0); 2232 } 2233 xfer->ux_state = XFER_FREE; 2234 #endif 2235 pool_cache_put(sc->sc_xferpool, xfer); 2236 } 2237 2238 static void 2239 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2240 { 2241 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2242 2243 *lock = &sc->sc_lock; 2244 } 2245 2246 extern uint32_t usb_cookie_no; 2247 2248 /* 2249 * xHCI 4.3 2250 * Called when uhub_explore finds a new device (via usbd_new_device). 2251 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2252 * This function does: 2253 * Allocate and construct dev structure of default endpoint (ep0). 2254 * Allocate and open pipe of ep0. 2255 * Enable slot and initialize slot context. 2256 * Set Address. 2257 * Read initial device descriptor. 2258 * Determine initial MaxPacketSize (mps) by speed. 2259 * Read full device descriptor. 2260 * Register this device. 2261 * Finally state of device transitions ADDRESSED. 2262 */ 2263 static usbd_status 2264 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2265 int speed, int port, struct usbd_port *up) 2266 { 2267 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2268 struct usbd_device *dev; 2269 usbd_status err; 2270 usb_device_descriptor_t *dd; 2271 struct xhci_slot *xs; 2272 uint32_t *cp; 2273 2274 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2275 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2276 2277 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2278 if (dev == NULL) 2279 return USBD_NOMEM; 2280 2281 dev->ud_bus = bus; 2282 dev->ud_quirks = &usbd_no_quirk; 2283 dev->ud_addr = 0; 2284 dev->ud_ddesc.bMaxPacketSize = 0; 2285 dev->ud_depth = depth; 2286 dev->ud_powersrc = up; 2287 dev->ud_myhub = up->up_parent; 2288 dev->ud_speed = speed; 2289 dev->ud_langid = USBD_NOLANG; 2290 dev->ud_cookie.cookie = ++usb_cookie_no; 2291 2292 /* Set up default endpoint handle. */ 2293 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2294 /* doesn't matter, just don't let it uninitialized */ 2295 dev->ud_ep0.ue_toggle = 0; 2296 2297 /* Set up default endpoint descriptor. */ 2298 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2299 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2300 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2301 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2302 dev->ud_ep0desc.bInterval = 0; 2303 2304 /* 4.3, 4.8.2.1 */ 2305 switch (speed) { 2306 case USB_SPEED_SUPER: 2307 case USB_SPEED_SUPER_PLUS: 2308 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2309 break; 2310 case USB_SPEED_FULL: 2311 /* XXX using 64 as initial mps of ep0 in FS */ 2312 case USB_SPEED_HIGH: 2313 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2314 break; 2315 case USB_SPEED_LOW: 2316 default: 2317 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2318 break; 2319 } 2320 2321 up->up_dev = dev; 2322 2323 /* Establish the default pipe. */ 2324 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2325 &dev->ud_pipe0); 2326 if (err) { 2327 goto bad; 2328 } 2329 2330 dd = &dev->ud_ddesc; 2331 2332 if (depth == 0 && port == 0) { 2333 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2334 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2335 err = usbd_get_initial_ddesc(dev, dd); 2336 if (err) { 2337 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2338 goto bad; 2339 } 2340 2341 err = usbd_reload_device_desc(dev); 2342 if (err) { 2343 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2344 goto bad; 2345 } 2346 } else { 2347 uint8_t slot = 0; 2348 2349 /* 4.3.2 */ 2350 err = xhci_enable_slot(sc, &slot); 2351 if (err) { 2352 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2353 goto bad; 2354 } 2355 2356 xs = &sc->sc_slots[slot]; 2357 dev->ud_hcpriv = xs; 2358 2359 /* 4.3.3 initialize slot structure */ 2360 err = xhci_init_slot(dev, slot); 2361 if (err) { 2362 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2363 dev->ud_hcpriv = NULL; 2364 /* 2365 * We have to disable_slot here because 2366 * xs->xs_idx == 0 when xhci_init_slot fails, 2367 * in that case usbd_remove_dev won't work. 2368 */ 2369 mutex_enter(&sc->sc_lock); 2370 xhci_disable_slot(sc, slot); 2371 mutex_exit(&sc->sc_lock); 2372 goto bad; 2373 } 2374 2375 /* 4.3.4 Address Assignment */ 2376 err = xhci_set_address(dev, slot, false); 2377 if (err) { 2378 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2379 goto bad; 2380 } 2381 2382 /* Allow device time to set new address */ 2383 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2384 2385 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2386 //hexdump("slot context", cp, sc->sc_ctxsz); 2387 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2388 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2389 /* 2390 * XXX ensure we know when the hardware does something 2391 * we can't yet cope with 2392 */ 2393 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2394 dev->ud_addr = addr; 2395 2396 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2397 "addr %d already allocated", dev->ud_addr); 2398 /* 2399 * The root hub is given its own slot 2400 */ 2401 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2402 2403 err = usbd_get_initial_ddesc(dev, dd); 2404 if (err) { 2405 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2406 goto bad; 2407 } 2408 2409 /* 4.8.2.1 */ 2410 if (USB_IS_SS(speed)) { 2411 if (dd->bMaxPacketSize != 9) { 2412 printf("%s: invalid mps 2^%u for SS ep0," 2413 " using 512\n", 2414 device_xname(sc->sc_dev), 2415 dd->bMaxPacketSize); 2416 dd->bMaxPacketSize = 9; 2417 } 2418 USETW(dev->ud_ep0desc.wMaxPacketSize, 2419 (1 << dd->bMaxPacketSize)); 2420 } else 2421 USETW(dev->ud_ep0desc.wMaxPacketSize, 2422 dd->bMaxPacketSize); 2423 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2424 err = xhci_update_ep0_mps(sc, xs, 2425 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2426 if (err) { 2427 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2428 goto bad; 2429 } 2430 2431 err = usbd_reload_device_desc(dev); 2432 if (err) { 2433 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2434 goto bad; 2435 } 2436 } 2437 2438 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2439 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2440 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2441 dd->bDeviceClass, dd->bDeviceSubClass, 2442 dd->bDeviceProtocol, 0); 2443 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2444 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2445 dev->ud_speed); 2446 2447 usbd_get_device_strings(dev); 2448 2449 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2450 2451 if (depth == 0 && port == 0) { 2452 usbd_attach_roothub(parent, dev); 2453 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2454 return USBD_NORMAL_COMPLETION; 2455 } 2456 2457 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2458 bad: 2459 if (err != USBD_NORMAL_COMPLETION) { 2460 usbd_remove_device(dev, up); 2461 } 2462 2463 return err; 2464 } 2465 2466 static usbd_status 2467 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2468 size_t ntrb, size_t align) 2469 { 2470 usbd_status err; 2471 size_t size = ntrb * XHCI_TRB_SIZE; 2472 2473 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2474 2475 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2476 if (err) 2477 return err; 2478 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2479 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2480 xr->xr_trb = xhci_ring_trbv(xr, 0); 2481 xr->xr_ntrb = ntrb; 2482 xr->is_halted = false; 2483 xhci_host_dequeue(xr); 2484 2485 return USBD_NORMAL_COMPLETION; 2486 } 2487 2488 static void 2489 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2490 { 2491 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2492 mutex_destroy(&xr->xr_lock); 2493 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2494 } 2495 2496 static void 2497 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2498 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2499 { 2500 size_t i; 2501 u_int ri; 2502 u_int cs; 2503 uint64_t parameter; 2504 uint32_t status; 2505 uint32_t control; 2506 2507 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2508 2509 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2510 for (i = 0; i < ntrbs; i++) { 2511 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2512 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2513 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2514 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2515 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2516 } 2517 2518 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2519 2520 ri = xr->xr_ep; 2521 cs = xr->xr_cs; 2522 2523 /* 2524 * Although the xhci hardware can do scatter/gather dma from 2525 * arbitrary sized buffers, there is a non-obvious restriction 2526 * that a LINK trb is only allowed at the end of a burst of 2527 * transfers - which might be 16kB. 2528 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2529 * The simple solution is not to allow a LINK trb in the middle 2530 * of anything - as here. 2531 * XXX: (dsl) There are xhci controllers out there (eg some made by 2532 * ASMedia) that seem to lock up if they process a LINK trb but 2533 * cannot process the linked-to trb yet. 2534 * The code should write the 'cycle' bit on the link trb AFTER 2535 * adding the other trb. 2536 */ 2537 u_int firstep = xr->xr_ep; 2538 u_int firstcs = xr->xr_cs; 2539 2540 for (i = 0; i < ntrbs; ) { 2541 u_int oldri = ri; 2542 u_int oldcs = cs; 2543 2544 if (ri >= (xr->xr_ntrb - 1)) { 2545 /* Put Link TD at the end of ring */ 2546 parameter = xhci_ring_trbp(xr, 0); 2547 status = 0; 2548 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2549 XHCI_TRB_3_TC_BIT; 2550 xr->xr_cookies[ri] = NULL; 2551 xr->xr_ep = 0; 2552 xr->xr_cs ^= 1; 2553 ri = xr->xr_ep; 2554 cs = xr->xr_cs; 2555 } else { 2556 parameter = trbs[i].trb_0; 2557 status = trbs[i].trb_2; 2558 control = trbs[i].trb_3; 2559 2560 xr->xr_cookies[ri] = cookie; 2561 ri++; 2562 i++; 2563 } 2564 /* 2565 * If this is a first TRB, mark it invalid to prevent 2566 * xHC from running it immediately. 2567 */ 2568 if (oldri == firstep) { 2569 if (oldcs) { 2570 control &= ~XHCI_TRB_3_CYCLE_BIT; 2571 } else { 2572 control |= XHCI_TRB_3_CYCLE_BIT; 2573 } 2574 } else { 2575 if (oldcs) { 2576 control |= XHCI_TRB_3_CYCLE_BIT; 2577 } else { 2578 control &= ~XHCI_TRB_3_CYCLE_BIT; 2579 } 2580 } 2581 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2582 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2583 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2584 } 2585 2586 /* Now invert cycle bit of first TRB */ 2587 if (firstcs) { 2588 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2589 } else { 2590 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2591 } 2592 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2593 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2594 2595 xr->xr_ep = ri; 2596 xr->xr_cs = cs; 2597 2598 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2599 } 2600 2601 /* 2602 * Stop execution commands, purge all commands on command ring, and 2603 * rewind dequeue pointer. 2604 */ 2605 static void 2606 xhci_abort_command(struct xhci_softc *sc) 2607 { 2608 struct xhci_ring * const cr = &sc->sc_cr; 2609 uint64_t crcr; 2610 int i; 2611 2612 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2613 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2614 sc->sc_command_addr, 0, 0, 0); 2615 2616 mutex_enter(&cr->xr_lock); 2617 2618 /* 4.6.1.2 Aborting a Command */ 2619 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2620 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2621 2622 for (i = 0; i < 500; i++) { 2623 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2624 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2625 break; 2626 usb_delay_ms(&sc->sc_bus, 1); 2627 } 2628 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2629 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2630 /* reset HC here? */ 2631 } 2632 2633 /* reset command ring dequeue pointer */ 2634 cr->xr_ep = 0; 2635 cr->xr_cs = 1; 2636 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2637 2638 mutex_exit(&cr->xr_lock); 2639 } 2640 2641 /* 2642 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2643 * Command completion is notified by cv_signal from xhci_event_cmd() 2644 * (called from xhci_softint), or timed-out. 2645 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2646 * then do_command examines it. 2647 */ 2648 static usbd_status 2649 xhci_do_command_locked(struct xhci_softc * const sc, 2650 struct xhci_trb * const trb, int timeout) 2651 { 2652 struct xhci_ring * const cr = &sc->sc_cr; 2653 usbd_status err; 2654 2655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2656 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2657 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2658 2659 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2660 KASSERT(mutex_owned(&sc->sc_lock)); 2661 2662 while (sc->sc_command_addr != 0) 2663 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2664 2665 /* 2666 * If enqueue pointer points at last of ring, it's Link TRB, 2667 * command TRB will be stored in 0th TRB. 2668 */ 2669 if (cr->xr_ep == cr->xr_ntrb - 1) 2670 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2671 else 2672 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2673 2674 sc->sc_resultpending = true; 2675 2676 mutex_enter(&cr->xr_lock); 2677 xhci_ring_put(sc, cr, NULL, trb, 1); 2678 mutex_exit(&cr->xr_lock); 2679 2680 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2681 2682 while (sc->sc_resultpending) { 2683 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2684 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2685 xhci_abort_command(sc); 2686 err = USBD_TIMEOUT; 2687 goto timedout; 2688 } 2689 } 2690 2691 trb->trb_0 = sc->sc_result_trb.trb_0; 2692 trb->trb_2 = sc->sc_result_trb.trb_2; 2693 trb->trb_3 = sc->sc_result_trb.trb_3; 2694 2695 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2696 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2697 2698 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2699 case XHCI_TRB_ERROR_SUCCESS: 2700 err = USBD_NORMAL_COMPLETION; 2701 break; 2702 default: 2703 case 192 ... 223: 2704 err = USBD_IOERROR; 2705 break; 2706 case 224 ... 255: 2707 err = USBD_NORMAL_COMPLETION; 2708 break; 2709 } 2710 2711 timedout: 2712 sc->sc_resultpending = false; 2713 sc->sc_command_addr = 0; 2714 cv_broadcast(&sc->sc_cmdbusy_cv); 2715 2716 return err; 2717 } 2718 2719 static usbd_status 2720 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2721 int timeout) 2722 { 2723 2724 mutex_enter(&sc->sc_lock); 2725 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2726 mutex_exit(&sc->sc_lock); 2727 2728 return ret; 2729 } 2730 2731 static usbd_status 2732 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2733 { 2734 struct xhci_trb trb; 2735 usbd_status err; 2736 2737 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2738 2739 trb.trb_0 = 0; 2740 trb.trb_2 = 0; 2741 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2742 2743 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2744 if (err != USBD_NORMAL_COMPLETION) { 2745 return err; 2746 } 2747 2748 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2749 2750 return err; 2751 } 2752 2753 /* 2754 * xHCI 4.6.4 2755 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2756 * All endpoints in the slot should be stopped. 2757 * Should be called with sc_lock held. 2758 */ 2759 static usbd_status 2760 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2761 { 2762 struct xhci_trb trb; 2763 struct xhci_slot *xs; 2764 usbd_status err; 2765 2766 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2767 2768 if (sc->sc_dying) 2769 return USBD_IOERROR; 2770 2771 trb.trb_0 = 0; 2772 trb.trb_2 = 0; 2773 trb.trb_3 = htole32( 2774 XHCI_TRB_3_SLOT_SET(slot) | 2775 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2776 2777 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2778 2779 if (!err) { 2780 xs = &sc->sc_slots[slot]; 2781 if (xs->xs_idx != 0) { 2782 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2783 xhci_set_dcba(sc, 0, slot); 2784 memset(xs, 0, sizeof(*xs)); 2785 } 2786 } 2787 2788 return err; 2789 } 2790 2791 /* 2792 * Set address of device and transition slot state from ENABLED to ADDRESSED 2793 * if Block Setaddress Request (BSR) is false. 2794 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2795 * see xHCI 1.1 4.5.3, 3.3.4 2796 * Should be called without sc_lock held. 2797 */ 2798 static usbd_status 2799 xhci_address_device(struct xhci_softc * const sc, 2800 uint64_t icp, uint8_t slot_id, bool bsr) 2801 { 2802 struct xhci_trb trb; 2803 usbd_status err; 2804 2805 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2806 2807 trb.trb_0 = icp; 2808 trb.trb_2 = 0; 2809 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2810 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2811 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2812 2813 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2814 2815 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2816 err = USBD_NO_ADDR; 2817 2818 return err; 2819 } 2820 2821 static usbd_status 2822 xhci_update_ep0_mps(struct xhci_softc * const sc, 2823 struct xhci_slot * const xs, u_int mps) 2824 { 2825 struct xhci_trb trb; 2826 usbd_status err; 2827 uint32_t * cp; 2828 2829 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2830 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2831 2832 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2833 cp[0] = htole32(0); 2834 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2835 2836 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2837 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2838 2839 /* sync input contexts before they are read from memory */ 2840 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2841 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2842 sc->sc_ctxsz * 4); 2843 2844 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2845 trb.trb_2 = 0; 2846 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2847 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2848 2849 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2850 return err; 2851 } 2852 2853 static void 2854 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2855 { 2856 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2857 2858 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2859 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2860 &dcbaa[si], dcba, si, 0); 2861 2862 dcbaa[si] = htole64(dcba); 2863 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2864 BUS_DMASYNC_PREWRITE); 2865 } 2866 2867 /* 2868 * Allocate device and input context DMA buffer, and 2869 * TRB DMA buffer for each endpoint. 2870 */ 2871 static usbd_status 2872 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2873 { 2874 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2875 struct xhci_slot *xs; 2876 usbd_status err; 2877 u_int dci; 2878 2879 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2880 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2881 2882 xs = &sc->sc_slots[slot]; 2883 2884 /* allocate contexts */ 2885 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2886 &xs->xs_dc_dma); 2887 if (err) 2888 return err; 2889 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2890 2891 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2892 &xs->xs_ic_dma); 2893 if (err) 2894 goto bad1; 2895 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2896 2897 for (dci = 0; dci < 32; dci++) { 2898 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2899 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2900 if (dci == XHCI_DCI_SLOT) 2901 continue; 2902 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2903 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2904 if (err) { 2905 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2906 goto bad2; 2907 } 2908 } 2909 2910 bad2: 2911 if (err == USBD_NORMAL_COMPLETION) { 2912 xs->xs_idx = slot; 2913 } else { 2914 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2915 } 2916 2917 return err; 2918 2919 bad1: 2920 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2921 xs->xs_idx = 0; 2922 return err; 2923 } 2924 2925 static void 2926 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2927 int end_dci) 2928 { 2929 u_int dci; 2930 2931 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2932 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2933 0); 2934 2935 for (dci = start_dci; dci < end_dci; dci++) { 2936 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2937 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2938 } 2939 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2940 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2941 xs->xs_idx = 0; 2942 } 2943 2944 /* 2945 * Setup slot context, set Device Context Base Address, and issue 2946 * Set Address Device command. 2947 */ 2948 static usbd_status 2949 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2950 { 2951 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2952 struct xhci_slot *xs; 2953 usbd_status err; 2954 2955 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2956 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2957 2958 xs = &sc->sc_slots[slot]; 2959 2960 xhci_setup_ctx(dev->ud_pipe0); 2961 2962 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2963 sc->sc_ctxsz * 3); 2964 2965 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2966 2967 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2968 2969 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2970 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2971 sc->sc_ctxsz * 2); 2972 2973 return err; 2974 } 2975 2976 /* 2977 * 4.8.2, 6.2.3.2 2978 * construct slot/endpoint context parameters and do syncmem 2979 */ 2980 static void 2981 xhci_setup_ctx(struct usbd_pipe *pipe) 2982 { 2983 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2984 struct usbd_device *dev = pipe->up_dev; 2985 struct xhci_slot * const xs = dev->ud_hcpriv; 2986 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2987 const u_int dci = xhci_ep_get_dci(ed); 2988 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2989 uint32_t *cp; 2990 uint16_t mps = UGETW(ed->wMaxPacketSize); 2991 uint8_t speed = dev->ud_speed; 2992 uint8_t ival = ed->bInterval; 2993 2994 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2995 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2996 speed); 2997 2998 /* set up initial input control context */ 2999 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3000 cp[0] = htole32(0); 3001 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3002 if (dci == XHCI_DCI_EP_CONTROL) 3003 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3004 cp[7] = htole32(0); 3005 3006 /* set up input slot context */ 3007 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3008 cp[0] = 3009 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3010 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3011 cp[1] = 0; 3012 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3013 cp[3] = 0; 3014 xhci_setup_route(pipe, cp); 3015 xhci_setup_tthub(pipe, cp); 3016 3017 cp[0] = htole32(cp[0]); 3018 cp[1] = htole32(cp[1]); 3019 cp[2] = htole32(cp[2]); 3020 cp[3] = htole32(cp[3]); 3021 3022 /* set up input endpoint context */ 3023 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3024 cp[0] = 3025 XHCI_EPCTX_0_EPSTATE_SET(0) | 3026 XHCI_EPCTX_0_MULT_SET(0) | 3027 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3028 XHCI_EPCTX_0_LSA_SET(0) | 3029 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3030 cp[1] = 3031 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3032 XHCI_EPCTX_1_HID_SET(0) | 3033 XHCI_EPCTX_1_MAXB_SET(0); 3034 3035 if (xfertype != UE_ISOCHRONOUS) 3036 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3037 3038 if (xfertype == UE_CONTROL) 3039 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3040 else if (USB_IS_SS(speed)) 3041 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3042 else 3043 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3044 3045 xhci_setup_maxburst(pipe, cp); 3046 3047 switch (xfertype) { 3048 case UE_CONTROL: 3049 break; 3050 case UE_BULK: 3051 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3052 break; 3053 case UE_INTERRUPT: 3054 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3055 ival = pipe->up_interval; 3056 3057 ival = xhci_bival2ival(ival, speed); 3058 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3059 break; 3060 case UE_ISOCHRONOUS: 3061 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3062 ival = pipe->up_interval; 3063 3064 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3065 if (speed == USB_SPEED_FULL) 3066 ival += 3; /* 1ms -> 125us */ 3067 ival--; 3068 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3069 break; 3070 default: 3071 break; 3072 } 3073 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3074 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3075 3076 /* rewind TR dequeue pointer in xHC */ 3077 /* can't use xhci_ep_get_dci() yet? */ 3078 *(uint64_t *)(&cp[2]) = htole64( 3079 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3080 XHCI_EPCTX_2_DCS_SET(1)); 3081 3082 cp[0] = htole32(cp[0]); 3083 cp[1] = htole32(cp[1]); 3084 cp[4] = htole32(cp[4]); 3085 3086 /* rewind TR dequeue pointer in driver */ 3087 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3088 mutex_enter(&xr->xr_lock); 3089 xhci_host_dequeue(xr); 3090 mutex_exit(&xr->xr_lock); 3091 3092 /* sync input contexts before they are read from memory */ 3093 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3094 } 3095 3096 /* 3097 * Setup route string and roothub port of given device for slot context 3098 */ 3099 static void 3100 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3101 { 3102 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3103 struct usbd_device *dev = pipe->up_dev; 3104 struct usbd_port *up = dev->ud_powersrc; 3105 struct usbd_device *hub; 3106 struct usbd_device *adev; 3107 uint8_t rhport = 0; 3108 uint32_t route = 0; 3109 3110 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3111 3112 /* Locate root hub port and Determine route string */ 3113 /* 4.3.3 route string does not include roothub port */ 3114 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3115 uint32_t dep; 3116 3117 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3118 hub, hub->ud_depth, hub->ud_powersrc, 3119 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3120 3121 if (hub->ud_powersrc == NULL) 3122 break; 3123 dep = hub->ud_depth; 3124 if (dep == 0) 3125 break; 3126 rhport = hub->ud_powersrc->up_portno; 3127 if (dep > USB_HUB_MAX_DEPTH) 3128 continue; 3129 3130 route |= 3131 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3132 << ((dep - 1) * 4); 3133 } 3134 route = route >> 4; 3135 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3136 3137 /* Locate port on upstream high speed hub */ 3138 for (adev = dev, hub = up->up_parent; 3139 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3140 adev = hub, hub = hub->ud_myhub) 3141 ; 3142 if (hub) { 3143 int p; 3144 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3145 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3146 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3147 goto found; 3148 } 3149 } 3150 panic("%s: cannot find HS port", __func__); 3151 found: 3152 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3153 } else { 3154 dev->ud_myhsport = NULL; 3155 } 3156 3157 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3158 3159 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3160 ctlrport, route, hub); 3161 3162 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3163 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3164 } 3165 3166 /* 3167 * Setup whether device is hub, whether device uses MTT, and 3168 * TT informations if it uses MTT. 3169 */ 3170 static void 3171 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3172 { 3173 struct usbd_device *dev = pipe->up_dev; 3174 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3175 uint32_t speed = dev->ud_speed; 3176 uint8_t tthubslot, ttportnum; 3177 bool ishub; 3178 bool usemtt; 3179 3180 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3181 3182 /* 3183 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3184 * tthubslot: 3185 * This is the slot ID of parent HS hub 3186 * if LS/FS device is connected && connected through HS hub. 3187 * This is 0 if device is not LS/FS device || 3188 * parent hub is not HS hub || 3189 * attached to root hub. 3190 * ttportnum: 3191 * This is the downstream facing port of parent HS hub 3192 * if LS/FS device is connected. 3193 * This is 0 if device is not LS/FS device || 3194 * parent hub is not HS hub || 3195 * attached to root hub. 3196 */ 3197 if (dev->ud_myhsport != NULL && 3198 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3199 (dev->ud_myhub != NULL && 3200 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3201 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3202 ttportnum = dev->ud_myhsport->up_portno; 3203 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3204 } else { 3205 ttportnum = 0; 3206 tthubslot = 0; 3207 } 3208 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3209 dev->ud_myhsport, ttportnum, tthubslot, 0); 3210 3211 /* ishub is valid after reading UDESC_DEVICE */ 3212 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3213 3214 /* dev->ud_hub is valid after reading UDESC_HUB */ 3215 if (ishub && dev->ud_hub) { 3216 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3217 uint8_t ttt = 3218 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3219 3220 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3221 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3222 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3223 } 3224 3225 #define IS_TTHUB(dd) \ 3226 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3227 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3228 3229 /* 3230 * MTT flag is set if 3231 * 1. this is HS hub && MTT is enabled 3232 * or 3233 * 2. this is not hub && this is LS or FS device && 3234 * MTT of parent HS hub (and its parent, too) is enabled 3235 */ 3236 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3237 usemtt = true; 3238 else if (!ishub && 3239 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3240 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3241 (dev->ud_myhub != NULL && 3242 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3243 dev->ud_myhsport != NULL && 3244 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3245 usemtt = true; 3246 else 3247 usemtt = false; 3248 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3249 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3250 3251 #undef IS_TTHUB 3252 3253 cp[0] |= 3254 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3255 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3256 cp[2] |= 3257 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3258 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3259 } 3260 3261 /* set up params for periodic endpoint */ 3262 static void 3263 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3264 { 3265 struct usbd_device *dev = pipe->up_dev; 3266 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3267 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3268 usbd_desc_iter_t iter; 3269 const usb_cdc_descriptor_t *cdcd; 3270 uint32_t maxb = 0; 3271 uint16_t mps = UGETW(ed->wMaxPacketSize); 3272 uint8_t speed = dev->ud_speed; 3273 uint8_t ep; 3274 3275 /* config desc is NULL when opening ep0 */ 3276 if (dev == NULL || dev->ud_cdesc == NULL) 3277 goto no_cdcd; 3278 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3279 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3280 if (cdcd == NULL) 3281 goto no_cdcd; 3282 usb_desc_iter_init(dev, &iter); 3283 iter.cur = (const void *)cdcd; 3284 3285 /* find endpoint_ss_comp desc for ep of this pipe */ 3286 for (ep = 0;;) { 3287 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3288 if (cdcd == NULL) 3289 break; 3290 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3291 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3292 bEndpointAddress; 3293 if (UE_GET_ADDR(ep) == 3294 UE_GET_ADDR(ed->bEndpointAddress)) { 3295 cdcd = (const usb_cdc_descriptor_t *) 3296 usb_desc_iter_next(&iter); 3297 break; 3298 } 3299 ep = 0; 3300 } 3301 } 3302 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3303 const usb_endpoint_ss_comp_descriptor_t * esscd = 3304 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3305 maxb = esscd->bMaxBurst; 3306 } 3307 3308 no_cdcd: 3309 /* 6.2.3.4, 4.8.2.4 */ 3310 if (USB_IS_SS(speed)) { 3311 /* USB 3.1 9.6.6 */ 3312 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3313 /* USB 3.1 9.6.7 */ 3314 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3315 #ifdef notyet 3316 if (xfertype == UE_ISOCHRONOUS) { 3317 } 3318 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3319 /* use ESIT */ 3320 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3321 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3322 3323 /* XXX if LEC = 1, set ESIT instead */ 3324 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3325 } else { 3326 /* use ival */ 3327 } 3328 #endif 3329 } else { 3330 /* USB 2.0 9.6.6 */ 3331 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3332 3333 /* 6.2.3.4 */ 3334 if (speed == USB_SPEED_HIGH && 3335 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3336 maxb = UE_GET_TRANS(mps); 3337 } else { 3338 /* LS/FS or HS CTRL or HS BULK */ 3339 maxb = 0; 3340 } 3341 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3342 } 3343 } 3344 3345 /* 3346 * Convert endpoint bInterval value to endpoint context interval value 3347 * for Interrupt pipe. 3348 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3349 */ 3350 static uint32_t 3351 xhci_bival2ival(uint32_t ival, uint32_t speed) 3352 { 3353 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3354 int i; 3355 3356 /* 3357 * round ival down to "the nearest base 2 multiple of 3358 * bInterval * 8". 3359 * bInterval is at most 255 as its type is uByte. 3360 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3361 */ 3362 for (i = 10; i > 0; i--) { 3363 if ((ival * 8) >= (1 << i)) 3364 break; 3365 } 3366 ival = i; 3367 } else { 3368 /* Interval = bInterval-1 for SS/HS */ 3369 ival--; 3370 } 3371 3372 return ival; 3373 } 3374 3375 /* ----- */ 3376 3377 static void 3378 xhci_noop(struct usbd_pipe *pipe) 3379 { 3380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3381 } 3382 3383 /* 3384 * Process root hub request. 3385 */ 3386 static int 3387 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3388 void *buf, int buflen) 3389 { 3390 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3391 usb_port_status_t ps; 3392 int l, totlen = 0; 3393 uint16_t len, value, index; 3394 int port, i; 3395 uint32_t v; 3396 3397 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3398 3399 if (sc->sc_dying) 3400 return -1; 3401 3402 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3403 3404 len = UGETW(req->wLength); 3405 value = UGETW(req->wValue); 3406 index = UGETW(req->wIndex); 3407 3408 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3409 req->bmRequestType | (req->bRequest << 8), value, index, len); 3410 3411 #define C(x,y) ((x) | ((y) << 8)) 3412 switch (C(req->bRequest, req->bmRequestType)) { 3413 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3414 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3415 if (len == 0) 3416 break; 3417 switch (value) { 3418 case C(0, UDESC_DEVICE): { 3419 usb_device_descriptor_t devd; 3420 totlen = min(buflen, sizeof(devd)); 3421 memcpy(&devd, buf, totlen); 3422 USETW(devd.idVendor, sc->sc_id_vendor); 3423 memcpy(buf, &devd, totlen); 3424 break; 3425 } 3426 #define sd ((usb_string_descriptor_t *)buf) 3427 case C(1, UDESC_STRING): 3428 /* Vendor */ 3429 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3430 break; 3431 case C(2, UDESC_STRING): 3432 /* Product */ 3433 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3434 break; 3435 #undef sd 3436 default: 3437 /* default from usbroothub */ 3438 return buflen; 3439 } 3440 break; 3441 3442 /* Hub requests */ 3443 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3444 break; 3445 /* Clear Port Feature request */ 3446 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3447 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3448 3449 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3450 index, value, bn, cp); 3451 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3452 return -1; 3453 } 3454 port = XHCI_PORTSC(cp); 3455 v = xhci_op_read_4(sc, port); 3456 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3457 v &= ~XHCI_PS_CLEAR; 3458 switch (value) { 3459 case UHF_PORT_ENABLE: 3460 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3461 break; 3462 case UHF_PORT_SUSPEND: 3463 return -1; 3464 case UHF_PORT_POWER: 3465 break; 3466 case UHF_PORT_TEST: 3467 case UHF_PORT_INDICATOR: 3468 return -1; 3469 case UHF_C_PORT_CONNECTION: 3470 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3471 break; 3472 case UHF_C_PORT_ENABLE: 3473 case UHF_C_PORT_SUSPEND: 3474 case UHF_C_PORT_OVER_CURRENT: 3475 return -1; 3476 case UHF_C_BH_PORT_RESET: 3477 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3478 break; 3479 case UHF_C_PORT_RESET: 3480 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3481 break; 3482 case UHF_C_PORT_LINK_STATE: 3483 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3484 break; 3485 case UHF_C_PORT_CONFIG_ERROR: 3486 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3487 break; 3488 default: 3489 return -1; 3490 } 3491 break; 3492 } 3493 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3494 if (len == 0) 3495 break; 3496 if ((value & 0xff) != 0) { 3497 return -1; 3498 } 3499 usb_hub_descriptor_t hubd; 3500 3501 totlen = min(buflen, sizeof(hubd)); 3502 memcpy(&hubd, buf, totlen); 3503 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3504 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3505 hubd.bPwrOn2PwrGood = 200; 3506 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3507 /* XXX can't find out? */ 3508 hubd.DeviceRemovable[i++] = 0; 3509 } 3510 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3511 totlen = min(totlen, hubd.bDescLength); 3512 memcpy(buf, &hubd, totlen); 3513 break; 3514 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3515 if (len != 4) { 3516 return -1; 3517 } 3518 memset(buf, 0, len); /* ? XXX */ 3519 totlen = len; 3520 break; 3521 /* Get Port Status request */ 3522 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3523 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3524 3525 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3526 0); 3527 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3528 return -1; 3529 } 3530 if (len != 4) { 3531 return -1; 3532 } 3533 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3534 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3535 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3536 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3537 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3538 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3539 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3540 if (v & XHCI_PS_PR) i |= UPS_RESET; 3541 if (v & XHCI_PS_PP) { 3542 if (i & UPS_OTHER_SPEED) 3543 i |= UPS_PORT_POWER_SS; 3544 else 3545 i |= UPS_PORT_POWER; 3546 } 3547 if (i & UPS_OTHER_SPEED) 3548 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3549 if (sc->sc_vendor_port_status) 3550 i = sc->sc_vendor_port_status(sc, v, i); 3551 USETW(ps.wPortStatus, i); 3552 i = 0; 3553 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3554 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3555 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3556 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3557 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3558 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3559 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3560 USETW(ps.wPortChange, i); 3561 totlen = min(len, sizeof(ps)); 3562 memcpy(buf, &ps, totlen); 3563 break; 3564 } 3565 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3566 return -1; 3567 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3568 break; 3569 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3570 break; 3571 /* Set Port Feature request */ 3572 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3573 int optval = (index >> 8) & 0xff; 3574 index &= 0xff; 3575 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3576 return -1; 3577 } 3578 3579 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3580 3581 port = XHCI_PORTSC(cp); 3582 v = xhci_op_read_4(sc, port); 3583 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3584 v &= ~XHCI_PS_CLEAR; 3585 switch (value) { 3586 case UHF_PORT_ENABLE: 3587 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3588 break; 3589 case UHF_PORT_SUSPEND: 3590 /* XXX suspend */ 3591 break; 3592 case UHF_PORT_RESET: 3593 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3594 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3595 /* Wait for reset to complete. */ 3596 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3597 if (sc->sc_dying) { 3598 return -1; 3599 } 3600 v = xhci_op_read_4(sc, port); 3601 if (v & XHCI_PS_PR) { 3602 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3603 usb_delay_ms(&sc->sc_bus, 10); 3604 /* XXX */ 3605 } 3606 break; 3607 case UHF_PORT_POWER: 3608 /* XXX power control */ 3609 break; 3610 /* XXX more */ 3611 case UHF_C_PORT_RESET: 3612 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3613 break; 3614 case UHF_PORT_U1_TIMEOUT: 3615 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3616 return -1; 3617 } 3618 port = XHCI_PORTPMSC(cp); 3619 v = xhci_op_read_4(sc, port); 3620 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3621 v &= ~XHCI_PM3_U1TO_SET(0xff); 3622 v |= XHCI_PM3_U1TO_SET(optval); 3623 xhci_op_write_4(sc, port, v); 3624 break; 3625 case UHF_PORT_U2_TIMEOUT: 3626 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3627 return -1; 3628 } 3629 port = XHCI_PORTPMSC(cp); 3630 v = xhci_op_read_4(sc, port); 3631 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3632 v &= ~XHCI_PM3_U2TO_SET(0xff); 3633 v |= XHCI_PM3_U2TO_SET(optval); 3634 xhci_op_write_4(sc, port, v); 3635 break; 3636 default: 3637 return -1; 3638 } 3639 } 3640 break; 3641 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3642 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3643 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3644 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3645 break; 3646 default: 3647 /* default from usbroothub */ 3648 return buflen; 3649 } 3650 3651 return totlen; 3652 } 3653 3654 /* root hub interrupt */ 3655 3656 static usbd_status 3657 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3658 { 3659 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3660 usbd_status err; 3661 3662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3663 3664 /* Insert last in queue. */ 3665 mutex_enter(&sc->sc_lock); 3666 err = usb_insert_transfer(xfer); 3667 mutex_exit(&sc->sc_lock); 3668 if (err) 3669 return err; 3670 3671 /* Pipe isn't running, start first */ 3672 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3673 } 3674 3675 /* Wait for roothub port status/change */ 3676 static usbd_status 3677 xhci_root_intr_start(struct usbd_xfer *xfer) 3678 { 3679 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3680 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3681 3682 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3683 3684 if (sc->sc_dying) 3685 return USBD_IOERROR; 3686 3687 mutex_enter(&sc->sc_lock); 3688 sc->sc_intrxfer[bn] = xfer; 3689 mutex_exit(&sc->sc_lock); 3690 3691 return USBD_IN_PROGRESS; 3692 } 3693 3694 static void 3695 xhci_root_intr_abort(struct usbd_xfer *xfer) 3696 { 3697 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3698 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3699 3700 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3701 3702 KASSERT(mutex_owned(&sc->sc_lock)); 3703 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3704 3705 sc->sc_intrxfer[bn] = NULL; 3706 3707 xfer->ux_status = USBD_CANCELLED; 3708 usb_transfer_complete(xfer); 3709 } 3710 3711 static void 3712 xhci_root_intr_close(struct usbd_pipe *pipe) 3713 { 3714 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3715 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3716 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3717 3718 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3719 3720 KASSERT(mutex_owned(&sc->sc_lock)); 3721 3722 sc->sc_intrxfer[bn] = NULL; 3723 } 3724 3725 static void 3726 xhci_root_intr_done(struct usbd_xfer *xfer) 3727 { 3728 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3729 3730 } 3731 3732 /* -------------- */ 3733 /* device control */ 3734 3735 static usbd_status 3736 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3737 { 3738 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3739 usbd_status err; 3740 3741 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3742 3743 /* Insert last in queue. */ 3744 mutex_enter(&sc->sc_lock); 3745 err = usb_insert_transfer(xfer); 3746 mutex_exit(&sc->sc_lock); 3747 if (err) 3748 return err; 3749 3750 /* Pipe isn't running, start first */ 3751 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3752 } 3753 3754 static usbd_status 3755 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3756 { 3757 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3758 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3759 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3760 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3761 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3762 usb_device_request_t * const req = &xfer->ux_request; 3763 const int isread = usbd_xfer_isread(xfer); 3764 const uint32_t len = UGETW(req->wLength); 3765 usb_dma_t * const dma = &xfer->ux_dmabuf; 3766 uint64_t parameter; 3767 uint32_t status; 3768 uint32_t control; 3769 u_int i; 3770 3771 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3772 DPRINTFN(12, "req: %04x %04x %04x %04x", 3773 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3774 UGETW(req->wIndex), UGETW(req->wLength)); 3775 3776 /* we rely on the bottom bits for extra info */ 3777 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3778 (uintptr_t) xfer); 3779 3780 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3781 3782 i = 0; 3783 3784 /* setup phase */ 3785 memcpy(¶meter, req, sizeof(parameter)); 3786 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3787 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3788 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3789 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3790 XHCI_TRB_3_IDT_BIT; 3791 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3792 3793 if (len != 0) { 3794 /* data phase */ 3795 parameter = DMAADDR(dma, 0); 3796 KASSERTMSG(len <= 0x10000, "len %d", len); 3797 status = XHCI_TRB_2_IRQ_SET(0) | 3798 XHCI_TRB_2_TDSZ_SET(0) | 3799 XHCI_TRB_2_BYTES_SET(len); 3800 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3801 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3802 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3803 XHCI_TRB_3_IOC_BIT; 3804 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3805 } 3806 3807 parameter = 0; 3808 status = XHCI_TRB_2_IRQ_SET(0); 3809 /* the status stage has inverted direction */ 3810 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3811 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3812 XHCI_TRB_3_IOC_BIT; 3813 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3814 xfer->ux_status = USBD_IN_PROGRESS; 3815 3816 mutex_enter(&tr->xr_lock); 3817 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3818 mutex_exit(&tr->xr_lock); 3819 3820 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3821 3822 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3823 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3824 xhci_timeout, xfer); 3825 } 3826 3827 return USBD_IN_PROGRESS; 3828 } 3829 3830 static void 3831 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3832 { 3833 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3834 usb_device_request_t *req = &xfer->ux_request; 3835 int len = UGETW(req->wLength); 3836 int rd = req->bmRequestType & UT_READ; 3837 3838 if (len) 3839 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3840 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3841 } 3842 3843 static void 3844 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3845 { 3846 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3847 3848 xhci_abort_xfer(xfer, USBD_CANCELLED); 3849 } 3850 3851 static void 3852 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3853 { 3854 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3855 3856 xhci_close_pipe(pipe); 3857 } 3858 3859 /* ------------------ */ 3860 /* device isochronous */ 3861 3862 /* ----------- */ 3863 /* device bulk */ 3864 3865 static usbd_status 3866 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3867 { 3868 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3869 usbd_status err; 3870 3871 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3872 3873 /* Insert last in queue. */ 3874 mutex_enter(&sc->sc_lock); 3875 err = usb_insert_transfer(xfer); 3876 mutex_exit(&sc->sc_lock); 3877 if (err) 3878 return err; 3879 3880 /* 3881 * Pipe isn't running (otherwise err would be USBD_INPROG), 3882 * so start it first. 3883 */ 3884 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3885 } 3886 3887 static usbd_status 3888 xhci_device_bulk_start(struct usbd_xfer *xfer) 3889 { 3890 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3891 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3892 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3893 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3894 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3895 const uint32_t len = xfer->ux_length; 3896 usb_dma_t * const dma = &xfer->ux_dmabuf; 3897 uint64_t parameter; 3898 uint32_t status; 3899 uint32_t control; 3900 u_int i = 0; 3901 3902 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3903 3904 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3905 3906 if (sc->sc_dying) 3907 return USBD_IOERROR; 3908 3909 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3910 3911 parameter = DMAADDR(dma, 0); 3912 /* 3913 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3914 * If the user supplied buffer crosses such a boundary then 2 3915 * (or more) TRB should be used. 3916 * If multiple TRB are used the td_size field must be set correctly. 3917 * For v1.0 devices (like ivy bridge) this is the number of usb data 3918 * blocks needed to complete the transfer. 3919 * Setting it to 1 in the last TRB causes an extra zero-length 3920 * data block be sent. 3921 * The earlier documentation differs, I don't know how it behaves. 3922 */ 3923 KASSERTMSG(len <= 0x10000, "len %d", len); 3924 status = XHCI_TRB_2_IRQ_SET(0) | 3925 XHCI_TRB_2_TDSZ_SET(0) | 3926 XHCI_TRB_2_BYTES_SET(len); 3927 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3928 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3929 XHCI_TRB_3_IOC_BIT; 3930 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3931 xfer->ux_status = USBD_IN_PROGRESS; 3932 3933 mutex_enter(&tr->xr_lock); 3934 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3935 mutex_exit(&tr->xr_lock); 3936 3937 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3938 3939 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3940 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3941 xhci_timeout, xfer); 3942 } 3943 3944 return USBD_IN_PROGRESS; 3945 } 3946 3947 static void 3948 xhci_device_bulk_done(struct usbd_xfer *xfer) 3949 { 3950 #ifdef USB_DEBUG 3951 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3952 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3953 #endif 3954 const int isread = usbd_xfer_isread(xfer); 3955 3956 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3957 3958 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3959 3960 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3961 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3962 } 3963 3964 static void 3965 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3966 { 3967 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3968 3969 xhci_abort_xfer(xfer, USBD_CANCELLED); 3970 } 3971 3972 static void 3973 xhci_device_bulk_close(struct usbd_pipe *pipe) 3974 { 3975 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3976 3977 xhci_close_pipe(pipe); 3978 } 3979 3980 /* ---------------- */ 3981 /* device interrupt */ 3982 3983 static usbd_status 3984 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3985 { 3986 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3987 usbd_status err; 3988 3989 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3990 3991 /* Insert last in queue. */ 3992 mutex_enter(&sc->sc_lock); 3993 err = usb_insert_transfer(xfer); 3994 mutex_exit(&sc->sc_lock); 3995 if (err) 3996 return err; 3997 3998 /* 3999 * Pipe isn't running (otherwise err would be USBD_INPROG), 4000 * so start it first. 4001 */ 4002 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4003 } 4004 4005 static usbd_status 4006 xhci_device_intr_start(struct usbd_xfer *xfer) 4007 { 4008 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4009 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4010 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4011 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4012 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4013 const uint32_t len = xfer->ux_length; 4014 usb_dma_t * const dma = &xfer->ux_dmabuf; 4015 uint64_t parameter; 4016 uint32_t status; 4017 uint32_t control; 4018 u_int i = 0; 4019 4020 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4021 4022 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4023 4024 if (sc->sc_dying) 4025 return USBD_IOERROR; 4026 4027 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4028 4029 parameter = DMAADDR(dma, 0); 4030 KASSERTMSG(len <= 0x10000, "len %d", len); 4031 status = XHCI_TRB_2_IRQ_SET(0) | 4032 XHCI_TRB_2_TDSZ_SET(0) | 4033 XHCI_TRB_2_BYTES_SET(len); 4034 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4035 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4036 XHCI_TRB_3_IOC_BIT; 4037 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4038 xfer->ux_status = USBD_IN_PROGRESS; 4039 4040 mutex_enter(&tr->xr_lock); 4041 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4042 mutex_exit(&tr->xr_lock); 4043 4044 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4045 4046 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4047 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4048 xhci_timeout, xfer); 4049 } 4050 4051 return USBD_IN_PROGRESS; 4052 } 4053 4054 static void 4055 xhci_device_intr_done(struct usbd_xfer *xfer) 4056 { 4057 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4058 #ifdef USB_DEBUG 4059 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4060 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4061 #endif 4062 const int isread = usbd_xfer_isread(xfer); 4063 4064 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4065 4066 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4067 4068 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4069 4070 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4071 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4072 } 4073 4074 static void 4075 xhci_device_intr_abort(struct usbd_xfer *xfer) 4076 { 4077 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4078 4079 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4080 4081 KASSERT(mutex_owned(&sc->sc_lock)); 4082 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4083 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4084 xhci_abort_xfer(xfer, USBD_CANCELLED); 4085 } 4086 4087 static void 4088 xhci_device_intr_close(struct usbd_pipe *pipe) 4089 { 4090 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4091 4092 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4093 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4094 4095 xhci_close_pipe(pipe); 4096 } 4097 4098 /* ------------ */ 4099 4100 static void 4101 xhci_timeout(void *addr) 4102 { 4103 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4104 struct xhci_xfer * const xx = addr; 4105 struct usbd_xfer * const xfer = &xx->xx_xfer; 4106 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4107 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4108 4109 mutex_enter(&sc->sc_lock); 4110 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 4111 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 4112 mutex_exit(&sc->sc_lock); 4113 } 4114 4115 static void 4116 xhci_timeout_task(void *addr) 4117 { 4118 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4119 struct usbd_xfer * const xfer = addr; 4120 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4121 4122 mutex_enter(&sc->sc_lock); 4123 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4124 mutex_exit(&sc->sc_lock); 4125 } 4126
Indexes created Wed Oct 01 18:09:54 GMT 2025